Large-scale Data Processing System

Abstract

The specification discloses an illustrative embodiment for the invention comprising a large-scale data processing system of the type which is composed of a plurality of quasi-independent units. The environmental data processing system includes a central processing unit or portion, which is herein referred to as a CPU, a plurality of storage units, a plurality of input/output control devices referred to herein as channels, as well as control and maintenance facilities which are found in a power distribution unit, herein referred to as a PDU. The CPU of the environmental system includes a control or instruction unit hereinafter referred to as an I-unit, and an arithmetic and logic or execution unit, hereinafter referred to as an E-unit. The I-unit includes controls for instruction fetching, branching, interruption handling, communication with the input/output channels, and other related functions. The E-unit of the environmental system can perform algebraic and logical operations, moving, shifting, and other functions. ##SPC1##

Parent Case Text

This application is a continuation-in-part of application Ser. No. 445,326, filed Apr. 5, 1965, entitled "Large Scale Data Processing System," now abandoned.

Description

1.0 BACKGROUND OF THE INVENTION

The invention herein relates to improved large scale electronic data processing systems.

In the prior art, high-performance, large scale data processing systems have been characterized by use of a plurality of smaller systems, having duplicate functions (such as instruction fetching) in each of said systems, or have been characterized in having heavily overlapped operation with multiple look-ahead and prefetch characteristics, or in other complex arrangements.

In the first type of system, a great deal of hardware is wasted due to the fact that the particular function involved could be performed for the entire configuration with a fraction of the hardware utilized. Also, propagation of signals between various systems of which the configuration is comprised is time consuming, and a great deal of complexity is necessary in order to correlate the operation of the various systems on a unitary problem. In the second type of system, service registers, counters, and status latches must all be duplicated in order to provide a sufficient number of them to keep track of the data and status current in the machine at each level of overlap therein. Additionally, a change in the sequential operation of the machine requires that all of the look-ahead levels be again brought up to current status of the machine, after the direction of machine operation has changed. Additionally, a great deal of unnecessary operating is involved in establishing look-ahead levels which are never used. Each of these types of machines are very costly in terms of performance, and are justified only when the absolute and ultimate performance is essential without regard to cost.

High-performance data processing systems of the prior art are further characterized in the instruction set and general architecture therein. The instruction set is typically one having long instructions, including a large number of address bits for operands, so that a large amount of storage is readily available to the system. Additionally, the interruption handling philosophy, and other basic system control organizations are specialized to accommodate the high-performance requirements and complex hardware involved. Other types of systems have also been known in this range of performance; one such system has addresses of a first kind for instructions only, and addresses of a second kind for operands only; obviously, this would impose a tremendous burden on a system of a smaller scale, and therefore render that type of large system difficult to make compatible with small systems.

A primary general object of the invention herein is to provide an improved and simplified high-performance large scale data processing system.

Another object of the invention herein is to provide a large scale data processing system of the type which is compatible with small data processing systems and intermediate data processing systems.

Other general objects of the present invention include the provision of:

Simplified high performance design in a large scale data processing system;

Improved circuit arrangements for a data processing system;

Simplified sequencing control in a large scale data processing system;

Improved data flow circuits in a large scale data processing system;

Simple high-performance control for a data processing system;

Improved storage relationships in a large scale data processing system;

Simplified circuitry which permits maximum performance without unduly lengthening logical circuit paths, whereby time of operation of a large scale system is not sacrificed in order to achieve the number of functions required thereby;

A fully checked large scale high-performance data processing system;

A large scale data processing system with overlapped execution utilizing a minimum of look-ahead hardware;

An overlapped large scale data processing system, with maximum use of common hardware between the instruction and the execution portions thereof;

A high performance large scale data processing system having a maximum sophistication-to-hardware ratio.

In the achievement of the foregoing objects, other more specific objectives of the invention relating to the present improvement are to be fulfilled. In accordance with one particular object of the present invention, the parity of a register which contains marks, said marks pointing to particular bytes to be stored within a storage device is automatically maintained current. Another detailed object of the invention is satisfied by the provision of a self-resetting, buffered channel priority circuit. An additional object is achieved by means of return-address hardware, whereby the various storage requests are continuously identified by the source thereof. In accordance with a further specific object of the invention herein, absolute priority to a requesting unit may be granted with respect to storage operations, in the event that the requesting unit requires it; this may be achieved in response to data conditions, or in response to control status in the requesting unit.

A further detailed object of the present invention is fulfilled by the provision of an improved clocking arrangement wherein a first clocking signal is utilized to set bistable devices of a first kind, and a second clocking signal, which straddles said first clocking signal, is utilized to control the latching and releasing of a two-state device to which said bistable device may be connected. In accordance with a further specific object, the clock control over said two-state devices is further modified to include status conditioning thereof.

A further object of the present invention includes provision of a plurality of operand decoders for various levels of operation in an overlapped system; in accordance therewith, several levels of operand decoding are provided, and these levels are overlapped, one with another, in such a fashion that the actual decoding of operands is achieved prior to the cycle within which the decoded outputs are utilized.

Further objects include the provision of branching, branch controls over instruction fetching, and the determination between branch and no branch sequencing; these are achieved by a branch philosophy which permits fetching first and second instructions in response to a branching instruction, utilizing only those instructions required in the event of a first successful branch which is not followed by a second branch; additionally, improvements in the philosophy of instruction fetching are provided so as to permit a more flexible and sophisticated utilization of storage means for operand and instruction handling. An additional detailed object of the present invention is fulfilled by means of improved parity control in instruction selection and in instruction addressing hardware.

In accordance with another object, a comparison between a register to be used and a register to be filled permits the utilization apparatus to remain responsive to the register until such time as a final setting of the register can occur.

A further object of the invention is to determine when an instruction may be retried without faulty operation of the system with respect thereto, which is achieved by sensing when the contents of addressable registers or storage locations have been changed by an instruction in the course of the execution thereof.

In accordance with still another object, improved control panel hardware permits long life of indicator lamps, together with the testing thereof, without interference with the logic circuits attached thereto; another object relates to providing a minimum of hardware in the handling of switch controls, which is fulfilled by means of a circuit which utilizes a single set of hardware to perform the shaping of signals resulting from pushbutton operations on a control panel.

In accordance with a further specific object of the present invention, an interruption-fixed sequence is established in such a fashion as to provide for the selective performance of various functions which relate to interruptions, said functions being therefore achieved with a minimum of logic circuitry. A related specific object is fulfilled by the provision of modifications to said sequence to handle timer advancing, machine check interruptions, interruptions resulting from signals external to the system, interruptions resulting from the input/output channels of the system, and interruptions which can be initiated in response to operator control. Still another related specific object is the handling of special circumstances which can arise while the system is operating in a problem-solving mode, such operations including an execution instruction which requires the performance of a single-step branch with a return to the main sequence of instructions, and including impending accessing of a storage location, into which further data is to be stored; this object is fulfilled by means of the utilization of certain portions of said interruption fixed sequence to recognize these conditions and to assist in the handling thereof.

A still further specific object of the present invention includes the provision of improved maintenance procedures. An example of such improvement is the provision of a forced repeat mode of operation which includes the ability to specify a particular instruction with which sequencing in this mode is to begin, and causing the system to operate to a point where an address set in control panel switches matches an address specified in a storage request. A related detailed object is the ability to provide single cycle operation in the system wherein a storage unit runs essentially asynchronously with respect to the CPU in terms of the major functions performed thereby; this is achieved by means of a circuit which regulates store operations when in the single-cycle mode.

Further specific objects relate to decimal, or variable field length operations, which may include arithmetic or logical operations. One such objective is met by the decimal adder which includes a decimal input converter, a binary adder, and a decimal output converter, the decimal adder being characterized by the provision of decimal conversion which does not assume that only values from 0 to 9 may be passed through the adder; this permits invalid data to be maintained as such, without causing parity or other machine failure alarms to be generated, unless an actual failure is the cause of the erroneous data. A related objective is provided by a simplified logical circuitry for generating logical functions of a pair of operands. Another specific objective is achieved in improved move instruction processing whereby a move instruction may be specified in general terms, and the move instruction will be carried out one small data group at a time or one large storage word at a time in dependence upon the starting condition of the move; in accordance with this objective, a move instruction may be finished in the character or byte mode even though it is started in the transmit or storage word mode.

Further specific objects of the present invention include provision of improvements in binary arithmetic and logical operations, the improvements relating to the implementation of arithmetic and related functions in a large scale data processing system. In accordance with these objectives, the present improvement includes an exponent adder which has the capability of utilizing excess 64 notation without the need for successive passes or correction cycles for each iteration; this is achieved, in part, by an exponent adder which performs multiple functions, included in which is the ability to select true or complement outputs thereof, and to provide "split gating" which is controlled thereby. In further accord with the foregoing objectives, the ability to test the parity error-sensing circuitry of a register which is isolated from the storage input circuits is provided by a circuit which permits forcing carries in the adder parity circuitry, but not in the arithmetic circuitry, so as to force the generation of false parity bits; together with this is the additional capability of selectively providing faulty data to the register so that the incorrect parity bit will seem correct; this permits selectively causing particular incorrect parity bits for diagnostic purposes. Still another related particular object is the provision of an improved parity checker which includes the ability, with an eight-bit parity-checked byte, to generate the total parity of half of the byte together with the parity bit, on a first cycle, and to generate the parity of the second half of the byte and compare it with the parity of the first half of the byte in a second cycle; this permits fully checking a parity byte even though it is shifted into a particular position only four bits at a time; this also reduces the amount of hardware required to perform successive parity checking on iterative handling of a parity-checked byte. A function related to the foregoing objectives includes the ability to multiply numbers in complement form, improvements herein residing in the ability of the multiplier to determine the correct operation even for the last byte, which is achieved not only be shifting the sign value of all high-order positions (to the left) as the values are shifted to the right (to the low-order positions) on successive iterations, but also through the ability to provide the sign bit in one position to the left of the highest order position which has to be examined. Still another objective is satisfied by means which include further improvements in fixed point multiplication and floating point multiplication by utilization of hexidecimal groups.

Other objects, features and advantages of the invention herein will become more apparent in the light of the following detailed description of a particular embodiment thereof, as shown in the accompanying drawings. The drawings are illustrative block diagrams, schematic block diagrams, timing diagrams, charts and illustrations of an embodiment of the present improvement, as set forth in a Large Scale Data Processing System which is referred to as "said environmental system," as set forth in the following list:

DESCRIPTION OF FIGURES

FIG. 1 SYSTEM ILLUSTRATION;

FIG. 2 ENVIRONMENTAL SYSTEM;

FIG. 3a-5b COMPONENT CIRCUITS;

FIG. 6a-8b COMPONENT CIRCUITS;

FIG. 9 SELECTION CIRCUITS;

FIG. 10 STORAGE INPUT CIRCUITS;

FIG. 11 STORAGE OUTPUT CIRCUITS;

FIG. 12 CH PRI;

FIG. 13-15 BFR, DELAY, BCU DATA REQ;

FIG. 16-18 BCU RESPONSE, CHAN REQUEST, GATE CH/CPU;

FIG. 19 BASIC CH REQ CYC;

FIG. 20 BASIC CPU CYC;

FIG. 21 CPU REQ;

FIG. 22 CPU E/O;

FIG. 23 SAR;

FIG. 24 CPU REQ CT;

FIG. 25 BUSY & CYC INH TIMING;

FIG. 26 CH-CPU INTERPLAY;

FIG. 27 SEL A/B-E/O CH-CPU;

FIG. 28 BUSY-POS SEL-INH;

FIG. 29 ACCEPT;

FIG. 30 CPU COM-BUSY;

FIG. 31 ADR OR;

FIG. 32 ADDRESSING;

FIG. 33 SAB ADR CHK;

FIG. 34 INV ADR;

FIG. 35 CANCEL-PKF;

FIG. 36 PAR ADJ;

FIG. 37 ADR COMP;

FIG. 38 STORE;

FIG. 39 SBIL;

FIG. 40 MARKS;

FIG. 41 MARK TIMING;

FIG. 42a-d IN KEYS;

FIG. 43 SIMPLIFIED RTN ADR TIMING;

FIG. 44 S/Y-W/Z;

FIG. 45 X REG;

FIG. 46 Y REG;

FIG. 47 ADVANCE;

FIG. 48 SAP;

FIG. 49 STR DATA CHK;

FIG. 50-52 STR ADR CHK, X/Y-W/Z CHK, BCU STOP CLK;

FIG. 53 OUT KEYS;

FIG. 54 SBOL;

FIG. 55 CH/BCU CONNECTIONS;

FIG. 56 OSC;

FIG. 57 CLOCK SYNCS;

FIG. 58 CLK TGRS;

FIG. 59 CLOCK;

FIG. 60 CHECK STOP TIMING;

FIG. 61 SINGLE CYCLE TIMING;

FIG. 62 CLOCK CONTROL TIMING;

FIG. 63 CHECK;

FIG. 64 CRC/SRC;

FIG. 65 PRIOR ART POWERING;

FIG. 66 CONSTANT POWERING;

FIG. 67 IDEAL CLOCK;

FIG. 68 I UNIT SCAN;

FIG. 69 E UNIT SCAN;

FIG. 70 SCAN GT EXAMPLE;

FIG. 71 SCAN IN EXAMPLE;

FIG. 72 E UNIT DATA FLOW (1);

FIG. 73 E UNIT DATA FLOW (2);

FIG. 74 I UNIT;

FIG. 75 GR + ADR;

FIG. 76 INST DEC DATA FLOW;

FIG. 77 SEL A/B;

FIG. 78 A/B INV KEY;

FIG. 79 A B REGISTER & GATING;

FIG. 80 A B GATE SELECT;

FIG. 81 PD-BRANCH DECODE;

FIG. 82 PD-IOP LOADED;

FIG. 83 IOP REG;

FIG. 84 D FLD GATE;

FIG. 85 IOP ERROR;

FIG. 86 IOP FORMAT DECODE;

FIG. 87 IOP INST DECODE;

FIG. 88 ID 3;

FIG. 89 ID 4;

FIG. 90 ID INV OP-1;

FIG. 91 ID INV OP-2;

FIG. 92 RR BRANCHING status switching;

FIG. 93 RR FLOATING--POINT DOUBLE PRECISION;

FIG. 94 RX FIXED--POINT HALF WORD & BRANCHING;

FIG. 95 RX FLOATING--POINT DOUBLE PRECISION;

FIG. 96 RS-SI BRANCHING, STATUS SWITCHING & SHIFTING;

FIG. 97 SS LOGICAL, SS DECIMAL;

FIG. 98-101 IOP LINE DECODE;

FIG. 102 BOP REG 0-7;

FIG. 103 BOP REG 8-11;

FIG. 104 ER 1 REG;

FIG. 105 BR 1 INCR;

FIG. 106 BOP PAR ERROR;

FIG. 107 ER 1 INCR;

FIG. 108 B SEL GR, FIG. 108a;

FIG. 109 R2-X SEL GR;

FIG. 110 BR1 SEL GR;

FIG. 111 GEN REG OUT GATING CTRL;

FIG. 112 GEN REG OUT GATE SEL;

FIG. 113 GEN REG OUT GATES;

FIG. 114 GBL & GBR;

FIG. 115 GBR;

FIG. 116 ER 1 GR IN SEL;

FIG. 117 GEN REG IN GATES;

FIG. 118 GEN REGS;

FIG. 119 OP ZERO TEST & BR 1 COMP;

FIG. 120 COMP BLK;

FIG. 121 ER 1 = I R2 - X;

FIG. 122 INPUTS FROM BOP (FIG. 102) OUTPUTS TO DECODERS;

FIG. 123 SPECIFICATION INTERRUPT DETECTION;

FIG. 124 BC BLK T1-T2;

FIG. 125 BOP DECODE 1;

FIG. 126 BOP DECODE 2;

FIG. 127 BD COMP REQ;

FIG. 128 BOP DECODE 3;

FIG. 129 BD MARKS & KEYS;

FIG. 130 CPU SET MARKS;

FIG. 131 GATING PSW 0-39;

FIG. 132 PSW 0-7;

FIG. 133 PSW 8-15;

FIG. 134 PSW 16-31;

FIG. 135 PSW 32-35;

FIG. 136 SET 34,35;

FIG. 137 PSW 36-39;

FIG. 138 GATING OF ICR (PSW 40-63);

FIG. 139 PSW 40-63;

FIG. 140 INCREMENTER;

FIG. 141 INCR IN GATING CTRLS;

FIG. 142 INCR EXT;

FIG. 143 INCR ADD ONE/TWO;

FIG. 144 INCR IN;

FIG. 145 INCR C IN;

FIG. 146 INCR-1;

FIG. 147 INCR-2;

FIG. 148 PARTIAL INVRT P;

FIG. 149 INCRT P;

FIG. 150 INCR P-1;

FIG. 151 INCR P-2;

FIG. 152 INCR P CHK;

FIG. 153 INCR CHK;

FIG. 154 INCR OUT GATING CTRLS;

FIG. 155 CPU RTN J;

FIG. 156 GS PRE LCH;

FIG. 157 ADV HLF WDS;

FIG. 158 GS ADDER;

FIG. 159-161 GS GATE;

FIG. 161a GS DECODE;

FIG. 162 GS PARITY;

FIG. 163 PRIOR ART ADDER;

FIG. 164 ADDRESS ADDER;

FIG. 165 ADDER INPUT;

FIG. 166-168 CSS/CSC;

FIG. 169 BIT FUNCTIONS G-T;

FIG. 170 T-G GROUP;

FIG. 171 C IN GROUP;

FIG. 172 C IN BIT;

FIG. 173-174 FINAL SUM;

FIG. 175 HALF SUMS;

FIG. 176 ADDRESS ADDER INPUT PARITY;

FIG. 177 ODD CARRY GENERATOR;

FIG. 178 CARRY SAVE PARITY;

FIG. 179 PARITY INVERT;

FIG. 180 AA PARITY;

FIG. 181 HALF SUMM ERROR;

FIG. 182 C OUT OF GROUP;

FIG. 183 CARRY ERROR AND AA STOP CLK;

FIG. 184 H REG CTRLS;

FIG. 185 AA OUT-GATING CTRLS;

FIG. 186 PGM STR COMP;

FIG. 187-190 IC HO ADV, SS OP, VFL ADR, GT FPR;

FIG. 191 J LOADED;

FIG. 192 BR SUCC;

FIG. 193 FR2;

FIG. 194 AB FTCH LCH;

FIG. 195 IOP INV ADR;

FIG. 196 BR OK;

FIG. 197 BLK T2M;

FIG. 198 TON T1;

FIG. 199-203 SET IOP;

FIG. 204 T1 LCH;

FIG. 205 TON T2;

FIG. 206 T2 LCH;

FIG. 207 FTCH PRIORITY;

FIG. 208 BLK ICM;

FIG. 209 LAST CYC;

FIG. 210 I/E GO;

FIG. 211 PSC;

FIG. 212 E/IE BUSY;

FIG. 213 STR REQ;

FIG. 214-217 I STR, OPF, CPU RET AB, I FTCH;

FIG. 218 IC FE CTRL;

FIG. 219 IC FE LCHS;

FIG. 220 IC RTN AB;

FIG. 221 IC FM LCHS;

FIG. 222 TON IC RCVY;

FIG. 223 IC RCVY LCH;

FIG. 224 IOP LOADED;

FIG. 225 ID AB REG EMPTY;

FIG. 226 FTCH FUNCTIONS;

FIG. 227 A/B LOADED;

FIG. 228 IC FM OR LD;

FIG. 229 ADD ONE/TWO;

FIG. 230 GT GSR;

FIG. 231-234 EN IC FTCH;

FIG. 235 TSTS CMPLT & BR OP;

FIG. 236-239 BR + 1 M;

FIG. 240 BR + 1 E;

FIG. 241 BR + 1 FTCH;

FIG. 242 BR SUCC M;

FIG. 243 TON RCVY;

FIG. 244 BR LC;

FIG. 245 XEQ OP / SEQ;

FIG. 246 BR CANC FTCH;

FIG. 247 SEL A/B CTRL;

FIG. 248 I TIME & E TIME FOR AN RX-FXP ADD;

FIG. 249 BLOCKING OF T1;

FIG. 250 INSTRUCTION WORD FORMATS;

FIG. 251 SETTING OF THE OP CODE REGS;

FIG. 252 BLOCKING OF T2;

FIG. 253 RR FLOATING POINT OPERAND GATING;

FIG. 254 OPERAND FETCH TIMING;

FIG. 255 I UNIT STORE REQUEST;

FIG. 256 I UNIT STORE REQUEST SINGLE CYCLE;

FIG. 257 GROUT TIMING;

FIG. 258 I UNIT TIME-1;

FIG. 259 I UNIT TIME-2;

FIG. 260 INST SEQ FOR EXECUTIONS & BRANCH;

FIG. 261 INST SEQ FOR EXECUTIONS & BRANCH;

FIG. 262 INST SEQ FOR START I/O & INTRPT;

FIG. 263 INST SEQ FOR START I/O & INTRPT;

FIG. 264 DIRECTORY OF I UNIT SEQUENCE CHARTS BY OP CODE;

FIG. 264-1 RR-FLP;

FIG. 264-2 RR-FLP;

FIG. 264-3 RR-FLP:DDR,DER;

FIG. 264-4 RX-FLP;

FIG. 264-5 RX-FLP:STD,STE;

FIG. 264-6 RX-FLP:MD,ME;

FIG. 264-7 RX-FLD:DD,DE;

FIG. 264-8 RR-FXP;

FIG. 264-9 RR-FXP:MR;

FIG. 264-10 RR-FXP:DR;

FIG. 264-11 RX-FXP;

FIG. 264-12 RX-FXP:LH,CH,RH,SH;

FIG. 264-13 RX-FXP:STH (IF H 22=1), ST;

FIG. 264-14 RX-FXP:STH(H22=0), STC, CVD;

FIG. 264-15 RX-FXP:LA;

FIG. 264-16 RX-FXP:M, MH;

FIG. 264-17 RX-FXP:D;

FIG. 264-18 SI:TM, CLI;

FIG. 264-19 SI:MVI;

FIG. 264-20 SI:NI, OI, XI;

FIG. 264-21 RS;

FIG. 264-22 SS (STARTING);

FIG. 264-23 SS (ENDING);

FIG. 264-24 RR:SPM;

FIG. 264-25 RR:SSK;

FIG. 264.apprxeq.RR:SSK;

FIG. 264-27 RR:SVC;

FIG. 264-28 RS:SSM;

FIG. 264-29 RS:LPSW;

FIG. 264-30 RS:DIAG;

FIG. 264-31 RS:WD;

FIG. 264-32 RS:RD;

FIG. 264-33 RS:STM;

FIG. 264-34 RS:LM;

FIG. 264-35 RS:SIO, TIO, HIO, TCH;

FIG. 264-36 RR:BALR;

FIG. 264-37 RR:BALR (R2 0) RX:BAL;

FIG. 264-38 RR:BCTR;

264-39 RR:BCTR (R2 0) RX:BCT;

FIG. 264-40 RR:BCR (R2=0);

FIG. 264-41 RR:BCR (R2 0) RX:BC;

FIG. 264-42 RS:B X H, BXLE;

FIG. 264-43 RX:XEQ;

FIG. 264-44 I IRPT FM I;

FIG. 265 INSTRNS IN SEQ;

FIG. 266 SS IC ADV (ASSUMING ADR X01010 HAS MVO);

FIG. 267 EXAMPLE OF TIMING OF REPEAT INSTRUCTION;

FIG. 268 EXAMPLE TIMING OF IC FETCH;

FIG. 269 IC SEQ TIME;

FIG. 270 EXAMPLE OF IC FETCH SINGLE-CYCLED;

FIG. 271 BLOCKING OF IC FETCHING;

FIG. 272 EXAMPLE OF TIMING FOR AN IC RCVY;

FIG. 273 BRANCH SEQUENCE (BR IS TO B REG);

FIG. 274 BRANCH SEQUENCING BR TO A REG;

FIG. 275 BRANCH SEQUENCING BR TO A REG;

FIG. 276 BRANCH SEQUENCING BR IS TO A REG;

FIG. 277 I E DECODE;

FIG. 278 TON T1M, T2M;

FIG. 279 TON IE 1;

FIG. 280 IM1;

FIG. 281 IM2;

FIG. 282 IE1;

FIG. 283 TON IE2, IE3;

FIG. 284 IE2;

FIG. 285 IE3;

FIG. 286 IE DEC-2;

FIG. 287 TON IEL;

FIG. 288 IEL;

FIG. 289 IPL LCH;

FIG. 290 IPL CTRL;

FIG. 291 REL BUF;

FIG. 292 REL TGR;

FIG. 293 IE CTRL-1;

FIG. 294 IE CTRL-2;

FIG. 295 IE-CTRL-3;

FIG. 296 IPL;

FIG. 297 CHAN INSTR START, TEST, HALT, TEST CHAN;

FIG. 298 LOAD PSW;

FIG. 299 SET SYS MSK;

FIG. 300 SET PGM MSK;

FIG. 301 DIAGNOSE;

FIG. 302 SET STORAGE KEY;

FIG. 303 INSERT STORAGE KEY;

FIG. 304 BRANCH NO-OP;

FIG. 305 MULT STR 1XX ODD NO;

FIG. 306 MULT STR OXX EVEN NO;

FIG. 307 MULT LOAD;

FIG. 308a CH IRPT SEL;

FIG. 308b CH INST SEL;

FIG. 309 CH PRI CTRL;

FIG. 310 CH DEC;

FIG. 311 CH IRPT PRI;

FIG. 312 CH IRPT RSPS;

FIG. 313 CH IRPT OUT;

FIG. 314 SEL CH;

FIG. 315 CH IRPT MASK;

FIG. 316 CPU REL;

FIG. 317 CPU UNIT ADR;

FIG. 318 CH/CPU CONNECTIONS;

FIG. 319 MODAR;

FIG. 320 TIM-CH PRI;

FIG. 321 RETRY;

FIG. 322 SAP / STR PRI;

FIG. 323 SUP CALL PRI;

FIG. 324 A / B IRPT;

FIG. 325 I IRPT FM I;

FIG. 326 IRPT PRI;

FIG. 327 E PGM PRI;

FIG. 328 EXT IRPT;

FIG. 329 IRPT PRI LOGIC;

FIG. 330 IRPT PSW ADR;

FIG. 331 CONS IRPT;

FIG. 332 IRPT SET / INH;

FIG. 333 E / I IRPT LCHS;

FIG. 334 IRPT SET PSW;

FIG. 335 CH IRPT RESP;

FIG. 336 CH IRPT REL;

FIG. 337 IC / RCVY REQ;

FIG. 338 MCH CHK CTRL;

FIG. 339 MCH CHK TIME;

FIG. 340 MCH CHK;

FIG. 341 EXT SIG LCHS;

FIG. 342-345 EXT IRPT PAR;

FIG. 346 IRPT CYC 1;

FIG. 347 IRPT CYC 2;

FIG. 348 IRPT CYC 3;

FIG. 349 IRPT PRI HOLD;

FIG. 350 IRPT CYC 4;

FIG. 351 IRPT CYC 5;

FIG. 352 IPL BFR;

FIG. 353 IRPT CYC 6;

FIG. 354 TIMER ADV REQ;

FIG. 355 IRPT LCH PRI;

FIG. 356 IRPT L CYC;

FIG. 357 WAIT STATUS;

FIG. 358 IRPT CTRLS;

FIG. 359 IRPT CODE 1;

FIG. 360 IRPT CODE 2;

FIG. 361 IRPT CODE 3;

FIG. 362 INTERRUPT SEQUENCING;

FIG. 363 I- O INTERRUPT PROCESSING;

FIG. 364 TIMER ADVANCE REQUEST SEQUENCING;

FIG. 365 RECOVERY ONLY SEQUENCING;

FIG. 366 IPL LOAD PSW SEQUENCING;

FIG. 367 T1 TYPE I PGM IRPT ENTRANCE SEQ;

FIG. 368 T2 TYPE I PGM IRPT ENTRANCE SEQ;

FIG. 369 E IRPT FM I/E ENTRANCE SEQ;

FIG. 370 CPU SAP CHECK;

FIG. 371 EX OF OVLPD I & E IRPTS;

FIG. 372 CPU COMM-BUSY & TIMING;

FIG. 373 VFL DATA FLOW;

FIG. 374 RIGHT BYTE GATE;

FIG. 375 IS A BLOCK DIAGRAM CONSISTING OF FIG. 375a LEFT BYTE GATE AND FIG. 375b NONRESTORE TRG;

FIG. 376 BG SIGN DETECT;

FIG. 377 EDIT DECODE;

FIG. 378 SIGN GEN & EDIT DEC;

FIG. 379 EDIT SOURCE DECODE LCHS;

FIG. 380 RIGHT DIGIT GATE;

FIG. 381 LEFT DIGIT GATE;

FIG. 382 T/C ZERO DET;

FIG. 383 RIGHT P ADJ;

FIG. 384 LEFT P ADJ;

FIG. 385 TRUE/CPMNT PLUS 6;

FIG. 386 BIN ADDER;

FIG. 387 D/C-DEC CORRECT;

FIG. 388 DA CARRY;

FIG. 389 DECIMAL ADDER PARITY PREDICT;

FIG. 390 DA HS CHK;

FIG. 391 DA ERROR;

FIG. 391a DIRECT DATA & OUT KEY IN GATE;

FIG. 392 AOE IN;

FIG. 393 AOE;

FIG. 394 DIGIT BUFFER;

FIG. 395 DIGIT CTR;

FIG. 396 DC/DB P;

FIG. 397 DIRECT DATA REG;

FIG. 398 Y/Z REG;

FIG. 399 Y/Z INCR;

FIG. 400 Y/Z LCH;

FIG. 401 VFL TO AA & PSW GATE;

FIG. 402 K BUS GATE;

FIG. 403 K BUS ZERO DET;

FIG. 403a LGTH / ADR P;

FIG. 404 S & T LCHS;

FIG. 405 S & T INCRS;

FIG. 406 S & T REGS;

FIG. 407 S PTR;

FIG. 408 T PTR;

FIG. 409 T IN DEC;

FIG. 409a DIAGRAM OF VFL SEQUENCERS;

FIG. 410 TON SEQ 2 & 4;

FIG. 411 SET SEQ 2, SF1 TGRS;

FIG. 412 SET SEQ 4 TGR;

FIG. 413 SET SEQ 3-7;

FIG. 414 EN/INH SEQS;

FIG. 415 VFL SEQ 1;

FIG. 416 VFL SEQ 2;

FIG. 417 VFL SEQ 3;

FIG. 418 VFL SEQ 4;

FIG. 419 VFL SEQ 5;

FIG. 420 VFL SEQ 6;

FIG. 421 VFL SEQ 7;

FIG. 422 VFL SEQ 8;

FIG. 423 VFL SEQ 9;

FIG. 424 VFL SEQ 10;

FIG. 425 VFL SEQ 11;

FIG. 426 VFL SEQ 12;

FIG. 427 SET PF 1;

FIG. 428 PF CTRLS;

FIG. 429 PF 1;

FIG. 430 SET PF2;

FIG. 431 PF 2;

FIG. 432 SET PF3;

FIG. 433 PF 3;

FIG. 434 PF 4;

FIG. 435 PF 1-2-8;

FIG. 436 PF IN PROCESS;

FIG. 437 PF 4 TGR-LCH;

FIG. 438 STORE/FETCH TGR;

FIG. 439 SF SEQ-1;

FIG. 440 SF SEQ-2;

FIG. 441 SF SEQ-3;

FIG. 442 SET UP SEQ-1;

FIG. 443 SET UP SEQ-2;

FIG. 444 SET IS 1;

FIG. 445 IS 1;

FIG. 446 TON IS 2;

FIG. 447 SET IS 2;

FIG. 448 IS 2;

FIG. 449 SET IS 3;

FIG. 450 IS 3;

FIG. 451 IS COMB'N-1;

FIG. 452 IS COMB'N-2;

FIG. 453 TON/TOF VFL T1;

FIG. 454 SET VFL T2;

FIG. 455 VFL T1, T2;

FIG. 456 RST T2 TGR;

FIG. 457 T3;

FIG. 458 T4;

FIG. 459 T5;

FIG. 460 SET T6;

FIG. 461 T6;

FIG. 462 T7;

FIG. 463 T8;

FIG. 464 T1, T2 DECODE;

FIG. 465 SEQ A TGR;

FIG. 466 SEQ A;

FIG. 467 SEQ B;

FIG. 468 SEQ C;

FIG. 469 SET SEQ D;

FIG. 470 SEQ D;

FIG. 471 DD SEQ CTRL;

FIG. 472 Y-Z TESTS;

FIG. 473 S,T,Y,Z COMP;

FIG. 474 T,Y,Z TESTS;

FIG. 475 IOP TESTS;

FIG. 476 MP-DP TESTS;

FIG. 477 GT L WITH S;

FIG. 478 GT K WITH S;

FIG. 479 RST K & L WITH S;

FIG. 480 K & L WITH S;

FIG. 481 T & DC/DB CTRLS;

FIG. 482 DC/DB-LBG;

FIG. 483 T & DC/DB CTRL TGRS;

FIG. 484 GT TO AA,BLK K ERR;

FIG. 485 GT TO AA-1;

FIG. 486 GT TO AA-2;

FIG. 487 H,S,T CTRLS;

FIG. 488 REL T PTR;

FIG. 489 REL S & T PTRS;

FIG. 490 S & T CTRLS;

FIG. 491 Y & Z CTRLS;

FIG. 492 GT REL AT A;

FIG. 493 COUNT Y & Z;

FIG. 494 AOE GATES;

FIG. 495 COUNT DC;

FIG. 496 DB/DC GATES-1;

FIG. 497 DB/DC GATES-2;

FIG. 498 DB/DC CTRLS;

FIG. 499 VFL ADR,GR,MKS;

FIG. 500 VFL GR,MKS;

FIG. 501 VFL CR,MODAR;

FIG. 502 DEC COND CODE;

FIG. 503 TRT OR EDMK SET PA;

FIG. 504 VFL K GTS-1;

FIG. 505 VFL K GATES-2;

FIG. 506 VFL MK & K CTRLS;

FIG. 507 VFL K GTS 3;

FIG. 508 SIGNS COMP;

FIG. 509 VFL OVLP;

FIG. 510 AOE OPS;

FIG. 511 TON E FTCH;

FIG. 511a SET E FTCH REQ TGR;

FIG. 512 SET E STR;

FIG. 513 E FTCH;

FIG. 514 E GT AA TO SAR,H;

FIG. 515 VFL IRPTS;

FIG. 516 GT TO DA LEFT;

FIG. 517 GT DA ACROSS;

FIG. 518 FORCE ZONE, SIGN;

FIG. 519 GT INVRT SIGN;

FIG. 520 GT DA TRUE;

FIG. 521 GT DA CPMNT;

FIG.522 DA INVRT SIGN;

FIG. 523 DA PARITY GATES;

FIG. 524 RGB P TO DA;

FIG. 525 GT LOD P;

FIG. 526 GT HOD P;

FIG. 527 GT & FORCE P;

FIG. 528 DA CARRY GATES;

FIG. 529 REL DA CARRY;

FIG. 530 CHK FOR SIGN/DIGIT;

FIG. 531 DEC DATA IRPT;

FIG. 532 DEC CORCT/RST ZERO;

FIG. 533 VFL SIGN;

FIG. 534 VFL THRU/END;

FIG. 535 E UNIT DATA FLOW (BINARY);

FIG. 536 E UNIT DATA FLOW (BINARY);

FIG. 537 EOP REG;

FIG. 538 LCOP REG;

FIG. 539 LCOP PARITY CHK;

FIG. 540 ED-1;

FIG. 541 ED-2;

FIG. 542 ED-3;

FIG. 543 ED-4;

FIG. 544 ED-5;

FIG. 545 ED-6;

FIG. 546 ED-7;

FIG. 547 ED-8;

FIG. 548 ED-9;

FIG. 549 ED-10;

FIG. 550 ED-11;

FIG. 551 ED-12;

FIG. 552 ED-13;

FIG. 553 ED-14;

FIG. 554 ED-15;

FIG. 555 ED FORMATS;

FIG. 556 ED-16;

FIG. 557 ED EVEN/ODD;

FIG. 558 ED-17;

FIG. 559 ED-18;

FIG. 560 ED-19;

FIG. 561 ED-20;

FIG. 562 ED-21;

FIG. 563 ED-22;

FIG. 564 ED-23;

FIG. 565 LD-1;

FIG. 566 LD-2;

FIG. 567 LD-3;

FIG. 568 LD-4;

FIG. 569 LD-5;

FIG. 570 LD-6;

FIG. 571 LD-7;

FIG. 572 LD-8;

FIG. 573 LD-9;

FIG. 574 LD-10;

FIG. 575 LD-11;

FIG. 576 LD-12;

FIG. 577 LD-13;

FIG. 578 LD-14;

FIG. 579 LD-15;

FIG. 580 LD-16;

FIG. 581 FPR CTRL;

FIG. 582 FR2 TGR;

FIG. 583 FLP REGS;

FIG. 584 SEL FPR OUT-CTRLS;

FIG. 585 FPR OUT GATE;

FIG. 586 FPR BUS;

FIG. 587 RBL GATES;

FIG. 588 RBL IN-4 THRU 31;

FIG. 589 IS A BLOCK DIAGRAM CONSISTING OF FIG. 589a RBL IN 32-63 AND FIG. 589b RBL;

FIG. 590 J REG GATES;

FIG. 591 J REG IN 0-7;

FIG. 592 J REG IN 8-63;

FIG. 593 J REG RELEASE;

FIG. 594 J REG;

FIG. 595 K REG GATES;

FIG. 596 K REG IN;

FIG. 597 K REG RELEASE;

FIG. 598 IS A BLOCK DIAGRAM CONSISTING OF FIG. 598a K REG, 598b K REG ZERO DETECT 1 AND 598c K REG ZERO DETECT 2;

FIG. 599 L REG GATES;

FIG. 600 L REG RELEASE;

FIG. 601 L REG;

FIG. 602 M REG GATES;

FIG. 603 M REG IN 0-31;

FIG. 604 M REG IN 32-63;

FIG. 605 M REG RELEASE;

FIG. 606 M REG;

FIG. 607 MA INPUT GATES;

FIG. 608 MA T/C IN GATES;

FIG. 609 STANDARD MA GATING TRIGGER-1;

FIG. 610 STANDARD MA GATING TRIGGER-2;

FIG. 611 CVB COMPACTER;

FIG. 612 CVB CHART;

FIG. 613 CVD CORR;

FIG. 614 ER GATES;

FIG. 615 ER RELEASE;

FIG. 616 ER REG;

FIG. 617 SC GATES;

FIG. 618 SC RELEASE;

FIG. 619 SC REG;

FIG. 620 SC IN;

FIG. 621 MAIN ADDER;

FIG. 622 SECTION CARRIES;

FIG. 623 GROUP FUNCTIONS;

FIG. 624 BIT FUNCTIONS (T & G);

FIG. 625 HALF SUMS+MA;

FIG. 626 SECTION FUNCTIONS;

FIG. 627 GROUP CARRIES-MA;

FIG. 628 C IN BITS (8-63);

FIG. 629 INTERNAL C IN BITS 0-6;

FIG. 630 C IN BITS 4-6;

FIG. 631 C IN BITS 0-3;

FIG. 632 SUM;

FIG. 633 MA LEFT EXT;

FIG. 634 SHIFTER IN;

FIG. 635 MA RIGHT EXT;

FIG. 636 SHIFTER;

FIG. 637 MA LATCH;

FIG. 638 MA P INVRT;

FIG. 639 P INT C;

FIG. 640 MA & HS P;

FIG. 641 MAIN ADDER LATCH PARITY;

FIG. 642 PRED HS PARITY;

FIG. 643 HS PARITY CHK;

FIG. 644 BIT FUNCTION CHK;

FIG. 645 C IN/OUT/ERR;

FIG. 646 BYTE ERR;

FIG. 647 MA ERR;

FIG. 648 MA ONE/ZERO;

FIG. 649 DIV RSLT;

FIG. 650 DVDN GTR DVSR;

FIG. 651 DVSR GEN;

FIG. 652 DCDR E,F;

FIG. 653 DCDR A-C;

FIG. 654 MULTIPLES NAC;

FIG. 655 MULTIPLES AC;

FIG. 656 DVSR MULTIPLES;

FIG. 657 DVSR MPLS- QUO FACTORS;

FIG. 658 IS A BLOCK DIAGRAM CONSISTING OF FIG. 658a X/Y QUOTIENTS AND 658b QUO-QUO SIGN OVFL TGRS;

FIG. 659 ENABLE J;

FIG. 660 STANDARD EA GATING TRIGGER;

FIG. 661 EA INPUT;

FIG. 662 EA T/C IN;

FIG. 663 DCDR IN;

FIG. 664 EXP ADDER;

FIG. 665 SFT/DCR DCDR-1;

FIG. 666 SFT/DCR DCDR-2;

FIG. 667 SC VALUE DETECTER-1;

FIG. 668 SC VALUE DETECTER-2;

FIG. 669 MA GATING CHECK;

FIG. 670 EA CHK;

FIG. 671 K ERR;

FIG. 672 K ERR TGRS;

FIG. 673 IRPT TGRS:

FIG. 674 E IRPT CODE;

FIG. 675 E/L & 1ST E;

FIG. 676 E SET CR;

FIG. 677 E TO CR-1;

FIG. 678 E TO CR-2;

FIG. 679 FXP-EXP OVFL;

FIG. 680 FXP-FLP IRPT;

FIG. 681 EXP UNFL & LOST SIG;

FIG. 682 ADR & DEC OVFL;

FIG. 683 E IRPT TGR;

FIG. 684 J LOADED TGR;

FIG. 685 ADR INV;

FIG. 686 ACC TGR/LCH;

FIG. 687 MAN STR;

FIG. 688 BLK PA;

FIG. 689 REL FPR/GR;

FIG. 690 EBR SUCC;

FIG 691 E CTRLS FOR I-1;

FIG. 692 E CTRLS FOR I-2;

FIG. 693 E CTRLS FOR I-3;

FIG. 694 MPLR BUS;

FIG. 695 MPLR DECODE;

FIG. 696 MPLR GT CTRLS;

FIG. 697 MPLR BUS P;

FIG. 698 J CTRLS-1;

FIG. 699 EN SIGNS;

FIGS. 700-703 M ZERO;

FIG. 704 EXP OVFL/UNFL;

FIG. 705 C OUT;

FIG. 706 GT FROM J;

FIG. 707 H REG LCH;

FIG. 708 ER1=IR2 LCH;

FIG. 709 IRPT RESET;

FIG. 710 1ST FXP CTRL;

FIG. 711 1ST FXP;

FIG. 712 SET PA;

FIG. 713 SIGN CTRL;

FIG. 714 PUT AWAY; FIG. 715 HW LGC;

FIG. 716 HW ADD;

FIG. 717 STR TGR/LCH;

FIG. 718 EM1;

FIG. 719 EM2;

FIG. 720 SET ELC;

FIG. 721 ELC SETS;

FIG. 722 TON ELC TGR;

FIG. 723 1ST FLP;

FIG. 724 PRESHIFT ADD;

FIG. 725 ITRN PREP;

FIG. 726 ITRN TGR;

FIG. 727 ADD TGR;

FIG. 728 NORM TGR/LCH;

FIG. 729 CURT TGR/LCH;

FIG. 730 TIM ADV;

FIG. 731 STR PSW;

FIG. 732 DX 1 TGR/LCH;

FIG. 733 D2 TGR LCH;

FIG. 734 REL L 0-63;

FIG. 735 REL COND;

FIG. 736 D3;

FIG. 737 DL 4;

FIG. 738 1ST TERM;

FIG. 739 2ND TERM;

FIG. 740 QUO TRANS CMPLT;

FIG. 741 DIV ZERO RESULT;

FIG. 742 TEST CYC;

FIG. 743 ENABLES;

FIG. 744 M GT CTRLS-1;

FIG. 745 M GT CTRLS- 2;

FIG. 746 M GT CTRLS-3;

FIG. 747 AOB/RBL TO M;

FIG. 748 RBL TO M;

FIG. 749 M GT CTRLS-4;

FIG. 750 J CTRL-2;

FIG. 751 ER CTRLS- 1;

FIG. 752 SC IN GT- 1;

FIG. 753 MA CTRLS- 1;

FIG. 754 SC IN GT- 2;

FIG. 755 FPR TO EA T/C;

FIG. 756 J CTRLS- 3;

FIG. 757 1ST CYC M;

FIG. 758 SHFT & PROPAGATE;

FIG. 759 EA CTRLS-1;

FIG. 760 EA CRTLS-2;

FIG. 761 DCDR CTRLS-1;

FIG. 762 EA CTRLS-3;

FIG. 763 DCDR CTRLS-2;

FIG. 764 MA CTRLS-2;

FIG. 765 MA CTRLS-3;

FIG. 766 MA CTRLS-4;

FIG. 767 MA CTRLS-5;

FIG. 768 MA CTRLS-6;

FIG. 769 MA CTRLS-7;

FIG. 770 MA CTRLS-8;

FIG. 771 MA CTRLS-9;

FIG. 772 MA CTRLS-10;

FIG. 773 MA CTRLS-11;

FIG. 774 MA CTRLS-12;

FIG. 775 MA CTRLS-13;

FIG. 776 MA CTRLS-14;

FIG. 777 J TO RBL;

FIG. 778 L CTRLS-1;

FIG. 779 SHIFT+1;

FIG. 780 SHIFT-2;

FIG. 781 SHIFT-3;

FIG. 782 SHIFTING CMPLT;

FIG. 783 K TO RBL;

FIG. 784 SEL AND/XOR;

FIG. 785 EA IN GTS-1;

FIG. 786 EA IN GTS-2;

FIG. 787 EA IN GTS-3;

FIG. 788 EA IN GTA-4;

FIG. 789 EA IN GTS-5;

FIG. 790 EA IN GTS-6;

FIG. 791 EZ/SC CTRLS;

FIG. 792 FORCE SC;

FIG. 793 FORCE EA;

FIG. 794 P TO MA;

FIG. 795 MA GT SETS;

FIG. 796 K GTS-1;

FIG. 797 K GTS-2;

FIG. 798 K GTS-3;

FIG. 799 K GTS-4;

FIG. 800 J=ZERO LCH;

FIG. 801 MA GT-15;

FIG. 802 MA GT-16;

FIG. 803 STATUS-1;

FIG. 804 STATUS-2;

FIG. 805 STATUS-3;

FIG. 806 STATUS-4;

FIG. 807 STATUS-5;

FIG. 808 STATUS-6;

FIG. 809 STATUS -7;

FIG. 810 STATUS-8;

FIG. 811 STATUS-9;

FIG. 812 MC SYST CONTROL PANEL;

FIG. 813 OPR CTRL;

FIG. 814 INDS;

FIG. 815 IND CTRL;

FIG. 816 OPR CONSOLE;

FIG. 817 OPR INTERVENTION-1;

FIG. 818 OPR INTERVENTION-2;

FIG. 819 ENGR CTRL;

FIG. 820 FLT CTRL;

FIG. 821 PB NET;

FIGS. 822-825 START;

FIG. 826 HALT;

FIG. 827 STOP/RESET;

FIG. 828 FR SIGNAL;

FIG. 829 PDU CLKS;

FIG. 830 MAN STG & CHKS;

FIG. 831 PDU CTRLS-2;

FIG. 832 PDU CTRLS-3;

FIG. 833 PDU CTRLS-4;

FIG. 834 IPL CTRL;

FIG. 835 FORCED REPEAT;

FIG. 836 T1 OR WAIT;

FIG. 837 DISABLE INV;

FIG. 838 RESTART;

FIG. 839 INTERVAL TIMING;

FIG. 840 METER CTRL;

FIG. 841 METER;

FIG. 842 D1-D3;

FIG. 843 PROCEED;

FIG. 844 STOP/PSDO CHK;

FIG. 845 PSDO CHK;

FIG. 846 MCW CTRLS;

FIGS. 847a-847d DIAG SEL CODE;

FIG. 848 DIAG DECODE;

FIG. 849 CH IRPT TOF;

FIG. 850 MCW CHART;

FIG. 851 MCW COUNT REG;

FIG. 852 MCW CTR;

FIG. 853 COUNT LCH;

FIG. 854 COUNT DECODE;

FIG. 855 PDU ADR BUS;

FIG. 856 PDU DATA BUS;

FIG. 857 PDU;

FIG. 858 PDU;

FIG. 859 STORAGE;

FIG 860 STG DATA CHK;

FIG. 861 STG CLK;

FIG. 862 STG RST;

FIG. 863 MARK P ERR;

FIG. 864 MARK P;

FIG. 865 ADR STG CHK;

FIG. 866 STG CHK;

FIG. 867 CANCEL;

FIG. 868 SBI EVEN/ODD;

FIG. 869 MAR ADR ERR;

FIG. 870 DATA ERR;

FIG. 871 MAR;

FIG. 872 COM STR CANCEL;

FIG. 873 MARK;

FIG. 874 DOG CHK;

FIG. 875 MDR;

FIG. 876 STG PROTECTION;

2.0 REFERENCES

The following reference explains the full environment of the present invention: "IBM System/360 Principles of Operation," a copy of which has been deposited in the Scientific Library of the U.S. Patent Office "IBM Form No. A-22-6821."

Another reference, which discloses a small system in accordance with the architecture of said System/360 Manual is found in a copending application of the same assignee entitled DATA PROCESSING SYSTEM, Ser. No. 357,372, filed on Apr. 6, 1964, now U.S. Pat. No. 357,372 by G. M. Amdahl, et al.

An input/output channel device which is adapted for use in said environmental system is disclosed in a copending application of the same assignee entitled AUTOMATIC CHANNEL APPARATUS, Ser. No. 357,369, filed Apr. 6, 1964, now U.S. Pat. No. 3,488,633 by L. E. King, et al.

A core storage device is shown in a copending application of the same assignee entitled DRIVE-SENSE LINE WITH INDEPENDENCE DEPENDENT ON FUNCTION, Ser. No. 445,306, filed on Apr. 5, 1965, by Anatol Furman, now U.S. Pat. No. 3,413,622, issued Nov. 26, 1968.

A bipolar latch, used throughout said environmental system, is described in detail in an article by O. J. Bedrij, entitled GATED TRIGGER WITH BIPOLAR SET, IBM Technical Disclosure Bulletin, Vol. 2 No. 6, Apr. 1960, Page 50 (a copy of which has been deposited in the Scientific Library of the U.S. Patent Office).

A binary trigger is referred to in particular in section 5. This trigger is described in detail in section 11b of a copending application of the same assignee entitled PARALLEL MEMORY, MULTIPLE PROCESSING, VARIABLE WORD LENGTH COMPUTER, Ser. No. 332,648, filed Dec. 23, 1963, by R. S. Carter and W. W. Welz, now U.S. Pat. No. 3,270,325 issued on Aug. 30, 1966.

Binary-decimal addition is described in a copending application of the same assignee, Ser. No. 223,431, entitled BYTE PROCESSING UNIT, filed Sept. 13, 1962 by Robert Keslin. A shifter is described in a copending application of the same assignee, Ser. No. 162,477, PROPORTIONAL SPACE MATRIX PRINTER, filed Dec. 27, 1961, by Richard L. Taylor, now U.S. Pat. No. 3,174,427 issued Mar. 23, 1965.

Additional references include the following copending applications of the same assignee as in this case, each of which forms a part of, and is illustrated in the environmental system:

STORAGE REFERENCE PRIORITY IN A DATA PROCESSING SYSTEM, Ser. No. 445,316, filed Apr. 5, 1965, by L. J. Hasbrouck et al. now abandoned.

STORAGE REFERENCE PRIORITY IN A DATA PROCESSING SYSTEM, Ser. No. 609,239 filed on Jan. 13, 1967, by L. J. Hasbrouck et al. said application, being a continuation-in-part of Ser. No. 445,316, now U.S. Pat. No. 3,376,556 issued on Mar. 2, 1968.

UNIT UNAVAILABILITY DETECTOR FOR A DATA PROCESSING SYSTEM, Ser. No. 445,318, filed Apr. 5, 1965, by W. P. Wissick et al. now U.S. Pat. No. 3,341,824 issued on Sept. 12, 1967.

RATE CONTROL IN AN ASYNCHRONOUS DEVICE STORAGE ACCESSING APPARATUS, Ser. No. 445,319, filed Apr. 5, 1965, by W. P. Wissick et al. now abandoned.

RATE CONTROL IN AN ASYNCHRONOUS DEVICE STORAGE ACCESSING APPARATUS, Ser. No. 609,254, filed on Jan. 13, 1967, by W. P. Wissick et al. said application being a continuation-in-part of now abandoned application, Ser. No. 445,319 filed Apr. 5, 1965, now U.S. Pat. No. 3,377,579 issued on Apr. 9, 1968.

STORAGE CANCELLATION AND PANEL DATA KEY FETCHING IN A DATA PROCESSING SYSTEM, Ser. No. 445,311, filed Apr. 5, 1965, by W. P. Wissick et al. now abandoned.

STORAGE CANCELLATION AND PANEL DATA KEY FETCHING IN A DATA PROCESSING SYSTEM, Ser. No. 609,252 filed on Jan. 13, 1967 by W. P. Wissick et al. said application being a continuation-in-part of now abandoned application Ser. No. 445,311, filed Apr. 5, 1965, now U.S. Pat. No. 3,374,472 issued on Mar. 19, 1968.

3.0 NOMENCLATURE

The nomenclature of the present embodiment is almost entirely consistent with that shown in said System/360 Manual. A few exceptions do exist however. One of these is the instruction Execute and is herein referred to in abbreviated form as XEQ, whereas said Manual refers to this instruction in abbreviated form as EX. Another example is the instruction Edit; it is referred to in abbreviated form herein as EDT whereas said Manual refers to same as ED. In order to avoid confusion with "execution," "E decode," and other similar functions in the present embodiment, these changes have been made. However, a good definition of each of the instructions which may be performed by the present embodiment is found in said Manual. Additionally, the functions of a data-processing system in accordance with the architectural definition within said Manual are applicable to this embodiment, with the exception of the fact that the present embodiment does not provide for: sharing of storage by more than one system, a multiplex channel, direct coupling between computers, large capacity storage, and certain other features which could be available on an embodiment of the system described in said Manual. However, said environmental system is readily adapted for the achievement of these functions.

In the present embodiment, a bit means a binary unit of intelligence, which can be either a one or a zero. A byte comprises eight bits, two bytes comprise a syllable or a half-word. Two syllables, or two half-words comprise a word, which includes 32 bits. A storage word is two words or 64 bits in the environmental system of the present embodiment. In storage, and within the data flow of the environmental system, there is one parity bit for each eight bits of data; at certain points in a data flow this is altered; for instance, at the output of an adder, it is possible that parity may be carried to several stages of logic on a four-bit basis, and then combined on an eight-bit basis.

In the detailed descriptions herein, the signals which propagate between various figures are all identified by unique lines which are referred to in the upper case (such as SAR meaning the output of the storage address register, CPU RST being the line that causes a computer reset of a particular type). As is discussed more fully in section 5, hereinafter, the use of positive and negative signals as inputs to positive- and negative-type circuits is so customary, that it no longer has any significance to consider signals in actual circuitry as being either the true or the complement of an event; for instance, if a signal is generated in a positive sense when the event occurs, a minus signal may nonetheless be required to indicate that event due to the fact that the circuit which is utilizing the signal requires a negative input. For that reason, complementary functions (such as NOT LC, meaning the complement of the LC signal) are referred to as inputs even though they may not explicitly generated in the circuit where the event is manifested by the true signal.

In block diagrams which comprise a plurality of blocks, each block being represented by one or more figures, the figure or figures within which the details of the particular block are shown may be identified in that block by figure number only, without the word "FIG." actually being printed within that block. This allows a simpler block configuration which is easier to read.

In the description of the detailed Figures, the various circuit elements are referred to by reference numerals, the reference numerals being applicable only in the particular figure number. However, in any case where a particular item is referred to in more than one place, it would have the same reference numeral wherever it is referred to. On the other hand, reference numerals between 1 and 30 are used repetitively throughout the environmental system due to the fact that the size of the environmental system would require reference numerals having four or five digits if completely sequential reference numerals were used for the entire environmental system. Therefore, any possible tendency toward confusion is alleviated by also specifying the figure number along with the reference numeral; additionally, the description itself is patently clear insofar as the precise element to which reference is being made.

When terms such as "storage cycle" or "last E cycle" are used, machine cycles as such are not necessarily involved. For instance, a storage cycle required five machine cycles in the embodiment of said environmental system; last cycle triggers may be set from the start of NOT L time to the start of the following NOT L time, a period equal to a 200 nanosecond machine cycle, but displaced therefrom by approximately 65 nanoseconds since the basic machine cycle is defined to be from the start of A time to the end of A time, as is described in section 7. The duration or phase of any specially referred to cycle often differs from a basic machine cycle. The terms, when used, refer to the latched condition or event being described, as is apparent in the context where used.

In order to facilitate cross referencing between the various copending applications, and most particularly, to facilitate cross referencing of embodiments in said copending applications of portions of said environmental system with the embodiment of a full environmental system, constant sequential figure numbers are used in all of said copending applications, whereby all figure numbers are identical in all of the cases. In order to reduce the cost of printing, figure numbers which relate to circuits not required in smaller embodiments are shown in an illustrative manner only. Any reference to a figure which is shown in an exemplary form in one of said copending applications should be interpreted as a reference to that same figure in the embodiment of said environmental system.

In certain instances, control lines comprising a particular combination of operational decoding or other status indications may not be shown in detail; that is, a line called "BR OR STATUS SWX" may be utilized, as an input to a circuit, but may not be generated, as an output from a circuit, However, there are innumerable examples of generated decode lines such that the generation of any other one would be well within the skill of the art. As an example, a line called "VFL T1 OR Y 0" could be generated by the OR of "VFL T1" with "Y O," or with "NOT Y EQ O," or by ORing the bits of the Y REG to see that Y does indeed equal other than zero.

4.0 BRIEF DESCRIPTION OF ENVIRONMENTAL SYSTEM FIG. 2

FIG. 1 broadly shows a typical data-processing system as including a central-processing unit, one or more storage units, one or more input/output channels and a control panel.

In FIG. 2, a more detailed block representation of said environmental system is shown to include a bus control unit (BCU) which is described in section 6, and which provides data flow communication between the various units of the system, and provides controls for the storage devices. The operator controls, certain maintenance controls, and basic stop start and reset controls are provided in the power distribution unit (PDU) described in section 21. The system also includes an I unit, the data flow portion of which is described in section 9, the main other functions of the unit being described in separate sections. The clock is shown in section 7, and includes the main timing pulses which are utilized throughout the system so as to synchronize operations. In section 10, instruction sequencing is described, and instruction fetching is described in section 11. Branching operations, and their effect on the remainder of the system are all described in section 12. Communication with channels, and performance of certain supervisory type instructions, inter alia, are described with respect to an I execution unit (IE UNIT) in section 13. Interruption handling, and functions which, although not interruptions, are handled by the interruption circuitry, are described in section 14 of said environmental system. The E unit of said environmental system includes a binary portion and a VFL portion, which are referred to in a compound fashion; both the binary and VFL portion are considered part of the E unit, and E-unit controls can come from either portion. However, the binary portion is generally not referred to as such, but is referred to merely as the E unit, and the VFL (variable field length) portion is usually referred to as the "VFL." Storage devices are not completely described herein, but the logical control thereover as it relates to the bus control unit is described in section 22.

5.0 COMPONENT CIRCUITS FIG. 3 THROUGH FIG. 8

In FIG. 3 through FIG. 8, component circuits of the type which may be utilized in said environmental system are illustrated. These are not exhaustive, and merely illustrate types of circuits which might be utilized, and the manner in which they are illustrated in the detailed description of said environmental system.

In FIG. 3a, a simple latch is shown. This comprises an "AND-OR-INVERTER" combination which includes an OR-INVERT circuit 1 and two AND-circuits 2, 3 as well as two inverters 4, 5. In normal operation, whenever the LC line is positive, the inverter 5 will provide a signal b to the AND-circuit 2 so that a +X signal, whenever it may arrive, will cause the AND-circuit 2 to activate the OR-INVERT circuit 1 thereby generating a -Y signal. If the +X signal is removed, then the -Y signal will disappear. The -Y signal causes the inverter 4 to generate the +Y signal which is fed back to an AND-circuit 3; however, so long as the -LC pulse is present, the AND-circuit 3 will not operate, so that the circuit of FIG. 3a is essentially an AND-circuit whereby a +X signal and the signal from the inverter 5 pass through the AND-circuit 2, becomes inverted in the OR-circuit 1, and no latching takes place.

When the LC signal turns positive (at NOT L time) then any +X signal will cause a +Y-signal to be gated through the AND-circuit 3 thereby causing the circuit of FIG. 3a to become latched for the duration of the +LC signal. When the LC signal returns to a negative condition (at L time) then the state of the latch can again be changed. During the time that the circuit is latched, the AND-circuit 3 will be passing a signal through the OR-circuit 1 provided the latch was on at the time that the latching condition commenced, and the AND-circuit 2 is blocked by the inverter 5. When the LC line returns to a negative condition, the AND-circuit 3 will be immediately blocked, and the inverter 5, having about a 7 nanosecond delay, will later cause the unblocking of the AND-circuit 2. Thus, there is a short period of about 7 nanoseconds (as illustrated in FIG. 3d) when the circuit of FIG. 3a will have no output whatever. This is of too short a duration to be illustrated in FIG. 3c which shows the operation of the latch of FIG. 3a in general terms.

The circuit of FIG. 3a is illustrated herein as shown in FIG. 3b. Thus, the circuit of FIG. 3a can be considered to be a latch circuit 6 settable by an AND-circuit 7 at NOT L time, to be reset at L-time.

In FIG. 4a is shown a variation of a latch having a combined reset condition which, as shown in FIG. 4b includes X or NOT Y. Notice that the AND-circuit 1 in FIG. 4a has a minus D signal applied thereto which represents a NOT D as illustrated by the AND-circuit 2 in FIG. 4b. Also notice that the AND-circuit 3 in FIG. 4a has both -X and applied Y signals thereto so that the latched effect will be ended by the disappearance of -X or by the disappearance of +Y. This is illustrated as resetting in response to either X or NOT Y by the OR-circuit 4 in FIG. 4b. A still further complicated latch is illustrated in FIG. 5a. This includes an AND-INVERT circuit 1 which passes a signal through an inverter 2 (the output of which then would be positive when the conditions to the AND-INVERT circuit 1 are met) so as to cause an AND-circuit 3 to operate when the +AC signal appears. +AC means a positive-controlled clock signal having the A time duration. The "C" within "AC" stands for "controlled," in contrast with "running," as is the case when an AR signal is involved. The AR signal would be of the same duration and timing as the AC signal, but could run even through single-cycle operations, whereas the AC signal would be stopped during single-cycle operations.

The latch of FIG. 5a can be reset by the CPU RST signal, or by the raw output of the AND-INVERT circuit 1 as applied to an AND-circuit 4. The circuit of FIG. 5a would be illustrated herein as shown in FIG. 5b, wherein an AND-circuit 5 will either set or reset the latch in dependence upon whether the conditions are met, due to the assistance of an inverter 6. Notice also that single-input AND circuits such as the AND-circuit 7 in FIG. 5a actually represent merely an input to the OR INVERT circuit, as illustrated by the direct application of the scan signal to the OR-circuit 8 in FIG. 5b.

A variation in the circuit of FIG. 5a is shown in FIG. 6a, wherein a first OR-INVERT circuit 1 operates when the latch is in the on condition, and a second OR-INVERT circuit 2 operates when the latch is in the reset condition. When the OR-circuit 2 operates, it has a negative output, thereby locking an AND-circuit 3. However, a negative output from the OR-circuit 2 does not preclude an output from the latch inasmuch as either one of two AND-circuits 4, 5 could supply an input to the OR-circuit 1. If either of the AND-circuits 4, 5 do operate, then there will be a minus signal out of the OR-circuit 1 which will block a single-input AND-circuit 6 at the input to the OR-circuit 2 so that the OR-circuit 2 will normally have no output unless inputs are applied to either an AND-circuit 7 or a single input AND-circuit 8. With the OR-circuit 2 locked, its positive output will be applied to an AND-circuit 3, and if there is an X signal at the AND-circuit 3, then the latch will remain on even though either of the OR-circuits 4, 5 which turn the latch on in the first place no longer has inputs thereto. This is illustrated more clearly in the circuit shown in FIG. 6b, which represents the manner of illustrating this circuit herein. As seen in FIG. 6b, the latch can be turned on by NOT A and B, or by C and NOT D. If turned on, it will latch up provided that E and F are not both present, and provided that G and X are both present. If the latch turns on and becomes latched in an on condition, then the appearance of E and F together or the appearance of NOT G or NOT X will cause the latch to turn off.

In FIG. 7a, and AND INVERT circuit with minus inputs is shown to create a +W signal. This is fully equivalent to the circuit of FIG. 7b wherein a positive, noninverting OR circuit responds to positive X Y Z signals to generate a positive W signal.

FIG. 8a is a simple illustration of a two input EXCLUSIVE OR circuit, which is represented herein as shown in FIG. 8b. It should be understood that the EXCLUSIVE OR function with only two inputs is a test for oddness: that is, one and only one input must be present; if no inputs or two inputs are present, then there will be no output. Thus, an odd number of inputs are required. In the embodiment described herein, a term "EXCLUSIVE OR circuit" is utilized to mean a complex of EXCLUSIVE OR circuits which test for oddness and evenness of the inputs thereto. These may be actually manifested in two input EXCLUSIVE OR circuits as shown in FIG. 8a, or may be represented with EXCLUSIVE OR circuits actually responding to more inputs. To the extent that more than two inputs are shown, it can be assumed that a three input EXCLUSIVE OR circuit or a two input EXCLUSIVE OR circuit or combinations thereof are utilized in a well-known "tree" fashion so as to provide an EXCLUSIVE OR complex which gives an output whenever the inputs thereto are odd in number.

From the foregoing description, it can be seen that the presence of a plus or a minus signal has no significance in and of itself, due to the way in which a plus or minus signal may be utilized. For instance, when applied to a +AND circuit of a reset side of a latch as shown in FIG. 6a, it may be a NOT signal, as illustrated by the NOT G signal shown in FIG. 6b. Similarly, when applied to a resetting AND circuit such as the AND-circuit 3 in FIG. 4a, a -X signal really becomes an X signal in terms of its logical connotation as illustrated in FIG. 4b. Also, the minus signals applied to the circuit of FIG. 7a in fact are plus signals when the function of that circuit is considered to be an OR circuit. For that reason, the simplified showing of the present embodiment (such as illustrated in FIGS. 3b, 4b, 5b, 6b, 7b and 8b) do not consider whether a plus or minus signal may be generated at the source of a signal, or whether that signal may be generated in true or complement form, since such considerations have no bearing on the way in which the signal may be utilized. However, at the input to any particular circuit (such as the input to FIG. 6b) the affirmative or negative function which the signal represents does have logical connotation and is shown. To the extent that a "NOT SIGNAL" is required but not generated, it is implied that one with ordinary skill in the art could obtain the opposite phase thereof from the source of the "SIGNAL." This is illustrated, for instance, in FIGS. 3a and 3b where both phases are generated in 3a, and only the affirmative phase is generated in 3b, the complement thereto being implied.

6.0 BASIC BUS CONTROL UNIT

The BCU (bus control unit) acts as a buffering traffic control for data, address, control, and checking signals between the storage devices and the rest of the system. In this embodiment, the CPU (including the I unit, the IE unit, the BC unit, and the E unit) is considered to be a single device with respect to the accessing of storage, and it must share storage with the channels. Each of the I/O channels 1-6 has a priority rating corresponding to its number (1- 6), and the MC (maintenance channel, including panel keys and panel indicators) comprises a seventh, lowest-priority channel for storage reference purpose. In accessing storage, priority is determined as between channels, and then priority is determined between the selected channel and the CPU. Stated alternatively, the CPU may reference storage unless it is prevented from doing so by a prior outstanding request for an available storage device initiated from one of the channels; which one of the channels will be permitted to reference storage is determined independently by a channel priority circuit. For purposes of completeness and simplicity, the embodiment of a bus control unit described in this section does not include provisions for handling a large capacity storage, nor for the sharing of a single storage device by more than one data processing system. The BCU comprises three general portions, shown in FIG. 9, FIG. 10 and FIG. 11, and described in Sections 6.1, 6.2 and 6.3, respectively.

6.1 SELECTION CIRCUITS

FIG. 9 is a simplified functional block diagram of the selection circuits in which all of the blocks represent figures where circuit details are shown, and the blocks are referred to by figure number rather than by an arbitrary reference numeral. For instance, in the extreme upper left-hand corner of FIG. 9, a CH PRI (channel priority) circuit is shown in detail in FIG. 12 (described hereinafter), and the circuit is referred to in the description of FIG. 9 as the "channel priority circuit FIG. 12." Although not all interconnecting lines are shown in FIG. 9, the main control, data and address lines of the selection circuits are all shown. Reference should also be made to FIG. 55 which shows various channel/BCU connections.

6.1.1 CHANNEL PRIORITY FIG. 9

In the upper left-hand corner of FIG. 9 are shown the circuits which determine priority as between channels, including the channel priority circuit FIG. 12, the buffer circuit FIG. 13, the delay circuit FIG. 14, the BCU data request circuit FIG. 15, and the BCU response circuit FIG. 16.

The channel priority circuit FIG. 12 (CH PRI) assigns priority to the channels, channel 1 being first, channel 6 being next to last, and the maintenance channel having lowest priority. All the circuit does, is lock out any channel of lower priority once it has selected a channel of a given priority; selection of the particular channel is complete when a buffer circuit (BFR) FIG. 13 (which is a trigger) turns on, in response to there being a request for storage reference from a channel; in turning on, the buffer blocks further channel storage requests. Once the buffer is turned on, it will start a delay circuit (DLY) FIG. 14, which provides signals at different times to control the timing of the channel priority circuits. The outputs of the channel priority circuit FIG. 12, the buffer circuit FIG. 13, and the delay circuit FIG. 14 are each fed to a BCU data request circuit (DATA REQ) FIG. 15 and a BCU response circuit (BCU RSP) FIG. 16. Each of these circuits sends a corresponding signal back to the respective channel (the selected channel) to request data and one address from the channel; a signal on the CH ACC (channel accept) line indicating to the channel that the storage request from that channel has been honored. The data request signal and BCU response signal are identical except for timing.

In the BCU, it is desirable to reset the priority circuits as soon as possible so that the priority circuits will be available to do the initial contact work with a channel making a subsequent request currently being handled. However, it cannot be reset so soon as to preclude receiving address and data information from the channel which has just made a request. Therefore, a time is picked which is sufficiently early to permit the next channel to make a request as soon as possible, but which will cause the communication of the resetting of the priority circuit back to the channel to be sufficiently late so that, by the time the channel received this communication, its data and address information will have been accepted at the BCU and be participating in an actual storage access. The timing of this is controlled when the BCU RSP and BCU DATA REQ are sent to the channel, the timing of the reset itself being fixed with respect to the turning on of the buffer. Inasmuch as the response to each of these channels can be controlled with sufficient precision by utilizing the various outputs of the delay circuit (FIG. 14), the resetting of the priority circuit can be done in a fixed fashion without regard to the particular channel which has been accepted for a storage reference. This simplifies the priority resetting circuit.

The significance of the interrelation of the selection circuits, and features of importance with respect to various component circuits thereof are discussed in detail in Section 6.1.6, which follows the detailed introduction to each of the circuits.

6.1.1.1 Channel Priority Circuit FIG. 12

The channel priority circuit FIG. 12 comprises essentially a plurality of latches 1, each settable by a corresponding AND-circuit 2 in response to a setting signal from an AND-circuit 3 which is operated by a signal on the NOT BFR line from FIG. 13 (indicating the buffer trigger is not SET,) and by a running A clock (AR) from the I unit. A channel storage request can therefore be set into one of the latches 1 at A time following the presence of a signal on a corresponding channel storage request line provided the buffer has not yet been set. It is the setting of the buffer therefore that controls the admissibility of requests, and that therefore establishes the point in time when priority has been established. The output of the latches comprise tentative channel priority bits, channel 1 being automatically recognized (if its latch is SET) as the channel for which priority has been granted, due to the fact that there is no AND circuit in the output of the latch. However, each of the latches corresponding to the channels 2 through MC has an AND-circuit 4 which is blocked by the setting of any latch corresponding to a channel of higher priority. For instance, the output of the latch corresponding to channel 4 will be blocked by the related AND-circuit 4 unless an AND-circuit 5 provides a gating signal in response to the out-of-phase outputs (0) of the latches corresponding to channels 1, 2 and 3; in other words, in the event that any of the channels 1, 2 or 3 has set its latch, then the output of the latch for channel 4 will be blocked by a lack of a signal from the AND-circuit 5. Similarly, another AND-circuit 6 together with the output from the AND-circuit 5 controls the gating of the output of the latch corresponding to channel 6.

Each of the latches 1 is reset by an OR-circuit 8 which will operate in response to the system reset control (SRC) from the CPU or in response to an AND-circuit 9 which, due to a further AND-circuit 10, will operate in response to a signal on the DLY FULL line from FIG. 14 during a late B running clock signal (LBR line) whenever a channel will in fact access storage (during the following cycle) as indicated by a GATE CH gate channel signal on the line from FIG. 18. The output of the AND-circuit 10 comprises a priority reset which is also used to reset the BFR circuit of FIG. 13.

The signal on the PRI RST line is also used along with the signal on the DLY FULL line and a late B clock pulse on the LBR line to gate an AND-circuit 12 which is used to set a latch 13 which generates a channel accept signal on a CH ACC line, which comprises an indication that a request for storage reference by a channel has been accepted. Notice that this is directly responsive to signal on the GATE CH line, which signal cannot appear until a channel request for even or odd storage has been matched by an available even or odd storage, and a corresponding storage cycle has been initiated. The latch 13 is reset at the start of the next B time due to the application to the reset side of the latch of the signal on the LBR line. Also, the channel accept signal is essentially identical to the reset condition of the channel storage request latches 1 (in FIG. 9) except for the fact that it is latched throughout one cycle.

The outputs of the AND-circuits 4 comprise the respective channel priority bits which are utilized in setting the buffer (FIG. 13) and in causing the correct BCU data request or BCU response to be generated in FIG. 15 and FIG. 16, respectively.

Thus the channel priority circuit of FIG. 12 will be set at A time provided it has not previously been set so as to activate the buffer of FIG. 13, and will remain set until late B time in some cycle which follows the presence of a signal on the DLY FULL line from FIG. 14; when GATE CH will appear depends on when a correct storage unit becomes available, up to five machine cycles (1 ns.) later (see Section 6.1.2.2). As can be seen from a timing diagram FIG. 19, DLY FULL does not appear until about the middle of the fifth cycle of a sequence of cycles in which a storage request has been made for one of the channels. Thus, the latches, when set, will remain set until the BCU response and BCU data request from FIG. 15 and FIG. 16 can be sent to the selected channel; note however, that no other channel request will be honored because the buffer is on until the time when DLY FULL goes off after having reset the latches.

Note that running clocks are used in FIG. 12 since channel priority is not operated by single-cycle operation under control of the maintenance panel, but rather, whenever single-cycle operation should cause a channel response, the priority circuits can respond thereto in a normal fashion.

6.1.1.2 Buffer Circuit FIG. 13

The buffer circuit shown in FIG. 13 comprises essentially a trigger 1 which is set by an AND-circuit 2 at B time provided there is an output from an OR-circuit 4 in response to any one of the channel priority signals 1-MC on the CH PRI BITS lines from the channel priority circuit, FIG. 12.

The buffer will be set within a small fraction of a cycle of the setting of any of the storage request priority latches in FIG. 12. With the buffer set, no further setting of the latches in FIG. 12 can take place, and due to the priority control at the output of those latches, the circuit of FIG. 12 will settle down to pick a particular channel as the channel having priority. The buffer is reset by a signal on the priority reset line from FIG. 12, as described in Section 6.1.2, hereinbefore.

The buffer guarantees sliver-free (definite) operation when a request latch is only partially set. A storage request signal appearing at the end of an A time could cause a short pulse that might condition the AND-circuit 2, FIG. 12; but it might not suffice to fully latch the request latch. Gating for the buffer is developed a quarter cycle after the end of A time. During this quarter cycle interval of time, the request latch would definitely be in a stable state (off or on); therefore, a definite priority would be established.

6.1.1.3 Delay Circuit FIG. 14

The delay circuit of FIG. 14 comprises essentially a plurality of delay units 1, each having a delay of approximately 100 ns. which is equal to about one-half of a cycle. Each of these delay units can be of any known type, the function of each being to cause the output of the unit to follow the input of the unit after the half cycle of delay time has expired. In other words, the signal will present on the DLY 1 line 100 nanoseconds after a signal appears on the BFR line from FIG. 13, and this signal will be present until 100 nanoseconds after the time that the signal is no longer present on the BFR line.

The delay circuit is somewhat unique in the provision of a signal on a DLY 1 SET line in response to an AND-circuit 2 which is operative in response to the concurrent presence of a signal on the DLY 1 line and the BFR line. The purpose of the signal on the DLY 1 SET line is to provide a signal which goes on at the time of DLY 1 but goes off as soon as the BFR signal goes off, rather than waiting the delay period after the BFR signal goes off. The DLY 1 SET line is also applied to an AND-circuit 3 to assist in generating a signal on a DLY FULL line. The AND-circuit 3 is operative in response to the concurrent presence of signals on each of lines DLY 1 SET, and DLY 2 through DLY 6. The outputs of the delay circuit FIG. 14 are used in FIG. 12, FIG. 15, FIG. 16, and FIG. 17 to control the channel priority circuits in a manner that is described in detail with respect to the various figures.

6.1.1.4 BCU Data Request Circuit FIG. 15

The BCU data request circuit shown in FIG. 15 comprises a gate circuit to cause a selected channel to send data to the BCU. A DATA REQ signal is sent even though the channel may have requested a storage fetch operation to send data to channel, since the BCU does not know at this time whether a store or fetch operation has been requested by the channel. The gating of the data request circuit is somewhat complex, to account for the different timing characteristics of the channels (which result in part from their different locations with respect to the BCU). Specifically, a data request for channel 4-6 is initiated by a corresponding AND-circuit 1 as soon as there is a signal on the BFR line from FIG. 13. On the other hand, requests for channel 1-3 and the maintenance channel (MC) are not gated by corresponding AND-circuits 2 until a signal appears on the DLY 1 SET line, which signal requires both the BFR signal and the output of the first delay unit to be present. Additionally, data requests for channels 1-3 and the maintenance channel (MC) are lodged in corresponding latches 3 so that the signal will be available for a somewhat longer period of time; because CH 1-3 and MC are so close to BCU it is required to maintain their Data Request signals to insure a sufficient gating pulse will be generated to complete the transfer of store data from channel to the storage, unit (via the SBI LTH). Dropping data request (CH 1-3 and MC) with the turnoff of the BFR would definitely not be a sufficient gating signal for those channels remember (the closer the channel--the faster the reaction between BCU and channel). A second request could in fact be initiated and cause the operation of the signal lines if these latches were not maintained set during this period where a second setting could take place, and a reset immediately thereafter. This prevents an erroneous second setting of the latches which result from the same signal being present from these close-in channels.

The MC channels is reset by the (NOT DLY 2) (rather than the NOT DLY 1) because the MC channel is so very close to the BCU within the CPU section of the main frame that the double-setting condition is even more critical.

The BCU DATA REQ SIGNALS (1- MC) are sent to the channel where the signals are used to initiate the sending of data on the CH SBI (channel storage bus in), which occurs only if a store operation were initiated by the channel.

6.1.1.5 BCU Response FIG. 16

The BCU response circuit shown in FIG. 16 comprises, essentially, a plurality of AND-circuits 1 which gate corresponding channel priority bits from FIG. 12 as soon as a signal appears on the BFR line from FIG. 13. On the other hand, the BCU response signal to the MC channel is delayed, it being set 100 nanoseconds later in response to a signal on the DLY 1 SET line, from FIG. 14, and being reset 100 nanoseconds after the disappearance of the BFR signal due to the application of a signal on a NOT DLY 1 line from FIG. 14. Although not shown in FIG. 14, in accordance with the general principals upon which this description is based, it should be understood by those skilled in the art that the NOT DLY 1 line may be generated merely by inverting the DLY 1 line in any well-known fashion, and, in many circuit technologies, may be available as an incident to generating DLY 1. In other words, whenever there is a signal on the DLY 1 line in FIG. 14, there will be no signal on the NOT DLY 1 line in FIG. 16, and vice versa, all is well within the skill of the art.

Summarizing, a BCU RESPONSE SIGNAL is sent almost immediately to each of the channels 1-6, and after a 100 nanosecond delay is sent to the BCU RESP MC channel, in response to corresponding channel priority bits. The BCU response is a signal which indicates to the appropriate channel, that priority has been granted to that channel, and that it may now send address signals and other related signals to the BCU.

6.1.2 CHANNEL SELECTION, GENERALLY FIG. 9

Selection of a channel for communication with a storage unit is achieved by the channel request circuit FIG. 17 and the channel even/odd circuit FIG. 18 shown in FIG. 9. As described in preceding sections, one channel will be selected in dependence upon the priority of the channels making storage requests; from the particular selected channel, a signal will be received on an ADR VAL (address valid) line in the channel request circuit, and, providing that even or odd storage is not busy (in correspondence with the desire to select an even storage or an odd storage, respectively), a GATE CH signal is generated in response to the selecting of the even or odd storage as shown in FIG. 18 and described in detail in Section 6.1.2.2, hereinafter.

6.1.2.1 CHANNEL REQUEST CIRCUIT FIG. 17

The channel request circuit shown in FIG. 17 comprises a latch 1, which when set by an AND-circuit 2 will generate a signal on the CH REQ line for use in FIG. 18. The AND-circuit 2 in turn responds to a latch 3 which is set by an AND-circuit 4 at A time, (due to a signal on the AR line) provided there is a signal on the DLY FULL line from FIG. 14 and a signal on an ADR VAL line from the channel. In the embodiment herein described, the signal will never appear on the ADR VAL line until after the DLY FULL signal has already appeared, which means that use of the ADR VAL signal as an input to the AND-circuit 4 is redundant. However, if a different channel device were applied to the BCU here being described, it is possible that the delay characteristics of the channel configuration could be such that the DLY FULL signal could be available at a time earlier than when a correct address were being presented to the BCU by the channel; therefore, the ADR VAL signal being applied to the AND-circuit 4 renders this BCU more universal in its compatibility with channels of various designs. The use of the two latches 1,3 permits recognizing the time when a channel request can be effective in starting a storage operation even though the ADR VAL signal may come on at differing times (in dependence upon the characteristics of the particular channel to which priority has been assigned). The latch 1 can be set only 100 ns. after latch 3 is set, which means there is no possibility of latch 3 becoming set at the wrong time within a timing signal so as to cause noise or other questionable operation of the various circuits. In other words, by the time the latch 1 can be turned on by the BR clock pulse, latch 3 must have been set nearly 50 nanoseconds earlier, and therefore has had plenty of time to fully establish the set condition (in view of the fact that only approximately 10 nanoseconds are required for a latch to establish a definite steady state). The latch 1 is not only set at B time, but also will be reset at B time. This is another latch of the type wherein the setting condition has a shorter path than the resetting condition, and a tendency to set simultaneously with a tendency to reset will cause the latch to be set. The latch is reset upon the rise of the BR signal, and is set immediately thereafter (about 4 ns.). When the BR signal disappears however, it disappears more quickly from the reset input to the latch than it does from the set input of the latch, due to the fact that an additional logic circuit is in the set path. Thus, the BR signal will be effective at the set input to the latch for a sufficient length of time after the loss of the BR signal at the reset input of the latch so as to leave the latch in a set condition, provided the other input to the AND-circuit 2 is present. In this manner, the latch 1 is set at the start of B time and remains set until the start of the following B time. This is illustrated in FIG. 19, the channel priority and selection-timing diagram.

The latch 3 is reset by an OR-circuit 5 in response to the offside of still another latch 7 which is set by an AND-circuit 8 in response to the NOT BFR signal and a signal on the DLY 6 line. In operation, the latch 7 is reset when DLY 6 appears, and will be set (during DLY 6) as soon as NOT BFR appears. This conditions latch 7 to reset the latch 3 until the next NOT BFR time which causes the latch 7 to be set again. (See FIG. 19). It is to be noted that the clock pulses are RUNNING clock pulses (AR, BR) and the reset signal utilized to reset the latch 3 is a system reset control signal (SRC) indicating that these circuits are allowed to operate by themselves during diagnostic procedures wherein CPU reset controls and single cycling may be effective.

Concerning the ADR VAL signal, it should be noted this signal is received by the BCU from the channel to indicate that the channel has sent to the BCU a valid address and other related signals. The ADR VAL signal is therefore directly caused by the BCU RSP signal sent to the channel, which causes the channel to apply a valid address on the input lines to the BCU. Thus, in the chain of operation, one considers that a storage request from a channel will eventually result in a BCU response, causing the channel to send an address and an address valid signal, which then permits the channel request circuits to recognize a particular channel storage request and initiate the storage selection process.

6.1.2.2 Channel Even/Odd Selection FIG. 18

The channel even/odd selection circuit, shown in FIG. 18, determines that a valid channel request has been accepted for either an even or an odd storage unit and, when this is so, that the channel, rather than the CPU, is to be gated in various other circuits within the BCU, as indicated by the GATE CH (gate channel), NOT CPU BLK (block), CH OP (operation), and CPU OP, control signals which are utilized in the remainder of the circuits shown in block form in FIG. 9 and FIG. 10.

The channel even/odd circuits control the selection of an even or an odd storage in response to a signal on the CH REQ (request) line from FIG. 17 and a signal on a NOT CYC INH (cyclic inhibit) line from FIG. 28 described in Section 6.1.4.2, hereinafter.

The AND-circuit 1 is operative in response to a signal on an EVEN NOT BUSY line which is described in Section 6.1.4.2, hereinafter. However, AND-circuit 1 will not be able to respond unless the channel has indicated a desire to reference an even storage unit by virtue of the fact that the address has no bit in bit position 20, as indicated by a signal on a NOT CAB 20 (channel address bus, bit 20). The relationship of bit 20 to the addressing of storage is described in detail in Section 6.2.2, hereinafter, for now it suffices that, considering the highest ordered address bit to be bit zero and the lowest ordered bit of the address to be bit 23, (0,1,2....22,23) the storage units herein are not responsive to the lowest 3 bits (bits 21, 22, 23) since these tend to select only a particular fraction of a storage word, called a byte (eight bits); therefore, the lowest ordered bit to which the storage unit themselves are responsive, is bit 20. This bit has merely an even and odd significance; for instance, addressing of storage location 6 would require the same address bits as accessing of storage location 7, with the exception of the fact that bit 20 would be a ZERO if addressing location 6 and bit 20 would be a ONE if addressing location 7. The AND-circuit 2 responds in a fashion similar to AND-circuit 1 except that it is responsive to a signal on the ODD NOT BUSY line (indicating that the odd storage units are available) and a signal on the CAB 20 line (indicating, by a bit in address position 20 of the CAB, that the channel has requested access of an odd storage unit). The outputs of the AND-circuits 1, 2 comprise signals on the CH SEL EVEN line and the CH SEL ODD line, which signals are applied to FIG. 27 for purposes to be described in Section 6.1.4.2, hereinafter. Each of these signals is also applied to an OR-circuit 3 to generated a signal on the GATE CH line, which indicates that the channel (rather than the CPU) is referencing one of the storage devices. In the event that no channel selection has taken place, then an inverter 4 will generated a signal on a NOT GATE CH line, and an inverter 5 will generate a signal on a NOT CPU BLK line. The NOT CPU BLK line is utilized to permit gating of the CPU, and it is so named to emphasize the fact that the CPU will be blocked whenever the channel is selected, and otherwise, the storage units are considered to be available to the CPU. Stated alternatively, one could say that the CPU is presumed to be using the storage selection circuitry unless a channel has affirmatively taken control.

The GATE CH signal is also applied to an OR-circuit 6; the OR-circuit 6 will generated a signal on a CH OP line in response to the signal on the GATE CH line, or in response to a signal on the NOT INH (inhibit) line from FIG. 28, described in Section 6.1.4.2, hereinafter. The INH signal is present whenever any of the storage units has just been selected or when there is a need to prevent a storage request from being recognized due to the time synchronization in the BCU described in Section 6.1.4.2 (section explaining cyclic inhibit), hereinafter. An inverter 7 will generate a signal on the CPU OP line whenever there is no signal on the CH OP line; note that this is identical to the relationship between the GATE CH line and the NOT CPU BLK line.

Thus, the channel even/odd selection circuit of FIG. 18 will permit a recognized channel to select an even or odd storage unit provided that the even or odd unit, respectively, is not busy, and this is used to indicate that the channel is to be allowed access to the storage units, and the CPU is to be blocked therefrom. The use of these signals is developed more fully in the succeeding portions of this section (Section 7, relating to the basic BCU).

6.1.3 CPU SELECTION, GENERALLY FIG. 9

Referring to the block diagram of the selection circuits in FIG. 9, various store and fetch requests from the I unit and the E unit of the CPU will cause a CPU REQ (request) circuit FIG. 21 to send a CPU request signal to the CPU E/O (even/odd) circuit FIG. 22. The requesting portion of the CPU requests either an even or an odd storage unit, as indicated by the absence or presence, respectively, of the bit 20 output of the DUP SAR (duplicate storage address register) circuit FIG. 23. If the corresponding (odd or even) storage unit is not busy, as indicated by the not busy input from the even/odd busy circuit FIG. 28, then a valid CPU request is generated. However, if a channel request has been recognized by the CH E/O (channel even/odd) circuit FIG. 18, then the CPU E/O circuit FIG. 22 is blocked from operating. In other words, the channel-selection circuit FIG. 18 is free to operate notwithstanding the operation of the CPU, provided the correct even or odd storage unit is available; on the other hand, the CPU-selected circuit FIG. 22 is not free to operate whenever there has been a valid selection of storage by the channel.

6.1.3.1 CPU Request Circuit FIG. 21

In FIG. 21, a signal is generated on a CPU REQ line by a latch 1 which is set by an OR-circuit 2 in response to any one of three AND-circuits 3-5. The AND-circuit 3 is operated during single-cycle storage operations as indicated by a signal on the SINGLE CYC (cycle) line, concurrently with a signal on the SC STR (single-cycle store) line. Thus, during single-cycle diagnostic operations wherein the CPU is to store data, the AND-circuit 3 will initiate a CPU request. The AND-circuit 4 is operated by an OR-circuit 6 which responds to signals on any one of three CPU fetch lines: 1 FTCH 1, 1 FTCH 2, E FTCH REQ. The AND-circuit 5 is operative, during other than single-cycle operations (due to the necessity of a signal on the NOT SINGLE CYC line), to respond to an OR-circuit 7 which recognizes requests from the I unit or the E unit to store data, due to the signals on the I STR or E STR REQ lines. Each of the AND-circuits 3-5 is gated with a signal on a SET CPU REQ (request) line generated by an AND-circuit 8, which is operative at A time (due to a signal on the AC line), provided that a SCAN operation is not being performed (inverter 9), and further provided that no accept condition exists as indicated by the signal on the NOT ACC line. The NOT ACC line indicates that the CPU has not recently been granted access to storage, thus indicating that a CPU request, if honored by the BCU, will not interfere with any other previous CPU request. The development of this signal is discussed in Section 7.1.4.3, hereinafter.

The latch 1 is reset by an OR-circuit 10 in response to a signal on the AC line, to a signal on the SCAN line, or to a signal on a P-ACC RST (pulse accept reset) line (which is developed in FIG. 29) and which indicates generally that the need to block further CPU requests has passed, and that the CPU-selection circuits are therefore to be prepared for further requests). It is to be noted that the timing control for the CPU REQ circuit of FIG. 21 is an AC (controlled A clock) signal, which means that, during single-cycle diagnostic procedure, the CPU REQ circuit can be set or reset only when an active single cycle is generated by an operator.

In summation, a CPU REQ may be instituted by a single-cycle storage operation, by any CPU fetch operation, or by CPU store operations other than single cycle. Subsequent requests will be blocked and a current request is cut off when previous requests have set the accept latch, and are reset when the accept latch is reset.

The CPU request latch is gated with NOT ACC primarily for single-cycle operations, and also just to be sure, should there be a very long I fetch or E fetch or I or E store request, that as soon as the request has been honored as is indicated by an accept signal, this will block further passage of this long request through the OR-circuit 2 to the latch 1 so that this latch can be reset in a timely fashion. Note particularly that although NOT ACC is used to block the AND-circuits 3-5, P-ACC RST is used to reset the circuit since it will be running at all times. Thus in a single-cycle operation, as soon as the accept latch is set, a NOT ACC will disappear and block the AND circuits, thus cutting off a long single-cycle store request. However, the P-ACC set is controlled by a running clock pulse, and is therefore available throughout single-cycle operations, and permits the CPU request latch to be reset when in fact the work has been done.

Referring to the timing diagram of the P-ACC latch and the reset of the CPU request, notice that the CPU request latch will be reset at AC time in the third cycle during a nonsingle-cycle operation since the AC pulse will appear the second time and that each cycle is independent insofar as CPU requests are concerned. For instance, supposing a branch operation took place, the branch location having been fetched and now the branch + location is being fetched, but in the meantime it was learned that the branch was not successful and that therefore this was not desired. If the initial request had not been accepted due to busy storage units, then this lack of desire for the branch + 1 location will cause a termination of the I fetch which had requested storage and therefore on the next cycle the latch will not be again set so that it will remain reset, thus avoiding the necessity of taking this redundant storage cycle. Another example of the value of the CPU request reset circuit and set circuit combination is in an interrupt situation. It speeds the handling of the interrupt if a redundant and worthless CPU request which related to the program prior to interrupt is not required; thus, if a request has not been accepted prior to the time that the interrupt is effective, then it will not be accepted in the following cycle due to the fact that the request will have been removed and the latch is reset for a few nanoseconds of time. Therefore, this redundant storage cycle is avoided.

In FIG. 22, a signal is generated on a CPU SEL (Select) EVEN line by an AND-circuit 1, or a signal is generated on a CPU SEL ODD line by an AND-circuit 2, alternatively. Both of the AND-circuits 1,2 respond to a signal on the CPU REQ line, to a signal on a NOT CYC INH (not cyclic inhibit) line, to a signal on the NOT CPU BLK line, and to a signal on the NOT CDA (chained data access) line. The lack of a signal on the NOT CPU BLK line indicates that a channel storage selection has just taken place. The lack of a signal on the NOT CDA line indicates that, although the CPU might normally be able to take the next storage cycle, due to the queuing of chained data in a channel, the channel is operating at a high rate of speed, and has need for multiple rapid accesses of storage. The NOT CDA signal is generated by the offside of a latch 3 which is set by an AND-circuit 4, whenever a channel sends a signal on a CDA PRI (priority) line. The latch is set at the end of B time and reset at the start of the following B time. The BR signal is used since continuous control by the channel is required, even though the CPU may be single cycling.

The AND-circuit 1 will operate if there is a signal on the NOT DUP SAR 20 line (indicating a ZERO in the bit 20 position of the duplicate storage address register) concurrently with a signal on the EVEN NOT BUSY line from FIG. 28 (the same line which is fed to the AND-circuit 1 in FIG. 18). Similarly, the AND-circuit 2 will operate if there is a signal on the ODD NOT BUSY line and a signal on the DUP SAR 20 line (indicating a ONE in the bit 20 position of DUP SAR).

Inasmuch as the CH E/O circuit FIG. 18 controls whether the channel or the CPU will be allowed a storage request, the CPU E/O circuit shown in FIG. 22 is therefore much simpler. Thus, in addition to the CPU REQ and NOT CYC INH inputs to the AND-circuit 1 and 2, the CPU E/O circuit of FIG. 22 has other inputs (for which there are no counterpart inputs in the CH E/O circuit of FIG. 18 which relate to the channel usage of the storage circuits).

6.1.4 CH CPU SELECTION CIRCUITS, GENERALLY FIG. 9

The CH E/O circuit FIG. 18 and CPU E/O circuit FIG. 22 each feed the CPU CH SEL A/B E/O circuit FIG. 27. This circuit responds to some combination of either the channel or the CPU, with even or odd (only one of the four possible signals will be available), and matches this with the proper storage address information to determine whether storage 1AE, 1AO, 1BE, or 1BO is to be selected. In the addressing of the storage units, address bit 5 (sixth from highest-ordered) denotes either the lowest address storage frame (the storage frame containing storage units 1A EVEN and 1A ODD) or the high-address storage frame (storage units 1B EVEN and 1B ODD), in dependence upon the absence or presence, respectively, of address bit 5. This is so because bits 6 through 20 are effective to select a particular location from either storage frame, and bit 5 indicates either the low-address or the high-address storage frame; for instance, 16,384 words can be specified by an address comprising 14 bits, in binary form, the 14 bits comprising bits 6 through 19; as described hereinbefore, bit 20 permits selecting between the even and odd portion of a storage frame, thereby providing the ability to select any one word out of 32,768 words, the amount which is contained in any one storage frame, (storage 1A even and odd, or storage 1B even and odd). By adding an additional, high-order binary bit to the address, the number of addressable locations is doubled, granting access to 65,536 words, the amount which is within all four of the storage units within the two storage frames. As used herein, therefore, bit 5 is used to select between the high-order frame (1B) and the low-ordered frame (1A) as described above. Selection of one of the storage units by the CPU-channel select A/B-even/odd circuit FIG. 27 will cause either an even or odd busy trigger to be set in the even/odd busy circuit FIG. 28, which in turn generates a positive select signal in the circuit FIG. 28; positive select will cause cyclic inhibit and inhibit to be generated in the CYC INH-INH circuit FIG. 28. The absence of a cyclic inhibit signal together with a CPU select even signal or a CPU select odd signal will cause an accept and a pulse accept signal to be generated in the ACC circuit FIG. 29; this in turn causes CPU communicate and CPU busy signals to be generated in the CPU COM-BUSY circuit FIG. 30. Additionally, as before described, the INH circuit FIG. 28 and the GATE CH circuit FIG. 18 operate the CH OP/CPU OP circuit FIG. 18.

6.1.4.1 Channel--CPU Selection A/B-- Even/Odd FIG. 27

The storage selection circuit of FIG. 27 comprises a plurality of latches 1-4 which are set by corresponding OR-circuits 5-8 each of which is responsive to a corresponding CPU AND-circuit 9-12 or a corresponding Channel AND-circuit 13-16, respectively. Each of the AND-circuits 9-16 is gated by the output of a 50-ns. delay unit 17 (at about early B time), in response to an AND-circuit 18 responsive to a signal on the NOT CYC INH line from (FIG. 28) concurrently with a C running timing signal on the CR line. Each of the AND circuits must also be gated with a signal on a NOT NEG SEL line (described in this section, hereinafter). Otherwise, each AND-circuit 9-16 operates in response to a peculiar combination so as to select one of the storage units, a pair of AND circuits corresponding to each of the OR-circuits 5-8 comprising similar inputs for the CPU and for the channel, respectively. For instance, the latch 2 is set by the OR-circuit 6 in response to an AND-circuit 10 if there is a signal on the CPU SEL ODD line, provided that the low-addressed storage frame is being accessed as indicated by a signal on the NOT DUP SAR 5 line. This will cause accessing of storage unit 1AO. Alternatively, the OR-circuit 6 could be operated to access storage 1AO provided that there is a signal on the CH SEL ODD line and there is a signal on the NOT CAB 5 line (indicating that there is no bit in the sixth bit position of the channel address bus code configuration being presented to the BCU). The remaining ones of the circuits 9-16 operate in a similar, obvious manner, so that either the channel or the CPU will select any one of the four storage units: whether it is to be even or odd being determined by the channel even/odd circuit of FIG. 18 or the CPU even/odd circuit of FIG. 22, and whether it is to be in the low-address frame (storage 1A) or the high-address frame (storage 1B) being determined by bit 5 of the incoming address (either the SAR or the CAB in dependence upon the CPU or the channel, respectively, being granted permission to access storage). The permission to access storage is actually controlled at the channel even/odd circuit FIG. 18; if the channel does select even or odd, then the CPU is precluded from making a selection. The only thing that could preclude the channel from selecting the even or odd is that the appropriate storage unit (whether selected previously by CPU or by channel) is busy, or that the NOT NEG SEL signal is absent, as described hereinafter. The in-phase outputs of the latches are used directly as select signals within the BCU (in FIG. 28) to generate busy, positive select, and inhibit signals. The select signals are also applied to corresponding delay units 17-20 to generate select signals for actually operating the storage units, the amount of delay in each of the delay units 17-20 being dependent upon the actual physical layout of the respective storage units with respect to the BCU. The out-of-phase output of each of the latches is fed to an AND-circuit 21 which will generate the signal on the NOT NEG SEL line during a CR clock pulse when none of the latches have been set, which fact indicates that there is not a current selection already in progress and that therefore a selection can be made; alternatively speaking, the absence of the signal on the NOT NEG SEL line indicates that the selection circuit is currently busy, and no further request from either the CPU or the channel can be recognized by the circuit of FIG. 27 at that time.

The lack of NOT NEG SEL prevents a circuit race when the CPU REQ latch and CH REQ latch come on in the same cycle and storage is not busy; CPU is gated into FIG. 27. At early B time (delayed CR); and CH SEL is therefore blocked when it comes on at B time. Notice that the timing input to this circuit is a running clock pulse, CR; this is due to the fact that a channel operation may be involved, and as before described, should single-cycle operation of the CPU cause channel operation to service the CPU, the channel operation is handled in a normal fashion.

6.1.4.2 Busy, Positive Select And Inhibit Circuits FIG. 28

The circuit of FIG. 28 centers around latches 1, 2, 3 and 4 which are operated by signals on the SEL 1AO, SEL 1BO, SEL 1AE, and SEL 1BE lines, respectively, all from FIG. 27. Thus, one of the latches will be set in dependence upon whether an odd or even storage unit has been selected. The output of each latch is used to set a related latch 5, 6, 5a or 6a the offside of which comprise the ODD NOT BUSY line and the EVEN NOT BUSY line, respectively. Thus, when one of the latches 1, 2, 3 or 4 is set, the corresponding latch 5, 6, 5a or 6a is set so as to remove the corresponding not busy signal, thereby indicating that the related storage unit is busy and preventing the selection of the corresponding storage unit by either the channel even/odd circuit of FIG. 18 or the CPU even/odd circuit of FIG. 22, as the case may be. The output of the latches 1, 2, 3 and 4 are also supplied to an OR-circuit 7 which generates a signal on the POS SEL (positive select) line indicating that selection of a storage unit has, in fact, taken place. The POS SEL line is fed to an AND-circuit 8 where it is gated by a signal on a BR line to set a cyclic inhibit latch 9, thereby generating a signal on the CYC INH line. The latch 9 is set at B time, of any cycle within which one of the latches 1, 2, 3 or 4 has been set, so as to prevent any selection operation from taking place during the next 200 nanoseconds machine cycle. However, if there has been no storage accessing, so that none of the latches 1, 2, 3 or 4 has been set, then there will be no cyclic inhibit signal during that particular cycle. In other words, cyclic inhibit prescribes the use of one machine cycle per storage selection, once a storage selection has been initiated; it does not, however, prevent storage selection during any cycle when no storage selection has in fact, taken place during the last few cycles.

The output of the latches 1, 2 as well as the output of the latch 9, are all applied to an OR-circuit 10 to generate an inhibit signal on the INH line. This provides in effect, an early cyclic inhibit signal, since the effect of the OR-circuit 10 is allowed the inhibit to start sooner than, but end at the same time as, the cyclic inhibit signal.

The latches 1, 2, 3 and 4 are reset by the output of an OR-circuit 11 which responds either to an AND-circuit 11a due to an SR STET signal (system reset control STET), with an LBR or to an AND-circuit 11b which is operative at A time whenever there is a cyclic inhibit signal generated by the latch 9. The AND-circuit 11b causes the latches 1, 2 to be reset one cycle after they are set.

The latches 5, 6, 5a and 6a are left on for a longer time, and are caused to be reset by the actual response of a storage unit in the form of a signal on the advance lines: ADV 1 AO, ADV 1 BO, ADV 1 AE, or ADV 1 BE as the case may be. The advance line feed corresponding OR-circuits 12, 13 the outputs of which are delayed by respective delay units 14, 15, 14a and 15a and fed to corresponding OR-circuits 16, 17, 16a and 17a. The OR-circuits 16, 17, 16a and 17a provide a means for resetting the latches 5, 6, 5a and 6a in response to a signal on the SYS RST (system reset) line. The output of the OR-circuits 16, 17, 16a and 17a are also fed to another OR-circuit 18 which generates an advance W/Z signal (on the ADV W/Z line) for use in the E storage return circuit shown generally in the block diagram of FIG. 11. The advance W/Z signal is a signal which represents the fact that an advance has been received by the BCU from the storage units indicating that the storage units have performed the requested storage operation and the BCU can now respond thereto.

In summation, the first set of latches respond to the select signal, and remain on for less than one cycle, being reset at A time of the next cycle by the cyclic inhibit signal. The second set of latches record the setting of the first set of latches and remain set until the storage unit indicates the near completion of the storage cycle, four cycles. A positive select signal is generated when either of the latches 1, 2, 3 or 4 is set, and this in turn will cause a cyclic inhibit latch to generate a signal on the line. The combination of positive select and cyclic inhibit cause the inhibit signal; the use of all these signals is described in sections hereinafter.

6.1.4.3 Accept Circuit FIG. 29

The accept circuit shown in FIG. 29 comprises primarily a pair of latches 1, 2 the circuitry of each being identical to the other with the exception of the fact that circuitry related to latch 1 is operated under the control of a controlled clock pulse AC and the computer reset control CRC, whereas the latch 2 is operated by the running clock pulse AR and the system reset control SRC; both circuits respond to the running early B pulse. Thus, the signal on the accept line reflects single cycle operation and computer reset, whereas the signal on the P-ACC line does not reflect computer resets, but only system resets, and is not aware of single cycle operation due to the use of the running clock pulse.

An AND-circuit 3 responds to a signal on the NOT CYC INH line from FIG. 28 at early B time, due to the signal on the EBR line; a CR line is provided to AND-circuit 3 to precondition the circuit for fast response at early B time. This is done to alleviate any timing problems that could occur if the CPU even/odd circuits have slower response time than expected and therefore would require delaying the early B time. This could cause a slivered accept signal on a cycle in which storage was not selected. The output of the AND-circuit 3 is used to gate a pair of AND-circuits 4, 5 either of which may operate an OR-circuit 6. The AND-circuit 4 is operative if there is a signal on the CPU SEL EVEN line, and the AND-circuit 5 is operative when there is a signal on the CPU SEL ODD line. The output of the OR-circuit 6 will set the latches 7, 8 which correspond respectively to latches 1, 2. The output of the latches 7, 8 comprise the accept, and pulse accept signals; the remainder of the circuitry generates only the reset signals for the latches 7, 8. Each of the latches 1, 2 will be set at A time following the setting of the corresponding latch 7, 8 but the output of the latches 1, 2 will not be used until the following early B time. Therefore, each of the latches 7, 8 is reset near the start of early B time next following when the latch was set. It should be noted that the OR-circuit 6 which sets the latches 7, 8 will be operated by the AND-circuit 3, the critical timing of which is also early B time of one cycle, and then the related latches 1, 2 will be set at the following A time; this in turn causes the respective latches 7, 8 to be reset at the following early B time. The latches 7, 8 are therefore on for approximately one machine cycle (200 nanoseconds). The reason for the difference between accept and pulse accept is: during single-cycle operation the CPU would not be able to recognize an accept signal that was on for only 200 nsec. (one cycle). Single-cycle rate is controlled by a pushbutton. Thousands of storage selections can occur between two successive single cycles, yet the CPU has only made one request. Thus, the BCU resets accept under single-cycle control; this retains the fact that the selection has occurred.

6.1.4.4 CPU Communicate-- Busy Circuit FIG. 30

In FIG. 30, a pair of latches 1, 2 are set by corresponding AND-circuits 3, 4 to generate signals on a CPU COM (communicate) line and on a CPU STG BUSY (storage busy) line, respectively. The AND-circuit 3 is responsive to a signal on a P-ACC line at B time, and the AND-circuit 4 responds to an OR-circuit 5 so as to be operated by a signal on the P-ACC line at early B time (EBR). The OR-circuit 5 is also operated by the signal on the CPU COM line. The purpose of the signals generated in FIG. 30 are to indicate to the storage device that the CPU is the device being serviced, and to indicate to the CPU that it is busy with a storage operation, respectively. The latch 1 is set on the rise of the B clock pulse and remains set until the rise of the following B clock pulse; similarly, the latch 2 is set from the start of early B until the start of the next early B; both latches are set as soon as the P-ACC signal appears. The reason for using the OR-circuit 5 in setting the latch 2 is to bring up CPU STG BUSY within the same cycle in which ACC comes on and to maintain CPU STG BUSY one cycle after P-ACC goes off by means of the CPU COM latch 1.

6.1.5 STORAGE ADDRESS REGISTER FIG. 23

The storage address register shown in FIG. 23 comprises essentially a plurality of latches 1 each of which is set by a corresponding OR-circuit 2 response to either one of two respective AND-circuits 3, 4. Each of the AND-circuits 3, 4 responds to a signal on a SET SAR line generated by an OR-circuit 5 due to the presence of a signal on a SCAN GT TO SAR line or the output of an AND-circuit 6. The AND-circuit 6 is operative at A time in response to an OR-circuit 7 which in turn responds to a signal on a GT INCR TO SAR line or a signal on a GT AA TO SAR line. Thus, whenever the incrementer or the address adder are to be gated into the storage address register, the AND-circuit 6 will cause the AND-circuit 5 to do this at A time. On the other hand, the OR-circuit 5 will provide a gating signal to SAR whenever the SCAN GT TO SAR line has a signal thereon. The AND-circuits 3 are additionally gated by a signal on an INCR TO SAR line from an OR-circuit 8 which is responsive to either the SCAN GT TO SAR line or the GT INCR TO SAR line. The AND-circuits 4 are responsive to a signal on the GT AA TO SAR line.

Note that the source of bits for SAR are bits 0 through 23 of the INCR (the incrementer) or bits 8 through 31 of the AA (addressing adder). Only the low order 24 bits (bits 8 through 31) of the addressing adder output are required as addresses in this case. (See said illustrative environmental system in which the addressing adder is described for further details as to the bits of the addressing adder which are used to generate storage addresses.) The circuit of FIG. 23 also includes a duplicate storage address register (DUP SAR) which comprises only two latches 10, 11 each set by a corresponding OR-circuit 12, 13 in response to a pair of respective AND-circuits 14, 15. These circuits 10-15 are identical to the circuits above, and relate only to SAR bits 5 and 20, the OR-circuit 14, relating to SAR bit 5, being set by INCR 5, the OR-circuit 14, relating to SAR bit 20, being set by INCR 20; the AND-circuit 15, relating to SAR bit 5, being set by AA 13; and the AND-circuit 15, relating to SAR bit 20, being set by AA 28. The relationship between the AA bits and the INCR bits is the same in the DUP SAR as it is in the SAR, above.

The reason for having SAR and DUP SAR is that in the embodiment herein described, the SAR is physically remote from the DUP SAR (in roughly the same fashion as illustrated with respect to the block diagrams: the SAR appearing in FIG. 10 and the DUP SAR appearing in FIG. 9). As it happens, there is plenty of time to get the input bits to the SAR, but once SAR is set, the timing is rather critical insofar as using SAR bits in FIG. 9, whereby it is preferable to provide these SAR bits directly by means of a DUP SAR so that as soon as they are set therein, they are immediately available without circuit propagation time delays being involved.

6.1.6 SUMMATION OF SELECTION CIRCUITS

The selection circuits shown in the block diagram of FIG. 9 comprises essentially four portions. In the upper left-hand corner, the channel priority circuit FIG. 12 through FIG. 16 and channel request and selection circuits FIG. 17 and FIG. 18 will recognize a channel (the highest priority channel which has requested a storage reference) and generate a channel select even or odd signal. The second part of the selection circuit includes the CPU request and CPU select even/odd circuits of FIG. 21 and FIG. 22 which recognize fetch and store operations from different parts of the CPU and generate a CPU select even (or odd) signal. The third part of this circuit includes the CPU-channel select A/B--even/odd circuit FIG. 27 and its dependent circuit FIG. 28 which generates even/odd not busy, the positive select, the cyclic inhibit and the inhibit signals. These circuits respond to either a channel of a CPU selection of even or odd to select the proper storage frame (1A or 1B) and then generate signals indicative of the fact that a storage selection has been made. The final portion of FIG. 9 relates only to the CPU and includes the accept circuit of FIG. 29 which recognizes that a CPU selection has been made, and the CPU communicate and busy circuits which are merely timing variations of the accept signal.

The channel priority circuits, particularly the circuits of FIG. 12 and FIG. 13 are so arranged as to select one and only one channel, having highest priority, at the last possible minute. It is, for instance, possible for the priority circuits to have a channel-selection process started by one channel, with a channel request latch 1 (FIG. 12) latched for a first, lower priority channel, and later have the circuit taken over by a higher priority channel.

Assume that channel 6 has been attempting to make a storage reference but has been prevented from doing so by repetitive requests from channel 1. Eventually, at the end of the last channel 1 request, the priority reset will reset the circuits of FIG. 12 and FIG. 13. On the following A time, the presence of a not buffer signal will permit a signal on the AR line to cause the AND-circuit 3 to gate the latches 1. Thus the latch 1 corresponding to channel 6 will become set, and since no higher channels are set, there will be a channel 6 priority bit passed to the buffer circuit in FIG. 13. However, due to the AND-circuit 2 (FIG. 13) the buffer trigger 1 (FIG. 13) cannot be set until B time due to the presence of the BR line. If, during the remaining part of the AR clock pulse (which gates the circuits of FIG. 12, the channel 2 request line became activated, then the latch 1 (FIG. 12)) corresponding to channel 2 will become set. In this situation, there will therefore be two latches set, one for channel 2 and one for channel 6. However, as soon as channel 2 is set, the AND-circuit 5 (FIG. 12) will become blocked so that the AND-circuit 4 corresponding to channel 6 will become blocked and there will be no output on the channel 6 priority bit. By this time, however, the OR-circuit 4 (FIG. 13) is being gated by the channel 2 priority bit so that when B time arrives, a signal on the BR line will cause the AND-circuit 2 (FIG. 13) to set the buffer trigger latch 1 (FIG. 13).

Note further that the timing as between the latches of FIG. 12 and the buffer trigger of FIG. 13 is such that there is no possibility of attempting to set one of the latches 1 (FIG. 12) after the end of A time, and that there is approximately a 50 ns. delay between that time and the time that the buffer trigger 1 (FIG. 13) can be set by the OR-circuit 4 (FIG. 13) with a BR clock pulse. Thus, it is impossible for noise on the channel priority lines, or for a very late channel priority request which doesn't quite get one of the latches 1 (FIG. 12) fully established in a set condition, to cause the buffer trigger to be set. The buffer trigger will be set only if one of the latches 1 (FIG. 12) is definitely set. Once the buffer trigger 1 (FIG. 13) is set, no further request will be gated into the latches 1 (even though several subsequent AR timing signals will be received) since the AND-circuit 3 (FIG. 12) is blocked by the lack of a NOT BFR signal. This permits use of these priority circuits with channels which are capable of generating a storage reference request once in every microsecond, but which, except when operating at maximum speed on a cyclic basis, may request storage accesses on a completely random basis, completely asynchronously with respect to the BCU.

Thus, the channel priority circuits herein provide essentially first come-first serve priority for asynchronous circuits in a synchronous BCU, with last minute recognition of the highest priority request, all other request being blocked out during the period of time that a particular channel request is manifested so as to send signals back to the selected channel and thereby permit that channel only to communicate with the BCU for a storage reference.

Concerning CH/CPU switching

Referring to FIG. 19 the gate channel signal is latched and remains latched until there is a signal on the NOT INH line to generate the channel-op signal. Inhibit is essentially cyclic inhibit which has been speeded up by adding positive select to it. Stated otherwise, it is POS SELECT held up longer with cyclic inhibit.

The purpose of INH is to have it available to the CH OP latch (by not having the NOT INH) just prior to the time that CYC INH appears to block the channel select even/odd inputs (AND-circuits 9-16, FIG. 27). Thus INH controls the latch which generates CH OP and thereby permits the CH OP to be available for gating purposes later than GATE CH is available.

A storage cycle begins at B time in every case. When initiated by a channel, the storage cycle begins one machine cycle after the CH REQ latch (FIG. 18) is set; when the result of a CPU REQ latch, the storage cycle begins less than half a machine cycle after the CPU REQ latch is set. This means that there is more time in a channel-initiated sequence than there is in a CPU-initiated sequence, for switching all the circuits (See FIG. 9-FIG. 11) from channel to CPU, or vice versa; Therefore, the CPU is always gated in the absence of a recognized channel request. Whenever the CH REQ latch is set, it then switches all required circuits from the CPU to the channel. The time for this switching therefore falls within a channel selection operation rather than within the shorter CPU selection operation.

In FIG. 24, two types of CPU request cycles are illustrated. In the upper part of the figure, a request cycle made during single-cycle operations (maintenance-type operations wherein the operator depresses a key each time that an additional 200 ns. machine cycle is to occur.) Due to the relationship of the ACC (accept) and the P-ACC (pulse accept) circuitry of FIG. 29 (which controls the basic CPU request cycle as illustrated in FIG. 24,) a CPU request cycle requires two A controlled clock pulses, one to set the cycle and one to reset it; this is due to the fact that the CPU request latch (FIG. 21) is both gated (through the AND's 3-5 and the OR 2) and reset (through the OR 10) in response to an AND-circuit 8 which requires a controlled A clock pulse on an AC line. In the upper part of FIG. 24, it is assumed that a single cycle operation is taking place. Each time that a single-cycle switch is operated there will be one AC pulse. Therefore, a CPU request cycle during single-cycle operations will take up to several seconds to be completed. Contrariwise, during normal operations when the machine is running, there will be an AC signal during each machine cycle and therefore the CPU request cycle requires only two machine cycles (400 ns.).

One of the features of the present invention is the ability of the CPU request latch to avoid taking useless storage cycles when a branch or an interrupt causes a change in the operation of the machine such that a particular storage access is no longer needed (as indicated by the loss of an I FTCH 1, E STORE, or other input to FIG. 21). The CPU request latch is set and reset by an A controlled clock pulse. This is due to the fact that there is a longer circuit path to the set input from the AC signal than there is to the reset input; thus, when the AC signal first appears it will reset the latch, and there will be a blocking of the inputs for a span of 1 or 2 nanoseconds sufficiently to let the latch reset. After that, as soon as the circuit delays are used up, the inputs will again be gated to the latch and the setting will take precedence over the resetting so the latch will again become set.

The timing of the CPU request cycle (including the fact that during running operations the CPU request latch is reset momentarily at the start of each machine cycle) is shown in FIG. 24; however, the usefulness of this resetting action is illustrated most clearly in the top line of FIG. 26. In FIG. 26, it can be seen that the second and the fourth CPU requests are not honored immediately; were it not for the fact that the CPU request latch can be reset, at the start of each cycle, any CPU request which is manifested in the latch would eventually result in a storage reference, even though it may be many machine cycles later. Of course, it would be possible to take some fastion of a branch or an interrupt signal and from it develop an appropriate resetting signal for the CPU request latch. However, the usage of this particular circuit makes the CPU request latch capable of being reset upon branch or interrupt (due to the removal of the remaining inputs such as I fetch, E fetch, I store, etc.) without regard to what is occurring within the CPU. This makes the BCU more versatile, and for instance, lends its use in multiple-computer operations wherein more than one computer may be utilizing the particular BCU for referencing storage devices. Stated alternatively, upon branch of interrupt which causes a loss of the storage access request (I fetch 1, fetch 2, E fetch, I store or E store) the loss of these signals act as a reset for the CPU request without any particular other reset signal being required.

6.2 STORAGE INPUT CIRCUITS FIG. 10

The selection circuits described with respect to FIG. 9 provide controlling signals to the storage input circuits shown in FIG. 10. These signals include gate channel, not CPU block, channel-op. CPU-op, and cyclic inhibit. The remaining inputs shown in FIG. 10 are from the channels 1-6, from the PDU (which inputs comprise the maintenance channel and a control signal, ENABLE PKF), and from the various portions of the CPU.

The storage input circuits of FIG. 10 select from among the CPU and the channel inputs to provide input signals for storage, and to perform certain checking operations. The address from the CPU AA (address) and INCR (incrementer), and from the channel on the CAB (channel address bus), are combined in the SAR (storage address register) FIG. 23 and the address OR FIG. 31 to generate a single address to control storage on the SAB (storage address bus). The SAB is checked for proper parity count in the SAB ADR CHK (address check) circuit FIG. 33 and is checked to determine that the address specifies a storage location within the capacity of a particular system in the INV ADR (invalid address) circuit FIG. 34. If either circuit FIG. 33, FIG. 34 indicates an error, then a cancel condition will be generated by a CANC-PKF (cancel-panel key fetch) circuit FIG. 35. This circuit also is responsive to an operator's indication that panel keys are to be used as a source of data, as indicated by the presence of a signal on the ENABLE PKF line and by an address (from the MC). Under these conditions the CANC-PKF circuit FIG. 35 generates a signal on a PKF line which is returned to the PDU to control fetching data from the panel keys, and a signal on a CANC line to terminate a storage reference operation. The parity bits, on the SAB are adjusted and new bits generated in the PAR ADJ (parity adjust) circuit FIG. 35. This adjustment accounts for the fact that, although the system generally may specify as many storage locations as can be addressed with a 24-bit address, only 14 bits are actually used by storage herein, bits 6 through 19 of the channel and CPU address busses. Thus, the parity which obtains for the 24-bit address received at SAB has to be adjusted to reflect the 14-bit address sent to storage.

The address bit content of the SAB is also compared against panel address keys in an ADR COMP (address compare) circuit FIG. 37. This sends a signal back to the PDU indicating that there is, or is not, a comparison.

When data is to be stored in one of selected storage devices, STR (store) circuit FIG. 38 enables an SBIL (storage bus in latch) circuit FIG. 39 to select from the CH SBI (channel storage bus in) and the K REG (a register designated K, within the E unit of the CPU), to generate the correct data bits on the SBI (storage bus in) which supplies actual data to the storage devices for storage therein. The STR circuit FIG. 38 also supplies a signal on a STORE line to indicate to storage that it is to store data, rather than to fetch data from the designated address.

In the system described herein, it is possible to store a full 8-byte storage word or to store only one or more bytes (8 bits and parity each), selectively, the remainder of the storage word being regenerated (that is, the data stored prior to the storage operation is returned with the exception of the one or more new bytes being stored). More than one byte can be stored, the particular bytes to be stored being identified by MARKS. Depending on which unit is controlling storage at a given time, either the channel, the I unit, or the E unit marks are selected by the marks circuit FIG. 40 to provide correct marks to storage.

In the embodiment being described, every storage location may be protected from erroneous accessing (which would spoil the data therein) by means of storage protection keys which represent a four bit code combination used to identify different blocks of storage locations. A storage operation must therefore indicate a key which is correct for the block of locations within which storage is to be effected, or a storage address protection (SAP) error will be indicated.

The IN KEYS circuit FIG. 42 selects IN KEYS from the channel, or from any one of four locations in the I unit, to send the proper keys to the storage unit.

In summation, the storage input circuits of FIG. 10 select an address from the channel or the CPU, check the address, partly adjust it, and compare the address against panel keys (in response to the proper control signals). This circuit also provides to the storage unit: a store signal, and data to be stored, along with MARKS and IN KEYS, to control the storing of data.

The SAR FIG. 23 is described with respect to the selection circuits, in Section 6.1.4.4. The remaining circuits shown in FIG. 10 are described in succeeding sections, hereinafter.

6.2.1 ADDRESS OR FIG. 31

The address OR-circuit (ADR OR, FIG. 31), responds to the channel address bus (CAB) and to the storage address register (SAR) to generate a 24-bit address, with three parity bits, on the storage address bus (SAB). The circuit comprises essentially a plurality of OR-circuits 1 each settable by either one of two corresponding AND-circuits 2, 3. The AND-circuits 2 are operative when there is a signal on the GATE CH line from FIG. 18, and the AND-circuits 3 are operative whenever there is a signal on the NOT CPU BLK line (from FIG. 18). The SAB is indicated as going to the storage unit, (see the storage interface, FIG. 49) the parity adjust FIG. 36, the address compare FIG. 37, the invalid address FIG. 34 and the SAB address check FIG. 33. However, not all of the SAB bits are utilized by all of these circuits, as is described in the ensuing sections.

6.2.2 STORAGE ADDRESSING FIG. 32

Referring to FIG. 32, in the present embodiment, the 24 possible address bits are not all used, and some are used in different ways. The three lowest ordered bits specify only bytes of a storage word (eight bits each, there being eight such bytes in a storage word), bit 20 is used to select odd or even storage units; the sixth from highest ordered bits specifying whether the lowest address or the high-address storage frame is to be utilized, the highest ordered bit being utilized for panel key fetch; the remaining high order bits (second highest to fifth highest) specify storage locations not included in the system of the embodiment shown in FIG. 9 through FIG. 54. Thus, the address sent on the SAB to storage will contain only 14 bits.

6.2.3 SAB ADDRESS CHECK FIG. 33

Parity in this embodiment is adjusted so that there is an odd number of bits in any parity checked group, including the parity bit. For instance, in a binary group having a value of zero, the group would consist of ZEROs except for the parity bit, which is a ONE. The SAB address check circuit of FIG. 33 compares the various data bits and parity bits of the SAB, in groups; each group comprises eight data bits and a parity bit, which is called a "byte" in this embodiment. At the top of FIG. 33 is shown detailed circuits for the A section of parity byte 1 and details of how the A, B and C sections of parity byte 1 are combined so as to generate a signal on the EVEN PAR BYTE 1 line. At the bottom of FIG. 33 is represented in block form similar circuitry for EVEN PAR BYTE 2 and EVEN PAR BYTE 3.

Each of the bytes are divided into three groups (there being eight data bits and one parity bit, or a total of nine bits in each group). Since it is well known in the art that three-input AND circuits are readily obtainable, this provides a simple means of checking the storage address bus. An OR-circuit 1 is fed by any one of four AND-circuits 2-5 and various combinations of the SAB bits: 0, NOT 0, 1, NOT 1, 2, NOT 2. For instance the AND-circuit 2 will cause the OR-circuit 1 to generate a signal on the EVEN A line if there is no 0 bit no 1 bit and no 2 bit. The AND-circuit 3 responds to no 0 bit but the presence of a 1 bit and a 2 bit. The AND-circuit 4 responds to the lack of a 1 bit but the presence of a 0 and a 2 bit, and so forth. In similar fashion, OR-circuit 6 responds to any one of four AND-circuits 7-10 to generate a signal on an ODD A line. The AND-circuit 7 responds to the presence of only a 0 bit; AND-circuit 9 responds to the presence of only the 2 bit.

The outputs of the OR circuits 1, 6 and the similar outputs (EVEN B, ODD B, EVEN C, ODD C) are applied to a plurality of AND-circuits 11-14 which feed an OR-circuit 15. Again the combinations are such that if all are even, or if only one is even and the remaining ones are odd, then the OR-circuit 15 will generate the signal on the EVEN PAR BYTE 1 line. An OR-circuit 16 responds to EVEN PAR lines for BYTE 1, BYTE 2 and BYTE 3 to generate SAB address check signal on the SAB ADR CHK. Thus, if any one of the three parity groups in the 24-bit address has a total even parity including the parity bit, the OR-circuit 16 will generate an error-indicating signal on the SAB ADR CHK line.

6.2.4 INVALID ADDRESS FIG. 34

A signal is generated on an INV ADR line in FIG. 34 by an OR-circuit 1 in response to either of two other OR-circuits 2, 3; of course more or less OR circuits can be used to perform the ORing function of circuits 1, 2, and 3; This configuration is chosen to clearly illustrate the logical functions involved. The OR-circuit 2 responds to those bits in the storage address bus which relate to addresses corresponding to locations in excess of those available in the storage units of this particular embodiment. As described in Section 6.2.2, address bits 0-4 could only be utilized in addressing storage locations in excess of those provided in the present embodiment. Therefore, the presence of one of these bits indicates an attempt by the channel or the CPU to reach storage areas which do not exist. The possible exception to this is the use of storage bit 0 to designate the fetching of data from the panel data keys as indicated by a signal on the ENABLE PKF line, which is fed to an inverter 4 that feeds an AND-circuit 5. The presence of bit 0 in an address will therefore be recognized as an invalid address bit only if there is no ENABLE PFK signal present. Notice that bit 5 of the storage address bus can be taken as an invalid address bit if only one storage frame is used; in this embodiment, if storage units 1BO and 1BE were not available, then jumpering of the two points to connect SAB bit 5 with the OR-circuit 2 would permit recognizing bit 5 as an invalid address bit.

The OR-circuit 3 responds to any one of four AND-circuits 6-9 provided that there is present a corresponding signal on one of the select lines 1BE, 1BO, 1AE, 1AO, respectively, and a positive potential can be sensed at the other input thereto. A plurality of resistance elements 10-13 correspond to the AND-circuits 6-9, and are connected to the storage units by corresponding RDY (ready) lines. When any storage device is both operating properly and has not been indicated as being "off-line" (or inoperative) by a manual switch (which maintenance personnel may operate), then the RDY lines will be connected essentially to ground in the storage unit, thereby causing a potential drop across each of the resistors 10-13, so that the inputs to the AND-circuits 6-9 are too low to permit these AND-circuits to operate. However, should the positive potential in the storage unit fail, or should maintenance personnel operate a switch to take a storage unit off line, then the corresponding ready line will comprise essentially an open circuit, whereby the positive potential of the BCU supply is supplied directly, with little or no voltage drop, via one of the resistances 10-13, to a corresponding AND-circuit 6-9, thereby to operate the OR-circuit 3, and generate an invalid address signal on the INV ADR line. The purpose of the circuitry connected to OR-circuitry 3 is to not only recognize when a power supply of a storage device has failed, or when the storage device has been removed from service for maintenance purposes, but to do so utilizing the existing invalid address circuitry and permitting the usual type of interruption response from the particular occurrence.

6.2.5 CANCEL-- PANEL KEY FETCH FIG. 35

A signal on both a PFK (panel key fetch) line and on a CANCEL line is generated in FIG. 35 by a latch 1 which is set by an AND-circuit 2 at B time (BR line), and is reset at the start of the following B time. The AND-circuit 2 responds to a signal on the POS SEL line from FIG. 28 and to a signal from an OR-circuit 3. The OR-circuit 3 recognizes certain error conditions and also recognizes an operation involving the fetching of data from the panel keys under operator control. The OR-circuit 3 responds to a storage address bus address check signal on an SAB ADR CHK line from FIG. 33 and to a system reset control signal on an SRC line from the I unit, as well as to three AND-circuits 4-6. The AND-circuit 4 is operative in response to a computer reset control signal on a CRC line concurrently with the presence of a pulse accept signal on a P-ACC line; the AND-circuit 5 is responsive to a signal on the INV ADR address line from FIG. 34, provided there is a signal from inverter 7 indicating that there is no disable invalid signal on a DISABLE INV line from the control panel in the PDU. The disable invalid signal results from the operating of a switch which indicates that invalid addresses are not to be recognized as error conditions during maintenance operations of the system. The AND-circuit 6 responds to a signal on the ENABLE PKF line which signal indicates that a switch on the control panel has been operated to cause a fetching of data from the panel data keys, whenever there is a bit in the highest ordered position of the address, that is, SAB bit 0 . The latch 2 will be set during the time that the positive select signal is present (which is approximately a half of a cycle of time within which the odd or even select latches of FIG. 28 are set, as the case may be). Thus, if, for instance, the even storage unit had in fact been selected, but error in the storage address (or otherwise) were to show up in the circuit of FIG. 35, the latch 1 would be set at the following B time and would remain set for a cycle; this would send a cancel signal to each of the storage units, where the signal would be effective to cancel the storage requests. Also, should fetching of data from panel keys be indicated, then the latch may be set in response to the AND-circuit 6. Furthermore, during reset conditions (CRC, SRC) the latch will be set to cancel any storage requests which may have been initiated in a preceding cycle. Whenever panel key fetch is involved, the output of the latch 1 is sent to the SBOL (Storage bus out latch) which is illustrated in block form in FIG. 11, storage output circuits. This signal is used there to select data from the panel rather than from storage to be applied to the storage bus out, for use in the usual fashion by any of the storage return registers as is described hereinafter.

Notice that cancelling a storage request and the fetching of data from the panel keys in the PDU are inseparable. This is so because the CANCEL line and the PKF line are one and the same. This relationship promotes more sophisticated error checking, in that it prevents a data check condition from masking an invalid address condition. Whenever an invalid address is sensed in FIG. 34, it causes a signal on the CANCEL line (FIG. 35), which in turn cancels the storage if a fetch operation is involved, the SBO will be checked for proper parity; since no data is fetched (due to the cancel signal), the SBO will be all ZEROs, and a parity error signal would result. However, since cancel also calls for a fetching of the panel key data, panel key data with correct parity will be sensed instead of the "dead" storage SBO. The data is meaningless, but it is not used, due to the INV ADR error condition which causes an interrupt. Thus, PKF prevents an INV ADR error from being masked by a parity error. Furthermore, the CANCEL line, enables normal storage fetch request circuity circuitry to be used to initiate a PKF, without causing an erroneous storage operation. All other inputs to FIG. 35 (SAB ADR CHK, SRC, CRC) cause storage cancellations which are not affected one way or the other by PKF, and the logic is simplified by allowing the panel key data to be gated to SBO, since it will never be sensed.

Notice that a fetch of data from the panel keys is identified by the presence of address bit 0 (the highest ordered address bit, FIG. 32). The fetch will be allowed (by generating a signal on the CANCEL line, blocking the usual type of fetch) and the PKF line (to fetch the data from the panel keys) if the operator has indicated that the data keys are properly set by setting the enable PKF switch (see AND 6, FIG. 35). If there is no signal on the ENABLE PKF line, the circuit of FIG. 35 does nothing primarily, but since the INV ADR line will be active (See AND 5, FIG. 34) the CANCEL and PKF lines will be active due to the address bit 0 causing an invalid address designation.

6.2.6 PARITY ADJUST FIG. 36

Referring again to Section 6.2.2 (FIG. 32) the possible 24 bits of address which the channels and the CPU are capable of delivering are not useful to the two frames of storage comprising four storage units 1AO, 1AE, 1BO, 1BE. Therefore, only 14 bits of address are sent to storage, these comprising bits 6 through 19. Therefore, the parity bits, which relate to groups of data bits 0-7, 8-15, and 16-23 are no longer valid when the address is sent to the storage unit. For this reason, new parity bits which reflect the parity of the 14 useful address bits have to be provided. These new parity bits are generated in FIG. 36 by a plurality of EXCLUSIVE OR circuits 1-7. The EXCLUSIVE OR circuit 1 generates a signal for the line reflecting a first parity bit PA which relates to bits 6 through 12 of the useful address in response to the EXCLUSIVE OR circuits 2 and 3. The EXCLUSIVE OR circuit 3 generates a parity bit for bits 8 through 12 by subtracting from the parity of bits 8 through 15 (this is the original parity bit which accompanies the address on the SAB) the parity of bits 13 through 15, as determined by the EXCLUSIVE OR circuit 4. The EXCLUSIVE OR circuit 5 generates the second parity bit which relates to address bits 13 through 19, called PB. An EXCLUSIVE OR circuit 5 responds to the parity of bits 13 through 18 which is generated by the EXCLUSIVE OR circuit 6, the EXCLUSIVE OR circuit 6 taking the parity of bits 13 through 15 from EXCLUSIVE OR circuit 4 and taking the parity of bits 16 through 18 from the EXCLUSIVE OR circuit 7. EXCLUSIVE OR circuit 5 also takes into account the presence or absence of bit 19 so as to generate parity for bits 13 through 19. The parity bits PA, PB are the parity bits which accompany the useful address bits sent on the SAB to the storage units from the address OR-circuit of FIG. 31. These parity bits are used in the storage unit to check the received address to see that it has proper parity.

6.2.7 ADDRESS COMPARE FIG. 37

A signal is generated on an ADR COMP line in FIG. 37 by a latch 1 which is set by an AND-circuit 2 in response to another AND-circuit 3 whenever there is a signal on an ADR COMP STOP SW line from the PDU, which line indicates the operation of a switch to cause address comparison to take place. The AND-circuit 3 responds to a plurality of circuits such as the circuit 4a which includes an AND-circuit 5 responsive to the outputs of three inverters 6 which are fed by corresponding EXCLUSIVE OR circuits 7-9. If, for instance SAB bit 0 and address switch bit 0 (SW O) are both present, then the EXCLUSIVE OR circuit 7 will have no output so that the related inverter 6 will have an output applied to the AND-circuit 5. Similarly, if SAB bit 1 is absent and address switch bit 1 is absent then the EXCLUSIVE OR circuit 8 will have no output so that the related inverter 6 will supply a signal to the AND-circuit 5. If all three inputs are present at the AND-circuit 5 then there will be an input to the AND-circuit 3. If all of the other circuits 4 likewise supply signals to the AND-circuit 3, then this indicates that all of the bits compare identically with one another, so that the AND-circuit 2 will set the latch 1 and generate the address compare signal. The latch 1 is reset every B time by a signal on the BR line.

6.2.8 STORE CIRCUIT FIG. 38

The store circuit shown in FIG. 38 generates a signal on a STORE line by means of an OR-circuit 1 which responds to either of the AND-circuits 2, 3 that operate alternatively in dependence upon whether the channel or the CPU has requested the recognized storage operation. A signal on a CH STR line from a channel will operate the AND-circuit 3 provided there is a signal on the GATE CH line from FIG. 18. Alternatively, a signal on a CPU STR line will operate the AND-circuit 2 if there is a signal on the NOT CPU BLK line. The CPU STR line is activated by a latch 4 which is set by an OR-circuit 5 in response to a signal on either the I STR line from the I unit, or the E STR REQ line from the E unit. The output of the OR-circuit 5 is also applied to an AND-circuit 6 for setting a latch 7 whenever there is concurrently present a signal on a SINGLE CYC line from the PDU (indicating that single-cycle operation is being controlled by maintenance personnel) and a signal on the SET CPU REQ line which is also utilized in FIG. 21 to gate the setting of the CPU request latch. The latch 7 will cause an AND-circuit 8 to be operated at B time so as to set a latch 9, the output of which comprises a signal on the SC STR (single-cycle store) line. The latches 7 and 9 are reset by an OR-circuit 10 in response to an accept signal on the ACCEPT line or a system reset control on the SRC line. The SC STR line is used to initiate a CPU request during single-cycle operations. The CPU STR line is used in FIG. 40 to control the MARKS, as described in Section 6.2.1. The STR line is used in a variety of circuits as an indication that a store operation (rather than a fetch operation) is being performed and is used in the storage units to give data to be stored. This activates certain of the circuits used only on store operations, and causes the storage unit to store data rather than fetch it.

The latches 7 and 9 are used to "kill" one single-cycle time before setting the request latch. This is to insure data will be gated into the K REG before the storage unit is selected. (K REG is normally set one cycle after the request is made when it is under S/C control.) The accept signal is used to reset the latches 7, 9 since it appears for each CPU storage request, thereby clearing these latches so they may reflect the nature of current CPU operation.

6.2.9 STORAGE BUS IN LATCH FIG. 39

FIG. 39 is a fragmentary schematic block diagram of the SBIL (storage bus in latch) which selects data from the CPU or from the channel and causes it to be set into a plurality of latches 1, 2. Each latch is set by a corresponding OR-circuit 3, 4 in response to related AND-circuits 5, 6 and 7, 8, respectively. The AND-circuits operate in response to an early B timing signal (EBR line) and SBI control signal from latch 10. The latch 10 is set by an AND-circuit 11 in response to signals on the STR line from FIG. 38 and the CYC INH line from FIG. 28. The CYC INH line is also used as a reset for latch 10, so that the latch 10 will be set from the start of cyclic inhibit of a store operation to the start of cyclic inhibit for a following storage reference, a period of about two machine cycles (400 nanoseconds). This means, then, that the storage bus in latches 1, 2 will be set during the second cycle of a sequence of cycles within which a storage request has been recognized by the selection circuits of FIG. 9. The AND-circuits 5 and 8 are operated by a latch 12 which is set by an AND-circuit 13 in response to an AR timing pulse and a signal on the CH OP line from FIG. 18. If the latch is not set, then the AND-circuits 6 and 7 will be operated by the offside of the latch 12. Thus, the AND-circuits 5 and 8 may be affirmatively brought into operation by the latch 12 so as to gate the CH SBI BITS into the SBIL, otherwise bits from the K register (in the E unit of the CPU) will automatically be gated by the AND-circuits 6 and 7 (this action is referred to in Section 6.1.5, concerning CH/CPU switching).

Note that the input to the storage units is from the K register in the E unit; this is true, no matter what form of data is to be supplied to the storage units from the CPU.

6.2.10 MARKS CIRCUIT FIG. 40

The marks circuit comprises a plurality of OR-circuits 1, 2, 3 which correspond respectively to various ones of eight mark bits 0-7, 8-15,...56- 63 each of which is operated by either one of two corresponding AND-circuits: 4, 5; 6, 7; 8, 9. Each mark bit corresponds to a byte of data containing the identified parity bits; for instance, one mark bit relates to bits 0-7 of a storage word, one relates to bits 8-15 of a storage word, etc. Each of the AND-circuits 4, 6, 8 responds to a corresponding channel mark 0-7, 8-15,...56- 63, and to a signal on the CH OP line from FIG. 18. On the other hand, the AND-circuits 5, 7, 9 respond to a signal on the CPU OP line from FIG. 18 and to a corresponding latch 10, 11,...12, each of which is settable by a respective OR-circuit 13, 14,...15. The OR-circuits 13-15 are responsive to a first set of corresponding AND-circuits 16, 17,...18 which are operated by a signal on a VFL MK GT (gate) line which comes from the E unit. This line is energized during variable field length operations where one or more bytes of each storage word may be operated upon and a storage word containing one or more bytes of results must therefore be accompanied by marks to indicate which bytes of the storage word are to be stored. Each of the AND-circuits 16, 17,...18 is operated at A time by a signal on the AC (controlled A clock) line from the I unit. Each AND-circuit also responds to a signal on a corresponding VFL MK line 0-7, 8-15,...56- 63. These are the lines which indicate individual bytes (such as the byte containing bits 0-7, or 48-55, etc.) which are to be stored in variable-field-length operations. Each of the OR-circuits 13-15 also respond to a corresponding OR-circuit 19, 20,...21, responsive at A time to signals on corresponding SET MK lines 0-15,...48- 63. These lines are from the I unit, and cause the setting of two mark bits at a time in related pairs of bytes, said pairs of bytes being called syllables herein. Two mark bits are set because the I unit cannot store, on a byte-by-byte basis, except in multiples of two bytes. Thus, the marks circuit of FIG. 40 can respond to individual mark bits from the E unit in variable-field-length operations, to the I unit during store operations, or to channel mark bits during channel operations.

Each of the latches 10-12 is reset by signals on a line from an OR-circuit 22 which responds to a signal on a CPU RST line from the I unit, and to the output of an AND-circuit 23. The AND-circuit 23 is operative at A time (due to a signal on the AC line) concurrently with the output of an OR-circuit 24 which in turn responds to a signal on an IRPT RST (interrupt reset) line from the I unit, or to the output of a latch 25. The latch 25 is set by an AND-circuit 26 in response to the concurrent presence of a signal on the CPU STORE line from FIG. 38 and a signal on the ACCEPT line from FIG. 29. The latch will remain set throughout the duration of the signal on the ACCEPT line, and will then be reset. Thus, whenever a CPU store operation has been accepted by the BCU, the latch 25 will operate the OR-circuit 24 so that, during the next following A time, the AND-circuit 23 will operate the OR-circuit 22 to reset the latches 10-12. Otherwise, the latches will be reset during an interrupt reset or during a CPU reset. Note that there is no channel reset for the latches 10-12 due to the fact that channel marks are not lodged in the latches, but rather are applied directly to AND-circuits 4, 6,...8. The nature of the CPU reset and interrupt reset are discussed in more detail in said environmental system (see references).

The output of the AND-circuit 23, and the signal on the CPU RST line also feed an OR-circuit 27 which will set a mark-parity latch 28 to provide a signal on a mark-parity line (P) which is used in storage to check the validity of the mark bits, and which is also used to operate a bipolar latch 29. The OR-circuit 27 will thus generate a parity bit for the mark register whenever the mark register is itself reset. The OR-circuit 27 will also set latch 28 in response to an AND-circuit 30 which operates at A time (due to a signal on the AC line) in response to an EXCLUSIVE OR circuit 31 which will generate a signal provided there is only one of two inputs present. One input is the output of the bipolar latch 29, and the other input is a signal on the VFL UPDATE MARK PAR (parity) line from the E unit. The output of the mark-parity latch 27 is applied to an AND-circuit 32 which responds to the signal on the CPU OP line along with the AND-circuits which corresponds to the OR-circuits 1, 2, 3, the other input of which has an AND-circuit 35 which corresponds to the AND-circuits 4, 6, 8 and is operative to gate a signal on a CH MARK P (parity) line whenever there is a signal on the CH OP line. Thus, the mark circuit of FIG. 40 includes 8 mark bits, one corresponding to each byte of a storage word (such as the byte containing bits 0-7,) and a parity bit (P). The parity bit accompanying the channel marks is generated in the channel; the parity bit accompanying CPU marks is generated by the circuitry at the bottom of FIG. 40. Mark Parity Latch 28 is set so as to generate a mark parity bit whenever the mark register (latches 10, 11, 12) are reset. Thereafter, whenever variable-field-length operations are involved, successive bytes of a storage word may be operated upon during each successive cycle, a mark bit is sent to the mark register for each byte handled. For instance, a first cycle of operation may involve byte 0-7; when the mark bit for byte 0-7 is set into the latch 10 under control of the VFL MK GT line, there will also be a signal on the VFL UPDATE MARK PAR line (bottom of FIG. 40) which will cause the parity bit reflected at the output of the bipolar latch 29 to be reversed by the operation of the EXCLUSIVE OR circuit 31. Thus there will then be no output from the EXCLUSIVE OR circuit 31 and no input from the AND-circuit 30 through the OR-circuit 27 to again set the latch 28. The latch 28 is, however, reset at A time of each cycle. Thus, during that cycle when a mark bit for byte 0-7 is set into the latch 10, there will be no parity bit output from the latch 28. On the next cycle of operation, assume that there will be a mark bit for byte 8-15 set into the latch 11. Again, this is achieved by a signal on the VFL MK GT line which is accompanied by a signal on the VFL UPDATE MARK PAR line; the latch 28 is reset at the start of A time: at not A time, the bipolar trigger 29 will be gated to reflect the setting of the latch 28. In this case, the trigger 29 will be set so as to have no output, so that there will be an output from the EXCLUSIVE OR circuit 31 in response to the signal on the VFL UPDATE MARK PAR line. The output of the EXCLUSIVE OR circuit 31 will then pass through the AND-circuit 30 at A time so as to set the latch 28 thereby generating a parity bit. The output of the mark circuit is at this time, therefore, two mark bits (0-7, 8-15) and a parity bit (P). In a similar fashion, the latch is left reset in each odd cycle, and is left set in each even cycle, provided that a mark bit is in fact sent to the mark register latches 10, 11, 12. CPU parity for the mark bits is automatically supplied to the storage unit except when a channel operation is actually being performed. However, the CPU mark-parity-generating circuit (bottom of FIG. 40) will provide a parity bit whenever the storage could possibly do a checking of the mark lines (output to FIG. 40), because the mark parity will never be sampled except during a store operation which has been accepted by a storage unit. Therefore, it is only during reset adjunctive to storage operations or during accepted CPU store operations wherein mark parity must be adjusted as described above.

The bipolar trigger 29 is a trigger which will respond to the output of latch 28 whenever there is a signal on the NOT AC line, and the output of the circuit 29 will be the same as it was at the end of the last signal on the NOT AC line until the next signal appears. The details of such a circuit, and how it operates are disclosed in an article by O. J. Bedrij, "Gated Trigger With With Bi-Polar Set," IBM Technical Disclosure Bulletin, Vol. 2, No. 6 Apr., 1960, page 50 (copy in Patent Office Scientific Library).

Summarizing, the mark-parity circuit (bottom of FIG. 40) operates in accordance with a philosophy which causes a changing of the parity bit only when parity could possibly be changed, and otherwise ignoring conditions in the system in so far as this parity bit is concerned. Specifically, whenever the mark register is reset (such as at the start of any operation) the parity latch 28 is set so that together with no mark bits there will be an odd number of bits including the parity bit. Thereafter, if the mark register is set by the I unit, the parity bit is not changed because the I unit supplies multiples of two mark bits at a time due to the fact that the I unit stores only syllables or multiples of syllables at any one time. See the Table of Contents for an appropriate section describing the reasons therefore.

During VFL operations, where streams of bytes are operated upon, the parity register may have a sequence of marks set therein, one mark at a time, on successive cycles, in preparation for storing all or part of storage word containing one or more bytes to be stored. The condition of the parity register 28 is sampled at not A time, and if it is set, it will cause the bipolar trigger 29 to be set. Whenever a mark is sent to the register by the VFL circuits, the output of the bipolar trigger 29 is sampled at the EXCLUSIVE OR circuit 31. Regardless of the setting of the trigger 29, the EXCLUSIVE OR circuit 31 will cause the opposite signal to pass through an AND-circuit 30 to set the latch 28 into the opposite condition. The way the latch 28 is set is in fact by resetting it and again setting it each time that it should be set, or leaving it in the reset condition each time that it should not be again set. Thus, at A time, the output of the EXCLUSIVE OR can be put into the latch 28, and at not A time, the setting of the latch 28 will be passed along to the bipolar trigger 29. The latch 28 operates essentially in the same fashion as the CPU request latch in FIG. 21 described hereinbefore. That is, being reset each cycle, and again set if the input so indicates or not again set if the input so indicates, alternatively. Thus, correct mark parity is available essentially immediately (at A time), so that storage is not held up.

6.2.11 IN KEYS CIRCUIT FIG. 42

As is described in detail in said System/360 Manual, storage protection may be provided to be sure that no block of storage is accessed erroneously by any particular operation of the CPU. To identify storage locations to which the CPU and the channels should be allowed to provide storage information, a set of four keys is used. Various coded combinations of the keys correspond to respective blocks of memory locations. In order for a store operation to be permitted in a particular block, a set of IN KEYS must accompany the storage request, and these KEYS must match those of the block within which the storage location being accessed is located. However, if the IN KEYS are each zero (forming a key combination of 0000), then any block of storage locations will be accessible at that time. Also, any storage location having a KEY designation of 0000 may be accessed by any KEY combination. The IN KEYS circuit of FIG. 42 selects a set of CPU IN KEYS from two sources within the CPU and then selects between the set of CPU IN KEYS and a set of channel IN KEYS to provide IN KEYS to storage.

In FIG. 42c, the various CPU IN KEYS 1-4, P are generated by corresponding OR-circuits 1, 2, each responsive to either one of two related AND-circuits 3, 4 and 5, 6 depending upon the source within the CPU of the IN KEYS. A signal on an IN KEY line signifies when an operation directly involved in manipulating the storage keys is being performed. Such an operation might be changing the key designation of a storage block in memory. A signal on a SET or INHIBIT KEYS line will operate an OR-circuit 7, the output of which is passed through an inverter 8 to generate a signal for application to the AND-circuits 4 and 6. Thus, whenever manipulation of the keys is not involved, or there is not an interrupt to inhibit the use of keys, the AND-circuits 4 and 6 will gate the key bit signals from the PSW IN KEYS lines 1-4, P. This is to cause storage protection action under control of the program status word (see said System/360 Manual). On the other hand, if a key manipulation operation is being performed, or there is an interrupt, the inverter 8 will supply NO signal to the AND-circuits 4, 6 therefore not gating PSW KEY bit signals through to the OR-circuits 1, 2.

During key operations, a signal on the SET or INSERT KEYS line will cause AND circuits 6, 5 to operate and to gate signals on the R1 IN KEYS lines 1-4, P through to the OR-circuits 1 and 2 so as to supply signals corresponding CPU IN KEYS lines.

Selection is made between CPU in keys and channel in keys in FIG. 42d. The signals on the IN KEYS lines 1-4, P are generated by corresponding OR-circuits 10, 11, each operative in response to either one of a pair of related AND-circuits 12, 13 and 14, 15. The AND-circuits 12 and 15 are responsive to the signal on the CPU OP line from FIG. 18 to gate the signals on CPU IN KEYS lines 1-4, P from FIG. 42c, and the AND-circuits 13, 14 are responsive to a signal on the CH OP line from FIG. 18 to gate signals on the CH IN KEYS lines 1-4, P. Thus, the signals on the IN KEYS lines will reflect either the channel in keys or the CPU in keys in dependence upon there being a channel operation or a CPU operation in progress, respectively.

The source of the R1 in keys and PSW in keys is FIG. 42A and 42B, which derive these keys from the IOP register and the PSW register in the I unit, respectively.

The signals on the R1 in keys lines 1-4, P in FIG. 42a are developed from bits 8 through 15 and the accompanying parity bit of the I OP register in the I unit. This is so because keys which are to be inserted in storage units to assume control thereof are found in the R1 register section of the I OP register and this includes bits 8-11 of the I OP register. In FIG. 42a, the effect of the R2-X register portion of the I OP register on the parity bit P is subtracted from the parity bit by means of an EXCLUSIVE OR circuit 16 which responds to the parity bit P 8-15 and to an EXCLUSIVE OR circuit 17 which is driven by a pair of EXCLUSIVE OR circuits l8, 19. Thus, if I OP bits 12 and 13 are both present, there will be no output from the EXCLUSIVE OR circuit 18; on the other hand if bit 14 is present, but bit 15 is not present, there will be an output from the EXCLUSIVE OR circuit 19, thus providing between them (18, 19) one input only to the EXCLUSIVE OR circuit 17, so that the EXCLUSIVE OR circuit 17 will provide an input to the EXCLUSIVE OR circuit 16; this indicates that bits 12-15 have an odd parity count, and that therefore the state of the parity bit p 8-15 (regardless of what it was) must be reversed by the EXCLUSIVE OR circuit 16. Thus if there had originally been a parity bit P 8-15 due to the fact that the total number of bits (8-15 ) was an even number, there would therefore be two inputs present to the EXCLUSIVE OR circuit 16 and so no parity bit P would be generated thereby. Other situations would achieve corresponding results.

In FIG. 42b signals are developed on PSW IN KEYS lines 1-4 by corresponding signals on PSW bits lines 8-11 because the key which actually controls whether or not a reference to memory is to be permitted, is stored in bits 8-11 of the PSW register (in the I unit). As before, the remaining bits of the parity-checked byte (BITS 12-15) and the parity bit are also received in the BCU so as to adjust the parity bit as described with reference to FIG. 42a.

6.3 STORAGE OUTPUT CIRCUITS (FIG. 11)

The storage output circuits shown in FIG. 11 respond to control signals from FIG. 9 and FIG. 10 and to outputs from the storage units and from the PDU to recognize error signals, and to return data from storage to the proper requesting locations.

Very briefly, this is achieved by the X/Y-W/Z circuits and the advance circuits FIG. 44, FIG. 45, FIG. 46 and FIG. 47 which keep track of a requesting unit with respect to returning data, and error conditions resulting from checks performed within storage itself are handled by the SAP (Storage Address Protection) circuit FIG. 48 (which operates in response to a mismatch of storage keys) the STG DATA CHK (Storage Data Check) circuit FIG. 49, and the STR ADR CHK (Storage Address Check) circuit FIG. 50. In addition, the X/Y-W/Z trigger synchronization is checked by the X-W, Y-Z CHK circuit FIG. 51. In the event of an error output from any of the circuits FIG. 49, FIG. 50, FIG. 51, a BCU STP CLK circuit FIG. 52 will indicate to the I unit that the BCU has an error which should stop the timing clock.

In addition, keys fetched from storage pass through the OUT KEYS circuit FIG. 53: additionally, data from the panel data keys as well as data fetched from storage will pass through the SBOL (storage bus out latch) FIG. 54. The details of the circuitry of FIG. 11 are described in succeeding sections.

6.3.1 RETURN ADDRESS TIMING FIG. 43

In FIG. 43, three fetches of data are illustrated and are denoted j, k, l and m. Because of the operation of the cyclic inhibit (which is generated in FIG. 28 and described with reference to the timing diagram of FIG. 19 and FIG. 24) a storage fetch request (such as j) can be made, followed two cycles later by a second storage fetch request (such as k); thereafter, two cycles must intervene before the next storage fetch (such as l) can take place, and then that fetch may be followed after only one cycle by a further storage fetch (such as m). As the fetch request for k is being made, the storage will be indicating to the BCU that the data requested for j is returning to the BCU. It is therefore essential to keep track of which data belongs with which request. The circuitry of FIG. 44, FIG. 47 accommodate this "keeping track."

In FIG. 43, the first select signal takes place in the second machine cycle. Assume, arbitrarily, that the XY trigger was set at X at the start of the operation. Thus the j-storage fetch is associated with the X-side of the X/Y-trigger. On the fourth machine cycle a fetch request k is recognized as indicated by the select signal in the fourth cycle. Note that by this time, the X/Y trigger has been set to Y (as a direct result of the select signal which denotes the request 4). At the end of the fourth cycle, the storage device has sent back an advance signal as indicated by the SBO ADV signal J (on 5th cycle). Thus although the k storage reference is being made during this cycle, the j storage reference will be handled by the W trigger, during the next cycle (5th cycle).

After a delay following the k select signal in the fourth cycle, the X/Y trigger is flipped back to X (in the fifth cycle). Thus the 1 storage reference, as indicated by the SEL signal in the seventh cycle, will be associated with the X trigger.

Midway in the sixth cycle, the W/Z trigger is flipped to Z after a delay from the SBO ADV signal, and so forth. The X-trigger causes a return address (that is an indication of the particular register associated with the fetch) to be stored in an X register. After the X/Y trigger is changed to Y, the next storage request will therefore have information relating to the particular unit which requested the storage fetch stored in a similar Y register.

The W/Z trigger is arranged so that when set to W, it will cause the advance circuit to recognize the setting in the X register, and when set to Z it will cause the advance circuit to recognize the setting in the Y register. Since the X/Y trigger is switched back and forth upon the occurrence of each select signal, this means that every time a storage reference is made, the X/Y trigger will be changed from one state (X or Y) to the other state (Y or X).

Note that even on store operations, where no return data comes from the storage unit, there is still an advance signal which is used to steer addresses, invalid address indications, storage address protection indications and data check indications; there is always an advance signal suitable for switching the W/Z register, so that if store and fetch operations are intermingled, the X/Y-W/Z synchronization will not be lost.

6.3.2 X/Y-- W/Z TRIGGERS FIG. 44

The X/Y- and W/Z-binary triggers are identical, they provide a change in the output each time that there is a corresponding input signal. For instance, the X/Y binary trigger shown in FIG. 44 will switch from X to Y the first time that a POS SEL signal on the POS SEL line causes a delay unit 1 to provide an input signal to the trigger; thereafter, the next time a signal appears on the POS SEL line so as to cause the delay unit 1 to provide an input to the trigger, the output of the trigger will switch from Y back to X. The W/Z trigger operates in the same fashion except that a delay unit 2 is responsive to an advance on an ADV W/Z line from FIG. 28, said signal being itself delayed from the advance signals from the storage units. The X/Y and W/Z binary triggers are identical to the triggers shown in FIG. 38 and FIG. 39, and described in Section 11b of a copending application, Ser. No. 332,648 filed Dec. 23, 1963, now U.S. Pat. No. 3,270,325, entitled "Parallel Memory, Multiple Processing, Variable Word Length Computer," R. S. Carter and W. R. Welz, assigned to the same Assignee as this patent application. In order to connect the circuit of FIG. 27 in said copending application so as to utilize it as an X/Y or a W/Z trigger herein, the input applied to blocks 2 and 5 in said copending application would be from the delay unit 1 or the delay unit 2 (as the case may be) as shown in FIG. 44 herein, rather than from the AND circuit FIG. 603 in said copending application. Also, rather than being reset as shown in said copending application, the signal on the SRC line as shown in FIG. 44 would be connected to the various blocks.

Whenever a signal appears on the SRC line, this automatically resets the triggers so that X and W are both set, and on the first activation of either trigger, the trigger will switch from X to Y, and from W to Z, respectively. Notice that it is immaterial to the circuits of FIG. 45-FIG. 47 whether the X and W lines are first activated, or whether the Y and Z lines are first activated; this is so because the X register and Y register are identical, and each of them has an identical circuit input in each of the other circuits FIG. 47-FIG. 51 which utilize the X/Y triggers.

6.3.2.1 X and Y Registers FIG. 45 and FIG. 46

The Y register shown in FIG. 46 is identical in all respects to the X register shown in FIG. 45 with the exception of the fact that it is gated by a Y signal rather than by an X signal and the outputs are oriented with respect to the Y register rather than with the X register.

The X register shown in FIG. 45 comprises essentially six latches 1-6, each respectively corresponding to either a destination for data returning from storage or to a condition which is being gated through the X register due to its relationship to a particular storage operation (in the same fashion that returning data relates to a particular storage operation). Each of the latches 1, 2, 3 and 5 are settable by a corresponding OR-circuit 7-10 which responds to either one of two AND-circuits 11, 12; 13, 14; 15, 16; 17, 18. The AND-circuits 12, 14, 16 and 18 are responsive to a signal on a NON CPU SET line which is generated by an AND-circuit 20 in response to signals on POS SEL and NOT P-ACC lines. Whenever there is a signal on NOT P-ACC line, this means that there has not been a CPU storage request recognized which is outstanding. This, in effect, is the same as saying that there has been a maintenance channel fetch or a fetch from the channels 1-6. On the other hand, the circuits 11, 13, 15 and 17 respond to a signal on a CPU SET line from an AND-circuit 22 which responds to signals on the POS SEL and P-ACC lines (as does the AND-circuit 20) and also responds to a signal on a NOT STR line from FIG. 38 (shown in the storage input circuit block diagram of FIG. 10). In addition, the latch 4 responds to a signal from an AND-circuit 24 which is responsive to the NON CPU SET line, and the latch is responsive to an AND-circuit 26 which responds to the CPU SET line. All of the AND-circuits 11-18, 24 and 26 are responsive to a gating signal generated by an OR-circuit 27 in response to either a signal on the SRC line or to the output of an AND-circuit 28. The AND-circuit 28 responds to a signal on the X line from the X/Y trigger of FIG. 44 along with a signal on the POS SEL line and a B running clock signal (on the BR line).

The latches 1, 2 are set when data passing through the X register is to be returned to the A and/or B registers in the I unit. The A and B registers are used to temporarily store instructions fetched from storage. Each register is capable of holding a full storage word (a double word as defined hereinbefore) of 64 bits of data and eight parity bits. The A register is used to store data returning from an even storage unit, and the B register is used to store data returning from an odd storage unit. The AND-circuits 11 and 13 are both operated by a signal on an IC RET AB (CPU return to A or B registers) line. This line is brought up within the I unit whenever an instruction fetch is made so as to indicate the BCU, and most particularly to the X-, Y-registers that the data being fetched is instruction data, and is to be returned to either the A or B registers in dependence upon whether an even or an odd address, respectively, were used in accessing the instruction. Thus, the selection between latch 1 and latch 2 via the AND-circuit 11 and 13 is based on whether or not there is a ONE in the bit 20 position of the storage address bus. A signal on the NOT SAB 20 line to AND-circuit 11 will cause AND-circuit 11 rather than AND-circuit 13 to operate, and conversely, a ONE in bit position 20 of the storage address bus will cause a signal to be present on the SAB 20 line which feeds AND-circuit 13. The other inputs to the latches 1, 2 are from the MC channel in the PDU. In case a double word of data (64 data bits plus eight parity bits) is being returned on the maintenance channel, an MC RTN AB signal will cause both the AND-circuits 12, 14 to set the latches 1, 2, so that there will be developed an X-A and X-B signal at the output thereof to cause this data to be stored in both the A register and the B register simultaneously.

The latch 3 is operated in essentially the same fashion as the latches 1, 2 with the exception of the fact that, since it represents but a single register, no address bit information is required (such as SAB 20) into the AND-circuits 15, 16. Since all noninstruction data which is fetched for the CPU (with the exception of maintenance operations) returns to the J register in the E unit, the I unit always causes noninstruction fetches to send a signal on the CPU RTN J (CPU requests return to J register) line. If on the other hand, certain maintenance operations (see Table of Contents) are being performed, a signal will be developed on an MC RTN J (maintenance channel return to J register) line to the AND-circuit 16.

The latch 5 is similar to the latch 3 in its operation with the exception of the fact that a single-gating line will operate the latch regardless of whether the NON CPU set line or the CPU SET line has the controlling gating signal thereon. In this case, it is not a return address control signal that energizes one of the AND-circuits 17, 18; rather, it is the fact that an invalid address has been sensed by one of the storage units; the effect of this invalid address is properly oriented with respect to the particular storage access which caused it, by gating it through the X or the Y register, as the case may be. The function of the latch 5 is not so much to orient the invalid address signal with respect to a particular circuit, but rather to gate it through at the proper time so that it will be returning to several circuits simultaneously but at a time when the data which would otherwise have been fetched (had there not been an invalid address) would be returning to the particular location. This is discussed in more detail in Section 6.3.2.2 with respect to the advance circuit of FIG. 47.

The latch 4 is operated by an AND-circuit 24 in response to the signal on the NON-CPU set line from the AND-circuit 20. In other words, the latch 4 will be set in all NON CPU cases, even though it may be either a maintenance channel operation or an actual channel request which is associated with a particular storage request that is using the X-register. Even in store operations, the latch 4 will be operated so as to provide a signal to steer address error, data errors or storage address protection indications to the channel. During maintenance operations which would operate the AND-circuits 12, 16, and 18 the AND-circuit 24 will also be operated; this is so because of the fact that data may be returned to the channel even though fetched for a maintenance channel operation, without interfering with channel operation since there will be no particular channel request outstanding to gate data into any one of the channels.

The latch 6 recognizes a special situation when the CPU is involved in a diagnostic fetch operation, and, as is described in Section 6.3.2.2 with respect to the advance circuit FIG. 47, this latch contributes to the generation of a diagnostic select signal indicative of the fact that a diagnostic reference to storage has taken place.

6.3.2.2 X/Y Advance Circuit FIG. 47.

"Advance" as used in the bus control unit means a signal indicating that storage has reached a near-completion point in either a store or a fetch cycle. Stated alternatively, advance comprises an input gate signal for a register with respect to data which has come from storage or errors related thereto. The advance signal, of course, denotes a point in a storage cycle of operation which can be recognized as a point where data is or will be (within a known increment of time) available to the requesting unit.

In FIG. 47 a plurality of OR-circuits 1-7 each generate a respective advance signal, each one corresponding to the output of either the X register or the Y register as selected by a signal from W or Z side of the W/Z trigger of FIG. 44. The OR-circuit 3 responds to an advance signal from any one of the four storage units so as to generate a signal on an SBO ADV line, which is used to fetch data into the SBOL (storage bus out latch) from any one of the storage units without regard to the destination of the data (such as the channel, or the A and B registers in the I unit, or the J register in the E unit). Each of the OR-circuits 1, 2, 4-7 responds to either one of a pair of respectively corresponding AND-circuits 8, 9; 10, 11; 12, 13; 14, 15; 16, 17; 18, 19, in dependence upon whether the W or Z side of the W/Z trigger, respectively, is presenting a signal on the W line or the Z line. The AND-circuits 8-11 are operated directly by signals on the W and Z lines, whereas the AND-circuits 12-19 are operated by signals on a Y ADV line or an X ADV line, respectively, which are generated by corresponding AND-circuits 20, 21. This difference is due to the fact that the SBO ADV signal is used directly in gating the AND-circuits 12-19, but it is passed through a delay unit 22 prior to being utilized by a pair of AND-circuits 23, 24 to gate the signals on the A ADV and B ADV lines respectively.

The A ADV and B ADV signals are delayed at the gates 23, 24 by the delay unit 22 because of the fact that the A register and the B register are in such close proximity with respect to the bus control unit that the advance signals would appear at the A and B registers prior to the time that data would be available thereto if it were not for this delay. Similarly, the signal on the J advance line is provided by a delay unit 25 in response to the OR-circuit 4, this delay unit being of a somewhat lesser delay than the delay unit 22 due to the fact that the J register is not quite as close as are the A and B registers. Of course, if a different arrangement of hardware within the frame work were provided, the delay characteristics of the circuit of FIG. 47 could be entirely different. The channels, which are located remotely of the CPU frame do not require delaying and therefore the OR-circuit 5 develops a signal directly on the channel advance line. The OR-circuit 6 takes an invalid address indication from either the X register or the Y register and develops a signal on each of three lines AB INV, J INV, CH INV, to indicate to all of these units that an invalid address has been sensed, without regard to which unit it was that initiated the storage request designated by a faulty address. As mentioned in Section 6.3.2.1, the OR-circuit 7 generates a signal on a DIAG SEL (diagnostic select) line which indicates to the PDU that a diagnostic reference to storage has been accepted for a Diagnose instruction. The even numbered AND-circuits 8-18 are all responsive to the X-register whereas the odd numbered AND-circuits 9-19 are all responsive to the Y-register. The X-register is gated by a signal on the W line whereas the Y-register is gated by a signal on the Z line. The reason for this is clarified by a reconsideration of the timing diagram of FIG. 43. A fetch made while the X/Y trigger is set to X will cause an advance signal from storage; this will occur while the W/Z trigger is set to W. Since the select signal which relates to the fetch will then cause the X/Y trigger to be reset (after a half cycle delay) the next storage reference will be made when the X/Y trigger is set to Y. Similarly, since the advance signal causes the switching of the W/Z trigger from W to Z (after a half cycle delay), the next advance signal will appear during the time that the W/Z trigger is set to Z. Thus, selection of storage in accompaniment with an X signal results in a return from storage in accompaniment with a W-signal; selection of storage with Y signal will result in an advance (or return) form storage with a Z signal.

6.3.2.3 Summation of X/Y W/Z circuits FIG. 42 and FIG. 43 through 47. The X/Y-W/Z and Advance circuits also control the return of error signals from the storage units in the circuits of FIGS. 48 through 50.

The X/Y-W/Z and advance circuits therefore provide for keeping track of the location or origination of a storage request, and control destination of stored data and/or check conditions without tying the circuits directly to the particular storage which was referenced. In other words, the circuits of FIGS. 43 through 51 are not concerned with whether an even or odd storage unit was utilized. Thus there has been avoided the necessity of identifying (to the storage output circuits of FIG. 11) the particular storage unit which was referenced (by the circuits of FIG. 9) in order to keep track of the alternating storage references which are being made.

6.3.3 BCU CHECKING CIRCUITS

6.3.3.1 Storage Address Protection Circuit FIG. 48

In the storage units, the key corresponding to a block of storage locations is compared against a key from the program status word within the I unit whenever a store operation (and not a fetch operation) is involved. In the event that either set of keys is not all zeros and does not match the other set of keys, there will be a signal generated on the storage protection line for the related storage frame 1A or 1B. For instance, in FIG. 48, an OR-circuit 1 will respond to signals on an SAP 1A line or an SAP 1B line. The system does not care whether storage unit 1A or storage unit 1B was referenced with erroneous keys, but it does have to insure that a storage address protection error indication is gated to the proper unit: to the channel or to the CPU.

A storage address protection error signal resulting from an erroneous set of keys sent from a channel (in connection with a channel reference of storage) is recognized at the channel, due to the fact that the channel responds differently to errors which it has created; in other words, the I unit of the CPU does not handle error indications from the channel; rather, a channel handles its own error indications. This is necessarily so since any single channel which causes an error should not cause stopping of the CPU or prevent other channels from referencing storage.

To accommodate these needs, the output of the OR-circuit 1 is passed to four AND-circuits 2-5 which are operated by signals on the X-CPU and Y-lines, respectively. The reason for this arrangement of X and Y input signals is that a storage address protection signal on one of the lines SAP 1a or SAP 1B is not received until more than a half-cycle after the select signal goes out to the storage unit. Therefore, it is evident that the X/Y-trigger will have its state reversed by the time that an SAP signal can be received in the circuit of FIG. 48. Thus, if X-CPU selection (which is generated in FIG. 45 by the off-side of the X-CH latch 4) is apparent at the input to the AND-circuit 2, and the X/Y-trigger has been set to Y, and it is known that more than a half-cycle has passed from a select signal for a CPU reference to storage. The other AND-circuits operate in a corresponding fashion for the Y register and for the channel in various combinations. The AND-circuits 2, 3 operate an OR-circuit 6 which sets a latch 7; the AND-circuits 4, 5 operate an OR-circuit 8 which sets a latch 9. The latch 7 is reset either by a CPU reset signal on a CPU RST line (a special reset condition generated in the I unit), or by a signal on an IRPT END RST line from the I unit (which indicates the end of an interrupt handling routine. The latch 9 is reset by a signal on the NOT GATE CH line which is generated in FIG. 18. Thus, the latch 9 will remain set until a following time when the channel is to be gated due to a new storage reference initiated by the channel. Note that the signal on the NOT GATE CH line will have disappeared by the time that a signal could appear on one of the SAP lines at the OR-circuit 1 due to the fact that, in FIG. 18, the CH REQ signal input to the AND-circuits 1, 2, will have disappeared due to the resetting, in FIG. 17, of the latch 1 by a signal on the BR line, B time being the third quarter of each cycle which is right after the X/Y trigger has been switched from X to Y. Thus, by the time that a signal could appear on the SAP 1A line or the SAP 1B line, the not gate signal has disappeared; therefore, the latch 9 will not be reset until the next time that a channel selection takes place. The usage of the signal on the CPU SAP line is described in the interrupt section of said environmental system. The usage of the CH SAP line is described in the aforementioned copending application, Ser. No. 357,369, filed Apr. 6, 1964, Automatic Channel Apparatus, L. E. King, W. C. Hoskinson and E. J. Annunziata.

6.3.3.2 Storage Data Check Circuit FIG. 49

Each of the storage frames 1A, 1B check incoming and outgoing data, data on the SBO. However, data checks performed on the SBO are ignored by the CPU and the channel since these data checks would involve, many times, data which never could be used because of the fact that a branch operation, or a preceding interrupt operation, has caused the system to leave that point in the program the anticipation of which has caused the fetching of the data. On store operations, however, the fact that the storage device has sensed erroneous date is utilized by the channels and the CPU; the use of this storage data check is different for the CPU than for the channel.

In FIG. 49 an OR-circuit 1 responds to a signal on a DATA CHK 1A line or on a DATA CHK 1B line to provide an input to each of two AND-circuits 2, 3 and to provide a signal on a CH STG DATA CHK (channel storage data check) line. The AND-circuits 2, 3 operate corresponding latches 4, 5 to provide timing synchronization for CPU storage data checks; on the other hand, the storage data check is sent directly to the channel at all times, because of the fact that the channels themselves have synchronizing circuitry so that any particular one of the channels will be able to respond to a storage data check signal output from the OR-circuit 1 only if that particular channel had previously received an advance signal from storage, said advance signal being the output of OR-circuit 5 in FIG. 47. In the case of the CPU, by the time that the data check 1A or data check 1B lines could have signals thereon, the CPU advance signals may already be dissipated. This is true because of the fact that the data check signals are very late in the storage operation in comparison with the advance signal. Therefore, the effect of a CPU advance is stored in a pair of latches 6, 7. The latch 6 is set by a corresponding AND-circuit 8 in response to signals on the X-CPU line (from FIG. 45), the X-ADV line (from FIG. 47), and a late B timing signal on the LBR line. The latch 7 is set by an AND-circuit 9 in response to signals on the Y-CPU line (from FIG. 46) and the Y ADV line (from FIG. 47) and a late B timing signal on the LBR line. Thus, the latch 6 or the latch 7 will be operated during a CPU access in dependence on whether the X or Y advance is up, respectively; said latches being set at the start of late B time and remaining set until the start of the following late B time. Referring to FIG. 43, it can be seen that this therefore will cause an X or Y advance which appears simultaneously with the SBO advance to be registered at late B in the cycle and to remain registered until late B in the following cycle even though the advance signal is on from the start of B time in one cycle to the start of the following B time in the next cycle; in other words, a quarter cycle delay is provided by the latches 6, 7. The AND-circuit 2, 3 also respond to corresponding OR-circuits 10, 11 which recognize the CPU operations that result from a fetch. Particularly, NOT X-A, B, J, DIAG and NOT Y-A. B, J, and DIAG are indicative of the fact that neither an I, E or diagnostic FETCH has been made; if this is true and the CPU has however accessed storage, then it must have been a CPU store operation. The OR-circuits 10, 11 are used to ascertain this fact due to the fact that the storage data check signal to the OR-circuit 1 arrive so late in a storage cycle that the selection for a next storage access could be taking place, and that the store circuit of FIG. 38 can no longer be relied upon to reflect the storage operations for the following access. The latches 4, 5 are reset by a signal on a CHK RST line which indicates that the error which was sensed has been handled, and all of the error circuitry involved is to be reset. The details of the signal on this line are developed more fully with respect to the I unit, for which preference may be made to the Table of Contents.

6.3.3.3 Storage Address Check Circuit FIG. 50

The storage address check circuit of FIG. 50 is similar to the storage address protection circuit of FIG. 48. Specifically, a signal will be generated on a CPU STG ADR CHK (CPU Storage Address Check) line by a latch 1, or a signal will be generated on a CH STG ADR CHK line by a latch 2, alternatively, in dependence upon whether the address error sensed in a storage unit relates to a CPU reference to storage or to a channel reference to storage, respectively. Each of the latches 1, 2 is set by a corresponding OR-circuit 3, 4 in response to either one of a pair of related AND-circuits 5, 6 and 7, 8 respectively. The OR-circuits 3, 4 also respond to corresponding AND-circuits 9, 10 which provide gating signals for the respective latches. All of the AND-circuits 5-8 are responsive to an OR-circuit 11 which responds to a signal on either an ADR CHK 1A (Address Check from storage frame 1A) line or on an ADR CHK 1B (from storage frame 1B) line. Thus, the OR-circuit 11 indicates to the AND-circuits 5-8 that an erroneous address has been sensed in one of the storage frames; the identity of the storage frame in which the error was sensed is not important; however, it is important to ascertain whether this resulted from a reference by the CPU or from a reference by one of the channels. Therefore, the AND-circuits 5-8 combine the output of the OR-circuit 11 with signals on lines from the X/Y and advance circuits of FIG. 44 through FIG. 47.

Specifically, the AND circuit 5 responds to signals on the X-CPU and Y lines, whereas the AND-circuit 1 responds to signals on the X-CPU and X lines. Similarly, the AND-circuit 7 responds to signals on the X-CH and Y lines and the AND-circuit 8 responds to signals on the Y-CH and X lines. The reason for pairing X-CPU and X-CH signals with Y signals is the same as described hereinbefore: specifically, by the time that an address check signal can be received in the circuit of FIG. 50, the X/Y trigger will have been switched from X to Y (in the case of a request which is recognized in the X register); therefore, it is known that the opposite side of the trigger must be used in order to properly relate the address check signals arriving at the OR-circuit 11 with requests from the CPU or from the channel, alternatively. The signal on the CPU STG ADR CHK is utilized in FIG. 52 described in Section 6.3.3.5 hereinafter. The signal on the CH STG ADR CHK line is utilized in the channel as described in said copending application, Ser. No. 357,369.

6.3.3.4 X/Y-W/Z Check Circuit FIG. 51.

The operation of the X/Y-W/Z trigger in controlling the X- and Y-registers is described in detail in the foregoing sections. However, should there be some sort of malfunction whereby a select signal is not followed by a respectively corresponding advance signal from storage, or whereby operation of the triggers themselves becomes faulty, it is possible that the X/Y and W/Z triggers could fall out of synchronization with one another. The circuit of FIG. 51 will operate, at a time when none of the storage units are busy, to check the synchronism of the X/Y and W/Z triggers. Specifically, a signal indicating an error in this synchronization is generated on an X/Y-W/Z SYNC CHK (synchronization check) line by a latch 1 which is set in response to an AND-circuit 2 that operates under control of an OR-circuit 3 in dependence upon either one of two AND-circuits 4, 5. The AND-circuit 4 responds to concurrent presence of signals on the X and Z lines, and the AND-circuit 5 responds to signals on the Y and W lines. Thus, the OR-circuit 3 will receive an input from both of the AND-circuits 4, 5 each time that the W/Z trigger is set to W concurrently with the X/Y trigger being set to Y. However, the AND-circuit 2 prevents the output of the OR-circuit 3 from setting the latch 1 except at late B time (due to a signal on the LBR line) during a cycle in which there are signals present on both an ODD NOT BUSY line and an EVEN NOT BUSY line. In other words, when the X/Y register circuits are in a quiescent state, due to the lack of outstanding storage operations being performed, then the AND-circuit 2 will permit the latch 1 to sample the condition of the OR-circuit 3. This time (odd and even not busy) is a time when this relation can easily be identified, and if both outputs of a trigger are off together, no error signal will result; however, this can only occur for a simultaneous failure of two circuits (AND's and OR's), so such a failure is rather unlikely. It should be noted that if one of the triggers X/Y, W/Z fails such that both outputs of the trigger come up at one time, then one of the AND-circuits 4, 5 will provide an error signal. The latch 1 is reset by a signal on a CHK RST (Check Reset) line supplied by the I unit.

6.3.3.5 BCU Stop Clock Circuit FIG. 52

The output of each of the Circuits 49-51 is supplied to the BCU STP CLK circuit of FIG. 52. These signals are received on corresponding lines by an OR-circuit 1 which supplies an AND-circuit 2 so as to set a latch 3 with the concurrent presence of an A running clock pulse signal on an AR line. The latch 3 generates a BCU Stop Clock signal on a BCU STOP CLK line. The latch 3 is reset by a signal on the CHK RST line from the 1 unit.

6.3.4 OUT KEYS FIG. 53

Each of the storage frames, 1A, 1B can respond to an INSERT KEYS instruction from the CPU to fetch from storage, a particular block of storage locations. Specifically, signals representing keys from storage frame 1A may be received by a plurality of OR-circuits 1-3 on corresponding out keys lines 1AP, 1A4, ... 1A1. The OR-circuits 1-3 will also respond to signals from storage frame 1B on a plurality of corresponding out key lines 1BP, 1B4, ... 1B1. The OR-circuits 1, 2, 3 each supply a signal to a corresponding AND-circuit 4, 5 so as to set a related latch 6, 7 in dependence upon the concurrent presence of a signal from an AND-circuit 8. The AND-circuit 8 responds to an OR-circuit 9 whenever there is a signal on either one of two lines; KEY ADV 1A, KEY ADV 1B, which denote that valid key manifestations have been delivered on the OUT KEYS lines by a storage unit within the respective storage frame 1A, 1B. The AND-circuit 8 is gated at A time by an A running clock pulse on the AR line. The output of the AND-circuit 8 is also used to reset the latches 6, 7 so that the latches 6, 7 will be set at the start of A time and will remain set until the start of a following A time.

The OR-circuit 1 also has an input on a CPU INV STR (CPU invalid storage) line from a latch 10 which is set by an AND-circuit 11. The AND-circuit 11 responds to signals on the following lines POS SEL, P-ACC INV ADR, STR and LBR. Thus, the AND-circuit 11 will be operative during a CPU (P-ACC) storage reference (POS SEL) during a store operation (STR) whenever the storage request includes an invalid address (INV ADR). The latch 10 set as late B time. The latch 10 is reset by signals on a CPU RST (reset) line or an IRPT END RST (interrupt end) line from the I unit. Thus, if an invalid CPU storage request is made, the latch 10 will be set early in the CPU storage operations and will remain set until much later in the operation (several cycles later) so that it will be supplying an input to the OR-circuit 1 to thereby gate the AND-circuit 4 at A time when the KEY ADV signal is received by the OR-circuit 9. The purpose of connecting the latch 10 to OR-circuit 1 is to provide a parity bit on the OUT KEYS TO VFL P line when no keys are in fact received from the storage unit, due to the fact that an invalid address was sensed. This prevents a parity check indication resulting from checking the parity of the outkeys to VFL lines from masking the CPU invalid storage indication which is sent to the I unit over the CPU INV STR line.

6.3.5 STORAGE BUS OUT LATCH CIRCUIT FIG. 54

The storage bus out latch in FIG. 54 comprises essentially a plurality of latches 1-5 each of which is set by corresponding AND-circuit 6-10 in response to a related OR-circuit 11-15. The AND-circuits 6-10 also respond to a signal on the SBO ADV (storage bus out advance) line which is generated in the advance circuit of FIG. 47. This signal is indicative of the fact that the storage unit is sending data to the BCU and that said data can be sampled.

Each of the OR-circuits 11-15 responds to one of three related AND-circuits such as AND-circuit 16, 17, and 18 for the OR-circuit 11. Each of the AND-circuits is gated by a different line in dependence upon the source of information which is to be received in the SBOL. For instance the AND-circuit 16 is gated by a data out gate signal for storage frame 1A on a DOG 1A line, the AND-circuit 17 is gated by a data out gate signal for storage frame 1B on the DOG 1B line, and the AND-circuit 18 is gated by a signal on the PKF line (from FIG. 35) which indicates that data is to be received on the storage bus out from the panel data keys in the PDU. The other inputs to the AND-circuit are the actual data bits; for instance the AND-circuit 16 responds to bit 0 signal from the storage bus out of storage frame 1A on an SBO A 0 line; an AND-circuit 17 responds to a SBO BO line; and AND-circuit 18 responds to a PK 0 line, which supplies a 0-bit signal from the panel data keys during a panel key fetch. The operation of the remainder of the circuit is similar and obvious with respect to the above description.

6.3.6 RESET CIRCUITS

6.3.6.1 Computer Reset Control

The computer reset control is a special resetting signal line which appears prior to B time of a final controlled machine cycle before the clock is stopped (that is, before the controlled timing signal AC is halted as shown in FIG. 41.) Computer reset control is used only in the accept circuit and in the PKF-CANCEL circuit of FIG. 29 and FIG. 35 respectively. The computer reset control signal (on the CRC line) remains present for approximately 4 microseconds. This is approximately four storage cycles, or 20 machine cycles. This signal is used to perform a cancel operation if the BCU had initiated a storage reference for the CPU during this last cycle before the clock has stopped. Whenever there is a CRC signal, there will also be a check reset signal (although the converse is not true.) The computer reset control signal on the CRC line is used at FIG. 29 to reset the accept latch. Notice however, that it does not reset the pulse accept latch; this is because pulse accept is used to continue control over the BCU as described in Section 7.19.0.0 hereinbefore.

The computer reset control signal on the CRC line is used in FIG. 35 to directly cause an AND-circuit 4 to generate a cancel if there is a signal on the P-ACC line indicating a CPU storage reference has been initiated within the last cycle. This CANCEL insures storage is not destroyed if the reference was a store (store data is not available until one cycle after retiming).

6.3.6.2 System Reset Control

The System Reset Control signal on the SRC line is a special reset signal which arrives at the BCU prior to B time of a last running machine cycle (that is the last machine cycle before CR, AR, EBR, BR, and LBR running clock signals will all be stopped). In other words, SRC heralds the shutting down or stopping of the system as is described in more detail with respect to the I Clock, for which reference may be made to the said environmental system. In FIG. 12, the system reset control signal on the SRC line is used to reset the channel priority latches 1 at LBR time so that when the system is again started, the latches will be ready to respond to channel storage requests.

This system reset control signal on the SRC line is used in FIG. 17 to reset the channel request latch 3 and in FIG. 28 to reset the latches 1, 2 at A time (AR line), which are used to set the odd and even busy latches. The SRC line is used in FIG. 35 to initiate a cancel operation and in FIG. 44 to reset the X/Y and W/Z triggers, and is used in FIG. 45 and FIG. 46 to reset all of the latches 1-6. E Note that this is on a combined set and reset line, but the gating of the setting AND-circuits 11-18, 24, and 26 will be ineffective since there will be no other inputs to these AND-circuits at the time that the SRC line is activated.

A summary of the use of these resets is shown in the following chart: ##SPC2##

6.3.6.3 System Reset

The system reset signal resets the busy triggers at LB time (LBR line, FIG. 28) whenever storage is inhibited by a "stop on error control" in response to maintenance operations (see Table of Contents) of said environmental system.

7.0 CLOCK CIRCUIT

The Clock Circuit for the system is shown in FIG. 56 through FIG. 59 and illustrated in FIG. 60 through FIG. 64.

7.1 OSCILLATOR CIRCUIT FIG. 56

The Oscillator Circuit shown in FIG. 56 supplies the basic signal from which the clocking signals are generated to run the system of this embodiment. In FIG. 56, either a variable oscillator 1 or a fixed oscillator 2 may be selected by a pair of AND-circuits 3, 4 in dependence upon the presence of a signal on a EN FREQ CHK SW line or the output of an inverter 5 driven thereby, respectively. The fixed oscillator 2 is normally in use, but when required for maintenance purposes, the variable oscillator can be brought into operation. The AND-circuits 3, 4 cause an OR-circuit 6 to drive a binary trigger 7 which halves the frequence of the selected oscillator 1, 2. The output of the binary trigger is applied to an OR-circuit 8 and to a delay unit 9 the operation of which is to cause the OR-circuit 8 to be operated not only for the length of the signal from the binary trigger, but also for an additional 60 nanoseconds (approximately). This then operates as a pulse stretcher so as to be sure that a pulse of at least 60 nanoseconds is available without regard to any criticality in the oscillators or in the binary trigger 7. The output of the OR-circuit 8 feeds an AND-circuit 10 and a delay unit 11 which, when complemented by an inverter 12, causes the AND-circuit 10 to provide a 45-nanosecond signal on the OSC line. This is the signal utilized throughout the clock to generate the various clocking signals.

7.2 CLOCK SYNCHRONIZATION CIRCUITS FIG. 57

The clock synchronization circuits cause the operation of various control circuits to be synchronized directly with the oscillator signal on the OSC line. Specifically, a signal on a START CLKS line or a signal on a SINGLE CYC line will cause an OR-circuit 1 to permit an AND-circuit 2 to set a latch 3 whenever there is a signal present on the OSC line. On the other hand, the absence of either input to the OR-circuit 1 will cause an inverter 4 to permit an AND-circuit 5 to reset the latch 3 in concurrence with a signal on the OSC line. The latch 3 will either be set or reset, therefore, every time an oscillator signal appears on the OSC line. During the times that there is no oscillator signal, an inverter 6 will cause a bipolar latch 7 to reflect the setting of the latch 3 (either set or reset). The output of the bipolar latch 7 comprises a signal on the START CLKS SYNC line. This is utilized to start both a controlled clock and a running clock, which are described in section 11. In a similar fashion, a signal on the SINGLE CYC line will cause a 20-nanosecond delay unit 8 to provide a signal to an AND-circuit 9 which also responds to the signal on the START CLKS SYNC line. The AND-circuit 9 will cause an OR-circuit 10 to permit an AND-circuit 11 to set a latch 12 whenever there is an oscillator signal present on the OSC line. If there is no output from the OR-circuit 10, an inverter 13 will cause an AND-circuit 14 to reset the latch 12 in response to a signal on the OSC line. The OR-circuit 10 is also responsive to a control clock stopping signal on a STOP CTRL CLK line. Thus, during each oscillator time, the latch 12 will either be set or reset in dependence upon there being an output from the OR-circuit 10. During times when there is no oscillator signal on the OSC line, the inverter 6 will cause the setting of the latch 12 to be reflected in a bipolar latch 15 which generates a signal on a STOP CTRL CLK SYNC line.

A signal on a STOP CTRL CLK line will cause an AND-circuit 16 to set a latch 17 during the presence of an oscillator signal on the OSC line, and if that signal is not present, then an inverter 18 will cause an AND-circuit 19 to reset the latch 17. As described before, during not oscillator time, the inverter 6 will cause the setting of latch 17 to be reflected in a bipolar latch 20 which generates a signal on a STOP CLKS SYNC line. The START CLKS, SINGLE CYC, and STOP CTRL CLK lines all come from the maintenance control panel portion of the power distribution unit (PDU) for which reference may be made. Thus, the clock synchronizing circuit of FIG. 57 generates a start clocks synchronization signal which is effective to synchronize the starting of both the control clock and the running clock, generates a stop clocks synchronizing signal which is effective to synchronize the stopping of both clocks, and also generates a stop control clock synchronizing signal which is effective only on the control clock to cause it to stop, while leaving the running clock in an operating condition.

7.3 CLOCK TRIGGER CIRCUIT FIG. 58

In FIG. 58, a control trigger (CTRL TGR) 1 supplies a basic gated controlling signal for the control clock, and a running trigger 2 supplies a basic control signal for the running clock. The control trigger 1 is set by an AND-circuit 2 in response to the concurrent presence of a signal from an OR-circuit 3 due to the lack of a single-cycle mode condition as indicated by a signal on a NOT SINGLE CYC MODE line or, when in the single-cycle mode, in response to the presence of a signal on the SINGLE CYC line. Other inputs to the AND-circuit 2 include signals on the NOT CHECK LCH line, the NOT STOP CTRL CLK SYNC line, the START CLKS SYNC line, and the OSC line. Thus, the AND-circuit 2 will operate either in nonsingle-cycle mode, or when an actual single cycle is desired, provided that there has not been a check condition, there is no synchronization for stopping the control clock, and there is synchronization for starting the clocks; this is all timed by an oscillator signal. The control trigger 1 is reset by an AND-circuit 4 in response to the concurrent presence of a signal on the OSC line together with the output of an OR-circuit 5. The OR-circuit 5 responds to an error condition as indicated by a signal on the CHK LCH line, to the synronization for stopping the clock as indicated by a signal on the STOP CLKS SYNC line, or to the presence of synchronization for stopping only the control clock as indicated by a signal on the STOP CTRL CLK SYNC LINE. Thus, the control trigger is set or reset concurrently with oscillator signals in dependence upon whether starting or stopping of the clocks is indicated, and whether or not there is an error check condition. The in-phase (or "1") output of the control trigger 1 causes an AND-circuit 6 to be operated by the output of a 60-nanosecond delay circuit 7 so as to generate a signal on a GATED CTRL PULSE line for a period of time which is coextensive with 60 nanoseconds following the start of an oscillator signal until 60 nanoseconds after the end of an oscillator signal, whenever the latch is on. The out of phase output (or "0") side of the latch 1 generates a signal on a NOT CTRL line which is used in FIG. 64 as described in section 14. The 60-nanosecond delay line 7 also operates an AND-circuit 8 in conjunction with a latch 2 which is set by an AND-circuit 9 in response to the concurrent presence of an oscillator signal with a signal on the START CLKS SYNC line, and which is reset by an AND-circuit 10 in response to the concurrent presence of an oscillator signal with a signal on the STOP CKLS SYNC line. Thus, whether the control clock and running clock are, in fact, in operation is determined by whether the corresponding control trigger or running trigger, respectively, is set or reset. Stated alternatively, the control trigger and running trigger provide permissive gating signals to the AND-circuits 6, 8 which permit actual pulses to be developed by the 60 nanosecond delayed oscillator signals from the delay unit 7. The signals on the GATED CTRL PULSE line and the GATED RUNNING PULSE line are used to generate the clock signals for the system.

7.4 CLOCK CIRCUIT FIG. 59

The actual timing signals used throughout the system are generated by the clock circuits shown in FIG. 59, the upper portion of which comprises the control clock, and the lower portion of which is identical to the upper portion and comprises the running clock; the only difference between them being that the control clock is operated by the gated control pulse signal from FIG. 58, whereas the running clock is operated by the gated running pulse signal from FIG. 58. The operation of the clock generating circuits is illustrated in FIG. 60 through FIG. 62. In FIG. 60 through FIG. 62, an OSC PULSE (illustration 1) comprises the signal on the OSC line. It is to be noted that this signal is about 45 nanoseconds in width, and the beginning of each pulse is separated from the beginning of the following pulse by 200 nanoseconds, which comprises a machine cycle. The delayed oscillator pulse (OSC PULSE DLY, illustration 2) comprises the output of the delay unit 7 in FIG. 58. This is the signal which gates the signals on the GATED CTRL PULSE line and on the GATED RUNNING PULSE line. These signals are utilized to generate the actual timing signals as shown in FIG. 59.

Whenever the clock has to be stopped because of error signals which give rise to a check condition, it is desirable to always know that the clock will stop at a definite time in relation to the time at which the error condition was sensed. Therefore, the clock circuits of FIG. 56 through FIG. 59 are arranged so that the clock will always stop within a machine cycle following the cycle within which an error could be sensed. Referring to illustration 3 of the check signal (CHK) in FIG. 60, it will be seen that check signals can appear at a number of different times within a machine cycle. It is therefore desirable to establish that these check signals will fall within a single defined machine cycle. For this reason, the final timing of the various clock signals (as shown in illustrations 7-12 in FIG. 60), is set up so that A time begins prior to the time when any of these check signals could occur and the next A described in section 7.5) only during the nonoscillator pulse time. Thus, either of the first two check setting times (3a, 3b) will cause the check latch to be set at time 4a, all other occurrences of a check condition causing the check latch to be set at a corresponding time, approximately 20 nanoseconds after the check condition has occurred, due to the time delays inherent in logic circuits used for setting the check latch. Thus, the establishment of a signal from the check latch is related to the timing of the oscillator in such a fashion that the basic timing signal which defines a machine cycle, which is A time, must occur approximately 180 nanoseconds after the oscillator pulse output on the OSC line in FIG. 56.

Therefore, the circuit of FIG. 59 utilizes appropriate basic delay times so as to provide a proper total delay including the 60-nanosecond delay of the delay unit 7. For instance, a delay unit 1 in FIG. 59 provides a 120-nanosecond delay between the signal on the GATED CTRL PULSE line and the signal on the AC line (controlled A clock line), A corresponding amount of delay is provided by an OR-circuit 2 (which has approximately a 5-nanosecond delay) together with a delay unit 3 (which has roughly a 115-nanosecond delay) in generating a controlled C clock signal on the CC line. Thus the CC (controlled C) clock signals are about 165 nanoseconds delayed from the oscillator signal. In similar fashion, an OR-circuit 4 together with a delay unit 5 provides approximately 105-nanoseconds delay between them in the generation of a controlled L clock signal on an LC line. The output of the OR-circuit 4 is also used with a 115-nanosecond delay unit 8 so as to provide a total delay of approximately 230 nanoseconds (with respect to the oscillator) in the generation of an early B controlled clock signal on an EBC line. The purpose of the combination of the delay unit 6 and the AND-circuit 7 is to compress the length of the LC signal, which is approximately 75 nanoseconds in width, and reduce it to approximately 50 nanoseconds in width, which is achieved by the delay unit 6 causing the AND-circuit 7 to respond to only the last 50 nanoseconds of the 75-nanosecond pulse from the OR-circuit 4; during the first 25 nanoseconds of the pulse, there is no output from the delay unit 6 and therefore the AND-circuit 7 is inoperative during that time. In addition, the B controlled clock pulse is 50 nanoseconds delayed from the early B controlled clock pulse due to the fact that there is a 50-nanosecond delay unit 9 between the delay unit 8 and the BC line. Similarly, a delay unit 10 provides 100 nanoseconds of delay between the late B controlled clock signal on the LBC line with respect to the early B controlled clock signal.

The OR-circuit 4 responds not only to the signal on the GATED CTRL PULSE line, but also responds to the output of a 30-nanosecond delay unit 11. This means that the output of the OR-circuit 4 will be 30 nanoseconds longer than the input, giving the signal on the LC line a width of approximately 75 nanoseconds compared to the 45-nanosecond width of the signal on the AC line. Similarly, two delay units are utilized with the OR-circuit 2 so as to provide a signal on the CC line which is approximately 100 nanoseconds in width. Considering first that the signal on the GATED CPRL PULSE line is 45 nanoseconds in width, a 55-nanosecond delay unit will provide a signal which drops 55 nanoseconds after the drop of the signal on the GATED CTRL PULSE line, but would also provide a 10-nanosecond gap right in the middle of the signal. Thus, not only is the 55-nanosecond delay provided by the delay unit 12, but a delay unit 13 provides a signal that begins 5 nanoseconds before the drop of the gated control pulse and lasts for approximately 35 nanoseconds after the fall of this pulse; this, in a sense, "bridges" the gap between the gated control pulse input to the OR-circuit 2 and the input to the OR-circuit 2 which comes from the 55-nanosecond delay unit 12. Thus the OR-circuit 2 will go on as soon as the gated control pulse goes on, and will stay on until 55 nanoseconds after the fall of the gated control pulse, thereby providing a 100-nanosecond signal to the delay unit 3 which generates the controlled C clock signal on the CC line.

At the bottom of FIG. 59 is illustrated the running clock which has exactly the same circuits as the controlled clock, but these circuits are driven by the signal on the GATED RUNNING PULSE line so as to generate signals on the AR, CR, LR, EBR, BR, and LBR lines. These signals are in every respect identical in time to the corresponding lines at the top of FIG. B4, with the exception of the fact that during single cycle operations, the running clock pulses at the bottom of FIG. 59 continue to appear whereas the controlled clock pulses each appear only once for each depression of the single cycle key.

7.5 CHECK CIRCUIT FIG. 63

A signal on a CHECK line is generated by an OR-circuit in FIG. 63 in response to a signal appearing on any one of the following lines: IOP ERR, BOP PAR ERROR, AA STOP CLK, BCU STOP CLK, INCR CHK, or E UNIT CHK. The signal on the CHECK line is gated by an AND-circuit 2 provided there is no machine check interrupt or no disable check condition as indicated by signals on the NOT MCH CHK IRPT and NOT DISABLE CHK lines.

The output of the AND-circuit 2 or a psuedo check signal on an MCW PSDO CHK LCH line will cause an OR-circuit 3 to operate an AND-circuit 4 so as to set a latch 5 during not oscillator time as indicated by a signal on a NOT OSC line. The latch 5 generates a signal on a CHK LCH line which is used in FIG. 58 and FIG. 64 and elsewhere in this system, particularly in the RETRY, MODAR, and interrupt portions of said environmental system. The signal on the NOT OSC line causes the latch 5 to be reset just a few nanoseconds before being set, as described in the section on component circuits.

7.6 LOG-CRC-SRC CIRCUITS FIG. 64

In FIG. 64, a signal on the NOT CTRL line is used to gate four AND-circuits 1-4 for performing special check and reset functions. The AND-circuit 1 is also responsive to a controlled C clock signal on the CC line, and to the output of the check latch on the CHK LCH line to generate a signal on a LOG ON CHK line which is used to start log out operations in response to the setting of the check latch. The AND-circuits 2, 3 and 4 provide special reset control signals to the bus control unit in response to an impending CPU reset an indicated by a signal on the PRE-CPU RST line or in response to an impending system reset as indicated by a signal on the PRE-SYS RST line. An OR-circuit 5 responds to either of the AND-circuits 2 or 3 so as to generate a computer reset control signal on the CRC line whenever either the CPU or the system is to be reset, and the AND-circuit 4 generates a system reset control signal on the SRC line whenever a system reset is to occur. These signals are used in the BCU to cancel storage operations whenever it is known that a given cycle is the last cycle before either a CPU or system shutdown, and that the storage unit will therefore not be able to complete its communication with one of the units of the system prior to the shutdown. The signals on the PRE-CPU RESET line and the PRE-SYS RST line are generated in the maintenance portion of the system within the power distribution unit (PDU) in response to master resetting controls.

7.7 OPERATION AND TIMING OF CLOCK CIRCUITS FIG. 60 THROUGH FIG. 62

As described in section 7.4, the basic consideration for the clock circuits is to provide a machine cycle which is defined by A time clock pulses (AC, AR) which give the machine the ability to stop in a cycle following a machine check. (Note that the machine check illustrations 3, 4 in FIG. 60 are merely illustrative of various times when checks may be sensed, there being no specific times or any particular increment of delay involved). In FIG. 60, the actual clocking signals are shown by illustrations 7 through 12. The timing of the CPU reset and/or the check reset is shown in illustration 13. These are reset signals used throughout the system to reset various portions thereof, and also cause, in the maintenance section of the PDU the generation of the START CLKS signal shown in illustration 14 in FIG. 60, at a time which is in excess of 300 nanoseconds delayed from the reset. The start clock signal illustration 14, FIG. 60, is applied to the OR-circuit 1 (FIG. 57), and after timing with the oscillator signal, causes the generation of the signal on the START CLKS SYNC line as shown in illustration 15 of FIG. 60. This is then manifested beginning at NOT OSCILLATOR time by the output of the BPL 7 (FIG. 57) which comprises the signal on the START CLKS SYNC line, as shown in illustration 16 (FIG. 60). This permits setting the CTRL TGR (illustration 5, FIG. 60) which permits further controlled signals, such as on the AC line (illustration 7).

Single-cycle operations are illustrated in FIG. 61 wherein the raw oscillator signal is shown in illustration 1, the delayed oscillator is shown in illustration 2, and a 1.5-microsecond single-cycle signal is shown in illustration 3; the single-cycle signal is a timed manifestation which can result from automatic cyclic control of the computer at the maintenance panel or from operator depression of the start button at the control panel, all of which is described in detail in the portion of said environmental system relating to the maintenance portion of the PDU. Whenever the single-cycle signal (shown in illustration 3 of FIG. 61) appears, this will be gated with an oscillator signal through the AND-circuit 2 (FIG. 57) so as to set the start clocks latch 3 (as shown in illustration 4 of FIG. 61) which in turn will cause generation of the signal on the START CLKS SYNC line by the BPL 7 of FIG. 57 as shown in illustration 5 of FIG. 61. This in turn will cause, on the next following oscillator signal, the setting of the CTRL TGR in FIG. 58 which will provide, after approximately 60 nanoseconds delay a signal on the GATED CTRL PULSE line as shown in illustration 7 of FIG. 61.

The presence of a signal on the START CLKS SYNC line will cause an AND-circuit 9 (FIG. 57) to permit an AND-circuit 11 to set the latch 12 in response to the 20-nanosecond delayed oscillator signal as shown in illustration 8 of FIG. 61, and this in turn will cause the generation of the STOP CTRL CLK SYNC as soon as the oscillator signal disappears (as shown in illustration 9 of FIG. 61). The next following oscillator signal will cause an AND-circuit 4 (FIG. 58) to set the CTRL TGR 1, which in turn blocks the AND-circuit 6 from generating any further signals on the GATED CTRL PULSE line. Thus, the particular gated control pulse signal shown in illustration 7 (FIG. 61) is the only one which can occur for the single appearance of the single cycle signal shown in illustration 3. Another depression of a single cycle pushbutton will cause the foregoing action (illustrated in FIG. 61) to be repeated.

General timing relationships of the circuits of FIG. 56 through FIG. 59 are further illustrated in FIG. 62.

7.8 CLOCK POWERING CIRCUITS FIG. 65 THROUGH FIG. 67

In FIG. 65, the normal way of following up a basic clock signal so as to cause it to "fan out" to many points within the system is illustrated. The usual form of clocking circuits includes various branches, the branches having delay units and powering circuits therein. In the present embodiment, the powering circuits are simply called inverters. In some instances, cathode followers, or emitter followers may be utilized, with or without inverters. In this case, inverters have been chosen as a powering circuit due to the simplicity of illustrating the present invention, and because of the general utility thereof in actual implementations of a system in accordance with the present embodiment. In FIG. 65, the basic clock signal is applied to two different legs 1, 2 each including a first circuit complex including an inverter 3, a delay unit 4 and an inverting terminator block (NT) 5. The output of the inverter terminator 5 is, in each case, applied to a further plurality of circuits 6, 7. In an actual machine, there may be as many as 50 circuits represented by the circuit 6, and another 50 circuits represented by the circuit 7. Thus it appears that the inverter terminator block 5 may be extremely heavily loaded, which causes a reduction in the time-response characteristics of these circuits. Referring to FIG. 67, a plurality of illustrations L, M, N illustrate ideal operations of a circuit such as that shown in FIG. 65. These illustrate that under ideal conditions, the pulse width of the basic clock signals will be the same without regard to the number of circuits through which it is passed. However, due to the characteristics of the inverter terminator blocks, this type of operation is not obtainable. In actual practice, operations such as illustrated by X, Y and Z in FIG. 67 can be expected. In accordance with the illustration, it can be seen that the inverter terminator block has caused the width of the signal at Y to be less than the width of the signal at X. This is due to the fact that a terminator used for terminating a delay line, which is heavily loaded by a plurality of circuits (6, 7) will have a slower turn-on response characteristic than turnoff response characteristic. Since the inverter terminator turns on relatively slowly compared with the speed at which it turns off, the pulse does not reach its maximum value until after a definite delay from the energization of the inverter terminator. This effect is further compounded at the inverter terminator 8, 9 due to the fact that the pulse is already late in starting when it is applied to the inverter terminator (as a result of the characteristics of the inverter terminators 5) even though the turn off of the inverter terminators 5 is relatively rapid and will therefore remain much nearly closer to constant as the signal is passed through successive inverter terminators.

The effect shown by the illustrations X, Y, Z in FIG. 67 can be compensated for by specially tuning each of the circuits where pulse width is critical. However, special tuning requires constant repetition rate and constant potential of clocking signals in order for the tuning to remain effective. Whenever voltage or frequency biassing is utilized, any special tuning compensation becomes useless, and the circuits will fail simply because of the pulse width variations illustrated in FIG. 67. Additionally, when the voltage on the clock signal is lowered, the effect of the loading on the characteristics of the inverter terminator are further complicated. This is illustrated briefly in illustrations X, Y and Z by the dotted lines which show that a reduced voltage causes the slow turn on characteristics to be further compounded. Therefore, voltage biassing will, in and of itself, cause the effects illustrated in FIG. 67 to become so pronounced that the clock signals will become totally erratic insofar as system operation is concerned, thereby preventing actual voltage bias tests upon the circuits from finding those circuits which will fail with a slightly lower voltage.

To alleviate the above situations, a circuit in accordance with the present embodiment provides additional inverters as shown in FIG. 66. As shown in FIG. 66, an additional inverter 10 causes a net phase change from the input of a first inverter terminator 11 to the input of a second inverter terminator 12. This means that inverter terminator 12 must turn off rather than turn on. Thus, though the illustrations P and Q are identical to the illustrations X and Y, illustration R shows that even though a shortened pulse is applied to the inverter 12, since it turns off immediately and turns back on rather slowly, it will generate a rather wide negative pulse, thereby compensating for the slow turn on of the pulse shown in Q so that the actual pulse width will be equal to the original pulse width T.

Although slow turn on, in a positive-going sense, is illustrated, it should be understood that various circuits designed to work under various pluralities of potential will operate in a similar manner, whether it be turn on, turn off, at the rise, or at the fall of the pulse width.

8.0 SCAN

Within the embodiment of said environmental system, the word "scan" means the forcing of conditions in bistable devices throughout the system, so as to cause the system to establish a particular state. This is accomplished by a network of circuitry which is complex in its size, but is conceptually very simple. The process includes defining a scan mode, identifying a particular cycle within the scan mode, and utilizing certain bits of a storage word fetched from storage as data bits to force particular bistable devices.

8.1 SCANNING INTO THE I UNIT FIG. 68

I unit scanning is illustrated in FIG. 68. Scanning into the I unit is controlled by six scan word cycles, each one of which causes a 63-bit word to be set into various latches and triggers of the machine. The first scan cycle is defined as word 1 (WD 1), which causes all 63 bits of the J register to be loaded into the PSW register, bit for bit, as shown in FIG. 68. In word 2 of the scan, bits 0-31 are loaded into the IOP register, and IOP parity bits themselves are forced by bits 32-36 of the J register. During this same cycle, the storage address register is loaded with bits 40-63 of the J register, and the parity bits of the storage address register are forced by bits 37-39 of the J register. In a similar fashion, the other words are applied to the various circuits as shown in the chart of FIG. 68. The manner of providing this gating is twofold: as in the case of the PSW register, scan gates are provided as shown at the top of FIG. 70. When status triggers and registers are being scanned into (as in the case of word 5 and word 6, FIG. 68) actual signals are generated by scan gate signals in combination with bits of the J register as shown in FIG. 71. But the circuits of FIG. 70 and 71 are merely illustrative of the manner in which scanning signals may be applied to the circuits of this embodiment.

8.2 SCANNING INTO THE E UNIT FIG. 69

A chart which is illustrated somewhat differently than FIG. 68, but which contains the same information, is shown in FIG. 69. E unit scanning commences after I unit scanning, and includes word 7 through word 15 of a scan operation. The chart of FIG. 69 is not complete as shown therein, bits 36-62 thereof for words 7 through 14 being illustrated in the following chart: --------------------------------------------------------------------------- E SCAN-IN CHART--WORD 7

Bit Trigger __________________________________________________________________________ 36 J 0-7 EA 37 J 0-63 MA T/C 38 J 0-31 MA T/C 39 J 32-39 EA 40 J L 32 MA T/C 41 J For Parity MA T/C 42 K 0-63 MA 43 K R4 MA 44 K L2 MA 45 DC 8 46 DC 4 47 DC 2 48 DC 1 49 DB 0 50 DB 1 51 DB 2 52 DB 3 53 DB P 54 QUOT OVFLO 55 QUOT SIGN OVFLO 56 QUOT INSRT Z VALID 57 QUOT INSRT Z QUOT 58 QUOT INSRT DIV TRUE __________________________________________________________________________ --------------------------------------------------------------------------- e scan-in chart--word 8

bit Trigger __________________________________________________________________________ 36 L ST MA T/C 37 L LT1 MA T/C 38 L RT1 MA T/C 39 L LT3 MA 40 L or Parity MA 41 L DEC CORR 24-31 42 L DEC CORR 32-59 45 Y 1 46 Y 2 47 Y 4 48 Y 8 49 Z 1 50 Z 2 51 Z 4 52 Z 8 53 VFL DVD 61 VFL T8 62 VFL DEC SIGN __________________________________________________________________________ --------------------------------------------------------------------------- e scan-in chart--word 9

bit Trigger __________________________________________________________________________ 36 M R1 MA T/C 37 MA T/C 38 M MA T/C 39 M R3 MA T/C 40 M 0-31 MA 41 M 0-55 MA T/C 42 M LT 32 MA T/C 43 M 56-63 EA T/C 45 T PTR 4 46 T PTR 2 47 T PTR 1 48 S PTR 4 49 S PTR 2 50 S PTR 1 51 RSLT Zero 52 MA Carry 53 ITRN 54 VFL END SEQ 55 VFL FTCH REQ 56 VFL STR REQ 57 1ST CYC STR 58 J=Zero 59 K=Zero 60 E IRPT FM E 61 PA 62 BLK PA __________________________________________________________________________ --------------------------------------------------------------------------- e scan-in chart--word 10

bit Trigger __________________________________________________________________________ 36 T1M IRPT 37 Carry Out MA 0 38 Carry Out MA 1 39 MA Hot 1 40 MA CPMNT 41 R1 SIGN 42 R2 SIGN 43 EA CPMNT 44 MA Allow EAG 45 Add 46 NORM 47 xd 1 48 DL 2 49 DL 3 50 DL 4 51 1ST Term 52 2ND Term 53 QUO XFER CPLT 54 STR 55 FLP to EA T/C 60 1ST VFL 61 VFL SEQ 1 62 VFL SEQ 2 __________________________________________________________________________ --------------------------------------------------------------------------- e scan-in chart--word 11

bit Trigger __________________________________________________________________________ 36 PRESHIFT 38 SFT OVFL 39 M TO SFT DCR-DCDR 40 E BR SUCC 41 FR 2 42 ELC 43 EXP OVFLO 44 EXP UNFLO 45 DVD ZERO RSLT 46 VFL SEQ A 47 VFL SEQ B 48 VFL SEQ C 49 VFL SEQ D 50 VFL PF 1 51 VFL PF 2 52 VFL PF 3 53 VFL PF 4 54 VFL SEQ 3 55 VFL SEQ 4 56 VFL SEQ 5 57 VFL SEQ 6 58 VFL SEQ 7 59 VFL SEQ 8 60 VFL SEQ 9 61 VFL SEQ 10 62 VFL SEQ 11 __________________________________________________________________________ --------------------------------------------------------------------------- e scan-in chart--word 12

bit Trigger __________________________________________________________________________ 36 GT H SC TO DCDR 37 GT SC TO DCDR 38 ER EA T/C 39 ER EA 40 SC EA T/C 41 EA Hot 1 42 J Loaded 43 ADR INV 44 ACCEPT 45 VFL K WITH S 46 VFL L WITH S 47 VFL T1 48 VFL T2 49 VFL T3 50 VFL T 4 51 VFL T 5 52 VFL T 6 53 VFL T 7 54 IS 1 55 IS 2 56 IS 3 57 GT K WITH T 58 DC-DB TO LBG 59 VFL OVLP 0-7 60 VFL OVLP 8-15 61 ADR IRPT 62 SPEC IRPT __________________________________________________________________________ --------------------------------------------------------------------------- e scan-in chart--word 13

bit Trigger __________________________________________________________________________ 36 MAN STR 37 1ST FXP 38 1ST CYC STG 39 EM 1 40 EM 2 41 1ST FLP 42 CVRT 43 TIMER J TO STG 44 TIMER SUB 45 M PROP SIGN 46 J P 60-63 54 DATA IRPT 55 FXP OVFL IRPT 56 FXP DVD IRPT 57 DEC OVFL IRPT 58 DEC DVD IRPT 59 EXP OVFL IRPT 60 EXP UNFL IRPT 61 SIGNIF IRPT 62 FLP DVD IRPT __________________________________________________________________________ --------------------------------------------------------------------------- e scan-in chart--word 14

bit Trigger 36 TIMER ADV 37 STR PSW 38 TST CYC 39 E RST 40 VFL STR FTCH 41 HW LGC 42 HW ADD 43 PRESHIFT ADD 44 ITRN PREP 45 EOP 0 46 EOP 1 47 EOP 48 EOP 3 49 EOP 4 50 EOP 5 51 EOP 6 52 EOP 7 53 EOP P 54 LCOP 0 55 LCOP 1 56 LCOP 2 57 LCOP 3 58 LCOP 4 59 LCOP 5 60 LCOP 6 61 LCOP 7 2 62 LCOP P __________________________________________________________________________

thus, each of the register bits, functions, counters, and so forth, referred to in FIG. 69 and in the above chart can be forced as illustrated therein. It should be understood that the scan control which generated the word and clock pulse signals referred to in FIGS. 70 and 71 would be provided by a suitable scan clock in a maintenance area, such as in the PDU of said environmental system, although said environmental system does not illustrate such a clock, it being within the skill of the art.

9.0 INSTRUCTION UNIT DATA FLOW

As is well known in the data processing art, every computer, or data processing system, utilizes instructions which include an operation portion that defines the actual data handling steps which the computer is to perform as well as an address portion which defines a location in storage of the data, or operands, upon which the operation is to be performed. Traditionally, a computer will have a section of the machine set aside for the purpose of handling the instruction, which section may have a variety of names such as control unit, instruction sequencing unit, or instruction unit. This portion of the machine is referred to herein as the I unit, the I unit selects instructions, handles branch and interrupt functions, communicates with the channels, and performs other related control function.

The description of the I unit herein is divided into "data flow" and controls. "Data flow" refers to the main registers, adders, incrementers, and decoders among which the manifestations of instructions, or portions of instructions, are routed, so as to perform the registering, testing, incrementing, and decoding of their instruction manifestations so as to derive a useful result therefrom.

The description of the I unit data flow is covered in two different ways herein: first, a complete look at the data flow will be given in sections 9.1 et seq., followed by individual descriptions of main portions thereof. The block diagrams of the first section show the same matter as the block diagrams of the second section, but the purpose and approach of the drawings differs. In studying the circuitry in detail, the second section should be utilized; to get an idea of how instructions are handled in this system, the drawings of the first section should be utilized.

9.1 GENERAL INTRODUCTION TO I UNIT DATA FLOW

The I unit data flow is described in conjunction with portions of the E unit (which performs the arithmetic and logic operations upon operands, thereby executing the instructions), and the BCU (bus control unit, which controls the flow of data to and from storage units). The I unit data flow may be considered to comprise four portions:

instruction selection shown in FIG. 72 and described in section 9.1.1;

instruction input paths shown in FIG. 73 and described in section 9.1.2;

instruction decoding shown in FIG. 74 and described in section 9.1.2;

And instruction utilization shown in FIG. 75 and described in section 9.1.4.

9.1.1 INSTRUCTION SELECTION FIG. 72

In the upper central section of FIG. 72 is shown the program status word register (PSW). This register is shown in detail in FIG. 131 through FIG. 139. The PSW contains the system mask, storage protection keys, status bits indicating that the machine is utilizing ASCII code (A), the machine check mask (M), a WAIT bit (W), a PROBLEM bit (P), the INTERRUPTION CODE (IRPT CODE), the instruction LENGTH CODE (LC), the CONDITION CODE (CC), the PROGRAM MASK (PGM), and the instruction counter register (ICR), including a low order portion thereof (LO). It is the ICR which determines the address of the next instruction in a sequence of instructions which comprise a program.

The ICR feeds an incrementer (INCR) which increments the instruction address each time that an instruction buffer register is to be loaded from storage; the ICR also feeds a gate select adder (GSA) which updates the instruction count each time an instruction is performed so as to generate a correct address for the next instruction in a sequence. The INCR is shown in detail in FIG. 140 through FIG. 154. The output of the INCR may be returned to the ICR and may also be applied to the SAR (storage address register) and the H REG (H register, a backup for the storage address register), as well as to a PGM STR COMP (program store compare circuit) and to the high order half (K 0-31) of the K register. The INCR is sometimes used merely as a data path to pass 32 bits from one portion of the PSW register to the K register, and is sometimes used to check (for correct parity) the two halves of the PSW. In order to provide a 32-bit data path, the INCR is provided with an INCR EXT (incrementer extender) which provides the low order eight bits (0-7) of the data path when the INCR is so utilized. The INCR may also receive inputs from the H REG.

The illustrative diagram of FIG. 72 also shows a gate select adder and gate select register (GSA, GSR) which control the selection of a particular group of instruction bytes from among eight-byte storage words as described in section 6.1.2. Since each instruction has at least two bytes, any addressing of storage is on a byte basis, the lowest ordered bit (23) of the ICR is not utilized in selecting instructions from the AB REG; thus, only bits 20-22 are involved in the gate select mechanism. The GS mechanism is shown in FIG. 156 through FIG. 162.

9.1.2 INSTRUCTION INPUT PATHS FIG. 73

The output of the gate select register (GSR) in FIG. 72 is applied to a gate select decode circuit GS DEC (AB REG) so as to select the correct 32 bits at one time out of the AB register (A REG, B REG), The AB register is utilized as a buffer register for instructions which are fetched from storage so as to insure that there is always one instruction available for processing in addition to the instruction which is currently being processed in the I unit. Since the I unit generally processes each instruction concurrently with the execution of a previous instruction by the E unit, this means that the contents of the AB register may be as much as two instructions ahead of that which is being executed. Instructions are received from one of the storage units (STG 1A, STG 1B) over the storage bus out (SBO), or on the channel storage bus out (CH SBO) including data from the power distribution unit (PDU, which includes the maintenance channel). All data so received are stored in the storage bus out latch (SBOL), instructions being transferrable directly to the AB register, and all data, including instructions, being transferrable to the channel storage bus out or to the J register (J REG). Instructions may be temporarily placed in the J REG if they have not been fetched by a certain time in an instruction fetch cycle, and will thereafter be transferred to the AB register provided that a branch has not occurred. In all other cases, timely received instructions are transferred directly from SBOL to the AB register. The contents of the AB register is transferred to the IOP register and to the PRE DEC or TP (Predecode) circuit by means of the gate select mechanism, 32 bits at a time. The choice of the 32-bit group to be selected from the AB register is made by the GATE SEL DEC (gate select decode) circuit which is controlled by the gate select circuitry of FIG. 72 so that the extraction of each instruction will result in extracting the next sequential instruction on a following operation. The AB register, and GS output gating therefor, are shown in FIG. 76 through FIG. 80.

9.1.3 INSTRUCTION DECODING FIG. 74

The 32 bits from the AB register are applied to the IOP register as shown in FIG. 74. This register includes an operation portion (OP), an R1 field, an R2-X field, a B field, and a D field. At the time an instruction (or a portion of an instruction) is loaded into the IOP register, preliminary information about the instruction is also being derived from the PRE DEC. The contents of the IOP register are transferred to various circuits which perform different functions in the handling of an instruction. The OP portion is applied to the IOP DEC (ID), where the operation portion is decoded for I unit use. The same portion is transferred along with the R1 portion to the BOP register; in turn, the OP portion of the BOP register is applied to the BOP DEC (BD), for backup operation decoding. It is the IOP and BOP decoders which perform a major portion of the operand and branch decoding in the system. Each of the fields R1, R2-X, and B are used to specify general purpose registers, the contents of which are involved in the execution of the instruction. The R1 field, however, is utilized from the instruction. The R1 field, however, is utilized from the BOP register rather than from the IOP register controlling selection of the general registers. Each of these fields is also tested for zero in order to determine special situations where no general register is to be utilized in accordance with the architectural definition of a data processing system in said System/ 360 Manual. The B field of the IOP register is applied to the addressing adder (AA) as a component of a storage address for all instructions which reference storage, the addressing adder being shown in FIG. 79 which the R1 portion of the BOP register also applies to an ER 1 register which provides R1 information later in a cycle. The ER 1 register is so called because it provides R1 information to the E cycle rather than to the I cycle.

In FIG. 74 various comparison circuits are shown which compare ER 1 with R2-X, BR 1 with R2-X, and BR 1 with B. The purposes of the various comparisons are described in conjunction with the circuits which utilize them. The instruction decoding circuits are shown in detail in FIG. 76 et seq.

9.1.4 INSTRUCTION UTILIZATION FIG. 75

In FIG. 75, a plurality of general purpose registers (GR) receive information from the K REG under control of the ER 1 SEL GR IN lines. The output of a general register selected by one of the lines: IR2 SEL GR, IB SEL GR, BR 1+1 SEL GR, lines will be applied to the general bus left or general bus right (GBL, GBR) for application to the register bus latch (RBL) shown in FIG. 73, and to the address adder (AA). The general registers, the GBL and GBR, and the controls therefor are shown in FIG. 114 et seq. Other inputs to the address adder include a VFL LGTH FLD (VFL length field), the interrupt controls (IRPT CTRLS), and the IOP D field. The output of the address adder is applied to the SAR, and thence to the SAB (storage address bus) which applies address bits to storage. The address adder is also applied to the H register which serves as a sort of backup register for the SAR; addresses which are to be manipulated or compared are derived through the H register whereas utilization of address manifestations is through the SAR.

Also illustrated in FIG. 75 are the channel and unit selection circuits which respond to the H REG. Specifically, either the H REG or channel address signals from the console may be utilized to form a unit address on the UABO as well as channel selecting signals.

It should be borne in mind that FIG. 72 through FIG. 75 are intended as illustrative figures for reference, rather than being descriptive of the hardware as such. All of the hardware illustrated in FIG. 72 through FIG. 75 is illustrated, both in block diagram form, and in detail, in figures relating thereto, described hereinafter.

9.2 INSTRUCTION DECODE DATA FLOW

In FIG. 76 is shown that portion of the I unit data flow circuitry which receives and initially decodes instructions, including the general registers and the gates for the control over the input and output thereof. In the upper left-hand corner of FIG. 76, a circuit which selects between the A register and the B register (SEL A/B) FIG. 77 and controls the operation of the A/B INV KEY circuit FIG. 78 and the SBO A/B GATING circuit FIG. 79 which select the proper invalid key for storage and which causes the proper one of the A and B registers to be gated, respectively. THE A register (A REG) and the B register (B REG) FIG. 79 may respond to signals from either the storage bus out latch (SBOL) or the J register (J REG) so as to store manifestations of instructions which are to be performed. Both the A REG and the B REG are utilized together as a single instruction register, (AB REG) the content of which may be selected by a gate select (GS) circuit FIG. 80 so as to supply one instruction at a time to the I unit operation register (IOP REG) FIG. 83. A portion of each instruction is also fed to a predecode circuit (PD) FIG. 81 and FIG. 82 where preliminary decoding takes place in order to provide control information useful in the proper fetching of instructions. Bits 8 to 15 of the IOP REG may also be set in response to bits 24-31 of the general bus left (GBL) output of the general registers (which is shown at the lower right-hand corner of FIG. 76).

The IOP REG is the primary instruction register for the system, and is utilized as a source of operands, operand addresses, and operational codes as is described in said System/360 Manual. Specifically, the IOP REG supplies the operational portion of an instruction to the instruction decoder (ID) FIG. 86 through FIG. 98 and to a backup (or buffer) operation register (BOP) FIG. 102 through FIG. 103 and FIG. 106, which in turn feeds the BOP decode circuit (BD) FIG. 122 through FIG. 130. It is the I decode and the BOP decode circuits which supply the primary operation decoding for the I unit. The IOP REG also supplies operational manifestations to an E unit operation register (EOP) which in turn feeds a last cycle operation register (LCOP), both of which are located in the E unit of the system. A parity check is performed on the contents of the IOP REG by a checking circuit (IOP CHK) FIG. 85. The D field portion of each instruction is passed to an address adder under the control of a D field gating circuit (GT D FLD TO AA) FIG. 84.

The B and R2-X portions of each instruction are utilized in selecting a particular general register, the contents of which are to be utilized in some manner in the performance of an instruction; this is achieved by a general register outgating selection circuit (GR OUT SEL) FIG. 108 through FIG. 110. The B, R2-X, and R1 portions of each instruction are each tested to see that it equals other than zero, and the R1 portion of the contents of the BOP register is compared against the B and R2-X portion of the IOP register, as well as the R1 portion of the E register being compared with the R2-X portion of the IOP register. This is accomplished in compare circuits (COMP), FIG. 119 through FIG. 121.

The R1 portion of the BOP register may be incremented one unit at a time by an incrementer which is referred to in FIG. 74 as the BR 1 ADDER and is referred to in FIG. 76 as the INCR FIG. 105. The R1 portion the BOP register is applied to another R1 register ER 1) FIG. 104, which contains a manifestation of the R1 portion of an execution which is currently being executed in the E unit; thus, the ER 1 register FIG. 104 is essentially an E unit register which is, however, located within the I unit and associated directly with control of circuitry within the I unit. The ER 1 register also has an incrementer (INCR) FIG. 107 which permits incrementing R1 one unit at the time within the ER 1 register. The content of the ER 1 register is not only used in the compare circuit, but is also applied to ingating controls for the general registers (IN GTS) FIG. 116 and FIG. 117. These gates control the passage of data manifestations from a K register (K REG) into the general registers (GEN REGISTERS) FIG. 118. The content of the general registers FIG. 118 may be passed to either a left-hand general register output bus called "general bus left" (GBL) or to a right-hand general register output bus called "general bus right" (GBR) by a general register outgate circuit (OUT GTS) FIG. 113 through FIG. 115. A general register gate control circuit (GT GR CTRLS) FIG 112 selects which of the outputs of the GR OUT SEL circuit will be utilized to control the OUT GTS circuit.

Although not shown in FIG. 76, the predecode, I decode and BOP decode all supply a plurality of signals to various parts of the system in order to control the handling and execution of successive instructions.

Thus, the basic instruction handling circuits shown in FIG. 76 receive, select, and decode instructions, as well controlling the input and output of data from the general registers, portions of the instructions being tested for zero and compared against one another so as to provide proper control signals for the system.

9.2.1 A B REGISTERS

9.2.1.1 A/B Selection Circuit FIG. 77

The selection as between the A register and the B register is determined by the SEL A/B circuit of FIG. 77 wherein a signal designating register A is generated on a SEL A line by an OR-circuit 1 in response to a signal on a SEL A UNCOND line or in response to either one of two AND-circuits 3,4. The AND-circuit 3 responds to the concurrence of a signal indicating that a branch condition upon events within the I unit has been successful on an I BR SUCC line together with the output of an OR-circuit 5 which responds to an AND-circuit 6. The AND-circuit 6 operates in response to signals on a J LOADED LCH (I) line concurrently with a signal on a SEL A ON BR SUCC & J LD line. The other input to the OR-circuit 5 is a signal on a SEL A ON SUCC BR line. The OR-circuit 5 is also supplied to the AND-circuit 4 which responds to signals on the E BR SUCC line. Thus, the OR-circuit 1 will generate a signal on the SEL A line whenever successful branch for the I unit or from the E unit is indicated concurrently with an indication that A should be selected on a successful branch or that A should be selected on a successful branch when the J register is loaded and the J register is in fact loaded. A signal indicating that the B register is to be selected on a SEL B line is generated by a circuit 7 which is identical to the circuitry 1-6 at the top of FIG. 77. The inputs of the circuit 7 are identical to those of the circuits 1-6 with the exception of the fact that the following lines relating to the B register are substituted for those relating to the A register: SEL B ON BR SUCC & J LD, SEL B ON SUCC BR SEL B UNCOND.

9.2.1.2 A/B Invalid Key Circuit FIG. 78

Instructions are fetched from storage in an overlap fashion; that is, a storage word containing instruction manifestations may be first fetched to the A register, and while these are being handled, a subsequent storage word, next in a sequence of storage words, may be fetched to the B register. If a fetch operation is initiated for either the A or B register with invalid storage protection keys, the bus control unit (BCU) will not be able to differentiate between the A and B register as to the destination of the fetch with which the invalid key was associated. This is so because of the fact that whether the A or B register is to be selected is determined solely by whether the storage word being fetched is in an even or an odd address. An instruction manifesting storage word fetched from an even address is automatically placed in the A register, whereas an instruction manifesting storage word from an odd address is placed in the B register. In order to properly handle an interruption resulting from the specification of an invalid storage key, the I unit data flow control circuits determine whether the invalid key is associated with a fetch to the A register or to the B register.

In FIG. 78, a signal is generated on an A INV ADR line by a latch 1 which is set by an OR-circuit 2 in response to a signal on a SCAN IN A INV KEY line or in response to either one of two AND-circuits 3,4. Both of the AND-circuits 3,4 respond to a signal on the SET A REG line. The AND-circuit 3 responds to a signal from the BCU which indicates that an invalid key was sensed as a result of a fetch to the A B registers (in this sense, there is no distinction between the A register and the B register) on an AB INV line, and also responds to a signal which indicates that data manifestations which in fact have been retrieved from storage are to be stored in the AB registers on a GT JBO TO AB line. The AND-circuit 4 responds to signals on a J INV line concurrently with a GT J TO AB line. Thus, either the AND-circuit 3 or the AND-circuit 4 will operate provided that the A register is to be set, and there is either an indication than an AB register fetch has resulted in an invalid key in an operation where the SBO is to be gated to the AB registers, or where a fetch to the J register has resulted in an invalid key indication in an operation where the J register is to be gated to the AB registers.

In the bottom of FIG. 78, a circuit 5 is identical to the circuits 1-4 with the exception that input lines relating to the B register are substituted for corresponding lines relating to the A register so as to generate a signal on a B INV ADR line.

Notice that the latch 1 and the corresponding latch within the circuit 5 are each reset by the same signal as is used to gate the setting AND circuit; thus, each latch is reset just a few nanoseconds prior to being set as described in the section herein relating to circuit components.

9.2.1.3 AB Register And Gating Circuits Therefor FIG. 79

At the top of FIG. 79 is shown the A register, and the B register is shown at the bottom thereof. The A register is set in response to a signal on a SET A REG line (which line is utilized in FIG. 78. A signal is generated on the SET A REG line by an OR-circuit 1a in response to a signal on a NOT SCAN GT TO IOP line or by an AND-circuit 2a which operates in response to signals on a SEL A line and to a late B running clock pulse on an LBR line. The scan input to the OR-circuit 1 permits setting the A register at the particular point in a scanning type of maintenance operation. The A register comprises a plurality of latches 1 each settable by a corresponding OR-circuit 2 in response to related pairs of AND-circuits 3,4, each of which responds to the signal on the SET A REG line. The AND-circuits 3 also respond to an inverter 5 which is operated by a signal on a GT J TO AB line. The GATE J TO AB signal is generated by an AND-circuit 6 in response to signals on the J LOADED LCH(I) and TSTS CMPLT lines. The AND-circuit 6 therefore operates at a time when a conditional branch operation has been indicated by a first instruction, and fetching of an instruction, to which a branch is to be effected, has taken place; when a storage word containing the instruction to which branching is to be effected is loaded in the J register, and when all conditional branch testing is completed, the AND-circuit 6 will provide a signal on the GT J TO AB line. Due to the inverter 5, each of the AND-circuits 3 will respond to a corresponding bit of the storage bus out (SBO) whenever there is no signal on the GT J TO AB line concurrently with a signal on the SET A REG line. On the other hand, if there is a signal on the GT J TO AB line, then each of the AND-circuits 4 will permit a corresponding bit of the J register (J REG) to set a corresponding one of the latches 1 of the A REG.

In a corresponding fashion, each bit of the B REG may be set by a corresponding bit of the SBO or the J REG in dependence upon an output from the inverter 5 or the AND-circuit 6, respectively, concurrently with a signal on the SET B REG line. The SET B REG line is controlled by an OR-circuit 7 in response to an AND-circuit 8, both of which operate in the same fashion as the OR-circuit 1 and the AND-circuit 2 except for the fact that a signal on the SEL B line is used instead of the SEL A line.

9.2.1.4 AB Gate Select Circuit FIG. 80

The manner in which the gate select mechanism selects a particular 32 bits for extraction from the AB register is illustrated in FIG. 73 and the actual implementation thereof is shown in FIG. 80. In FIG. 80, a plurality of AND-circuits 1-6 permit gating out particular 32-bit groups of the AB register, there being two AND circuits for each bit of the AB register so as to achieve the overlapped gating of 32-bit groups which are separated by 16 bits as illustrated in FIG. 73. The outputs of the AND-circuits 1-6 are supplied to a plurality of OR-circuits 8...9, there being 36 OR circuits, one for each bit in a 32-bit group and one for each of four parity bits associated therewith. The output of FIG. 80 comprises the AB register output which is utilized by the IOP register and the predecode circuit.

9.2.2 PREDECODE

9.2.2.1 Predecode Circuit FIG. 76

In order to determine whether a second group of manifestations must be gated out of the AB register, and to sense the presence of special instructions such as branch instructions which affect the manner in which the instruction itself will be processed prior to the execution thereof, the predecode circuit (PD) of FIG. 81, 82 determines the presence of certain types of instructions. A first group of branch instructions is indicated by a signal on a PD BR GROUP 1 line by an AND-circuit 1 in FIG. 81, 82 which responds to the following bits of an AB register: NOT 2, NOT 3, NOT 4, and 5. Reference to the operation code charts shown in section 9.2.4.1 illustrates that this combination of bits will specify the following instructions as being within branch group 1 as sensed by the AND-circuit 1: (RR format instructions). Set Program Mask, Branch and Link, Branch on Count, Branch on Condition; (RX format instructions) Execute, Branch and Link, Branch on Count, Branch on Condition; and (RS, SI format instructions) Write Direct, Read Direct, Branch on Index High, and Branch on Index Low-Equal.

A second group of branch-type instructions are indicated by a signal on a PD BR GROUP 2 line which is generated by an OR-circuit 2 in response to any one of three AND-circuits 3-6 in FIG. 81. The AND-circuit 3 responds to AB bits NOT 7, 6, AND NOT 0. The NOT 0 bit restricts the decoding to the RR and RX formats; the combination of NOT 7 and 6 specify Branch and Link and Superviser Call instructions in the RR format, and specify Branch and Link, Add, and Convert To Decimal instructions in the RX format. The AND-circuit 3 also requires a signal from an inverter 7, which it will have when there is no signal on a PD R1 = 15 line from an AND-circuit 8, which in turn senses all ONES in the R1 field of BOP (8-11). In a similar fashion, the AND-circuit 4 will create a signal for the Branch And Link instruction in the RR format, the AND-circuit 5 will provide a signal for the Execute instruction, and the AND-circuit 6 provides a signal for the Branch On Index High and Branch On Index Low-Equal instructions.

9.2.2.2 Predecode IOP Loaded Circuit FIG. 82

In order to determine whether the AB register is sufficiently loaded so that an instruction of suitable length (two, four or six bytes) is available for initial decoding of the instruction, the circuit of FIG. 82 analyzes the setting of the gate select register (GSR) and the highest order two bits of the instruction which determine the format (and therefore the length) of the instruction which is being read out of the AB register. Referring to the chart on operation codes in section 9.2.4.1 and to the data flow illustration of FIG. 73, whenever bits 21 and 22 of the GSR are both present, that means that a 32-bit instruction manifestation will be derived partly from the A register and partly from the B register. If a 16-bit (RR) instruction is to be involved. 16 of the bits are useful and the other 16 are not. Of the various instruction formats, the RR format is of a single syllable (16 bits) and therefore even though the GSR specified both bits 21 and 22, which means that split gating as between the A and B registers is involved, a complete RR instruction may be had out of the remainder of the register wherein the instruction starts.

For instance, assuming that the GSR is set to 011, this will cause bits 48 through 63 of the A register and bits 0 through 15 of the B register to be gated out. If an RR instruction is involved, the instruction will be complete within bits 48-63 of the A register. The content of bits 0-15 of the B register are totally immaterial. Therefore, the A register can be considered to be completely loaded insofar as that instruction is concerned when the GSR is set to 011. On the other hand, the RX, RS AND SI formats each contain two syllables (32 bits) and therefore addresses within the A and B register of 0, 16 or 32 will specify a complete instruction of that type within one of those registers. On the other hand, two syllable instructions beginning at bit 48 of the A register will not be complete without the first 16 bits of the B register, and these two-syllable instructions if they begin at bit 48 of the B register will not be complete without the first 16 bits of the A register. The circuit of FIG. 82 senses whether or not a complete instruction is contained within the register which is being referenced, beginning at the bit position designated by the GSR. For instance, an AND-circuit 1 senses the presence of GSR bits 21 and 22 so as to indicate that a split register situation exists: that is, bits 48 to 63 of the A register will be gated out with bits 0-15 of the B register, or bits 48-63 of the B register. When this is true, and the instruction format is one which contains either four or six syllables, then the instruction is not complete within the particular register where it begins. The AND-circuit 1 senses a 1 bit from the AB registers, which bit is present in both the RX and the SS format, and the AND-circuit 2 senses a 0 bit from the AB register which 0 bit is present in the RS, SI format and in the SS format. Thus, between AND-circuit 1 and AND-circuit 2 it is possible to sense that the GSR setting is such that only a 16-bit instruction can be read out, but that either a 32-bit or a 48-bit instruction is being specified.

When either of the AND-circuits 1, 2 is operated, an OR-circuit 3 will supply a signal to an inverter 4 which prevents the presence of a signal on a PD COND IOP LOADED line. In a similar fashion, an AND-circuit 5 senses the presence of GSR bit 21, which will be present whenever an instruction begins in the high order half of a register. That is, if bits 32 through 63 are being read out, or if bits 48-63 together with bits 0-15 of the other register are being read out, the AND-circuit 5 will be operative. Since 32 bits or 16 bits only will be available in whichever register is being read out, it is apparent that a 48-bit instruction will not be completely contained within the register at that time. The AND-circuit 5 responds to a 0 bit from the AB register to recognize that the SS format is involved (see the instruction format chart shown in said System/360 Manual), to cause the OR-circuit 3 to energize the inverter 4 and thereby prevent a signal from being generated on the PD COND IOP LOADED line. In all other situations, the inverter 4 will supply the predecode condition IOP loaded signal which is utilized elsewhere to sense when the instruction is properly loaded.

9.2.3 IOP CIRCUITS

9.2.3.1 IOP Register FIG. 83

As is illustrated in FIG. 74, all of the bits of the IOP register are set by the AB register, and in addition, bits 8-15 of the IOP register may be set by bits 24-31 of the GBL (general bus left). As shown in FIG. 83, the IOP register comprises a plurality of latches 1 each of which is set by a corresponding OR-circuit 2 in response to a related pair of AND-circuits 3, the OR-circuits 2 for bits 8-15 and p8-15 also responding to a related AND-circuit 4 which relates to the GBL input. Each of the latches 1 is reset by a related OR-circuit 5 in response to either one of a pair of corresponding AND-circuits 6. Half of the AND-circuits 3, 6 are responsive to an AND-circuit 7 which provides a gating signal whenever there are signals present on the SET IOP and AC lines. The remainder of the AND circuits 3 and the AND-circuits 6 respond to a SCAN gating signal on the SCAN GT TO IOP line. The AND circuits 4 are responsive to a gating signal on the GT GR to RBL line.

Concurrently with a signal on the XEQ GATE line, which permits ORing bits 24-31 of GR (R1) into bits 8-15 of the subject instruction of an Execute instruction. The SCAN input to IOP is not shown on the data flow illustrative drawing of FIG. 74 since it has to do with maintenance, rather than with regular operation of the machine. Whenever scanning into the IOP is involved, a signal on the SCAN GT TO IOP line will cause the related AND-circuits 3, 6 which are fed thereby to respond to respectively corresponding bits of the J register, the J register being gated through the instruction counter register (ICR); therefore, respective bit lines of the ICR are applied to the AND-circuits 3, 6 in FIG. 83. During normal system operation, a signal on the SET IOP line causes corresponding bits of the IOP register to respond to related AB register bits, that is the bits presented from the A register and B register through the gate select mechanism. The output of the IOP register comprises the IOP bits 0-23 together with three parity bits: P0-7, P8-15, and P16-23.

A portion of the IOP register is shown in FIG. 108a, wherein a parity bit for the high-order four bits of the D field is generated. In order to generate a parity bit for the D field, the parity bit for the eight-bit group which includes the D field has the effect of the B field removed therefrom whereby the result is correct parity for the D field. In FIG. 108 a, a signal is generated on the D FLD P20-23 line by an EXCLUSIVE OR circuit 1 in response to an EXCLUSIVE OR complex 2 which in turn responds to IOP bits 16-19. The EXCLUSIVE OR circuit 1 also responds to the parity bit for IOP bits 16-23 as manifested by a signal on the P16-23 line. Thus, the output of the EXCLUSIVE OR circuit will reflect the total eveness or oddness of the high-order four bits of the D field (bits 20-23 of the IOP register).

9.2.3.2 D Field Gate FIG. 84

Referring briefly to the illustrative drawings in FIG. 74 and FIG. 75, the D field of the IOP register is a "displacement" field of operand addresses for instructions which are in the RX, RS, SI, and SS formats. The contents of the D field therefore is to be applied to the address adder so that it may be added to the value derived from a general register which is specified by the B field of the IOP register, and, in the case of an RX format instruction, there is also added the value of a general register specified by the contents of the R2-X field of the IOP register. The circuit of FIG. 84 controls gating of the D field from the IOP register to the addressing adder (AA).

In FIG. 84, a D field gating signal is generated on a GT D FLD TO AA line by an OR-circuit -1 in response to an AND-circuit 2 which in turn is operated by signals on a T1 line concurrently with a signal on a NOT ID RR line. The other input to the OR-circuit 1 is a signal on the SS OP line. The GT D FLD TO AA line is also connected to a plurality of AND-circuits 3, each of which responds to a related IOP bit 20-31 (which comprises the D field portion of the IOP register). Each of the AND-circuits 3 generates a respectively corresponding signal on a related one of a plurality of D FLD lines 20-31. In addition, an AND circuit 4 will generate a D field parity bit in response to a signal on the D FLD P20-20-23 line.

9.2.3.3 IOP Error Circuit FIG. 85

In FIG. 85 is shown a latch 1 which generates an error signal on an IOP ERR line. The latch 1 is set by an AND-circuit 2 at A time in response to a signal on the SET IOP ERR line whenever there is a signal generated by an OR-circuit 3. The OR-circuit 3 is responsive to three different EXCLUSIVE OR complexes, only one of which is shown in FIG. 85. Concerning the parity of the byte containing bits 8-15, an inverter 4 is responsive to an EXCLUSIVE OR tree 5 so that there will be a signal from the inverter 4 to the OR-circuit 3 whenever the sum total of inputs to the EXCLUSIVE OR tree 5 is an even number. Circuits similar to the inverter 4 and the EXCLUSIVE OR tree 5 would be provided for the other two bytes of the IOP register so that the OR circuit 3 would provide a signal to set the latch 1 in the event that other than odd parity existed in any one of the bytes.

9.2.4 IOP instruction DECODE FIG. 86 THROUGH FIG. 98

The I decode circuits are shown in a simplified form in FIG. 86 through FIG. 91. FIG. 92 through FIG. 97 comprise charts illustrating the I decode and BOP decode lines which are energized for each of the instructions of the present embodiment. The chart layout shown in FIG. 92 through FIG. 97 is similar to the layout of the instruction chart shown hereinbefore, that is, the format of the instruction is indicated in the upper left-hand corner of the top half of the chart and in the upper left-hand corner of the bottom half of the chart, and the variation bits for the particular instruction within the format is shown in the right-hand column of each chart. Thus, the branch and link instruction in the RR format (BALR) is shown in the center section of FIG. 92, and has an operand code for the IOP bits 0-7 of 0000 0101. Taking the BALR instruction as an example, it can be seen that a number of lines (which are indicated vertically at the top of the figure) are involved with this instruction. The nature of the involvement is identified by the key letters found in the horizontal row which correspond to the BALR instruction. The conditions, upon which the generation of signals on the lines indicated in FIG. 92 through FIG. 97 are conditioned, are shown in the following chart:

ID and BD decoding Conditions

A. (R2 or X2=0) & (BR 1 equals IRZ) & (BD COMP REQ) B. (B2 0) & (BR1 equals IB) & (BD COMP REQ) C. R2 0 D. GROUT E. T2 F. (T1) & (R2 or X2=0) G. H REG 22=1 H. H REG 21=0 J. (H REG 21=0) & (H REG 22=0) K. (H REG 21=0) & (H REG 22=1) L. (H REG 21=1) & (H REG 22=0) M. H REG 21=1 N. (H REG 21=1) & (H REG 22=1) X Unconditional

Whenever more than one condition letter is shown in the tables of FIG. 92 through FIG. 97, the satisfaction of any one of the conditions will permit the generation of the indicated signal. It should be noted that the majority of the decode lines are energized by the BOP decode circuits rather than the I decode circuits; for that reason, the BOP decode circuits are shown in complete detail, but to avoid duplicity, the I decode circuits are shown in a simplified, illustrative manner. It should be understood by those skilled in the art that the manner in which the various decode lines are energized is relatively unimportant, it being sufficient that the requirements of the embodiment be satisfied by generating sufficient signals of a suitable kind so as to initiate circuit responses in a required manner. More specifically, a "shotgun" approach to decoding is illustrated with respect to the I decode circuitry shown in FIG. 86 through FIG. 98, whereas an efficient, though conceptionally complex method of decoding is utilized in the illustrative example of the BOP decode circuits illustrated in FIG. 122 through FIG. 130.

9.2.4.1 Chart Of Instuctions By Class

The following chart illustrates instructions to which the system of the present embodiment may respond. These instructions are the same as those set forth in the architectural definition of the data processing system disclosed in said System/360 Manual.

In the following chart, the following abbreviations are used:

& And BR Branch CH Channel CHAR Character COMP Compare COND Condition CPMNT Complement CVRT Convert D Double DL Double Logical EQ Equal EXCL Exclusive N Normalized NEG Negative NUM Numeric PGM Program POS Positive S Single SL Single Logical SUB Subtract SUP Supervisor U Unnormalized ##SPC3##

9.2.4.2 Alphabetical List Of Instructions

The following list is an alphabetical list by instruction name of the instructions found in the chart shown in the preceding section. This chart also includes instruction abbreviations as used herein, although not all of such abbreviations appear specifically in the description of this embodiment. The chart also shows the instruction format, indicates whether or not the condition code is set, indicates the kinds of exceptions which may cause interruptions during the execution of the particular instruction, and indicates the code (that is, the two digit designation which is equal to the 8-bit code such as bits 0-7 of the IOP register) which identifies a particular instruction: in that code, decimal values of 1 through 9 are created by an equivalent binary value, and the values A-F are equal to decimal values of 10-15, whereby the code is specified in two hexidecimal columns, each column capable of having a decimal value of 0-15 as indicated by the numbers 0-9 and A-F. The first character of the instruction code (such as the numeral 1 for the AR instruction) equals the hexidecimal value of the IOP bits 0-3 shown at the top of each column in the chart of the preceding section; ##SPC4## ---------------------------------------------------------------------------

Legend A Addressing exception C Condition code is set D Data exception DF Decimal-overflow exception DK Decimal-divide exception E Exponent-overflow exception EX Execute exception FK Floating-point divide exception IF Fixed-point overflow exception IK Fixed-point divide exception L New condition code loaded LS Significance exception M Privileged-operation exception N Normalized operation P Protection exception S Specification exception U Exponent-underflow exception __________________________________________________________________________

9.2.4.3 IOP Format Decode FIG. 86

In FIG. 86, a plurality of AND-circuits 1-4 each respond to a different combination of 0 to 1 bits of the IOP register to generate a signal identifying the instruction format of the particular instruction which is being held in the IOP register. For instance, if there is neither a 0 nor a 1 bit in the IOP register, then the AND-circuit 1 will generate a signal on the ID RR line. If there is no 0 bit but there is a 1 bit, then the AND-circuit 2 will generate a signal on an ID RX line. Similarly, the AND-circuit 3 responds to a 0 bit but no 1 bit so as to generate a signal on the ID RS-SI line, and the AND-circuit 4 responds to the presence of both bits so as to generate a signal on the ID SS line.

9.2.4.4 IOP Exemplary Instruction Decode FIG. 87 Through FIG. 89

In FIG. 87, the branching and status switching type of instructions are identified by a signal generated by an AND-circuit 1 in response to a signal on the ID RR line together with the absence of bits 2 and 3 in the IOP register as indicated by signals on the NOT-2, NOT-3 lines. The output of the AND-circuit 1 is applied to two AND-circuits 2, 3 each of which partially decode for a group of instructions, the output of each being used to energize a plurality of corresponding AND-circuits 4, 5 respectively. By referring to the charts in the preceding section, it will be seen that the AND-circuits 4, 5 are responding in toto, to the code combination for the instruction indicated by the name of the output line thereof, to wit: SPM, BALR, BCTR, BCR, SSK, ISK, and SVC. In a similar fashion, the other groups of instructions in the RR format might be decoded by similar circuits so that all of the RR instructions would be decoded as illustrated in FIG. 88 by a plurality of circuits 1-4 therein. In the same fashion, a plurality of circuits of the type shown in FIG. 88 might be combined as illustrated by the circuits 1-4 of FIG. 89 whereby the entire instruction set of the system would be decoded.

It should be recalled that this is illustrative merely of a conceptionally simple, straightforward approach to decoding all of the instructions.

9.2.4.5 IOP Invalid Operand Decode FIG. 90 and FIG. 91

In a manner similar to the manner of decoding the instructions, invalid operand codes for each format may be sensed, and the presence of any invalid format utilized to generate an invalid operand signal. In FIG. 90, a signal is generated on an RR INV OP line by an OR-circuit 1 in response to either one of two AND-circuits 2, 3 each of which is operative only when there is a signal present on the ID RR line. The AND-circuit 3 recognizes the voids (in the charts of the preceding section) which are in the floating point columns of the RR format. An OR-circuit 4 preventing the AND-circuit 3 from responding for the Halve instruction. Similarly, the AND-circuit 2 senses the low and high voids in the branching and status-switching column of the RR format chart. Presence of signals on the NOT-2 and NOT-3 lines recognize the branching and status switching column, an AND-circuit 6 recognizes an instruction immediately below the Supervisor Call instruction, an AND-circuit 7 recognizes the void which comprises the same columns as the Divide, Add Logical, Subtract Logical instructions, and an AND-circuit 8 recognizes the void at the top of the column (in the rows adjacent to the various Load instructions.) Circuits similar to the circuit of FIG. 90 could be provided for each of the formats, as illustrated in FIG. 91. Thus, additional signals may be generated on an RX INV OP line, on an RS-SI INV OP line, and on an SS INV OP line. As illustrated in FIG. 91, all of these lines might be applied to an OR-circuit 9 so as to generate an invalid operation signal for the system on an ID INV OP line. Other variations in the circuitry could of course be provided, to thereby best satisfy the needs of any particular embodiment of a system in accordance with the present invention.

9.2.4.6 IOP Line Decode FIG. 98

The I decode circuit of FIG. 98 is illustrative merely, the output lines therefrom being illustrated in the chart of FIG. 92 through FIG. 97. Any manner of encoding known in the prior art may be utilized so that the various output lines may be energized in response to the proper instructions or formats, in an obvious manner. Alternatively, circuitry similar to that which is shown in complete detail with respect to the BOP decode may be utilized.

9.2.5 BOP CIRCUITS FIG. 76

The backup operation register is associated with an incrementer, a decoder, and (together with the IOP register) is involved in the general register out selection and the compare circuits, as described in section 9.2 with respect to FIG. 76

9.2.5.1 BOP Setting And Release FIG. 100 and FIG. 101

In FIG. 100, a signal is generated on a SET BOP line by an OR-circuit 1 in response to any one of four AND-circuits 2-5. The AND-circuits 2-4 respond to a TON T2 line in dependence upon three different conditions which may obtain in the system. The AND-circuit 2 must also sense a signal on a TSTS COMPLT & BR UNSUCC line so as to indicate that there will be no branching operation, therefore that the presently available instruction will be utilized. The AND-circuit 3 will operate when the I unit finishes the I unit execution or branch handling of a presently involved instruction as indicated by a signal on the I DONE line. The AND-circuit 4 responds to a signal which indicates that the last cycle of an IE (I unit type of execution, such as a channel communication operation) is about to be completed, due to a signal on the TON IEL line. The AND-circuit 5 operates similarly to the AND-circuit 4, but responds to the T2 latch being set as indicated by a signal on the T2 LCH line rather than the signal on the TON T2 line.

In FIG. 101, a signal is generated on a RELEASE BOP line by an OR-circuit 6 in response to either one of two AND-circuits 7, 8, or in response to a signal on a SCAN GT TO BOP line. The AND-circuits 7 and 8 are both responsive to a controlled A clock signal on the AC line, the AND-circuit 7 also requiring a signal on the SET BOP line, and the AND-circuit 8 requiring a signal on the INCR BR 1 FLD line. Thus, the OR-circuit 6 will generate a signal on the RELEASE BOP line during a scanning operation, or at A time whenever the BOP register is to be set, or whenever the BR1 field is being incremented by the IE unit.

9.2.5.2 BOP Register FIG. 102 and FIG. 103

As seen in FIG. 102, the 0 -bit position of the BOP register comprises a latch 1 which is set by an OR-circuit 2 in response to either one of two AND-circuits 3, 4 in dependence upon whether a scan operation or normal operation is involved, respectively. The AND-circuit 3 responds to a signal on the SCAN GT TO BOP line concurrently with a scan in control signal on the J REG 40 line. In normal operations, the AND-circuit 4 responds to a signal on the SET BOP line whenever there is a bit in the IOP register position 0 as indicated by a signal on the IOP 0 line. The AND-circuit 4 is also contingent upon an A running clock pulse on the AC line. The latch 1 is reset by an OR-circuit 5 in response to either one of the two AND-circuits 7, 6 in dependence upon scan or normal operation respectively. In other words, the AND-circuit 3 is associated with the AND-circuit 7, and the AND-circuit 6 is associated with the AND-circuit 4. Thus, during a scan operation if there is no signal on the J REG 40 line, then there will be a signal on NOT J REG 40 line so that the AND-circuit 7 will cause the latch to be reset, or to be left in the reset condition had it been previously reset. Similarly, if there is no signal on the IOP 0 line, then there will be a signal on the NOT IOP 0 line so that the AND-circuit 6 will cause the latch either to be reset or to remain reset.

The remaining bits 1-7 of the high-order portion of the BOP register are the same as that illustrated with respect to bit 0, as indicated by a block 8 which corresponds to bit 7.

The parity bit for the IOP register is simpler, comprising a latch 9 which is set by an OR-circuit 10 in response to either one of the two AND-circuits 11, 12, the AND-circuit 12 being operative by a signal on the SET BOP line concurrently with a signal on the RELEASE BOP line during normal operations, the AND-circuit 11 in response to a signal on the SCAN J REG 48 line concurrently with a signal on a SCAN GT TO BOP line.

Referring to FIG. 103, the R1 portion of the BOP register comprises a plurality of latches 1 each set by a corresponding OR-circuit 2 in response to related AND-circuits 3-5. The AND-circuits 3 are operative during scan operations in response to signals on related scan in lines such as the lines J REG 49. SCAN IN BOP 11, concurrently with the presence of a signal on the SCAN GT TO BOP line. The AND-circuits 4 are operative during normal operation of the type wherein the R1 field of the BOP register is to be incremented as indicated by a signal on the INCR BR 1 FLD line concurrently with a signal on the RELEASE BOP line and a signal on a corresponding one of a plurality of BOP incrementer lines such as the lines BR 1 INCR 8, BR 1 INCR 11. The AND-circuits 5 are operative during other normal operations in response to a signal on the SET BOP line concurrently with a signal on the RELEASE BOP line together with a signal on a corresponding one of a plurality of lines from the IOP register such as the lines IOP 8, IOP 11. The output of the latches 1 comprise signals on the lines BOP 8--BOP 11.

9.2.5.3 BOP R1 Incrementer FIG. 105

The BOP R1 incrementer (BR 1 INCR) comprises a plurality of latches 1-4 as shown in FIG. 105. Each of the latches is set by a corresponding AND-circuit 5-8, each of which responds to a B controlled clock signal on a BC line. The BC line is also applied to reset each of the latches 1-4. The theory of operation behind the incrementer is that it is to be considered that a four-bit field is to be incremented by 1; in other words, it is the same as if an absolute adder were being utilized, and a 1 were being supplied as one of the inputs to the adder. However, whatever the input is can be automatically converted to be an input which is one higher by logical means, as shown in FIG. 105. It should be borne in mind that the nomenclature of the present embodiment as such that bit 8 is the high-order bit of the BR 1 field, and bit 11 is the low-order bit thereof. Therefore, from the general rules of binary addition, the low-order bit, bit 11, will be reversed each time that a 1 is added thereto. Thus, if there was no bit 11 there will be a signal on the NOT-11 line so that the AND-circuit 5 will set the latch 1 thereby indicating a bit on the BR 1 INCR 11 line. Similarly, if either the 10 or the 11 bit is present but not both, then there should be a 10 bit in the final result; this is because if there is an 11 bit but no 10 bit then there will be a carry from the 11-bit position into the 10-bit position, but if both are present, then the 10 bit becomes a 0 with a carry into the 9 bit; on the other hand, if there is no 11 bit then there is no carry into the 10 bit but if the 10 bit is present in the first place then it should be continued. This fact is sensed by an EXCLUSIVE OR circuit 9. In a similar fashion, an AND-circuit 10 will recognize if both the 10 and 11 bits are present which will cause a carry into the 9 bit, and an EXCLUSIVE OR-circuit 11 will recognize whether there is a 9 bit without the 10 and the 11, or vice versa, so as to generate a 9 bit in the appropriate circumstance. An AND-circuit 12 in combination with an EXCLUSIVE OR-circuit 13 perform a similar function for the bit 8, so that a carry all the way from bit 11 into bit 8 can take place if there is no bit 8, or bit 8 will cause itself to continue if there will be no carry rippled to it.

9.2.5.4 BOP Parity Error Circuit FIG. 106

In FIG. 106, an EXCLUSIVE OR complex 1 (which is illustrated therein as a single circuit, but which is to be understood as being a circuit which senses the oddness or evenness of the total inputs thereto) will provide a signal whenever there is an odd number of bits present at the input thereto from the BOP register. This signal is applied to an inverter 2 which therefore will provide a signal to an AND-circuit 3 whenever the bits are even, the AND-circuit 3 responding at A time due to a signal on the AC line concurrently with a transfer of control from the I unit to the E unit due to a signal on the I TO E XFER line. The AND-circuit 3 will set a latch 4 which generated a signal on the BOP PAR ERROR line. The latch 4 is reset by a signal on the CHK RST line.

9.2.6 ER 1 CIRCUITS

The ER 1 circuits respond to the R1 field of the BOP register which comprises bits 8-11 thereof. The ER 1 register is utilized for controlling the input selection of the general registers, and is provided with an incrementer and a parity checking circuit as described in the succeeding sections, and in sections 5.2.0.0 with respect to FIG. 76

9.2.6.1 ER 1 Gating FIG. 99

In FIG. 99, a pair of AND-circuits 1, 2 generate signals on a GT BOP BITS TO ER 1 line and on a GT INCR BITS TO ER 1 line. The AND-circuit 1 is operative at A time due to a signal on an AC line, concurrently with a signal on an I TO E XFER line. The AND-circuit 2 is operative at B time due to a signal on an BC line concurrently with a signal on a INCR ER 1 line. Thus, during the I to E transfer, the AND-circuit 1 will cause the BOP register R1 field to be transferred to the ER 1 register, and during the incrementing of the ER 1 field, the ER 1 incrementer will be gated back into the ER 1 register. Either one of the AND circuit 1, 2 may operate an OR-circuit 3 which is also operable by either one of two signal lines: SCAN GT OUT or DISPLAY FPR. The OR-circuit 3 will generate a signal on a RELEASE ER 1 line.

9.2.6.2 ER 1 Register FIG. 104

As shown in FIG. 104, the ER 1 register comprises a plurality of latches 1, each of which may be set by a corresponding OR-circuit 2 in response to any one of three related AND-circuits 3-5. The AND-circuits 3 are operated by a signal on a SCAN GT ER 1 line concurrently with a corresponding one of a plurality of scan in lines such as the lines J REG 53 and J REG 56. The AND-circuits 4 are operated by the concurrence of signals on a GT BOP BITS TO ER 1 line and a RELEASE ER 1 line. Each of the AND-circuits 4 also requires a signal on a corresponding one of a plurality of BOP register output lines, as illustrated by lines BOP 8, BOP 11. The AND-circuits 5 are operated by signals on the GT INCR BITS TO ER 1 line concurrently with the signal on the RELEASE ER 1 line. Each of the AND-circuits 5 also requires a corresponding input from the ER 1 incrementer on a related line such as the E INCR 8 and E INCR 11 lines.

9.2.6.3 ER 1 Incrementer FIG. 107

The bits of the ER 1 register are applied to the ER 1 incrementer shown in FIG. 107, which is gated by a signal on an AC line. In all other respects, the ER 1 incrementer of FIG. 107 operates in a manner identical with the BR 1 incrementer shown in FIG. 105, therefore no further description is given thereof.

9.2.7 GENERAL REGISTER CIRCUITS FIG. 72

9.2.7.1 General Register Output Selection Circuits FIG. 108 Through FIG. 111

Selection of a particular general register, the output of which is to be applied to the general bus left or the general bus right is under control of the general register output selection circuits shown in FIG. 108 through FIG. 111, which circuits are described in detail in the ensuing sections.

9.2.7.1.1 B FIELD SELECTION OF GENERAL REGISTERS FIG. 108

The selection of a particular general register under control of the B field of the IOP register, which comprises bits 16-19 thereof, is illustrated in FIG. 108 wherein a plurality of first AND-circuits 1 predecode the high-order bits (16, 17) of the B field, and a plurality of AND-circuits 2 predecode the low-order bits of the field (18, 19). The outputs of the AND-circuits 1 and 2 are combined by a plurality of AND-circuits 3 in an obvious manner so as to provide a straight binary decoding of the four input bits to thereby generate a signal on one out of the 16 possible B FLD SEL GR lines 0-15. As an example only, a NOT 16 together with a 17 will cause the second AND-circuit 1 from the top of FIG. 108 to generate a signal indicating that a 01 combination is indicated for the high-order half. Similarly, the second AND-circuit 2 from the bottom of FIG. 108 will respond to the absence of both bit 18 and bit 19 so as to indicate that the low-order half has a value of 00. These are combined in a second AND-circuit 3 from the bottom of FIG. 108 so as to generate a combination 0100 which thereby designates general register 8 as the register which is to be selected.

9.2.7.1.2 R2-X FIELD SELECTION OF GENERAL REGISTERS FIG. 109

The circuit of FIG. 109 is nearly identical to the circuit of FIG. 108, the difference being that bits 12-15 (and the complements thereof) of the IOP register are applied to the circuit of FIG. 108, whereas bits 16-19 (and the complements thereof) of the IOP register are applied to the circuit of FIG. 108. The output of the circuit of FIG. 109 will be a signal on any one of the 16 possible R2-X FLD SEL GR lines 0-15.

9.2.7.1.3 BR 1 FIELD SELECTION OF REGISTERS FIG. 110

The circuit of FIG. 110 is an alternative to the circuit shown in FIG. 108 and FIG. 109 in that, rather than a straightforward low order, high order, and combinational type of decoding, the low-order bit and the high-order bit are combined, and then these are in turn combined with the results of combinations of the two middle order bits (9,10). In addition, the circuit of FIG. 110 may respond in the alternative to the output of the BOP register, or to the coded combination designated by the Maintenance switches. A first plurality of AND-circuits 1 are gated by a signal on a BR 1 INH line, or a second plurality of AND-circuits 2 are gated by a signal from an OR-CIRCUIT 4 which responds to signals on either the DISPLAY FPR line or the DISPLAY GR line.

Each pair of AND-circuits 1, 2 operates a corresponding OR-circuit 5 which generates a signal on a corresponding one of a plurality of lines A-H for application to selected ones of 16 different AND-circuits 6 where the lines combined so as to generate signals on corresponding BR 1 SEL GR lines 0-15. For instance, when the AND-circuits 1 are operative, the B signal is generated in response to a 0 xx1 value and the F signal is generated in response to an X01X value, a combination of which is a BR 1 SEL GR 3 as generated by the fourth AND circuit from the top in FIG. 110, a 3 having a binary representation of 0011. On the other hand, a conversion from one binary code to another is involved whenever the AND-circuits 2 are operative inasmuch as the MS lines are not applied to the AND-circuits 2 in such a manner as will create a straight binary conversion when the outputs therefrom are combined in the AND-circuits 6. The conversion is illustrated in the following chart: ---------------------------------------------------------------------------

BINARY DECIMAL BITS VALUE __________________________________________________________________________ 0 0 0 0 0 1 0 0 0 1 0 0 1 0 2 1 0 1 0 3 0 0 0 1 4 1 0 0 0 5 0 0 1 1 6 1 0 1 1 7 0 1 0 0 8 x x 1 1 1 1 15 __________________________________________________________________________

From the table, it can be observed that the MS bits 8, 9, 10, and 11 have equivalent binary weight values of 1, 8, 2, and 4, respectively, when considered in the light of the manner in which the BR1 SEL TR signals are generated therefrom.

As described in section 9.2.7.1.6, hereinafter, the selection of a general register for output of the GBR or GBL under control of R1 plus 1 is generated logically in FIG. 113 in response to the BR 1 SEL GR signals generated in FIG. 110 in combination with a GT GR R1 PLUS 1 OUT signal which is generated in FIG. 112. In other words, the BR 1 SEL GR lines are used both for the R1 and for the R1 plus 1 outgating control.

9.2.7.1.4 GENERAL REGISTER OUTGATING CONTROL FIG. 111

In FIG. 111, a signal which indicates that the general registers are to be gated out to the GBL and GBR is generated on a GROUT line by a latch 1 which is set by an OR-circuit 2 in response to an AND-circuit 3 or in response to a signal on a SCAN GROUT line which may be energized as a result of FLT operations. The AND-circuit 3 is operative at A time due to a signal on the AC line at the time of I to E transfer as indicated by a signal on the I to E XFER line during instructions which are of the GROUT type as indicated by a signal on the BD GROUT CL line. Additionally, there must be no interrupt reset as indicated by a signal on a NOT IRPT RST line. The latch 1 is reset by an OR-circuit 4 in response to a signal on the CPU RST line or in response to an AND-circuit 5 which in turn is operated by an OR-circuit 6. The OR-circuit 6 responds to an AND-circuit 7 or to a signal on any one of the following lines: E TOF GROUT, IRPT RST, IE TOF BLK T1M. The AND-circuit 7 responds during the last cycle of operations involving the Execute instruction as indicated by a signal on the XEQ SEQ LCH line concurrently with a signal on the IOP LOADED line. Thus, the latch 1 will be set as a result of a scan or during GROUT class instructions at I to E transfer provided there is no interrupt reset, and the latch 1 will be reset by a CPU reset or by the Execute, E unit, interrupt, and IE controls associated with the OR-circuit 6.

9.2.7.1.5 GATE GENERAL REGISTER OUT CONTROLS FIG. 112

In FIG. 112, an OR-circuit 1 responds to a signal on the GROUT line as well as the signal on a DISPLAY GR (display general registers) line or a signal on a VFL GT GR TO RBL line. The OR-circuit 1 is also responsive to an AND-circuit 2 which is operative during the second instruction unit sequence cycle as indicated by a signal on a T2 line, concurrently with the absence of bit 2 in the IOP register as indicated by a signal on the NOT IOP BIT 2 (NOT DEC OR FLP) line. As indicated parenthetically in FIG. 112, the NOTIOP BIT 2 line has a signal thereon in other than decimal and floating point operations. The OR-circuit 1 generates a signal on the GT GR TO RBL line which causes the general registers to be gated to the register bus latch, as described with respect to FIG. 72 and FIG. 75 in section 5.2.0.0 hereinbefore.

Referring again to FIG. 76, the general registers may be gated to the GBL or to the GBR under the control of any one of four factors: R1, R2-X, R1 & 1, and B, control signals for which are generated in FIG. 112.

In FIG. 112 an OR-circuit 3 may be operated during a T2 sequence or when there is a signal on a GROUT line, or when general registers are to be displayed as indicated by a signal on the DISPLAY GR line The OR-circuit 3 generates a signal on a GT GR R1 OUT line, which will cause the general register indicated by the R1 field to be gated out.

A signal is generated on a GT GR R2-X OUT line by an OR-circuit 4 in response to any one of four AND-circuits 5-8 depending upon different conditions which may obtain. During RR or RX instructions in which the R2-X field of the instructions does not equal 0, the AND-circuit 5 will operate during the T1 sequence of the I unit in response to signals on the ID RR OR RX, circuit 6 will also respond to a signal on the T1 line when concurrent with the signal on a NOT RX OR RS SHIFT NOT RR .sup.MPY line. The AND-circuit 7 responds to a signal on the GROUT line concurrently with a signal on the GT R2 FLD line. The AND-circuit 8 is operative during a T2 sequence cycle as indicated by a signal on the T2 line during RR instructions as indicated by a signal on the ID RR line.

A register adjacent to the register specified by R1 may be called into operation by a signal on a GT GR R1 +1 OUT line which is generated by an OR-circuit 9 in response to either one of two AND-circuits 10, 11. The AND-circuit 10 responds to a signal on the GROUT line concurrently with a signal on the RX OR RS SHIFT OR RR MPY lines. The AND-circuit 11 is operative during the T2 sequencing cycle in response to a signal on the T2 line concurrently with a signal on the NOT INH R1 +1 FLD line.

B field control is established by a signal on a GATE GR B OUT line which is generated by an OR-circuit 12 in response to either one of two AND-circuits 13, 14. The AND-circuit 13 responds to signals on the following lines: T1, B 0, NOT ID RR, and NOT GROUT. The AND-circuit 14 responds to signals on the following lines: SS OP, B 0, NOT VFL SEL GR 1 OUT, and NOT VFL SEL GR 2 OUT.

It should be noticed that various ones of the AND circuits shown in FIG. 112 are inhibited whenever corresponding control fields equal 0; thus, the AND-circuit 5 will be inhibited unless there is a signal present on the R2-X 0 line, and the AND-circuits 13, 14 will be inhibited unless there is a signal present on the B 0 line. This is due to the fact that in the architectural definition of a system in accordance with the present invention, specification of general register 0 in certain conditional branching instructions absolutely prevent a branching operation from taking place, rather than calling for general register 0 to control the condition thereof, as set forth in said System/36U Manual.

9.2.7.1.6 GENERAL REGISTER OUT GATES FIG. 113

The general register outgates shown in FIG. 113 comprise two portions, one which transmits to the general bus left (GBL) and the other of which (shown at the bottom of FIG. 113) transmits data to the general bus right (GBR). The GBL portion of the general register gates comprises essentially a plurality of OR-circuits 1, 2 each of which responds to a related pair of AND-circuits 3, 4, the AND-circuits 3 relating to R1 control and the AND-circuits 4 relating to D field control. In addition, the OR-circuits 2 may respond directly to signals on the VFL SEL GRI OUT and VFL SEL GR 2 OUT lines. The AND-circuits 3 are gated by a signal on the GT GR R1 OUT lines so as to pass a corresponding signal on a related one of a plurality of BR 1 SEL GR lines. The AND-circuits 4 are gated by a signal on a GT GR B OUT line so that each of them will pass a related signal or on a corresponding one of a plurality of B FLD SEL GR lines to the OR-circuits 1, 2.

At the bottom of FIG. 113, a plurality of OR-circuits 5 generate signals on corresponding odd numbered ones of a plurality of GT GR TO GBR lines 1,3,--15, and a plurality of AND-circuits 6 generate signals on even numbered ones of the GT GR TO GBR lines 0,2--14. Each of the OR-circuits 5 is responsive to a related pair of AND-circuits 7, 8 in dependence upon the alternative presence of a signal on either the GT GR RX-2 OUT line or on the GT GR R1 +1 OUT line respectively. Each of the AND-circuits 7 respond to a related odd number bit of the R2-X field on a corresponding one of a plurality of R2-X SEL GR lines. The AND-circuits 8 each respond to a related even numbered bit of the BR 1 field on a corresponding one of a plurality of BR 1 SEL GR lines. In operation, either the R2-X or the R1+1 control signal will be present, so that either the R2-X or the BR 1 field will be utilized to control the OR circuits 5. It should be noticed that R1+1 is a valid designation of a register only when the register selected by the BR 1 field is an even numbered register, and therefor, the even number designation by the R1 field is utilized to specify the next higher register to indicate selection under control of the R1&1 factor. In this manner, the BR 1 field may select general register 0 for application to the GBL, and at the same time the same designation might be used to select general register 1 for application to the GBR; selection of other pairs of registers is similarly obtained.

9.2.7.2 General Buses FIG. 114

The general bus left (GBL) is shown at the top of FIG. 114 to comprise the output of a plurality of OR-circuits 1, 2, each of which relates to a particular one of the 32 data bits or four parity bits of the GBL. Each of the OR-circuits 1,2 responds to 16 different AND-circuits 3, each of which corresponds with one of the general registers 0-15. Thus, the oR-circuit 1 responds to bit 0 of a selected one of the general registers, selection of the particular general register being under control of a signal on one of the lines GT GR 0 TO GBL, GT GR 1 TO GBL,--GT GR 15 TO GBL. Similarly, the OR-circuit 2 will respond to bit 31 at the input of a selected one of 16 different AND-circuits 3 in dependence upon which one of the GT GR TO GBL lines has a signal thereon. In a similar fashion, each of the other bits 1-30 of all 16 of the general registers are applied to similar AND-circuits 3 so as to generate a signal on a related one of a plurality of GBL lines by OR circuits similar to the OR-circuits 1,2. In addition, the four parity bits of each of the general registers are gated by similar circuitry, as illustrated by the AND-circuit 4 and the OR-circuit 5. Thus, one general register is selected for gating to the GBL, and one OR circuit for each bit of the register will generate signals in accordance with the contents of the register which has been selected, for signals appearing on the GBL lines; additionally, the four parity bits of the selected register will also be applied to related parity bits on the GBL. At the bottom of FIG. 114 is illustrated the general bus right (GBR) which comprises circuitry identical to that of the GBL, except for the fact that it is controlled by signals on a plurality of GT GR TO GBR lines.

9.2.7.3 General Register Input Controls

9.2.7.3.1 ER 1 REGISTER INPUT SELECTION FIG. 116

The circuit of FIG. 116 operates in a manner identical with that of FIG. 110, the only difference being the provision of a pair of OR-circuits 1,2 which respectively correspond to selection of general register 1 or selection of general register 2 in that the OR circuits generate signals on the ER 1 SEL GR line 1 and the ER 1 SEL GR line 2 respectively. These OR circuits permit the signals on the VFL SEL GR 1 IN line and on the VFL SEL GR 2 IN line to select general registers directly under control of the variable field length portion of the system. These two lines also operate an AND-circuit 3 which is applied to two inverters 4,5, the purpose of which is to inhibit the operation of the remainder of the circuitry shown in FIG. 116. In the event that there is no signal present to either of the inverters 4,5, one of a pair of AND-circuits 6,7 will be operative so as to provide gating signals for a plurality of AND-circuits 8,9, respectively. Specifically, if there is no variable field length input, the AND-circuit 7 will operate in response to a signal on a NOT MAN LOAD line, which indicates that manual operation of the circuit is not involved. If the AND-circuit 7 does operate, then an inverter 10 will prevent the AND-circuit 6 from operating, so that there will only be one or the other of two signals present on corresponding lines GT EOP and GT MS. On the other hand, if there is no signal on the NOT MAN LOAD line, then the inverter 10 will permit the AND-circuit 6 to generate a gating signal on the GT MS line whereby manual input representations on a plurality of MS lines (the same lines as are utilized in FIG. 110) will gate the corresponding AND-circuits 8, which will cause generation of appropriate signals at the output of one of a plurality of OR-circuits 12 and also at the output of one of a plurality of OR-circuits 13. Combinations of OR-circuit output are achieved by means of a plurality of AND-circuits 14, in the same fashion as described with respect to FIG. 110 in section 5.2.13.3 hereinbefore. In the same fashion as in the previous section, the encoding of the MS lines is converted by the circuit of FIG. 116, said coding being such that the MS bits 1,2,4,8 respectfully correspond to a binary value of 8,4,2 and 1 in the generation of a particular one of the ER 1 SEL GR lines 0-15. Additionally, the outputs of the OR-circuits 13 are utilized directly as floating point register selecting lines by providing appropriate signals on the ER 1 SEL FPR lines 0,2,4,6. There are eight floating point registers in the system, but when selected by the ER 1 field, they must be selected in pairs; therefore, the four lines will select them in the following pairs: 0,1; 2,3; 4,5; 6,7.

9.2.7.3.2 GENERAL REGISTER IN GATES FIG. 117

Any one of the 16 general registers may be selected by a signal on a corresponding one of the SET GR lines 0-15 as shown in FIG. 117. Each of these lines is energized by a corresponding AND-circuit 1,2,3 the AND-circuits 3 responding only to a pair of gating signals and to a signal on a corresponding one of the ER 1 SEL GR lines. The AND-circuits 1,2 respond to similar signals as the AND-circuits 3, but also are responsive to scan signals by means of a pair of OR-circuits 4,5 respectively. Thus, the OR-circuit 4 responds to a signal on a SCAN SET GR O line, and the OR-circuit 5 responds to a signal on a SCAN SET GR 4 line. All of the AND-circuits 1-3 are operative only at early B time due to a controlled clock signal on the EBC line, and are also conditioned upon receiving a signal on the GT IN GR line which indicates the presence of data to be gated in to one of the general registers. The AND-circuits 1-3 each generate a signal on a corresponding 1 of a plurality of SET GR lines 0-15.

9.2.7.4 General Registers FIG. 118

The general registers are illustrated in breakaway fashion in FIG. 118. Each of the general registers comprises a plurality of latches 1 each of which is set by a corresponding AND-circuit 2. Each of the latches 1 is reset, and each of the AND-circuits 2 is conditioned by the setting signal for the corresponding register: for instance, general register 0 is conditioned by a signal present on the SET GR 0 line, and general register 1 is operated by a signal on a SET GR 1 line, and so forth. Each of the AND-circuits 2 is also responsive to a related bit of the K register as manifested by signals on a plurality of K REG lines.

9.2.8 OP TEST AND COMPARE CIRCUITS FIG. 119 THROUGH FIG. 121

As described in section 9.2 with respect to FIG. 76, the test and compare circuits shown in FIG. 119 through FIG. 121 compare several of the instruction fields with one another, and test certain fields to see if they equal 0.

9.2.8.1 Op Zero Test & BR 1 Compare FIG. 119

In FIG. 119 is shown a plurality of OR-circuits 1-3 each of which responds to a four bit instruction field. The OR-circuit 1 responds to BOP bits 8-11 which comprises the BR 1 field, and provided there is any one of the signals present, the OR-circuit 1 will generate a signal on a BR 1 0 line. The OR-circuit 2 responds to bits 12-15 of the IOP register, which bits comprise the R2-X field, and will generate a signal on a R2-X 0 line in the event that there is at least one signal present on the IOP lines 12-15. In the same fashion, the OR-circuit 3 will generate a signal on a B 0 line in the event that any one of the IOP bits 16-19 are present on corresponding IOP lines.

At the bottom of FIG. 119, an inverter 4 generates a signal on a BR 2 =IR2 line, in response to the absence of a signal from an OR-circuit 5. The OR-circuit 5 compares bits 8-11 of the BOP register with bits 12-15 of the IOP register, which bits comprise the R1 and R2 fields of an instruction, respectively. The OR-circuit 5 responds to a plurality of EXCLUSIVE OR-circuits 6-7, some of which are not shown for circuit simplicity, in such a fashion that each of the EXCLUSIVE OR-circuits 6-7 must have no output therefrom, thereby having no output from the OR-circuit 5 so that there will be an output from the inverter 4 when the two fields are equal. The EXCLUSIVE OR circuit 7 is gated by an AND-circuit 8 in response to a signal from an inverter 9, the inverter being prevented from gating the AND-circuit 8 whenever there is a signal on a BD DBL REG COMP line. This same line will operate an OR-circuit 10 which is utilized to gate an EXCLUSIVE OR circuit 11 thereby to operate an OR-circuit 12.

9.2.8.2 Instruction Compare Block FIG. 120

At the top of FIG. 120 is shown a latch 1 which is set by an AND-circuit 2 so as to generate a signal on a BR 1=IR2 LCH line in dependence upon there being a signal on the BR 1=IR2 line whenever R2 does not equal 0 as indicated by a signal on the R2-X 0 line. The AND-circuit 2 is also controlled by a signal on a NOT AC line which first resets the latch and then will set the latch provided the other conditions of the AND-circuit 2 are met.

The BR 1=IR2 line is also applied to an AND-circuit 3 which, together with another pair of AND-circuits 4,5 will cause an OR-circuit 6 to set a latch 7. Each of the AND-circuits 3-5 is effective to set the latch 7 just following A time due to the fact that a signal on the NOT AC line is utilized to reset the latch and thereafter to gate one of the AND-circuits 3-5. These AND circuits are also dependent upon the appearance of a signal on the BD COMP REQ line, which indicates that a compare is required to be sure that the instruction being decoded by the BOP circuits will not store results in a GR to be used by the IOP instruction. The AND-circuit 3 is operative in response to a signal on a ID KEY OPS line, the AND-circuit 4 is additionally responsive to a signal on the R2-X O line and an instruction responsive signal on an ID (RR + RS + RX), which indicates an RR, or an RS, or an RX instruction being decoded by the IOP circuits. The AND-circuit 5 responds to R1 being equal to B providing that B is not equal to 0 as indicated by signals on the BR 1=IB line and the B 0 line. The AND-circuit 5 is also conditioned by an RS or an RX instruction as indicated by a signal on a ID RS OR RX line. Thus, in the event that any of the AND-circuits 3-5 are operated, the latch 7 will be set, indicating that a blocking is to occur, and therefore there will be no signal on a NOT COMP BLK LCH line; this line is used in various parts of the system to permit operations to continue so long as the fields which are compared are not equal; thus, when the fields are equal, the latch is set and this signal will disappear thereby preventing faulty operations which might include overlapping of fields.

9.2.8.3 ER 1=IR2-X Compare FIG. 121

Another compare circuit is shown in FIG. 121 to comprise essentially a latch 1 which is set by an AND-circuit 2 so as to generate a signal on an ER1=IR2-X line. The AND-circuit 2 is conditioned by a signal on a NOT LCH ER 1 INCR, which signal is utilized both to reset the latch 1 and to gate the AND-circuit 2 in such a fashion that the latch is first reset and immediately set provided that there is a signal at the other input of the AND-circuit 2 from an inverter 3. The inverter 3 responds to an OR-circuit 4 which in turn recognizes outputs from any one of four EXCLUSIVE OR circuits 5, each of which corresponds to respective bits of the R2-X field and the R1 field of successive instructions. Assuming a first instruction is being executed in the E unit, and the results are to be stored in a register specified by the R1 field, a second instruction will be undergoing analysis in the I unit, and an operand fetch may result so as to prepare the E unit for executing the second instruction. However, if the results of the first instruction are to be stored in the same register as the source of the second instruction, then erroneous results will be achieved. Therefore, the ER 1 register is utilized as a source for the R1 field of the first instruction while the IOP register is used as a source for the R2-X field of the second instruction. Each of the EXCLUSIVE OR circuits 5 senses a related pair of bits so that the two fields are compared on a bit-by-bit basis, and in the event that both fields are equal there will be no input to the OR-circuit 4 so there will be an output from the inverter 3 to the AND-circuit 2. Thus, if both fields are equal the latch 1 will indicate that fact by a signal on the ER1=IR2-X line.

9.2.9 BOP DECODE CIRCUITS FIGS. 122-130

The BOP decode is shown in FIG. 122 through FIG. 130, and comprises a plurality of individual decoding circuits which first partially decode the instructions and then combine the partial decode results so as to generate a plurality of different signal lines in response to appropriate conditions. Each of the lines are illustrated in the charts of the decoders shown in FIG. 92 through FIG. 97

9.2.9.1 BOP Inputs To Decoders FIG. 122

In FIG. 122 a plurality of AND-circuits 1 provide predecode signals on BD lines in response to various input combinations from BOP, all in an obvious manner.

9.2.9.2 BD Specification Interrupt Circuit FIG. 123

9.2.93 BD Block T1-T2 Control FIG. 124

In FIG. 124 is shown circuitry which decodes the various instruction bits so as to generate signals on the BD BLK T1 line and the BD BLK T2 line. The circuit arrangement of FIG. 124 is such as will generate the output signals therefrom in each case as such signals are needed, as indicated by the instruction decode line charts of FIG. 92 through FIG. 97. The manner of the decoding is straightforward, it being a combination of what is sometimes called "truth table decoding" and instruction format type of decoding. For instance, the RR, RX, et cetera instructions are utilized in that figure, as are the partial decode bits of FIG. 122.

9.2.9.4 BOP Decode-1 Circuit FIG. 125

In FIG. 125, a plurality of OR-circuits 1 each decode a signal in response to the particular instructions relating thereto as called for in the instruction decode line charts of FIGS. 92-97, and an AND-circuit 2 responds to an appropriate instruction bit so as to recognize an "execute" instruction by generating a signal on a BD XEQ line. As in the case of FIG. 124, the OR-circuits 1 and the circuitry related with each of them, use a combination of format and truth table decoding so as to recognize the various conditions under which signals have to be generated on the respective lines; BD I EXEC, BD E EXEC, BD STR REQ, BD PRIV INST.

9.2.9.5 BOP Decode-2 Circuit FIG. 126

In FIG. 126, signals appear on the instruction decode lines BD, resulting in signals on the outgoing BD INS KEY, BD GROUP, BD EN INS KEY, and BD EN KEY OPS lines in accordance with the AND and OR circuits.

At the bottom of FIG. 126 an OR-circuit 8 will generate a signal on a BD GROUT CL line in response to any one of 5 AND-circuits 9-13 each of which recognizes various elements shown in the table of section 9.2.4.1, hereinbefore. Additionally, the OR-circuit 8 is responsive to a signal on an RX DIVIDE line which is generated by the AND-circuit 7. In each case, the general registers are utilized as a source of operands or operand addresses in the performance of the various instructions which can be sensed by the OR-circuit 8. The necessity of utilization of the general registers is verified for the various instructions in the instruction decode line charts of FIG. 92 through FIG. 97, which indicates the use of the signal on the BD GROUT CL line, by reference to the architectural definition of a system in accordance with the present invention in said System/360 Manual.

9.2.9.6 BOP Decode Compare Required FIG. 127

In FIG. 127, a signal is generated on a BD COMP REQ line by an OR-circuit 1 in response to any one of three AND-circuits 2-4 which respond respectively to RR, RX, OR RS instructions due to signals applied thereto on the BDRR, BD RX, and BD RS lines, respectively. The AND-circuits 2, 3 respond to respective OR-circuits 5, 6 and the AND-circuit 4 responds to an AND-circuit 7, the operation of which again is based on well-known truth table decoding so as to generate a signal on the BD COMP REQ line for each instruction calling for same in the instruction decode line charts of FIG. 92 through FIG. 97, utilizing the appropriate op codes as illustrated in the chart of section 9.2.4.1, hereinbefore.

9.2.9.7 BOP Decode-3 Circuit FIG. 128

In FIG. 128, a signal is generated on a BD DBL REG COMP line by an OR-circuit 1 in response to either one of two AND-circuits 2, 3 each of which responds to BOP decode format and partial decode bits so as to generate an output from the OR-circuit 2 in response to those instructions shown in FIG. 92 and in FIG. 94 which require a double register comparison due to the possibility of selecting an implied register with an explicitly identify register, or in selecting an explicit register alone. The remaining circuitry of FIG. 128 comprises a plurality of AND-circuits 4-6 which generate signals relating to the specific instructions on corresponding lines: BD LD MPL, BD BR & LNK, BD BR ON COND. The circuits of FIG. 128 also include an AND-circuit 7 which generates a signal on a BD RR BR ON COND line, and an OR-circuit 8 which generates a signal on a BD RS OR B6 & NOT B7 line. The appropriateness of the respective inputs to the circuits 2-8 in FIG. 128 is illustrated in the instruction chart of section 9.2.4.1.

9.2.9.8 BD Mark And Key Circuits FIG. 129

In FIG. 129, an AND-circuit 1 will cause a plurality of OR-circuits 2-5 to generate mark signals on corresponding BD SET MK lines in case of RX instructions where an entire 64-bit storage word is to be stored. Each of the OR-circuits 2-5 might also be operated by a corresponding AND-circuit 6-9, and the OR-circuits 2-5 may be operated by pairs of respective AND-circuits 10, 11. The AND-circuits 10 and 11 are gated by an AND-circuit 12, and by the absence of an H register bit 21 or the presence of an H register bit 21, respectively, in the alternative. The AND circuits 6-9 are all gated by an AND-circuit 13 in respond to various combinations of the H register setting in a binary fashion, such that the absence of both bits 21 and 22 of the H register will cause the setting of the lowest 2 bytes of a storage word by generating a signal on the BD SET MK 0-15 line, the presence of both bits causing the OR-circuit 5 to generate a signal on the BD SET MK 48-63 line. The other OR-circuits 3, 4 operate in a corresponding fashion.

At the bottom of FIG. 129, an AND-circuit 14 senses all the bits of a Set Key instruction or an Insert Key instruction except for bit 7, whereby the AND circuit generates a signal which indicates either the set or the insert instruction on a SET-INS KEYS line. This signal is used to gate a plurality of AND-circuits 15, such that in the event that there is any one of the H register bits 20-23 present on corresponding H REG lines, the AND circuit 15 will cause an OR-circuit 16 to generate a signal on a INV KEY SPEC line. This indicates that the address for the operation did not have bits 20-23 equal to zero, as called for by the architectural definition in said System/360 Manual.

9.2.9.9 CPU Set Marks FIG. 130

In FIG. 130, a plurality of OR-circuits 1 each generates a signal on a corresponding one of a plurality of SET MARK lines. Each OR circuit is responsive to an AND-circuit 2 which is gated by a signal on the I TO E XFER line and a corresponding one of the BD SET MK lines. The OR-circuits 1 are also responsive to a pair of OR-circuits 3, 4 so that the OR circuits relating to bits 0-15 and bits 16-31 will be set in response to a signal on either one of the lines IE SET MK 0-31 or IRPT SET MK 0-31. Similarly, the OR-circuits 1 relating to bits 32-47 and 48-63 will be operated in response to signals on either one of the lines IE SET MK 32-63 or IRPT SET MK 32-63. Thus, set mark signals can be generated so as to permit storing of two bytes at a time or more, in dependence upon energizing more of the OR circuits in FIG. 130.

9.A PSW REGISTER

The PSW register is fully illustrated in terms of its functions in the I unit data flow illustration of FIG. 72. In control of the PSW, bits 0-39 are handled independently of bits 40-63. This is due to the fact that bits 40-63 comprise the ICR, and in fact, are referred to herein as bits 0-23 of the ICR. Various portions of the PSW are handled differently insofar as permissive changing of the setting therein is concerned. Specifically, the PSW comprises a plurality of latches, and the latches are responsive to new inputs only when there is an UNLCH signal for the appropriate latch. These signals are generated for portions of the PSW as follows:

bits 0-7 system mask

bits 8-15 keys and status bits

bits 16-23 interruption code-channel identification

bits 24-31 interruption code

bits 32 and 33 instruction length code

bits 34 and 35 condition register

bits 36-39 program mask

parity for bits 32-39.

In addition, the ICR is divided into bits 0-19 and 23, and bits 20-22. Bits 20-22 comprise the ICR LO whereas bits 0-19 comprise the high-order portion of the ICR; bit 23 must always be a zero or an instruction boundary specification will result since bit 23 will specify an odd byte, and all instructions must be an integral number of even number bytes and therefore must be on even byte boundaries. The details of the PSW register are disclosed in FIG. 131-139, and described in the following sections.

9. A.1 GATING LINES FOR PSW 0-39: FIG. 131

In FIG. 131, a plurality of UNLCH signals are generated by a corresponding plurality of OR-circuits 1-8. Each of the OR circuits corresponds to a different group of the PSW, or a parity bit therefor. Each of the OR-circuits 1-8 may be operated by an AND-circuit 9 which is responsive to a signal on a set PSW 0-39 line, which is energized either by maintenance controls, by the interruption controls when an initial program load PSW, or an interrupt new PSW is being loaded, or by the IE unit when a set PSW instruction is being executed. The AND circuits 9 are operated at A time by a controlled A clock signal on an AC line. Each of the OR-circuits 1, 3-7 is also operable by one or more additional AND-circuits 10-20. Each of the AND-circuits 10-20 relates to a different condition under which the particular group of the PSW is to be set. Each of the AND-circuits 10-20 is responsive to the signal on the AC line.

An AND-circuit 10 will cause the OR-circuit 1 to generate a signal on the UNLCH PSW 0-7, P line in response to a signal on the SET SYS MASK line. An AND-circuit 11 will cause the OR-circuit 3 to generate a signal on the UNLCH PSW 16-23, P line in response to a signal on the IRPT RST line. A trio of AND-circuits 12, 13, 14 are each effective to cause an OR-circuit 4 to generate a signal on the UNLCH PSW 24-31, P line in response to signals on the T2 SET PSW, T1 SET PSW, or EXEC SET PSW lines. The operation of the OR-circuits 3, 4 is described in more detail in the section relating to interruptions.

The OR-circuit 5 can generate a signal on the UNLCH PSW 32, 33 line in response to signals on the SET LGTH TO 00 line or the SET LGTH PSW line. The OR-circuit 6 generates a signal on the UNLCH PSW 34, 35 line in response to AND-circuit 17-19 having inputs thereto on the E SET CR, IE SET CR, or SET PGM MASK lines, respectively. The OR-circuit 7 will generate a signal on the UNLCH PSW 36-39 line in response to an AND-circuit 20 having an input on the SET PGM MASK line. Each of the OR-circuits 1-8 is also responsive to a signal on the SCAN IN PSW line.

9.A. 2 PSW 0-7: SYSTEM MASK FIG. 132

In FIG. 132, a plurality of latches 1 comprise register bit positions for PSW bits 0-7, and the parity bit therefor. Each of the latches 1 is set by an OR-circuit 2 in response to either one of a pair of related AND-circuits 3, 4. The latches are reset, and the AND-circuits 3, 4 are gated by the signal on the UNLCH PSW 0-7, P line. The AND-circuits 3 are operated in response to a signal on a SET SYS MASK line concurrently with a corresponding bit on the E unit address bus which comprises lines E UNIT ADR 0-E UNIT ADR P. The AND-circuits 4 are gated by a signal from an OR-circuit 5 which is operated by either the signal on the SET PSW 0-39 line, or by a signal on the SCAN IN PSW line. Each AND-circuit 4 also responds to a corresponding bit of the J register on J REG 0-J REG P 0-7 lines.

9.A.3 PSW 8-15: KEYS, A, M, W, P FIG. 133

In FIG. 133, bits 8-15 (and the parity bit therefor) of the PSW comprise a plurality of latches 1, each of which may be set by a corresponding AND-circuit 2 when gated by an OR-circuit 3 in response to the SET PSW 0-39 or SCAN IN PSW signals. Each AND-circuit 2 also requires a related bit from the J register on a plurality of J REG lines 8 -P 8-15. The latches 1 are reset, and the AND-circuits 2 are gated, by a signal on the UNLCH PSW 8-15, P line.

9.A.4 PSW 16-31: INTERRUPTION CODE FIG. 134

As shown in FIG. 134, bits 16-31 of the PSW, and the parity bits therefor, comprise a plurality of latches 1-7, the latches 1-5, and AND circuits relating thereto being reset and gated by the signal on the UNLCH PSW 16-23, P line, and the latches 6-7 and the AND-circuits 23, 24 related thereto being reset by, and gated by, the signal on the UNLCH PSW 24-31, P line.

The latches 1, 2 relating to bits 16-20 of the PSW are set by corresponding AND-circuits 8, 9 in dependence upon a gating signal from an OR-circuit 25 in response to either the set PSW 0-39 or SCAN IN PSW line. Each of the AND-circuits 8, 9 also respond to related bits 16-20 of the J REG. Bits 16-20 of the interruption code are not utilized in the control of the system in accordance with the present embodiment, but actually provide for expansion of the capabilities of such a system as desired.

Bits 21-23 of the PSW relate to channel identification of input/output interruptions. These bits are manifested in the latches 3-5 which are set by corresponding OR-circuits 10-12 in response to pairs of related AND-circuits 15-17, 20-22. The AND-circuits 15 require the gating signal from the OR-circuit 25, and are otherwise responsive to related bits 21-23 from the J REG. The AND-circuits 20-22 utilize a gating signal from an AND-circuit 26 which in turn responds to concurrence of signals on the CH IRPT PRI and IRPT RST lines. The AND-circuits 20-22 are thus made responsive to related interrupt code bits on a plurality of lines such as the CH IRPT CD 4, CH IRPT CD 2, CH IRPT CD 1, and CH IRPT P lines. Bits 24-31 of the PSW are utilized for the interruption code of all types of interruptions, and are manifested in a plurality of latches 6-7 each of which is settable by a corresponding OR-circuit 13-14 in response to related pairs of AND-circuits 18-19, 23-24. The AND-circuits 18 are gated by the output of an AND-circuit 27 which is responsive to the presence of the gating signal from the OR-circuit 25 at A time due to a signal on the AC line. The AND-circuits 18-19 are thus made responsive to corresponding bits of the J register such as J REG 24-J REG P 24-31. The AND-circuits 23-24 respond to the output of the interruption code circuitry of FIG. 359 through FIG. 361 on the IRPT CODE 24-IRPT CODE P lines.

9.A.5 PSW 32-35: LENGTH, CONDITION CODE FIG. 135 AND FIG. 136

In FIG. 135, bits 32 and 33 of the PSW register which comprise the length code, are represented by a pair of latches 1, 2 each of which is settable by a corresponding OR-circuit 3, 4 in response to a related pair of AND-circuits 5, 6; 7, 8. Each of the AND-circuits 5-8 are gated, and the latches 1, 2 are reset by the signal on the UNLCH PSW 32, 33 line. The AND-circuits 5, 7 are gated as well by a signal from an OR-circuit 9 in response to either of the SET PSW 0-39 or SCAN IN PSW lines. When so gated, the AND-circuits 5, 6 respond to related bits of the J register on the J REG 32 and J REG 33 lines. The AND-circuits 6, 8 have an additional gate in the SET LGTH PSW line, and are thereby made responsive to a permutation of BOP bits 0 and 1. Specifically, if either BOP 0 or BOP 1 is present at the input of an OR-circuit 10, then the AND-circuit 6 may set the latch 1. On the other hand, if neither of the BOP bits, or both of them, are present at the input to an EXCLUSIVE OR circuit 11, then there will be no output therefrom, so that an inverter 12 will provide an input to an AND-circuit 8. The reasoning behind this can be seen in the light of the chart of section 5.2.10.1. In said chart, it can be seen that the RR format which has a one syllable length has zeros in both the zero- and one-bit positions of the operand which means that both BOP 0 and BOP 1 would be zeros. In this case, there is no input to either the OR-circuit 10 or the OR-circuit 11 so that the inverter 12 will cause the AND-circuit 8 to set the latch 2, but the OR-circuit 10 will not set the latch 1. This means that the length code will be set to 01. In the case of either RX instructions, or RS-SI instructions, the length of the instruction is two syllables, so that the OR-circuit 10 will respond to BOP bits 1 (in the case of RX instructions) or to BOP bit 0 (in the case of RS-SI instructions) so as to cause the AND-circuit 6 to set the latch 1. However, with only a single input to the exclusive OR-circuit 11, it will have an output, so that the inverter 12 will have no output, and therefore the latch 2 will not be set. In the case of the SI instruction, both the 0 and 1 bits will be 1, so that both the OR-circuit 10 and the inverter 12 will have an output and the latches 1 and 2 will both be set so as to indicate a length of 11 (three syllables).

In FIG. 136, signals for setting PSW 34 and 35 are generated on the SET PSW 34 and SET PSW 35 lines by a pair of OR-circuits 24, 25 each of which is settable by a related set of AND-circuits 26-28, 29-31. The AND-circuits 27-30 are gated by a signal on a IE SET CR line, and the AND-circuits 26, 31 are gated by a signal on a E SET CR line. The AND-circuits 26, 31 are thus made responsive to signals on the E TO CR BIT 34 and E TO CR BIT 35 lines, which indicate that the results of any instructions being executed in the E unit which cause the setting of the condition register require the setting of the condition register as indicated by the signal on these two lines. The AND-circuits 27, 30 are responsive to signals on the I/O COND LINE 01 and I/O COND LINE 02 lines. The AND-circuits 28, 29 respond to the IE unit setting of the condition register to 11 by the signal on the SET CR TO 11, which indicates that an attempt has been made to select an unavailable channel, and that the channel operation has therefore been terminated.

The signals on the SET PSW 34 and SET PSW 35 lines are applied to AND-circuits 20, 23 in FIG. 135. These AND circuits are effective to cause a pair of related OR-circuits 16, 17, to set related latches 14, 15 so as to manifest PSW bits 34, 35. The OR-circuits 16, 17 are also responsive to other related AND-circuits 18, 19; 21, 22. The latches 14, 15 are reset, and the AND-circuits 18-23 are set by a signal on the UNLCH PSW 34, 35 line. The AND-circuits 18, 21 are gated by the output of the OR-circuit 9, and are thus made responsive to signals on the J REG 34 and J REG 35 lines. These lines will be active whenever scanning operations are involved, or when the PSW is being loaded from the J register. The AND-circuits 19, 22 are further gated by a signal on the SET PGM MSK line, and are then responsive to bits 2 and 3, respectively, of the general bus left due to signals on the GBL 2, and GBL 3 lines. Thus, when the program mask is being set, not only is the program mask itself set, but the condition code additionally is set as well. The setting takes place by transferring bits 2-7 from a selected general register over the general bus left into bits 34-39 of the PSW, which is illustrated in FIG. 72. This is described in more detail in the section on the IE unit.

9.A.6 PSW 36-39: PROGRAM MASK FIG. 137

In FIG. 137, the program mask portion of the PSW is lodged in a plurality of latches 1, 2a, each of which is set by a corresponding OR-circuit 2, 3 in response to a related pair of AND-circuits 4, 5; 6, 7. An additional latch 9 relates to the parity bit for bits 32-39 of the PSW.

Each of the latches 1, 2a is reset, and the AND-circuits 4-7 are gated by a signal on the UNLCH PSW 36-39 line. The AND-circuits 4, 6 and an AND-circuit 10 which sets the latch 9 are additionally gated by a signal from an OR-circuit 8 which responds to either the signal on the SET PSW 0-39 or SCAN IN PSW line. The AND-circuit 4, 6 are thus made responsive to related bits of the J register on the J REG 36 and J REG 32-39 lines. The AND-circuits 5, 7 are provided with gating from the IE unit on the SET PGM MASK line, and thereafter respond to related bits 4- 7 of the general bus left on lines such as the GBL 4 and GBL 7 line. The AND-circuit 10 is gated, and the latch 9 is reset by a signal on the UNLCH PSW P 32-39 line. The AND-circuit 10 also responds to a related bit of the J register on the J REG P 32-39 line.

9.A.7 GATING OF ICR (PSW 40-63) FIG. 138

In FIG. 138, a plurality of UNLCH signals are generated by related OR-circuits 1-5 in response to various conditions. Each of the OR-circuits 1, 2, 4 is responsive to a related pair of AND-circuits 6, 7; 8, 9; 10, 11. The AND-circuits 6, 8, 10 are responsive to a signal on the SET PSW 40-63 line which may be generated in response to interruption, I execution, or maintenance controls. The AND-circuits 7, 9 are responsive to a signal on the GT INCR TO ICR, which renders bits 0-19 and bit 23 responsive to the outputs of the incrementer as a result of an IC HO ADV as described in the section on instruction fetching. To the contrary, an AND-circuit 11 will provide the UNLCH ICR 20-22 signal in response to a signal on the GD GS TO ICR, which results from the normal low-order updating of the ICR LO. An AND-circuit 12 responds to a GT GSR P TO ICR line which is generated by a combination of I unit control lines in FIG. 230. The output of the AND-circuit 12 and the output of the OR-circuit 2 are both applied to an OR-circuit 3 so as to generate a signal on the UNLCH ICR P 16-23 line. The AND-circuit 11 responds to a signal on the GT GSR TO ICR, which is also generated in FIG. 230. An OR-circuit 5 further provides a signal on a GT J TO ICR line in response to either the SET PSW 40-63 line, or in response to a signal on the SCAN IN PSW line. All the signals generated in FIG. 138 are applied to the ICR which is shown in FIG. 139 and described in the next section.

9.A.8 PSW 40-63: ICR FIG. 139

In FIG. 139, the instruction counter register (ICR) comprises a plurality of latches 1-7 each of which is settable by a related OR-circuit 8-14 in response to a related AND-circuit 15-21. The OR-circuits 8, 9, 12-14 are also responsive to additional AND-circuits 22-28, in dependence upon particular conditions. Each of the latches 1-7 is reset, and all the AND-circuits 15-28 are gated by signals on the related UNLCH ICR lines. For instance, the latches 1, 2 are reset by a signal on the UNLCH ICR 0-7, P line, which also is utilized to gate the AND-circuits 15, 16, 22, 23. The AND-circuits 15-21 are gated by a signal on a GT J TO ICR line, and are thereafter responsive to related bits of the J register on lines such as the J REG 0 line. The AND-circuits 22-25 are responsive to a signal on the GT INCR TO ICR line, and are thus made responsive to related lines from the incrementer such as the ICR 0 line. The AND-circuits 22-25 are therefore utilized to permit gating of bits 0-19 and 23 of the ICR from the INCR following a IC HO ADV (high-order ICR advance). The AND-circuit 26 is responsive to the signal on the GT GSR P TO ICR line concurrently with a signal on the GSR P line so as to cause the latch 7 to manifest the parity bit from the gate select adder. The AND-circuits 27 and 28 are also responsive to a signal on the GT GSR TO ICR line so as to cause related bits of the GSR to be set into latches 4, 5 in response to signals on the GSR 20-GSR 22 lines. In this fashion, bits 0-23 of the ICR may be set by the J REG, bits 0-19 and bit 23 may be set in response to the INCR, and bits 20-22, together with the parity bit for bits 16-23, may be set in response to the GSR.

9.B INCREMENTER FIG. 140

As illustrated in the center of FIG. 72, an incrementer is provided for incrementing the instruction count as normal processing proceeds. This incrementer is also utilized as a data path between the H register, the PSW register, the instruction counter register, and other related circuits as illustrated in FIG. 72. The incrementer actually serves as an incrementer in two different ways; the first way is that the incrementer is used as the high-order portion of an instruction counter, of which the low-order portion is a gate select adder; the second way is that the incrementer is utilized to generate an "on the fly" address for storage to fetch a storage word which is necessary to replenish either the A or the B register, notwithstanding whether one or both of them are empty, and without regard to the particular instruction count which the gate select register is utilizing to gate an actual instruction out of the AB register. As each instruction is gated into the IOP and related operational circuits, and is analyzed during T1 and T2, the next following instruction will of course be found in the AB register at a position therein which is displaced from the position of the current instruction by an amount which is equal to the length of the current instruction. At the I to E transfer of a current instruction, the gate select adder responds to the then current setting of the ICR LO (the low-order portion of the instruction counter register, which comprises bits 20, 21, and 22 thereof) and adds the length of the current instruction to the current setting of the ICR LO. The incrementer itself may or may not be involved in the operation, in dependence upon whether bit 20 of the ICR is advanced from a 1 to a 0, causing a GSA carry; the GSA carry must be reflected in bit 19 of the ICR, and therefore must cause bit 19 of the ICR to be incremented within the incrementer. However, this does not take place until one cycle following the I to E transfer within which the GSA carry is generated. The reflecting of the GSA carry into bit 19 of the ICR is called an IC HO ADV (IC high-order advance). When the INCR is so used, bits 0-19, and bit 23 are returned to the ICR. However, when the INCR is used to generate "on the fly" addresses for referencing storage word within which instructions to be used in the future are contained, the output of the INCR is applied to the H REG and to SAR, but it is not applied to the ICR. In this case, the setting of the ICR is used as a base, and the conditions which obtain, including whether A or B is empty or may be considered to be empty, and the setting of the ICR are combined to generate an input to the incrementer which will cause the incrementer to generate an address which is a full 23 bits long, which will specify a storage word containing instructions, the storage word being required either to reach the next instruction, in the case of both the A and B registers being exhausted, or merely to replenish the A or the B register. In this case, all 23 bits of the ICR are read into the INCR, and either bit 19 or bit 20, but not both, may be added to the setting of the ICR in order to generate the proper address. This is described in detail in relation to the charts shown in section 5.3.4.5. In the case of an IC HO ADV which is a carry from the gate select adder into the incrementer, the only possible control input into the incrementer is bit 19.

The incrementer itself is illustrated in FIG. 72. The incrementer itself is shown in block diagram form in FIG. 140, wherein input selection is provided by an incrementer input circuit (INCR IN) FIG. 144 under the control of an incrementer input gating control circuit (INCR IN GATING CTRLS) FIG. 141. The INCR IN FIG. 144 is responsive to bits 8-31 of the low-order half of the PSW , bits 0-23 of the ICR (which comprise bits 40-63 of the Psw register), or to bits 0-23 of the H register (which bits comprise an indication of a working address), since the H register is in effect a backup register for the SAR (storage address register). The INCR IN FIG. 144 provides signals to a circuit which generates input carries for groups within the incrementer (C IN GROUP) FIG. 145. This circuit in turn feeds the actual incrementing circuits FIG. 146 and FIG. 147 together with the parity predicting circuits FIG. 150 and FIG. 151. These latter circuits and the C IN GROUP circuit of FIG. 145 are controlled by the ADD ONE/TWO circuit FIG. 143. The incrementing circuits are also responsive to the INCR IN circuit FIG. 144, as is the parity invert function generating circuit INVRT P1/P2 FIG. 148 and FIG. 149. The output of the parity stages of the incrementing circuit FIG. 150 and FIG. 151 are applied to an incrementer parity check circuit INCR P CHK FIG. 152, which, together with a parity output of the incrementer extender FIG. 142 control an incrementer check circuit INCR CHK FIG. 153. The numerical output of the incrementing circuits FIG. 146 and FIG. 147 is distributed under control of an incrementer output gating control circuit INCR OUT GATING CTRLS FIG. 154.

At the bottom of FIG. 140, is shown the incrementer extender INCR EXT FIG. 142 which provides an additional 8-bit data path for use with the incrementer when the incrementer is being used only as a data path. The incrementer extender can respond to either bits 0-7 z of the PSW (which would accompany bit 8-31 of the PSW as they are applied to the INCR IN circuit of FIG. 144, or the INCR EXT FIG. 2. may respond to PSW bits 32-39 which it will do when the INCR IN FIG. 144 is responding to the ICR bits 0-23.

9.B.1 CONTROLS

9.B.1.1 Incrementer In Gating Controls FIG. 141

In FIG. 141, an OR-circuit 1 will generate a signal on a GT RH PSW to to INCR line under I unit control in response to a signal on any one of the following lines: IC HO ADV, STR REQ, IC GT RH PSW TO INCR, IRPT GT RH PSW TO INCR, or IE GT RH PSW TO INCR. As described in the PSW section, the right hand of the PSW actually refers to the ICR (instruction counter register) portion of the PSW, which is hereinafter referred to as ICR, for the most part.

Another OR-circuit 2 in FIG. 141 generates a signal on a GT H TO INCR line to cause the contents of the H register to be gated into the incrementer. The OR-circuit 2 responds to a signal from the E unit on an E GT H TO INCR line and to a signal from the IE unit on an IE GT H TO INCR line. The OR-circuit 2 is also responsive to a pair of AND-circuits 3, 4 the AND-circuit 3 in turn requiring a signal from an OR-circuit 5. The OR-circuit 5 is operative during branch ops due to a signal on a BR OP line, or during a multiple load operation due to a signal on a BD LD MULT line. The AND-circuit 3 also requires a signal on the T2 line which indicates the T2 portion of instruction sequencing. The AND-circuit 4 responds to the last cycle of a successful branch due to signals on a BR LC line and a BR SUCC M line.

9.B.1.2 Incrementer Input FIG. 144

The circuit of FIG. 144 comprises a three-way input gate, there being provided an OR-circuit 1 for each bit (including parity bit) of the incrementer, each OR circuit being responsive to a respective trio of AND-circuits 2-4. The AND-circuits 2 permit gating of the left-hand half of the PSW, the AND-circuits 3 permit gating of H register bits, and the AND-circuits 4 permit gating of the right-hand half of the PSW, all in an obvious manner. Each of the OR-circuits 1 provides a signal on a corresponding one of a plurality of INCR IN lines 0-23, PO-7-P16-23.

9.B.1.3 ADD One/Two Circuits FIG. 143

In FIG. 143, an OR-circuit 1 generates a signal on a ADD ONE line in response to a storage request as indicated by a signal on a STR REQ line or in response to IE unit controls as indicated by a signal on a IE GT H TO INCR line. The OR-circuit 1 is also responsive to a pair of AND-circuits 2, 3, the AND-circuit 2 being operative at T2 time in response to an OR-circuit 4 which can be operated either by a signal on the BR OP line, or by a signal on the BD LD MULT lines. The AND-circuit 3 is responsive to the concurrence of a signal on the DECODE ADD ONE line, on the IC GT RH PSW TO INCR line, and on the NOT IC RCVY line. These latter two lines also operate an AND-circuit 5 which, together with an input on a DECODE ADD TWO line will cause an OR-circuit 6 to generate a signal on an ADD TWO line. The OR-circuit 6 is also operative in response to a signal on the IC HO ADV line. Thus, the OR-circuits 1 and 6 provide control to cause the incrementer to add either one or two to the setting by providing control inputs to bits 20, and 19 thereof, respectively.

9.B.1.4 Incrementer Carries Into Groups FIG. 145

In FIG. 145, a plurality of C IN lines are provided, one for each four-bit group in the incrementer, each energized by a corresponding circuit 1-5. The OR-circuit 1 will generate a carry into group 16-19 whenever there is a signal on the ADD TWO line, or when there is an output from an AND-circuit 6 which will be when there is a signal on the ADD ONE line concurrently with a signal on the INCR IN 20 line. An ADD TWO signal is in fact a signal into bit 19, and it is utilized in the incrementer as a carry into the group 16-19. Similarly, an ADD ONE is an input into bit 20 of the incrementer, and so if there is a bit 20 and a 1 is added to it, this will cause a carry into bit 19 which is therefore a carry into the group which comprises bits 16 through 19. Inasmuch as the only inputs into the incrementer are the incrementer input bits themselves, and the ADD ONE and ADD TWO signals, it therefore follows that any carries within the incrementer must be generated as a result of the ADD ONE and ADD TWO signals. Therefore, the AND-circuits 2-5 can each operate only if a carry is propagated to the corresponding group from the OR-circuit 1. thus, the AND-circuit 2 will provide a carry into group 12-15 if there is a signal on the C IN 16-19 together with the output of an AND-circuit 7 which responds to each of the bits in the group 16-19. Therefore, a carry into bit 19 will be propagated through bit 19, 18, 17 and 16 so as to provide an input to the AND-circuit 2 in order to generate a carry into group 12-15. The remaining AND-circuits 8-10 operate in a similar fashion, in combinations with AND-circuits 3-5, so that carries may propagate all the way to the group which comprises bits 0-3 provided that the incrementer input is all one from bit 4 to bit 19, and there is a carry into bit 19 (C IN 16-19).

9.B.2 INCREMENTING CIRCUIT FIG. 146 AND FIG. 147

The incrementing circuits of FIG. 146 and FIG. 147 differ due to the nature of the ADD ONE and ADD TWO inputs to the incrementer. Thus, it can be seen that the control input to FIG. 146 is a carry in to bits 16-19 on the C IN 16-19 line, whereas the control input to FIG. 147 is an ADD ONE input on the ADD ONE line. In both FIG. 146 and FIG. 147, the J register may be gated into the incrementer latch circuits from the ICR; in other words, when the incrementer is used as a data path for the J register, the signals do not pass through the incrementer input circuits of FIG. 144; this means that the incrementer is a faster data path for the J register than it is for the H register or the PSW, which makes up for the fact that the J-INCR path includes the ICR as part of the data path, and the fact that the J register is more remote (in the E unit).

In FIG. 146, a plurality of latches 1 may each be set by a related OR-circuit 2 in response to any one of three corresponding AND-circuits 3-5. The AND-circuits 3 are all operative in response to a signal on the SCAN GT J TO INCR line concurrently with a signal on a related one of a plurality of ICR lines 0-19. These lines, though fed by the ICR, are in fact supplying J register data bits to the INCR on a scan operation.

Each of the AND-circuits 4, 5 are in turn responsive to a related inverter 6 which is fed by a corresponding AND-circuit 7. The AND-circuits 4, 5, 7 and the inverter 6 all operate more or less as an EXCLUSIVE OR circuit, where the corresponding input bit is EXCLUSIVE OR'd with a carry into that bit. Thus, for bit 19, the INCR IN 19 line is EXCLUSIVE OR'd with the C IN 16-19 INCR line; thus, if there is either a carry into bit 19 (which is the same as a carry into the group 16-19) or an incrementer input bit 19, then there will be an incrementer bit 19 unless both of them are present, in which case there will be no bit 19. This is due to the fact that the AND-circuit 7, when it senses the presence of both inputs, will cause the inverter 6 to block the AND-circuits 4 and 5.

The expression gets more complicated with higher order bits, due to the fact that a control input into successively higher order bits is based on the carry into the group 16-19 having to be propagated through more of the bits of the incrementer to reach the subject bit. For instance, with respect to bit 18, there must be a carry into the group 16-19 and an incrementer input bit 19 in order to propagate the carry to bit 18. Therefore, bit 18 is EXCLUSIVE OR'd with a combination of bit 19 and a carry into bit 19. In a similar fashion, the AND-circuit 7 which corresponds to bit 17 requires that there be a carry into bits 16-19, an incrementer input bit 19, an incrementer input bit 18, and bit 17, in order to block the AND-circuits 4, 5 corresponding thereto. With respect to bit 16, the carry into the bit is detected by an inverter 8 which is responsive to the inverter 6 related to bit 17; however, all of the various bits could be collected (as for bit 17) with respect to bit 16 if faster circuits are desired. The relationship including the inverter 8 which is shown with respect to bit 16 is illustrative merely.

At the bottom of FIG. 146 is illustrated arrangements for the remaining bits of the incrementer, where each four-bit groups is identical to the four-bit group shown in the upper portion of FIG. 146, except for the actual bits, and carries into groups, which are applied thereto. Thus, the circuit of FIG. 146 provides incrementer outputs for the bits 0-19.

In FIG. 147, bits 20-23 are handled somewhat differently. In FIG. 147, a plurality of latches 1 may be set by an OR-circuit 2 in response to either one of two AND-circuits 3, 4. Each of the latches 1 generates a signal on a corresponding one of three INCR lines 21-23. In addition, a latch 5 is settable by an OR-circuit 6 in response to anyone of three AND-circuits 7-9. The AND-circuit 7 is identical to the AND-circuit 3 and the AND-circuits 8, 9 correspond to the AND-circuits 4. In operation, the AND-circuits 3, 7 are each operative whenever there is a signal present on a SCAN GT J TO INCR line concurrently with a signal present on a corresponding one of a plurality of ICR lines 20-23 (each of which is actually transmitting data from the J register for scan purposes). This function of the AND-circuits 3 in FIG. 147 is identical to the function of the AND-circuits 3 in FIG. 146. Each of the AND-circuits 4, 8, 9 is operative only during NOT LC time as indicated by a signal on a NOT L C line. The AND-circuits 4 will set the corresponding latch 1 provided there is a signal on a corresponding one of the INCR IN lines 21-23 whereas the AND-circuits 8, 9 form an EXCLUSIVE OR function with the OR-circuit 6 in combination with a pair of inverters 10, 11. Thus, if there is either an ADD ONE input to the AND-circuit 8 and the inverter 11, or an INCR IN 20 input to the AND-circuit 9 and the inverter 10, then there will be an output from the AND-circuit 8, or the AND-circuit 9, respectively, so as to cause the OR-circuit 6 to set the latch 5. However, if both and ADD ONE and the INCR IN 20 inputs are present to the inverters 10, 11 then both of the AND-circuits 8, 9 will be blocked by said inverters. Thus, there will be an INCR bit 20 out of the latch 5 only when there is an ADD ONE, or an INCR IN 20, but not both applied to the AND-circuits 8, 9. The function of the AND-circuits 8, 9 in FIG. 147 is identical to the function of the AND-circuits 4, 5 in FIG. 146.

Thus, the incrementer can respond directly to bits of the J register during scanning operations, or can act as an adder by responding to incrementer input bits together with the ADD ONE and ADD TWO bits. However, should there be an ADD ONE, an ADD TWO, and an INCR IN bit 20 all at the same time, then the incrementer will not operate to give the proper sum, as indicated in the Instruction Fetching section.

The reason why the incrementer should not operate properly is that this condition should never occur, and if it does occur, a faulty sum is desired so that the parity checking circuit will be able to indicate that a malfunction has occurred. The reason that this condition should never occur is because of the fact that the gate select adder causes an IC HO ADV only when bit 20 of the ICR LO is advanced from 1 to 0, and the IC HO ADV takes place on the following cycle so that whenever a high-order advance takes place, bit 20 is always 0. Although an IC high-order advance can be done simultaneously with an "on the fly" generation of a storage address, the only time when this could cause a conflict is in the case of SS instructions, and IC fetching is blocked during SS instructions.

The reason for the incrementer actually providing a faulty sum in the event of an ADD ONE, and ADD TWO, and an incrementer input into bit 20 concurrently, is that the OR-circuit 1 in FIG. 145 recognizes a carry into the group 16-19 either from ADD TWO or from ADD ONE together with an input to bit 20. However, if there is an output from the AND-circuit 6 concurrently with an ADD TWO signal, this alone should cause the reversal of the carry into bits 16-19, and create instead a carry into bits 12-15 even without propagation by an AND circuit such as the AND-circuit 7. It is thus the simplicity of the circuit of FIG. 145 (rather than any complex control hardware) which permits checking of the operation of the instruction updating apparatus.

9.B.2.1 Incrementer Bits 0-15 Parity FIG. 148 and FIG. 150

The parity of the incrementer output for bits 0-7 and for bits 8-15 will depend upon whether a carry into one of these parity groups has occurred, and whether an odd or even number of changes in the output bits results from the carry into the group in comparison with the configuration of bits at the input to the incrementer. The circuit of FIG. 148 recognizes where there is a parity change, by generating a partial invert parity signal for each of the parity groups 0-7 and 8-15. Specifically, an OR-circuit 1 responds to either one of three AND-circuits 2-4 or to a signal on an INCR IN NOT 7 line. The AND-circuit 2 responds to a 6 but no 5; the AND-circuit 3 responds to 4 and 6 but no 3; and the AND-circuit 4 responds to 2, 4, and 6 but no 1 input to the incrementer. In other words, each of the inputs to the OR-circuits 1 represents the fact that a 0 bit has occurred an even number of bits from the input (noting that the bit 7 input is located an even number of bits, ZERO, from the input into the group). Thus, if bit 7 is a 0, than a carry into the group which is a carry into bit 7, will cause bit 7 to change from 0 to 1; this change will not cause any further rippling of carries, so that the parity will be changed from an odd to an even number, or from an even to an odd number. Similarly, the AND-circuit 2 recognizes the case where if bit 7 is not a 0, and bit 6 is a 1, then if bit 5 is 0, carries will propagate to bit 5 and no further, which means that a configuration of 011 (for bits 5, 6, and 7 respectively) will be changed to 100, thus resulting in a need to change the parity bit. The other AND-circuits 3, 4 operate in the same fashion; note that whenever one of the odd bits is a 0, the highest number (lowest ordered) odd bit will exercise control over the OR-circuit 1.

A set of circuits 5, similar to that shown at the top of FIG. 148, is provided for bits 9-15, although not shown in detail herein.

In FIG. 150, the effect of the invert parity signals of FIG. 148 is to reverse the related parity bit from whatever it is at the input so as to provide a correct parity bit at the output. Parity is set in a latch 6 for the parity group including bits 0-7 whenever the latch is set by an OR-circuit 7 in response to any one of four AND-circuits 8-11. The AND-circuit 8 in FIG. 150 is similar in function to the AND-circuit 3 in FIG. 146 and FIG. 147 in providing an input to the incrementer latches from the J register (via the PSW register) for scan purposes. Note that the AND-circuit 8 responds to PSW bit 37, which is therefore J register bit 37, rather than to a parity bit for bits 0-7 of the J register. The purpose of this is to provide for scanning a particular parity bit into the incrementer parity circuit of FIG. 150 while maintaining the parity bits of the J register for the purpose of checking the actual scan-in word which is contained therein. In other words, PSW 37 is used as a data path for J register bit 37 which is used in scanning operations as a parity bit for groups 0 to 7 of the incrementer. This is described more fully in the section on scan operations.

The AND-circuit 9 recognizes the case where there is a signal on the NOT PARTIAL INVRT P 0-7 line concurrently with a parity bit as indicated by a signal on the INCR IN P 0-7 line when there is a carry into bits 0-7 of the incrementer as indicated by a signal on the C IN 0-7 line. The AND-circuit 10 recognizes the case where, although there is a carry into bits 0-7 and a partial invert parity function for bits 0-7 (as indicated by signals on the C IN 0-7 and PARTIAL INVRT P 0-7 lines), there nontheless is no parity input to the bit as indicated by a signal on the ICR IN NOT P 0-7 line. Thus, a parity bit should result because of being changed from no parity bit.

The AND-circuit 11 is operative when there is a parity bit at the input to the incrementer, and since there is no carry into bits 0-7, there can be no change in the parity bit as a result of the incrementing operation; thus, the AND-circuit 11 operates in response to signals on the NOT C In 0-7 and INCR IN P 0-7 lines. A circuit 12 is provided which is fully equivalent to the circuits 6-11 except for the fact that the circuit 12 responds to signals which relate to the parity of bits 8-15 of the incrementer.

9.B.2.2 Incrementer Bits 16-23 Parity FIG. 149 and FIG. 151

With respect to bits 16-23 of the incrementer, two parity bits are provided, one of which (P1) is used only during IC HO ADV (instruction counter high order advances), and the other of which (P2) is used as a normal parity bit for incrementer bits 16-23. The P1 bit is not used for parity checking of the incrementer output, but is merely used as a parity bit to be returned to the ICR with bits 16-20 and 23 after an IC HO ADV; the INCR parity checking circuits (described in the next section) respond to the P2 bit.

In FIG. 149, a function which indicates that P1 should be inverted is generated by an OR-circuit 1 in response to either one of two AND-circuits 2, 3. Both of these AND-circuits are operative only when there is an ADD TWO signal at the input thereto. The AND-circuit 3 responds to a NOT 19 bit, whereas the AND-circuit 2 responds to a Not 17 together with an 18 bit. The reasoning behind this is the same as with respect to the circuit of FIG. 148, to wit, to determine whether the ADD TWO signal is going to affect only bit 19, or if it will affect bit 19, 18 and bit 17. If it affects all three of the bits 17-19 and bit 16 as well, then the effect is to leave the parity the same as it was without considering the effect of the ADD TWO. Another OR-circuit 4 is provided to generate a similar function indicating that parity bit P2 is to be inverted. The principal behind the circuitry associated with the OR-circuit 4 is the same as that of the circuit 3 associated with the OR-circuit 1, although it is more complex. Additionally, the OR-circuit 4 and its associated circuitry is established in such a fashion that correct parity signals should result from an ADD ONE and an ADD TWO concurrently only when there is No bit 20 at the incrementer input. The OR-circuit 4 responds to any one of five AND-circuits 5-9, each of which recognizes a different condition with respect to the parity as a result of ADD ONE and ADD TWO inputs for various combinations of incrementer input bits. The AND-circuit 5 recognizes the case where the ADD TWO is applied to bit 19, and bit 19 is a 0, and there is no other effect on bit 19 due to the fact that there is no ADD ONE as indicated by a signal on the NOT ADD ONE line. The AND-circuit 6 can respond in a similar situation due to the fact that an OR-circuit 10 is operative in response to a signal on the NOT ADD ONE line, so that if bit 19 is present, and bit 18 is also present, but bit 17 is a 0, then the AND-circuit 6 can supply a signal to the OR-circuit 4. On the other hand, with bit 18 a 1 and bit 17 a 0, even if there is an ADD ONE, if there is no bit 19 but there is a bit 20, then parity must be inverted to a carry into bit 19 as a result of a carry from bit 20 into bit 19; however, when there is also an ADD TWO, this will result in an error situation (as it should) due to the fact that the ADD TWO, when combined with a carry into bit 19 will cause bit 19 to again look as it did in the first instance, and therefore nullifies the parity effect. Thus, the AND-circuit 11 will tend to sense the case where there is a malfunction that has permitted an ADD ONE, an ADD TWO, and bit 20 all to appear simultaneously.

An AND-circuit 7 detects the case where there is an ADD ONE (which is an input to bit 20) together with 1's in bits 17 and 19. Thus, if bit 20 is a 0, then the ADD ONE itself will stop at bit 20, but will change the bit 20 from a 0 to a 1 and therefore causes the parity to change. On the other hand, if bit 20 is a 1, then the ADD ONE will cause bit 20 to change to 0, with a carry to bit 19, so bit 19 changes to 0, and will either propagate through bit 18 to bit 17 which will change to 0, or it will cause bit 18 to change from a 0 to a 1 and stop there. Thus, parity will be affected without regard to the even-numbered bits provided that the odd-numbered bits are both 1's when an ADD ONE is presented to bit 20.

The AND-circuit 8 recognizes the case where the propagation of the carry from bit 20 into bit 19 ends with bit 18 without regard to the status of bit 17; specifically, with bits 19 and 20 both equal to a 1, the ADD ONE will cause bit 20 to change to 0, giving a carry into bit 19, which in turn changes to 0 with a carry into bit 18. Since bit 18 is 0, it becomes a 1, so that as between the three bits 18-20, only bit 18 now has a 1 therein whereas bits 19 and 20 had 1's therein prior to the effect of ADD ONE. Thus, parity has to be changed for the condition sensed by the AND-circuit 8.

The AND-circuit 9 recognizes a simple case where there is an ADD ONE but no ADD TWO and there is no bit 20; this then recognizes the case where the 0 in bit 20 is changed to a 1 by a signal on the ADD ONE line, and no carry is to be effected, and since there is not also an ADD TWO, there is no change in bit 19 (and upward) so that parity must be inverted.

The invert P1 and invert P2 functions are utilized in FIG. 151 to generate final P1 and P2 parity bits by means of a pair of EXCLUSIVE OR circuits 12, 13, each of which will operate a corresponding AND-circuit 14, 15 so as to set a related latch 16, 17. The latch 17 is in fact set by an OR-circuit 18 since the latch 17 may also be set by an AND-circuit 19 which reflects bit 39 of the J register (in the same fashion that bits 37 and 38 are utilized in the circuit of FIG. 150 for scan purposes). Thus, if there is a parity bit at the input to either of the EXCLUSIVE OR circuits 12, 13, but there is an instruction to invert the bit by means of a signal on one of the related lines INVRT P1 and INVRT P2, then there will be no input to the AND-circuits 14, 15 so that the related latch will not be set. On the other hand, if there is an input parity bit and no invert function, or if there is an invert function but no parity bit, then the EXCLUSIVE OR circuits 12, 13 are able to set the related latches 16, 17. The outputs of the latches 16, 17 are signals on related INCR P1 16-23 and INCR P2 16-23 lines. The P1 line is used merely to accompany bits back to the incrementer, but the P2 line out of FIG. 151 is utilized in FIG. 152 to check the output of the incrementer.

9.B.2.3 Incrementer Parity Check FIG. 152

In FIG. 152, a plurality of EXCLUSIVE OR complexes 1-3 are each connected so as to operate an AND-circuit 4 in the event that there is an odd number of inputs thereto. Should all of these EXCLUSIVE OR complexes 1-3 operate and AND-circuit 4, then there will be no output from an inverter 5 on a INCR P CHK line. On the other hand, if an even number of inputs are applied to any one of the EXCLUSIVE OR complexes 1-3, then that complex will have no output, and will provide no input to the AND-circuit 4; with less than all of the inputs present at the AND-circuit 4, then there will be an output from the inverter 5 on the INCR P CHK line. The EXCLUSIVE OR complexes 1-3 respond to the eight bits of a corresponding parity-check-byte, together with the parity bit for that byte, bits 16-23 are combined with the P2 16-23 bit from FIG. 151, for instance.

9.B.3 INCREMENTER EXTENDER FIG. 142

The incrementer extender shown in FIG. 142 comprises essentially a plurality of latches 1 each of which may be set by a corresponding OR-circuit 2 in response to either one of two related AND-circuits 3, 4. The OR-circuits 2 and the AND-circuits 3, 4 correspond identically with the OR-circuits 1 of FIG. 144 and the AND-circuits 2, 4 of FIG. 144. In other words, the latches 1 may be set in response to either bits 0-7 of the PSW (together with parity bits 0-7) or in response to bits 32-39 (together with the parity bits 32-39) in dependence upon the presence of a signal on either a GT LH PSW TO INCR line or on a GT RH PSW TO INCR line, respectively. The output of each of the latches 1 is applied to an EXCLUSIVE OR complex 5, the output of which comprises a generated parity bit which is combined in an EXCLUSIVE OR circuit 6 with the actual parity bit from the related latch 1. In the event that either or both parity bits are present, there is no signal on an INCR EXT P CHK line, but the presence of one of them without the other will cause an incrementer extender parity check condition to be manifested by a signal on the INCR EXT P CHK line. This signal is utilized in FIG. 153 in generating the incrementer check function.

The output of each of the latches 1 is also applied to a corresponding AND-circuit 7 so as to cause said output to be gated to the K register whenever there is a signal present on a GT INCR TO K line. The output of the AND-circuits 7 comprise a plurality of signals on corresponding INCR EXT lines 0-7,P.

9.B.4 INCREMENTER CHECK CIRCUIT FIG. 153

In FIG. 153, a latch 1 will generate an incrementer check signal on an INCR CHK line whenever it is set by an OR-circuit 2 in response to either one of two AND-circuits 3, 4. The AND-circuit 3 responds to an incrementer parity check signal on the INCR P CHK line concurrently with a signal on the GT INCR ERR line; the AND-circuit 4 responds to an incrementer extender parity check signal on the INCR EXT P CHK line together with an incrementer extender gating signal on the GT INCR EXT ERR line. The latch 1 is reset by the regular check reset signal which is utilized throughout the system on the CHK RST line. The output of the latch 1 is applied to the clocking signals.

9.B.5 INCREMENTER OUT-GATING CONTROL FIG. 154

In FIG. 154, a plurality of OR-circuits 1-4 provide corresponding incrementer output gating signals to the ICR, K REG, H REG, and SAR. Additionally, an OR-circuit 5 generates a signal to gate the incrementer extender error, and an OR-circuit 6 responds to any one of the OR-circuits 1-5 to generate a signal for gating incrementer error on a GT INCR ERR line.

The signal on the GT INCR TO ICR line is generated by the OR-circuit 1 in response either to a signal on a IC HO ADV LCH line or in response to an AND-circuit 7 which requires concurrent presence of signals on both the BR SUCC M LCH line and the NOT BR LC LCH line. Thus, the contents of the incrementer is returned to the ICR during IC high-order advance, or during the last cycle of a successful branch. In the latter case, the INCR is used as a data path for the new ICR setting, which is the address of the subject (or branch-to) instruction, from the H register, where the subject instruction address computed by the address adder has been placed.

The signal on the GT INCR EXT ERR line is generated by the OR-circuit 5 in response to signals on either the IE GT INCR EXT ERR line or the IRPT GT INCR EXT ERR line. Thus, the incrementer extender error may be gated in response to interruptions when the INCR and INCR EXT are used as a data path for checking the new PSW. The INCR EXT ERR may also be gated by the I UNIT when it is performing the Load PSW instruction, and thus using INCR as a means of checking the new PSW.

The signal on the GT INCR TO K line is generated by the OR-circuit 2 in response to either E unit or interrupt control as manifested by signals on the E GATE INCR TO K line or the IRPT GT INCR TO K line. The interrupt gate is used when the old PSW is being moved from the PSW register to the K register so that it may be transferred to storage.

The OR-circuit 3 will generate a signal on the GT INCR TO H line in response to either a signal on the IE GT INCR TO SAR line or the output of an AND-circuit 8 which requires concurrent signals on the I TO E XFER line and the BD LD MPL line. Thus the incrementer is gated to the H register in response to multiple load and store requirements of the IE unit controls, or during the I to E transfer of a multiple load instruction. In the case of an I to E gating of incrementer to H, it will also cause an OR-circuit 4 to gate the incrementor to SAR as indicated by a signal on the GT INCR TO SAR line. This permits cycling the address through the INCR to and the H register for repetitive updating. The OR-circuit 4 is also responsive to three AND-circuits 9-11, the AND-circuit 9 being response to the output of an OR-circuit 12 during branch ops as indicated by a signal on the BR OP line or during a multiple load operations as indicated by a signal on a BD LD MPL line. Thus, the INCR is gated to both the H register and to SAR during the I to E of a multiple load, since the AND-circuit 9 is gated at I to E transfer time as indicated by a signal on an I TO E XFER line. The AND-circuits 10, 11 are each gated by the concurrence of a signal on the NOT BLK ICM LCH & SUCC BR line together with NOT TON T2 or NOT ID BLK IC lines, alternatively. Thus, the INCR is gated to SAR when a successful branch is completed provided the IC blocks are removed or TON T2 is off.

9.C GATE SELECT MECHANISM

As shown in FIG. 72, the gate select mechanism includes a prelatch, a gate select adder, a gate select register, and, as shown in FIG. 73, a gate select decoder. The purposes to which the gate select mechanism are put are described in the Instruction Fetching section of said environmental system.

The various parts of the gate select mechanism are described in the following sections.

9.C.1 GATE SELECT PRELATCH FIG. 156

In FIG. 156, the gate select prelatch is shown to comprise essentially three latches 1 each of which is set by a corresponding OR-circuit 2 in response to either one of a pair of AND-circuits 3, 4. Each of the AND-circuits 3 is operative in response to a signal on a GATE ICR line which is generated by an AND-circuit 5 at all times other than during an SS OP, an EXECUTE OP, or a repeat instruction operation. The AND-circuits 4 are gated by a signal on a GATE GSR line which is generated by an AND-circuit 6 during execute instruction as indicated by a signal on a XEQ OP LCH line. The AND-circuit 6 is inhibited during SS operations as is the AND-circuit 5. Each of the AND-circuits 3, 4 respond to the respective gate signal and to a corresponding bit of either the ICR, or the GSR, respectively. The latches 1 are each reset by a signal on a NOT SS OP line.

The output of each of the latches 1 comprises a signal on a corresponding one of a plurality of GS PRE LCH lines, which are also used as GS ADDER IN lines. The GS PRE LCH lines are renumerated 20-22 for positions of the ICR to which they correspond, and the GS ADDER IN lines are designated u, t, h (in the complements thereof) for units tens and hundreds as used in the GS ADDER.

9.C.2 GATE SELECT ADVANCE FIG. 157

In FIG. 157, a two half-word (or two syllable) advance of the gate select adder is called for by a signal on a ADV 2 HLF WDS line which is generated by an AND-circuit 1 in response to the output of an inverter 2 which is operated by an OR-circuit 3, concurrently with a signal on a NOT ID RR line. The OR-circuit 3 is operative during instruction operations as indicated by a signal on a MC REPEAT INST line, or in response to instructions in the SS format as indicated by a signal on a SS OP LCH line. The OR-circuit 3 is also operative in response to a signal on a VFL ADR.

9.C.3 GATE SELECT ADDER FIG. 158

The gate select adder shown in FIG. 158 comprises three orders: units (bit 22), tens (bit 21), and hundreds (bit 20). The GS adder also supplies a carry, whenever a carry out of bit 20 is indicated. The units order comprises an exclusive OR-circuit 1 which responds to the u and U signals to generate bit 22. Thus, if either but not both of the u and U signals is present, there will be a signal on the GSA 22 line. On the other hand, if both or neither are present, then bit 22 will be a 0.

The tens order comprises an OR-circuit 2 which is responsive to any one of four AND-circuits 3-6, each of which accounts for a different combination of u, U, t, T bits. The AND-circuit 3 takes into account when there are both t and T inputs, and both u and U inputs so that an AND-circuit 7 generates a carry into the tens order from the units order thereby causing a net affect on bit 21 being a 1. The AND-circuit 4 is also responsive to a carry into the tens order from the units order, but recognizes a situation where there is neither a t or T input. In other words, it recognizes that bit 21 is only the carry from the units order (from bit 22). The AND-circuit 5 recognizes the case where there is no carry from the units into the tens order as indicated by an output from the OR-circuit 8 which responds to not u or NOT U as an indication that no carry can result in the units order. The AND-circuit 5 is also responsive to a T with no t which indicates that there should be a bit 21 into the presence only of the control input (T) and no other inputs to the tens order. The AND-circuit 6 also recognizes the lack of a carry from the units order as indicated by a signal output from the OR-circuit 8 and the case where there is no control input (NOT T) but there is a bit input from the GS prelatch (t). Thus, each of the AND-circuits 3-6 recognizes the case where the net effect of carries control and prelatch inputs to the tens order result in a tens order output bit, GSA bit 21.

The hundreds order of the gate select adder relates to bit 20, and comprises essentially an OR-circuit 10 which is fed by any one of four AND-circuits 11-14. The AND-circuit 11 recognizes the case where there is no inputs to the tens order as indicated by a NOT t and a NOT T which is sensed by an AND-circuit 15, but there is an input to the hundreds order as indicated by the h applied to the AND-circuit 11. Thus, no inputs from the tens order, nor carries from the units order, can cause a carry from the tens order to the hundreds order, so that the presence of the hundreds order bit will require the presence of an output bit for the hundreds order on the GSA 20 line. The AND-circuit 12 recognizes the case where there may be one input to the tens order, but there is no carry from the units order so that there will be no carry into the hundreds order; this is achieved by application of not u or not U, and not t or not T (OR-circuit 16). The AND-circuit 13 recognizes the case when there is at least one input to the tens order (OR-circuit 17) together with both inputs present at the units order (AND-circuit 18,), which means that a carry into the hundreds order will result, but there being no input to the hundreds order, this carry will require that there be an output from the hundreds order.

The AND-circuit 14 recognizes the case where both inputs are present to the tens order so that there will be a carry into the hundreds order without regard to conditions in the units order and yet there is no input to the hundreds order so that the carry into the hundreds should be reflected in an output bit on the GSA 20 line.

GSA carry is generated by an AND-circuit 19 in response to an OR-circuit 20 provided there is also an input to the hundreds order of the adder. The OR-circuit 20 may be operated by either one of two AND-circuits 22, 23, the AND-circuit 23 recognizing the case where there are two inputs to the tens order so that there will be a carry into the hundreds, which together with the regular input to the hundreds order will cause a carry out of the GS adder. The AND-circuit 22 recognizes the case where both inputs are present to the units order so that there will be a carry into the tens order, and that either one or the other of the tens order inputs are present as indicated by an OR-circuit 24, thus giving rise to a carry into the hundreds order; again a carry into the hundreds order together with an input to the hundreds order will result in a hundreds order of 0 with a carry out of the hundreds order.

Thus, the gate select adder recognizes three inputs u, t, h and two control inputs U and T to generate output bits 20-22 together with a CARRY on corresponding GSA lines.

9.C.4 GS GATE CONTROLS FIG. 159 AND FIG. 160

In FIG. 159, a signal is generated on a VFL ADR & NOT T1 or LCH by an AND-circuit 1 in response to a signal on a VFL ADR line concurrently with a signal on the NOT T1 & NOT T1 LCH line. The output of the AND-circuit 1 is also used as a gate for an AND-circuit 2 which otherwise responds to a signal on the EBC (early B control clock) line so as to operate an OR-circuit 3 which generates a signal on a GS GT line, which is utilized in FIG. 161a as an input control gating line for the GSR. The OR-circuit 3 is also responsive to an AND-circuit 4 which may be operated at early B time in response to a concurrence of a signal on the TSTS CMPLT (tests complete) line and a signal on the I BR SUCC (I unit branch success) line. The OR-circuit 3 is responsive to another AND-circuit 5 which is operated by EBC and TSTS EMPLT concurrently with a signal on the E BR SUCC line. An AND-circuit 6 is operative in response to MC REPEAT INST and NOT VFL ADR lines. An AND-circuit 7 is operated at A time by a signal on a AC line provided there is an output from an OR-circuit 8 which may be caused by a signal on a IC RCVY LCH line or by an AND-circuit 9. The AND-circuit 9 operates with TON T2 during other than an execute instruction as indicated by a signal on a NOT XEQ OP LCH line.

In FIG. 160, a signal which gates the H register to the gate select register is generated on a GT H TO GS line, the complement of which is generated by an inverter 10 on a GT GSA GS line so that either the gate select adder or the H register are always gated into the gate select register. These lines are controlled by an OR-circuit 11 which responds to either AND-circuits 12, 13, each of which requires a signal on a TSTS CMPLT line. The AND-circuit 12 is also responsive to a signal on the I BR SUCC, whereas the AND-circuit 13 is responsive to a successful branch from E, as indicated by E BR SUCC.

9.C.5 GATE SELECT REGISTER FIG. 161

In FIG. 161, the gate select register comprises essentially a plurality of latches 1, each of which is setable by an OR-circuit 2 in response to either one of two AND-circuits 3, 4 or in response to a scan input for the corresponding latch. The AND-circuits 3, 4 are responsive to a signal on the GS GT line, and to related inputs for either the H register or the gate select adder, respectively. Thus, the AND-circuits 3 will respond to a related bit of the H register if there is present a signal on the GT H TO GS, and in the alternative, the AND-circuits 4 will respond to the corresponding gate select adder bit provided there is a signal on the GT GSA GS line. Each of the latches 1 is reset by a signal from an OR-circuit 5 which responds to either a CPU RST signal, or to the GS GT signal. Although shown in FIG. 161 in detail only with respect to bit 22, a plurality of similar circuitry 6, 7 is provided for bits 20 and 21 thereof.

A carry position is provided in the GS register comprising a latch 8 which is set by an OR-circuit 9 in response to an AND-circuit 10 or in response to a scan input for the GSR carry. The AND-circuit 10 in response to the GS gate signal on a GS GT line, to a signal on the GT GSA GS line, and to a gate select carry from the adder circuit as indicated by a signal on the GSA carry line. The latches 1 each operate a bipolar latch such as the bipolar latch 12 so that the contents of the latch 1 will be reflected in the latch 12 and not LC time, thereby providing for signals on GSR LCH lines as well as on the GSR lines 20-22.

9.C.6 GATE SELECT DECODE CIRCUIT FIG. 161a

In FIG. 161a, a plurality of gate select control bits are provided on corresponding GS bits lines 000-111 which are generated by corresponding AND-circuits 1, 2,-3 in response to various combinations of GSR input bits. This is a straight binary decoder which recognizes that bit 20 is high order, bit 22 is low order, and the various combinations of bits will generate a corresponding binary output line 000-111. These lines are utilized at the output of the AB register to select the correct instruction for application to the IOP register in the predecoder, as described in section 5.2.0.0.

9.C.7 GATE SELECT PARITY CIRCUIT FIG. 162

The parity stage of the gate select register comprises a latch 1 shown in FIG. 162. This latch generates a signal on a GS P line when set by an AND-circuit 2 in response to an OR-circuit 3 concurrently with the GS GT signal which is the same signal that is utilized to set and reset the remaining latches in the gate select register. The OR-circuit 3 is responsive to a signal on a SCAN IN GS COR PAR line or to the output of an exclusive OR-circuit 4. The exclusive OR circuit responds to parity as indicated by an OR-circuit 5 and to an invert parity function from an OR-circuit 6 so as to provide an output when there is no parity and the parity is to be inverted, or when there is parity and the parity is not to be inverted. Otherwise, the exclusive OR-circuit 4 will provide no input to the OR-circuit 3. The OR-circuit 5 responds to either one of two AND-circuits 7, 8 in respect to dependence upon whether there is no output or there is an output from an OR-circuit 9. The OR-circuit 9 in turn is responsive to an IC high-order advance as indicated by a signal on the IC HO ADV LCH lines, or to the output of an AND-circuit 10 which is operated during the last cycle of a successful branch as indicated by signals on the BR LC LCH lines and the BR SUCC LCH line. Thus, during the last cycle of a branch or an IC high-order advance, the AND-circuit 8 is operative to cause the parity bit of bits 16-23 or the ICR to be controlling, and otherwise, the incrementer parity bits 16-23 will cause the AND-circuit 7 to operate the OR-circuit 5 due to the gating effect of an inverter 11.

The OR-circuit 6 senses various cases where parity must be inverted due to the effect of the control inputs U and T on the gate select adder inputs u, t, h. Since the parity bit which is to be changed is that which accompanies an eight-bit byte including the three inputs to the gate select adder, and the only effect on that byte at the time of a gate select addition is the effect on bits 20-22 thereof, then the only effect on the parity is that which the control inputs have upon the input bits u, t, h. Each of the AND-circuits 13-16 recognizes a case where the parity of the entire byte must be changed in order to reflect the results of the addition. The theory of operation of each of the AND-circuits is very straightforward, and merely senses a condition where parity will change. As an example only, the following table illustrates the change in parity which is sensed by the AND-circuit 13, it being possible to draw a similar table for each of the AND-circuits 14 15 and 16, which has been eliminated herein, however, for simplicity. The changes in parity sensed by the AND-circuit 13 are as follows:

POSSIBLE INPUTS h t u P 0 0 0 10 0 1 01 0 0 01 0 1 1 CTRL INPUTS T, U 1 0 1 0 1 0 1 0 POSSIBLE RESULTS 0 1 0 00 1 1 11 1 0 11 1 1 0

9.3 address adder

9.3.1 brief description fig. 164

a typical prior art adder is shown in FIG. 163. The address adder and H used in the environmental system register are shown in block diagram form in FIG. 164. The addressing adder may be considered to be essentially in four sections.

In the first section comprising the circuits of FIG. 165 through FIG. 168 and FIG. 176, a plurality of inputs are combined so as to provide two inputs to the adder together with certain parity inputs. In the second section, which includes the circuit of FIG. 170 through FIG. 174, a final sum is generated in a method that utilizes the input bits as nearly directly as possible, so as to provide a very fast path for data which is flushed through the adder at times when the adder is merely used as a data path. In the third section, which includes the circuit of FIG. 176 through FIG. 180 parity for the sum is generated. The fourth section includes FIG. 181 through FIG. 183 in which various portions of the adder circuit are checked by independent circuitry. The output of the address adder is applied to the storage address register (SAR) in the BCU where it is used for addressing storage. The address adder output is also applied to the H register (FIG. 184), which is a sort of backup register for the SAR. The H register, in turn, feeds a program store compare circuit (PGM STR COMP), FIG. 186. Each of the circuits briefly mentioned is described in more detail in the ensuing sections.

9.3.2 INPUT SECTION

9.3.2.1 Adder Input Circuit FIG. 165

In the top of FIG. 165, general bus left signals from the general purpose registers on a respective plurality of GBL lines 8-31 are converted to signals on a plurality of corresponding lines L8-L31 together with the complements NOT L8-NOT L31. Also, the parity bits for groups 8-15, 16-23, and 24-31 are also provided. Notice that bits 0 through 7 of the GBL are not used in the address adder. In the center of FIG. 165 a plurality of signals on GBR lines 8-22 are converted to corresponding signals on a plurality of lines R8-R22 and their complements as well as the related parity bits RP 8-15 and RP 16-23. In addition, a plurality of OR-circuits 3 respond to either a plurality of general bus right signals on GBR lines 23-31 and P 24-31, or to a plurality of VFL LGTH (length) lines 23-31 and P 24-31 from the E unit. The outputs of the OR-circuits 3 comprise a plurality of lines R23-R31 (together with corresponding parity lines) and are applied to inverters 4 so as to supply complement lines NOT R23-NOT R31.

In the bottom of FIG. 165, D field signals from IOP are applied on a plurality of D FLD lines 20-31 so as to supply a corresponding plurality of signals on lines D20-D31, the signals on the lines D25-D28 being generated by a plurality of OR-circuits 5 in response to either the D field signals or to interrupt control signals on a plurality of IRPT CTRL lines 25-28. Complement lines are supplied signals by a plurality inverters 6. Additionally, parity bits D P 16-23 and D P 24-31 are provided.

9.3.2.2 Carry Save Sum And Carry Circuits FIG. 166 through FIG. 168

In FIG. 166a is illustrated the general data format for addresses applied to the addressing adder. Groups of four bits each are utilized for carry propagation purposes, the highest ordered group comprising bits 8-11, the lowest ordered group comprising bits 28-31. Therefore, bit 31 would supply a carry to bit 30, but not conversely. Similarly, propagation is from higher ordered bit to lower ordered bit throughout the adder.

In FIG. 166, a plurality of two- and three-input circuits are utilized to combine D and L inputs, and to provide carry outputs on a plurality of lines CSC 8-CSC 31, and the complements thereto on lines NOT CSC 8-NOT CSC 31. The three-input blocks 1 are illustrated in FIG. 168, wherein a CSC 20 line is energized by an OR-circuit 3 in response to any one of three AND-circuits 4 each of which responds to a different pair of inputs L20, R20, D20. Thus, the OR-circuit 3 will be operated whenever there are two or three inputs to the block 1. Similarly, a signal is generated on a NOT CSC 20 line by an OR-circuit 5 in response to any one of three AND-circuits 6 each of which is energized by a different pair of complement inputs NOT L20, NOT R20, NOT D20 so that a not carry save carry signal will be generated on a NOT CSC 20 line whenever there is concurrently absent two of the inputs to the block 1. Thus, the block 1, as shown in FIG. 168, will generate either a carry save carry signal or a not carry save carry signal in dependence upon whether there are at least two inputs present or nor more than one input present, respectively to the block 1.

The two input circuit 2 of FIG. 166 is illustrated in FIG. 167, wherein a signal is generated on a CSC 8 line provided there are two inputs present to an AND-circuit 7 on the L8 and R8 lines; similarly, a signal is generated by an AND-circuit 8 on a NOT CSC 8 line in response to the concurrent presence of complement inputs NOT L8, NOT R8. Thus the block 2 as shown in FIG. 167 will generate a carry save carry signal if both inputs are present, and will generate a not carry save carry signal if neither input is present.

At the bottom of FIG. 166 a plurality of EXCLUSIVE OR circuits 9 generate carry save sum signals on a plurality of lines CSS 8-CSS 31 in response to two or more input bits being present (or not) to the corresponding one of the circuits 1-3. The effect of FIG. 166-FIG. 168 is to convert the three inputs L, R and D to two outputs CSC, CSS, so as to permit implementation of the actual addition circuits in a two-input configuration rather than in a three-input configuration.

9.3.3 SUM GENERATING SECTION

9.3.3.1 Generate And Transmit Functions FIG. 169

The CSC and CSS signals generated in FIG. 166 are applied to FIG. 169 so as to produce transmit functions (T) and generate functions (G) which are utilized in variety of circuits within the address adder. Bearing in mind that the lowest ordered bit is bit 31 and the highest ordered bit is bit 8, the carries necessarily propagate from high-numbered bits (such as 31) to low-numbered bits (such as 8). The inputs to the adder comprise the outputs of the CSC and CSS circuits, and in each case, a transmit can be generated provided there is a sum for the corresponding bit or a carry for the next low-ordered bit. More specifically, a latch 1 will be set by an AND-circuit 2 in response to a not L controlled clock signal on the NOT LC line, provided there is a signal on the CSS 31 line. Similarly an AND-circuit 3 will cause an OR-circuit 4 to set a latch 5 if there is a signal on a CSS 30 line; similarly an AND-circuit 6 will cause the OR-circuit 4 to set the latch 5 if there is a signal on a CSC 31 line. Thus the OR-circuit 4 can respond either to a carry from the low-ordered bit (31) or a sum from the corresponding bit (30) so as to manifest a transmit function on the T30 line by means of the latch 5. In a similar fashion, all the remaining bits 8-31 of the carry save sum and carry save carry circuits are utilized so as to generate transmit bits on lines T8-T31, with the complements on lines NOT T8-NOT T31. Note that there is only one input to the AND-circuit 2 because there cannot possibly be a CSC 32.

At the bottom of FIG. 169 are circuits which produce the generate functions. The generate functions indicate that a carry is being generated in a particular bit for propagation into the next higher ordered bit. A carry will be generated whenever there is concurrently a carry save sum for the bit and carry save carry for the next lower ordered bit. Specifically, a latch 7 will be set by an AND-circuit 8 at NOT LC time provided there is concurrently present signals on the CSS 30 line and the CSC 31 line. Note that there can be no generate from position 31 (and that therefore no G31 line is shown) due to the fact there is no CSC 32, since the lowest ordered bit in the adder is bit 31. In a similar fashion, a latch 9 is set by an AND-circuit 10 at NOT LC time provided there is concurrently present signals on the CSS 8 line and the CSC 9 line. All of the latches in FIG. 169 are reset just prior to being set by the signal on the NOT LC line.

9.3.3.2 Group Transmit And Generate Circuits FIG. 170

The transmit and generate signals which are developed in FIG. 169 are utilized, inter alia, to produce group transmit and generate signals in FIG. 170. In this adder, addition is handled in four-bit groups such that a carry out of every fourth bit is considered a carry out of the group rather than a carry out of a bit as such. Thus, the OR-circuit 1, FIG. 170, will respond to a G28 to produce a generate function, and all higher ordered bits have transmit functions, then the generate will be transmitted through the group so as to produce a group generate. For instance, the AND-circuit 2 will respond to a generate in bit 27 together with a transmit for bit 28 so as to produce the equivalent of a generate for bit 28 which causes the OR-circuit 1 to produce a generate for the group (28-31). In a similar fashion the AND-circuit 3 will produce a group generate provided there is a generate for bit 30 and transmits for bit 29 and bit 28. The OR-circuit 1 responds only to two AND circuits and to the generate 28 function due to the fact that there is no generate 31, inasmuch as bit 31 is the lowest ordered bit in the entire adder. An OR-circuit 4 will respond to a generate for bit 24 or to an AND-circuit 5 which responds to a generate for bit 25 and a transmit for bit 24, to an AND-circuit 6 which responds to a generate for bit 26 together with transmits for bits 25 and 24, or to an AND-circuit 7 which responds to a generate for bit 27 together with transmits for bits 26, 25, and 24. In a similar fashion, generate signals are provided for all of the groups except for group 8-11.

At the bottom of FIG. 170, transmit functions for groups are produced merely by ANDing together transmits for the individual bits within the group. No transmit is generated for group 28-31 since there never can be an input carry to be transmitted through the group, inasmuch as this is the lowest ordered group in the adder. No transmit is generated for group 8-11 since there is nothing to which a carry may be transmitted inasmuch as this group is the highest ordered group in the adder. Thus transmits are generated for groups 12-15 through 24-27 by corresponding AND-circuits 8, 9 in response to the concurrent presence of all the transmits T12-T15, T24-T27 respectively, for each group.

9.3.3.3 Carry Into Group Circuit FIG. 171

The group generate and transmit functions which are developed in FIG. 170 are utilized in FIG. 171 so as to develop signals indicative of a carry into a four-bit group. A carry into a group is equal to a generate from the preceding group, which may be produced in a preceding group itself, or may be a generate produced in a still further lowered ordered group and transmitted through the preceding group. Thus, a generate in group 28-31 is equal to a carry into group 24-27 as illustrated by the top line of FIG. 171. An OR-circuit 1 in FIG. 171 will generate a signal on the C IN 20-23 line in response to a generate for group 24-27, or in response to an AND-circuit 2 which will be operative when there is a generate for group 28-31 together with a transmit for group 24-27. In a similar fashion, other carries into groups are generated, by corresponding circuits, the most complicated of which is that which generates a signal on the C IN 8-11 line in response to a generate for group 12-15, or in response to any one of four AND-circuits 4-7. The AND-circuit 7 responds to a generate for group 16-19 together with a transmit for group 12-15; the AND-circuit 6 responds to a generate for group 20-23 together with transmits for groups 16-19 and 12-15; the AND-circuit 5 responds to a generate for group 24-27 together with transmits for groups 20-23, 16-19, and 12-15; and the AND-circuit 4 responds to a generate for group 28-31 together with transmits for groups 24-27, 20-23, 16-19 and 12-15. Thus the carry in for one group can be a generate from the preceding group, or a generate transmitted from an even lower ordered group.

9.3.3.4 Carry Into Bit FIG. 172

As shown with respect to bits 30, 27-8 in FIG. 172, the carry in to the lowest ordered bit of a group is the carry in to that group, and a carry in to any other bit comprises a generate from the next lower bit or a generate transmitted from a still further lower ordered bit. Specifically, a carry in to bit 30 is a generate from bit 31. A carry in to bit 29 is produced by an OR-circuit 1 in FIG. 172 in response to an AND-circuit 2 whenever there is a generate in 31 and a transmit in 30, or in response to a generate for bit 30. Similarly, a carry in to bit 28 will be produced by an OR-circuit 3 whenever there is a generate from bit 29, when there is a generate for bit 30 together with a transmit for bit 29 which causes an AND-circuit 4 to respond, or in response to an AND-circuit 5 which is operative whenever there is a generate for bit 31 together with transmits for bits 30 and 29. The remaining circuitry of FIG. 172 (including that which is eliminated therefrom for simplicity) operates in a similar fashion.

9.3.3.5 Final Sum Generating Circuit FIG. 173

Final sums are generated in the address adder herein in a manner which is somewhat different from the usual carry lookahead adder; specifically, rather than using half sums of the inputs (essentially the EXCLUSIVE OR of the two input bits) together with lookahead-generated carries into each bit to generate the final sum for each bit, the present adder utilizes the transmit and generate functions of the input bits together with carries in to each bit so as to generate the final sum. Referring briefly to FIG. 174, an OR-circuit 1 responds to any one of four AND-circuits 2-5 to generate a final sum (FS). Each of the AND circuits responds to a different combination of bits so that the OR-circuit 1 will be operative provided there is an odd number of inputs thereto. The AND-circuit 2 will operate if there are all three bits T, G, C present, which bits represent the transmit, generate and carry-in functions to the corresponding bit. The AND-circuit 3 will operate provided there is only the transmit input, the AND-circuit 4 will operate provided there is only a generate input, and the AND-circuit 5 will operate provided there is only a carry input. Thus each of the AND-circuits 3-5 respond to one and only one input bit whereas the AND-circuit 2 responds to all three input bits being present. However, it is possible to simplify the circuit due to the relationship between the transmit and the generate function. Since the transmit function is equal to the presence of either of the two input bits CSC and CSS, and the generate function is equal to the presence of both input bits CSC, CSS, it follows that there can be no generate bit without there being a transmit bit, and it also follows that if there is a generate bit there must be a transmit bit. Therefore, since a generate bit is applied to AND-circuit 2, there will always be a transmit bit whenever there is a generate bit applied thereto; therefore, it is unnecessary to apply the transmit directly to the AND-circuit 2 of FIG. 174. Similarly, since the AND-circuit 4 requires the presence of a generate function concurrently with the absence of a transmit function (which can never occur), it is possible to omit the entire AND-circuit 4 from the final sum generator. Also, the AND-circuit 5 calls for the absence of a generate function which necessarily will occur whenever the transmit function is absent; therefore, it is unnecessary to apply the not generate function directly to the AND-circuit 5. Simplified versions of the circuit of FIG. 174 are utilized to form the final sum in FIG. 173.

In FIG. 173, the final sum for bit 31 is merely the carry save sum for bit 31 since there can be no carrier into the lowest ordered bit of the adder. An OR-circuit 6 responds to any one of three AND-circuits 7-9 to generate a final sum for bit 30 in accordance with the principals discussed hereinbefore with respect to FIG. 174. Specifically, if there is G30 and C IN 30, then the AND-circuit 7 recognizes the fact that all three inputs are present for that bit; the AND-circuit 8 recognizes the condition where there is no T30, and where, therefore, there can be no G30, but there is a C IN 30. The AND-circuit 9 is responsive to the presence of a T30 concurrently with the absence of G30 and C IN 30. A plurality of other OR circuits, one for each bit, each operative in the same fashion as OR-circuits 6 and 10, shown in FIG. 173, provide final sums for all of the bits of the adder in a similar manner.

It is to be noted that the use of the transmit and generate functions together with the lookahead carries into each bit has eliminated several stages of logic (which stages are shown in FIG. 175) so that whenever the adder is used as a data path with only a single input being applied thereto, this single input will propagate through the adder that much faster than it would if it had to be passed through the half sum circuits of FIG. 175.

9.3.4 PARITY GENERATING CIRCUITS FIG. 176 THROUGH FIG. 180

Parity for the address adder output is provided for each of the three eight-bit bytes; inasmuch as the adder is set up in terms of four-bit groups, parity is generated for each four bit group and the parity bits for each pair of four bit groups (which form a byte) are EXCLUSIVE ORed so as to form a final parity bit for the two-group, eight-bit byte to which the bit relates.

In generating parity for each of the four-bit groups, the first consideration is that the parity of any four bit group is equal to the EXCLUSIVE OR of the output bits within the group. As is known in the art, each sum bit is equal to the half sum EXCLUSIVE ORed with a carry into that bit, which in turn is equal to the EXCLUSIVE OR of the original input bits EXCLUSIVE ORed with a carry into that bit. Thus, the parity of a group will be equal to the EXCLUSIVE OR summation of each of the half sums in the group which is EXCLUSIVE ORed with the EXCLUSIVE OR summation of each of the carries into each bit of the group. The summation of the EXCLUSIVE ORs of all the carries into the bits of the groups is in turn equal to an odd or even status, as the case may be, of the total number of carries which are present for all of the bits within the group. This in turn can be produced in response to transmit and generate functions for the bits in the group. Thus, it is not necessary to rely on the carries into the bits to generate the parity for the address adder output and therefore it is possible to generate the parity at a time which is closer to the time at which inputs are applied to the adder circuit, due to the elimination of the time delay which results from the circuit response characteristics of the logic circuits which generate the bit carries. The oddness (or evenness) of the input bit carries does not, however, reflect a change in the parity due to a carry into the group; therefore, this factor must be taken into account by considering the effect of the parity of the group which a carry into the group will have. The effect of a carry into a group is handled by an invert parity function which changes the parity factor that is generated in dependence upon the oddness or evenness of carries within the group whenever there is an invert parity (INVRT P) function.

In this embodiment, parity of the final sum is determined by considering the fact that the parity of any data bit group is equal to the EXCLUSIVE OR of the individual bits in the group, the parity of each of said bits being equal to a half sum for that bit EXCLUSIVE OR'd with a carry into that bit. Thus, the parity for group 16-23 for instance, is equal to:

(HS 16 EXCLUSIVE OR C IN 16) EXCLUSIVE OR (HS 17 EXCLUSIVE OR C IN 17)--EXCLUSIVE OR HS 23 EXCLUSIVE OR C IN 23).

This function is equal to:

(HS 16 EXCLUSIVE OR HS 17--EXCLUSIVE OR HS 23)

Exclusive or (c in 16 exclusive or c in 17--exclusive or c in 23).

in this last equation, the first bracket is equal to the parity of the input to the carry lookahead adder, which in turn is equal to the parity of the input to the carry save adder EXCLUSIVE OR'd with the parity of the carries within the carry save adder; the second bracket is equal to the parity of the bit carries within one of the four-bit groups in an eight-bit parity byte, EXCLUSIVE OR'd with the parity of the carries of the other four-bit group within the byte. The parity of the bit carries within any four-bit group may be expressed in terms of the parity of the bit carries which do not consider a carry into the group EXCLUSIVE OR'd with a factor which reflects the difference if there is a carry into the group. Thus, the parity of the output of the adder for the byte which includes bits 16-23 is equal to the EXCLUSIVE OR of all of the following: the input parity of bits 16-23; the parity of the carry save carries for bits 16-23; an odd carry function for bits 20-23; an INVRT P factor for bits 20-23; an odd carry function for bits 16-19; and an INVRT P factor for bits 16-19. The odd carry function is the indication of whether the bit carries within the four-bit group are odd (or even), disregarding a carry into the group and the INVRT P factor is equal to the effect on this parity of the carry into the group; the effect is to reverse (or invert) the parity under certain circumstances. The generation of parity for the adder output is described in more detail in the description of the parity circuits in the following sections.

9.3.4.1 Address Adder Input Parity FIG. 176

The address adder input parity circuit of FIG. 176 utilizes a plurality of EXCLUSIVE OR circuits 1-3 to generate a single parity bit which reflects the parity of the inputs from the general bus left (GBL), general bus right (GBR), and from the D field (D). The EXCLUSIVE OR circuit 1 responds to the parity bits 24-31 for each of these inputs on the L P 24-31, R P 24-31, and D P 24-31 lines. Similarly, the EXCLUSIVE OR circuit 2 responds to three lines relating to parity for bits 16-23. The AND-circuit 3 responds only to GBL and GBR bits on the L P 8-15 and R P 8-15 lines since there is no D field input for the byte which includes bits 7-15 (see FIG. 165), and therefore no D field parity consideration is necessary in the circuit of FIG. 176.

Each of the EXCLUSIVE OR circuits 1-3 will cause a corresponding AND-circuit 4-6 to set a related latch 7-9 at not L time (due to the signal on the NOT LC line). The outputs of the latches 7-9 comprise parity bits of the input to the adder on corresponding PAR IN lines P 24-31 through P 8-15.

9.3.4.2 Half Sum Generator FIG. 175

True and complement representation of half-sums are generated in FIG. 175, wherein the half-sum for bit 31 equals the transmit for bit 31, due to the fact that there is no generate in bit 31 (which in turn results from there being no possibility of a carry input to bit 31, it being the lowest ordered bit in the adder). A plurality of AND-circuits 1 generate half-sums for each bit in response to the presence of a transmit together with the absence of a generate for that bit. A plurality of OR-circuits 2 generate complement half sums (not half sum) in response to either the absence of the transmit or the presence of the generate. Thus the OR-circuits 2 respond to no bits or two bits whereas the AND-circuits 1 responds to one bit only.

9.3.4.3 Odd Carry Generator FIG. 177

The odd carry generator as shown in FIG. 177 generates a signal, for each four-bit group within the adder, to indicate that the conditions within the group are such as will cause an odd number of carries into bits within that group, not considering whether or not there is a carry into the group itself. These signals are generated by a plurality of OR-circuits 1, 2-3, one OR circuit for each four-bit group in the adder. Considering first the OR-circuit 2, it can be operated by any one of four AND-circuits 4-7, each of which corresponds to a different situation. For instance the AND-circuit 4 will operate if there is a generate for bit 27, no transmit for bit 26, and no generate for bit 25. This recognizes the fact of a carry into bit 26 only. The AND-circuit 7 will operate if there is a generate for bit 2, and a transmit for bits 26 and 25, which will result in bit carries into bits 26, 25 and 24. The AND-circuit 5 recognizes the case when there is a carry into bit 25 only, which carry results from a generate in bit 26, the generate from bit 26 not being propogated due to the lack of a transmit for bit 25. The AND-circuit 6 recognizes the case where the only generate is that for bit 25 and therefore the only carry is a carry into bit 24. The relationships shown with respect to the AND-circuits 4-7 in FIG. 177 may most easily be understood with reference to FIG. 172, bearing in mind that the AND-circuit 4 covers the situation where there is a carry into bit 26 only in FIG. 172, the AND-circuit 5 of FIG. 177 covers the situation where there is a carry into bit 25 only in FIG. 172, the AND-circuit 6 in FIG. 177 covers the situation where there is a carry into bit 24 only in FIG. 172, and the AND-circuit 7 in FIG. 177 covers the situation when there is a carry into bits 24, 25 and 26 in FIG. 172. The effect of a carry into the group is considered with respect to the invert parity circuit of FIG. 179, to be described in section 9.3.4.5, hereinafter.

It is to be noted that the OR-circuit 1 is responsive only to two AND-circuits 8, 9 since there can be no generate for bit 31, the situation of there being a carry into bit 30, or into all three bits 28, 29 and 30 concurrently, cannot occur. Also, only two inputs are required to the AND-circuits 8 and 9 since these AND circuits need not recognize the condition of no generate from bit 31 since it is impossible for bit 31 to have a generate function. Thus the AND-circuit 8 responds to a carry into bit 29 only, and the AND-circuit 9 recognizes the case of the carry into bit 28 only; there is no case for a carry into bit 30 and there is no case for carry into three of the bits at one time.

For each of the groups including bits 8-23, the circuitry is the same as that shown for the group including bits 24-27, associated with OR-circuit 2.

9.3.4.4 Carry Save Parity Circuit FIG. 178

In FIG. 178, a plurality of EXCLUSIVE OR circuits 1 generate parity for three eight-bit groups on corresponding lines CSC P 8-15 through CSC P 24-31. The EXCLUSIVE OR circuits merely take into account the odd or even characteristics of the total bits present at the output of the CSC generator shown in FIG. 166. Note that the inputs to the EXCLUSIVE OR circuits 1 are NOT CSC lines (generated independently in FIG. 166) rather than CSS lines simply because this provides more independence of circuitry, so that in the event that the CSC bits are generated erroneously, the erroneous generation will not take any part in providing the CSC parity bits which are themselves used for generating the address parity. Thus, parity will be supplied for a correct address adder sum even though the address sum itself is incorrect, so that the parity circuits themselves will detect erroneous addition in more of the cases which might obtain.

9.3.4.5 Parity Invert Circuit FIG. 179

The parity invert circuit shown in FIG. 179 comprises essentially a plurality of AND-circuits 1-2 each of which corresponds to one of the four-bit groups 8-11- 24-27, there being no parity invert function for the group 28-31 (since there can never be a carry into that lowest-ordered group). Each of the AND-circuits 1, 2 is settable by a corresponding pair of OR-circuits 3, 4; 5, 6; respectively. The AND-circuit 1 will operate whenever there is a carry into group 8-11 concurrently with the absence of a half-sum for bit 11. The AND-circuit 1 will also operate whenever there is a carry into group 8-11 concurrently with the presence of a half-sum for bit 10 in the absence of a half-sum for bit 9. This is achieved by the OR-circuits 3, 4 which operate in a manner equivalent to that shown in FIG. 8. In FIG. 179, an AND-circuit 1a will operate in response to a carry into group 8-11 concurrently with the operation of an OR-circuit 7 which may in turn be operated either by a not half-sum for bit 11 or by an AND-circuit 8 which requires concurrent presence of a half-sum for bit 10 and no half-sum for bit 9. The circuit of FIG. 179 requires fewer levels so it operates somewhat faster than the circuits shown in FIG. 178, and is therefore usually found to be preferable. The AND-circuit 2 is equivalent in all respects to the AND-circuit 1, being operated in response to the outputs of OR-circuits 5 and 6 together with a carry into the bits 24-27.

The theory behind the circuit of FIG. 179 is illustrated in the following chart: ##SPC5##

The chart is illustrative of the operation of the AND-circuit 2 which generates a signal on an INVRT P 24-27 line. Considering the left most column, the bits within the groups 24-27 are shown when one ignores a carry into the group. In the second column from the left, the bits are shown after a carry into the group has been reflected. Whether or not a parity change has occurred in the bits (as a result of the carry in being reflected in the half sums), is illustrated in the third column, where an "X" delineates that a parity change has occurred. The right-hand column is indicative of the conditions utilized by the AND-circuit 2 and the OR-circuits 5, 6 to sense the configuration of half sums (as in the leftmost column) for which a parity change will occur and that, therefore, any parity predicted on the basis of half sums prior to the reflection of C IN 24-27 must be changed. Notice that bit 14 is immaterial in this logic due to the fact that the parity will either change or not in dependence upon the three lower bits of the group, without regard to the highest ordered bit, as indicated by the symmetry between group a- h (at the top of the chart) and group i-p (at the bottom of the chart). As an example only, line a of the chart illustrates that if the half sums for the group 24-27 are all ZEROS when one ignores a carry into the group, a carry in to the group will cause only bit 27 to change to a ONE. This results in a change in parity from even to odd and therefore must be sensed by the AND-circuit 2. Since the half sums in the leftmost column which do not take into account a carry into the group include not HS 27, that fact will be sensed by the OR-circuits 5, 6 causing the AND-circuit 2 to generate a signal on an INVRT P 24-27 line. All of the other groups generate invert parity signals in a similar fashion.

9.3.4.6 Address Adder Parity FIG. 180

In FIG. 180, each of three EXCLUSIVE OR complexes 1, 2, 3 generates a signal on a corresponding line P 24-31 through P 8-15. Considering first the EXCLUSIVE OR complex 2, a signal will be generated on the P 16-23 line provided there is an odd number of inputs to the complex. The theory of operation of the circuit FIG. 180 is discussed in section 9.3.4 and is based on the well-known axiom of the parity of the sum is equal to the parity of the inputs EXCLUSIVE OR'd with the parity of the bit carries within an adder. Considering that the inputs to the carry look ahead adder herein are in fact the carry save carries and carry save sums, the parity of the carry save carries and of the carry save sums is in fact the parity of the input. The parity of the carry save sums is identical to the parity of the input to the carry save adder, which in turn is the parity of the input bits to the entire address adder circuitry. This is true because each carry save sum is merely the EXCLUSIVE OR of the carry save inputs. Therefore, the input parity EXCLUSIVE OR'd with the parity of the carry save carries is equal to the parity of the input bits to the carry lookahead adder. The parity of the carries within the adder is equal to the parity of the bit carries which in turn equals the oddness (or the evenness) of the bit carries within the group, excluding the effect of a carry into the group, EXCLUSIVE OR'd with a signal indicating that the parity for that group should be inverted as determined by the INVERT P lines. Thus, the EXCLUSIVE OR composite 2 in FIG. 180 responds to the parity in and to the carry save carry parity of the two-group byte (16-23); to the odd carry and the invert parity function for group 20-23, and to the odd carry and invert parity function for group 16-19. Thus, all of the factors are taken into account by each of the EXCLUSIVE OR composites 1, 2, 3. Notice that the EXCLUSIVE OR composite 1 is simpler, because there is no invert parity function for bits 23-31 inasmuch as there cannot be a carry into group 28-31.

9.3.5 ADDER CHECKING CIRCUITS FIG. 181 THROUGH FIG. 183

To check the operation of the adder, a half-sum error circuit FIG. 181 and a carry error circuit FIG. 183 each determine independently whether or not there is an error in a carry or in the half sums generated for the adder. The carry error circuit FIG. 183 responds to carries out of each group from FIG. 182 and to carries into each group. The half-sum error is generated in response to adder input parities together with the output of the half-sum circuit 175. The details of the operation of the circuits are described in section 9.3.5.1 et seq.

9.3.5.1 Carry Out of Group FIG. 182

In FIG. 182, a plurality of OR-circuits 1, 2...3 is provided, one for each of the five lower-ordered four-bit groups in the adder, each generating a signal on a corresponding line: C OUT 28, C OUT 24,...C OUT 12, there being no carry out of the group which includes bit 8 since it is the highest ordered bit in the adder, and a carry out of the address adder is ignored. The OR-circuit 2, (as an example), responds to any one of four AND-circuits 4-7 each of which reflects a carry into a particular bit together with transmits for that bit and all higher ordered bits. For instance, the AND-circuit 4 reflects a carry into bit 27 together with transmits for bits 27, 26, 25 and 24; the AND-circuit 5 responds to a carry into bit 26 together with transmits for bits 26, 25 and 24; and the AND-circuit 7 responds to a carry into bit 24 together with a transmit for bit 24. Similarly, there is provided, for each of the four-bit groups in the adder (with the exception of the highest ordered group), an OR circuit to generate the carry out for that group in dependence upon proper combinations of carries into the lowest ordered bit of that group together with transmit functions to transmit the carry through the highest ordered bit of the group.

9.3.5.2 Half Sum Error Circuit FIG. 181

The half sum error circuit FIG. 181 comprises essentially an OR-circuit 1 responsive to either one of three inverters 2-4 which in turn respond to corresponding ones of three EXCLUSIVE OR composites 5-7, each of which checks the parity for one two-group, eight-bit byte. Since the half sums are equal to a condition of oddness as to each bit (that is, that there may be a carry save carry into the adder at that bit, or a carry save sum, but not both), it follows that the half sums should reflect the same parity condition as the parity of the input to the carry look ahead adder. As described in section 9.3.4.6, with reference to the address adder parity circuit of FIG. 180, the parity of the input to the carry look ahead adder is equal to the parity of the input to the carry save adder EXCLUSIVE OR'd with the parity of the carry save carries; therefore, each of the EXCLUSIVE OR complexes 5-7 is associated with an EXCLUSIVE OR circuit 8-10, respectively, which combines the parity into the address adder with the carry save parity so as to provide at the output of the EXCLUSIVE OR circuits 5-7 a signal which reflects the parity of the input to the carry look ahead adder. Thus, each of the EXCLUSIVE OR complexes 5-7 should reflect a total parity count which is odd, and in the event that it does, it provides a signal to the related inverter 2-4 which prevents the OR-circuit 1 from generating a half sum error signal on the HS ERROR line.

9.3.5.3 Carry Error and Addressing Adder Stop Clock Circuit FIG. 183

The carry error circuit shown at the top of FIG. 183 comprises essentially a single OR-circuit 1 (which could however of course be implemented by a suitable number of interconnected OR circuits of a smaller size) which responds to the outputs of a plurality of EXCLUSIVE OR circuits 2, 3,...4. Each of the EXCLUSIVE OR circuits compares a carry out of a bit with a carry into the next higher ordered group: for instance, the EXCLUSIVE OR circuit 2 compares a carry out of bit 28 with a carry into group 24-27. Since these should be identical, the presence of only one of them will cause the EXCLUSIVE OR circuit 2 to provide a signal to the OR-circuit 1 thereby generating a signal on the CARRY ERROR line.

The carry error and the half sum error are fed to corresponding AND-circuits 5, 6 at the bottom of FIG. 183. Either of these AND circuits or a signal on a SCAN IN AA ERROR line may operate an OR-circuit 7 so as to set a latch 8. The output of the latch 8 comprises a signal to the clock circuit to stop the clock because of an addressing error, said signal being passed via an AA STOP CLK line. The AND-circuits 5, 6 are operated by a signal on a SMPL AA ERROR line, which signal is generated in the general control circuits, for which reference may be made to other portions of said environmental system. Latch 8 is reset by a signal on the ERROR RST line.

9.3.5.4 Address Adder Outgating FIG. 185

In FIG. 185, a signal is generated on a GT AA TO SAR line by an OR-circuit 1 in response to interrupt, VFL, or IOP decode signals on the IRPT GT AA TO SAR, VFL GT AA TO SAR, or ID GT AA TO SAR lines. The ID GT AA TO SAR line is gated by an AND-circuit 2 at the turn on of T2. The VFL and interruption controls are also applied to an OR-circuit 2 to generate a signal on a SMPL AA ERR line to cause a sampling of address adder error when the address adder is actually used. The OR-circuit 2, as well as an OR-circuit 3 are operated also by a VFL GT AA TO H line. The OR-circuit 3 can thus generate a signal on a GT AA TO H line; notice that turn on of T2 will always cause the addressing adder to be gated to the H register due to the application to the OR-circuit 3 of a signal on the TON T2 line. As can be seen in FIG. 264, this is sometimes redundant, but nonetheless is provided automatically. OR-circuit 2 is also responsive to an AND-circuit 4 which will operate at the turn on of T2 provided there is a signal on a ID SMPL AA ERR.

9.4 H REGISTER AND PROGRAM STORE COMPARE

As shown in FIG. 75, the H register has the same inputs as SAR, and in fact, is loaded more often than is SAR. The H register provides internal indication of the setting of SAR, and additionally provides a medium for moving addresses within the CPU even though storage addressing is not involved, and so that SAR is not involved. FIG. 75 shows that the inputs to the H register are the address adder and the incrementer. The outputs go to the incrementer, to the program store compare circuitry of FIG. 72, to the channel and unit address circuits illustrated at the bottom of FIG. 75, and to various controls including the GSR.

The program store compare circuit (PGM STR COMP) is shown at the bottom of FIG. 72, and provides a means to compare inputs from ICR, INCR, and the H REG.

9.4.1 H REGISTER CONTROLS FIG. 184

In FIG. 184, a signal which permits changing the setting of the H register is generated on a UNLCH H REG line by an OR-circuit 1 in response to a signal on the SCAN IN TO H line or in response to either one of two AND-circuits 2, 3 which are gated at A time by a signal on the AC line. The AND-circuit 2 responds to a signal on the GT INCR TO H line, and the AND-circuit 3 is responsive to a signal on a GT AA TO H line.

An OR-circuit 4 provides a gate for the incrementer to feed H in response to either a signal on the GT INCR TO H line or in response to a signal on the SCAN IN TO H line. During scanning operation, the incrementer is used as a data path from the J register to reach the H register so that the bits involved in the test can be applied to the H register through the incrementer.

9.4.2 H REGISTER FIG. 184

In FIG. 184, the H register comprises a plurality of latches 1 each of which is settable by a corresponding OR-circuit 2 in response to a related pair of AND-circuits 3, 4. The latches 1 are reset and the AND-circuits 3, 4 are gated by a signal on the UNLCH H REG line. The AND-circuits 3 are responsive to a signal on the GT AA TO H line to cause corresponding bits of the address adder to set respective stages of the H register due to signals on the AA 8...AA 31 lines. The AND-circuits 4 are responsive to a signal on the IN GT TO H line so as to cause the latches 1 to be set by related bits of the incrementer due to signals on the INCR 0...INCR 23 line.

Two stages of the H register are buffered in a pair of latches 5, 6 each of which is settable by a related AND-circuit 7, 8. The latches 5, 6 are reset, and the AND-circuits 7, 8 are gated by the signal on the UNLCH H REG line. The AND-circuit 7 responds to bit 20 of the H register, and the AND-circuit 8 responds to bit 23 of the H register, so that there is provided signals on the H REG 20 LCH and H REG 23 LCH lines.

9.4.3 PROGRAM STORE COMPARE CIRCUIT FIG. 186

In FIG. 186, an AND-circuit 1 provides an indication that the setting of the ICR is equal to the setting of the H REG. This AND circuit is fed by a plurality of OR-circuits 2, 3 each of which responds to a related pair of AND-circuits 4, 5; 6, 7. Each of the AND-circuits 4, 5 relates to a corresponding bit of the ICR and the H register, such that the AND-circuits 4 sense the presence of ones in both ICR and H for the related bit, and the AND-circuit 5 will sense the presence of zeros in the related bit of both ICR and H. This is true for all of the bits 0-19, the output of either AND-circuit 4, 5 causing the OR-circuit 2 to provide an input to the AND-circuit 1. In the case of the OR-circuit 3, the AND-circuit 6, 7 will not operate during an IC high-order advance, due to the fact that a program store compare of ICR will be inaccurate during the updating (HO ADV) of the ICR.

At the bottom of FIG. 186, an AND-circuit 8 is responsive to a plurality of OR-circuits 9, 10 each of which responds to a pair of AND-circuits 11, 12; the OR-circuit 10 is also responsive to a signal on the NOT IC HO ADV LINE. Each of the AND-circuits 11, 12 is responsive to ones or zeros, respectively, in the related bits of both the INCR and H register. If all the bits are either both zero or both one, then the OR-circuit 9, 10 will energize the AND-circuit 8 thereby causing input to an OR-circuit 13 which is also responsive to the AND circuit. The OR-circuit 13 feeds an AND-circuit 14 which is gated by a signal on the UNLCH H REG line, the signal also being used to reset a latch 15 so that the latch may respond to the AND-circuit 14 when there is an output from the OR-circuit 13. The output of the latch 15 comprises a PSC signal which indicates that a comparison does exist within the program store compare circuit.

10.0 INSTRUCTION SEQUENCING

10.1 INTRODUCTION

Instruction execution in the system is performed in two parts: an I time and E time. The timing for a typical RX instruction is shown in FIG. 248 (see said System/360 Manual for details of an RX instruction).

I time (instruction time) is further broken down into two parts to perform "instruction handling," which includes the generation of storage addresses, and the gating of operands to the execution units from the general registers (GRs) or from the floating point registers (FPRs). The first part of I time is defined by the control trigger T1. The second part is defined by another control trigger, T2. When the T1 and T2 cycles have been completed, the proper execution unit or units may be started. Both T1 and T2 may be repeated, as necessary, until the aforesaid functions are completed.

E time (execution time) is accomplished within different areas: the E unit, the IE Unit and the branch (BR) Unit. All instructions require the use of at least one execution unit, and some require the concurrent use of two execution units.

The following instructions use both the E unit and the IE Unit:

ISK; SSM; LM; STM.

the following instructions require the BR unit as well as the E unit:

BALR (if R2 0); BCTR (if R2 0); BCT; BAL; BXH; BXLE.

when an execution unit is started, the I time control triggers begin their functions on the next instruction, overlapping the operation of the execution unit.

The T1 cycle is used to generate storage addresses when required. When this is completed, a logical control called TON T2 (turn on T2), which is developed from many conditions described in detail hereinafter, will initiate operand fetches from storage and set the T2 control trigger. During the T2 cycle, internal operands contained in either the general registers or floating point registers are gated to the execution unit. When the necessary conditions have been met, another logical control line called I TO E FER will cause the execution unit to start, unless an interruption has occurred.

While execution units are performing the actual functions of one instruction during a related E time, their "busy" state is recorded in control triggers located in the I unit. The last machine cycle for the E time conditions a turn off for a related busy trigger, IE BUSY or E BUSY; the branch unit uses the IE BUSY trigger to indicate the busy status of the BR unit. Since the I time for one instruction is allowed to overlap (occur simultaneously with) the execution of a previous instruction, interference which could occur for many instructions is avoided by generating various "blocks" which control the following instruction. Blocking can occur to either part (T1 or T2) of the overlapped I time, and may be removed at various points during the handling of a current instruction. It is advantageous to allow instruction handling to proceed to a point which just precedes causing interference with instruction execution. By providing two points at which blocking of the I time functions of the next instruction is employed, a variable degree of overlap is obtained, which provides versatility necessary for maximum instruction handling speeds.

10.1.1 T1 CYCLE

The basic function of the T1 cycle is to gate the fields required to form an effective address into the addressing adder. A control trigger, T1, defines this cycle.

10.1.1.1 Ton T1 (See FIG. 198)

If an instruction belongs to the class of instruction for which T1 of the next instruction may cause interference with execution of the first instruction, then T1 of the next instruction is always blocked. At the I to E transfer of the first instruction, the trigger BLOCK T1M is set if the instruction belongs to the interferring class. The interferring class is described in a subsequent paragraph. This blocks T1 of the next instruction until the unit executing the first instruction generates a signal cancelling the block. Similarly if an instruction belongs to the class of instruction for which T2 of the next instruction may cause interference with execution of the first instruction, the T2 of the next instruction is blocked, unless blocking of T1 provides sufficient delay. A trigger BLOCK T2M is operated in a method analogous to BLOCK T1M.

The T1 cycle is always taken as the first cycle of an instruction, even if no effective address is required: in some instructions, it procures only a single field to be used as an address. All fields are obtained from the general register(s) and/or the IOP register.

The turn on for T1 (called TON-T1 is controlled by many logic lines. The usual case is to turn it on with the I to E transfer of the previous instruction. Before the I to E transfer occurs, BOP decoding examines the class of the instruction and determines if blocking of T1 of the next instruction is required. If BOP senses that blocking of T1 is required and generates a BD BLOCK T1 signal, then the I to E transfer is not allowed to turn on T1, but instead turns on the BLOCK T1M trigger, which maintains the blocking of T1 during successive cycles. When the E time execution has progressed to the point of no longer interfering with instruction handling, it will generate a signal to turn off the BLOCK T1M trigger and to generate the TON-T1 condition.

T1 may also be turned on by NOT BLK TIM, which allows the system to start up after it has been manually halted. FIG. 249 shows the timing of the decode line from BOP, BLOCK T1M and the effective blocking condition. Instructions that generate blocking of the next T1 cycle are listed below with a short statement as to why the blocking is required.

All SS instructions and SPM, SSK, MR, DR, D, BXH, BXLE, STM: require reading out of the general registers during the E time of the instruction. The execution unit is required to turn off the blocking trigger when this gating is no longer required.

All I/O instructions: The channel and unit addresses are sent to the I/O devices from the H Register. Blocking of T2 would prevent H from being changed; however, the release line from the channel (used to end the instruction) could extend into the next instruction and, if it were another I/O instruction, cause premature termination. This may occur because the Release line is multiplexed and uses slow circuits. Thus T1 is blocked to allow the extra start up cycle, when necessary.

Load Address: The effective address must be saved in the H register until the E unit can transfer it to a general register. Although blocking of T2 could accomplish this, simplification of packaging requirements caused T1 to be used: no additional delays resulted.

Load Multiple: In the LM instruction many general registers are loaded. The compare block is not capable of detecting a compare from more than two registers.

LPSW: In load PSW the ICR is changed so that instructions will need to be fetched to the AB register before processing can continue.

DIAGNOSE: Until the MCW (maintenance control word) is loaded and the error status lines have settled down, any further instruction execution must be blocked.

SVC: The supervisor call instruction requires blocking of T1 to prevent TON T1 from changing IOP. IOP is required during the setting of the interrupt code into the PSW.

In addition to the foregoing block conditions, the program halt trigger can also prevent TON T1. This trigger, located in the maintenance console, is used for the maintenance functions MANUAL HALT, IS RATE, etc. An output of the program halt trigger is latched on the sequence control board and deconditions TON T1.

10.1.1.2 Set IOP

As described in other sections, the IOP register contains two instruction halfwords. The first halfword contains an operation code and, for multiple halfword instructions (all but RR), the second halfword is used for addressing. Handling of the third halfword, required by SS instructions, is described hereinafter. The instruction formats along with the fields contained in each are shown in FIG. 250. By means of the gate select mechanism, any successive two of the eight halfwords contained in the instruction buffers (A and B registers) are selected and sent to the IOP register. The proper selection is normally made during a T2 cycle of the previous instruction. The gate select mechanism causes the length of the previous instruction, as decoded from the first two bits of IOP, to be added to the ICR and this value to be stored in the gate select register (GSR) at TON T2. The output of the gate select register selects a particular 32-bit halfword from the two storage words, totaling 128 bits, in the A and B registers, for IOP. With the I to E transfer the gate select register contents are sent back to the ICR thus updating the ICR. Processing of the SS format instructions required the implementation of additional controls for the gate select mechanism and the setting of IOP. They are unique to these instructions and are described hereinafter.

The T1 function can be (and often is) accomplished in one machine cycle. However, if the conditions to generate TON T2 do not exist, the T1 cycle continues to repeat itself until TON T2 occurs. IOP is set to the selected contents of the AB register at the beginning of every T1 cycle. The logic line TON T1 sets IOP for the first T1 cycle. If T1 repeats itself, SET IOP occurs at the beginning of each machine cycle until TON T2 occurs. There is one exception to the latter set condition. During the EXECUTE instruction, the setting of IOP is blocked for the T1 cycle which occurs after the modification of the subject of an Execute instruction has taken place. This special block is represented by the presence of NOT IOP LOADED or NOT XEQ SEQ.

A special set, SSOP and NOT VFL ADR, is also provided for setting IOP ON SS instructions. Therefore the total expression of conditions for setting IOP is: TON T1, or T1 and NOT TON T2 and NOT IOP LOADED or XEQ SEQ, or SSOP and VFL ADR.

I time may start (e.g. T1 may turn on) even though the selected instruction has not yet returned to the instruction buffer (AB register). This may occur, for example, after successful branches or recoveries. Since T1 cannot be turned off (see TON T2) until the selected instruction has returned to IOP, it follows that there will be at least one T1 cycle during at least a part of which IOP has contained the correct instruction.

The selected instruction will arrive at IOP during the same cycle it returns to the AB register since SET IOP has occurred for each T1 cycle. It should be noted that if the selected instruction is contained wholly within one register then waiting is only required until this register is loaded.

10.1.1.3 Effective Addressing

The T1 cycle conditions input gating to the addressing adder, for up to three fields. The fields determined by the instruction are selected by IOP. The contents of general register specified by the R2-X field of the instruction are gated to the addressing adder via GBR, (general bus right) and the contents of the B2 register (general register specified by the B2 field) via GBL. D2 is gated directly to the addressing adder from IOP. The general register busses (GBL, GBR) are 32 bits wide. However, only the low-order 24 bits participate in the address generation. The D field is 12 bits wide. When general register zero (GRO) is specified as one of the fields, that adder input receives all zero data with correct parity for that field. The instructions in the RR format are exceptions in that they make no distinctions for GRO.

The effective address is 24 bits wide. With TON T2, it is always gated into the H register, and may also be sent to SAR. When the effective address is sent to SAR the error checking of the AA is sampled. All of the above conditions are decoded by IOP. The RS shift type of instructions, which use the effective address only as a shift amount, are unique in that they sample the AA error but that they do not send the result to SAR.

Components of the effective address are shown in FIG. 264 et seq. For many instructions that require no effective addressing, a quantity is generated and set into the H register at TON T2. This occurs through "loose decoding." These components are noted in FIG. 264 et seq. and shown by an asterisk.

10.1.1.4 T1 Cycle Additional Functions

The T1 control trigger has outputs used in other areas of the machine: e.g., it is used during the maintenance feature IS RATE (which lets the system execute one instruction, and then stop), to turn on BLOCK T1M trigger and also used by the E unit for setting EOP.

The T1 cycle during which TON T2 occurs can be considered the "good T1 cycle." For TON T2 to occur, every condition for the T1 functions must be available, and every blocking condition preventing the second part of I time (T2) must have been removed.

10.1.2 TON T2 (SEE FIG. 205)

The following are the conditions necessary to generate the logical control TON T2:

IOP LOADED: The IC controls generate this condition if the selected gate (from AB to IOP) is pointing to a loaded instruction in the AB register.

NOT COMP BLK or NOT E BUSY: Buffer Operation Register (BOP) decodes those E Unit instructions that will perform "put-aways" to the general registers. A comparison occurs when the "put-away" is scheduled to any of the general registers used by T1 of the next instruction. T1 must subsequently stay on until the new result has been put away. This waiting is accomplished by blocking TON T2. The block exists until the E BUSY trigger is turned off.

NO INSTRUCTION FETCH PRIORITY: When the processing has emptied one instruction buffer (either A or B) and is approaching the point of emptying the second buffer (either B or A), without having allowed the first to be reloaded, the IC controls may generate a block TON T2 until an IC fetch is made. This gives the IC controls access to SAR.

NOT BLOCK T2M or TOF BLK T2M: This condition is available if the previous instruction processing has not set the BLOCK T2M trigger or if the E unit is turning off BLOCK T2M.

10.1.2.1 Block T2M

The need for the blocking of T2 is determined in the same manner as is the blocking of T2: BOP decoding generates BD BLK T2, which, with the I to E transfer, turns on BLOCK T2M. Since TON T2 can never occur with the I to E transfer which is when a new T1 is normally started, no additional logic is needed to anticipate the blocking of T2 as is required for the blocking of T1.

Some instructions will generate both BD BLOCK T1 and BD BLOCK T2. In these cases, both block triggers are set, and when the processing no longer requires the blocking of T1, the E unit turns it off. Processing continues and the overlap is started on the next instruction. However T2 is blocked until the E unit turns off BLOCK T2M.

The following paragraphs show the instructions that generate BD BLOCK T2 and the reasons for this.

ISK, ST, STH, STC, CVD, STD, STE, RD, STM, MVI, NI, OI, XI, and all SS instructions: Operand fetches are generated by the execution unit, or operands are to be stored in external storage. For these instructions, SAR is required to provide the necessary storage addresses. SAR must not be changed by TON T2 of the overlapped instruction.

LH, CH, AH, SH: The E Unit requires the RBL as part of the data path to expand the fields to 32 bits. T2 of overlapped instructions is blocked to prevent the gating of operands into the RBL.

MR, DR, MDR, DDR, MER, DER, MD: The E Unit requires the J register as part of the data path during E time. Overlap of the next instructions could result in a fetch of an operand to J if T2 were not blocked.

For branch instructions the BLOCK T2 trigger is turned on by BRANCH OP and I TO E XFER. This blocks the second part of I time on overlapped instructions until the success of the branch is determined. Blocking T2 eliminates the need for recoveries if the branch is unsuccessful and protects the contents of the H Register which contains the address of the subject (or branch-to) instruction.

Logic is provided to remove the Block T2 condition at the earliest time possible. Each turn off for the Block trigger also enters TON T2 as a conditioning level. The only exception occurs during the EXECUTE instruction. Here the BLOCK T2M trigger is turned off one cycle before T2 is allowed to turn on. In this case the latched output of BLK T2M maintains the block for this cycle.

When blocking is employed to protect SAR, the execution unit conditions the turn off of BLOCK T2M with TOF BLK T2M ON ACC at the appropriate time during instruction execution. This control line and ACCEPT (from the BCU) turns off BLOCK T2M.

If the blocking was protecting the J register, E TOF BLK T2 is generated by the E Unit to turn off BLOCK T2M. This line is always generated during the last cycle of relevent instructions; and if the system is not in single cycle mode, the line is also generated a number of cycles before J is free. T2 can be allowed to turn on earlier because any operand fetches it may initiate would not return to J for at least four cycles. The turn off may be anticipated for up to three cycles before J is free. If RBL usage requires blocking T2, the E Unit generates TOF BLK T2M when this usage is no longer required.

10.1.2.2 Compare Block

A compare block condition with E BUSY on causes a deconditioning of TON T2. If the previous instruction is doing a put-away into a general register which is to be used to compute an effective address during T1 of the next instruction, then T1 of the next instruction must be held up until the operands have been put away. This condition is detected by comparing BR 1 to both IR2 (R2-X) and IB. IR2 and IB contain the address of the general registers which are to be used to form the T1 cycle effective address, and BR 1 contains the address of the general register into which results of the previous instruction are to be put away.

BOP remains unchanged from the previous instruction until TON T2 of the next instruction (see FIG. 251) and therefore provides the op code of the previous instruction during T1 of the next instruction. On the basis of BOP, it is determined whether or not the previous instruction requires a put-away to the general registers. It is also determined if there is a pair of put-aways to an even odd pair of general registers.

If BOP indicates a single put-away (BD COMP REQ) then BR 1 is compared to IR2 (which is also IX2) and IB according to their usage in the effective address. Clearly IR2 (or IB) is not used in the effective address if it references GR O. If BOP indicates a double put-away to an even odd register pair (BD DBL REG COMP) then the same compares are made as for a single put-away; but the low order bit is ignored in the compare. If either compare is satisfied, and if E BUSY is on, then COMP BLK (compare block) prevents T2 from turning on. All put-aways to the general registers are completed before the end of the last E cycle of an instruction. The usage of E BUSY in COMP BLK insures that if a compare situation occurs, at least one correct effective addressing cycle (one "good" T2 cycle) is taken after the execution of the previous instruction is completed.

In the discussion of T2, no control comparable to COMP BLK is required in the gating of internal operands to the E unit. No block is necessary because all put-aways are completed by B time of ELC (E last cycle). In the remaining half cycle, any general register may be gated to the E unit before the I to E transfer.

10.1.2.3 Ton T2 Conditioning of Functions Controlled by IOP

As stated, the TON T2 indicates a "GOOD" T1 CYCLE. In addition to providing a setting condition for the T2 cycle, it performs many functions. IOP decoding controls the TON T2 condition. The following functions are described with respect to their functions at TON T2:

Id aa to SAR: with TON T2 the effective address formed by the AA is gated from the AA latches into SAR.

Id smpl aa err: tests the error checking lines of the AA during TON T2. If an error occurs, it causes a machine check condition.

Id ftch cl: indicates that operand fetching is required. With TON T2 it initiates the request to BCU.

Id block ic: at TON T2 this forms the third blocking condition. It prevents IC fetches from interfering with instruction processing. It also forms the TON for BLOCK IC M, a control trigger used to maintain the IC blocking condition.

Id fp: used in the controls that gate out the floating point registers; it sets the FLOUT trigger with TON T2.

Id rr: used during TON T2 to set the FR2 trigger. FR2 determines the order in which floating point operands are gated to the E Unit. This is further discussed in the T2 CYCLE.

Id ss: id ss conditions the sequencing controls to process the SS format instructions by turning on the SSOP control trigger with TON T2.

Id b rop: sets the BRANCH OP control trigger with TON T2. BRANCH OP is a status trigger used during branches. ID BROP is also used to override any blocking of TON T2 generated by the IC controls.

10.1.2.4 Ton T2 Additional Functions

In addition to the foregoing functions, which are controlled by IOP, TON T2 also conditions the following additional functions:

Setting the Gate Select Register: During T1 the instruction in IOP is examined to determined its length (in halfwords). This length is added to the ICR low order. With TON T2 the adder output is gated into the GSR. Gate selection now changes and a new gate for AB to IOP is selected to handle the next instruction.

Setting of IOP: Since TON T2 indicates a "good" T1 cycle, the TON T2 logic line deconditions the setting of IOP from the T1 latch output.

Setting of BOP: The setting of BOP usually occurs with TON T2.

Instruction buffer empty condition: When the last instruction located in one of the AB registers has been selected and set into IOP, TON T2 indicates the empty condition to the IC fetch controls and turns off the appropriate loaded trigger.

Iop error: TON T2 is used to test the parity of IOP bits 8-15, and if an error exists, the IOP ERROR trigger is turned on.

Interruptions: I PGM IRPT is set at TON T2 if the instruction being executed is from an invalid storage address, if bit 23 of the address of the instruction is one, or if the op code of the instruction is invalid. The Interruption Code for the type of interruption is set into the PSW with TON T2.

H reg: the output of the addressing adder is always set into H at TON T2.

10.1.2.5 BOP

BOP Buffer (or backup) op register is a 12-bit op register set from IOP 0-11. By taking advantage of the way E time and I time are overlapped, three areas are able to share usage of BOP. BOP is used by T2 during the cycle of the I to E transfer, and it is used by branch executions and IE executions during E time (see FIG. 251).

Branch executions and IE executions have been implemented in a way such that no op code is required by the execution unit during the last cycle. Since the I to E transfer of the next instruction cannot occur until the end of execution (E time) of the previous instruction, it follows that there is a time to set BOP which accomplishes all of the following:

1. BOP is not to be updated until one cycle after IOP is correctly set.

2. BOP is updated at least one cycle before the I to E transfer.

3. BOP is available to the branch and IE units for the cycle before the I to E transfer and for every E cycle except the last (ELC).

4. no performance penalty is taken because of shared usage of BOP. The specific logic implementation to control the setting of BOP is as follows:

Bop is set at TON T2 if IE BUSY is off, indicating that neither the IE unit nor the branch unit are operating. BOP is set at TON T2 if either IEL (IE unit last cycle) or BRLC (branch unit last cycle) is on, indicating that the relevent unit is finishing execution. These set conditions are not, however, sufficient to insure that BOP is set at least one cycle before an I to E transfer whenever the previous instruction is an I execution or an unsuccessful branch. In the case of IE Unit execution, the combination of TON IEL, and TON T2 or T2 is used to obtain a further set condition for BOP. Thus BOP is set one cycle early even if IEL causes an I TO E XFER on the next cycle.

For unsuccessful branches, T2 can be turned on with the turn on of BRLC but not before. Therefore, TON T2 is combined with the turn on of BRLC due to the unsuccessful branch to obtain another setting of BOP. Thus, for unsuccessful branches, BOP is set one cycle early even if BRLC causes an I TO E transfer on the next cycle. For successful branches, T2 is never turned on until BRLC is turned off; therefore no special set is required for successful branches.

BOP decoding is used during the T2 cycle to specify: (1) which internal registers are to be gated to the RBL as operands, (2) the execution unit(s) required to perform the E time of the instruction, and (3) at what point overlap of the next instruction is to be blocked if necessary. BOP decode lines also define many functions of the store instructions. A list of the BOP decode lines can be found in FIG. 92 through FIG. 97. The fact that BOP is still maintained during T1 of the next instruction allows its usage in generating the compare block of TON T2.

10.1.3 T2 CYCLE

The TON T2 logic control indicates that the T2 cycle has been properly performed and thus initiates the T2 cycle. The T2 cycle has, as one of its functions, the gating of internal operands.

10.1.3.1 Internal Operand Gating

Internal operands are gated to the RBL (register bus latch), a 64-bit latch located in the E Unit. RBL is latched (unchanging) during every L clock and unlatched (setable) during every not L clock. Operands from the general registers are sent to RBL via GBL or GBR. However, if the instruction is in the floating point class, operands are gated from the floating point registers, which are located in the E unit, instead of from the general registers.

General register operands are gated to RBL by T2 if IOP bit 2 = 0 (indicating an instruction other than floating). Operands are gated simultaneously to RBL by T2 on GBL (general bus left) and GBR (general bus right). General register BR 1 is gated to GBL and either general register IR2 or general register BR 1 is gated to GBR. BR 1 + 1 is gated to GBR for all shift and all RX instructions, and for MR; for all other instructions, IR2 is gated to GBR. The execution unit ignores those operands gated by T2 which are not needed to complete the instruction.

Certain instructions require that gating be continued after the I to E transfer or that additional operands be sent. This gating is accomplished by the control triggers GROUT or FLOUT. FLOUT is set with TON T2 for any floating point instruction, regardless of format. The timing for FLOUT, is shown in FIG. 253. It opens the gate from the floating point registers (FPRs) to the RBL. Floating point register gating is performed on the full 64 data bits of the registers. Thus each addressed register fills the RBL. For instructions in the RR format this full gating means that the two operands must be sent sequentially. With TON T2 and ID RR present, a control trigger FR2 (located in the PDU) is conditioned. The FR2 trigger causes floating point register gating to be addressed by the IR2 field, (the second operand). The turn on for FR2 is maintained during subsequent T2 cycles (if they occur) by T2 and the BOP decode line BD RR; the turn on for FR2 condition is removed with the I to E transfer. With no turn on, the FR2 trigger will turn itself off. When FR2 is off, the first operand (addressed by the BR 1 field) is selected for gating to the RBL by FLOUT. FLOUT stays on after the I to E transfer, and the E Unit provides a turn off when gating is no longer required. Normally the turn off is generated during the first E time cycle. The exceptions are the divide instructions. Divide instructions require prenormalization of the divisor to be completed before the second operand, the dividend, can be accepted. For the divide instructions, BLOCK T2 M is set and this prevents TON T2 which prevents the overlap of another instruction from setting the FR2 trigger prematurely.

10.1.3.2 Incrementer Gating

During branches, the effective address formed by T1 is the address of the instruction to which a branch must be effected. Since two instructions buffers (A, B) are provided within the CPU, two effective addresses are required in order to fill them both. The H REG and SAR are set to the effective address by TON T2 which also initiates the first fetch. The second address is formed by adding a control amount (1 in position 20) to the contents of the H Register; T2 and BROP gate the H Register and the control amount to the incrementer. With the I to E transfer, the output of the incrementer is sent to SAR. Branch controls initiate the second fetch.

The LM instruction requires that the effective address of the H REG and SAR be updated by one storage word after the first operand fetch has been made. The BOP decode line BD LD MPL gates the contents of the H Register and a control amount (+1 in INCR position 20) to the Incrementer. With the I to E transfer the incrementer output is sent to SAR and H.

Any time the output of the incrementer is gated into a register, the checking circuits in the incrementer are tested. If there is an error the INCR ERROR trigger is turned on. Therefore, the incrementer error line is tested at the I to E transfer of branches and LM.

10.1.3.3 Operand Fetching

Most features of a T2 operand fetch request are similar to the features of all CPU fetch requests. Operand fetch timing is shown in FIG. 254. If IOP contains an instruction requiring an operand fetch, then TON T2 and ID FTCH CL generates a fetch request. This turns on the CPU REQ trigger at A time in the BCU, which actually initiates storage operation. The TON T2 and ID FTCH CL combination also turns on the trigger OPF (OPERAND FETCH) in the I unit controls. Whenever a fetch request is made, SAR must be loaded with the correct fetch address at the time of the request (or earlier). For all instructions requiring a fetch during I time, the logic combination of ID GATE AA TO SAR and TON T2 sets SAR from the address adder with an A clock.

The CPU REQ trigger is normally kept on until the request is accepted. However, if the request line from CPU is cancelled, the CPU REQ turns off on the next A clock. This feature is very useful, as it enables fetch requests which have not been honored by the BCU, and which are no longer needed, to be self-cancelled. This ability is used extensively during IC fetching, and is also used to cancel fetch requests when entering an interrupt sequence. In the case of T2 operand fetches, the request line is held up by the latched output of OPF.

Whenever the CPU REQUEST trigger is on, a requested storage is not busy and a channel does not have priority, then the requested storage is started at about B time. The BCU then generates a signal called ACCEPT, which straddles the next A clock. This is distributed throughout the CPU. If OPF is on, ACCEPT turns the OPF trigger off, thus dropping the request. The request does not drop early enough to prevent setting of CPU REQ again at the A clock straddled by ACCEPT. The two cycle repetition rate of BCU prevents any further action being taken by the request, and CPU REQ is immediately reset with a BR (B running) clock.

ACCEPT rises with an early BR clock (EBR) and remains until the next early B clock. Thus A clock is straddled by ACCEPT even if the clock is being single cycled. This line is used in connection with conventional CPU request logic. There is another accept line, called pulsed accept (P-ACC), which rises at the same time as ACCEPT, but which falls on the next EBR clock, so that P-ACC straddles the next AR clock only. Pulsed accept is used primarily in the branch and IC controls.

OPF is also used to indicate that the fetch should be returned to the J register. The unlatched output of OPF is OR'ed with certain other fetch controls and sent to BCU. This line is used by BCU to set up a return address register for a return to J. When the storage provides the requested word on the SBO, the storage also sends a line called "advance" (ADV) to the BCU: ADV and a BR clock are used to gate the storage data into the SBO latch. If the appropriate return address register indicates a return to J, the ADV is gated out to the CPU as J ADV, which is used with an AR clock to gate the SBO latch data into the J register and to turn on J LOADED. The trigger J LOADED indicates to the various execution units that the fetched data has returned and is in the J register; J LOADED is normally turned off when the data is transferred out of J.

In the standard storage configuration, data is returned four cycles after CPU REQ is set (assuming that the requested storage unit was available). The storage times out in five cycles and is available at that time for another operation. A fetch of an operand from an odd address (which includes a ONE in bit 20) can be overlapped with a fetch of an operand from an even address. Fetches from addresses with bit 20 identical (both odd, or both even) cannot be overlapped.

Because of the overlapped operation of the BCU, it is possible for two operand fetches for two different instructions to be outstanding at the same time. This does not cause difficulty because the relevent execution unit clears out the contents of J before the second fetch returns. At the time the J register is cleared out, J LOADED is also turned off and the controls are thus prepared to receive the second fetch. In the few cases where the execution unit cannot clear out J in time (e.g. multiply or divide) T2 and the associated fetch of the next instruction are blocked until such time as J register availability may be anticipated.

10.1.4 I to E transfer

The I to E transfer is a logical control generated during the "last" T2 cycle. The principal function of the I to E transfer is to initiate the start of E time: The I to E transfer occurs when all of the T2 cycle functions for one instruction and the E time of the previous instruction, have both been completed. Lines from the interrupt mechanism further condition the I to E transfer. If an interrupt is outstanding, the E time is not started, but the interrupt mechanism begins an interrupt sequence instead.

10.1.4.1 Generation of I to E Transfer

The logic for the I to E transfer is T2 and LCM and either OPF or ACCEPT. LCM (last cycle memorized indicates that E time of the previous instruction has been completed. The other two quantities indicate that I time of the instruction to be transferred for execution is completed. If OPF is not on then, either no operand fetch was required or the fetch request already has been honored by BCU, since ACCEPT turns off OPF. Use of ACCEPT directly in the generation of I to E transfer allows the I to E transfer to be made at the time the request is honored.

LCM is the part of the I to E transfer statement which occurs when a previous E time reaches its last cycle or when all execution units are idle. The execution units are idle when both E BUSY and IE BUSY are off. E BUSY is turned on at the I to E transfer of any instruction starting the E unit. ELC turns E BUSY off unless it is also being turned on by the next instruction. IE BUSY is turned on at the I to E transfer of any instruction which starts the branch unit or the IE unit. BRLC or IEL turns IE BUSY off unless it is also being turned on by the next instruction.

The last cycle of E time must be allowed to condition the I to E transfer in order to provide successive E times without idle machine cycles. Since two execution units may be required to accomplish execution of an instruction, further complications arise in determining the true last cycle of E time. The last cycle logic from each of the execution units cannot alone indicate the true last cycle. Only when the last of two units completes its operation, or when both end simultaneously, can a true last cycle be generated.

As shown above, none of the instructions require that the branch unit and the IE unit both operate simultaneously. It is this fact that allows both these units to share the same busy trigger (IE BUSY).

Testing for the true last cycle is performed in the following manner. When any unit sends its last cycle, this last cycle is compared against the busy trigger of the other unit. If the busy trigger for the other unit is off then the last cycle condition is the true last cycle. If the other busy trigger is still on, the last cycle of the first unit only provides a turn off for its own BUSY trigger. Logic is also provided to test for the simultaneous ending of the two units. The simultaneous occurrence of both last cycle conditions generates a true last cycle, called CTRL LAST CYC. Any one of the following statements will cause the true last cycle to be determined:

IEL or BRLC and NOT E BUSY; or ELC and NOT IE BUSY; ELC and IEL or BRLC. The logic control generated by the above function is called CTRL LAST CYC, and it is used in generating LCM. It is also sent to the interrupt mechanism where it is used to indicate that E time is ending so that the interrupt mechanism may test for E time interrupt conditions.

10.1.4.2 Interruption Effect On Instruction Sequencing

Since interruptions are so important to the I to E transfer, they are discussed before going further into the functions performed at that time. There are two classes of interruptions: I time interruptions and E time interruptions. I time and E time interruptions are distinguished by the time that the interruption is processed. I time interruption sequences are entered at the I to E transfer and E time interruptions are entered after the last cycle of execution time.

I time interruptions may be detected during T1 or T2. Interruptions resulting from instructions located in an invalid storage address, from instructions located on a non-half word boundary, or from instructions with invalid operation codes are detected during T1. If any of these interruptions occur, I PGM IRPT is turned on with TON T2. At the same time, the interruption identity code is set up for the type of interruption which has occurred. An I time interruption is then taken at the time of the I to E transfer and no execution unit is started.

Interruptions resulting from an invalid operand specification, from an attempt to process an EXECUTE instruction while in execute mode, from decoding the instruction SOS, or from decoding of a privileged instruction while not in monitor mode are all detected during T2. If any of these interruptions occur (except supervisor call), I PGM IRPT is turned on with the I to E transfer. If I PGM IRPT was not previously on, the interruption code is set up at the I to E transfer for the type of interrupt which has occurred. An I time interruption is then taken at the I to E transfer and no execution unit is started.

I time interruptions are entered into at I to E transfer time by turning on the trigger I IRPT END in the interrupt sequencing controls. The essential control which does all the conditioning for I time interruption is I IRPT FM I.

E time interruptions are normally detected during the last cycle of instruction execution. Certain E time interruptions are also detected during an interrupt last cycle or while the system is in WAIT status.

E time interruptions are generated in two locations: the I unit and the E unit. Interruptions which are detected in the E unit during the course of an instruction are set into a buffer register in the E unit. These interruptions are program interruptions such as divide check, exponent overflow, etc. The detection of such an interruption results in E IRPT FM E. A second group of E time interruptions consist of interruptions which are detected asynchronously in the I unit. These are interruptions such as I/O interruptions, timer advance requests, external interruptions, etc. These interruptions, which are buffered in the I unit, result in E IRPT FM I.

During the last cycle of instruction execution, detection of an E time interruption starts an E time interruption sequence by turning on EXIT with an A clock. The interruption code is set from the interruption buffers during the interruption sequencing. It is possible that the I to E transfer of the next instruction is occurring at the same time as the turn on of EXIT. If this is so, the execution unit is blocked from starting by the E time interruption lines.

It is clearly possible for an E time interruption to occur at the same time as an I time interruption for the next instruction. Since the E time interruption is associated with the earlier instruction, it takes priority over the I time interruption. Thus, even though the interruption code has already been set into the PSW for the I time interruption, the E time interruption is processed and the interruption code is altered accordingly.

Both EXIT and I IRPT END generate a control called IRPT RST (reset). This control resets any sequence controls in the I unit which might still be on and thus effectively terminates all normal instruction processing.

10.1.4.3 Starting of Execution Units

Execution units are started at I to E transfer time. The branch unit is started by I to E XFER with NO IRPTS and BROP. BROP is turned on at TON T2 for all branch instructions (provided R2 0 in an RR branch) and, therefore, may be used to condition the branch unit. The IE unit is started by I GO, which equals I to E XFER with NO INRPTS, BD I EXEC and NOT BROP. BROP must be excluded because the instruction BCR is included in BD I EXEC. For BCR, the IE unit is started if R2=0 in which case the IE unit does a NO OP. BROP is turned on for this instruction only if R2=0 and hence the exclusion in I GO.

The E unit is started by E GO, which is complicated by the fact that certain lines from the E unit may be late in arriving at the I unit (due to inherent circuit transmission delay) and which is present only with the concurrence of all of the following:

T2

not opf or ACCEPT

Not ie busy or BRLC or IEL

Not i irpt fm i

not e irpt fm i

bd e exec.

the combination of ELC or NOT E BUSY with NOT E IRPT FROM E is effectively generated in the E unit, and is combined with E GO to obtain a signal to start the E unit, which is closely analogous to the expression for I GO. It is necessary to do part of the logical combining in the E unit because the line E IRPT FM E is too late to send to the I unit and then back to the E unit. ELC or NOT E BUSY is also AND'ed with E GO in the E unit, as protection against a late ELC signal.

10.1.4.4 I Unit Store Operations

Stores which are made at the I to E transfer by the I unit are described in this section. Most features of this type of store are similar to the features of any CPU store. Thus an understanding of all stores may be obtained through this section. A normal I unit store request is shown in FIG. 255.

For instructions such as ST, STE and STD, store requests are made at the I to E transfer if no interrupts are outstanding. BD STR REQ with NC IRPTS and I TO E XFER set the CPU REQ and the CPU STR triggers in the BCU and the STR REQ trigger in the I unit. For all stores of this type the effective address is set into SAR and the H REG at TON T2. BLK T2M is turned on by the I to E transfer, thus preventing TON T2 of the next instruction from altering SAR until an ACCEPT is received. For these instructions, the E unit generates TOF BLK T2M ON ACC which is combined with ACCEPT to turn off BLK T2M and to allow setting of SAR by TON T2 of the next instruction. CPU REQ starts a storage unit and generates accepts, just as for a fetch. The STR REQ is maintained on until it is turned off by ACCEPT. The CPU STR trigger indicates to the BCU that a store rather than a fetch is being requested; CPU STR remains on until SAR is again set.

There are eight mark bits in BCU which must be set to indicate which bytes in external storage are to be altered (that is, where new data is stored rather than existing data regenerated). These bits are set at the I to E transfer of store operations of the type being discussed. The mark bits are set on the basis of the output of the BOP decoder and and bits 21 and 22 of the H register. The output of the BOP decoder indicates the length of the field being stored and bits 21 and 22 indicate where the field being altered starts in a storage word. The mark bit corresponding to any byte in the storage word which is to be altered is set to a ONE at this time. NOTE: It is possible to set the mark bits individually on various cycles. This facility is used extensively in the SS instructions for setting up fields to be stored on successive cycles of VFL operations.

The E unit is started at the I to E transfer of the instructions being discussed (ST, STE and STD). The E unit places the operand to be stored into the K register at the end of the first E unit cycle. The K register is gated into the SBI latch on the EBR clock immediately following the AR clock which is straddled by P-ACC. ELC is set by an A clock with ACCEPT, for this class of instructions.

If the address for the store is for a nonexistent storage (e.g., an optional unit not in a particular embodiment), CPU INV STR is set with an LBR clock just before the AR clock which is straddled by P-ACC. The invalid address interruption is then taken as an E time interruption at the end of ELC.

For all stores by CPU (except stores by the interruption mechanism), the storage keys (bits 8-11 of the PSW) are transferred to the storage protection apparatus in the Storage units. If the transferred keys do not match the keys of the addressed portion of storage, a storage address protection (SAP) signal is sent back to CPU. This signal is sampled into the SAP latch at approximately one cycle following the AR clock which is straddled by the accept. This causes an interruption which is treated as an E time interruption. However, the interruption may return too late for processing immediately after the instruction causing it. Therefore, the interruption will not be processed until after the next following instruction is completed.

The trigger STR REQ gates the ICR into the incrementer and adds one into position 20 of the incrementer. Comparisons are made between the H REG and the ICR, and between the H REG and the output of the incrementer to generated the PGM STR COMP. This signal together with STR REQ turns on the PSC trigger in the interrupt mechanism. The PSC line indicates that a store is being made into an address which may have already been prefetched into the A or B register for instruction processing. The PSC trigger will cause an E time interruption to be taken which initiates an IC recovery only. This results in data for the AB register being refetched (from the same address) after the store is completed.

If the CPU is being single cycled, the store request must be delayed for one cycle to allow the E unit time to set the K register. The one cycle delay is generated by a pair of single-cycle store triggers in the BCU. These triggers are turned on in place of CPU REQ when the store request if first made. On the next A CLK the single-cycle store triggers turn on CPU REQUEST, and the store proceeds at high speed. The timing for a single-cycled store is shown in FIG. 256.

10.1.4.5 Additional FUNCTIONS OF the I to E Transfer

1. Updating the PSW: Bits 32 and 33 of the PSW, the instruction length code (ILC), are set to the length of the instruction as determined by BOP 0 and 1 at the I to E transfer. The number of halfwords contained by the instruction in the I unit determines its length. Updating the ILC does not occur if an E time interruption of the previous instruction is detected.

2. Updating the ICR is considered in two parts, high order and low order. With the I to E transfer, the contents of the gate select register is set into the ICR low-order (ICLO). If the IC HO needs advancing, which occurs only when the A REG will be filled next, then IC HO ADV is turned on by the I to E transfer. Neither action takes place if an E time interruption is outstanding.

3. Ending T2: the I to E transfer turns T2 off.

4. Turn on Block Triggers: When BOP decoding indicates that the blocking of the next T1 cycle or the next T2 cycle is required, BLOCK T1 M and/or BLOCK T2 M will be turned on by the I to E transfer.

5. Setting of Busy Triggers: The I to E transfer, in generating the start condition for the execution units, also sets their respective busy triggers (IE BUSY and E BUSY).

6. SS Instructions: The SSOP status trigger (set by TON T2) and the I to E transfer, condition the VFL ADR trigger if there is no interrupt. See the discussion of SS instructions.

7. Decondition FR2: The I to E transfer prevents any further setting of FR2.

8. Set SAR, H REG: SAR is set from the incrementer at I to E transfer time for branches and LM; the H REG is also updated for LM and the incrementer error is sampled at this time.

9. ER 1: The content of the BOP R1 field is set into the ER 1 Register with the I to E transfer. ER 1 is used by the E unit for "put-aways" to internal registers (GRs and FPRs).

10. BR + 1 Request: the BR + 1 fetch for branches is generally made at I to E transfer time, if there is no interrupt, to fetch a second storage word of instructions in the sequence of instructions to which a branch has been effected.

11. T1 and IOP: As described above the I to E transfer is used in the logic for setting T1 and IOP.

12. GROUT: GROUT is turned on for certain instructions as is described in section 10.1.5.2.

13. BOP ERROR: A parity check is performed on the first byte of BOP at the I to E transfer. BOP ERROR is turned on at this time if there is a parity error.

10.1.4.6 E Unit Decoders

The E unit contains two operand registers, the execution op register (EOP) and the last cycle op register (LCOP). Both EOP and LCOP are 8-bit registers which are loaded with the first 8 bits (the operational, or op, portion) of an instruction. EOP is set from IOP, and LCOP is set from EOP. Through the use of two operand registers, the E unit is able to overlap the last cycle of one instruction with the decode cycle for the next following instruction. The setting of these registers is shown in FIG. 251.

EOP is set by TON ELC, or by T1 together with either NOT E BUSY or with ELC. This logic insures that EOP is set one cycle before the start of execution of an E unit instruction. If the E unit is not operating, or if ELC is on during the "last" T1 cycle, then EOP is correctly set at TON T2. Therefore, EOP is set at least a cycle before the I to E transfer. However, if the E unit does not finish the previous instruction until after T1 of the next instruction, then TON ELC insures that EOP is set at least one cycle before the I to E transfer. Notice that EOP is not available to the E unit during the last cycle of an instruction, therefore, decoding is taken from the LCOP during this time.

LCOP is set by T2 together with NOT E BUSY or ELC. This logic has the effect of setting LCOP at the I to E transfer, perhaps along with many unnecessary earlier settings, in the case of branch or IE operations, when the E unit is not busy.

10.1.5 INSTRUCTION EXECUTIONS

10.1.5.1 General

I E unit, branch unit, and E unit executions are described in respective sections. SS instructions have a large impact on IC controls and are discussed extensively in the Instruction Sequencing sections. There are a few instructions which have unique features relevant to the present discussion, and these are described in subsequent sections.

10.1.5.2 Grout Class Instructions

There are a number of instructions which require that general register operands be gated out during E time. This gating is accomplished by GROUT, a trigger which gates out operands from the general registers, as does T1, which is blocked by GROUT turning on BLOCK T1 M (except in an Execute instruction).

Those instructions which use GROUT are SPM, SSK, MR, DR, XEQ, D, BXH, BXLE, and STM. For the instructions SPM, SSK, and STM, GROUT gates the GR specified by BR1 out on GBL. T1 and GROUT are on simultaneously for XEQ, but GROUT overrides T1 to the extent of preventing the GR specified by the IOP B field from being gated onto GBL.

For the instructions D and DR, the R1 field must be EVEN or an invalid specification interruption is taken. If R1 is not ODD, then GROUT gates general register BR 1 onto GBL and general register BR 1 + 1 onto GBR. For the instruction MR, GROUT gates general register IR2 onto GBR.

For the instructions BXH and BXLE, GROUT gates general register IR3 (an implicitly addressed register) onto GBR also. However, in this case GROUT forces a one into the low-order position of the decoder so that the odd register of an even odd pair, or the R2 register itself, is always obtained by R3 or 1 .

For all of these instructions (except XEQ), the execution unit sends a signal to turn off GROUT. For the XEQ instruction, GROUT is turned off by the I unit controls after bits 24-31 of the general register addressed by BR 1 (based on the XEQ instruction) have been OR'ed into bits 8-15 of IOP (which contains the R1 field of the subject instruction).

It should be noted that operands gated to a specified half of RBL are generally also gated out to the unspecified half of RBL by GROUT, but these operands are ignored by the execution unit.

10.1.5.3 Supervisor Call Instruction

The SVC instruction is unique in that it is treated as a T2 interrupt and no normal E time is taken. The processing of this instruction is discussed hereinbefore.

10.1.5.4 Shift Instructions

The shift amount for shift instructions is obtained from bits 18-23 of the effective address which is placed in the H REG at TON T2; THE H register is available to the E unit for this function in "H REG LCH-E" latches.

10.1.5.5 WD, RD And The Immediate Instructions

For these instructions, IOP bits 8-15 are transferred to the Y and Z registers in VFL. The Y and Z registers are set by VFL controls at B time in response to essentially the same logic that sets EOP. Thus, the I to E transfer may still be allowed to change IOP.

10.1.6 IE UNIT SEQUENCE CONTROL CIRCUITS

The I unit sequence control circuits are the circuits which implement instruction sequencing as described in section 5.4.0.0 hereinbefore. These circuits include primarily the two I unit sequencer controls: T1 and T2, and the turn on and turnoff controls therefor; additional miscellaneous controls are also provided. These are discussed in detail in turn in successive sections hereunder.

10.1.6.1 FPR Switching: Set FR2 FIG. 193

When control of the floating point register gates is to be switched from the R1 field of the BOP register into the R2 field of the 10P register, then a signal is generated on a SET FR 2 line by an OR-circuit 1 in FIG. 193. The OR-circuit 1 is operated by either one of two AND-circuits 2, 3, each of which is operative only during RR instructions (ID RR, BD RR). The AND-circuit 2 is operative at turn on T2 due to a signal on the TON T2 line, and the AND-circuit 3 is operative during that portion of T2 (due to the signal on the T2 LCH line) which precedes the I to E transfer as indicated by the signal on the NOT I TO E XFER line.

10.1.6.2 SS OP Latch FIG. 188

In FIG. 188, a signal indicating that an SS operation is to be performed is generated on a SS OP line by a latch 1 which is set by an OR-circuit 2 in response to a signal on the SCAN IN SS OP line or in response to an AND-circuit 3. The AND-circuit 3 is operated at A time of a cycle during the turn on of T2 due to the A control clock signal on the AC line and the signal on the TON T2 line provided that the IOP decode circuit indicates an SS operation by means of a signal on the ID SS line. The latch 1 is reset by an OR-circuit 4 in response to a signal on the CPU RST line, or in response to an AND-circuit 5 which is operated by a signal on the AC line concurrently with an output from an OR-circuit 6. The OR-circuit 6 responds either to a signal on the IRPT RST line, or to a signal on a E UNIT THRU line. Thus, the latch 1 is reset anytime by the CPU reset, or at A time by an interrupt reset, or A time as a result of completion of the E unit execution. The output of the latch 1 on the SS OP line is used at not L time to set a related bipolar latch 7 so as to generate a signal on the SS OP LCH line.

10.1.6.3 VFL Address Latch FIG. 189

A VFL address signal is generated on a VFL ADR line in FIG. 189 by a latch 1 which is set by an OR-circuit 2 in response to a signal on the SCAN IN VFL ADR line or in response to an AND-circuit 3. The AND-circuit 3 is operative at A time of the I to E transfer in an SS op where no interrupt is outstanding due to its response to signals on the following lines: SS OP LCH, I TO E & NOT IRPT, and AC. The latch 1 is reset by an OR-circuit 4 in response to CPU RST, or in response to an AND-circuit 5 which is responsive at A time to an OR-circuit 6. The OR-circuit 6 responds to signals on the ACCEPT line or on the STR REQ LCH line. Thus, the latch 1 will be set during the I to E transfer of an SS op, and will be reset upon the receipt of an accept signal from the BCU or if a storage request is made. The output of the latch 1 on the VFL ADR line is also used to set a bipolar latch 7 which generates a signal on the VFL ADR LCH line.

10.1.6.4 Floating Point Register Gate FIG. 190.

In FIG. 190, a signal which will cause gating of the floating point registers to the register bus latch is generated on a GT FPR TO RBL line by an OR-circuit 1 in response to a signal on a DISPLAY FPR line, or in response to a signal on a FLOUT line which is generated by a latch 2 that is set by an OR-circuit 3 in response to a signal on a SCAN IN FLOUT line or in response to an AND-circuit 4. The AND-circuit 4 responds to an AND-circuit 5 at turn on of T2 of floating point operations due to the effect of signals on the TON T2 line and the IOP 2 line which indicate floating point instructions. The AND-circuit 4 is gated by a controlled A clock signal on the AC line. The latch 2 is reset by an AND-circuit 6 at A time provided there is an output from an OR-circuit 7 which responds to a signal on the IRPT RST line, or to the output of an AND-circuit 8 which is responsive to a signal on the E TOF FLOUT line concurrently with the output from the AND-circuit 5. Thus, the latch 2 can be set during turn on T2 of floating point operation, and will be reset during turn on T2 of floating point operation provided there is a turnoff of FLOUT from the E unit, or the latch may be reset by interrupt reset.

10.1.6.5 IOP Invalid Address Circuit FIG. 195

A signal indicating that an invalid instruction address is specified is generated on the IOP INV ADR line in FIG. 195 by an OR-circuit 1 in response to either one of two AND-circuits 2, 3 each of which is fed by an OR-circuit 4 in response to a signal on either the A INV ADR line or the B INV ADR line. The AND-circuit 3, however, also requires a signal from an inverter 5 which indicates that there is no signal from an OR-circuit 6. The OR-circuit 6 can be operated by signals on the GS PRE LCH 20 line and the A INV ADR line which are applied to an AND-circuit 7, or it may be operated by signals on the NOT GS PRE LCH 20 line and the B INV ADR line which are applied to an AND-circuit 8. Either of the AND-circuits 7, 8 senses that the invalid address designation was taken from the opposite register to the register which is currently being referenced by the gate select mechanism. However, in the event that the instruction in fact has been taken from both the A and the B register, and the invalid address is in the opposite register from the beginning register (for instance, the invalid address being in the B register although the A register contains the start of the instructions and the B register contains the final part of the instruction), an AND-circuit 9 may permit operation of the AND-circuit 2 even though the AND-circuit 3 is blocked by the inverter 5. The AND-circuit 9 responds to signals on a NOT ID RR line and the GS PRE LCH 21 line, as well as the output of an OR-circuit 10. The OR-circuit 10 responds to signals on the ID SS line and on the GS PRE LCH 22 line. The effect of the AND-circuit 9 is therefore to recognize a case where two registers A, B are involved in a current instruction. This can be accounted for by considering the fact that when the gate select bit 21 is a 1, fetching is taking place from bit 32 onward in either the A or the B register. Thus, if there is an SS instruction, or if there is a 1 in bit 22 of the GS (meaning that the fetch is between bit 48 of one register and bit 15 of the other register, then it can be seen that any such a fetch would result in taking instructions from two registers. The only exclusion is for RR instructions which, although the gate select mechanism will select bit 48 of one register through bit 15 of another register, the RR instruction will be complete between bit 48 and bit 63 of the address register, so therefore the NOT ID RR signal is used to block the AND-circuit 9.

In summation, A invalid address or B invalid address may cause the OR-circuit 1 to generate the IOP INV ADR signal provided that the AND-circuit 3 is not blocked by the inverter 5, or provided that the AND-circuit 2 is enabled by the AND-circuit 9. This accounts for the fact that an invalid address is not recognized for a fetch to one register when the instruction is being removed solely from the other register, but it will be recognized when the instruction may be partly in the register for which a fetch has manifested an invalid address.

10.1.6.6 T1 Sequence Controls

The instruction handling sequence, which fetches, analyzes, and in turn some times prefetches operands for the various instructions in sequence as the system proceeds through a program of instructions is initiated by a sequencer called T1. In fact, T1 defines the first machine cycle which relates to any particular instruction, and T1 may be repeated as necessary until it is possible to turn on the second instruction sequencer which is called T2. In the following sections, the turning on, turning off and otherwise handling of the controls with respect to the T1 cycle are described.

10.1.6.6.1 TURN OF OF T1 (TON T1) FIG. 198

In FIG. 198, a signal which will cause the T1 cycle to turn on is generated on a TON T1 line by an OR-circuit 1 in response to either one of two AND-circuits 2, 3 each of which requires an input from a further AND-circuit 4. The AND-circuit 4 responds to various conditions which are the complements, or opposites, of conditions under which T1 is not to be set. For instance, an OR-circuit 5 senses signals on the COND BLK T1 OFF line and on the NOT BLK T1M LCH line. Thus, if the blocked T1M latch is off, or if it is about to be turned off as a result of certain conditions, the OR-circuit 5 will be operated. The AND-circuit 4 also responds to signals on a NOT T1 LCH, NOT IRBT RST, and NOT HALT LCH lines. Thus, T1 cannot be established by means of the OR-circuit 4 when it is already on, when there is an interrupt reset, or when the machine is in a halt state. The AND-circuit 2 will be operated whenever there is an output from the AND-circuit 4 provided that the T2 latch has not been set as indicated by a signal on the NOT T2 LCH line. The AND-circuit 3, on the other hand, may be operated even though the T2 latch is set provided there are signals on the LCM and NOT BD BLK T1 lines together with the output of an OR-circuit 6. The OR-circuit 6 indicates that no storage fetch is involved either because of the fact that no operand fetch has been requested, or because even though it may have been requested, the bus control unit has accepted the request and therefore is ready to accept additional requests. The OR-circuit 6 senses these conditions via signals on the NOT OPF LCH and ACCEPT lines.

10.1.6.6.2 CONDITION BLOCK T1 OFF FIG. 202

In FIG. 202, a signal is generated on the COND BLK T1 OFF line by an OR-circuit 1 in response to VFL ending, or the turning off of block T1M by either the E unit or the IE unit. The OR-circuit 1 responds to signals on the VFL ENDING, IE TOF BLK T1M, and E TOF BLK T1M lines.

10,1.6.6.3 VFL ENDING FIG. 200

A signal is generated on the VFL ENDING line by an AND-circuit 2 in FIG. 200 provided there is present signals indicating that the VFL address latch has stayed on even though the SS op latch has been turned off as manifested by signals on the VFL ADR LCH and NOT SS OP LCH lines.

10.1.6.6.4 HALT LATCH FIG. 201

In FIG. 201, a signal is generated on the HALT LCH line by a latch 1 which is set by an AND-circuit 2. The latch 1 is reset at the start of each NOT L line due to the effect of a controlled L clock signal on the NOT LC line. Thereafter, if there is a signal on the MC HALT line, the latch will again immediately be set; however in the event that there is no signal on the MC HALT line, the latch will remain reset. When reset, the latch 1 of FIG. 201 generates a signal on the NOT HALT LCH line.

10.1.6.6.5 BLOCKING OF T1 (BLK T1 M) FIG. 203

In FIG. 203, a signal is generated on the BLK T1M LCH line by a bipolar latch 1 which is set by a latch 2 at the start of not L time in response to a signal from the controlled L clock on the NOT LC line. The latch 2 is set by an OR-circuit 3 in response to a scanning signal on the SCAN IN BLK T1 line, or in response to an AND-circuit 4. The AND-circuit 4 is gated by a controlled A clock signal on the AC line concurrently with the output of an OR-circuit 5. The OR-circuit 5 in turn may respond to either a signal on a IRPT SET BLK IC & T1 line.

It should be noted that the effect of the BLOCK T1M LCH line as manifested in the circuit of FIG. 198 which is described in section 10.1.1.1, is the complement of that signal (NOT BLK T1M LCH) must be applied to the OR-circuit 5 in FIG. 198 in order to obtain a signal on the TON T1 line, or, the impending resetting of the blocked T1M LATCH must be sensed by the presence of the COND BLK T1 OFF line by the OR-circuit 4 in FIG. 198 just as that signal is being applied to the OR-circuit 13 in FIG. 203.

10.1.6.6.6. T1 CYCLE (T1 LCH) FIG. 204

The control signals which actually delineate the first instruction sequence cycle, the T1 cycle, are generated in FIG. 204 by a latch 1 which provides a signal on the T1 line and by a bipolar latch 2 which is responsive to the T1 signal so as to generate a signal on the T1 LCH line. A bipolar latch 2 is caused to reflect the setting of the latch 1 at the beginning of L time under the control of the complement of a controlled L clock signal which is presented on the NOT LC line. The latch 1 is set by an OR-circuit 2 in response to a signal on the SCAN T1 line, or in response to an AND-circuit 3 which is operated at A time (AC line) concurrently with a signal on the TON T1 line. The latch 1 is reset by an OR-circuit 4 in response to a signal on the CPU RST line, or in response to an AND-circuit 5 which is operative at A time (due to the AC line) when there is an output from an OR-circuit 6. This OR circuit recognizes the turning on of T1 or interrupt reset conditions by signals on the TON T2 line and IRTT RST line.

Thus it can be seen, that the actual controls for the turning on and turning off of T1 are mainly manifested in the controls for a TON T1 which includes the lack of a blocking of T1, and the controls for turning on T2 or for interrupt reset.

10.1.6.7 T2 Instruction Cycle Controls

A second delineated cycle of the instruction handling sequence is identified as T2. This signal can appear only after a "good" T1 cycle, which means that the instruction has been decoded and operand fetching for the instruction may commence. The controls for the T2 cycle are described in the following sections.

10.1.6.7.1 TURNING ON OF THE T2 CYCLE (TON T2) FIG. 205

The signal which causes the T2 cycle to turn on is generated on the TON T2 line by an AND-circuit 1 in response to concurrent presence of outputs from any one of four OR-circuits 2-5 together with signals on the T1 LCH, NOT IRPT RST, and IOP LOADED lines. The OR-circuit 2 senses the fact that there is no compare problem, that is that there will not be any data stored into the storage word which may be fetched for the next instruction operand due to the fact that either the E unit is not busy, and therefore cannot possibly store anything, or that the compare block latch is off. These conditions are manifested by signals on the E NOT BUSY LCH and NOT COMP BLK LCH lines.

The OR-circuit 3 recognizes that either a branch operation is involved, or that the conditions in the instruction counter fetching mechanism are proper for the allowance of the T2 cycle as indicated by signals on the ID BR OP and NOT FTCH PRIORITY lines, respectively. The OR-circuit 4 recognizes either that the block T27 latch is not on, or that it will be turned off shortly due to the presence of a signal on the NOT BLK T2M LCH line or on the PRE TOF BLK T2M line, respectively. In addition, the AND-circuit 1 responds to an OR-circuit 5 that is responsive in turn to signals which indicate that neither an A nor B instruction fetch is outstanding, or that storage is not being shared. This is because of the fact that the storage indicated by the presence of a signal on the NOT IC AFE OR IC BFE LCHS lines and on the NOT SHD STG BLK line. Of course, as a shared storage feature is not included in this embodiment, there will always be a signal present on the NOT SHD STG BLK line so that the OR-circuit 5 will always condition the latch 1 provided the other inputs thereto are present.

In summation, a signal permitting the turn on of T2 on the TON T2 line can only occur when all the following conditions have been met: IOP must be loaded (meaning that the complete instruction is available in the AB register), there must be no interrupt reset, and the T1 latch must be on; there must be no blocking due to the fact of storing into a register from which an operand must be fetched, there must either be a branch instruction indicated by the IOP decode or all conditions for turning on T2 as a function of the instruction counter mechanism must be present, there must be no blocking of required IC fetches to the A or B register due to storage sharing (when that feature is employed) and the blocked T2 latch must either be off or must be in the process of being turned off.

10.1.6.7.2 IC FETCH PRIORITY SENSING FIG. 207

A signal which indicates that IC fetches do not have priority over operand fetches, and which therefore indicates that the T2 cycle is not to be blocked in order to permit further IC fetches, is generated on the NOT FTCH PRIORITY line by an OR-circuit 1 in FIG. 207. THe OR-circuit 1 can respond to a signal on the ID RR line or to any one three AND-circuits 2-4. The theory behind circuit of FIG. 207 is discussed in section 11.5.4 which describes the IC fetch priority rule. The logic shown in that section for the blocking of TON T2 is in a sense the converse of the logic shown in FIG. 207 which implements the turning on of T2, or the unblocking thereof, when there is no IC fetch priority, by generating the signal on the NOT IC FTCH PRIORITY line. However, the lack of a block on the turning on of T2 because there is not need for IC fetch priority is not complete in FIG. 207, but becomes complete only when combined with ID BR OP at the OR-circuit 3 in FIG. 205. Stated alternatively, it can be considered that the OR-circuit 1 in FIG. 207 also responds to a signal on the ID BR OP line and T2 can be turned on (insofar as IC fetch priority is concerned) if there is a branch op, or an RR instruction, or the output of any one of the three AND-circuits 2-4 in FIG. 207.

The philosophy of the not IC fetch priority includes the fact that if the branch op is involved, then there is no point in fetching the next sequential instruction from the current instruction stream, since a successful branch operation will cause the machine to pick up a different sequence of instructions. If an RR instruction is involved, the operands and the putaways are involved only with the general purpose registers, storage in the storage addressing circuits not being involved, so that there cannot possibly be any conflict between instruction counter fetches from storage in the RR instruction handling of operands at the general registers.

The AND-circuit 2 in FIG. 207 operates when the current instruction is being taken from either the A or the B register starting at bit 0 of that register because both bits 21 and 22 (the lowest order bits) are 0; this is illustrated a little more clearly with a reference to FIG. 73, wherein it can be seen that whenever both bit 21 and bit 22 of the GRS are 0, the gate select mechanism will select bit 0-31 of either the A or the B register in dependence only upon the condition of bit 20 of the GSR. Since the current instruction is from the uppermost part of either the A or the B register, it is impossible to exhaust the AB register merely from the one instruction, and therefore IC fetch priority should not be granted in preference to the turning on of T2.

The AND-circuits 3 and 4 represent two different conditions; the AND-circuit 3 is operative in a case where an accept signal is present indicating that perhaps an IC fetch has just been accepted, whereas the AND-circuit 4 is operative in conditions where the IC AFM or IC BFM latches have been energized indicating that an IC fetch has already been accepted.

The AND-circuit 3 will operate when there is an accept signal and when there is either a signal on the IC AFE LCH line or on the IC BFE LCH line, together with belated other conditions which are described in the following sentences. Consider first where the case of an IC AFE LCH signal into an OR-circuit 5. This signal is also applied to an OR-circuit 6 so that all that remains to be operated is an OR-circuit 7 in order to have the AND-circuit 3 operate. Since it is impossible to have an IC AFE concurrently with a IC BFE, the OR-circuit 7 can operate only if there is a signal on the G 20 LCH, B LOADED LCH, or IC BFM LCH line. The logic for operating the AND-circuit 3 in this case therefore is as follows:

accept IC AFE LCH (GS 20 LCH or B LOADED LCH or IC BFM LCH) .

The meaning of these terms is as follows: if there is an accept signal concurrently with a IC AFE, this means that a fetch request for the A register is just now being accepted, and therefore that a fetch to A should not hold up the turning on of T2; a fetch to B shall now hold up T2 due to the fact that either B is loaded, or a fetch to B has already been accepted as indicated by the IC BFM, or current instructions are being removed from the B register as indicated by the GS 20 LCH, so that the B register cannot be fetched at the present time. Thus, neither the A nor the B register can possibly require a fetch which should hold up T2. Similar reasoning obtains with respect to the current acceptance of a B fetch as indicated by the concurrent presence of the ACCEPT and IC BFE LCH, together with one of the inputs to the OR-circuit 6 such as NOT GS 20 LCH, A LOADED LCH, or IC AFM LCH.

Stated alternatively, with ACCEPT and IC AFE, no A fetch is required, and with either GS 20, or IC BFM, no B fetch is required; this then corresponds with the logical expressions set forth in section 11.5.5.

The AND-circuit 4 responds to any one of three OR-circuits 8-10. Consider the situation when there is a signal on the IC AFM LCH line which will cause the OR-circuit 8 to operate, and also cause the OR-circuit 9 to operate. Then any one of the signals to the OR-circuit 10 will cause the AND-circuit 4 to operate. For instance, the OR-circuit 10 can respond to any one of the following: B LOADED LCH, IC BFM LCH, or GS 20 LCH. The operation of the OR-circuit 10 is very similar to the operation of the OR-circuit 7; the difference between the two is that the fetch to A has now been recognized totally by turning on IC AFM, whereas with respect to the OR-circuit 7, the fetch to A is recognized as accepted by the combination of ACCEPT and IC AFE. A similar result obtains whenever there is a signal on the A LOADED LCH line. On the other hand, if either B LOADED or IC BFM is present at the input to the OR-circuit 8, then the same signal will cause the operation of the OR-circuit 10, so that any one of the three inputs to the OR-circuit 9 will cause the AND-circuit 4 to operate in a similar fashion. In other words, one could say that the AND-circuit 3 represents the case where an A or B fetch has just been accepted as indicated by a signal on the ACCEPT line, the OR-circuits 9 and 10 are operative either when the fetch is outstanding as indicated by IC AFM or IC BFM, or when the corresponding register is fully loaded as indicated by A LOADED or B LOADED. Thus, one might consider there to be a progression in control from initially accepting a fetch, to the fetch being outstanding, or to the fetch being completed in that the related register is fully loaded.

10.1.6.7.3 T2 LATCH FIG. 206

In FIG. 206, the signal indicating the T2 sequence is generated on the T2 line by a latch 1 which is set by an OR-circuit 2 in response to a scanning signal on the SCAN T2 line or in response to an AND-circuit 3 which is operative at A time whenever there is a signal on the TON T2 line. The latch 1 is reset by an OR-circuit 4 in response to a signal on the CPU RST line or in response to the output of an AND-circuit 5 which is operative at A time to respond to an OR-circuit 6. The OR-circuit 6 will operate the AND-circuit 5 in response to a signal on the IRPT RST line, or in response to a signal on the I TO E XFER line. Thus, the latch is set in accordance with the conditions for the signal TON T2 or during scanning operations, and is reset at I to E transfer or in response to interrupt resetting control.

10.1.6.7.4 BLK T2 M FIG. 197

In order for a turn on of T2, there must be no output signal from the BLK T2M LCH, which output is manifested on a line energized by a bipolar latch 1 in FIG. 197, said bipolar latch being utilized to reflect the setting of a latch 2 which in turn is set by an OR-circuit 3. The OR-circuit 3 is operative during scan in operations in response to a signal on the SCAN IN BLK T2M line, or in response to an AND-circuit 4 which responds at A time to another AND-circuit 5. The AND-circuit 5 operates at I to E transfer due to a signal on the I to E XFER line provided there is no interrupt reset as indicated by a signal on the NOT IRPT RST line concurrently with the output of an OR-circuit 6. The OR-circuit 6 recognizes either branch operations, or BOP decode blocking of T2 by signals on the BR OP and BD BLK T2 lines. The output of the AND-circuit 5 is also applied to an inverter 7 so as to cause an AND-circuit 8 to operate an OR-circuit 9, thereby to reset the latch 2. The AND-circuit 8 is responsive at A time due to a controlled A clock signal on the AC line, when there is also a signal present on the PRE TOF BLK T2M line. The generation of this preblocking line is described in the next section. The OR-circuit 9 is also responsive to an AND-circuit 10 which will cause a resetting of the latch 2 if there is an interrupt reset signal, and to an AND-circuit 11 which is responsive to the execute sequence cycle when IOP is loaded as indicated by a signal on the IOP LD & XEQ SEQ LCH LINE. The OR-circuit 9 may also respond directly to a signal on the CPU RST line. Thus, the BLK T2M LCH signal can be established as a result of I to E transfer without an interrupt reset during either a branch op or when the BOP decode circuits indicate instruction conditions such that T2 should be blocked. This blocking is reset in the absence of an output from the AND-circuit 5 in response to a preturnoff of the blocking of T2, or by interrupt reset, or by the execute sequence cycle when IOP is loaded. As in the case of most of these controls, BLK T2M LCH can be turned on by the scan circuits and reset by CPU RST.

10.1.6.7.5 PRETURNOFF OF BLOCK T2 FIG. 208

The signal on the PRE TOF BLK T2M line is generated in FIG. 208 by an OR-circuit 20 in response to an AND-circuit 13, an AND-circuit 21, or an OR-circuit 22. The AND-circuit 13 is one of the conditions which may cause the resetting of the BLK LCM LCH as described hereinbefore. The AND-circuit 13 indicates that an accept signal has been received and either a VFL operation is ending, or that the E or IE units have sent a signal for turning off of the T2M block whenever accept is received. The OR-circuit 22 responds to E unit turn off of block T2, to branch success concurrently with branch 1st cycle, or to the concurrence of VFL ending with no storage request, all as controlled by signals on the E TOF BLK T2M, BR LC LCH & BR SUCC M LCH, VFL ENDING, and not STG REG LCH lines.

The AND-circuit 21 operates in response to tests complete and an unsuccessful branch as indicated by signals on the TSTS CMPLT LCH and NOT BR SUCC LCH lines. The AND-circuit 21 also requires that no blocking of this control be outstanding as a result of shared storage operations, in the event that such operations are provided for in any particular embodiment; in the case of the present embodiment, this line is illustrative merely, the details of storage sharing not being included herein.

10.1.6.8 I Unit Last Cycle Controls FIG. 209

In FIG. 209, an OR-circuit 1 senses the last cycle in either the I execution unit or in the branch unit in response to signals on the IEL LCH or BR LC LCH line. The output of the OR-circuit 1 is fed to another OR-circuit 2 which generates a signal on the I DONE line. This signal indicates that the IE unit and the branch unit are both either not operating, or are in the last cycle of operations. The OR-circuit 2 is responsive to a signal on the IE NOT BUSY LATCH line, so that the I DONE signal indicates either that there is no branch or IE operation, or one of these operations is in its last cycle, due to the fact that the IE busy latch is used both for the IE unit and for the branch unit. The output of the OR-circuit 1 is also applied to an AND-circuit 3 which is operative in response to the presence of a signal on the NOT E BUSY LCH line to cause an OR-circuit 4 to generate a signal on the CTRL LAST CYC line. Another input to the OR-circuit 4 is an AND-circuit 5 which is responsive to the OR-circuit 2 and to a signal on the ELC LCH line. Thus, the AND-circuit 5 responds to the IE NOT BUSY LCH signal concurrently with ELC LCH signal, and the AND-circuit 3 operates in response to either the IEL LCH or BR LC LCH signals concurrently with the NOT E BUSY LCH signal. The OR-circuit 4 is thus operated when the I unit is finishing and the E unit is not busy, or the E unit is finishing and the I unit is not busy, or the E unit is finishing and the I unit is not busy so as to generate CTRL LAST CYC. The output of the OR-circuit 4 is also applied to an OR-circuit 6 which generates a signal on the LCM line, the OR-circuit 6 also being responsive to an AND-circuit 7. The AND-circuit 7 recognizes that both the E and the I unit are not busy in execution functions due to signals on the IE NOT BUSY LCH and NOT E BUSY LCH lines. Thus, the signal on the LCM line indicates that either one unit is finishing and the other unit is not busy, or that both units are not busy.

10.1.6.9 GO/I GO Circuits FIG. 210

In FIG. 210, a signal is generated on the E GO line y by an AND-circuit 1 in response to concurrent presence of a need for E execution as indicated by the BOP decode circuit, the presence of T2, the fact that the I unit is not busy or is finishing, there is no interrupt from the I unit, and that no operand fetch is required and cannot be achieved. The AND-circuit 1 responds to signals on the following lines: BD E EXEC, T2 LCH, I DONE, NOT IRPT FM I, T2; the AND-circuit 1 also responds to the output of an OR-circuit 2 which indicates that either no operand fetch is required, or that the fetch request has been accepted due to signals on the ACCEPT and NOT OPF lines.

Another AND-circuit 3 responds to the OR-circuit 2 and to the T2 signal, but is also responsive to the signal on the LCM line to generate a signal on the I TO E XFER line. In other words, when T2 and LCM coincide with no operand fetching problem, then I to E transfer will be developed, as described in section 10.1.4.1 The output of the AND-circuit 3 is also applied to two AND-circuits 4, 5 which are both also responsive to a signal on the NOT E IRPT line. The AND-circuit 4 generates a signal on the I TO E & NOT IRPT line. The output of the AND-circuit 5 is applied to an AND-circuit 6 which generates a signal on the I GO line in response to presence of signals on the I TO E & NOT IR PT, NOT BR OP LCH, and BD I EXEC lines. Thus, the signal on the I GO line indicates that I execution can begin since there is no branch op, no interrupt, and the I to E transfer has occurred.

Comparing E GO with I TO E XFER, it is noticed that E GO responds to I DONE, whereas I TO E XFER responds to LCM. Thus, if the IE unit is initially busy, I DONE will appear with IEL, but LCM cannot appear until there is a signal on the IE NOT BUSY LCH line. Thus, the I to E transfer will occur a little later than E GO.

11.0 INSTRUCTION COUNTER CONTROLS FIG. 72 THROUGH FIG. 75

The incrementer and gate select circuits control the normal advancing of the instruction counter and the normal fetching of instructions.

Instructions fetched from storage are buffered in either the A or the B register before being set into the IOP register for initial execution. (see FIG. 72 through FIG. 75) The instruction counter register (ICR) contains 24 bits (numbered 0 through 23) and is advanced by means of two adders: the gate select adder for advancing the low-order portion!C LO (bits 20-22) and the incrementer for advancing the instruction high-order order portion ICHO (the remaining bits). The gate select adder works in conjunction with the gate select register (GSR) to select gates from the A and B registers to the IOP register.

11.1 INTRODUCTION

All instructions are executed in two parts an I time and an E time. I time of one instruction may be overlapped with controls, while advancing the setting of the gate select register GSR, also maintain the ICR with a proper address for interrupt purposes.

The IC controls also generate the instruction fetch addresses and make normal IC fetches. The addresses are generated by adding, in the incrementer, an appropriate, small increment amount to the ICR. The IC controls attempt to make an IC fetch as soon as an empty instruction bugger (A or B REG) condition is detected, but any instruction in the process of execution may block out IC fetches if an IC fetch would cause interference with the instruction execution. If the IC fetches are continuously blocked by instruction executions, the I unit ultimately will exhaust all instructions in the buffers. At this time, the IC block will drop, allowing IC fetches to be made and instruction execution to resume. Normally the instruction buffers will not be exhausted before IC fetches are made. However, special logic has been incorporated to insure that, except in unique situations, both buffers are not emptied. In other words, fetches relating to executions take priority over instructions fetches until the A and B registers no longer have a full instruction left; then, one instruction fetch is allowed notwithstanding the need for operands.

First there is a physical description of the IC data flow. IC addressing, advancing, fetching and recoveries are discussed, in that order.

11.2 PHYSICAL DESCRIPTION OF DATA FLOW

An illustration of the data flow for the I unit is shown in FIG. 72 through FIG. 75. That portion of the data flow relevant to the INCR and GS adder is shown in FIG. 72.

11.2.1 ICR AND INCREMENTER

The ICR is a 24-bit register used for addressing instructions in external storage during normal linear sequencing. Though the register is located in positions 40-63 of the PSW, it is called ICR 0-23 in this description. The ICR is gated into a 24-bit adder called the incrementer (INCR) The input on the other side of the incrementer is at positions 20 and 19 only. These two lines are generated by controls, and are called ADD ONE and ADD TWO, respectively. By various combinations, addresses at the incrementer input can be advanced zero, one, two or three 64--bit storage words. While the gate to SAR is a full 24 bits wide, the gate to ICR lacks positions 20-22 and therefore consists of only 21 bits. A full 24-bit path from the H register to the incrementer is also provided.

It should be noted that the incrementer is not a true general adder because certain special inputs will not give a correct sum. However, these special inputs can occur only if there is a machine malfunction. If there is a bit in incrementer data input position 20 at the same time as there are bits on both control inputs, an incorrect sum results. For this case the result in bit 19 is erroneous, and if x is zero, the carry which normally would go into position 18 is not generated. For any other inputs, the incrementer gives a correct sum. The parity prediction and checker for incrementer P16-23 (called P2) is designed for the incrementer as implemented--not a true adder. Thus if all three inputs did appear, the parity circuit would detect the malfunction. The details of the incrementer implementation are described hereinafter.

11.2.2 A, B AND J REGISTERS

The two instruction buffer registers A and B each hold one storage word of 64 bits. The A register is associated with double words in storage for which the address is even, that is, the address contains a 0 in bit position 20; the B register relates to storage words for which the address is ODD (contains a 1 in position 20). Except for this one consideration, registers A and B are completely similar in usage. Bit 63 of register A is considered as being adjacent to bit 0 of register B, and bit 63 of register B is considered as being adjacent to bit 0 of register A. There is also one 64-bit operand buffer, the J register. All these buffer registers are fed by the 64-bit SBO (storage bus out) which is fed from external storage. There is also the 64-bit bus from the J REG to the AB REG (which includes A and B). There is a 32-bit op (operational) register called IOP which can be loaded directly from any 30 two-bit field in AB starting at a halfword address (0,16,32,48). The field in AB that is selected for gating to IOP is determined by a full binary decode output of a 3-bit gate select register.

11.2.3 CHECKING

The A, B, J, IOP, SBO, H and ICR registers have one parity bit for each eight-bit byte. The incrementer has a checker which checks input parity and checks internal operation of the incrementer. The incrementer also generates normal parities for each of the three output bytes. These are generated by independent circuitry. A unique parity bit P1 is also generated within the incrementer. This is necessary because bits 21 and 22 of the INCR are not gated into the ICR with the rest of the INCR output. This parity is generated by considering incrementer inputs 16-19, control input 19, and the input parity. Assume that there are an even (odd) number of bits in incrementer input 16-19. If control input 19 is one, and if adding a one into position 19 of the incrementer input would result in a sum with an odd (even) number of bits in positions 16-19, then P1 is set equal to the input parity inverted. If the result has an even (odd) number of bits in positions 16-19, then P1 is set equal to the input parity. The parity bit P1 is gated into ICR P16-23 instead of the conventional parity bit for 16-23. However, the normal incrementer parity for 16-23 is gated to SAR P16-23. The following is an example of the operation of the incrementer:

Position 16 17 18 19 20 21 22 23 P P1 INCR Input 0 0 1 1 0 0 1 0 0 CTRL Input 1 1 INCR Output 0 1 0 0 1 0 1 0 0 1

Thus, P1 is correct when ignoring 21 and 22, and P is correct when 21 and 22 are included.

11.2.4 GATE SELECT MECHANISM

A three-bit path is provided from ICR 20-22 to the gate select adder prelatch A second three-bit input to the gate select adder prelatch comes from the gate select register. The output of this latch feeds into the gate select adder. The gate select adder is a three-position adder implemented in two levels. Control inputs are provided at positions 21-22 of the second side of the gate select adder. The output of the gate select adder can be gated into the three-position gate select register. This register also has a gated input from positions 20-22 of the H register, which is used during branches. There is also a carry position in the gate select register which is fed by the carry output of the gate select adder. The decoder of the gate select register selects 30 two bit fields in the A, B registers for gating to IOP as follows: (see FIG. 73)

ab register GSR Bits Selected 000 A 00-31 001 A 16-47 010 A 32-63 011 A 48-63, B 00-15 100 B 00-31 101 B 16-47 110 B 32-63 111 B 48-63, A 00-15

the gate select register is provided with a "Corrected Parity" position which is used in updating ICR P16-23 whenever ICR 20-22 is updated from the GSR. The corrected parity is generated from the gate select adder date inputs and a parity bit sent along with the data. Normally this parity comes from ICR P16-23, but if the ICR is being set from the incrementer at the same time as the GSR is being set from the ICR, the input parity is taken from P1 of the incrementer. This corrected parity reflects the new ICR P16-23 that results from the add in the gate select adder. But, if any single error occurs in the gate select adder or the parity generation circuitry, the corrected parity bit is incorrectly set. When the GSR is returned to the ICR, the last byte of the ICR will then contain incorrect parity. Whenever the ICR is gated into the incrementer, for an IC HO ADV or for an instruction fetch, the parity is checked. At this time the erroneous parity will lead to a data check.

11.2.5 ADDRESSING OF INSTRUCTIONS

At the start of each T1 cycle the instruction being executed by the I Unit is placed into the IOP register. The leftmost halfword or syllable; two eight-bit bytes of the instruction is placed in IOP 0-15, and the next halfword is placed into IOP 16-31. If the instruction is an RR instruction, (one syllable in length) then IOP 16-31 is not involved in the instruction execution, and will be followed in IOP. The basic unit of data in external storage is the 64-bit storage word, which contains eight bytes, four syllables, or two "full words." Addresses, which are 24 bits long, access storage to the byte level. Therefore bits 0-20 of any address specify a double word in storage and bits 21-23 specifies a byte within a double word. Instructions always start at syllable (or halfword) addresses and hence any address for an instruction should have a zero in position 23, thus indicating an even-number byte. In order to obtain an instruction at a given address it is necessary to first fetch the storage word addressed by bits 0-20. If bit 20 is 0, the double word is buffered in the A register. If bit 20 is 1, the double word is buffered in the B register. If the instruction is located in a position which overlaps a double word boundary, it is necessary to also fetch the next double word; this second double word would be buffered in the B register if the first double word was in the A register, and vice versa. The A and B registers are hereinafter referred to jointly as the AB register.

Before any instruction contained in the AB register can be properly set into IOP, it is first necessary to select one of the gates out of AB. This is accomplished by setting bits 20-22 of the instruction counter into the GSR. On the basis of the GSR, one of the eight gates from the AB register to IOP is selected. The specific decoding is described in section 11.2.4.

The first two bits of any instruction, which are placed in IOP 0, 1 (and BOP 0, 1), contain a code which identifies the number of halfwords or syllables in the instruction, which is determined by the format of the instruction. There is a length decoder connected to BOP 0, 1 which provides the actual length of the instruction. The output of the length decoder is fed to PSW 32, 33. The coding is as follows:

0 1 32,33 0 0 0 1 RR 0 1 1 0 RX 1 0 1 0 RS-SI 1 1 1 1 ss

11.4 INSTRUCTION COUNTER ADVANCING

An example of ICR advancing is shown in FIG. 265, and described with respect to FIG. 72, and to a lesser degree with respect to FIG. 73 through FIG. 75.

Except during special circumstances, ICR 20-22 is continuously gated into the gate select prelatch of the GSA illustration 4, FIG. 265 Normally, the input to the GSA is not latched, but acts as a flush path. Also, normally, the two-bit indication of the instruction length, which is obtained from the IOP decoder, is gated into the control inputs of the gate select adder (illustration 5, FIG. 265).

At the start of any instruction predecoding cycle (the first T1 cycle), bits 20-22 of the address of that instruction are contained in both ICR 20-22 (illustration 10) and the GSR (illustration 12). During the last T1 cycle for that instruction, the instruction being predecoded is located in IOP, and therefore bits 20-22 of the address of the next instruction can be made available at the output of the gate select adder. This output, along with the carry and corrected parity, are gated into corresponding GSR positions by TON T2 at A time (AC). During T2 the GSR output selects the proper gate from the AB registers for the next instruction FIG. 72) Thus the gates are selected in time for setting IOP with the next instruction in the AB register on the clock cycle following TON T2 (i.e., in the first T2 cycle).

When an instruction is transferred from the I unit to the E unit, (called the I to E transfer) ICLO is advanced by gating the GSR to ICR 20-22, the "corrected Parity" is also set back into ICR P16-23, and, the length of the instruction being transferred is gated from the BOP decoder to PSW 32, 33. If a carry is generated by the gate select adder (ICLO). The ICR will not be completely advanced until ICR positions 3-20 (ICHO) are advanced. Therefore, in order to advance the ICHO, the ICHO ADV trigger is turned on by I to E XFER concurring with GS CARRY. The ICHO ADV gates the complete ICR into the incrementer, increments position 19, (ADD T2), and gates the sum along with new parities back into the ICR 0-19. Thus, within at most one cycle of the I to E transfer, the whole ICR is updated. ICR bits 20-22 (ICLO) are not gated from the INCR result, so they remain as set the GSR.

As is described under IC fetching, the IC controls have the ability under certain circumstances to force the incrementer control input to generate IC fetch addresses, but the fetch controls are not necessarily blocked during an ICHO ADV. Therefore, the possibility exists that the IC fetch controls may activate the incrementer control input 20 (ADD 1), and may also, incidentally, increment position 19 at the same time as an ICHO ADV is activating incrementer control input 19. However, ICR 20 is always zero whenever an ICHO ADV is made, due to the fact that an ICHO ADV is made only when advancing from the B register to the A register, and bit 20 equals zero when the B register is in use. Therefore, there can be no carry into position 19 of the incrementer during an ICHO ADV. It follows that during an ICHO ADV, incrementer sum positions 0-19, 23 are the correct bits for updating the ICHO even if IC fetch addresses are being generated. Incrementer parity bit P1 16-23, which is generated by predicting the effect of incrementer control input 19 on the input parity, is the correct parity for the updated ICR, and therefore is gated back to ICR 16-23.

When updating the ICLO, the quantity to be updated should be taken from the fully advanced previous ICR value. However, it is possible for an ICHO ADV to coincide with a "good" or "last" T1 cycle. In this case, the ICHO is being advanced for one update at the same time as the updated IC LO is being set into the GSR for the next update. This generates no problems (because of the partial incrementer to ICR gate) except for the setting of the "corrected parity" into the GSR. Since the parity to be modified in the gate select adder has not yet been set into the ICR, the parity is taken directly from P1 16-23 of the incrementer output. Thus the "corrected parity" is set correctly at TON T2 for transfer to the ICR P16-23 on the next I to E transfer.

The advancing of the IC high order during the first cycle of E time creates problems with the execution of only two instructions. These are the load address instruction (LA) and the load PSW instruction (LPSW). In LA, the E unit makes use of the incrementer to transfer the effective address from the H register to the K register. The transfer is made on the second E time cycle, instead of the first, in order to avoid conflict with an ICHO ADV. In LPSW, there is a possibility that an ICHO ADV will gate the incrementer output into the ICR at the same time that the J register is being gated into the ICR by the instruction execution. To avoid this duplicate gating, the IE unit which controls the load PSW operation) blocks the INCR to ICR gate whenever the PSW is being loaded from the J register.

11.4.1 INTERRUPTION EFFECT ON IC ADVANCING

If an interruption occurs, the PSW which is stored must contain the address of the next instruction. There are two types of interruptions, E interruptions and I interruptions. E interruptions take place after the last cycle of instruction execution. This class includes the majority of interruption types. I interruptions take place at the I to E transfer in place of normal instruction execution. It is possible for an E interruption and an I interruption to occur simultaneously. In this case the E interruption is processed and the I interruption is suppressed, due to the fact that the E interruption relates to a prior instruction.

In the case of an E interruption, the ICR has already been advanced to the next instruction. Therefore, the I to E transfer of the next instruction is blocked from having any further effect on the ICR, the IC HO ADV trigger or the PSW length code. In the case of an I interruption, the ICR must still be advanced to the next instruction. At the time of the I to E transfer, ICR 20-22 is advanced normally, IC HO ADV is turned on, if required, and the PSW length code (ILC) is set.

11.4.2 EFFECT OF SS INSTRUCTIONS ON IC ADVANCING

The ICR is advanced normally at the start of all SS instructions, which involve the VFL (variable field length) section of the system. However, during SS instructions the execution unit must alternately have access to the second and third halfwords or syllables, of the SS instruction. This is due to the fact that the first and second operand address functions are handled alternatively by the same fields of IOP, AA, etc. Access to these halfwords is obtained through special controls into the gate select mechanism. An example of SS instruction timing is shown in FIG. 266, in which a Move With Offset (MVO) instruction is taken as the example.

At TON T2 of SS instructions, the "SS OP" status trigger is turned on, providing an SS OP control signal. This latches the gate select prelatch, thus holding bits 20-22 of the address of the SS instruction at the gate select adder input SSOP also inhibits the normal gating of the instruction format length (which indicates length) into the control side of the gate select adder. However, upon the occurrence of TON T2, GSR is updated in a normal fashion. At the I to E transfer the GSR is transferred to ICR 20-22; an IC HO ADV can also take place if needed. Thus, the ICR is advanced for SS instructions as in other instructions, and the ICR thereby has the proper value for handling any interruptions during the SS instruction E time.

At TON T2, BLOCK ICM is turned on, and at the I to E transfer BLOCK T1M and BLOCK T2M are turned on. These three triggers guarantee that neither IC fetches nor I time of the next instruction can interfere with the SS execution, since further T1 or T2 cycles are blocked.

The VFL ADR trigger is turned on with I to E transfer in an SS instruction, the output of which, called NFG ADR, is used to set the output of the GSA into the GSR: an early B Clock, timed to not overlap an A clock, is used to gate this transfer, and serves, in effect, as a latch, since the GSR is guaranteed not to change until after the ICLO has been set on the I to E transfer.

During execution of the SS instruction, the VFL unit has control over a special line called VFL ADR ADV, which provides an ADV 1 HLF WD (advance one halfword) input to the GSA. Since SS OP is on, it follows that the address of the SS instruction is held (latched) at the gate select adder input by the gate select adder prelatch, and normal length code addition (under control of instruction formats) is suppressed. Thus with each early B clock, the GSR is either set with the address of the SS instruction (if there is no VFL ADR ADV) or is set to the address of the second half word of the SS instruction (if there is a VFL ADR ADV signal present).

The IOP register is set from the AB register by VFL ADR concurring with SS OP on every A clock. The SS instruction is still in the AB register because IC fetching is blocked during SS instruction executions. IOP is set according to the quantity which was placed in the GSR by the previous early B clock. Therefore IOP is loaded on every A clock with either the first two half words or the second two half words of the SS instruction, depending ultimately on the VFL ADR ADV line, SS OP gates the IOP D field and the general register addressed by the IOP B field to the addressing adder. Therefore, on the cycle after IOP is set, either the address resulting from the addition of the contents of GR B1 to the D1 field (or the contents of GR B2 plus D2) is available at the input to the SAR and the H REG, since the VFL apparatus has controls for setting the resulting address into the SAR or H REG as desired.

At the end of an SS instruction, the VFL THRU line is activated so that the I unit will return the controls to normal operation. VFL THRU turns off SS OP with an A clock, thus unlatching the GSA prelatch. VFL now holds down the VFL ADR ADV line, and a line called VFL ADR & NOT (T1) or LCH) blocks the length code from entering the gate select adder. Therefore, ICR 20-22 flushes through into the gate select adder from the GSA PRELATCH and is set into the GSR on the next early B clock. The GSR now contains the proper value for the next instruction. BLOCK T1M is turned off on the next A clock and T1 of the next instruction is turned on. BLOCK T2M, BLOCK ICM, and VFL ADR are all turned off whenever SAR is no longer needed by the SS instruction. However, when T1 turns on, VFL ADR & NOT (T1 or LCH) is disenergized and no longer blocks the length code input to the GSA. Therefore, a normal add is made in the gate select adder at TON T2.

11.4.3 THE REPEAT INSTRUCTION FUNCTION

The repeat instruction function (called REPEAT INST hereinafter) is designed to enable the continuous execution of an instruction located in the left end of the A register. In order to utilize REPEAT INST it is necessary to first place the desired instruction in the left end of the A register.

All instructions may be processed in REPEAT INST mode except branches, LPSW or XEQ. Also, interruptions or IC recoveries may not be taken while in REPEAT INST. Any of the above exceptions initiates instruction fetches to A and B, thus destroying the instruction being repeated. A steady MC REPEAT INST signal suppresses the following gates in the gate select mechanism:

1. ICR 20-22 to gate select adder input

2. Length code to gate select adder input

3. GT GSR TO ICR

Repeat instr and NOT VFL ADR holds the gate to the GSR open continuously.

Except during SS instructions, the suppression of gating forces zeros to be flushed into the gate select adder. The zeros are set into the GSR because of REPEAT INST and NOT VFL ADR. The GSR holds zeros at all times and thus continuously selects the first halfword in the A register. At no time is the GSR able to make an ordinary advance. The gate back to ICR 20-22 is suppressed in order to prevent setting the ICR with incorrect parity. If the original parity in the ICR was correct, it will remain correct throughout the operation of REPEAT INST.

During SS instructions VFL ADR is on and therefore REPEAT INST and NOT VFL ADR no longer sets the GSR. The SS controls now operate and are able to utilize the gate select mechanism in the usual manner during instruction execution. Upon completion of the SS instruction, zeros are returned to the GSR.

Since the GSR continuously indicates all zeros, thereby specifying the first halfword of the A register, neither the A REG nor the B REG can be exhausted, and so no IC fetches are needed during REPEAT INST.

11.5 INSTRUCTION FETCHING

11.5.1 GENERAL

In the instruction counter apparatus, the interlocks between IC advancing and IC fetching are indirect in nature. Advancing of the IC and fetching of instructions take place at times which are not closely synchronized. In order to generate correct IC fetch addresses the instruction fetching mechanism monitors the ICR. On the basis of the ICR and the loaded status of the AB register the ICR is modified in the incrementer to obtain an instruction fetch address.

Seven rules of IC fetching, which are discussed in detail in following sections, are used in providing IC fetch control.

11.5.2 RULE 1. IOP LOADED RULE

In order to turn on T2 of an instruction, all halfwords (or syllables) of the instruction must have been in IOP for at least one "good" T1 cycle. The GSR is set with bits 20-22 of the instruction address no later than the cycle preceding the start of T1. The GSR is set with an A clock for normal ICR advancing; but in other cases, such as at the termination of SS instructions or branching, the GSR is set with an early B. In either case, the GSR output has at least three-fourths cycle to select a gate from AB to IOP. Any words returning to A or B are loaded with a late BR clock and an advance from BCU. BCU generates an A advance to gate in A and a B advance to gate in B. The contents of A or B have, at the very least, one-fourth cycle to get to IOP. Usually, however, the required instruction will have been available in the AB register for a number of cycles.

On the AR clock immediately following the late BR clock on which a word is returned to the A or B register, the trigger A LOADED or B LOADED, respectively, is set. The loaded triggers are set by the same logic which gates in the data to AB. A LOADED stays on until the last instruction is removed from the A register. B LOADED is treated similarly. A LOADED and B LOADED indicate when the A register and B register, respectively, contain unprocessed instructions. With the start of every T1 cycle, IOP is set from the output of the selected AB gate.

The line IOP LOADED must rise before T2 can be turned on. This line, which indicates when an unprocessed instruction is available at the output of the AB ORs, indicates that the instruction being sensed in A or B is complete in only A or B, respectively.

GS20, GS21 and GS22 are positions of the GSR. P0 and P1 are positions of the selected word from the AB registers. P0 goes to IOP 0 and P1 goes to IOP 1. The above line is latched with a not B clock and is then used to condition TON T2.

An explanation of the above line follows. If both A and B are loaded, then certainly a good instruction is available in IOP no matter which AB gate is selected. If the instruction selected is contained entirely with the A register and A is loaded, then again a good instruction is available in IOP. The instruction addressed is entirely within the A register if GSR position 20 is zero and if none of the following are satisfied:

1. The instruction starts at the last halfword of a register (GS21=1, GS22=1) and is not an RR instruction,

2. The instruction starts in the last half of a register (GS21=1) and is an SS instruction (i.e., if P0=1).

Exactly analogous reasoning holds for the B register.

The line IOP LOADED is latched with a not B clock because of a problem arising during single cycling. A fetch may return to A or B on a running B clock a few cycles after the last controlled clock pulse has been given. IOP is loaded on an A clock however. If T1 is on and if the turn on of T2 is waiting for IOP LOADED, it is clear that this line must not be allowed to rise before IOP has been set. Immediately upon setting the A (or B) register and the associated A LOADED trigger (or B LOADED trigger), the raw line IOP LOADED rises. The line IOP LOADED LCH does not rise because it was latched after the last B clock. IOP is set with the next A clock and IOP LOADED LCH rises with the next corresponding B clock. Therefore a "good" T1 cycle will occur before T2 is turned on by IOP LOADED LCH.

11.5.3 RULE 2. EMPTY RULE

If an instruction is emptying the A register or B register and an IC fetch is therefore required, the A LOADED trigger is turned off an TON T2. Though this section discusses the A register, an exactly analogous discussion holds for the B register. The logic, called NOT A LOADED, for recognizing the last instruction in A is GS20 (GS20 for B register) and any of the following:

1. GS21&ID RR

2. gs21&gsS22

3. gs22&idss

idrr is the ANDed output of IOP 0 and IOP 1. IDSS is the ANDed output of IOP 0 and IOP 1.

The first term covers any two or three halfword instruction starting in the last half of A. The second term covers any instruction starting in the last quarter of A. The last term covers SS instructions starting in the second quarter of A.

NOT A LOADED (ANDED with no outstanding fetch to A) is the normal method for indicating the necessity for a fetch to A. If IC fetches are not blocked and if a fetch to B does not have priority a fetch request to A is made on the next A CLK. As explained previously, A LOADED is turned on when the fetch returns to A. However, an auxiliary trigger I CAM (instruction counter fetch to A memorized) is turned on when the BCU accepts the request to A. ICAM (along with its turn on) serves to indicate an outstanding fetch. ICAM (along with its turn on) prevents A LOADED from indicating a fetch required condition for A. Accept is applied thereto in anticipation thereof.

If an instruction is emptying the A register, the conditions which turn off A LOADED at TON T2 also enter directly into the fetch request circuitry. If IC fetches are not blocked and if a fetch to B does not have priority, a fetch request to A is then made at TON T2. For a number of instructions, including most RR's, this anticipation circuitry allows early IC fetches to be made.

It should be noted that if the system is in Repeat Instruction, then the GSR never leaves the first halfword of the A register. Therefore, no instruction buffer is ever made empty and no IC fetch is ever made. Thus the contents of the instruction buffers remain unchanged throughout Repeat Instruction.

11.5.4 RULE 3. IC FETCH RULE

If either A or B is empty and if IC fetches are not blocked, an IC fetch request is sent to the BCU, and remains in control until an accept is received, or until IC fetching is blocked. If both A and B are empty, the priority circuitry described in the next section (IC Address Rule) determines which register is first requested. This section discusses fetches to the A register and, as before, an analogous discussion holds for the B register.

At the same time as an IC request is made to BCU, the trigger IC AFE (Instruction counter fetch to A execute) is turned on. On any A clock on which an IC request is made SAR is set from the incrementer. This is controlled by NOT BLK ICM, and is described under the Block IC section. IC AFE turns off unless turned on. It therefore is turned on each cycle of a request for A is made, and goes off on any cycle that a request for A is not made. IC AFE has two functions. First of all it is OR'ed with IC BFE to indicate that the fetch is to be returned to the A or B register. If a fetch to AB is indicated, BCU examines bit 20 of SAR and sets the A return trigger in BCU if SAR20=0, and sets the B return trigger in BCU if SAR20=1.

When the accept is received from BCU, IC AFE steers the accept to turn on IC AFM. IC AFM is the "IC fetch to A outstanding" trigger. ICAFM remains on until the word is returned to the A register. At this time A ADV turns off ICAFM and turns on A LOADED.

The full logic for generating the "A empty" condition of the previous section can now be described. A appears empty to the fetch logic if the following expression is satisfied: NOT A LOADED and NOT IC AFM and NOT IC AFE or NOT ACCEPT or the combination of + ID A EMPTY.TON T2 The first term represents the normal empty condition and the second term is the anticipatory term. Notice that NOT IC AFE or NOT ACCEPT is included in the first term. This quantity makes the register look full immediately upon receipt of the accept for an IC fetch to A. Therefore IC AFE will not stay on after the accept has been generated. The normal fetching is shown in FIG. 215.

If the B register is empty at the same time as a fetch to A is being made, it is possible that the fetch request to A is followed by a fetch request to B. The request to B in this case occurs on the cycle following the cycle of the accept for the first fetch. The request to B is not made on the cycle of the accept because the address circuitry (see next section) is not able to respond until IC AFM is turned on. This causes no deterioration in performance because of the two-cycle bus rate of BCU.

If the CPU is being single cycled, the sequencing of the IC fetch sequencers is slightly modified. At this time, single clock pulses are generated upon each depression of the start button. All running clocks continue to operate, however, in the normal high speed manner.

PULSED ACCEPT is a 200 nsec. latched line which stradles the AR CLK following the start of storage activity. ACCEPT rises at the same time as PULSED ACCEPT and falls after the first A CLK following the start of storage.

The request trigger in BCU (CPU REQUEST) turns off with each A CLK unless turned on by a request from CPU at a time when ACCEPT is not on. The request trigger is also turned off by PULSED ACCEPT AR CLK. Since single-cycle pulses can be issued at a very slow rate only, it follows that any word requested on one A CLK will be returned to the CPU before the next A CLK. It also follows that the BCU request trigger is turned off by PULSED ACCEPT and cannot be turned on with the next A CLK.

IC AFE is turned on and off with an A CLK. IC AFM is turned on and off with an AR CLK. A LOADED is turned on with an AR CLK and is turned off with an A CLK. Therefore, if an IC request is made while single cycling, IC AFE will turn on and stay until the next A CLK. IC AFM will turn on and off at high speed, and A LOADED will turn on when IC AFM turns off. This is shown in FIG. 218.

11.5.5 CHART OF IC FETCH ADDRESS GENERATION

ICR AE & NOT BE AE & BE NOT AE & BE NOT AE & NOT BE POSITIONS CTRL REG CTRL REGCTRL REG

20 21 22 19 20 19 20 19 20 19 20 0 0 00 0 a r0 0 a 0 1 b 0 0 a r 0 0 10 0 a r 0 1 a r 0 1 b 0 0 a r 0 1 0 1 0 a 0 1 b 0 1 b 1 0 a 0 1 11 0 a 0 1 b 0 1 b 1 0 a 1 0 0 0 1 a 0 0 b 0 0 b r 0 0 b r 1 0 1 0 1 a 0 1 b r 0 0 b r 0 0 b r 1 1 0 0 1 a 0 1 a 1 0 b 1 0 b 1 1 1 0 1 a 0 1 a 1 0 b 1 0 b ae = not ic afm or a loaded be = not ic bfm or b loaded ctrl 19 = add 2 input to incrementer pos. 19 ctrl 20 = add 1 input to incrementer pos. 20 a,b indicates the register to which the fetch is made. r indicates inputs cannot occur and entry is therefore redundant.

11.5.6 rule 4. ic address rule

whenever BLK ICM is off (that is, whenever IC fetches are not prevented by BLK ICM) or the ICR is gated to the incrementer and an increment amount is added into positions 19 and 20, in dependence upon the empty status of the A REG and the B REG, the amount to be added to the ICR is shown in the chart of the preceding section, which also indicates whether the generated address is for the A register or the B register. This chart does not illustrate branch fetches or the first IC fetch during an IC recovery, but it does indicate how addresses are generated for any other IC fetch situation. AE is equal to the expression NOT A LOADED & NOT IC AFM, and BE is NOT B LOADED & NOT IC BFM. AE or (BE) therefore is an unlatched line which is related to the need for a fetch to A or (B). AE and BE are used in conjunction with ICR 20-22 to generate the increment amount for the incrementer and are therefore the five coordinates of the chart. Whenever an R appears in the table, that entry then represents a situation which can never happen if the machine operates correctly. An analysis of the various entries now follows:

Consider those entries of NOT AE & BE for which ICR 20=0, which means that current fetching is from the A register, that A does not need to be fetched, and that B does need to be fetched. Therefore good instructions in A are currently being processed, but the B register must be fetched if instruction processing is to continue to proceed without interruption. Since instructions are fetched sequentially and the ICR specifies the address of an instruction in the A register, it follows that ICR bits 0-20 of the proper address for a fetch to B can be obtained by adding a 1 into position 20 of the ICR. Since SAR bits 21-23 are ignored by the BCU. No problem is created by the fact that the output of incrementer positions 21-23 is set into SAR along with the rest of the address.

If ICR 20=0 in the case of AE & NOT BE, then A must be fetched and B does not need to be fetched. This situation can arise while processing the last instruction in the A register. At least one cycle occurs after the AE condition has been recognized and before the ICR has been updated to the B register.

The case where AE & NOT BE obtains with ICR 20=0 cannot occur until at least one good T1 cycle has been executed on an instruction located in the A register. This can be demonstrated by considering the situation with ICR 20=0 and AE, and with no instructions in the A register yet processed: the ICR has therefore just left the B register, thereby emptying that register without any fetches being made. If the AE condition exists, then the A register has necessarily been empty for an extended period. The situation is now ICR 20=0 with AE & BE, and the A register is provided with a fetch at this time. Therefore, the situation now becomes ICR 20=0 NOT AE & BE. Thus ICR 20=0 with AE & NOT BE cannot occur until an instruction in A is processed.

If the ICR addresses the first halfword of A, then A cannot be emptied by use of a single instruction in A because it would take a four halfword instruction to empty A and no instruction exceeds three halfwords. If the ICR addresses the second halfword of A then A can be emptied only through an SS instruction. For SS instructions, however, IC fetching is always blocked during the period between the recognition of the empty condition and the advance of the ICR and again this situation cannot occur. Therefore the top two entries in the situation now being considered are marked with an R (for redundant). If the third or fourth halfwords are specified, since B is already loaded, it is necessary to fetch the A register two storage words ahead of the ICR. Therefore a bit is added to the ICR in position 19.

If ICR 20=0 with AE & BE then both A and B must be filled. If the ICR addresses any but the first halfword of A then the AE condition occurs as just described for ICR 20=0 with AE & NOT BE. The only difference arises from the fact that the previously emptied B register has not yet been filled. Therefore the fetch will be for the B register, the address for which is obtained by adding a bit into position 20 of the incrementer. Again, the situation for the ICR addressing the second halfword of A is redundant because SS instructions block the IC, and only an SS instruction is long enough to exhaust the A register.

If the ICR addresses the first halfword of the A register with AE & BE, then there are no loaded instructions available in the instructions buffers. Before the instruction at the address specified by the ICR can be executed, a new instruction must be fetched to the A register. Therefore the ICR is used as a fetch address without any modification.

The entries for ICR 20=0 with NOT AE & NOT BE have meaning because a fetch request can be made at the same moment as A LOADED is turned off. Therefore it is necessary to generate a correct fetch address in anticipation of an empty condition. (An example of this situation is shown in FIG. 268) This column is the same as the column for ICR 20=0 with AE & NOT BE because the only new empty condition which can be generated while ICR 20=0 is the A empty condition.

All of the foregoing reasoning holds for entries in the chart for which ICR 20=1, with the exception that AE and BE must be interchanged in the explanation.

As described under ICR Advancing, hereinbefore, the generation of IC fetch addresses is not inhibited if there is an IC high order advance. At this time the ICR address is incorrect because a carry from the ICR LO must be entered into position 19. While gating the ICR to the incrementer, ICHO ADV forces a one into position 19. If an IC HO ADV is taking place when bit 20 must be zero, and ICR 20-22 = 000, 001, or 010. If ICR 20-22 = 010 when an IC fetch occurs, then an SS instruction is being executed and IC fetches are necessarily blocked by the SS execution. If ICR 20-22 = 000 or 001 then the chart in the preceding section indicates that either a 0 or a 1 must be added into position 20 of the ICR. If the entry is 0, then the correct updated ICR (Old ICR +1 in position 19) for the IC HO ADV is obtained at the output of the incrementer for IC fetching. If the chart entry is 1, then (Old ICR + 1 in position 19 + 1 in position 20) is obtained at the output of the incrementer, and this is the correct value for making an IC fetch, so that, as described under ICR advancing, hereinbefore, bits 0-20, 23 of the incrementer contain the correct updated IC HO value for all cases and are therefore gated back into the ICR at the end of the ICR HO ADV.

Thus, during IC HO ADV, IC fetch addresses may also be computed and no special interlocks are necessary to inhibit the IC fetching during this time. (An example of this situation is shown in FIG. 269)

11.5.7 RULE 5. BLOCK IC RULE

Many instructions block IC fetches in order to insure that no interference occurs in the usage of SAR or the incrementer. For all instructions which block the IC, the trigger BLOCK ICM is turned on by TON T2, concurring with ID BLK IC. IC Fetch requests and the gating of ICR to SAR are inhibited by TON T2 and ID BLK IC or BLOCK ICM LCH. The ICR, along with the appropriate increment amounts, (ADD 1 OR ADD 2) is gated into the incrementer for IC fetch address computation whenever BLOCK IGM is off. When BLOCK ICM is turned on, this gating is suppressed.

The timing for BLOCK ICM is shown in FIG. 269 and FIG. 270.

The uses of BLOCK ICM by instruction classes are now described.

a. One Fetch Class

For this class an operand is fetched at TON T2. During the fetching of the operand, the IC controls are denied access to SAR. Upon generation of ACCEPT (which indicates that the fetch request is being honored by storage), the IC fetch mechanism is again allowed to operate. ID ONE FETCH CL (class) and OPF and ACCEPT and NOT TON BLK ICM, turn together BLK ICM off. An IC fetch address is then generated which can be set into SAR at the next A time. This is the earliest time that the BCU can accept another storage request because of a two cycle bus rate, described in section 6.2.9. Therefore, the I unit controls are able to operate the BCU at its maximum rate in this situation, if necessary.

The instructions which belong one fetch class are most of the external fetch instructions for which no storage requests are made during E time. These include instructions such as A, SD, DE and TM.

For the following instructions the execution unit makes use of SAR for storage fetches and stores:

b. Store/Fetch Execution Class

STH, STC, CVD, ST, STD, STE, SSK, ISK, RD, STM, MVI, NI, OI, XI, LM; SS Instructions Therefore, the IC controls are inhibited from making any requests until the last storage request of E time has been accepted. At this time the execution unit, or the I unit controls in the case of SS instructions, generates a signal on a TOF BLK T2M ON acc LINE. This line, which conditions the turn off of BLK T2M is also used to condition the turn of BLK ICM. The condition which actually turns BLK ICM off, except for SS instructions, is TOF BLK T2M ON ACC together with ACCEPT and NOT TON BLK ICM,. For SS instructions, NOT SSOP and VFL ADR with either NOT STORE REQUEST or ACCEPT combine to turn off BLK ICM. As described under SS instructions, hereinafter, SSOP and VFL ADR occur together at the end of an SS instruction. At this time, if there is no store request outstanding, BLK ICM is turned off immediately. If there is a store request outstanding, BLK ICM is turned off upon receipt of the ACCEPT.

c. Branches

IC fetches are blocked until the end of branch instructions, and the Execute (XEQ) instructions, which provides the branch controls with access to both the incrementer and SAR.

The turn off conditions for BLK ICM are described with respect to branching in D-0037.

d. BALR (R2=0), LA

For these instructions (and certain instructions of the Store Fetch class), instruction execution makes use of the incrementer. Therefore, BLK ICM is turned on to prevent IC fetch address generation from interfering with the instruction execution use of the incrementer. The E unit turns off BLK ICM when through with the incrementer.

e. LOAD PSW

BLK ICM is turned on for the Load PSW instruction because a fetch is made at TON T2. It is turned off when the new PSW has been loaded and an IC Recovery has been started.

f. Diagnose

BLK ICM is turned on for the diagnose instruction because the I E Unit makes a fetch during E time. BLK ICM is turned off by a sequencer (IE 3) which in turn is turned on by a PROCEED signal from the PDU. This insures that the IC fetches will always start at a known time after a Diagnose.

Interruptions

BLOCK ICM is also turned on during interrupt routines even though the turn on of BLOCK ICM does not itself block IC fetches, in this case, because the interrupt lines themselves directly block IC fetches at this time. BLOCK ICM is turned off when an IC recovery is started.

Resets

BLOCK ICM is turned on by a CPU reset: if the reset resulted from an IPL or a machine check, BLOCK ICM is turned off at the end of the appropriate routine; if the reset resulted from a manual reset, BLOCK ICM is turned off by SET IC or SET PSW.

11.5.8 RULE 6. PRE BLOCK IC RULE

Whenever the GSR is advanced to select a new instructions, that new instruction (if in AB) becomes available at the output of the eight way OR off the AB register. If certain branch instructions are decoded at this point, then IC fetching is blocked. An example of this block is shown in FIG. 272 This block does not prevent generation of IC fetch addresses and their placement into SAR, but only inhibits the IC fetch request line to BCU. The combination which generates the block is IOP LOADED and together with one of the following predecode outputs: BALR, BAL, BCTR, BCT, XEQ, BXH, or BXLE.

The effect of this rule is to block unnecessary IC fetches before branches which have a high probability of being successful branches. Thus, storage activity just before the branch fetch is decreased by blocking the IC fetch. This increases the likelihood that the branch fetch can be made without running into storage conflicts. BCR and BC are excluded from this block because these are not considered to be branches with a high probability of success.

11.5.9 RULE 7. IC FETCH PRIORITY RULE

The action of the previous rules may be summarized as follows: the empty status of a register is recognized at TON T2 of the instruction emptying that register. IC fetch requests are then made to that register unless some instruction in the process of execution generates a block to inhibit IC fetching. This block may occur through the action of BLOCK ICM or through the action of pre block IC. IC fetch requests may or may not be accepted by BCU. A fetch request which has not yet been accepted by BCU may be cancelled at any time by a block generated by a new instruction. It is therefore possible for the IC fetch to be made very early, and it is also possible for IC fetches to be blocked out continuously by instruction executions until both registers are emptied. If both registers are emptied, all IC blocks are definitely removed, and both registers are fetched in proper order.

It is the nature of these rules to give IC fetches low priority, except when both A and B are empty. Whenever an IC fetch request is recognized to cause interference with instruction execution, the instruction execution wins out. This has two advantages: (1) IC fetches cause minimum interference with instruction executions; (2) if IC fetches are not forced prematurely, they will be recognized to be unnecessary if a successful branch is encountered before both registers are emptied, and are thus avoided. Therefore, an unnecessary storage cycle is not taken. However, for normal instruction sequences (i.e. sequences not containing successful branches) a net performance loss is suffered if both registers are allowed to become empty.

With both registers empty it is necessary to make an IC fetch while the I unit remains idle. This results in a significant number of lost cycles. It is better to take a smaller penalty by forcing IC fetches at some earlier time when instructions are still available for processing. Therefore this rule-- IC Fetch Priority-- is incorporated to allow IC fetches to be made as late as possible while minimizing the chances of the I unit being idled by lack of instructions. The action of this rule is accomplished by blocking TON T2 at times which are described in the following. An example of usage of this rule is shown in FIG. 269.

TON T2 is blocked by the combination of not a branch or RR instruction from the I decode together with both GSR bits 21 and 22 present, together with either GSR 20=0 & B FTCH REQD GSR 20=1 & A FTCH REQD, where A FTCH REQD = NOT IC AFE or NOT ACCEPT, NOT IC AFM and NOT A LOADED. With A FTCH REQD, note that no block of TON T2 can be generated by this rule until the GSR addresses the second, third or fourth halfword of B, since there are ample instructions available in B (or in A and B together) until this time; thus forcing IC fetches prematurely is avoided.

If the GSR addresses the second, third, or fourth halfword, and the instruction is an RR instruction, then again no block is generated. A block is not generated because no interference is possible between RR instructions and IC fetches (except for ISK, SSK, and the branches). In all probability the IC fetch will be made without any special block to hold up RR execution most of the time.

If the GSR addresses a branch instruction (RS, RX branch, or RR branch with R2 0 ) then IC fetching is not given special priority. This is for the same reason that the Pre-block IC Rule was incorporated: it is undesirable to make IC fetches which might prove unnecessary before a branch instruction. If branches were not excluded from bringing up IC fetch priority there would be a conflict between these two rules.

If the GSR addresses any instruction which starts in the last three halfwords of B and which is neither a branch nor an RR instruction, and A is exhausted, then the IC fetch priority holds up TON T2 until a fetch to A has been made. RX instructions are assumed to be the instructions with the highest rate of occurrence; it follows that if A is empty, an instruction starting in the second, third, or fourth halfwords of the B register is probably the last complete instruction available in the buffers. It is therefore another feature of this rule to force any unmade IC fetches before TON T2 of the probable last instruction in the IC buffers. As a result, there is an excellent chance that a new instruction will be available in the buffers when needed for execution.

11.6 INSTRUCTION FETCHING-- SPECIAL CASES

11.6.1 PROGRAM STORE COMPARE

If a store is made by the CPU to an address which has been prefetched to the AB register, it becomes necessary to refetch the storage word for that register. Whenever a store is made to either the storage word addressed by the ICR or to the next adjacent storage word, the storage word is refetched. To sense this condition, two comparisons are provided which enable comparison between the store address and the ICR, and between the store address and the address next to that of the ICR. Whenever a store takes place (except stores made by interruptions) these comparisons are made without regard to whether or not the instruction buffers have been loaded. If the addresses do compare, an IC Recovery is taken as an E time interruption and the AB registers are refetched.

Whenever a CPU store (except an interrupt store) is made, the STR REQ latch is turned on. This latch gates the ICR into the incrementer and adds one into position 20; BLOCK ICM is always on at this time.

At the time that a store address is set into SAR, the address is also set into the H REG. The is compared H register. A full compare of the H register bits 0-20 with ICR bits 0-20 and a full compare of H register bits 0-19 with the incrementer output bits 0-19 are made. The second compare can be modified to include bit 20 in the event that no IC HO ADV is being made. This is illustrated in the following chart:

BITS COMPARED

COMPARE NOT IC HO ADV IC HO ADV H: ICR 0-20 -- H: INCR 0--20 0-19

store request gates: icr to INCR +1 to INCR position 20

IC HO ADV GATES: ICR TO INCR +1 to INCR position 19

if all bits in any of the indicated comparisons are satisfied when store request is on, the trigger prg sto cmp is turned on.

If the IC HO ADV is off, bits 0-20 of the H register is compared to bits 0-20 of the ICR and to bits 0-20 of the incrementer output. Bits 21-23 are ignored because they are not relevent to external storage addresses. If either compare is satisfied while STO REQ is on, PGR STR COMP is turned on and an IC Recovery will result at the end of the instruction. If IC HO ADV is on, the ICR is necessarily two full storage words behind its proper value. Therefore, the H:ICR compare is blocked by IC HO ADV. Since 1 is added into incrementer position 19 by the IC HO ADV and 1 is added into incrementer position 20 by the STR REQ it follows that the incrementer output is one full storage word ahead of the correct ICR value. Whenever IC HO ADV is turned on, bit 20 of the ICR is necessarily zero. With bit 20 = 0, if H REG bits 0-19 are compared to incrementer outputs 0-19 the following comparisons are effectively generated:

1. 0-20 of H to 0-20 of the "correct" ICR;

2. 0-20 of H to 0-20 of the next address following the "correct" ICR.

If the H:INCR comparison is satisfied, PGM STR CMP is a gain turned on.

11.6.2 INTERRUPTION ENTRY

Whenever an interruption is detected and a signal appears on one of the three interruption lines into the I unit sequencing controls, IC fetches are immediately blocked. The IC fetch controls may still attempt to make IC fetches, but since no storage unit can be started, it is impossible for the request to be acknowledged. All IC fetching is terminated by the first interruption sequences, and the IC controls are reset and BLOCK ICM is turned on (unless the interruption is an IC Recovery only).

11.6.3 IC RECOVERIES

During an interruption routine, the instruction LPSW, or the manual operations SET IC or SET PSW, a new value is placed into the instruction counter. It is therefore necessary to refetch the A and B registers. At the appropriate time after the IC has been loaded, a signal is generated by the unit loading the IC. This signal starts an IC recovery. A typical example of an IC recovery is shown in FIG. 222. This signal resets A LOADED, B LOADED, BLOCK ICM, and BLOCK T1M; and sets IC RECOVERY.

IC RECOVERY blocks the control inputs into the gate select adder and gates the gate select adder into the GSR at A time. Thus the GSR is correctly loaded for the first instruction.

IC RECOVERY prohibits the normal methods of generating IC fetch addresses and of establishing priority between the A and B registers. The ICR is gated directly through the incrementer to SAR. Since BLOCK ICM is off, an IC fetch request is now made. This fetch is from the location addressed by the ICR and goes to the instruction buffer indicated by ICR 20.

IC RECOVERY finally resets J LOADED to insure that it is not left on if a previous instruction failed to reset it.

IC RECOVERY is reset by P-ACC with either IC AFE or IC BFE, and an AR clock signal. Therefore IC RECOVERY turns off when the first fetch is accepted. The IC fetch controls now operate normally and fetch the next storage word for the second instruction buffer. T1 turns on one cycle after BLOCK T1 M is turned off, and instruction sequencing now proceeds normally.

11.8 INSTRUCTION COUNTER FETCH CONTROL CIRCUITS

The following sections are concerned with IC fetches, and more particularly with the control circuits which govern the operation of instruction fetches, and other related circuitry.

11.8.1 E AND IE BUSY LATCHES FIG. 212

In FIG. 212 a signal is generated on the E BUSY line by a latch 1 which is set by an OR-circuit 2 in response to a signal on a SCAN IN E BUSY line or in response to an AND-circuit 3. The AND-circuit 3 in turn is responsive to an AND-circuit 4 which is operated at the I to E transfer when there is no interrupt and an execution by the E unit is required as indicated by a signal on a BD E EXEC line. The other input to the AND-circuit 3 is a timing line which causes the circuit to operate at A time. The latch 1 is reset by an OR-circuit 5 in response to a CPU reset signal on a CPU RST line, or in response to an AND-circuit 6 which is operative at A time of a last E cycle provided there is an input thereto from an inverter 7. The AND-circuit 6 responds to signals on the AC line and on the ELC LCH line so as to reset the latch 1 unless ELC occurs at the I to E transfer without an interrupt and another E execution is required, or as indicated by an AND-circuit 4. The output of the latch 1 is applied to a bipolar latch 8 which reflects the setting of the latch 1 at not LC time, and thereby generates the signal on the E BUSY LCH line and the complement thereto. The E BUSY line is applied to an OR-circuit 9 to generate a signal on an E BUSY OR IE BUSY line. The other input to the OR-circuit 9 is the output of the latch 10 which is set by an OR-circuit 11 in response to a signal on a SCAN IN IE BUSY line or in response to an AND-circuit 12. The AND-circuit 12 is operative at A time in response to an AND-circuit 13 which in turn recognizes the I to E transfer without interrupt due to a signal on the I TO E & NOT IRPT line concurrently with the output of an OR-circuit 14 which recognizes branch and IE functions due to the signals on the BD I EXEC and BR OP LCH lines. Thus, either a branch execution or an I execution will cause the setting of the latch 10. The latch 10 can be reset by an OR-circuit 15 in response to a CPU reset or in response to one of two AND-circuits 16, 17. The AND-circuit 16 is operative at A time at the end of the last IE or BR cycle as indicated by signals on the AC line and on the IEL LCH line or BR LC line provided that there is an input from an inverter 18 from the AND-circuit 13. Thus, as is true in the case of the latch 1, the latch 10 will be reset during the last IE or BR cycle unless a further IE or BR cycle is being called for. The AND-circuit 17 is operative at A time when IOP is loaded and an execute sequence is being performed. The output of the latch 10 comprises the signal on the IE BUSY line, and a complement thereto, and is also applied to a bipolar latch 19 which is caused to follow the setting of the latch 10 at not LC time so as to generate a signal on the IE BUSY LCH line and the complement thereto.

11.8.2 STORAGE REQUEST CIRCUITS FIG. 213 AND FIG. 214

In FIG. 213, a storage request signal is generated on a STR REQ line by a latch 1 which is set by an OR circuit 2 in response to a scan in signal on a SCAN IN STR REQ LCH line or in response to an AND-circuit 3. The AND-circuit 3 may be operated by an OR-circuit 4 which in turn is operable in response to an AND-circuit 5. The AND-circuit 5 recognizes I to E transfer without interrupts where a storage request is indicated by the BOP decode circuitry, all as manifested by signals on the BD STR REQ line, the NO IRPTS line, and the I TO E XFER line. The OR-circuit 4 also responds to signals on a E STR REQ line and the IE STR REQ line. In order for the OR-circuit 4 to cause the AND-circuit 3 to set the latch 1, there must be a signal from an inverter 6 indicating that there is no current accept signal, and the storage request latch line has not been energized as indicated by an AND-circuit 7. The AND-circuit 7 responds to a signal on the ACCEPT line, and to a signal on the STR REQ LCH line, which signal is generated by a bipolar latch 8 that is set by the latch 1 at not LC time. Thus, once the latch is set, the bipolar latch 8 will become set and when an ACCEPT is returned from the BCU, the AND-circuit 7 will block the AND-circuit 3 and will also have its output applied to an AND-circuit 9 which is operative at A time to cause an OR-circuit 10 to reset the latch 1. The OR-circuit 10 can also respond to a CPU reset signal on a CPU RST line.

In FIG. 214, an I unit storage signal is developed on an I STR line by an OR-circuit 11 in response to an AND-circuit 12 which in turn senses the I to E transfer without interrupt when a storage request is made (in the same fashion as the AND-circuit 5 in FIG. 213), and which also can respond to storage requests from the IE unit or from interrupts, or to the output of the circuit of FIG. 213 on the STR REQ LCH line. Thus, the signal will be generated on the I STR line anytime the latch of FIG. 213 has been set; however, whether the latch is set by means of the AND-circuit 5 or the IE or IRPT storage request, the OR-circuit 11 (FIG. 214) will operate at the same time as the OR-circuit 4 (FIG. 213), thereby anticipating the setting of the bipolar latch 8 by one cycle so as to provide the signal on the I STR line somewhat earlier than would otherwise be possible.

11.8.3 OPERAND FETCH LATCH FIG. 215

In FIG. 215, an operand fetch signal is generated on a OPF line by a latch 1 which is set by an OR-circuit 2 in response to a scan signal on the SCAN IN OPF line, or in response to an AND-circuit 3 which is operative at A time in the cycle with TON T2 present, when the instruction is within the class of instructions which require a fetch as indicated by a signal on the ID FTCH CLASS line. The latch 1 is reset by an OR-circuit 4 in response to either one of two AND-circuits 5,6 or in response to a CPU reset signal on the CPU RST line. The AND-circuit 6 is operative at A time in response to a signal on the IRPT RST line. The AND-circuit 5 responds at A time to the combination of the ACCEPT and OPF LCH, lines. The latch 1 will cause the setting of a bipolar latch 7 to reflect the setting of the latch 1 at not LC time, so as to generate a signal on the OPF LCH line.

11.8.4 CPU RETURN TO AB/J FIG. 216 and FIG. 155

In FIG. 216, a signal indicating that a storage word is to be returned to the AB register in the CPU is generated on a TC RET AB Line by an OR-circuit 1 in response to an AND-circuit 2 which senses the presence of signals on the OPF line and the BR OP line. The OR-circuit 1 also may operate in response to either a signal on an IC RET AB Line or on the BR + 1 E line. Thus, the OR-circuit 1 can operate during a branch op when the operand fetch is indicated, or in response to an instruction counter operation, or when the branch unit is about to fetch the storage word adjacent to the word which contains the branch-to, or subject instruction.

In FIG. 155, a signal indicating that the storage word is to be returned to the J register in the CPU is generated on a CPU RTN J line by an OR-circuit 3 in response to a signal on any one of the following lines: OPF, IRPT FTCH REQ, IE FTCH TO J, or E FTCH REQ. Thus, the OR-circuit 3 will operate for any operand fetch, during an interrupt fetch request, when the IE unit calls for a fetch to J, or for any E unit fetch.

11.8.5 INSTRUCTION FETCH REQUESTS FIG. 217

In FIG. 217, first and second fetch requests for the I unit are provided by signals on the I FTCH 1 line and on the I FTCH 2 line. The signals are generated by a pair of OR-circuits 1,2 in response to five AND-circuits 3-7, each of which is gated by a signal indicating that no interrupts are outstanding on a NO IRPTS line, and in response to four other input lines. The AND-circuit 3 responds to operand fetches as indicated by a signal on the OPF LCH line. The AND-circuit 4 additionally requires concurrence of TON T2 and ID FTCH CLASS indicating that operands are required for this particular instruction. The AND-circuit 5 is operative at I TO E XFER provided there is a signal on a COND BR + 1 E FTCH line which indicates a conditioning of a branch plus one fetch. The AND-circuits 6 and 7 respond respectively to signals on the TON IC AFE line and TON IC BFE line which indicates a turning on of an IC fetch execution for the A or B register, respectively. The OR-circuit 2 is responsive not only to the AND-circuits 6,7, but also to the following lines: BR + 1 E FTCH, IRPT FTCH REQ, IE FTCH TO J, and IE DIAG FTCH, which indicate a branch op second fetch, a fetch request for an interrupt, a fetch for the IE unit to the J register, or a diagnostic fetch, respectively.

11.8.6 IC FETCH EXECUTIONS TO A B

In the following sections, the manner in which IC fetches are initiated and remembered is described. There are provided two sets of primary latches, one set is the "E" set, and the other set is the "M" set. The E set indicates that a fetch should be made, and these latches will stay on until an accept signal is received from the BCU indicating that the fetch request will be honored by the storage device; at that point, the M set turn on and remember that a fetch is outstanding, and this set will remain on until an advance signal is received from the BCU indicating that the fetched data is on its way back from the storage unit. The E set of latches are called IC AFE for the A register, and IC BFE for the B register. The M set are respectively called IC AFM and IC BFM.

11.8.6.1 TURN ON OF IC AFE AND BFE FIG. 218

In FIG. 218, an OR-circuit 1 generates a signal on a TON IC FE line which indicates that either the ICAFE or the ICBFE latch should be turned on. This OR circuit responds to a signal on a NOT PD COND IOP LOADED which is generated in the predecode and shown in FIG. 82; this line indicates that the length of the instruction as compared with the point of the AB registers where the instruction begins indicates that a complete instruction is contained within the AB registers, as described in the section relating to FIG. 82. The OR-circuit 1 also responds to a signal on a NOT PD BR BLK IC LCH line which is generated by the off-side of a latch 2, the latch being reset at every not LC time, and set at not LC time (after a short delay) by an AND-circuit 3 only if there is present the output of an OR-circuit 4 which in turn is responsive to either one of two predecode branch indicating signals on the PD BR GROUP 1 line or on the PD BR GROUP 2 line. Thus, unless the predecode indicates that the current instruction is in a branch group, the latch 2 will be off, and therefore there will be a signal applied to the OR-circuit 1. The nature of the logic for the OR-circuit 1 is based on the fact that whenever a branch is indicated, no IC fetch would be made unless it is possible that the complete branch instruction is not apparent in the AB register. When this is true, then there will be a signal on the NOT PD COND IOP LOADED line so that a fetch can be made anyway. However, if a complete instruction is contained within the IOP register, there will be no signal to the OR-circuit 1 whenever there is a branch indicated by the predecode, so that IC fetching will be blocked by the OR-circuit 1 having failed to generate a signal on the TON IC FE line.

Another latch 5 is provided to determine whether the A or the B register is involved in the current fetch; this latch is set by an AND-circuit 6 provided there is a bit in ICR 20, which indicates that the next instruction to be fetched should be to an odd storage address, and therefore relates to the B register rather than to the A register. When there is a signal on the ICR 20 line, the latch 5 will always have an output. Thus, there will be an input which, together with a signal on the IC RCVY LCH line will cause an OR-circuit 8 to generate a signal on a COND IC BFE line which will cause a B register fetch provided other conditions are met. On the other hand, when there is no output from the OR-circuit 8, an inverter 9 causes any IC fetch to be to the A register in response to a signal on a COND IC AFE line. The OR-circuit 8 is also responsive to an AND circuit 10 which can be operated by the AB fetch latch.

The COND IC AFE line is applied to an AND-circuit 11 concurrently with TON IC FE, NOT BLK IC OR ICM, and NOT IRPT RST. Also applied to the AND-circuit 11 is an OR-circuit 12 which is operated by a signal on a FUNC IC IC AFE line, or either of two AND-circuits 13, 14, each of which will operate only if there is applied thereto signals on the NOT IC AFM LCH line and on the NOT A LOADED LCH line. The AND-circuit 13 also requires a signal on the NOT IC AFE LCH line, and the AND-circuit 14 requires a signal on a NOT ACCEPT line. Either of the AND-circuits 13, 14 can sense the condition of the A register being empty. Thus, when there is no accept signal outstanding, and A is not loaded and there is no outstanding fetch memorized for A, then the AND-circuit 14 recognizes that the A register is empty; when there has been no request for an A fetch as indicated by the NOT IC AFE LCH signal, and no such a request has been memorized by the IC AFM LCH, then if A is not loaded, the AND-circuit 13 will recognize that A is empty. Thus, A can be sensed as requiring a fetch by functional conditions of the IC controls, by the lack of a fetch memorized when A is not loaded with either a lack of an accept signal or the lack of an IC AFE signal. Although not shown in detail for simplicity, a plurality of circuits 15 provide a signal on a TON IC BFE line in the same fashion that the signal is generated on a TON IC AFE line by the circuits 11-14 in FIG. 218.

11.8.6.2 FETCH EXECUTION LATCHES FIG. 219

In FIG. 219, the call for an IC fetch to the A register is manifested by a signal on an IC AFE line which is generated by a latch 1 that is setable by an OR-circuit 2 in response to an AND-circuit 3 or in response to a SCAN input thereto. The AND-circuit 3 responds to a signal on a TON IC AFE line provided there is also a signal on the AC line. The latch 1 is reset by an OR-circuit 4 in response to a CPU reset as manifested on a CPU RST line or by an AND-circuit 5 which may operate at a A time due to the effect of an inverter 6. In other words, at every A time, the latch 1 will either be set or reset depending upon whether there is or is not, respectively, a signal on the TON IC AFE line. The circuit may be set by scan controls or reset by the CPU RST. The setting of the latch 1 will be transferred into a bipolar latch 7 at not LC time so as to generate a signal on an IC AFE LCH line. Although not shown in detail in FIG. 219, a plurality of circuits 8 are provided for the B register which are identical in all respects to the circuits 1-7 which relate to the 1 REGISTER.

The signals of FIG. 219 are those which indicate that a fetch request for the A or the B register in response to IC control has been made. These signals will be continuously reset into the latches 1, 7 at every A and not L time so long as the turn on for the corresponding latch (such as TON IC AFE) remains present from the circuit of FIG. 218. This will be true until an accept signal appears, which will cause the blocking of the AND circuit 14 in FIG. 218, the AND-circuit 13 of FIG. 218 being blocked at this time due to the fact that the bipolar latch 7 is set so there is no longer a signal on the NOT IC AFE LCH line. Thus, eventually the signal on the TON IC AFE line in FIG. 218 will disappear so that the inverter 6 in FIG. 219 will cause the AND-circuit 5 to reset the latch 1 in FIG. 219 rather than set it. The same, of course, holds true for B register fetches.

11.8.6.3 IC FETCH EXECUTION USAGE FIG. 220

In FIG. 220, the signals on the IC AFE and IC BFE lines are applied to an OR-circuit 1 which generates a signal on the IC RET AB line, which signal causes the fetched storage word to return to the AB register as required. In a similar fashion, the signals on the IC AFE LCH line and on the IC BFE LCH line cause an OR-circuit 2 to generate a signal on a IC AFE OR BFE LCHS line.

11.8.6.4 FETCH MEMORIZED LATCHES FIG. 221

In FIG. 221 is shown the circuitry for generating signals on an IC AFM LCH line and on an IC BFM LCH line by corresponding bipolar latches 1, 2 in response to similar latch circuits 3,4. The latch 3 is set by an OR-circuit 5 in response to scan controls, or in response to either one of two AND-circuits 6, 7, either of which operates in response to a running A clock pulse on an AR line. The AND circuit 6 will operate when there is a signal on a BR TON IC AFM line which indicates that branch controls are causing the A fetch memorized latch to turn on. The AND-circuit 7 will operate provided there is a signal on a P-ACC (pulse accept) line concurrently with a signal on the IC AFE LCH line. The AND-circuit 7 therefore indicates that a fetch to A has been requested, and the BCU has accepted the request as indicated by the return of a pulse accept signal. The latch 3 is reset by an OR-circuit 8 in response to a CPU RST, or in response to an AND-circuit 9 which is operative at A time in response to a A ADV (A register advance) line which indicates that a storage unit is momentarily going to supply storage data, and that this data has been indicated to be fetched for the A register. The details of the pulse accept and A advance lines are described with respect to the BCU.

Although not shown in detail in FIG. 221, the circuits 4 which relate to the B register are identical to the circuits 3, 5-9 which relate to the A register, as before described.

11.8.6.5 IC FETCH AS A FUNCTION OF IC FIG. 226

In FIG. 226, four AND-circuits 1-4 each generate signals on corresponding lines; FUNC IC IC AFE, FUNC IC IC BFE, GS FUNC O, and GS FUNC 1. Each of the AND-circuits 1-4 is operative only in response to a signal on the ID AB REG EMPTY. In addition, the AND-circuits 1 and 2 are operative only during TON T2. The AND-circuit 1 will operate when gate select bit 20 is 0 as indicated by a signal on a NOT GS PRE LCH 20 line, and the AND-circuit 2 will operate when gate select bit 20 is a 1 as indicated by a signal on a GS PRE LCH 20 line. The AND-circuits 3, 4 operate directly in response to the 0 or 1 condition of the GS register so as to indicate that the gate select function (that is, the status of bit 20) is either 0 or 1, respectively.

11.8.6.6 AB REGISTER EMPTY CIRCUIT FIG. 225

The signal on the ID AB REG EMPTY line is generated in FIG. 225 by an AND-circuit 1 at all times other than during an execute operation due to the requirement of a signal on a NOT XEQ OP LCH line. The AND-circuit 1 also responds to an OR-circuit 2 which in turn is operated by any one of three AND-circuits 3-5. The AND-circuits 3 and 4 require a signal on a GS PRE LCH 21 line, and the AND-circuits 4 and 5 require a signal on a GS PRE LCH 22 line. The AND-circuit 3 recognizes the case where bits 32- 63 of either the A register or the B register are going to be read out (as illustrated more clearly in FIG. 73) so that anything other than an RR instruction will exhaust the register from which the instruction is being read. The AND-circuit 5 recognizes the case where the instruction is being read out of bit 16 through 47 of the A register or the B register, and if it is an SS instruction it will exhaust the A or B register because a second fetch which is effective to present bits 48 through 63 of that register (and also redundantly present bits 32 through 47) will completely exhaust the register. The AND-circuit 4 senses the case where bit 48 of the A register through bit 15 of the B register, or bit 48 of the B register through bit 15 of the A register is being read out, and thereby will exhaust either the A or the B register, respectively. Thus, the AND-circuits 3-5 recognize conditions when the AB registers will be exhausted, and provided that other than an execute operation is being performed, the AB register must be considered to be empty by generating a signal on the ID AB REG EMPTY line. This line is combined with the circuitry (previously described) in FIG. 226 to determine which register is empty so that a fetch can be instituted as a function of the conditions in the A and B register with respect to a particular instruction being extracted therefrom.

11.8.7 IC RECOVERY FIG. 222 AND FIG. 223

In FIG. 222 an OR-circuit 1 generates a signal to turn on the IC recovery circuits on a TON IC RCVY line. The OR-circuit 1 can respond to an AND-circuit 2 or to signals on any one of the following lines: IE TON RCVY, IRPT TO RCVY 1, or IRPT TO RCVY 2. The AND-circuit 2 is operative when the maintenance console requires the setting of the instruction counter when the K register is loaded as indicated by signals on the MC SET IC line and on the J LOADED LCH line. The output of FIG. 222 is utilized in FIG. 223 as input to an AND-circuit 3 which, together with a controlled A clock pulse on an AC line will cause an OR-circuit 4 to set a latch 5. The OR-circuit 4 is also responsive to a scan input thereto. A latch 5 generates a signal on a IC RCVY line and also causes a bipolar latch 6 to be set at not LC time so as to generate a signal on a IC RCVY LCH line. The latch 5 is reset by an OR-circuit 7 in response to a CPU RST, or in response to an AND-circuit 8 which is operative at A time due to a running A controlled clock pulse on the AR line when there is concurrently present thereto a pulse accept signal on a P-ACC line and the output of an OR-circuit 9. The OR-circuit 9 senses that an IC fetch request has been made for the A register or for the B register in dependence upon signals on the IC AFE LCH line or on the IC BFE LCH line. Thus, IC recovery can be initiated by the conditions in FIG. 222, and will be turned off when a pulse accept signal has been received for an A or B register IC fetch.

11.8.8 IOP LOADED FIG. 224

A signal is generated on a IOP LOADED line in FIG. 224 by a latch 1 which is set by an OR-circuit 2 in response to either one of two AND-circuits 3, 4 both of which are operative only at not B time as indicated by a signal on a BC line. The AND-circuit 3 operates in response to an AND-circuit 5 which senses the fact that both the A register and the B register are loaded. The AND-circuit 4 requires a concurrence of a signal indicating that a complete instruction is contained in the AB registers, said signal appearing on the PD COND IOP LOADED line, together with the output of an OR-circuit 6. The OR-circuit 6 responds to either of two AND-circuits 7, 8 in dependence upon AB loaded with a not bit 20 or B being loaded with a bit 20. Thus, the AND circuit 3 senses the case where both A and B are loaded, and the AND-circuit 4 senses the case where one of the registers is considered to be loaded, and the OR-circuit 6 determines that it is either the A or the B register as called for by the condition of gate select register bit 20.

11.8.9 A-B LOADED FIG. 227

In FIG. 227, a signal indicating that the A register is loaded is generated on a A LOADED line by a latch 1 which is set by an OR-circuit 2 in response to a scanning signal on a SCAN IN A LOADED line, or in response to an AND-circuit 3. The AND-circuit 3 is responsive to a latch 4 which is set by an AND-circuit 5 at not LR time provided that there is a signal present on a SEL A line. The latch 4 will be reset at the start of each LR time, and immediately thereafter will again be set so long as the signal is present on the SEL A line. The AND-circuit 3 responds to the latch 4 at A time due to the presence of a signal on a AR line. The A LOADED signal at the output of latch 1 is used to set a bipolar latch 6 at not LR time so as to provide a signal on a A LOADED LCH line. The latch 1 is reset by an OR-circuit 7 in response to either one of two AND-circuit 8, 9 the AND-circuit 8 operates only at A time due to the presence of a controlled A clock signal on the AC line, and also requires the presence of either a recovery turnoff of A loaded or the combination of turn on T 2 with GS function 0 as indicated by signals on the corresponding inputs to a pair of OR-circuits 10, 11. Thus, if there is a signal on the RCVY TOF AB LD line, then both the OR-circuits 10, 11 are satisfied so that with an AC signal, the AND-circuit 8 can set the latch 1. On the other hand, if a signal is present on the TON T2 line, and a signal is also present on the GS FUNC 0 line, then the OR-circuit 10 or 11 are again both satisfied so that the AND-circuit 8 can operate at A time. The AND-circuit 9 is operative at A time due to the presence of an A running clock pulse on the AR line provided there is a signal on a TOF A LOADED line from an OR circuit 12. The OR-circuit 12 may be operated by an AND-circuit 13 which is set when a successful branch is memorized provided H register bit 20 is 0 and there is no A advance from the BCU. This is brought about by application of signals on the following lines; BR M LCH, NOT H 20 LCH, BR SUCC LCH, TSTS CMPLT LCH, and NOT A ADV. The OR-circuit 12 may also be operated by another OR-circuit 14 which is responsive to either one of two AND-circuits 15, 16, each of which in turn requires an input from a further AND-circuit 17. The AND-circuit 17 is similar to the AND-circuit 13 except that it requires a bit in H register position 20, and an indication of a branch + 1 fetch; thus the AND-circuit 17 relates to fetching the next successive storage word following the storage word containing the instruction to which a branch may be effected. The AND-circuit 17 requires signals on the BR SUCC LCH, TSTS CMPLT LCH, NOT A ADV, H 20 LCH, and BR + 1 LCH lines. In addition, the AND-circuit 15 requires a pulse accept signal on the P-ACC LINE, and the AND circuit 16 requires a signal on the BR + 1 M LCH line. Whenever the OR-circuit 14 causes generation of the TOF A LOADED signal, it will cause an AND-circuit 18 to generate a signal on the BR TON IC AFM line provided that there is no interrupt reset as indicated by a signal on the NOT IRPT RST line. The AND-circuit 18 therefore indicates that an A fetch for a branch operation has been initiated, but has not yet been terminated due to the fact that an advance signal has not yet been received from the BCU heralding the approach of data returning from storage.

A plurality of circuits 19 are provided for the B register, and, although not shown in detail in FIG. 227, comprise circuitry identical with the circuit 1-18 which relate to the A register.

11.8.10 J LOADED CIRCUIT FIG. 191

At the top of FIG. 191, an AND circuit 1 is responsive to a signal from the E unit on the J LOADED line which will cause a latch 2 to be set immediately following its reset at the start of HL time so long as the signal remains present. This causes the latch 2 to generate a signal on a J LOADED LCH line for use within the I unit. Whenever the signal disappears from the J LOADED line, then the AND-circuit 2 will remain reset upon its being reset at the start of not L time.

The signal on the J LOADED LCH line is applied to an AND-circuit 3 in FIG. 191 which, when energized by a signal on the TSTS CMPLT LCH line will cause an OR-circuit 4 to generate an I unit turnoff for J Loaded on the I TOF J LD line. The OR-circuit 4 is also responsive to signals on a IRPT RST J LOADED line, the IE TOF J LOADED line, and the IC RCVY LCH line. Thus, I unit turnoff J loaded can be caused by test complete when J is loaded, by interrupts reset of J, by the IE unit turning off J, or by an IC recovery. The signal on the IC RCVY LCH line is also applied to an OR-circuit 5 which is responsive as well to a signal on the TON IC RCVY line, so that either during the start of an IC recovery or after the IC recovery has been manifested in the latch, the OR-circuit 5 will generate a signal to turnoff AB loaded on the RCVY TOF AB LD line. The IC RCVY LCH line can also apply to an OR-circuit 6 which generates a signal for blocking the turn on of J loaded on a BLK TON J LD line. The OR-circuit 6 is also responsive to test complete, or branch handling of A or B as manifested by signals on the TSTS CMPLT LCH, BR CANC A LCH, and BR CANC B LCH lines.

11.8.11 AB FETCH, LOAD AND DECODE ADD 1, 2 FIG. 228 AND FIG. 229

In FIG. 228, an OR-circuit 1 responds to signals on the IC AFM LCH line or on the A LOADED line to generate a signal on a IC AFM OR A LD line; this signal is complemented by an inverter 2 which generates a signal on the NOT IC AFM OR A LD line. Similarly, an OR-circuit 3 generates a signal on a IC BFM OR B LD line and causes an inverter 4 to generate a signal on a NOT IC BFM OR B LD line.

The signals generated in FIG. 228 are utilized in FIG. 229 to indicate that the related register (A or B) is either loaded or about to be loaded, or it is not. This, together with bits 20-22 of the instruction counter register (ICR) is utilized to determine what fetching ought to take place, as indicated in section 11.5.5 which comprises a chart of IC fetch address generation. In FIG. 229, a plurality of AND-circuits 1-6 recognize the condition set forth in the chart described in Section 11.5.6. The AND-circuits 1-6 each relate to a particular portion of the chart, certain simplifications being obtainable due to symmetry within the chart. The AND-circuit 1 sense a response to signals on the IC AFM OR A LD line and on the NOT IC BFM OR B LD line recognizes the case where A is not empty but B is empty and therefore represents the expression NOT AE & BE. This condition, together with ICR bit 20 being a 0 as indicated by a signal on a ICR NOT 20 line will cause an OR-circuit 7 to generate a signal on the DECODE ADD 1 line, which is equal to a controlled input into incrementer bit 20. This is verified by reference to the upper portion of the third section of the chart, wherein a control input to bit 20 is indicated for all values of ICR bits 21 and 22 provided that ICR bit 20 is a 0.

The AND-circuit 2 responds to signals on the IC BFM OR BLD line and on the NOT IC AFM OR A LD line together with a signal on the ICR 20 line which is equivalent to the upper portion of the first section of the chart of Section 11.5.5 and relates to the expression AE & NOT BE, which indicates that A is empty and requires a fetch, but B is not empty and does not require a fetch. Examination of this portion of the table shows that a DECODE ADD 1 (CTRL 19) should be generated only when bit 21 of the ICR is a 1, and not when bit 21 of the ICR is 0; however, since the fetches which relate to bit 21 of the ICR being 0 are redundant fetches, it is immaterial what the inputs to the incrementer are.

The AND-circuit 3 responds to a signal on the NOT IC AFM OR A LD line and therefore represents any AE condition shown in the chart, without regard to BE or not BE. This AND circuit also responds to a signal on the ICR 20 line, and to an AND-circuit 9 which recognizes ICR 21 and ICR 22. This means the AND-circuit 3 relates to the lowermost role of the first and second sections of the table. The AND-circuit 4 also responds to the AND-circuit 9, but is responsive to a signal on the NOT IC BFM OR B LD line and to a signal indicating that ICR bit 20 is a 0. The AND-circuit 4 therefore specifies the bottom row of the upper portions of the second and third portions of the chart of Section 11.5.5.

The AND-circuit 5 recognizes a NOT AE condition due to the presence of a signal on the IC AFM OR A LD line, and also recognizes that both bits 20 and 21 of the ICR equal 1. This specifies therefore the bottom two rows of the rightmost two portions of the chart of Section 11.5.5. Thus, the AND-circuit 5 will cause the OR-circuit 8 to generate a signal on the DECODE ADD 2 line which corresponds to the fact that a controlled input to bit 19 is called for in this portion of the chart.

The AND-circuit 6 represents a NOT BE condition due to the presence of a signal on the IC BFM OR B LD line concurrently with bit 21 and not bit 20 of the ICR This represents the lowest two rows of the upper half of the first (leftmost) and last (rightmost) portions of the chart of Section 11.5.5 which calls for a control input to bit 19 of the ICR which is equivalent to the DECODE ADD 2 output of the OR-circuit 8. Thus, each of the situations which are not redundant in the chart of 11.5.5 are accounted for by the circuits 1-8 of FIG. 229.

11.8.12 OPERAND FETCH LATCH FIG. 215

In FIG. 215, an operand fetch signal is generated on a OPF line by a latch 1 which is set by an OR circuit 2 in response to a scan signal on the SCAN IN OPF line, or in response to an AND-circuit 3 which is operated at A time in a cycle with TON T2 present, when the instruction is within the class of instructions which require a fetch as indicated by a signal on the ID FTCH CL line. The latch 1 is reset by an OR-circuit 4 in response to either one of two AND-circuits 5, 6 or in response to a CPU reset signal on the CPU RST line. The AND-circuit 6 is operative at A time in response to a signal on the IRPT RST line. The AND-circuit 5 responds at A time to the combination of ACCEPT, OPFLCH, and NOT SHRD STG BLK. The latch 1 will cause the setting of a bipolar latch 7 to reflect the setting of the latch 1 at not LC time, so as to generate a signal on the OPF LCH line.

11.8.13 GSR AND PSW LENGTH GATES FIG. 230

In FIG. 230, an AND-circuit 1 is operative except during repeat instruction operations to respond to the I to E transfer when there is no interruptions to gate the GSR together with its parity bit to the ICR, and to set the length field (bits 32 and 33) of the PSW register. The AND-circuit 1 is responsive to signals on the NOT MC REPEAT INST line and on the I TO E XFER & not irpt LINE. The AND-circuit 1 generates signals on the SET LGTH PSW line and on the GT GSR P TO ICR line as well as causing an OR-circuit 2 to generate a signal on the GT GSR TO ICR line. The OR-circuit 2 is also responsive to an AND-circuit 3 which will cause the OR-circuit 2 to provide a gating signal only for the numerical portion of the GSR by providing a signal on a GT GSR TO ICR line. The AND-circuit 3 is responsive to the complete testing of a successful branch provided that an execute operation is not involved, as manifested by signals on the following lines: TSTS CMPLT LCH, BR SUCC, and NOT BD XEQ. Thus, when the tests are complete for successful branch, the GSR numerical portion is transferred to the ICR; this portion along with the parity bit of the ICR and the length for the PSW are all gated at I to E transfer by the AND-circuit 1.

11.8.14 IC HIGH-ORDER ADVANCE LATCH FIG. 187

In FIG. 187, a signal indicating that a high-order instruction counter advance is required is generated on an IC HO ADV line by a latch 1 which is set by an OR-circuit 2 in response to a scanning signal on the SCAN IN IC HO ADV line or in response to an AND-circuit 3. The AND-circuit 3 is operative at A time due to the appearance of a controlled A clock signal on the AC line during I to E transfers without an interrupt provided there is a carry from the gate select mechanism. The AND-circuit 3 therefore responds to signals on the I TO E & NOT E IRPT line and on the GSR CARRY line. When the latch 1 is set, it will cause a bipolar latch 4 to be set at NOT LC time so as to generate a signal on a IC HO ABV LCH line, this signal is used by an AND-circuit 5 to cause an OR-circuit 6 to reset latch 1 at A time. The OR-circuit 6 may also respond to a signal on the CPU RST line to cause a resetting of the latch 1.

11.8.15 BLOCKING OF IC FETCHES (BLK ICM LCH) FIG. 208

At the bottom of FIG. 208, a signal which absolutely prevents making instruction counter fetches is generated on a BLK ICM line by a latch 1 which is set by an OR-circuit 2 in response to a CPU reset signal on a CPU RST line or in response to an AND-circuit 3 which in turn is operative at A time provided there is an output of an OR-circuit 4. The OR-circuit 4 responds either to a signal on the IRPT SET BLK IC & T1 line or in response to an AND-circuit 5 which is energized with the turn on of T2 if there is a signal on the ID BLK IC rule. Thus, if the interrupt controls require the blocking of IC fetches, or if the decoded instruction indicates that operands must be fetched from storage and that therefore blocking of IC fetches must be affected with the turn of T2, then the OR-circuit 4 will cause the AND-circuit 3 to set the latch 1 at A time. The latch 1 is reset by an OR-circuit 6 in FIG. 208 in response to either one of two AND-circuit 7, 8. The AND-circuit 8 is operated at A time in response to turning on of IC recovery operations, due to the signal on the AC line and the signal on the TON IC RCVY. The AND-circuit 7 will operate at A time provided there is no signal from the OR-circuit 4 due to the effect of an inverter 9 which blocks the AND-circuit 7 in the event that the latch 1 is again being set by the OR-circuit 4. The AND-circuit 7 is also responsive to an OR-circuit 10 which can respond directly to a signal on the BR TOF BLK IC line, or to an OR circuit 11, an AND-circuit 12 or an AND-circuit 13. Each of the inputs to the OR-circuit 10 represent the end of a condition for which blocking of IC fetches has been required, thus indicating that IC fetches need no longer be blocked and that therefore the BLK ICM latch 1 is to be reset. The OR-circuit 11 actually responds to three different conditions which indicate the end of the necessity for blocking of IC fetches: first of these is manifested by a signal on the IE TOF BLK ICM line, a second is manifested by the inputs to an AND-circuit 14 on the E TOF BLK ICM line and the BR OP LCH line. A third input to the OR-circuit 11 results when an AND-circuit 15 responds to signals present on the NOT STG REQ LCH line concurrently with a signal on the VFL ENDING line.

The AND-circuit 12 recognizes that the fetch for a 1 fetch class of instructions has been accepted at the BCU as indicated by a signal on the ACCEPT line concurrently with signals on the OPF LCH AND ID one FTCH CL lines. The AND-circit 13 recognizes three different conditions which require a storage reference, when that storage reference has been made. The AND-circuit 13 responds to a signal on the ACCEPT line and to an OR circuit 16; the OR-circuit 16 is responsive to any one of three different conditions which include: an E unit condition or an IE unit condition which block the turning on of the T2 sequence in the I unit, the condition ending as soon as the accept signal is received; the other condition is the fact that VLF operation is ending, and that an accept signal has been received for the final operation thereof. The OR-circuit 16 thus responds to signals on the E TOF BLK T2M ON ACC, IE TOF BLK T2M ON ACC, and VFL ENDING lines. The block ICM signal which is generated by the latch 1 on the BLK ICM line is utilized to set a bipolar latch 17 at not L time so as to generate a signal on the BLK ICM LCH line.

All of the various conditions which are utilized to set and reset the block ICM latch are described in detail with respect to the Block IC Rule in Section 5.3.4.7. However, these conditions are not necessarily apparent in FIG. 208 due to the fact that certain of these conditions are utilized to generate specialized lines in other parts of the systems, such as the line E TOF BLK T2M ON ACC, and E TOF BLK ICM, which are generated in the E unit, and other signals of that kind generated in other parts of the system.

11.8.16 IOP SETTING CONTROL FIG. 199

In FIG. 199, a control which causes the setting of the IOP register from the AB registers is generated on a SET IOP line by an OR-circuit 1 in response to either one of two AND-circuits 2, 3, or, in response to a signal on the TON T1 line. Thus, as described in Section 5.4.0.0, in relation to instructions sequencing, and in other sections thereunder, the IOP register is set during the first T1 cycle of an instruction sequence, which means that the setting of IOP is the first step in establishing a new instruction handling sequence. The AND-circuit 2 is utilized for setting IOP with the second operand addresses, which is required because IOP is only 32 bits in length, and the second operand addresses are contained in a low order syllable of an SS instruction, which means that bits 32 through 47 of the SS instruction must be brought into the IOP register after the bits 0- 31 have all been manifested and recognized. Thus, the AND-circuit 2 recognizes signals on the SS OP LCH line and on the VFL ADR LCH line so as to indicate through the OR-circuit 1 by means of the SET IOP signals to cause the remainder of the SS instructions to be brought into the IOP register. The AND-circuit 3 relates to the execute instruction, and therefore is operative only when there is a signal on the XEQ SEQ LCH line. The other requirements for loading of IOP as a result of an execute instruction is that a "good" T1 cycle obtained as indicated by signals on the T1 LCH line and on the NOT TON T2 line. Additionally, a complete instruction must be available for loading into IOP as indicated by the signal on the IOP LOADED line.

11.8.17 ENABLE IC FETCH FIG. 231

In FIG. 231, a signal which enables IC fetches is generated on a EN IC FTCH line by an OR-circuit 1 in response to either one of two AND-circuits 2, 3, each of which may operate only if it is not blocked because of shared storage usage (a feature which may be incorporated into a system of this embodiment, but which is not in fact shown in detail; therefore, the NOT SHD STG BLK line is illustrative merely, and can be ignored in this embodiment). The AND-circuit 2 will operate the OR-circuit 1 whenever the block ICM latch is not on as indicated by a signal on a NOT BLK ICM LCH line. The AND-circuit 3 recognizes that a conditional branch operation has been indicated, but that after completion of the tests to determine whether or not the condition has been met, it has been determined that the condition has not been met so that the branch is unsuccessful. This is indicated by signals on the TSTS CMPLT LCH line and on the NOT BR SUCC LCH line. The output of the OR-circuit 1 is also applied to an inverter 4 to operate an OR-circuit 1 is also applied to an inverter 4 to operate an OR-circuit 5 in the event that there is no EN IC FTCH signal. Then the OR-circuit 5 will generate a signal on the BLK IC OR ICM line. The OR-circuit 5 may also be operated by an AND-circuit 6 if, during the turn on of T2, the instruction being decoded indicates that blocking of IC is required as indicated by signals on the TON T2 line and on the ID BLK IC line.

11.8.18 TURN ON OF PROGRAM STORE COMPARE FIG. 211

In FIG. 211 a signal is generated on the TON PGM STR COMP line by an OR-circuit 1 in response to either one of two AND-circuits 2, 3. The AND-circuit 2 recognizes that a storage request has been made and that comparison exists as indicated by a signal on a PSC line concurrently with a signal on a STG REQ LCH line. The AND-circuit 3 senses an execute instruction at the I to E transfer as manifested by signals on the XEQ OP LCH line, and on the I to E XFER line.

11.8.19 AB FETCH LATCH FIG. 194

In FIG. 194, a signal indicating the ICR bit 20 status with respect to AB fetches is generated on an AB FTCH LCH line by a latch 1 which is set by an OR-circuit 2 in response to any one of four AND-circuits 3-6. Whenever fetching is to be to the B register, as if the ICR was bit 20 in a normal fetch, then the latch 1 will be set; at other times, the latch 1 will be reset. A function of the various AND-circuits 3-6 is to affect the foregoing purpose. The AND-circuit 3 recognizes the case where A does not require a fetch (NOT AE in the chart of Section 5.3.4.5 which relates to IC fetch address generation). Whenever the ICR bit 20 is a 1, the NOT AE condition causes fetching to the B address as shown in the chart of Section 5.3.4.5. This is sensed by the AND-circuit 3. The condition of not AE and BE is sensed by the AND-circuit 4, and this always causes fetching to the B register as shown in the chart of Section 5.3.4.5. The AND-circuit 5 recognizes the BE condition with ICR bit 20 equal to a 1 and ICR bit 21 equal to a 0. These conditions always result in a fetch to B as shown in the second portion, lower half of the chart of Section 5.3.4.5. The AND-circuit 6 recognizes the BE condition with ICR bit 20 equal to 0 and ICR bit 21 equal to 1; this always causes a fetch to B as indicated by the lowest two lines of the upper half of the two center portions of the chart of Section 5.3.4.5. Thus, the AND-circuits 3-6 recognize cases within the chart of Section 5.3.4.5 which require a fetch to the B register, and any one of these AND-circuits will cause the OR-circuit 2 to set the latch 1 to thereby call for a fetch to the B address when the latch is set, and a fetch to the A address when the latch is reset.

12.0 BRANCHING

12.1 BRANCH OPERATIONS

12.1.1 INTRODUCTION TO BRANCH CONTROLS

In this system, branch fetches (i.e., fetches of instructions which are themselves the subjects of branch instructions) are made at TON T2 in the same way as are operand fetches. For branch fetches, however, return addresses are generated for both the J register and the A register or the B register, whichever is appropriate to the branch-to address: if bit 20 of the address is 0, the fetch is returned to A; if bit 20 of the address is 1, the fetch is returned to B.

Since two instruction buffer registers (A, B) are provided, branch instructions also initiate a fetch to fill the second buffer. This fetch, which is obtained from the storage location following the location of the subject instruction, is called the branch-plus-1 (BR + 1) fetch. The address for this fetch is computed during T2 of the branch instruction. The BR + 1 fetch request is normally made at the I to E transfer. A return address for this fetch is generated for the register of the AB buffers opposite to the register designated for the branch fetch.

At some predetermined time of the branch execution a tests complete (TSTS CMPLT) latch is turned on. During this cycle a branch successful (BR SUCC M) line attains a value according to whether or not the branch was successful.

If the branch operand returns before TSTS CMPLT of any branch, the operand is inhibited from gating into the AB register; but in any case, the branch operand is returned to the J REG. If a successful branch is detected during TSTS CMPLT, and the branch operand has already been loaded into the J REG, the branch operand in the J REG is then gated to the proper half of the AB register by TSTS CMPLT. If the branch operand returns after TSTS CMPLT has been turned on, the returning operand is gated into the proper register of the AB buffers if, and only if, the branch is successful; if not, the operand is put to no use whatever.

The branch + 1 fetch is always made at a time late enough so that the operand returns after TSTS CMPLT has been turned on. If the branch is successful, the BR + 1 operand is gated into the appropriate half of the AB register upon its return. If the branch is unsuccessful the BR + 1 operand is blocked upon its return, and in fact is put to no use whatever.

If a branch is unsuccessful, normal processing of the next instruction effectively starts at the same time as TSTS CMPLT is turned on. If a branch is successful, the subject instruction effectively starts as soon as the instruction is available in the AB register. During TSTS CMPLT of successful branches, the gate select register is updated to the subject address, and the ICR is then set on the cycle following TSTS CMPLT.

The following sections contain detailed discussion of the branch fetch, the branch-plus-1 fetch and the methods of terminating successful and unsuccessful branches. Certain features unique to each branch are also discussed when these features have an impact on the aspects of branching which are being discussed.

For the three RR format branches Branch on Condition (BCR), Branch and Link (BALR), and Branch on Count (BCTR) no branch is ever made if the R2 field is zero. If the R2 field is zero in a BCTR instruction, the E unit is utilized to decrement the contents of the general register specified by R1. If the R2 field is zero in a BALR instruction, the E unit is utilized to store the right half of the PSW in general register R1. If the R2 field is zero in a BCR instruction, the IE unit is utilized to perform a NO OP. In all of these, the branch unit is not started and no branch fetches are made. Therefore, these instructions are not considered to be branches when R2=0, in the following sections.

The Execute instruction (XEQ) is processed by branch controls and, therefore, is included whenever a general reference to "branches" is made.

In the following sections, reference is made to a number of figures which show by examples how exemplary branch situations are treated. Since there are so many possible variations on branches, no attempt is made to show every one. The figures included are intended, however, to show the significant features of branching and therefore FIG. 235 through FIG. 236 should be referenced in conjunction with these sections.

12.1.2 FETCHES

12.1.2.1 BRANCH FETCH

During T1 of any branch instruction, a branch address is computed in the addressing adder (AA). For the RR branches (BALR, BCTR, and BCR) this address is equal to the contents of general register R2. For the RX branches Branch and Link (BAL), Branch and Count (BCT), Branch on Condition (BC) and Execute (EX) this address is equal to the contents of general register X2 plus the contents of general register B2 plus the D2 field. For the RS branches Branch on Index High (BXH) and Branch on Index Low or Equal (BXLE) this address is equal to the contents of general register B2 plus the D2 field.

At TON T2 the branch address is set into SAR and the H REG and a normal fetch request is made to the BCU. As is done for all TON T2 operand fetches, OPF (operand fetch) is turned on (FIG. 215). The sequence control called branch op (BR OP) is also turned on at this time by TON T2 together with ID BR OP (FIG. 235) OPF, which stays on until an ACCEPT is received, and generates a return address for the J register. BR OP generates an AB return address (FIG. 216). The BCU examines SAR 20 and sets a return address for A if SAR 20 = 0 or a return address for B if SAR 20 = 1, as for all instruction fetches. BR OP does much more than provide a return address for the branch fetch. It is the status trigger which indicates to the controls that a branch is taking place, and therefore enters into the logic in numerous places. BR OP remains on until TSTS CMPLT is turned off (FIG. 235)

When the accept is generated for the branch fetch, BR M is turned on (FIG. 237). The trigger is set by an AR clock. This trigger is turned off by either the branch fetch word returning or a turn off of TSTS CMPLT, which is in response to an unsuccessful branch, whichever occurs first.

The principal function of BR M is to indicate to the branch controls during TSTS CMPLT whether or not the branch fetch has been returned. When BR M is on, the branch word has not returned, and when BR M is off, the word has returned.

12.1.2.2 Branch-plus-Fetch

At the I to E transfer of most branches a BR + 1 fetch request is made unless there is an interruption. The address for this fetch is generated during T2 by gating the H register (which contains the branch address) into the incrementer and adding one into position 20. The result is placed into SAR on the I to E transfer.

There are three cases where the BR + 1 fetch request is not made at the I to E trnasfer of a branch instruction. These cases follow:

a. If the system is being single cycled, the BR + 1 fetch request is not made by the I to E transfer because there is no provision for buffering a second operand. Therefore, the BR + 1 fetch is not made until TSTS CMPLT has been turned on, and then not at all unless the branch is successful.

b. In the branch on condition instructions BCR and BC, the BR + 1 fetch is not made at the I to E transfer if the condition register is to be set on the A clock of the E time of the previous instruction.

In this case BR + 1 fetch is made by TSTS CMPLT if (and only if) the branch is successful. The BR + 1 fetch request is delayed one cycle in this case to wait until the condition register is correctly set. The one cycle penalty possibly paid in the BR + 1 fetch for successful branches is greatly outweighed by the gain in not making the BR + 1 fetch for unsuccessful branches.

c. Also in the instructions BCR and BC, the BR + 1 fetch is not made at the I to E transfer if the compare between the condition register and BR 1 (BOP R1 field) indicates no branch. In this case the BR + 1 fetch is never made.

For all cases the BR + 1 fetch cannot return to the CPU until TSTS CMPLT is on for at least one cycle. This is so because TSTS CMPLT is turned on at least by the third cycle of E time, and storage words are returned no sooner than four cycles after a request is made.

At the same time as a BR + 1 fetch request is made the sequencer BR + 1 E is turned on. When an accept is received for this fetch the sequencer BR + M is turned on. When the BR + 1 operand returns, BR + 1 E is turned off by the advance. Together, BR + 1 E and BR + 1 M indicate the status of the BR + 1 fetch at all times, in the same fashion as IC AFE and IC AFM. In certain cases, such as unsuccessful branches, these sequencers are turned off before the fetch is completed. This is done whenever the sequencers no longer perform a useful function. Where BD BRANCH ON COND is the branch on condition decode line from BOP, E UNIT SET COND REG is the line generated by the E unit to set the condition register, and BRANCH ON COND OK indicates that the compare between the condition register and BR 1 is satisfied.

The logic for turning on BR + 1 E is: BR + 1 E TON = BR + 1 FTCH REQ (I TO E) + TSTS CMPLT LCH BR SUCC LCH BR + 1 M LCH BR + 1 E LCH

The logic for turning on BR + 1 M (with an AR CLK) is: BR + 1 M TON =(BR+ 1 E LCH). PULSED ACCEPT

The complete logic for a BR + 1 fetch request is: BR + 1 FTCH REQ = (BR + 1 FTCH REQ (I TO E)) + (BR + 1 M LCH. TSTS COMPLT LCH. BR SUCC LCH) + (BR + 1 M LCH BR + 1 E LCH. TSTS CMPLT LCH)

Examination of the logic for turning on BR + 1 E shows that it is turned on whenever a BR + 1 fetch request is first made. BR + 1 M is turned on when the BR + 1 fetch is accepted.

The first term of the BR + 1 fetch request is clearly for requests made at the I to E transfer.

The very last term for BR + 1 requests maintains any branch + 1 fetches made at the I to E transfer until TSTS CMPLT or BR + 1 M is turned on. The second term for BR + 1 requests maintains the fetch request on into TSTS CMPLT if the branch is successful and if BR + 1 M is not on. The second term also initiates a BR + 1 fetch request for the cases described under (a) and (b).

For unsuccessful branches, BR + 1 E is turned off (if turned on) when TSTS CMPLT is turned off. For successful branches, BR + 1 E is turned off by BRLC LCH + XEQ SEQ LCH. BRLC is the last cycle trigger for branches, and XEQ SEQ is the final timing sequencer for the instruction XEQ. For successful branches single cycled BR + 1 E is turned off with a running clock by the advance (ADV) for the BR + 1 fetch. The logic for this turn off is BR + IE LCH. BR + 1 M LCH. (AADV. H20 + B ADV. NOT H 20). H20, which is the 20-bit of the branch address, indicates throughout the branch instructions whether a branch is being made to the A register or the B register.

BR + 1 M is turned off by BRLC LCH + XEQ SEQ LCH.

12.1.3 TESTS AND BRANCH SUCCESS

12.1.3.1 Turn On Tests Complete and Branch Success

The line BR SUCC always attains its correct value at least within a few logic levels of the turn on of TSTS CMPLT.

Since the branch successful condition is available for one cycle only in the case of the E unit branches, branch successful is memorized in the trigger BR SUCC M. This trigger is turned on by BR SUCC LCH and TSTS CMPLT LCH. The output of this trigger is OR'ed with the various branches BR SUCC. BR SUCC M is turned off by BR LC LCH + XEQ SEQ LCH. Thus, BR + 1 E, TSTS CMPLT and BR SUCC M are all turned off by the last branch cycle: either BR LC LCH or XEQ SEQ LCH.

For each branch class instruction TSTS CMPLT is turned on when the success of the branch is determined. The turn on for TSTS CMPLT is at a predetermined time for each instruction, which varies with different instructions. The methods for turning on TSTS CMPLT and for determining the success of a branch, as well as a brief description of the arithmetic done during each branch operation, is given in the following paragraphs. BAL, BALR, XEQ

See FIGS. 264-37 and 264-38

For these instructions TSTS CMPLT is turned on immediately by the concurrence of I to E TRANSFER, NOT IRPT, BR OP LCH, and NOT BD RS or (6 NOT 7); NOT BD RS or (6 NOT 7) excludes BXLE, BXH, BCTR and BCT from turning on TSTS CMPLT at this time. The branch successful condition is forced in a steady fashion by BOP decode lines for BAL, or BALR, or XEQ.

In the instructions BAL and BALR, the RH PSW is gated through the incrementer and the incrementer extender into the K REG on the first E unit cycle. The output of the incrementer is always the address of the next instruction whether there is an IC HO ADV or not. On the second E unit cycle the contents of the K REG are stored into GR (R1).

The Execute instruction is described in detail later in this chapter. BCT, BCTR, BXH, BXLE

See Charts 39 and 42 in FIG. 264.

TSTS CMPLT is turned on by BR OP LCH AND'ed with a line from the E unit called E TON TSTS CMPLT. This line, which is latched, is generated by the first E unit cycle of BCT and BCTR, or is generated by the second E unit cycle of BXH and BXLE. BR OP LCH is included to prevent TSTS CMPLT being turned on during BALR (R2=0).

On the A clock with which TSTS CMPLT is turned on, the E unit turns on the ELC trigger; if the branch is successful, E BR SUCC appears at the same time. ELC and E BR SUCC are used in the branch controls to generate a branch successful condition.

In BCT and BCTR, the E unit tests for a value of ONE in general register R1, and also subtracts one from general register R1. If the register does not contain a value of one, the branch successful line is energized during the next cycle (ELC). The result of the subtraction is also placed back into general register R1 during ELC.

In the instructions BXH and BXLE, the operands in GR (R1) and GR (R3) are added in the main adder (MA) during the E unit first cycle. At the same time, GROUT gates out operand GR (R3 or 1). During the second E unit cycle, the sum is compared to GR (R3 or 1). If the sum is greater, then the E branch successful line is energized during the next cycle (ELC) of a BXH. If the sum is smaller or equal, then the E branch successful line is energized during EC LC of BXLE in instruction. The sum is stored back into GR (R1) on the second E cycle. BC and BCR

See FIG. 264-40 and FIG. 264-41.

TSTS CMPLT is turned on by the same logic for these instructions as for BAL, BALR, and XEQ. The branch successful line for these instructions is energized by BD BR ON cond and COND BR OK. COND BR OK is generated by a successful comparison of the R1 field of BOP with the setting of the condition register of the PSW, as shown in FIG. 196.

12.1.3.2 TURN OFF OF TESTS COMPLETE

In a normal unsuccessful branch, TSTS CMPLT is turned off within one cycle. The actual turnoff is achieved by the combination of: TSTS CMPLT LCH and NOT BR SUCC LCH. By turning off TSTS CMPLT immediately in unsuccessful branches, the execution of the branch is terminated as rapidly as possible.

In a successful branch, TSTS CMPLT is not turned off until at least one half of the AB register is loaded with the subject (or branch-to) address and the BR + 1 fetch has been accepted. The logic for turning off TSTS CMPLT for a successful branch is the combination of BR OPER RET and TSTS CMPLT LCH where BR OPER RET (operand return) equals (see FIG. 238) : A ADV and NOT H REG 20 or B ADV and H REG 20, or NOT BR M LCH , together with BR + 1 E LCH and ACCEPT, or BR + 1 M LCH. This reset is called RST TSTS CMPLT

When TSTS CMPLT is turned off, BR LC (FIG. 244) is turned on for one cycle to complete the instruction. In the case of XEQ, the sequencer XEQ SEQ LCH (FIG. 245) is turned on in place of BR LC, to permit continued processing of the Execute instruction.

12.1.4 FETCH RETURNS

12.1.4.1 Branch Return

For purposes of making this discussion easier, it is assumed in this section that the subject (or branch-to) address contains a ZERO in position 20, indicating a return to the A register from an EVEN storage unit.

In handling the return of branch and BR + 1 fetches, as in handling the return of IC fetches, advantage is taken of the address interlock in the BCU. If a fetch with ZERO in address position 20 is outstanding (i.e., the ACCEPT has been generated but the advance (ADV) has not), then the EVEN storage is BUSY and a second fetch with zero in address position 20 will not be accepted by BCU before an advance is generated for the first fetch. The same interlock exists for fetches with a ONE in address position 20. The effect of this interlock is to insure that two fetches to the same half of the AB register are not outstanding simultaneously. Therefore, the problem of identifying a returning fetch is considerably simplified.

For example, if H 20=0, BR M is on, and an A ADV is received, the word returning is necessarily the BR fetch. If the address interlock did not exist, the word returning in this case might be either an IC fetch to A or an earlier branch fetch to A.

If the branch fetch returns either before or at the same time as TSTS CMPLT is turned on, the operand is returned to the J register only. J ADV gates the returning operands into the J REG unconditionally. J LOADED is turned on by J ADV because no block is generated by the branch controls.

The branch operand is not gated into the A register if TSTS CMPLT is not yet on. This can be seen by examining the logic for setting A register in FIG. 247 and FIG. 77.

H 20 is bit 20 of the H register. A ADV is the advance given upon return of a word to A from storage. BR CANC A is a trigger used for cancelling branch fetches to A when the branch is unsuccessful.

The expression for setting the A register (FIG. 77) is also latched and then used to set A LOADED (FIG. 227).

This logic, which may seem very complicated, is in its present form because of the necessity to identify returning fetches. It is because of these circuits that all legal combinations of IC fetches, BR fetches, and BR + 1 fetches are correctly returned to the AB register. Examples, such as successive, unsuccessful branches, or IC fetches followed by branch fetches, will illustrate certain interesting situations.

Before TSTS CMPLT is turned on, either the AND-circuit 6 or the AND-circuit 7 in FIG. 247 might cause the A register to be set. However, BR M is necessarily on if a branch fetch is outstanding, and since it is assumed that the branch is to A, H 20 should be 0. Therefore, H 20 blocks AND 5, and, NOT BR M blocks AND 7, so that the A register is not loaded before TSTS CMPLT is turned on during branches.

After TSTS CMPLT is turned on, the action taken upon a returning branch fetch depends upon the success of the branch. It can be seen that the last half of the expression to set A cannot be satisfied at this time because H 20=0 (blocking ANDs 5 and 6) and TSTS CMPLT is on (blocking ANDs 5 and 7 in FIG. 247. If the branch is unsuccessful, then the A register clearly cannot be set by a returning branch operand during TSTS CMPLT. If the branch is successful, BR CANC A is necessarily off because the branch success latch is on when TSTS CMPLT arrives, and because there is an A ADV since the fetch to A has been accepted. (See FIG. 246). Therefore, the combination of A ADV and TSTS CMPLT (FIG. 247) and branch success from I J or K (FIG. 77) gates the returning word into the A register.

If the branch is successful, and the branch operand returns before TSTS CMPLT, then the branch operand is necessarily in the J register and J LOADED is on. The combination of TSTS CMPLT, NOT H20 (FIG. 247), J LOADED and branch success from I, J or K (FIG. 77) then causes the A register to be set from the J register, since the combination of TSTS CMPLT and J LOADED (AND 6, FIG. 79) forces any quantity set into A or B to be loaded from the J register instead of from the SBO. Therefore, the J register is transferred from J to A on every AR clock until J LOADED is turned off. J LOADED is turned off by TSTS CMPLT LCH and AC, and therefore remains on for only one controlled cycle of TSTS CMPLT.

In the case of an unsuccessful branch, it is possible for the branch operand to return after TSTS CMPLT is turned off. This situation does not arise for successful branches because for this case TSTS CMPLT is not turned off until the branch operand returns. (FIG. 235).

If a branch to A is unsuccessful, then BR CANC A (FIG. 246) is turned on by NOT H 20 LCH, BR M LCH, and NOT A ADV (AND 7) together with TSTS CMPLT LCH, NOT BR SUCC LCH and an AR clock pulse (AND 3). Thus BR CANC A is turned on during TSTS CMPLT of an unsuccessful branch to A if BR M LCH indicates an outstanding branch fetch which is not in the process of being returned, as indicated by NOT A ADV. BR CANC A inhibits setting of the A register from external storage. It serves to cancel a branch fetch to A after TSTS CMPLT has been turned off. BR CANC A is turned off by an A ADVANCE and an AR CLK. Besides blocking the setting of A, BR CANC A directly prevents J LOADED (FIG. 191) which in turn prevents SEL A and hence also prevents A LOADED from being turned on by the return of the branch operand.

For a successful branch, A LOADED is reset by AND 13 in FIG. 227. This turn off now serves no useful purpose since A LOADED will necessarily be turned back before the subject instruction is unblocked.

12.1.4.2 BR + 1 Return

It is again assumed in this section that a branch to A is being made and therefore the BR + 1 fetch is to B. If a branch is successful, then the BR + 1 fetch is necessarily maintained until the fetch is accepted by BCU. This fetch request is never maintained beyond TSTS CMPLT because TSTS CMPLT does not turn off on a successful branch until the BR + 1 fetch has been accepted (though not yet returned).

If a branch is unsuccessful, then the BR + 1 fetch request is immediately dropped by TSTS CMPLT, due to lack of NOT TSTS CMPLT at AND 2, FIG. 241.

If the branch is successful and the BR + 1 fetch returns during TSTS CMPLT, then the operand is gated into the B register by the combination of TSTS CMPLT, BR SUCC, NOT BR CANC B, and B ADV. If the branch is unsuccessful, then the BR + 1 operand cannot be returned to the B register because each condition to set the B register is blocked by NOT TSTS CMPLT, NOT BR + 1 M, or NOT BR SUCC.

If the branch is successful, it is necessary to turn off B LOADED provided the BR + 1 fetch has not returned by the time TSTS CMPLT is turned off. B LOADED must be turned off because instruction execution is allowed to proceed when TSTS CMPLT is turned off. If B LOADED were not turned off, it would be possible for the system to process an old instruction contained in the B register. By "old" instruction is meant an instruction which is located sequentially after the branch instruction rather than sequentially after the subject (or branch-to) instruction .

The logic for turning off B LOADED in this case is (see FIG. 227) the combination of BR + 1 E LCH, and either BR + 1 M LCH or P-ACC. NOT B ADV, NOT H20 LCH, TSTS CMPLT LCH, BR SUCC LCH.

The second and third parts indicate that TSTS CMPLT is on for a successful branch, and the remaining four parts of this expression indicate that a BR + 1 fetch to B is outstanding.

If the branch is successful and the BR + 1 operand has not returned when TSTS CMPLT is turned off, then the trigger IC BFM is turned on in this situation by the same logic as was just described for turning off B LOADED. (see AND 18, FIG. 227 IC BFM is turned on to make the BR + 1 fetch appear as an IC fetch after TSTS CMPLT is turned off. If IC BFM were not turned on, the IC controls might attempt to refetch the B register. With IC BFM on, the B register cannot possible appear empty to the IC controls.

If a branch instruction is unsuccessful, then the BR + 1 fetch must not be allowed to enter the B register even after TSTS CMPLT. In this case, the gate for the B register is blocked by the BR CANC B trigger. BR CANC B is turned on by BR + 1 E LCH & NOT H20 LCH & (BR + 1 M LCH & NOT B ADV + PULSED ACCEPT) & TSTS CMPLT LCH & NOT BR SUCC LCH. Notice that BR CANC B is turned on only if the BR + 1 fetch has been accepted by the BCU (due to BR + 1 M LCH or P-ACC, FIG. 246) and if the word is not returning or has not returned (NOT B ADV). BR CANC B remains on to block the return of the BR + 1 fetch from setting the B register of B LOADED. When the BR + 1 fetch is returned, BR CANC B is turned off by a B ADV. The same reasoning applies to the A REG when the BR fetch is to B and the BR + 1 is to A.

12.1.5 UPDATING OF THE ICR AND GSR

The ICR LO is updated at the I to E transfer of a branch and the ICR HO is updated (if necessary) on the next cycle. This is the same as for any other (nonbranch) instruction.

If the branch is unsuccessful, the GSR is set at TON T2 of the next instruction in a conventional manner.

If the branch is successful, bits 20-22 of the branch address (H REG 20-22) are set into the GSR by TSTS CMPLT and BR SUCC, with an early B controlled clock pulse (EBC).

The GSR (exclusive of the parity), which now contains part of the branch address, is gated into ICR 20-22 by the next A clock with TSTS CMPLT LCH, BR SUCC LCH, and NOT BD XEQ. In the case of the execute instruction, the ICR is not allowed to be updated.

During BR LC of a successful branch, the H register is gated into the incrementer by BR LC and BR SUCC M. The incrementer is then gated into the incrementer by BR LC and BR SUCC M. The incrementer is then gated into ICR 0-19, 23 by BR LC LCH and BR SUCC M LCH. Along with these data bits, the three parity positions of the ICR are set from the incrementer at the same time.

12.1.6 BLOCKING

As described in Section 11.5.8, under the Pre Block IC Rule, certain branch instructions with a high probability of being successful are predecoded. The predecoding is done while the instruction is in the AB register. The predecoding is done by looking at the instruction in the AB register selected by the GSR. If the instruction decoded is a BALR, BAL(BCTR BCT, XEQ, BXH, OR BXLE,) and if IOP LOADED is present, then IC fetching is blocked. The purpose of this rule is to give these branch instructions maximum access to storage. By eliminating IC fetches before the branch, branch fetches have a much greater chance to gain access to storage without interference. The block becomes effective whenever the GSR addresses a loaded branch instruction (except BC or BCR) in the AB register. The block normally rises whenever the GSR is advanced at TON T2 of an instruction preceding a branch instruction. BC and BCR are excluded from this early block because the probability of such a branch being successful is assumed not to be high.

For all branches, BLK ICM is turned on at TON T2, and IC fetches are blocked from TON T2 of the branch. IC fetches are blocked because SAR must be available for the branch and BR + 1 fetches. BLK ICM is also turned on because branch operands are transferred through the incrementer during a branch instruction.

During TSTS CMPLT of all branches except BALR or BAL, the ICR is gated into the incrementer for an IC fetch address computation. This gating is accomplished even though BLK ICM is on. The purpose of this feature is to allow IC fetches to be made one cycle sooner after unsuccessful branches.

The proper IC fetch address is computed during TSTS CMPLT for all branches except branch and link (BAL, BALR), as is done when BLK ICM is off. TSTS CMPLT and NOT BD BAL or BALR gates the ICR to the incrementer, and enables the IC address computation logic.

If a branch is unsuccessful, and if the next instruction generates no blocks of IC fetching, the unsuccessful branch turn off of TSTS CMPLT also sets SAR from the incrementer. The same condition also generates an IC fetch (if required). The unsuccessful branch turnoff of TSTS CMPLT is also a turn off for BLK ICM (provided the next instruction is not turning BLK ICM on at the same time).

For successful branches, an IC fetch address is still computed during TSTS CMPLT, but the address is never set into SAR and no IC fetch request is made at the end of TSTS CMPLT.

If a successful branch BLK ICM is turned off by BR LC and BR SUCC M (FIG. 242 and FIG. 208) the trigger is not turned off until this time because BR LC gates the H REG into the incrementer on a successful branch. Therefore NOT BLK ICM must not be allowed to gate the ICR into the incrementer 1t this time.

Except for BXH and BXLE, T1 of the next instruction is not blocked. For BXH and BXLE, BLK T1 M is turned on at the I to E transfer for one cycle so that GROUT may gate out GR (R3 + 1). This block of T1, however, has no effect when T2 of the next instruction is turned on.

BLK T2M is turned on at the I to E transfer of all branches. This trigger is used to hold up the next instruction until the direction of the branch is known.

The times for turning off BLK T2M are chosen to insure that any fetches made by TON T2 of the next instruction are made for the proper instruction. Thus, storage is not tied up returning operands for instructions which are never executed.

For unsuccessful branches, it is only necessary to hold up T2 until the direction of the branch is known. Therefore, BLOCK T2M is turned off by the unsuccessful branch turnoff of TSTS CMPLT. For successful branches, T2 is held up an additional cycle to insure that IOP is set with the branch-to, or subject instruction. Therefore, BLK T2M is turned off by BR LC LCH and BR SUCC M LCH. Both of the turnoff's for BLK T2M directly enter the logic to allow TON T2, so TON T2 can appear as soon as possible.

12.1.7 EXECUTE SEE FIG. 264-43.

The branch fetch and the BR + 1 fetch are made for the instruction XEQ as for any successful branch. TSTS CMPLT is also turned on in a normal manner, but the sequencing after this is quite unique. The unique features are now described:

a. BD XEQ blocks TSTS CMPLT from gating the GSR into the ICR LO. The gate-in to the ICR is blocked because XEQ is not a true branch instruction.

b. XEQ SEQ is turned on in place of BR LC. The H register is not gated to the ICR HO and BLK ICM is not turned off. Since no last cycle is generated, no interrupts can be taken at this time.

c. GROUT is turned on by the I to E transfer. However, T1 is allowed to turn on. This is the only time that this situation is allowed to occur. GROUT gates general register BR 1 onto GBL. GROUT inhibits T1 from gating general register IB onto GBL. IF BR 1 0, XEQ SEQ gates GBL 24-31 into IOP 8-15 with a B clock. This gate-in is actually an "OR" GATE. The bits on GBL 24-31 are OR'ed with the bits already loaded into IOP 8-15.

d. XEQ SEQ and GROUT are turned off by IOP LOADED LCH and XEQ SEQ LCH. Thus these triggers are turned off when the subject instruction has been available in IOP for one cycle.

e. XEQ SEQ LCH and IOP LOADED LCH block the setting of IOP. Therefore, once IOP has been loaded and the GBL bits have been OR'ed into IOP, no further setting of IOP is allowed.

f. XEQ SEQ LCH and IOP LOADED LCH turn off BLK T2M. This turnoff is unique in that it does not directly enter the logic for TON T2. Thus T2 can turn on one cycle after XEQ SEQ and GROUT turn off. Thus, one T1 cycle is taken after IOP is loaded with the modified subject instruction. Since it is impossible for any other blocks to prevent T2 from turning on at this time, the T2 cycle necessarily occurs one cycle after XEQ SEQ turns off.

g. At the same time that XEQ SEQ is turned on, the trigger XEQ OP is turned on. This is a status trigger which remains on throughout the processing of the subject instruction.

Xeq op prevents any empty conditions from being generated by TON T2 of the subject instruction. This is so because control is returned to the instruction stream unless the subject of the XEQ is a branch instruction.

j. When XEQ OP is on, the invalid specification test made during T1 is modified to use H 23 instead of ICR 23. H 23 is used because the address of the subject instruction is located in the H register.

k. If XEQ OP is on and an XEQ instruction is decoded from BOP during T2, then an execute exception interrupt is taken, because an XEQ is not allowed to be the subject of an XEQ.

1. xeq op causes the GSR to be gated to the gate select adder prelatch. It also blocks the gating of the ICR to the gate select adder pre latch. Therefore, if an SS instruction is the subject instruction of an XEQ, bits 20-22 of the address of the SS instruction are properly latched at the input to the gate select adder. The VFL unit thus has access to the needed effective addresses.

m. XEQ OP and I TO E XFER turn on IC RCVY REQ. This trigger causes an IC recovery to be taken after the last cycle of the subject instruction.

n. If the subject instruction of an XEQ is a successful branch, then XEQ OP and IC RCVY REQD are turned off by TSTS CMPLT. Therefore, no IC recovery is taken after executing 1 successful branch.

12.2 BRANCH CONTROL CIRCUITS

The circuits which relate primarily to branch control are described in the following sections, and the use thereof in branch operations is described in Section 12.1 et seq. Reference should be made to other sections which are descriptive of circuits or controls that are involved in branch operations or controlled thereby, although not primarily related to branch controls or branch operations.

12.2.1 BRANCH OPERATIONS LATCH FIG. 235

At the bottom of FIG. 235, a signal which indicates a branch operation is to be performed is generated on a BR OP line by a latch 1 which is set by an OR-circuit 2 in response to scanning controls on the SCAN IN BR OP line or in response to an AND-circuit 3. The AND-circuit 3 responds to a controlled A clock signal on the AC line and to an AND-circuit 4 which is operated by the combination of TON T2 and ID BR OP. In other words, the BR OP latch can be set by scan in signal, or by a branch op indication from the IOP decode at turn on T2.

A latch 1 is reset by an OR-circuit 5 in response to a signal on the CPU RST line, or in response to an AND-circuit 6. The AND-circuit 6 responds to a signal on the AC line and to an OR-circuit 7. The OR-circuit 7 responds to signals on a IRPT RST line, or on the TSTS CMPLT & BR OP line from the middle of FIG. 235.

The signal on the RST TSTS CMPLT & E OP line is generated by an OR-circuit 9 in response to either one of two AND-circuits 10, 11, each of which is gated by a signal on the BR OPER RET & TSTS CMPLT line. The AND-circuit 10 is responsive to a signal on a BR + 1 M LCH line, and the AND-circuit 11 is responsive to signals on both the ACCEPT and BR + 1 E LCH line. Thus, the AND-circuit 10 responds to an outstanding branch +IM fetch, whereas the AND-circuit 11 responds to a fetch request for branch IE which is being accepted as indicated by the presence of the ACCEPT signal. The OR-circuit 9 therefore will permit the setting of the branch-op latch following the return of the branch operand when tests are complete provided that the branch + 1 fetch request has been accepted.

The signal on the BR OP line out of the latch 1 in FIG. 235 is utilized to set a bipolar latch 12 at the start of not L time due to a signal on the NOT LC line so as to generate a signal on the BR OP LCH line. Thus, so long as the latch 1 is set, the latch 12 will continuously be set in each cycle so as to provide the working output from the bottom of FIG. 235.

12.2.2 BRANCH M LATCH FIG. 237

Reference to FIG. 91, and more particularly to subfigures a, c and e thereof, will show that all of the branch operations cause the IOP decode circuits to generate a signal on the IE FTCH CL line which indicates that the instruction is one which requires a storage fetch in order to be properly handled. The ID FTCH CL signal causes the generation of OPF (operand fetch) in FIG. 215, which together with BR OP LCH will prepare an AND-circuit 1 in FIG. 237 for setting a latch 2. The AND-circuit 1 will not operate, however, unless there is no interrupt reset as indicated by a signal on a NOT IRPT RST line, nor does it operate until the branch fetch request has been accepted by the BCU as indicated by a signal on the P-ACC line. When all of these conditions are met, an A running clock pulse on the AR line will cause the AND-circuit 1 to operate an OR circuit 3 so as to set the latch 2. The latch 2 generates a signal on a BR M line, and this is utilized at NOT L time to set a bipolar latch 4 so as to generate a signal on the BR M LCH line. The OR-circuit 3 may also be operated by a scan in signal on the SCAN IN BR M line.

The purpose of the BR M latch is to indicate that the branch fetch has been accepted, but that it has not yet been returned. When the branch fetch storage word is returned, then the BR M latch is turned off. This is achieved by an AND-circuit 5 which is responsive to the BR OP LCH line and to a signal on the OPERAND RET line so as to operate an OR-circuit 6 at A time (due to the signal on the AR line). The OR-circuit 6 will reset the latch 2 in response to the AND-circuit 5 or in response to an AND-circuit 7 which in turn is responsive to an OR-circuit 8. The OR-circuit 8 provides an alternative method for resetting the latch 2 in the event that there is an interrupt reset, or that after the tests have been completed, the branch is found to be unsuccessful as indicated by signals on the IRPT RST and TSTS COMPLT & BR UNSUCC lines. Thus the latch 2 is set by an accepted operand fetch when branch op is on, and is reset either by interrupts, by the branch being unsuccessful, or by the return of an operand concurrently with the BR OP LCH signal.

12.2.3 BRANCH +1 OUTSTANDING CONTROLS FIG. 240

In FIG. 240, a signal indicating that a branch + 1 fetch is outstanding is generated on a BR + 1 E line by a latch 1 which is set by an OR-circuit 2 in response to a scan signal on a SCAN IN BR + 1 E line or in response to either one of two AND-circuits 3, 4. The AND-circuit 3 in turn responds to an AND-circuit 5 which generates a signal on a COND BR + 1 E FTCH line in advance of a BR + 1 E condition. The AND-circuit 5 is responsive to the absence of single cycle as indicated by a signal on a NOT SINGLE CYC MODE line, and to the presence of a signal on a BR OP LCH line. The AND-circuit 5 is also responsive to an OR-circuit 6 which in turn is operated by either a signal on a NOT ND BR ON COND & R1 NOT 15 line which indicates that a truly conditional branch on condition instruction is not involved, either because BOP decode did not indicate a branch on condition instruction, or because all of the bits are present in the R1 field (so that R1 does equal 15) such that the branch on condition instruction is unconditional, in accordance with the architectural definition of a system set forth in said copending application to Amdahl et al. The OR-circuit 6 may also be operated by an AND-circuit 7 which is responsive to a signal on the BR ON COND OK line, concurrently with a signal on the NOT E SET CR line. In other words, the OR-circuit 6 can operate whenever a branch on condition is OK and the E unit is not going to again set the condition register, or when there is no branch on condition, or if there is a branch on condition it is an unconditional branch as indicated by R1 being equal to 15. In this connection, it is to be noted that the lowermost line into the OR-circuit 6 might be read NOT BD BR ON COND & R1 NOT 15 . The purpose of the AND-circuit 5 is to predetermine that a branch + 1 fetch for a branch on condition instruction might take place at the time of the I to E transfer. Thus, the AND-circuit 3 will respond to the signal on the COND BR + 1 E FTCH line at A time of an I to E transfer provided there is no interrupt as indicated by signals on the AC and I TO E & NOT IRPT lines. The latch 1 may also be set in response to an AND-circuit 4 provided that the branch is successful, and that no branch + 1 fetch is outstanding after testing of the branch is completed, all as is indicated by signals on the BR SUCC LCH, NOT BR + 1 M LCH, NOT BR + 1 E LCH, and TSTS CMPLT LCH lines. The latch 1 is reset by an OR-circuit 9 in response to either one of two AND-circuits 10, 11. The AND-circuit 10 causes the resetting of the latch 1 when the actual BR + 1 fetch is completed, and the AND-circuit 11 causes resetting of the latch 1 when the BR + 1 fetch will become completed after branch last cycle, due to the fact that an execute op is involved as indicated by the execute last cycle sequencer, or when it is determined that an unsuccessful branch is involved after tests have been completed. The AND-circuit 11 is operative in response to a controlled A clock signal on the AC line concurrently with the output of an OR-circuit 12 which in turn responds to signals on the BR LC LCH & BR SUCC M LCH, XEQ SEQ LCH, and TSTS CMP LT & BR UNSUCC LCH lines.

The AND-circuit 10 is responsive to an OR-circuit 13 provided there are also present signals on the BR + 1 E LCH and BR + 1 M LCH lines. The OR-circuit 13 is responsive to two AND-circuits 14, 15 in dependence upon whether a fetch to A or a fetch to B is involved, respectively. The AND-circuit 14 recognizes that a fetch to A is involved by a signal on the H 20 LCH line, and it recognizes that the fetch is about completed due to the presence of a signal on the A ADV line. Similarly, the AND-circuit 15 recognizes a correct advance for a B fetch by signals on the B ADV and NOT H 20 LCH. Notice that the condition of bit 20, of the H register is opposite from that which is normally associated with either the A or the B register, respectively, due to the fact that the branch + 1 fetch will necessarily be to the opposite register which was filled by branch fetch; since the H register determines where the branch fetch will be, the advance received for a branch + 1 fetch will be received for the opposite setting of the H register. In other words, if a branch is to be, the branch + 1 fetch will be to A, but the H register indicates the branch fetch to B by presenting a 1 in bit 20. Thus, the BR + 1 E latch 1 in FIG. 240 is reset when the fetch is no longer outstanding, or during the last branch cycle, or when tests are completed and the branch is determined to be unsuccessful. The signal generated by the latch 1 on the BR + 1 E line is utilized at NOT L time to set a bipolar latch 16 so as to generate a signal on the BR + 1 E LCH line.

12.2.4 BRANCH + 1 FETCH CONTROL FIG. 241

In FIG. 241, a signal is generated on a BR + 1 FTCH line by an OR-circuit 1 in response to either one of two AND-circuits 2, 3 each of which requires a signal on a NOT BR + 1 M LCH line. The AND-circuit 2 responds to a signal on a BR + 1 E LCH line, and to a signal on the NOT TSTS CMPLT LCH line. On the other hand, the AND-circuit 3 responds to a signal on a TSTS CMPLT LCH line and to a signal on a BR SUCC LCH line. Thus, the OR-circuit 1 will operate provided that the branch + 1 latch has not been set if a branch + 1 fetch is outstanding before tests are complete, or if branch is determined to be successful after tests are complete.

12.2.5 BRANCH + 1 FETCH MEMORIZED FIG. 236

In FIG. 236, a signal indicating that a branch + 1 fetch has been accepted is generated on a BR + 1 M line by a latch 1 which is set by an OR-circuit 2 in response to a scan control signal on the SCAN IN BR + 1 M line or in response to an AND-circuit 3. The AND-circuit 3 is operative at A time due to the effect of a running A clock signal on the AR line concurrently with a pulse accept signal on a P-ACC line and a signal on a BR + 1 E LCH line. In other words, as soon as the fetch request indicated by the BR + 1 E latch is accepted by the BCU as indicated by the B-ACC signal, the latch 1 will be set so as to provide the BR + 1 M signal.

The latch 1 is reset by an OR-circuit 4 in response to a signal on a CPU RST line, or in response to an AND-circuit 5. The AND-circuit 5 is operative at A time due to a controlled A clock signal on the AC line provided there is an output from an OR-circuit 6. The OR-circuit 6 recognizes the last branch cycle either by means of a signal on the BR LC LCH line, or by means of a signal on the XEQ SEQ LCH line. The output of the latch 1 on the BR + 1 M line is used at NOT L time to set a bipolar latch 7 so as to provide a signal on the BR + 1 M LCH line.

12.2.5.1 TESTS COMPLETE FIG. 235

In FIG. 235, a signal indicating that testing of the conditions for a branch has been completed is generated on a TSTS CMPLT line by a latch 21 which is set by an OR-circuit 22 in response to a scan in control signal on the SCAN IN TSTS CMPLT line or in response to either one of two AND-circuits 23, 24 which are both operated at A time due to the controlled A clock signal on the AC line. The AND-circuit 23 relates to E unit testing of branches, due to the signal on the E TON TSTS CMPLT line, provided there is a signal on the BR OP LCH line. The AND-circuit 24 on the other hand relates only to branch and length and execute instructions due to the fact that a signal is presented on the NOT BD RS OR (B6 NOT B7) line. Thus, the branch and length and execute instructions can cause the setting of tests complete at the I to E transfer due to the presence of signals on the I TO E & NOT IRPT and BR OP LCH lines.

The latch 21 is reset by an OR-circuit 25 which may be operated by a signal on the CPU RST line, or by either one of two AND-circuits 26, 27 each of which is operated at A time due to the A control clock signal on the AC line. The AND-circuit 26 responds to the signal on the RST TSTS CMPLT & BR OP line which is generated by the OR-circuit 9 and applied to the resetting circuits for the BR OP latch 1, as well. The AND-circuit 27 is responsive to a signal on the TSTS CMPLT & BR UNSUCC line. Thus, the latch 21 can be set by the I to E transfer when the branch on condition, branch and length or execute instructions are involved, can be set by the E unit turn on of tests complete for the branch on index and branch on count instructions, and the latch 21 is reset by tests complete either when the branch is unsuccessful or when operands are fully returned. The output of the latch 21 on the TSTS CMPLT line is utilized at NOT L time to set a bipolar latch 28 thereby to generate a signal on the TSTS CMPLT LCH line.

12.2.6 BRANCH SUCCESS LATCH FIG. 192

In FIG. 192, a signal is generated on the BR SUCC LCH line by a latch 1 which is set by an OR-circuit 2 in response to any one of three AND-circuits 3-5, each of which is gated during NOT L time due to the effect of a complement controlled L clock signal on the NOT LC line. The AND-circuit 3 is responsive to E unit determination that a conditional branch, the condition for which is tested within the E unit, has been found successful as indicated by a signal on a E BR SUCC line, which is gated, timewise, by a signal which indicates the last E cycle on the ELC line. The AND-circuit 4, on the other hand, is responsive to an OR-circuit 6 which recognizes a successful branch in the I unit other than resulting from a branch on condition instruction. The OR-circuit 6 responds to signals on the BD BAL OR BALR, BD XEQ, and BR SUCC M lines to provide a signal on the BR OK line which is used to operate the AND-circuit 4, and is also used elsewhere herein. The AND-circuit 5, on the other hand, operates in response to branch on condition instructions due to the signal on the BR ON COND line concurrently with a signal on the BR ON COND OK line, which together indicate that a branch on condition instruction is involved, and that the condition has been met so that the branch will be successful. Notice that the latch 1 is reset by the signal on the NOT LC line so that the latch is always reset and immediately again set so long as one of the circuits 3-5 is providing an input to the OR-circuit 2; when none of the AND-circuits is operative, the latch will remain reset until such time as there is again a signal to the OR-circuit 2.

12.2.7 BRANCH SUCCESS MEMORIZED LATCH FIG. 242

The branch success latch which is described in the preceding section can be reset at the start at any NOT L time, and remain set unless one of the inputs thereto is maintained to cause the latch to again be set immediately after being reset. One such an input is the BR SUCC M signal applied to the OR-circuit 6 which will cause the AND-circuit 4 to set the latch 1. This signal is generated in FIG. 242 by a latch 1 which is set by an OR-circuit 2 in response to a scan in signal on the SCAN IN BR SUCC M line or in response to an AND-circuit 3. The AND-circuit 3 responds directly to the BR SUCC LCH line at the first A time following the L time in which BR SUCC is set. Thus, once the latch 1 in FIG. 242 is sent, its output is set back to the latch 1 in FIG. 192 so that the latch in FIG. 192 will continuously be set until the latch 1 in FIG. 242 is reset.

In FIG. 242, the latch 1 is reset by an OR-circuit 4 in response to a signal on the CPU RST line, or in response to an AND-circuit 5 which is operative at A time provided there is an output from an OR-circuit 6. The OR-circuit 6 recognizes the last cycle of a branch operation by means of the signals on the XEQ SEQ LCH or BR LC LCH line. The output of the latch 1 on the BR SUCC M line is utilized to set a bipolar latch 7 at NOT LC time so as to generate a signal on the BR SUCC M LCH line, which is utilized in various circuits, and is also utilized to operate an AND-circuit 8. The AND-circuit 8 recognizes the last cycle of an unsuccessful branch by means of signals on the BR LC LCH and TSTS CMPLT & BR UNSUCC lines to generate a signal which will terminate the blocking of the IC fetch latch by means of a signal on the BR TOF BLK IC M line. Thus, the BR SUCC latch in FIG. 192 is turned on by different indications of a successful branch, and in turning causes the BR SUCC M latch of FIG. 242 to turn on, which then causes the BR SUCC latch of FIG. 192 to essentially remain on until such time as the last cycle of a branch is sensed by the AND-circuit 8 in FIG. 242 which resets the BR SUCC M latch therein, thereby permitting the BR SUCC latch of FIG. 192 to remain reset in following NOT L times. Additionally, when the BR SUCC M latch is set, there will be a signal on the BR SUCC M LCH line, and when this is present at the last cycle of an unsuccessful branch, the AND-circuit 8 permits turning off of the block ICM latch.

12.2.8 BRANCH LAST CYCLE CONTROLS

The last cycle of a branch operation can be indicated either by a BR LC signal, or by a XEQ SEQ signal. The XEQ SEQ signal is utilized instead of a BR LC signal so as to permit the execute instruction to be performed in the proper fashion, and to permit terminating of the quasi branch operation which is involved with the execute instructions in a fashion similar to the termination of all branching operations, but with appropriate differences.

In FIG. 244 and in FIG. 245, the controls for generating a BR LC (branch last cycle) signal, or a XEQ SEQ signal (execute sequence) signal, as well as, the XEQ OP (execute operations) signal are shown.

12.2.8.1 BRANCH LAST CYCLE LATCH FIG. 244

The normal last cycle of a branch operation is defined by the signal on the BR LC line which is generated in FIG. 244 by a latch 1 which is set by an OR-circuit 2 in response to a scan in control signal on a SCAN IN BR LC line, or in response to either one of two AND-circuits 3, 4 each of which responds to a controlled A clock signal on a AC line concurrently with the absence of an execute instruction as determined by the BOP decode circuit which presents a signal on the NOT BD XEQ line. The AND-circuit 3 permits setting of the latch 1 at the end of an unsuccessful branch due to the signal on the TSTS CMPLT & BR UNSUCC line. On the other hand, the AND-circuit 4 is responsive to the receipt of an operand concurrently with tests complete due to the fact that it responds to a signal on the RST TSTS CMPLT & BR OP line, which line is utilized in FIG. 235 to reset the tests complete latch and the branch-op latch. Bearing in mind that a successful branch requires only the fetching of a storage word containing the subject address, and the fetching of the next sequential storage word, it is evident that a successful branch is terminated when these operands have been returned; such is the case when the signal appears on the RST TSTS CMPLT & BR OP line. In other words, the AND circuit 3 causes the last cycle of the branch as a result of the branch becoming unsuccessful, whereas the AND-circuit 4 causes the turning on of the branch last cycle as a result of a successful branch having fetched its operands and therefore branch operations being completed.

The latch 1 is reset by an OR-circuit 5 in response to a signal on the CPU RST line, or in response to an AND-circuit 6 which is operated at A time (AC line) whenever the BR LC LCH line has a signal thereon. This line is controlled by a bipolar latch 7 in FIG. 244 which is controlled in turn by the latch 1. At each NOT L time, a signal appears on the NOT LC line and causes the bipolar latch 7 to reflect the setting of the latch 1. Thus, when the latch 1 turns on at A time of some cycle, a bipolar latch 7 will be turned on approximately a quarter of a cycle later when not L time begins. This in turn will cause the resetting of the latch 1 at the following A time. When the latch 1 has been reset, the bipolar latch 7 will itself be turned off at the start of the second NOT L time.

The output of the bipolar latch 7 on the BR LC LCH line is utilized along with a signal on the BR SUCC M LCH line to cause the AND-circuit 8 to generate a signal on a BR LC LCH & BR SUCC M LCH line which indicates that a last cycle of a successful branch has reached.

12.2.8.2 EXECUTE OP AND SEQUENCE CONTROLS FIG. 245

In FIG. 245, a signal which finds an execute instruction operation is generated on a XEQ OP LCH line by a bipolar latch 1 which is set at NOT L time in response to the setting of the latch 2. The latch 2 is set by an OR-circuit 3 in response to a scan in control signal on a SCAN IN XEQ OP line, or in response to an AND-circuit 4. The AND-circuit 4 also operates an OR-circuit 5 so as to set a latch 6, the setting of which is selected in a bipolar latch 7 so as to generate a signal on the XEQ SEQ LCH line. The OR-circuit 5 is also operable by a scan in control signal on a SCAN IN XEQ SEQ line. Thus, the AND-circuit 4 will set XEQ OP and XEQ SEQ. The AND-circuit 4 is operative at A time due to a controlled A clock signal on the AC line provided there are signals on the BD XEQ and BR OP LCH lines. The actual gating of the AND-circuit 4 is dependent upon the appearance of the signal on the RST TSTS COMPT & BR OP line which indicates that the operands have been returned as in the case of other branches. It is only after the branch and branch + 1 fetches have been completed that an execute instruction differs from other branch instructions. This is caused by the AND-circuit 4 responding to RST TSTS CMPLT & BROP, rather than allowing the AND-circuit 4 of FIG. 244 to respond thereto. Thus, the AND-circuits circuits 4 in FIG. 244 and FIG. 245 are alternatives in dependence upon whether there is a NOT BD XEQ signal (FIG. 244) or a BD XEQ signal (FIG. 244).

The latch 2 in FIG. 245 is reset by an OR-circuit 8 in response to a signal on the CPU RST line, or in response to an AND-circuit 9 which responds at A time to an AND-circuit 10. The AND-circuit 10 responds to signals on the RST TSTS CMPLT & BR OP, BR SUCC LCH, and XEQ OP LCH lines.

The output of the latch 6 is fed to an AND-circuit 12 which generates a gating signal to permit gating of the BOP R1 field (BR1) into IOP after IOP has been loaded with the subject instruction so as to permit OR'ing the R1 field of the subject instruction with the R1 field of the execute instruction. The AND-circuit 12 is gated at B time by a controlled B clock signal on the BC line so as to generate a signal on the XEQ GATE line. However, in the event that the R1 field of the execute instruction is all O's then no OR'ing into IOP takes place. This is accomplished by the presence of an OR-circuit 13, the output of which is required in order for the AND-circuit 12 to operate. The OR-circuit 13 requires a signal on any one of the BR 1-bit lines 8-11.

The latch 6 in FIG. 245 is reset by an OR-circuit 14 in response to a signal on the CPU RST line, or in response to the output of an AND-circuit 15 which in turn is operated by the concurrence of signals on the XEQ SEQ LCH and NOT IOP LOADED lines.

12.2.9 BRANCH ON CONDITION AND I BRANCH SUCCESS FIG. 196

In FIG. 196, the determination of whether a branch on condition instruction is successful or not is made by an OR-circuit 1 in combination with four AND-circuits 2-5. Each of the AND-circuits 2-5 correspond to a possible setting of the condition register, which comprises bits 34 and 35 of the PSW. The AND-circuit 2 corresponds to a setting of 00, the AND-circuit 3 corresponds to a setting of 01, and AND-circuit 4 corresponds to a setting of 10, the AND-circuit 5 corresponds to a setting of 11. Assuming that the corresponding setting of the condition register is present for any one of the AND-circuits 2-5, that AND circuit will operate provided that the corresponding mask bit in the R1 field of the branch on condition instruction is a 1. For instance, if the AND-circuit 2 has signals present on the NOT CR 34 and NOT CR 35 lines, it will operate provided there is a signal on the BR 1 8-line. The other AND-circuits 3-5 operate in a similar fashion. The operation of any one of the AND-circuits 2-5 will cause the OR-circuit 1 to generate a signal on the BR ON COND OK line. This signal is applied to an AND-circuit 6 which is gated by a signal on the BD BR ON COND line so as to cause an OR-circuit 7 to generate a signal on a I BR SUCC line. The OR-circuit 7 may also respond to a signal on the BR OK line. Thus, the circuit of FIG. 196 will determine if a branch on condition instruction is successful, and provided it is, it will also cause the I BR SUCC signal to appear; if a branch on condition is not involved, the AND-circuit 6 will not operate, so that the OR-circuit 7 must rely on the BR OK signal in order to operate.

12.2.10 BRANCH CANCEL AB FETCHES FIG. 246

At the top of FIG. 246, a signal indicating that a fetch to A should be cancelled as a result of branch conditions is generated on a BR CANC A line by a latch 1 which is set by an OR-circuit 2 in response to a scan in control signal on a SCAN IN BR CANC A line or in response to an AND-circuit 3 which in turn requires an output from an OR-circuit 4. A signal is also generated on a BR CANC A LCH line by a bipolar latch 10a which is set at NOT L time in response to the setting of the latch 1. The OR-circuit 4 is responsive to any one of three AND-circuits 5-7, each of which recognizes an outstanding branch fetch to A in various stages of advancement thereof. The AND-circuits 5 and 6 are responsive to branch + 1 fetches to A as determined by the combination of signals on the H 20 LCH and BR + 1 E LCH LINES. Thus, when the branch fetch is to an odd address as indicated by H register bit 20 being a 1, the branch + 1 fetch will be an even storage and therefore relate to the A register. The AND-circuit 5 additionally responds to the BR + 1 M LCH line which indicates that the fetch has been accepted and is therefore outstanding. The AND-circuit 6, on the other hand, responds to a signal on the P-ACC line concurrently with a signal on the NOT A ADV line, indicating that branch + 1 fetch has been accepted but that the storage word has not yet commenced to transfer from storage into the CPU due to the lack of an advance signal.

The AND-circuit 7 recognizes branch fetches which have been completed due to the presence of signals on the BR M LCH line, whenever the branch relates to the A register as indicated by a signal on the NOT H 20 LCH line. If there has been no advance for the A register as indicated by a signal on the NOT A ADV line, then the AND-circuit 7 will operate the OR-circuit 4. Summarizing, the AND-circuits 5 and 6 recognize branch + 1 outstanding fetches to the A register, and the AND-circuit 7 recognizes a branch fetch to the A register which is still outstanding. An output from any one of these will cause the OR-circuit 4 to present a signal to the AND-circuit 3. If tests are completed and the branch is determined to be unsuccessful, then there will be signals present on the NOT BR SUCC LCH line and on the TSTS CMPLT LCH line, which will cause the AND-circuit 3 to respond to the OR-circuit 4 at A time due to the presence of a running A clock signal on the AR line. Thus, the cancel latch for the A register will be set when tests are completed, the branch is unsuccessful, and there is an outstanding branch or branch + 1 fetch for the A register. The latch 1 is reset by an OR-circuit 8 in response to a signal on the CPU RST line, or in response to an AND-circuit 9 which is operative at A time due to the running A clock signal on the AR line whenever an A advance signal appears on the A ADV line. At the bottom of FIG. 246, a plurality of circuits 10b provide similar control for the B register, the details of which are identical to the circuits 1-10a at the top of FIG. 246, except that B advance is involved, and the H20 latch lines are reversed.

12.2.11 BRANCH SELECTION OF AB REGISTER FIG. 247

In FIG. 247, an AND-circuit 1 determines when a branch fetch storage word is being returned to the A register in response to a signal on the A ADV line, which is permitted to gate the AND-circuit 1 provided that the branch fetch should not be cancelled as indicated by a signal on the NOT BR CANC A line concurrently with a signal on the TSTS CMPLT line. The AND-circuit 1 generates a signal on the SEL A ON SUCC BR line. The AND-circuit 1 therefore generates a signal which permits returning a storage word directly to the A register from the SBOL. The AND-circuit 2 generates a signal on the SEL A ON BR SUCC & J LD line in response to signals on the TSTS CMPLT and NOT H 20 LCH lines. The AND-circuit 2 recognizes the case where the determination of the branch is not completed at the time that the storage word is returned through the SBOL, and therefore if the A register is to be loaded it should be loaded from the J REGISTER rather than from the SBOL. An AND-circuit 3 generates a signal on the SEL A UNCOND line which indicates that the A register should be selected without regard to the success of a branch. The AND-circuit 3 responds to an advance signal from the A register when the A fetch is not cancelled as indicated by signals on the A ADV and NOT BR CANC A line concurrently with the output of an OR-circuit 4. The OR-circuit 4 responds to any one of three AND-circuits 5-7, the AND-circuit 5 and 6 providing means to permit operands which were previously requested as a result of IC fetching to be returned to the A register even though a fetch to the B register for branch purposes may have been already made. Thus, if the H register bit 20 is a 1 (signal on the H 20 line) both of the AND-circuits 5 and 6 are potentially operable. The AND-circuit 5 can operate up until the time that tests are completed (NOT TSTS CMPLT line) and the AND-circuit 6 can operate so long as no branch + 1 fetch is involved as indicated by the NOT BR + 1 M line. A branch + 1 fetch would actually be recognized by the AND-circuit 1, and any fetch after tests complete has come on with H register set to 20 must be either a branch fetch which is to go to the B register or a branch + 1 fetch which is to go to the A register. The AND-circuit 7 accounts for all nonbranch situations due to the fact that the NOT BR M line and the NOT TSTS CMPLT line must both present signals thereto in order for it to operate; thus, there could be no A advance signal at the AND-circuit 3 during a branch operation without either the branch M latch being set, or the tests complete latch being set; thus there is no danger of the AND-circuit 7 allowing the AND-circuit 3 to permit selecting A without regard to the success of a branch when branch operations are in fact involved. However, whenever branching is not being done, both the branch M latch and the tests complete latch will be off so that the AND-circuit 7 will permit operating the AND-circuit 3 thereby allowing all IC and recovery fetches to be gated unconditionally as indicated by a signal on the SEL A UNCOND line.

A plurality of circuitry 8 is provided for the B register which is equivalent in every respect to the circuits 1-7. These circuits have not been shown in detail for the purpose of simplicity.

12.2.12 OPERAND RETURN CIRCUIT FIG. 238

In FIG. 238, a signal indicating that an operand has to return from storage is generated on a OPERAND RET line by an OR-circuit 1 in response to either one of two AND-circuits 2, 3 each of which is responsive to an advance signal which relates to the current setting of H register bit 20. The AND-circuit 2 is responsive to signals on the A ADV line and NOT H 20 LCH line, whereas the AND-circuit 3 is responsive to signals on the B ADV and H 20 LCH lines.

12.2.13 CONTROL LINES COMBINED WITH TESTS COMPLETE

12.2.13.1 OPERAND RETURN FIG. 238

In FIG. 238, the signal on the OPERAND RET line is applied to an OR-circuit 4 so as to cause the AND-circuit 5 to generate a signal on the BR OPER RET & TSTS CMPLT line provided that there is a signal on the TSTS CMPLT LCH line. The OR-circuit 4 can also respond to the NOT BRM LCH line which of course will indicate that the branch operand has returned.

12.2.13.2 Branch Unsuccessful FIG. 239

In FIG. 239 an AND-circuit 6 generates a signal on the TSTS CMPLT & BR UNSUCC line in response to the concurrent presence of signals on the NOT BR SUCC, TSTS CMPLT LCH, and NOT SHRD STG BLK lines. Note that the shared storage block control will always be available to the AND-circuit 6 in this embodiment which includes no storage sharing provisions whatever, that line being applied to the AND-circuit 6 for exemplary purposes only.

13.0 I UNIT EXECUTION

I unit execution comprises the performance of actual data manipulation within the I unit (rather than within the E unit). The functions executed within the I unit are primarily channel instructions and supervisory type instructions such as setting the program and the system mask, loading the PSW, setting or inserting keys, and diagnose. In addition, the IE unit cooperates with the E unit on the performance of multiple load and store operations. The IE unit comprises essentially a control section (FIG. 277 et seq.) and a channel communications section (FIG. 308b et seq.).

13.1 IE UNIT CIRCUIT

13.1.1 IE UNIT CONTROL CIRCUITS

The control circuits which comprise the major portion of the IE unit are shown in FIG. 277 et seq. These circuits may be considered in four major groups: instruction decoding (FIG. 277 and FIG. 286); sequencing (FIG. 278 through FIG. 283); special logic circuits (FIG. 289 through FIG. 292); and control lines which comprise combinations of sequence, system status, and instruction decode or function lines, the control lines actually controlling the system in IE unit operations (FIG. 293 through FIG. 295).

13.1.1.1 IE Decode Circuits FIG. 277 And FIG. 286

The actual instructions which involve the IE unit are decoded in FIG. 277. Therein, decoding is accomplished in three levels by a plurality of AND-circuits 1-4; the AND-circuits 1 respond to BOP bits 0-3 for high order decoding, the AND-circuits 2 respond to BOP bits 4 and 5 for middle-order decoding, the AND-circuits 3 respond to BOP bits 6 and 7 for low-order decoding. The outputs of the AND-circuits 1-3 are combined in the AND-circuits 4 to generate signals indicative of the actual instructions. Notice that no instruction decoding is allowed during initial program loading due to the presence of a signal on a NOT IPL A line at the input to each of the AND-circuits 1. In FIG. 286, an OR-circuit 1 responds to the various channel instructions so as to generate a signal on a CHAN INST line, which line is applied to an OR-circuit 2 together with other lines so as to generate a signal on a MODAR DEC line. The signal on the MODAR DEC line indicates that an addressable register will be modified as a result of one of these IE unit instructions; hence the name MODAR (MOD = modified, A = addressable, R = register).

13.1.1.2 Load And Store Multiple Sequencers (IM1 IM2) FIG. 278, FIG. 280 and FIG. 281

For the multiple load and multiple store operations, a pair of special sequencers, not used for other instructions or functions, are provided. The IM1 and IM2 sequences are used to define fetches or stores to even and odd halves of a storage word, respectively. Thus, if an even half of a storage word is to be reached, IMI will come on with IE1 for a first cycle; thereafter, IM2 will come on for a second cycle and IM1 will again come on for a third cycle. This is illustrated in FIG. 306. On the other hand, if the first store is to be made to an odd (low order) half of a storage unit, then IM2 will come on with IE 1 for a first cycle, after which IM1 will come on, and then IM2, and so forth, as illustrated in FIG. 305. The turn on for IM1 is effected by an OR-circuit 1 which will generate a signal on the TON IM1 line in response to any one of three AND-circuits 2-4 in FIG. 278. The AND-circuit 2 is operative during a multiple store operation when the IM2 latch is on; this is because IM1 will follow IM2 during a multiple store. The AND-circuit 3 is operative during a multiple load operation when IM2 is on provided BR 1 does not equal IR2. The AND-circuit 4 will operate during either multiple load or multiple store on the occurrence of I GO when H register bit 21 is a 0 indicating an even half of a storage word. Thus the AND-circuit 4 would be for an initial turn on of IM2 that turn on being concurrent with the turn on of IE1 as described hereinafter.

IM1 can be turned off by a signal on a TOF IM1 line which is generated by an OR-circuit 5 in response to either one of four AND-circuits 6--9. Each of these AND-circuits is operative during either multiple load or multiple store operations due to the signal on the MULT LD OR STR line. The AND-circuit 6 provides for the turnoff of IM1 in the event that it is on at the time of I GO in the event that H REG bit 21 is a 1 indicating an odd half of a storage word is involved. The AND-circuit 7 causes IM1 to be turned off whenever IM1 is latched concurrently with IE1 being latched. Thus, IM1 will automatically be turned off after a first cycle when it is on concurrently with IE1; the usual turn off of IM1 will be an accept signal for the storage request indicating that both halves of a storage word are to be stored or fetched except during the initiation of multiple load and store operations, which is prevented from occurring by the presence of the signal on the NOT I GO line at the input to an AND-circuit 9. An AND-circuit 8 is also provided.

The IM2 latch is turned on by a signal on a TON IM2 line which is generated by an OR-circuit 10 in response to either one of two AND-circuits 11, 12, or in response to a signal on a TN IM2 line. The AND-circuit 11 is operative during multiple load when BR 1 does not equal IR2 following an IM1 cycle when an accept (other than an accept for a previous operation) is received. The AND-circuit 12 is responsive to the same signals as the AND-circuit 11 except for the fact that a multiple store operation is involved, and it is further prohibited from operating once the IE3 latch has been set. The signal on the TN IM2 line is generated in FIG. 290 by an OR-circuit 1 in response to either one of two AND-circuits 2, 3 each of which requires a signal on a MULT LD OR STR line. The AND-circuit 3 provides for the turn on of IM2 as a second IM cycle due to the presence of IM1 and IE1 at the input thereto, whereas the AND-circuit 2 provides for the initial turning on of IM2 when H REGISTER BIT 21 is a 1 due to the presence of the I GO signal.

The IM1 latch is shown in FIG. 280 to comprise a bipolar latch 1 which is settable at NOT LC time by a latch 2 so as to generate a signal on the IM1 LCH line. The latch 2 is set by an OR-circuit 3 in response to a scan signal or in response to an AND-circuit 4. The AND-circuit 4 operates at A time in response to the signal on the TON IM1 line. The latch 2 is reset by an OR-circuit 5 in response to CPU reset, or in response to either one of two AND-circuits 6, 7 each of which is operable at A time. The AND-circuits 6 respond to a signal on a TOF IM1 line, and the AND-circuit 7 responds to the signal on the TON IEL LCH line. Thus the latch 2 can be reset because of the logic of FIG. 278, or in response to the same logic which will cause the turning on of the last IE cycle, IEL.

The IM2 latch is shown in FIG. 281. A signal is generated on a IM2 LCH line by a bipolar latch 1 in FIG. 281 in response to a signal on an IM2 line at NOT LC time. The IM2 signal is generated by a latch 2 which is settable by an OR-circuit 3 in response to a scan signal or in response to an AND-circuit 4 which is operated at A time provided there is a signal on a TON IM2 line. The latch 2 is reset by an OR-circuit 5 in response to a CPU RST signal, or in response to a signal on the IM2 LCH line being applied to an AND-circuit 6. Thus the IM2 LCH is turned off one cycle after it is turned on, automatically, due to the operation of the AND-circuit 6.

13.1.1.3 IE Sequencers

13.1.1.3.1 IE 1 CIRCUITS FIG. 279 and FIG. 282

The IE1 sequence defines the first cycle of an IE operation in every case except the case of channel instructions, wherein IE2 comprises the first cycle. IE1 is is turned on by a signal on a TON IE1 line which is generated by an OR-circuit 11 in FIG. 279 in response to any one of nine AND-circuits 12-19. Each of the AND-circuits 12-16 comprise a way to turn on IE1 as a first cycle in response to the signal on the I GO line. Each of these AND-circuits relates to a particular instruction (or pair thereof), except for the AND-circuit 12 which is turned on with the turn on of IE last provided there is also an I GO at that time, which indicates that two functions, one after the other, require the operation of the IE unit. The AND-circuit 16 also has an inhibit provided so as to prevent operation during initial-program-loading operations.

The AND-circuits 17-19 provide for turning on of IE1 in response to other than I GO during related operations. For instance, the AND-circuit 17 will cause IE1 to follow IE2 during channel instructions, the AND-circuits 18 will respond to DEC GO signal (from the VFL, or decimal, area of the machine) during a set system mask instruction. The AND-circuit 19 operates only during initial program loading, and recognizes the order from the PDU to turn on the IPL trigger in response to the signal on the MC TON IPL TGR line. However, the AND-circuit 19 will not operate when the IE3 latch has been set.

The turning off of the IE1 latch is accomplished by a signal on a TOF IE1 line which is generated by an OR-circuit 1 in FIG. 279. The OR-circuit 1 can be operated with the turning on of the IE last cycle due to the signal on the TON IEL LCH line. Otherwise, the AND-circuit 1 is responsive to any one of nine AND-circuits 2-10. The AND-circuits 2 and 3 will cause IE1 to be turned off one cycle after it is turned on in set program mask and set system mask operations due to the presence of the signal on the IE1 LCH line. The AND-circuit 4 operates during a load PSW instruction when J is loaded, other than at the very start of IE sequencing due to the fact that the J loaded signal may result from a prior operation. The AND-circuit 5 recognizes an accept received during a diagnosing instruction provided that accept is not received at the start of the IE operation, which proviso is effected by the signal on the NOT I GO line. The AND-circuit 6 recognizes the accept for the set or insert key instructions. The AND-circuit 7 is operative during any channel instruction when the release trigger latch is set; the AND-circuit 8 operates similarly during initial-program-loading operations. The A 9 causes the turning off of IE1 when the IM2 latch is on during multiple load or store operations. An AND-circuit 10 operates during multiple store operations when IM1 is set provided BR 1 does not equal IR2.

The IE1 latch itself is shown in FIG. 282 to comprise a bipolar latch 1 which is set by a signal on a IE1 line so as to generate a signal on a IE1 LCH line at NOT LC time. The IE1 signal is generated by a latch 2 which is settable by an OR-circuit 3 in response to a scan signal or to an AND-circuit 4 which operates at A time in response to the signal on the TON IE1 line. The latch 2 is reset by an OR-circuit 5 in response to CPU RST, or in response to TOF IE1 due to the effect of an AND-circuit 6.

13.1.1.3.2 IE2 CIRCUITS FIG. 288 AND FIG. 284

The IE2 sequence is the second sequence of all IE operations except channel instructions, wherein IE2 provides a first, dead cycle to permit sufficient time for all signals to propagate from the channel back to the IE unit.

IE2 can be turned on by a signal on a TON IE2 line which is generated by an OR-circuit 1 in FIG. 288 in response to any one of five AND-circuits 2-6, each of which is operative only when the IE1 latch is already set. Another AND-circuit 7 will permit turning on IE2 as a first cycle when I GO appears in a channel instruction. The AND-circuit 2 operates during load PSW when J is loaded, the AND-circuit 3 turns on in a set system mask instruction, the AND-circuit 4 is operated during the set key instruction when an accept signal is received, the AND-circuit 5 operates in the set program mask instruction, and the AND-circuit 6 will operate during initial program loading provided IE2 is not already turned on, and the IE3 latch is not on.

The signal on the TON IE2 line is applied to an AND-circuit 1 in FIG. 284 so as to cause an OR-circuit 2 to set a latch 3, the output of which is reflected in a bipolar latch 4 at NOT LC time so as to generate a signal on the IE2 LCH line. The latch 3 is reset by an OR-circuit 5 in response to CPU RST or in response to the signal on the IE2 LCH line due to the effect of an AND-circuit 6. Thus, the IE2 latch is always turned off one cycle after it is turned on.

13.1.1.3.3. IE3 CIRCUITS FIG. 288 and FIG. 285

The IE3 sequence is utilized as a third sequence in several different operations, and is turned on by a signal on a TON IE3 line which is generated in FIG. 288 by an OR-circuit 8 in response to any one of six AND-circuits 9-14. The AND-circuits 9 and 10 permit the turn on of IE3 as a result of IE2 being on during IPL and LOAD PSW operations respectively. The AND-circuit 11 responds to a proceed signal from the PDU during the diagnose instruction which is an indication to the IE unit that T1 and IC need no longer be blocked which is accomplished with IE3. The AND-circuit 12 causes IE3 to be turned on following IE1 in channel instructions; this is due to the fact that IE2 is a first cycle therein and IE3 is used as a second cycle following IE1 in channel instructions. The AND-circuit 12 is brought into operation when the release trigger latch is set, this latch in turn indicating that the channel performing the operation has finished its part, and is now releasing the CPU. The AND-circuits 13 and 14 are operated in a multiple store operation when BR 1 does not equal IR2 in dependence upon the IM2 or the IM1 latches being set, respectively. The AND-circuit 14, however, also requires a signal on a line indicating the presence of either accept with NOT I GO or IE1 latch, both concurrent with not TON IEL LCH. This permits the taking of a first IE3 cycle in response to IE1, and later cycles (after I GO if off) only in response to ACCEPT. The ACC & NOT GO OR IE1 LCH line cannot appear if TON IEL LCH is present, since an ACCEPT received at that time is the last ACCEPT for the instruction; prior ACCEPTS, however, indicate that BR 1=IR2 is signalling the start of the last storage reference.

IE3 is turned off by a signal on a TOF IE3 line which is generated by an OR-circuit 18 in response either to the turn on of IEL, or in response to an AND-circuit 19 which recognizes that the release trigger latch has been set during initial program loading.

The TON IE3 signal is applied to an AND-circuit 1 in FIG. 285 so as to cause an OR-circuit 2 to set a latch 3, the output of which is reflected in a bipolar latch 4 at NOT LC time so as to generate a signal on the IE3 LCH line. The OR-circuit 2 can also respond to a scan signal. The latch 3 is reset by an OR-circuit 5 in response to a CPU RST signal, or in response to the application of the TOF IE3 signal to an AND-circuit 6.

13.1.1.3.4. LAST IE CYCLE (IEL) FIG. 287 AND FIG. 283

The last cycle of every IE unit operation is "IE last," referred to herein as IEL. The actual last cycle is defined by IEL LCH and the anticipation of this, as well as the turning on thereof, is manifested by TON IEL. The TON IEL signal is also sent to the I unit controls to permit setting of TON T2 so that T2 can appear simultaneously with IEL LCH.

The TON IEL signal is generated by a latch 1 in FIG. 287. This latch is set by an OR-circuit 2 in response to either one of two AND-circuits 3, 4, each of which requires a signal on a NOT LC line. The AND-circuit 3 also requires a signal on a ACCEPT line. The AND-circuits 3, 4 are respectively responsive to a pair of OR-circuits 5, 6. The OR-circuit 5 responds to any one of three AND-circuits 7-9, the AND-circuit 7 responding during an insert key instruction when the IE1 latch has been set. In other words, IE1 and IEL are the only two sequences for an insert key instruction (see FIG. 295). The AND-circuit 8 is operative during multiple store instruction (FIG. 305 and FIG. 306) to cause IEL to come on following IE3, provided that I GO is not on. The AND-circuit 9 is similarly operative during multiple-loading instruction (FIG. 307), but causes IEL to turn on following IM1 when BR 1 equals IR2 (indicating the end of the multiple-loading operation.) As an alternative to the AND-circuit 9, and AND-circuit 10 can turn on with IM2 on so as to set IEL through the OR-circuit 6 and the AND-circuit 4 even though there is no accept signal. An AND-circuit 11 operates during a diagnose instruction to turn on IEL following IE3. The LOAD PSW instruction causes an AND-circuit 12 to operate in a manner similar to that of the AND-circuit 11 by turning on IEL following IE3. The set system mask instruction calls for IEL to follow IE2 due to the effect of an AND-circuit 13, as does the set key instruction (AND-circuit 14). The OR-circuits 6 can also respond to a signal on a TN IEL line, which signal is generated in FIG. 291 by an OR-circuit 1 in response to any one of three AND-circuits 2-4. The AND-circuit 2 is operative during channel instructions to cause IEL to follow IE3, the AND-circuit 3 handling the branch-no-op which is a branch on condition instruction when the condition upon which a branch is to be made is all zeros; in other words, an RR format branch on condition with R2 containing all zeros in a no-op instruction. Thus, provided an IPL operation is not involved, a BOP decode RR branch on condition signal together with not R2 0 will cause IEL to follow IE1. An AND-circuit 4 in FIG. 291 causes IEL to follwo IE2 in a set program mask instruction.

The IE last cycle latch, as shown in FIG. 283, comprises a bipolar latch 1 which generates a signal on the IEL LCH line. A bipolar latch 1 is responsive during NOT LC time to a latch 2 which is settable by an OR-circuit 3 in response to a scan signal or in response to an AND-circuit 4. The AND-circuit 4 operates at A time when there is a signal on the TON IEL LCH line. The latch 2 is reset by an OR-circuit 5 in response to CPU RST, or in response to the turning on of the IPL latch as indicated by a signal on the IPL LCH line due to the effect of an AND-circuit 6.

13.1.1.4. Special Logical Circuits

13.1.1.4.1 INITIAL PROGRAM LOADING CONTROLS FIG. 289 AND FIG. 290

In FIG. 289, the initiation of initial program loading within the IE unit is effected by the appearance of a signal on the MC TON IPL TGR line. This causes an AND-circuit 1 to operate an OR-circuit 2 thereby setting a latch 3, provided there is no signal on a CPU RST line at the input to the AND-circuit 1. The reason for this AND-circuit is to insure that the reset which accompanies or precedes an IPL operation is apparent when an attempt is made to cause the IE unit to respond to initial program loading. The output of the latch 3 comprises a signal on an IPL line, which in turn will be effective at the input of a bipolar latch 4 during NOT LC time, so that the latch 4 may in turn generate a signal on the IPL LCH line. The OR-circuit 2 is also responsive to a scan signal. The latch 3 is reset by an OR-circuit 5 in response to either one of two AND-circuits 6, 7. The AND-circuit 6 is the normal turn off for the latch 3, being responsive to a signal on the TOF IPL line at A time. The AND-circuit 7 causes the IPL latch to be reset in response to CPU RST provided that the PDU is not trying to turn on an IPL sequence.

The signal on the MC TON IPL trigger is also applied to an OR-circuit 8 in FIG. 290, the output of which comprises the signal on the IPL A line. The OR-circuit 8 also responds to the signal on the IPL LCH line which provides for the IPL A line to indicate either the turn on of the IPL latch or the IPL latch itself. A signal is generated on a IPL PULSE line by an OR-circuit 9 in response to IPL LCH in the presence of the IE2 LCH signal.

Turning off of IPL is normally accomplished by an OR-circuit 10 in FIG. 290 which generates a TOF IPL signal in response to a signal on an IE TOF IPL TGR line from the interrupt controls. The OR-circuit 10 can also respond to an AND-circuit 11 which will cause IPL to turn off when in the scan mode and the release trigger latch has been set by scanning signals.

13.1.1.4.2 CHANNEL RELEASE BUFFER AND TRIGGER CIRCUITS FIG. 291 AND FIG. 292

In order to accommodate the asynchronous nature of channel operations, a release buffer is provided which then sets a release trigger thereby synchronizing the operation of the channels with the CPU, in much the same fashion as takes place in the release circuits within the interruption controls.

During initial program loading, an AND-circuit 6 in FIG. 291 is responsive to a signal on a CHAN REL line, which signal is sent to the CPU from the channel to indicate that its part of the IPL operation is completed. The AND-circuit 6 therefore will cause an OR-circuit 7 to pass a signal through an AND-circuit 8 at A time so as to cause an OR-circuit 9 to set a latch 10. The OR-circuit 7 may also be operated by a pair of AND-circuits 11, 12, each of which is operative during channel instructions. The AND-circuit 11 operates when the IE1 latch is set and the channel release is received, and the AND-circuit 12 operates when the IE1 latch is set and a CPU release is received. As described in Section 1.0.0.0, et seq., an attempt to select a channel which is not included within a particular embodiment of said environmental system will cause a CPU release to be sent to the IE unit in place of the normal channel release so that the CPU will not hang indefinitely attempting to reach an unavailable channel. This is where the AND-circuit 12 comes into operation. The OR-circuit 9 is also responsive to scan signals, and the output of the latch 10 is used to set a bipolar latch 13 at NOT LC time, so as to generate a signal on the REL BUF LCH line. A latch 10 is reset by an OR-circuit 14 in response to CPU RST, or in response to an AND-circuit 15 which is reset at A time as soon as the IE1 latch itself has been reset. However, IE1 will not be reset until the release trigger latch is turned on in the case of IPL or channel instructions.

The signal on the REL BUF LCH line is applied to an AND-circuit 1 in FIG. 292, which when enabled, will cause an OR-circuit 3 to set a latch 4, the output of which can be reflected in a bipolar latch 5 so as to generate a signal on a REL TGR LCH line. The OR-circuit 3 is also responsive to scan signals SCN IN REL TGR line. The AND-circuit 1 also requires the presence of a signal on a IE1 LCH line, so that the AND-circuit 1 also cannot be set by the release buffer latch a second time, this being assured because IE1 is turned off in response to the turn on of the release trigger latch (FIG. 279, AND-circuits 6, 7). The latch 4 is reset by an OR-circuit 6 in FIG. 292 in response to CPU RST, or in response to the turning on of AND-circuit 2 which responds to the absence of IE1 concurrently with an A clock signal. Thus, release trigger will turn on, and turn off IE1, so that on the next A clock the lack of IE1 will turn off the release trigger. Thus, the release trigger is always on for but a single cycle.

13.1.1.5 Control Gating Signals FIG. 293, FIG. 294 and FIG. 295

The signal lines actually used for controlling IE operations will not be described in great detail due to the fact that the operation of the circuits is obvious from the drawings thereof.

During channel instructions, the diagnose instruction, multiple store, set program mask or set key instructions, a signal is generated on the IE TOF BLK T1M line by an OR-circuit 1 in FIG 293 in order to turn off GROUT and to allow the turn on of T1. An OR-circuit 2 generates a signal on a IE RST PRI line at the start of a channel instruction, or when a new PSW is being loaded, on when the system mask has been changed. This is due to the fact that interruptions which have been granted priority should no longer be gated by the circuit of FIG 312 due to the fact that a new PSW may have a new mask, and when there is a new system mask, a particular interruption might not be recognizable. Additionally, if an IO interruption is manifested by a particular IO unit which is involved in a channel instruction, the interruption is removed at the channel in accordance with the architectural definition of said environmental system as set forth in said System/360 Manual.

In FIG 293, an OR-circuit 3 recognizes the set key and multiple store instructions so as to generate a signal on a IE TON MODAR line, the OR-circuit 3 also being responsive to the signal on the MODAR DEC line which is generated in FIG 286 in response to the channel instructions set program and system mask, diagnose and load PSW. On a multiple store instruction, or in set or insert key instructions an OR-circuit 4 in FIG. 293 permits turning on of T2 when the storage unit will no longer be busy with the CPU for these instructions. This is effected by generating a signal on a IE TOF BLK T2 ON ACC line.

In FIG. 294, a new PSW is provided parity checking by means of a signal on a IE INCR EXT ERROR line which is generated by an OR-circuit 1. The OR-circuit 1 is operated in both IE2 and IE3 cycles whenever J is valid so as to permit checking of each half of the PSW, one half in each cycle, by gating the PSW to the incrementer and sampling the possibility of an error sensed by the checking circuits of the incrementer. An AND-circuit 2 in FIG. 294 generates a signal for setting the PSW on an IE SET PSW line during a load PSW instruction An AND-circuit 3 and an AND-circuit 4 operate in conjunction with the OR-circuit 1 so as to gate each half of the PSW to the incrementer for parity checking during the load PSW instruction When a channel instruction is involved, the condition register must be set in accordance with the condition which obtains at the channel, and therefore and AND-circuit 5 generates a signal on the IE SET CR line. The set program mask instructs and AND-circuit 6 to generate a signal on the IE SET PGM MASK line. In a multiple load instruction, the incrementer is used for a plurality of fetches, and therefore instruction-fetching operations must be blocked. Similarly, during the diagnose instruction, an MCW control word is loaded from storage into a maintenance register within the PDU, and IC fetching must be blocked during that time. Therefore, an OR-circuit 7 generates a signal on the IE TOF BLK ICM line at the end of interference by the multiple load or diagnose instructions which occurs at IEL and IE3 respectively. During a multiple load instruction and AND-circuit 8 will cause an OR-circuit 9 to pass a signal through an OR-circuit 10 so as to generate a signal on an IE FTCH TO J line. The AND-circuit 8 will operate both single cycle and nonsingle-cycle operations, companion AND-circuit 11 is operatively only during nonsingle-cycle operations. Another AND-circuit 12 can also operate the OR-circuit 10 during set or insert key instructions.

In FIG. 295, an OR-circuit 1 generates a signal on the IE STR REQ line in response to the multiple store instruction. Notice that an AND-circuit 2 prevents IM1 from creating a multiple store with the IE latches on. This is due to the fact that if the first address is in the high order, or even half of a storage word, then the next one will be in the low order or odd half of a storage work and that therefore storage requests cannot be made until the IM2 latch is set. However, in cases where IM2 latch is set first, IE1 latch will turn off when IM1 latch turns on in which case the AND-circuit 2 will then be able to make the storage request. Whenever the AND-circuit 2 cannot make the request, an AND-circuit 3 will do so at the appropriate time in response to IM2.

An AND-circuit 4 causes the setting of mark bits for a multiple store operation with a high order half (even) of a storage word in response to IM1, and an AND-circuit 5 operates similarly for the low order half of a storage word in response to IM2. The AND-circuit 4 is further conditioned by the signal on ACC & NOT GO OR IE1 LCH line. The purpose of this line is described in Section 12.1.1.5, hereinbefore.

On either multiple load or multiple store operations, the incrementer is gated to the storage address register by a signal on the IE GT INCR TO SAR line which is generated by an AND-circuit 6 in FIG. 295. The purpose of this is to allow updating of the multiple and store addresses at each IM2 (which signals a completion of a storage word ready for storage). A similar AND-circuit 7 causes the gating of the H register to the incrementer just before the incrementer is gated to SAR because it responds to IE1 and IM2 in their unlatched state which occurs at A time, the latch state occurring slightly later at the beginning of NOT L TIME. Thus, the contents of the H register will pass through the incrementer roughly a quarter of a cycle before the incrementer is gated to SAR.

An OR-circuit 8 generates a signal on the IE INCR BR 1 line to increment BR 1 until BR 1 equals IR2 which signals the end of the multiple load or store operation. An AND-circuit 9 operates at IM2 time whereas the AND-circuit 10 operates in response to IM1, or to the fact that BR 1 does not yet equal IR2. The AND-circuit 10 is also responsive to the signal on the ACC & NOT GO OR IE1 LCH line.

Whenever there is a diagnose instruction, an AND-circuit 11 causes an IE diagnose fetch by generating a signal on a IE DIAG FTCH line. An AND-circuit 12 operates during initial program loading once the channel has completed whatever it is to do as indicated by the initial-load-program setup within the channel, which fact is indicated by the receipt of a signal on the REL BUF LCH line. Initial program loading will cause the AND-circuit 13 to generate a signal on a IE IPL START SEQ as soon as the release trigger latch is set provided a scan operation is not being performed. In a set system mask instruction, if J is valid, the IE1 latch will cause the AND-circuit 14 to generate a signal on a SET SYS MASK line to actually gate the new mask into the PSW mask operation. An AND-circuit 15 generates a signal on a IE SET KEYS line during IE1 of a set key instruction. An AND-circuit 16 generates a signal on a IE SET KEY line in response to an insert key instruction. An AND-circuit 17 causes the turn on of instruction counter recovery (fetching a new instruction into the AB registers so as to either begin instruction under a new PSW or to fetch an instruction previously fetched which has been changed) whenever the load PSW instruction is executed and the machine is not in the wait state as indicated by the presence of a signal on the NOT PSW 14 line. An AND-circuit 18 generates a signal to turn off J loaded during IE2 of the load PSW instruction, so that J loaded will be off at the commencement of the next following instruction, whenever it may be.

13.1.2. CPU CHANNEL SELECTION CIRCUITS

In FIG. 308a and FIG. 308b are shown circuits for selecting particular channels in response to either interrupts or channel instructions, respectively Each of these circuits, and the details of the component circuits thereof, are described in the following sections.

13.1.2.1 Channel Interrupt Selection Circuits FIG. 308a

In FIG. 308a, the various parts of the channel interruption circuits are shown in block form; the numbers within the blocks refer to the figure numbers wherein the details of the corresponding circuits are shown.

In FIG. 308a, a circuit FIG. 309 provides SET CH PRI (set channel priority) and RST CH PRI (reset channel priority) signals to control a CH IRPT MASK (channel interrupt mask) circuit FIG. 315 which designates a particular channel in response to program status word signals on LH PSW 1-6 lines and channel interrupt signals on INTR CH 1-6 lines in dependence upon there being an initial program load (IPL) operation, or not, respectively. One of the channel signals will be selected by a CH IRPT PRI circuit FIG. 311, such that the channel with the lowest number has highest priority and will be selected. Signals designating the channel which has been granted interrupt priority are applied to a CH IRPT OUT circuit FIG. 312, FIG. 313 which generates a signal on a NOT PRI GRANTED line, to control the circuit of FIG. 309, and also generates signals on a CH IRPT OUT LCH line and on CH IRPT OUT CODE lines 1-4, P for controlling interrupt responses to channels. The CH IRPT PRI lines from the CH IRPT PRI circuit FIG. 311 are also used in a CH RSP circuit FIG. 312 to generate individual channel interrupt responses to the CH IRPT RSPS lines 1-6.

13.1.2.1.1 CHANNEL PRIORITY-- SET/RESET FIG. 309

A set channel priority signal is generated on a SET CH PRI line by an OR-circuit 1 in FIG. 309 at B time provided that priority has not previously been granted as indicated by a signal on a NOT PRI GRANTED line. A signal is generated on a RESET CH PRI line by an OR-circuit 2 in response to a CPU reset as manifested by a signal on a CPU RST line or by an AND-circuit 3. The AND-circuit 3 is responsive at A time, provided that a signal is present on a IE RST PRI line or on a RST CH IRPT line, which designate resetting of I execution handling or of channel interrupts, respectively. Signals on the SET CH PRI line and RESET CH PRI line are utilized in the CH IRPT MASK circuit of FIG. 315

13.1.2.1.2 CHANNEL INTERRUPT MASK FIG. 315

A plurality of channel interrupt signals are generated in FIG. 315 on corresponding CH IRPT lines 1-6 and on a NOT CH 1 IRPT line by a plurality of corresponding latches 1 in response to related AND-circuits 2. Each of the AND-circuits 2 has applied thereto a signal on a SET CH PRI line, and each of the latches 1 is reset by a signal on a RESET CH PRI line. The other inputs to the respective AND-circuits 2 are channel interrupt signals on corresponding INTR CH lines 1-6 and PSW-masking bits for these channels on corresponding PSW lines 1-6. The operation of the AND-circuits 2 is to set the latches 1 whenever an interrupt for a particular channel coincides with a masking bit which permits the interrupt from the channel to occur. The masking bits are bits 1-6 of the PSW register. This is in accordance with the architectural requirements for this system, an explanation of which may be found in said System/360 Manual.

13.1.2.1.3 CHANNEL INTERRUPT PRIORITY CIRCUIT FIG. 311

Priority of channel interrupts is determined by the circuit of FIG. 311 in which priority is indicated by a plurality of CH IRPT PRIS lines, of which channel 1 will always have a signal provided there is a channel 1 interrupt signal at the input of the circuit, and the remaining five of which are selected by a plurality of AND-circuits 1-5. The AND-circuit 1 will be activated whenever there is a channel 2 interrupt signal and a not channel 1 interrupt signal concurrently. The AND-circuit 2 will operate in response to an inverter 6 whenever there is no output from an OR-circuit 7 concurrently with the presence of a channel 3 interrupt signal. The OR-circuit 7 recognizes the presence of a channel 1 interrupt signal or a channel 2 interrupt signal. Thus, if either channel 1 or channel 2 is causing an interrupt, the inverter 6 will block the channel interrupt priority for channel 3. Similarly, the AND-circuits 3, 4 and 5 are inhibited by the presence of a channel interrupt for a channel having a higher priority than the channel corresponding thereto. The CH IRPT PRIS lines are applied to FIG. 312 through FIG. 313 to generate proper responses.

13.1.2.1.4 CHANNEL INTERRUPT OUT CIRCUIT FIG. 312, FIG. 313

A NOT PRI granted signal is generated in FIG. 313 by an inverter 1 in response to an OR-circuit 2 whenever priority has been granted to any channel interrupt as indicated by a signal on a corresponding one of a plurality of CH IRPT PRI lines. The output of the OR-circuit 2 is also fed to an AND-circuit 3 which will set a latch 4 at A time. The latch 4 is reset by a signal on a RST CH PRIS line from FIG. 309. The output of the latch 4 is reflected in a bipolar latch 5 which generates a signal on a CH IRPT OUTST LCH line for use in the interrupt control circuits of the said environmental system.

The output of the latch 4 is also utilized to permit gating of any one of the channel interrupt priority signals on corresponding CH IRPT PRI lines to a plurality of related AND-circuits 6 so as to provide inputs to a plurality of OR-circuits 7-9 which generate signals on CH IRPT CODE 1, 2, 4 lines. These lines form an encoded manifestation of the particular channel to which priority was granted. The OR-circuits 7 operate in a regular binary fashion; that is, the 1 bit is generated for all of the odd number channels, the 2 bit is generated for channels 2, 3 and 6 (which include the value 2 in the binary code thereof), and a 4 bit is generated only for channels 4, 5 and 6.

The signals on the CH IRPT CODE 1, 2, 4 lines are applied to a pair of EXCLUSIVE OR circuits 11, 12 in FIG. 312 which generate, together with an inverter 11, a parity bit whenever the combination of bits 1, 2, 4 is even. The channel interrupt code bit 1, 2, 4 and the parity bits from FIG. 312 and FIG. 313 are applied to the PSW as an indication of the interrupt code; that is, these signals are applied to the PSW to indicate, in part, the reason for which an interrupt occurred.

13.1.2.2 Channel Instruction Selection Circuits FIG. 308b

In FIG. 308b, a CH DEC (channel decode) circuit FIG. 310 responds to initial-program-load signals or to signals representative of an instruction on a plurality of IPL CH ADR 0, 1, 2 lines, or on a plurality of lines from the H REG (H register) to designate a particular channel in dependence whether an initial-program-loading operation is being performed, or not, respectively. A decoded channel signal is sent over a corresponding one of a plurality of CH DEC 1-6 lines to a SEL CH (select channel) circuit FIG. 314 which generates a signal on a corresponding one of a plurality of SEL CH lines. These lines are applied together with the CH DEC lines to an UNAVAIL CH REL (unavailable channel release) circuit FIG. 316 which generates a CPU release signal on a CPU REL line, and also causes the condition code in the PSW to be set to value 3 by means of a signal on a SET CR TO 11 line (binary 11 equals decimal 3).

Lines from the H register are also applied to a CPU UNIT ADR circuit FIG. 317 which selects between the H register and the Unit Address Bus In for Initial Program Loading (IPL UABI) to generate a signal on a corresponding one of a plurality of CPU CH UNIT ADR BUS OUT lines.

13.1.2.2.1 CHANNEL DECODE CIRCUIT FIG. 310

During initial program loading, the CH DEC circuit FIG. 310 utilizes signals on IPL CH ADR 0, 1, 2 lines to designate a particular channel in an encoded fashion. At other times, a particular channel is designated by bits 13-15 of the H register, which specifies a channel address for an I/O operation. These bits correspond to bits 21-31 of the sum formed by the addition of the contents of a general register specified by the B field of an instruction with the contents of the D field of an instruction; this value comprises a channel address portion of an input/output device address which is to be utilized by a particular instruction involved. In FIG. 310 a plurality of OR-circuits 1 respond to a pair of corresponding AND-circuits 2, 3 so as to generate the channel address code bits 13, 14, 15, and their complements; the AND-circuits 2 respond to a signal on an IPL OR MC TON IPL line together with a signal on a related plurality of IPL CH ADR lines; the AND-circuits 3 respond to the complement of the IPL OR MC TON IPL signal on a NOT IPL OR MC TON IPL line and to a signal on a related line from the H register.

The signals on the H register lines 13, 14, 15 and their complements, are applied in a straight binary fashion to a plurality of AND-circuits 4, so as to decode the signals to specify a particular channel. For example, the lack of any bits will cause the top AND circuit to decode channel 0, all bits cause the decoding of channel 7, and bits 14 and 15 together with the absence of 13 will cause the decoding of channel 3. The other AND circuits operate in a similar fashion as is well within the skill of the art.

13.1.2.2.2 SELECT CHANNEL CIRCUIT FIG. 314

Whenever a channel instruction is being performed as indicated by a signal on a CH INST line, an AND-circuit 1 in FIG. 314 will provide a signal to an OR-circuit 2 provided that there is also a signal present on a NOT SCAN MODE line. the OR-circuit 2 may otherwise be operable by a signal on an MC TON IPL TGR line. Thus there will be a signal on a GT CH SEL line from the OR-circuit 2 whenever the maintenance channel causes turning on of the IPL trigger, or whenever a channel instruction is being performed in other than a scan mode of operation. The signal on the GT CH SEL line is used to gate a plurality of AND-circuits 3, each of which responds to a signal on an IE 1 LCH line to pass a signal on a corresponding one of a plurality of CH DEC lines to the related one of a plurality of SEL CH lines 1-6. The signal on the IE 1 LCH line indicates a first cycle portion of an I unit execution cycle. This is a cycle wherein the I unit must perform the function required by the instruction, as is the case when the instruction calls for monitoring, or communicating with, one of the input/output devices, such as in the case of a channel instruction. Each of the SEL CH lines is applied to a respectively corresponding channel so as to indicate to that channel that it has been selected for a channel instruction operation. The complements of these lines (although not shown) are applied to the circuit of FIG. 316 which is described in the next section.

13.1.2.2.3 UNAVAILABLE CHANNEL RELEASE CIRCUIT FIG. 316

In FIG. 316 a pair of AND-circuits 1, 2 generate signals on a SET CR TO 11 and a CPU REL line. These lines are used to release the CPU from the channel instruction and to set the condition code portion of the PSW register to binary 11 (decimal 3) so as to indicate that an unavailable channel is the cause for terminating the operation. The AND-circuits 1, 2 respond to an OR-circuit 3 and to a signal on a NOT IPL LCH line. The OR-circuit 3 responds to any one of three AND-circuits 4-6 when there is a signal present on the IE 1 LCH line concurrently with the signal on the CHAN INST line. The AND-circuit 4 responds to an OR-circuit 7 which in turn is operated by any one of a plurality of AND-circuits 8 whenever a select channel signal 1-6 has not been generated for a channel for which a corresponding channel decode signal has been generated. In other words, if a particular channel is decoded, but the decode line for that channel is NOT connected to a related AND-circuit 3 in FIG. 314, then no select signal can be generated for that channel. A decode without a select will cause a related AND-circuit 8 in FIG. 316 to indicated an error. Thus, when the channel is prevented from generating a select channel signal by the circuitry of FIG. 315, then there will be provided an indication via the OR-circuit 7 that the selected channel is not available in a particular configuration involved.

The AND-circuit 5 is operative whenever channel 7 is decoded because the present embodiment does not include provisions for a seventh channel; similarly, the AND-circuit 6 will operate whatever channel zero has been decoded. Thus, the circuit of FIG. 316 recognizes a case where a channel is either not included in the system, or because of power breakdown or maintenance operations has been removed from availability to the system temporarily, and causes the channel instruction operation to be terminated by means of a signal on the CPU REL line. This line is utilized in the I unit execution circuits IE for which reference may be made to said environmental system.

13.1.2.2.4 CPU UNIT ADDRESS CIRCUIT FIG. 317

In FIG. 317 is shown a circuit which selects between IPL signals and H register signals to generate a signal on a corresponding one of a plurality of CPU CH UNIT ADR BUS OUT lines. Specifically, signals are generated by a plurality of OR-circuits 1 in response to either one of two respectively corresponding AND-circuits 2, 3. The AND-circuits 2 are operated during initial-program-load operations as indicated by the presence of a signal on an IPL LCH line. Contrariwise, the AND-circuits 3 are operative whenever initial-program-loading operations are not being performed as indicated by a signal on a NOT IPL LCH line. Each of the AND-circuits 2 responds to a respectively corresponding one of a plurality of IPL UABI (unit address bus in) lines P 0,...7. Similarly, the AND-circuits 3 respond to a plurality of H register lines P(16-23), 16,...23. Thus, this circuit will provide a correct signal on the CPU channel unit address bus out for IPL and non-IPL operations.

13.2 I UNIT EXECUTION OPERATIONS AND SUMMARY

13.2.1 INTRODUCTION

The I execution and the channel controls include the control triggers and the logic to generate the necessary control lines to perform the I execution instructions, together with the logic necessary to communicate with the channels (excluding data buses and error lines) and an IE instruction decoder receiving its input from BOP and a further decoding facility responsive to the channel interrupt priority circuits.

The instructions performed entirely by the IE unit are Load PSW, Diagnose, Set Program Mask, Branch No-Op (BR ON COND, with CR=00), Set Tags, Start I/O, Test I/O, Halt I/O and Test Channel. Instructions performed in conjunction with the E unit are Set System Mask Insert Key, Load Multiple, and Store Multiple. The IE unit also performs a portion of IPL (initial program loading).

The triggers (or latches) which control the above operations IE1, IE2, IE3, IEL, IM1, IM2, the Release Buffer, Release Trigger and the IPL Trigger. Two or more of the IE sequences controlled thereby are used in each IE instruction. IM1 and IM2 are used only in Load and Store Multiple and the REL BUF and REL TGR are used only in the channel instructions and IPL.

Each of these triggers are set and reset with an A clock, and the trigger setting is reflected in a latch which follows each trigger and is controlled by an L clock.

13.2.2 INITIAL PROGRAM LOADING (IPL)

An IPL sequence will result from pushing the IPL pushbutton on the operator's console or on the maintenance console. The I/O unit and channel addresses are gated to the CPU from the MC or operator's console depending upon which IPL pushbutton is activated. CONS IPL or MC IPL is turned on in the PDU, the control clock is stopped and a system reset is generated. The OR'd output of CONS IPL and MC IPL gate the MC TON IPL TGR line. This line and CPU RST turns on MODAR (FIG. 319) and the CPU's IPL trigger (FIG. 289). This trigger gates the unit address to the channels from the MC (called IPL CH ADR, FIG. 308b) instead of from the H register. The unit address is sent to the channels on the unit address bus out (UABO) which is composed of 8 bits plus parity. The channel address is sent to the channel decoder (FIG. 310). The output of the decoder is sent to the channel select circuit (FIG. 314) and thence to an unavailable channel detector (FIG. 316). If channel 0 or channel 7 in this embodiment, or any other channel not physically present is selected, the system will hang with CONS IPL or MC IPL on in the PDU, and with IPL and IE 1 on in the CPU.

After SYS RST is over, the clock is started and IE 1 turns on with the first A clock (FIG. 279 and FIG. 282). IE1 gates the channel-selecting signal (FIG. 315) and turns on IE2 which gates "IPL pulse" to all the channels. IE2 always turns itself off one cycle later and IE3 is turned on to prevent IE2 from coming back on. The CPU holds "select channel" active until "release" is received from the channel, which sets the release buffer so that the CPU becomes synchronized with the asynchronous release line. The latched output of the release buffer sets the release trigger on the next cycle, the latched output of which routes the turn off of IE1 and IE3, and provides "IE IPL START SEQ" to the interrupt controls, if FLT mode is not active (FIG. 295). The latched output of the release buffer is used in the PDU to turn off CONS IPL or MC I PL.

If the FLT MODE is active, the IPL TGR in the CPU is also turned off with the presence of REL LCH; if this line is not active the interrupt controls turn off the IPL TGR. When an IPL is executed in FLT MODE, the CPU is not activated and its status is determined by the FLT programs; the REL BUF and REL TGR are turned off and the interrupt controls cause a word to be fetched from address zero and set into the PSW. Two fetches are made from the value of the ICR and ICR + 1. When the first word returns, the CPU will start the first instruction unless this instruction is partially located in both the A and B registers; if this is the case, the CPU must wait for both words to return.

13.2.3 INSTRUCTIONS

13.2.3.1 Channel Instructions (Start I/O, Test I/O, Halt I/O and Test Channel)

All of the channel instructions are privileged instructions and are of the RS format in which R 1 and R 3 are ignored. The contests of the GR specified by the B2 field of the instruction (when B2 0) is added to the D2 field in the T1 cycle and the result is placed in the H REG to form the channel and unit address. Bits 13, 14 and 15 form the channel address and bits 16 to 23 form the unit address. The unit address plus the parity for bits 16 to 23 are placed on the unit address bus out (the same bus used in IPL). The instruction (from BOP) is decoded (FIG. 277) and the appropriate one of the four channel instruction controls is sent out to the channels. In cycle T2, T1 is blocked to maintain the unit address applied to the channels until a release is received.

When I GO is generated (by instruction-sequencing controls), IE2 is turned on (FIG. 288). The latched output of IE2 turns on IE1. This is the only case (CHAN INST) where IE2 turns on before IE1; IE2 provides a "dead cycle" to allow sufficient time for the slowest release signal from one channel to be received and acted upon in IE1, without the possibility of using the decoded channel address (FIG. 314) of the first channel instruction to select a channel for an immediately following second channel instruction. IE2 is necessary to insure the UABO is good at each channel when select channel is activated. Modar is then turned on. The circuits used in IPL operations to select a channel are also used in these instructions, but the gate lines are activated by CHAN INST and NOT FLT MODE. In FLT MODE the conditions necessary to activate select channel might be fulfilled and a false select channel sent out.

If channel 0, channel 7 or a channel not physically present on the system is selected the INV CH SPEC trigger is turned on. The CPU generates a release line and a 1 (FIG. 306) and 11 is set into the condition code register (bits 34 and 35 of the PSW). The output of the invalid channel specification trigger is applied to the interruption controls, and causes an invalid specification interruption at the end of the instruction. This trigger is reset by the interruption controls.

If a valid channel is selected, the CPU waits for a release signal which is handled as in IPL. The latched output of the REL TGR turns off IE 1, turns on IE 3 and, together with the latched output of IE 1, generates the lines to set the condition register and reset the channel priority circuits. The channels set the condition register after every I/O instruction, and channel interruptions might have changed during the instruction. A more detailed description of the channel priority is given hereinafter. IE3 LCH unblocks T1 and turns on IEL. IE3 is necessary to allow changes in channel interruptions and still take the interruption after IEL. FIG. 297 shows the timing of a channel instruction.

13.2.3.2 Load PSW

Load PSW is a privileged instruction in the RS format in which R1 and R3 are ignored. The contents of the general register specified by the B2 field (when B2 0) is added to D2 to form a storage address from which the new PSW will be obtained.

In cycle T1 this address is placed in SAR, a fetch request is generated, and block IC is turned on. In cycle T2, T1 is blocked.

IE1 is turned on by I GO and stays on until the new PSW returns to the J register. MODAR is turned on by IE 1. When the storage word returns, J LOADED turns on. J LOADED turns off IE 1, turns on IE2 and if J is valid sets the new PSW into the PSW register and resets the channel priority circuits. This is necessary because the new PSW might have a different system mask and interrupts already in the channel priority circuits may be changed.

The latched output of IE2 turns on IE3 and turns off J LOADED. If the data in the J REG is valid, the unlatched output of IE3 gates the right half of the new PSW to the incrementer for checking, and the latched output (IE3 LCH) allows a parity check to be set if one is present.

The latched output of IE3 turns on IEL and turns on IC recovery if the system is in running state as indicated by PSW Bit 14 being a zero. IC recovery turns off J LOADED, unblocks the IC and T1, and causes two fetches to be made from the value of IC and IC + 1. If PSW Bit 14 is a one, wait state, a recovery is not started, and the WAIT Trigger in the interrupt controls is turned on at the end of this instruction. If J is valid, the unlatched output of IE3 gates the left half of the new PSW to the incrementer for checking and the latched output allows a parity check to be set if there is a parity error. FIG. 298 show the timing of Load PSW.

13.2.3.3 SET System Mask

Set system mask is a privileged instruction in the RS format in which R 1 and R 3 are ignored. The contents of the general register specified by the B 2 field (with B2 0) is added to D2 to form a storage address from which the new system mask will be obtained. Bits 0-7 of the PSW comprise the system mask. The presence of these bits allows interruptions to be taken from the channel associated with each bit. Bit 0 is the mask bit for a MPX channel which is not looked at because this embodiment of a system does not include a multiplex (MPX) channel. Bits 1-6 are the mask bits for six selector channels (CH1-CH6) and bit 7 is the mask bit for external interruptions.

In cycle T1 the storage address is placed in SAR and a storage request is generated.

E GO turns on the first fixed point trigger and with J advance or J loaded, the first fixed point latch is set. The first fixed point latch gates the J REG to the main adder. The first fixed point latch also gates the main adder to the K REG, releases K, turns on Put Away 1 (PA1) and generates DEC GO, which turns on IE1. PA1, when latched, gates the correct byte to the PSW.

The latched output of IE 1 turns on MODAR, turns on IE2 and, if J is valid, sets bits 0-7 of the PSW and resets the channel priority. The latched output of IE2 turns on IEL and is necessary to allow any required changes in interrupt through the channel priority circuits. FIG. 299 shows the timing of Set System Mask.

13.2.3.4 Set Program Mask

Set Program Mask is an instruction in the RR format in which R2 is ignored. Bits 2 to 7 of the general register specified by R1 (GR R1) replace bits 34 to 39 of the PSW.

Bits 34 and 35 comprise the condition register, and bits 36 to 39 are program mask bits which allow or inhibit program interruptions from being taken. When bit 36 is a one, an interrupt will be taken on fixed point overflow; when bit 37 is a one, on decimal overflow; when bit 38 is a one, on exponent underflow; and when bit 39 is a one, on lost significance.

In cycle T2, T1 is blocked and when I GO is generated, GROUT is turned on. GROUT gates GR R1 to GBL, and bits 2 to 7 of GBL are gated to PSW 34-39.

IE1 is turned on by I GO, the latched output of which sets bits 34-39 of the PSW, turns on MODAR, turns off IE1 and turns on IE2. The latched output of IE2 turns off BLK T2M and GROUT, and turns on IEL (last IE cycle). FIG. 300 shows the timing of the Set Program Mask.

13.2.3.5 Diagnose

Diagnose is a privileged instruction in the RS format in which R1 and R3 are ignored. The contents of GR B2 (B2 0) is added to D2 to form the storage address from which the MCW maintenance control word) will be set. The MCW is a 20-bit register located in the PDU. In cycle T1, the address is placed in SAR and IC is blocked. In cycle T2, T1 is blocked. IE 1 is turned on by I GO, the latched output of which turns on MODAR and causes a diagnostic fetch. When storage is free, a normal accept is sent which turns off IE 1. In place of the usual advance pulse, the BCU sends, instead, a diagnostic select (DIAG SEL) to the MC, which turns on the PDU sequencer D1 and gates the word into the MCW. D1 turns on D2, the output of which comprises a PROCEED line which is applied to the IE unit. PROCEED turns on IE 2 which unblocks 1 and IC, and turns on IE1. FIG. 301 shows the timing of DIAGNOSE.

13.2.3.6 Set Storage Key

Set Storage Key is a privileged instruction in the RR format. The four bits, 24 to 27 of GR R1, form the new protection keys. Bits 8-20 of GR R2 form the storage address of the storage block to be protected by the keys which are set (see said System/360 Manual).

In cycle T1, the address is placed in SAR and IC is blocked. In cycle T2, T1 is blocked and GROUT is turned on.

I GO turns on IE 1, the latched output of which gates the new protection key to storage, turns on MODAR and makes a fetch request. The bits are gated (FIG. 75) from GR R1 to GBL, into the BCU.

The latched output of IE1 is also sent to the BCU to enable the BCU to inform storage that a Set Key instruction is being performed, and to block all return address by treating the fetch as a store. Sequencing controls also receive the latched output of IE1 to unblock IC on an accept.

An accept turns off IE1 and turns on IE2, which drops the fetch request, unblocks T1 and turns off GROUT. The latched output of IE2 turns on IEL. FIG. 302 shows the timing of Set Storage Key.

13.2.3.7 Insert Storage Key

Insert Storage Key is a privileged instruction in the RR format. The protection key of the memory block addressed by GR R2 is inserted into bits 24 to 27 of GR R1.

In cycle T1 the address is set in SAR and the IC is blocked. In cycle T2, T2 itself is blocked from coming back on.

I GO turns on IE1, the latched output of which causes a fetch request and also is sent to the BCU to internally treat the fetch as a store, block the return address and inform storage that an Insert Key instruction is being performed. Sequencing controls also receive the latched output of IE1 to unblock IC and T2 with an accept. An accept turns off IE1 and turns on IEL. E GO which is generated at the same time as I GO, turns on the first fixed point trigger which sets the M REG with the contents of GR R1. The path is through the RBL and into the M REG. The first fixed point trigger stays on, gating the M REG to the K REG, until storage sends a KEY ADV.

When storage sends the KEY ADV, the BCU gates the new keys into a storage key buffer (in the VFL section) and the E unit turns on the half word logical sequencer which gates the contents of the storage key buffer through the AOE latch and on to the byte gates back to the K REG. P A 1 is turned on and gates the K REG to GR R1. FIG. 303 shows the timing of Insert Storage Key.

13.2.3.8 Branch No-Op

Branch No-Op is an RR Branch on condition instruction (BCR) in which the R2 field is zero. BCR is sent from the BOP decode to the IE unit, and, if BR OP is not set (R2=0), sequencing controls generate an I GO. I GO turns on IE1, the latched output of which turns on IEL. FIG. 304 shows the timing of Branch No-Op.

13.2.3.9 Store Multiple

Store Multiple is an instruction in the RS format in which R1 defines the first GR to be stored and R3 defines the last. The contents of GRB2 (B2 0) is added to D2 to form the address of the first storage location to be stored into.

A storage word is 64 bits long (excluding parity), and a GR is 32 bits long; therefore, two GRs can be stored into one storage word. The first GR can be stored in the right or left half of the first storage word, and the last GR can be stored in either the right or left half of the last storage word. This leads to differences in the starting and ending sequencing. If H REG bit 21 is a ZERO, the first GR is stored in the left half of the first storage word; if H REG bit 21 is a ONE, the first GR is stored in the right half. The last GR can be stored in either the left or right half.

In cycle T1, the address is placed in SAR and IC is blocked. In cycle T2, T1 and T2 are blocked. When I GO is generated, IE1 turns on to denote the first, or first two, IE cycles (first cycle only if H REG bit 21=1, first two cycles if H REG bit 21=0.) IM1 or IM2 also turn on depending upon H REG bit 21, and MODAR is turned on by IM2.

When H REG bit 21=0, IE1 and IM1 turn on, the latched output of which causes BR 1 to be incremented by 1 at the next A clock, and sets the storage marks for bits 0-31. GR R1 is gated through the GBL to the RBL and into the M REG at the start of the second IE cycle. In the second IE cycle, IM1 turns off and IM2 turns on, the latched output of which causes a store request to be made and marks 32-64 to be set. GR1 + 1 is gated to the M REG at the same time as GR1 is gated from the M REG to the K REG H0, at the start of the third IE cycle. BR 1 is incremented + 1. In the third IE cycle IM2 turns off, IM 1 turns on and stays on until an accept is received, keeping the store request up. At the start of the fourth IE cycle, GR1 + 2 is gated into the M REG and GR 1 + 1 is gated from the M REG to the K REG L0. When an accept is received, the K REG is gated to the SBIL (storage bus in latch), IM 1 turns off and IM2 turns on, which causes BR 1 to be incremented + 1; marks 0-31 to be set for the next store; the H REG to be incremented + 1 by way of the incrementer; the incrementer gated to both SAR and the H REG; and causes another store request to be made. GR R1 + 2 is gated to the K REG HO and GR R1 + 3 is gated to the M REG. IM 1 and IM 2 keep alternating until BR 1 = IR2, which indicates the end of the store multiple operation. When BR 1 = IR 2 and IM 2 is on, IE3 is turned on at the start of the next IE cycle; if IM 1 is on, IE3 is turned on with an accept. The latched output of IE 3 unblocks T1 when IM2 is on. IE3 together with IM1 cause T2 and IC to be unblocked with an accept. An accept and IE3 turn on IEL.

If H REG bit 21=1 at the start, IM2 and IE1 are turned on by I GO, which effectively skips over the first cycle of the routine as described above, and causes the first GR to be set into the K REG L0.

When I GO is generated, E GO is also generated, which turns on the first fixed point trigger for one cycle. EM1 and EM2 then alternate as do IM1 and IM2. The E unit increments ER 1 and will receive a compare when all but the last store is done. For the last store, the store sequencer is turned on and, with an accept, ELC is generated; ELC coincides with IEL in this case. FIG. 305 and FIG. 306 shows the timing of Store Multiple.

13.2.3.10 Load Multiple

Load Multiple is an instruction in the RS format in which R1 defines the first GR to be loaded and R3 defines the last. The contents of GR B2 (B 2 0) is added to D2 to form the address of the first storage location from which the GRs are to be loaded. Paragraph 2 of the preceding section is applicable to Load Multiple except that instead of storing, the GRs are loaded from storage.

In the T1 cycle, the first address is set into SAR and the H REG, a fetch request made and the IC is blocked. In the T2 cycle, T1 is blocked and the H REG contents are incremented by 1 in the incrementer, the result being set into SAR and the H REG.

Unlike a store multiple operation, the IE unit may or may not be required to start a storage cycle for a Load Multiple operation. I Execution will make one or more fetches if H REG bit 21=0 and at least three GRs are to be loaded or if H REG bit 21=1 and at least two GRs are to be loaded. The GRs are loaded by the E unit, the path being from storage to the J REG (H0 or L0) through the adder to the K REG H0, and to the GR. The GR to be loaded is controlled by ER 1.

When I GO is generated and H REG bit 21=0, IE1 and IM1 are turned on, which causes BR 1 to be incremented at the start of the next IE cycle. If BR 7 = IR 2 at the start of an IE cycle, IEL is turned on and no other controls are generated. In the second IE cycle, IM1 turns off, IM2 turns on, BR 1 is incremented by 1 and a fetch request is made. In the third IE cycle, IM2 and IE1 turn off, and IM1 turns on which holds the fetch request until an accept is received. When an accept is received BR 1 is incremented by 1, IM1 turns off, IM2 turns on, H REG is incremented by 1 in the incrementer, the incrementer is gated to SAR and the H REG and, if BR 1 IR2, another fetch request is made. This process continues until BR 1 = IR2, in which case IEL is turned on either when IM2 is on, or when IM1 is on and an accept is received. IEL unblocks the IC and the ELC unblocks T1.

In single cycle, IM1 alone makes the fetch request to prevent the I unit from fetching words too fast for the E unit to put away.

If H REG bit 21=1 at the start, IM2 and IE 1 are turned on by I GO which effectively skips the first cycle (of an H REG bit 21=0 start), and the first GR is loaded into the K REG H0 from the J REG L0 (instead of from the J REG HO).

E GO is generated at the same time as I GO, and the first fixed point trigger is turned on until J LOADED or J ADV is received. IM1 and EM 2 then alternate in the incrementing of ER 1 and the loading of GRs until ER 1 = IR2. This causes 1 to be turned on to load the last GR. FIG. 307 shows the timing of Load Multiple.

13.2.4 CHANNEL INTERRUPT PRIORITY

The channel interrupt priority circuits are composed of seven triggers and priority network. Six of these triggers, called CH IRPT LCHS, are assigned to the six selector channels that may be attached to the computer. The seventh trigger is the channel interrupt outstanding latch (CH IRPT OUTST) which notifies interrupt controls of any channel interrupt present.

In order to set one of the CH IRPT LCHS: the interrupt line from the associated channel must be active; the channel must not be masked off by the System Mask; priority could not have been granted to any other channel; the reset must not be active; and a B clock must be present. The reset, which resets the priority A triggers and channel interrupt outstanding latch, is controlled by IE and interrupt controls, and is ANDed with an A clock. The channel interrupt outstanding latch is set if any of the CH IRPT six latches are set, interrupt controls are not blocking the set, and an A clock is present.

Between the CH IRPT latches and the CH IRPT OUTST latch is the priority network which allows more than one of the CH IRPT LCHS to be set and only the one with the highest priority to be serviced. Channel 1 is assigned the highest priority, channel 2 the second highest, and so on, through channel 6. The output of the priority network is indicated so only the channel which has been granted priority will be seen even if more than one CH PRI LCH is set.

When the interrupt controls service a channel interrupt, an interrupt response is sent to the priority network where it is gated with the channel which has been granted priority and sent to the selected channel as an interrupt response. The designation of the channel which has been granted priority is encoded in three bits and sent to bits 21 to 23 of the interrupt code in the PSW together with a generated parity bit.

14.0 INTERRUPTIONS

14.1 INTERRUPTION HANDLING

The sections hereunder describe the response of the system to both internally and externally generated interruption signals.

Interruptions are first defined in general terms; then the individual signals are further defined, classified, and assigned servicing priorities consistent with basic architectural criteria set forth in said System/360 Manual and the implementation plan of the present embodiment. The detection of interruptions and the means by which interruption processing is initiated are examined next, followed by detailed descriptions of the specific sequences associated with each type of interruption. Actual circuits are described in sections hereunder.

14.1.1 THE INTERRUPTION FIXED SEQUENCE

Interruptions can be generally defined as those signals which cause the CPU to suspend (or interrupt) normal instruction processing and enter into a fixed-sequence routine. Their purpose is to change the CPU state according to certain specified conditions which may arise inside or outside of the system.

In general, the fixed sequence consists of storing the old PSW, which contains an interruption code field defining the cause of the interruption, and fetching a new PSW with which to continue processing. Those interruption signals which result from the detection of program exceptions normally follow this sequencing pattern. A number of other situations, however, such as machine malfunctions, instruction recoveries, the Supervisor Call instruction, timer advance requests, and the initial program load (IPL) procedure also rely on utilization of the interruption system and may cause the fixed sequence to be specifically modified. These cases are not really interruptions, but since they are treated as interruptions by the CPU, they are considered as such for purposes of further discussion.

14.1.2 INTERRUPTION CLASSIFICATION

The architectural definition of a system in said System/360 Manual discusses interruptions and assigns permanent storage locations for the PSW's stored and fetched during interruption processing. These interruptions, and also those conditions which are treated as interruptions are classified according to the signal source and their relationship with normal instruction processing. With the exception of two cases, which are handled in an individual manner, interruptions fall within three classes, as set forth in the following enumerated paragraphs.

1. Interrupt From I: The first class, I IRPT FM I, represents those program-caused interruptions detected solely in the I unit during T1 and T2. These interruptions signify that no valid instruction execution may follow. The instruction is suppressed and the fixed-sequence interruption routine is conditioned. Examples of interruptions in this category are those caused by an invalid instruction address, an invalid operation code, and the Supervisor Call instruction.

2. E Interrupt From E: Another class, E IRPT FM E, represents those program interruptions detected solely in the E unit during the execution of an instruction, such as, for instance, overflows, divide checks and invalid data addresses. All E IRPT FM E cases are E unit program interruptions (E PGM IRPTS).

3. e interrupt From I: The final class, E IRPT FM I, is more general than the others and represents those interruptions which are associated with execution-end detection but are observed strictly within the I unit interruption controls. These signals mainly occur asynchronously with respect to CPU processing. Included are signals external to the CPU, such as Console Interrupt, I/O Interrupt, and Timer Advance Request, as well as internal interruptions such as Invalid Store Address (CPU INV STR).

4. exceptional Cases: The two remaining cases, which do not belong in any of the above classes, are the machine check interruption and IPL PSW loading. Since a machine check does not evolve from normal processing, it cannot be assigned to any of the three foregoing classes. During the IPL procedure, interrupt sequencing is used to fetch and check the PSW and to start CPU processing. Both of these cases follow CPU resets and are initiated by controls external to the interruption apparatus, although they utilize said apparatus.

5. WAIT: In addition, the running/waiting status of the machine is monitored by circuits within the interruption apparatus.

14.1.3 INTERRUPTION

14.1.3.1 Priority Assignments and Classes

Since it is possible for several interruption signals to occur during the same instruction, a priority selection system is necessary to provide exclusive servicing privileges for only one interruption at a time. In addition, E PGM IRPT and I PGM IRPT must be assigned priorities within their classes since more than one may arise concurrently. E PGM IRPTs are weighted by the E unit such that the interruption controls service only one interruption for a given instruction. The weighting of I PGM IRPT is discussed later in this section.

Because of overlapped operation, the I unit is one sequential instruction ahead of the E unit, and therefore, all program interruptions associated with E unit executions take precedence over all other interruptions detected during normal processing. Note that CPU SAP and CPU INV STR may relate to E unit execution.

14.1.3.2 Interruption Priority Group Descriptions

Each priority level group is discussed in this section with respect to the action taken by interruption controls and, where appropriate, the reasoning upon which the priority assignment is based. The interruptions are described in detail in said SYSTEM/360 Manual.

1. Machine Check: This interruption causes a Machine Old PSW to be stored with an all-zero interruption code and a Machine New PSW to be fetched. Since it always follows a CPU reset, the incidence of all other interruptions is precluded, and it automatically acquires top priority.

2. IPL Load PSW: Following the I/O operation which loads storage, the Initial Program Load PSW is fetched. Since no other interruptions can occur at this time, IPL also occupies the top priority position along with MCH CHK.

3. storage Address Protection: Of all the program-caused interruptions, this has highest priority. When the program attempts to store into a protected area of storage, the BCU signals with a CPU SAP check. This is forwarded to the interruption controls and causes the exchange of Program PSW's with the Protection code stored in the interruption code of the old PSW. The high priority granted this interruption stems from the fact that it is frequently futile to determine which Store instruction is associated with the interruption. Accordingly, the length code bits in the old PSW are set to zero.

4. Invalid Store Address: This BCU interruption causes an exchange of Program PSW's after the Addressing interruption code first is set in the old PSW. If both CPU SAP and CPU INV STR occur on the same storage operation, the storage transfers only CPU INV STR, and does not send an ADVANCE, so no CPU SAP can be received. Therefore, if both signals are simultaneously present in the interruption controls, the CPU SAP must be associated with a previous instruction or a previous storage request within the same instruction, and it will therefore receive priority.

5. E Program Interruptions: All interruptions discovered during an E unit execution belong in this category (E IRPT FM E). The interruption codes applicable to this class include: Addressing (relating to operands), Specification (only decimal types relate to the E unit), Data, Fixed-Point, Overflow, Fixed-Point Divide, Decimal Overflow, Decimal Divide, Exponent Overflow, Exponent Underflow, Significance. And Floating-Point Divide. As stated heretofore, although several E PGM IRPTs (E IRPT FM E) may occur on the same execution, only one is selected for transmittal to the interruption controls. A single E IRPT FM E control line and the appropriate interruption code bits provide all the necessary inputs for servicing these exceptions. If priority is granted to an E IRPT FM E, the interruption code bits will be set into the PSW when the interruption handling begins, at the end of the fixed sequence.

6. External Interruptions: Of the nonprogram-oriented interruptions, EXT IRPTs are granted highest priority and include Timer (count completed), Console, and six external signals (which can relate to anything the user desires). The interruption code consists of an independent bit for each EXT IRPT source, and External PSW's are exchanged (store old, fetch new). If there are concurrent interruptions under this priority class, all appropriate code bits are set. Note that a TIM IRPT can only occur following a TIM ADV REQ (outlined below) and, therefore, has virtual priority over all other interruptions.

7. Timer Advance Request: The Timer word is fetched from storage using the interruption sequence controls normally used for PSW fetches. The actual advance of the Timer comprises decrementing the timer word which is performed in the E unit, and which also stores the Timer word at the address previously calculated by the I unit. Following the advance, the interruption controls are again initiated and a Timer interruption may be recorded if the value in the timer storage word has changed from positive to negative as a result of the updating.

8. Input/Output (Channel) Interruptions: If any of the channels have interruptions pending, and CH IRPTs have current priority, Input/Output PSW are stored and fetched and an interruption code for identifying the particular channel and unit address is set into the old PSW before it is stored. Individual CH IRT CH IRPT priorities are determined in the IE unit (I execution area of I unit).

9. Recovery: This condition (RCVY) is observed during the last cycle of an execution and signifies, to the I unit controls, that undesired data is contained in the AB register. The recovery situation exists (a) when data is stored into a storage word which has already been fetched, as detected by a program store comparison and (b) following an Execute instruction which does not reach a branch instruction. These conditions are called "recovery only" (RCVY ONLY) implying that PSW exchanges are not to be made. The recovery situation also exists following the loading of all new PSW's, which occurs after the LOAD PSW instruction and following the interruption fixed sequencing: in the former case, the IE unit, which performs the LOAD PSW function, conditions the recovery. The recovery process involves fetching an instruction from the address designated by the instruction counter. Note that any execution interruptions will take priority over the recovery so that the IC fetch is deferred until a new ICR value is obtained in a new PSW.

10. i program Interruptions: Because of overlapped I-E operation, I PGM IRPTs are associated with the instruction following the current one. Therefore, priority is granted to I PGM IRPTs only if there are no outstanding interruptions due to current instructions.

Tests are made during I unit T1 time to detect invalid instruction addressing, invalid syllable resolution (erroneous boundary specification) of the instruction address, and invalid operation codes. If more than one of these is concurrently present, they are assigned priority in the order listed. During T2, further examinations are made for Privileged-Operations (provided the CPU is not in Monitor Mode), and Execute instruction which is the subject instruction of another Execute, or a Specification violation involving either the R1 or R2 fields or the operand effective address calculated during T1. Of these, the first two are mutually exclusive and are granted the same priority, which is higher than that for Specification. Any T1 interruption blocks any T2 interruption from affecting its processing. Program PSW's are exchanged in all cases with the appropriate interruption code stored in the old PSW, before the exchange.

11. Supervisor Call: This instruction results in the exchange of Supervisor Call PSW's with the interrupt code field containing the R1 and R2 fields from BOP and IOP, respectively. It is exclusive of all other T2 interruptions (e.g. PGM IRPT) and is not processed if a T1 interruption occurs. The purpose of this instruction is primarily to permit exchanging a new, monitor-mode PSW for the old, problem-mode PSW.

14.1.4 INTERRUPT SEQUENCE INITIATION

The CPU may enter into interrupt sequencing through three primary "routes:" as a result of an execution last cycle (ELC) test for E IRPT FM E (which is developed in the E unit) and E IRPT FM I signals gated by CTRL L CYC; at the normal I to E transfer when an I IRPT FM I has been detected; or through forced entrance, such as a MCH CHK interruption or an IPL load PSW operation.

A secondary entrance route is provided by a test for additional outstanding interruptions during the last cycle of the interruption processing sequence itself, gated by IRPT L CYC.

Reference is made to the general timing chart, FIG. 362, throughout the discussion of the sections hereunder.

Certain interruption conditions are masked by bits contained in the PSW; i.e., the mask bit of a particular interruption must be a 1 or the interruption will be ignored by the CPU. The following table lists the masks which affect interruptions either directly or through other logical areas.

14.1.4.1 EXIT-- E Last Cycle Test

During a control last cycle (CTRL L CYC), which represents the absolute last cycle of both the I and E execution areas (ELC, IEL, BR L CYC), any interruption signals of the E IRPT FM E and E IRPT FM I classes are observed. If one or more are found to exist, the execution interrupt trigger, EXIT, is turned on. EXIT means the "exiting" from normal sequencing, the exiting occurring as a result of an E IRPT FM E or an E IRPT FM I, sensed at CTRL L CYC.

Also at this time, several block conditions are set to insure breakaway from normal processing and commencement of the fixed interruption sequence. Breakaway is effected by blocking all of the following: the start signals to the execution units, updating of the ICR, changing of the length code in the PSW, and requests to storage.

Additionally, an interruption priority hold (IRPT PRI HOLD) trigger is set at the turn on of EXIT. Its purpose is to eliminate interferences from other interruptions which may arise while the current one which caused EXIT is being serviced. These other possibly-interferring interruptions are CH IRPTs, which are directly blocked by the latched output of IRPT PRI HOLD in the IE unit, and timer advance requests and asynchronous external interrupts, which are deferred by blocking, with LCH PRI, the setting of the bipolar latches which are used as outputs of their respective interruption triggers. When IRPT PRI HOLD is turned off near the end of the interruption sequence, these latches are permitted to set and consideration is given to those interruptions present during IRPT L CYC. E PGM IRPTs cannot interfere because they would have occurred in time for the CTRL L CYC test, and EXIT blocks I IRPT FM I processing. Therefore, E time interruptions are exclusively presented to the fixed sequence controls following EXIT.

Except in the case of recovery-only conditions, EXIT leads directly into interrupt cycle 1 (IRPT CYC 1) of the fixed sequence at which time the interruption code bits are set into the interruption code field of the old PSW and an interrupt reset (IRPT RST) prevents the I unit from continuing with normal processing.

14.1.4.2 IRPT FM I Test

If an interruption condition is detected during T1, the interruption code bits (see preceding section) corresponding to the highest priority interrupt are set into the PSW at TON T2. The I PGM IRPT trigger is also set to block any T2 interrupts from affecting the code bits and this trigger is also used for later PSW address calculations. Later, the I IRPT END trigger is set at the I to E transfer for entrance into the interrupt fixed sequence. Note that some interruptions are sensed at T1, but are not acted upon until I to E XFER.

For the case where no interruptions are present during T1 but are detected during T2, both I PGM IRPT and I IRPT END are set at I to E transfer, and the code bits associated with the highest priority T2 interruption are set into the PSW. Except for the fact that the code bits have been preset, I IRPT END then functions similarly to EXIT as an I unit sequencing reset (via IRPT RST) and as a set condition for IRPT CYC 1. Executions and storage requests are blocked in the event of an I IRPT FM I. Either I IRPT END or EXIT, depending which is set, is turned off at the start of interrupt sequencing by IRPT RST, when no CPU storage request is outstanding. The I PGM IRPT trigger remains on until the completion of the fixed sequence and is then reset by IRPT END RST, which is caused by IRPT CYC 5.

14.1.4.3 Forced Entrance

Forced entrance into the interrupt sequence, for processing machine check interrupts and IPL load PSW, is attained by direct turn on of IRPT CYC 1. Any processing interference by asynchronous signals, such as TIM ADV REQ and I/O (or CH) IRPT, is prevented.

14.1.4.4 Interruption Last Cycle Test

The IRPT L CYC test closely resembles that made during a CTRL L CYC.

Certain interrupts of the E IRPT FM I class (CH IRPT, TIM ADV REQ, TIM IRPT, CONS IRPT, and other external signals) are observed and may again set EXIT and be processed according to established priority.

14.1.5 INTERRUPTION SEQUENCING

FIGS. 362-372 illustrate the following discussion of interruption sequencing.

14.1.5.1 Normal Sequencing

The general interruption processing plan (FIG. 362) consists of seven sequence triggers. They control the storing, loading and checking of PSW's and either the return to normal processing or the recycling of interruption processing to service additional outstanding asynchronous interruptions. Other control triggers are used to handle channel communications on I/O interruptions, timer updating, and irregular sequencing, such as the PSW fetch during an IPL procedure.

Both PSW fetches and PSW stores reference even storage locations, which results in serial, rather than interleaved, storage timeout patterns. By fetching the new PSW to the J register before storing the old PSW, the timeout of storage for the store operation may be overlapped with a parity check on the new PSW.

IRPT CYC 1 and IRPT CYC 2 administer the fetch operations which will return a new PSW to the J register. During IRPT CYC 1, the new PSW address, encoded according to the highest priority interruption signal, is gated through the address adder (AA) into the storage address register (SAR) to meet the fetch request at the turn-on of IRPT CYC 2. IRPT CYC 1 is always one machine cycle in length; IRPT CYC 2 stays on until the retch accept is received from the BCU.

IRPT CYC 3 and IRPT CYC 4 proceed with the store operation for the old PSW. During IRPT CYC 3 the store address is sent to SAR through the AA and the right half of the PSW (RH PSW) is flushed through the incrementer (INCR) to the high-order section of the K register (K HO). A store request is initiated at the turn on of IRPT CYC 4 while manipulations are performed to move the remainder of the old PSW into the K REG. This is accomplished by setting a trigger in the E unit, which shifts K HO to K LO (K REG low order), while gating the left half PSW (LH PSW) through the INCR to K HO. IRPT CYC 4 then holds up until the store accept comes from the BCU, which follows the fetch timeout and restarting of storage. Meanwhile, the fetched PSW returns to the J register where it also awaits the store accept which will allow it to be set into the PSW register. Once the store accept arrives, the interruption controls are no longer concerned with storage. Since the PSW's are located within a protected area of storage, the protection keys are inhibited during the PSW store operation.

IRPT CYC 5 and IRPT CYC 6 are used to control checking of the new PSW and to reset the interrupt triggers being serviced (IRPT END RST). Checking is accomplished by gating both halves of the PSW through the INCR and sampling the error line. The channel interruption mechanism is reset to allow for changes in the system amask (PSW bits 1-6). All program interrupt triggers are reset at this time and IRPT PRI HOLD is reset to allow the established priorities to change. If any interruptions are still outstanding they will be observed during the last cycle test, EXIT will be set and the CPU will proceed directly through another interruption sequence.

At the turn-on of IRPT L CYC, a CPU recovery is initiated. All blocks of I unit controls, which are established earlier in the sequence (during EXIT or I IRPT END), are removed to allow processing to continue normally.

The interruptions which are processed by pattern as described in this section are:

1. E program interruptions

2. I program interruptions

3. BCU (CPU INV STR and SAP)

4. external (Timer, Console, etc.)

5. Supervisor Call instruction

14.1.5.2 I/O Sequencing

The processing of CH IRPTs (I/O or channel interruptions) departs from normal sequencing only in that a pause is injected between IRPT CYC 1 and IRPT CYC 2 (before the fetch request is made), during which the channel originating the interruption performs its own interruption routine, as shown in FIG. 363. The unit address bits used as the old PSW interrupt code are not available until the channel has completed its processing, as indicated by receipt of a CH REL signal, but are set into the PSW when processing resumes with IRPT CYC 2.

When a CH IRPT has top priority (established during EXIT). A channel interrupt response (CH IRPT RSP) trigger is set coincidentally with IRPT CYC 1. This trigger remains on (although IRPT CYC 1 turns off on the advent of the next A clock pulse) and serves as a "go" signal, for the channel to service its interruption.

When the channel has completed this processing, it transmits a channel release (CH REL) signal to the interruption controls. The CH REL signal turns on a one-cycle CH IRPT REL trigger which conditions interrupt controls for resumption of the normal interrupt sequence. The CH IRPT RSP trigger turns off at the same time as CH IRPT REL.

14.1.5.3 Timer Advance Request Sequencing

In the case of a TIM ADV REQ (FIG. 364), the interruption controls are used to fetch the timer word and to initiate a recovery. Actual updating takes place within the E unit under control of independent sequencers.

To initiate the updating process, a timer oscillator pulse which sends an INT TIM ADV signal (Interval Timer Advance) in the PDU, trips a single-shot to the interruption controls, causing the TIM ADV REQ trigger to be set. Priority is determined, as usual, during EXIT, and if the request for timer updating has priority, the timer word is fetched in the manner of a PSW.

At the end of IRPT CYC 2, a transfer is made to the E unit controls which wait for the timer word to return to the J register. Upon this transfer, the TIM ADV REQ trigger and the IRPT PRI HOLD trigger are reset to allow detection of other interruptions, when sequencing is resumed following the advance. When the J register is loaded, the data is transferred to the M register decremented in the MA and then sent to the K register. Meanwhile, a store request is made referencing the same address which was previously set into SAR for the timer fetch. A check of the contents of the K register is made following the store accept. Upon receipt of a control signal from the E unit and of the store accept, interruption processing continues. A recovery is preconditioned and IRPT L CYC is set.

14.1.5.4 Recovery-Only Sequencing

Processing of PSC (program store compare) and XEQ OP (RCVY) situations (see FIG. 365) is accomplished during the EXIT cycle by resetting the necessary controls in the I unit with IRPT RST and turning off the BLK TIM and BLK ICM triggers. No further interruption processing is required. Note that all concurrent I unit detection of program interruptions is halted and is reset on RCVY priority as well as on all other execution interruptions. The PGM STR COMP and XEQ OP triggers are reset as the recovery is initiated.

14.1.5.5 IPL Load PSW Sequencing

Those portions of the interruption controls which are capable of fetching and checking a PSW and of initiating a recovery are utilized as a part of the IPL procedure. Sequencing is initiated by an IE IPL START SEQ signal from the IE unit, which forces IRPT CYC 1 on FIG. 366. The usual fetch request is made, and IRPT CYC 2 stays on until the fetch accept is received. Then the normal sequence is broken (no store is to be made), with the IPL BUF (buffer) trigger filling the storage timeout gap. When the word returns to the J REG it is set into the PSW, and sequencing continues in a normal fashion with IRPT CYC 5.

14.1.5.6 Machine Check Interrupt Sequencing

A MCH CHK interrupt is processed exactly as a normal interrupt except for the manner in which entrance is made to IRPT CYC 1. For this purpose, a trigger is used which has two outputs, a normal trigger line and an output which represents the initial L clock pulse following trigger turn on. The latter signal, MCH CHK START, is used to set the interrupt code bits to zero and to turn on IRPT CYC 1; while the normal signal MCH CHK IRPT, sets the PSW address bits. The MCH CHK trigger is reset with IRPT END RST.

14.1.6 WAIT STATUS

Bit 14 of the PSW indicates, when it is a one, that the CPU is in the wait state, rather than the running state. In the wait state the CPU, does not execute instructions, but remains suspended until an interruption occurs. The only interruption which may occur are External (Console, Timer, and external signals), and I/O. These interruptions initiate the interruption fixed sequence which results in the loading of a new PSW that may or may not change the running-waiting status of the CPU, depending on the value of bit 14 or the new PSW. In the wait state the timer is advanced normally without affecting the wait status.

Associated with the status bit in the PSW is a WAIT trigger within the interruption controls. This trigger reflects the true status of the CPU since there is a delay between the setting of the PSW wait bit and the halting of processing, and there is also a delay between the resetting of the wait bit and the resumption of normal operation.

After each setting of a new PSW, the wait bit is observed before normal processing may be continued. At the end of the LOAD PSW instruction, the wait bit prevents instruction fetching for the new ICR value and the WAIT trigger is set if no interruptions require servicing. At the end of every interruption sequence which fetches a PSW, the wait bit is again observed and, if it is a ONE, the WAIT trigger is set when no further interruptions are outstanding. Any of the interruption signals mentioned above arising in the wait status will reset the WAIT trigger and set EXIT which leads into the interruption fixed sequencing.

If the CPU is in the wait state and the HALT trigger is set, all processing is inhibited. This includes external and I/O interruptions and timer advances. All operation is deferred until the HALT trigger is reset, which is accomplished by setting the IRPT PRI HOLD trigger. When processing resumes, the highest priority interruption that is outstanding will be serviced.

14.1.7 STORAGE INTERLOCK

An interlock is provided at the entrance to interruption sequencing for two reasons:

1. If a store operation is in process, no interruptions may be handled until sufficient time is allowed for a SAP check to return. This avoids premature termination of the protection interruption.

2. If a fetch is outstanding, sufficient time must be allowed before entering the interruption routine in order to nullify the effects of the returning word. This is accomplished the the CPU COMM-BUSY line (from the BCU) which designates that the CPU has a storage operation in process. The interlock is provided during the setting of EXIT and I IRPT END which remain on until the BCU control drops.

14.2 INTERRUPTION CIRCUITRY

The sections hereunder describe circuits which implement above interruption handling in this system as briefly described in Section 8.1.1.0. The first circuits to be described will be those relating to the entrance routes, that is, to the methods through which interruptions are actually recognized, masking effected, priorities determined, proper fixed-sequence starting latches set, and so forth. As described in above sections, E unit execution interruptions must take precedence over I unit interruptions due to the fact that the E unit is one instruction ahead of the I unit. This does not hold for external interruptions, timer advance requests, input output interruptions, machine check and initial program loading due to the fact that these are asynchronous with respect to the I unit and the E unit, or, as in the case of the machine check, no further sensible processing can take place in any event. It is to be noticed that E unit interruptions are recognized by CTRL L CYC, which exactly spans one machine cycle, whereas I unit interruptions of the I IRPT FM I type are recognized at the I to E transfer, which occurs from the second half of a T2 cycle to the first half of the following cycle. Thus, priority as between these interruptions is settled by the fact that CTRL L CYC appears a half-cycle before I TO E XFER. Thus, at a given instant of time, as far as normal interruptions are concerned, the interruptions sense that CTRL L CYC would normally have precedence. This is where the discussion of the circuitry begins.

14.2.1 ENTRANCE, PRIORITIES, AND MASKING

Due to the fact that the recognition in the interrupt circuitry of a particular interruption is achieved in conjunction to some extent with masking and with establishment of priorities, circuits directly related with the establishment of the interruptions fixed sequence include to some extent all three of these factors. Therefore, the discussion in the sections hereunder which request priorities, and then describe the actual receipt of interruption signals and the effect caused thereby.

In the system, the effects of having to recognize an E unit interruption of a first instruction which is being executed prior to recognizing an I unit interruption of a following instruction which is being prepared for execution, the absolute priority which necessarily relates to machine check (failure-oriented) and initial program loading of the PSW, the definitions of interruption priorities as set forth in said System/360 Manual, and all other factors are resolved by the assignment of absolute priority to the various interruptions. The absolute priority assignments take into account the timing of the system, and all other factors which must be considered.

14.2.1.1 Absolute Interruption Priorities (Table)

The absolute priority of various instructions is set forth in the following table, wherein priority assignments 6-8 relate to external interruptions, which are shown there due to the individual manner in which these are handled, although there is no difference between the CONS IRPT, TIM IRPT, and EXT SIG.

14.2.1.2. effective Interruption Priorities and Entrance Routes (Table)

There are four different distinct cycles within the operational timing of this system wherein interruptions may actually be sensed for the purpose of acting thereon. These are: CTRL L CYC, IRPT L CYC, I TO XFER (sensed at either T1 or T2), in that order of priority. The various interruptions (and noninterruption functions which are handled by the interruption circuits) are set forth in the following table, highest priority being at the top of the table, and descending to lowest priority at the bottom of the table.

Ctrl l cyc-- exit-- b irpt

e irpt fm e and E IRPT EM I (includes all except I IRPT FM I, below)

Irpt 1 cyc-- exit-- a irpt

asynchronous e irpt fm i

ext irpt

cons irpt

tim irpt

ext sig

tim adv req

ch irpt (i/o)

i to e xfer-- i irpt end--

t1-- i pgm irpt types of I IRPT FM 1

Inv adr (relating to instruction address)

Spec (relating to instruction address boundary)

Inv op

t2-- i irpt fm i

i pgm irpt

priv op (if PSW 15 = 0)

Xeq to xeq

spec (relating to R1, R2 or operand address of T1)

Sup call (svc instruction)

14.2.1.3 A IRPT Group and B IRPT Group FIG. 326, FIG. 327, FIG. 320, and FIG. 324, FIG. 328

In FIG. 324, THE B interrupt group, which includes all interruptions with priorities from 1 through 11 (which can be seen in the chart of Section 14.2.1.1 to comprise all interruptions except I IRPT FM I) is manifested by a signal on the B IRPT line by an OR-circuit 1 which is responsive to signals relating to priority groups 1-4, 7-8, 9-10 and 11. These signals appear on IRPT PRI 1-4, IRPT PRI 5-8, IRPT PRI 9-10, and IC RCVY REQ lines. Similarly, an OR-circuit 2 generates a signal on the A IRPT line, which signal indicates the asynchronous B IRPT FM I group of interruptions; as seen in the chart of Section 14.2.1.2, this comprises the external interruptions (CONS IRPT, TIM IRPT, EXT SIG), timer advance requests and input/output interruptions (CH IRPT). The OR-circuit 2 responds to the signal on the IRPT PRI 9-10 line and to a signal on a EXT IRPT line.

The IRPT PRI 1-4 line is energized in FIG. 327 by an inverter 1 in response to a signal on a NOT IRPT PRI 1-4 line in response to an AND-circuit 2, the inputs to which comprise signals indicating the absence of the various interruptions having priorities between 1 and 4. Specifically, the AND-circuit 2 is responsive to signals on the NOT CPU SAP, NOT CPU INV STR, NOT MCH CHK IRPT, and NOT IPL LCH lines. The output of the AND-circuit 2 is also applied to an AND-circuit 3 which responds as well to a signal on an E IRPT FME line from the E unit, so as to recognize the case where there is an E program interruption (E IRPT FM E, with priority of 5) and no interruptions of any higher priority. The AND-circuit 3 indicates that the E program interruptions have the highest priority by generating a signal on the E PGM IRPT PRI line.

In FIG. 320, a signal is generated on the IRPT PRI 5-8 line by an inverter 1 in response to a signal on a NOT IRPT PRI 5-8 line which is generated by an AND-circuit 2. The AND-circuit 2 responds to signals on the NOT EXT IRPT and NOT E IRPT FME lines. Thus, the signal on the IRPT PRI 5-8 line is indicative of either an external interruption or an E unit interruption preset at the input to the AND-circuit 2.

The circuit of FIG. 320 also supplies proper priority as between the external, timer, and channel interruption by means of a pair of AND-circuits 3, 4, which can operate only if there is a signal present on the NOT IRPT PRI 5-8 line. The AND-circuits 3, 4 also require a signal on the NOT IRPT PRI 1-4 line to indicate that no priority later than that of the external interrupts is outstanding. The AND-circuit 3 responds to a signal on the TIM ADV REQ LCH line to generate a signal on the TIM ADV REQ PRI line, indicating that there being no priority between 1 and 8, the timer advance has priority. The AND-circuit 4 must also recognize that the timer advance has not been granted priority by means of a signal on a NOT TIM ADV REQ LCH line, and if all of these other inputs are present, then the AND-circuit 4 can generate a CH IRPT PRI signal in response to a signal on a CH IRPT OUTST LCH line.

The signal on the IRPT PRI 9-10 line is generated in FIG. 326 by an inverter 1 in response to a NOT IRPT PRI 9-10 signal from an AND-circuit 2 which in turn is responsive to signals on the NOT TIM ADV REQ LCH and NOT CH IRPT OUTST LCH lines. Thus, interrupt priority 9-10 will be provided if there is either a timer or a channel interrupt input to the AND-circuit 2 in FIG. 326.

The output of the AND-circuit 2 in FIG. 326 is also applied to an AND-circuit 3 along with other priority signals on the NOT IRPT PRI 1-4 and NOT IRPT PRI 5-8 lines. If there is a signal input on a IC RCVY REQ line, then the AND-circuit 3 generates a signal indicating that priority has been granted for instruction counter recovery on a RCVY PRI line.

The IC RCVY REQ signal is generated in FIG. 326 by an AND-circuit 4 provided the IC recovery request latch is set as indicated by a signal on the IC RCVY REQ LCH line. The AND-circuit 4 also requires, however, an input from an OR-circuit 5 which may respond either to the absence of an execute instruction as indicated by a signal on the NOT XEQ OR LCH line, or to the output of an AND-circuit 6 which recognizes that there is no I IRPT FM I outstanding by means of signals on the NOT I PGM IRPT LCH and NOT BD SUP CALL lines. Thus, although recovery is shown in the chart of Section 14.2.1.1 to have a priority of 11, recovery is not recognized in the interrupt circuit whenever there is an I IRPT FM I. The output of the OR-circuit 4 is also applied to an inverter 5-7 so as to generate a signal on a NOT IC RCVY REQ line.

The external interrupt circuits are shown in FIG. 7, wherein a signal is generated on the EXT IRPT line by an OR-circuit 1 in response to any one of three AND-circuits 2-4, each of which requires an indication that bit 7 of the PSW register is equal to a 1 as indicated by a signal on the PSW 7 line. The reason for this is that no external interrupt may be taken unless the corresponding mask bit (PSW 7) is a 1. The external interruptions include external signals, the interrupt key on the console, and timer interrupts which result from a timer advance which has caused the setting of the timer storage word to change from a positive value to a negative value. These are recognized by the various AND-circuits 2-4 in FIG. 328, by responding to signals on the EXT SIG IRPT OUTST, CONS IRPT LCH, and TIM IRPT TGR lines. Thus, if any of the three external-type interrupts are present, the OR-circuit 1 will generate the signal on the EXT IRPT line. This signal is also applied to an inverter 5 in FIG. 328 which generates a signal on the NOT EXT IRPT line. This signal is further applied to an AND-circuit 6 in FIG. 328 which will generate a signal indicating that external interruptions have priority on a EXT IRPT PRI line provided that there is no interrupt priority 1- 4 and no E IRPT FM E, as indicated by signals on the NOT IRPT PRI 1-4 and NOT E IRPT FM E lines.

In FIG. 324, in addition to the A IRPT and B IRPT signals, a signal indicating that there is an execution type of interrupt from the I unit is generated on a E IRPT FM I line by an OR-circuit 3 signals is responsive to signals on the IRPT PRI 1-4, EXT IRPT, IRPT PRI 9-10, and IC RCVY REQ lines. The machine check interruption and initial program loading of a PSW are first of all not interruptions, and secondly do not fall within the E IRPT FM I group; however, the manner in which the signal on the E IRPT FM I line is utilized is such that use of the IRPT PRI 1-4 signal creates no problems, and permits simplicity of circuit design. Thus, the OR-circuit 3 recognizes all of the interruptions shown in the table of Section 14.2.1.1 except for E IRPT FM E (E program interruptions) and I IRPT FM I (I program interruptions and supervisor call).

In this section, there has been described the manner in which the A IRPT and B IRPT signals are generated, by means of recognizing interruptions of certain priority groupings, and individual interruption types, and there has also been described some of the circuitry related to that which generates the inputs for the A IRPT and B IRPT signals.

14.2.1.4 Turning on of the EXIT Trigger FIG. 358 and FIG. 333

The EXIT latch may be set either due to the fact that E last cycle (ELC) has been reached, and together with IE last cycle and branch last cycle has caused CTRL L CYC (control last cycle), or the EXIT latch may be set because of the fact that interrupt last cycle (IRPT L CYC) has been reached, and there is an asynchronous E IRPT FMI, which comprises external, channel, and timer advance type of interruptions.

The exit latch is turned on by signal on a TON EXIT line which is shown at the top of FIG. 358 to be generated by an AND-circuit 1. The AND-circuit 1 senses the fact that interrupt priority hold is not on, thereby indicating that the system is not in the wait state with the pulse latch turned on. The interrupt priority hold latch is utilized to prevent even asynchronous interruptions from returning the system from the wait state into the running state, whenever the halt latch is set.

If there is a signal on the NOT IRPT PRI HOLD LCH line, the AND-circuit 1 is free to respond to an OR-circuit 2 which in turn is responsive to any one of three AND-circuits 3-5. Each of these AND circuits indicates a different manner in which entrance into an interruption sequence governed by the exit latch may be made. The AND-circuit 3 recognizes control last cycle with a B interrupt, the AND-circuit 4 recognizes an interrupt last cycle with an A interrupt, and the AND-circuit 5 recognizes that an A interrupt has occurred while the WAIT STAT LCH is on.

The TON EXIT signal is applied to an AND-circuit 1 in FIG. 333 which will operate at A time (due to a signal on the AC line) to cause an OR-circuit 2 to set a latch 3. The output of the latch 3 is reflected in a bipolar latch 4 at the start of not L time due to the effect of the complement controlled L clock signal applied to the bipolar latch 4 on a NOT LC line. The output of the bipolar latch 4 comprises a signal on the EXIT line. The OR-circuit 2 may also be set by scan control signals because of an AND-circuit 5 which responds to signals on the J REG 32 and SC GT WD 5 lines, which causes the AND-circuit 5 to operate if there is a 1 in bit 32 of the J register during word 5 of a scan operation. The latch 3 is reset by an OR-circuit 6 in response to a signal on the CPU RST line, or in response to an AND-circuit 7 which operates at A time provided there is an interrupt pulse reset signal on the IRPT PULSE RST line.

The signal on the EXIT line (referred to elsewhere herein as EXIT) defines the entrance into the interruption 6 sequence for all interruptions except I IRPT FM I, either as a result of CTRL L CYC, or as a result of IRPT L CYC, as illustrated in the chart of Section 14.2.1.2.

The basic functions of an interruption 6 sequence may be performed either by the exit, or by I INTERRUPT END, which is equivalent to exit but relates to I IRPT FM I classes of interruptions as shown in the chart of Section 14.2.1.2. The establishment of the I IRPT END signal is described in the next section, and thereafter, functions which may be generated by either EXIT or I IRPT END are described in following sections.

14.2.1.5 Turning on I IRPT END FIG. 325, FIG. 329, and FIG. 333

In FIG. 325, the signal which will turn on the I INTERRUPT END latch is generated on a TON I IRPT END line by an AND-circuit 1 in response to concurrence of an I IRPT FROM I with the I TO E XFER, provided that EXIT has not previously turned on. This is achieved by having the AND-circuit 1 respond to the I IRPT FROM I line and to the I TO E XFER line as well as to an inverter 2 which is responsive to a signal on the IRPT RST line. The signal on the IRPT RST line is generated in FIG. 325 by an OR-circuit 3 in response to either EXIT or in response to a signal on the I IRPT END LCH line. Inasmuch as EXIT appears at the start of not L time (during early B time), the IRPT RST line will appear before the I TO E XFER signal whenever EXIT has been turned on. Thus, the output of the OR-circuit 3 applies to the inverter 2 provides priority as between the CTRL L CYC-- EXIT-type of interruptions over the I TO E XER--I IRPT END interruptions in accordance with the chart shown in Section 14.2.1.2.

The signal on the I IRPT FM I line in FIG. 325 is generated by an OR-circuit 4 in response to signals on either the SET ID T2 or I PGM IRPT LCH lines. These two signals indicate that two different classes of I IRPT FM I interruptions: the SET ID T2 signal indicates interruptions of the type which are sensed at T2, whereas the I PGM IRPT LCH signal indicates interruptions sensed at T1, as illustrated in the chart of Section 14.2.1.2. Thus, SET ID T2 and I PGM IRPT LCH identify I IRPT FROM I, which will permit the I TO E XFER to provide a TON I IRPT END signal provided that IRPT RST has not previously been generated, thus indicating that EXIT is not already on.

The I TO E XFER is also applied to an AND-circuit 5 in FIG. 325 along with an inverter 6 which responds to EXIT. This generates a signal on the GT I PGM IRPT line, which is applied to an AND-circuit 7 in FIG. 325 the AND-circuit 7 is also responsive to the SET ID T2 signal and to a signal on the NOT I PGM IRPT LCH line. Thus the AND-circuit 7 differs somewhat from the inputs to the AND-circuit 1, in that the AND-circuit 7 will not operate if I PGM IRPT has already been set. This is the manner in which the T1 and T2 interruptions are distinguished. Thus, if a T1-type of interruptions has already been sensed (prior to the I TO E XFER) then the I PGM IRPT LCH will already have been set so that the AND-circuit 7 will be blocked.

In FIG. 329, the signal on the SET ID T2 line is generated by an OR-circuit 1 in response to a signal on the BD SUP CALL line, or in response to the output of a latch 2 which is set by an AND-circuit 3 at the start of NOT L time provided there is a signal on a BD SPEC IRPT line, which signal indicates that the BOP decode circuit has sensed an invalid boundary specification. The OR-circuit 1 may also respond to a signal from an AND-circuit 4 which in turn is responsive to signals indicating privilege instruction on a BD PRIV INSTN line provided that the PSW indicates the system to be in the problem (rather than the supervisor) state, as is indicated by a signal on the PSW 15 line. The OR-circuit 1 is also responsive to the situation where one execute instruction has as its subject instruction another execute instruction, as is indicated by a signal on the XEQ TO XEQ line. The signal on this line is generated in FIG. 329 by an AND-circuit 5 in response to the BOP decode sensing an execute instruction concurrently with a previous execute instruction having set the execute latch. This is indicated by concurrent signals on the XEQ OP LCH line and on the BD XEQ line.

The OR-circuit 1 in FIG. 329 is nearly duplicated by an OR-circuit 6 (shown immediately adjacent thereto) which senses all of the inputs to the OR-circuit 1 except for the supervisor call input on the BD SUP CALL line. The OR-circuit 6 therefore recognizes T2 I program-type of interruptions (as is seen in the chart of Section 14.2.1.2). The output of the OR-circuit 6 is applied to an AND-circuit 7 together with a signal on the GT I PGM IRPT line. The effect of the OR-circuit 7 is to recognize I program interruptions of the T2-type (which exclude supervisor call) the gating of which is permitted (as shown in FIG. 325 and described hereinbefore) by the lack of EXIT when the I to E transfer appears. Notice that the T2 interruption is not prevented from providing a signal out of the AND-circuit 7 even though there may have been a T1-type of interruption; this contrasts with the AND-circuit 7 in FIG. 325 which will not provide a T2 set for the PSW if the I program interrupt latch had previously been set by a T1-type of interrupt. The output of the AND-circuit 7 in FIG. 329 comprises a T2 I PGM IRPT line which is applied to an OR-circuit 8 in FIG. 328, the output of which comprises a signal on the TON I PGM IRPT line. The OR-circuit 8 is also responsive to an AND-circuit 9 which operates with a turning on of T2 due to the signal on the TON T2 line provided there is a T1-type of interruption as indicated by a signal on the T1 IRPT line. The T1 IRPT line is responsive to an OR-circuit 10 in FIG. 329 which, in turn, may be operated by a signal on the IOP INV ADR line (indicating an instruction-related invalid address), by a signal on a ID INV OP line, or by a signal from an OR-circuit 11. The OR-circuit 11 recognizes two different types of specification interruptions from the I unit. The first of these is manifested by a latch 12 which is set by an AND-circuit 13 whenever the instruction counter register has a 1 in bit 23, indicating that the instruction counter is trying to address storage field to the byte level although all instructions are limited to the syllable level (two bytes per syllable). The second of these is manifested as the output as an AND-circuit 14 which will respond to the 1 in bit 23 of the H Register whenever there is an output from the OR-circuit 15 indicating that either a successful branch is outstanding, or an execute operation is outstanding. The OR-circuit 15 responds to a signal on the BR SUCC M LCH line or a signal on the XEQ OP LCH line. The AND-circuit 14 therefore responds to the concurrence of one of the above signals and a signal on the H REG 23 line.

A further AND circuit in FIG. 329 indicates priority granted to invalid op type of T1 interrupt: the AND-circuit 16 is responsive to an inverter 17 whenever there is no output from the OR-circuit 11, indicating that there is no invalid specification type of interruption. The AND-circuit 16 also requires an input on the NOT IOP INV ADR line; when these two inputs are present, then the AND-circuit 16 will generate a signal on the INV OP PRI line in response to a signal on the ID INV OP line.

At the bottom of FIG. 329, an AND-circuit 18 generates a signal for setting the PSW in response to interruptions of the T1 type. The AND-circuit 18 generates a signal on the T1 SET PSW line in response to signals on the T1 IRPT and NOT EXIT lines. Notice that the signal will appear on the T1 SET PSW line even through a T2-type of interruption may later by sensed; this is so because the T2-type of interruption can again set the PSW thereby changing its setting so as to reflect the condition extant within the T2-type of interruption, effectively erasing the effect of having set the PSW with the interruption code of the T1-type of interruption. The timing of the setting of the PSW is illustrated in the chart of the following section.

The signal on the TON 1 IRPT END line which is generated by the AND-circuit 1 in FIG. 325 is applied to an AND-circuit 10 in FIG. 333 which will cause an OR-circuit 11 to be operated at A time thereby to set a latch 12. The output of the latch 12 is reflected in a bipolar latch 13 at the start of not L time, so as to generate a signal on the I IRPT END LCH line. This signal is referred to herein as I IRPT END. The OR-circuit 11 is also responsive to an AND-circuit 14 which can cause the setting of the latch 12 during scan operations in response to a signal on the SC GD WD 5 line concurrently with a signal on the J REG 33 line. The latch 12 is reset by an OR-circuit 15 in response to a signal on the CPU RST line, or in response to an AND-circuit 16 which is operated at A time by a signal on a IRPT PULSE RST line. The IRPT PULSE RST signal appears as soon as either EXIT or I IRPT END has caused the interrupt reset provided that no storage requests are outstanding from the CPU, as is developed hereinafter.

Another factor in the setting of I IRPT END is the I program interrupt latch. In FIG. 329, the OR-circuit 8 provides a signal on the TON I PGM IRPT, which is applied to an AND-circuit 20 in FIG. 333. The AND-circuit 20 will respond at A time (AC line) so as to cause an OR-circuit 21 to set a latch 22. The output of the latch 22 is reflected at not L time in a bipolar latch 23 so as to generate a signal on the I PGM IRPT LCH line. This signal in turn, is the signal applied to the OR-circuit 4 in FIG. 325 which, together with the signal on the SET ID T2 line can cause recognition of an I interruption from I by generating a signal or the I IRPT FM I line. This in turn is one of the signals which is required in order for the AND-circuit 1 of FIG. 325 to generate the signal on the TON I IRPT END line. In other words, the OR-circuit 8 in FIG. 329 will respond to the AND-circuit 9 therein if there is a T1 interrupt, this in turn will cause the setting of the I PGM IRPT LCH in FIG. 333, which in turn will operate the OR-circuit 4 in FIG. 325 so as to permit the AND-circuit 1 in FIG. 325 to generate the TON I IRPT END signal. On the other hand, in the case of an T2-type of interruption, the OR-circuit 1 in FIG. 329 will provide a SET ID T2 signal which is used directly by the OR-circuit 4 in FIG. 325 to cause the AND-circuit 1 to generate the TON I IRPT END signal. One of the reasons that the T1-type of interrupt has a longer path in the setting of the I IRPT END is because buffering is needed to preserve the interruption indications from T1 until the latter part of T2 when the I to E transfer occurs.

In FIG. 333, the I program interrupt latch 22 is reset by on OR-circuit 24 in response to a signal on the CPU RST line, or in response to an AND-circuit 25 which operates at A time in response to the IRPT END RST signal. This signal occurs at the end of the interrupt fix sequence; thus the latch 22 will be made set during the interrupt fix sequence so as to continue to identify the T1 interruptions, and distinguish them from T2 interruptions.

14.2.1.6 Timing Control for Setting Interruption Code

One of the characteristics of the interruption-fixed sequence is the setting of the interruption code into the PSW prior to exchanging PSW's. This is effected at different times, and the times differ for bits 16-23 in comparison with the timing for bits 24-31, in some instances. For instance, bits 24-31 of a T1-type of interruption are set at the turn on of T2; bits 24-31 of a T2-type of interruption are set at the I to E transfer; bits 24-31 of channel (I/O) interruptions are set at the turn on of interrupt cycle 2. On the other hand, bits 16-23 of all interruptions are set with the turn on of interrupt cycle 1, and bits 24-31 of all interruptions except channel and I IRPT FM I interruptions are set also at the turn on of interrupt cycle 1. This is all illustrate in the chart which follows.

14.2.1.7 Priority Hold and Interrupt Reset FIG. 325, FIG. 358, and FIG. 349 ##SPC6##

Two of the initial main functions of a normal interruption fixed-sequence are the resetting of normal system functions as required so as to permit the interruption functions to take place, stopping the operation of instruction fixing and instruction execution, and the freezing of interruption recognition circuitry so that once an interruption has set either the EXIT or the I IRPT END, no further interruptions will be recognized until the end of the recognition fixed sequence.

In FIG. 325, IRPT RST is generated by the OR-circuit 3 in response to either I IRPT END or EXIT. The interrupt reset line (IRPT RST) is used in various parts of the CPU so as to permit handling of the interruptions.

In FIG. 358, a signal is generated on a IRPT TON PRI HOLD line by an OR-circuit 6 in response to either TON I IRPT END or TON EXIT. Thus, the signal which will turn on either one of the additional interruption sequence latches will also provide a turn on signal for IRPT PRI HOLD. The output of the OR-circuit 6 in FIG. 358 is applied to an OR-circuit 1 in FIG. 349. This OR circuit is effective at A time to cause an AND-circuit 2 to operate an OR-circuit 3 so as to set a latch 4, the output of which is reflected in a bipolar latch 5 that generates a signal on the IRPT PRI HOLD LCH line (hereinafter referred to as IRPT PRI HOLD). The OR-circuit 3 in FIG. 349 can also be operated by an AND-circuit 6 in response to the scan signals on the SCAN GT WD 6 line so as to permit setting of the latch 4 whenever the bit 27 of the J register is a 1.

Another input to the OR-circuit 1 in FIG. 349 is from an AND-circuit 7 which operates in response to a signal on the HALT LCH line concurrently with the output of an AND-circuit 8. The AND-circuit 8 recognizes the wait status of the system, whenever timer advance request has not been set due to signals on the NOT TIM ADV REQ LCH and WAIT STAT LCH lines. Thus, IRPT PRI HOLD can be turned on by the IRPT TON PRI HOLD in response to either EXIT or I IRPT END, or IRPT PRI HOLD can be turned on whenever the machine is in the wait status and the halt latch is set provided that no timer advance request is outstanding.

The latch 4 in FIG. 349 is reset by an OR-circuit 9 in response to a signal on the CPU RST line, or in response to an AND-circuit 10 which operates at A time provided there is an output signal from an OR-circuit 11. The OR-circuit 11 is in turn responsive either to interrupt cycle 5 signal on the IRPT CYC 5 LCH line, or to the output of any one of three AND-circuits 12-14. The AND-circuit 12 recognizes when the system is in the wait stage, the interrupt priority hold latch has been set so as to prevent interruptions from occurring (which is done only when the halt latch is also set when the system is in the wait state), and the AND-circuit 12 then will operate if the halt latch is turned off as indicated by a signal on the NOT HALT LCH. Other inputs to the AND-circuit 12 include an output from the AND-circuit 8 and a signal on the IRPT PRI HOLD LCH line. The AND-circuit 13 permits a short interruption sequence in the case of timer advance request by recognizing the turnoff of interrupt cycle 2 when timer advance request has priority due to signals on the TOF IRPT CYC 2 and TIM ADV REQ PRI lines. The AND-circuit 14 permits an even shorter sequence in the case of recovery only, by recognizing the signal on the IRPT PULSE RST line concurrently with a signal indicating that recovery priority has been granted on the RCVY PRI line.

Thus, interrupt priority hold is used at the start of a fix sequence even though the fix sequence be for timer advance or recovery purposes, and it is also used to recognize the case where the system is in the wait state and the halt latch is set so as to prevent any of the asynchronous interruptions from removing the system from the wait state by blocking the interruptions from being sensed in the interruption circuitry.

14.2.1.8 IC Recovery Request Latch FIG. 337

Normal operation of the IC recovery request latch show in FIG. 337 commences with a signal on the TON IC RCVY to IRPT line to an AND-circuit 1 which is operative at A time to cause an OR-circuit 2 to set a latch 3, the output of which is respected in the bipolar latch 4 at NOT L time so as to generate a signal on the IC RCVY REQ LCH line. The signal on the TON IC RCVY REQ line is generated in FIG. 243 whenever a program store compare together with a storage request indicates that storing into an already fetched storage word has taken place, or whenever there is an execute operation, at I to E transfer. The OR-circuit 2 in FIG. 337 can also respond to an AND-circuit 5 which recognizes bit 26 of the J register during scan word 6 due to signals on the J REG 26 and SCAN GT WD 6 lines. The latch 3 is reset by an OR-circuit 6 in response to a signal on the CPU RST line, or in response to an AND-circuit 7 which is operative at A time provided there is a signal from an OR-circuit 8. The OR-circuit 8 responds to a signal on the IRPT PULSE RST line, which indicates that the storage sequence can begin without interference from data returning from memory, or in response to a signal on the BR TOF XEQ OP, which indicates that the system has branched so that an execute operation will not take place, and therefore no execute recovery is required: in effect, the BR TOF XEQ OP cancels the execute recovery.

The output of the circuit of FIG. 337 on IC RCVY REQ LCH line is applied as an input to the circuit of FIG. 326. As described briefly in hereinbefore the IC recovery request latch will not result in the IC recovery request signal in FIG. 326 whenever there is an I interrupt from I (AND-circuit 6) or when an execute operation is involved due to the face that the IC recovery is not known to be required unless those conditions are true. Additionally, recovery priority is not granted in FIG. 326 unless there is no higher priority 1-10. Recovery priority, if granted, is utilized in FIG. 349 to reset interrupt priority hold, and is not needed to generate interrupt control bits for addressing storage words in FIG. 330 nor is it needed in FIG. 359 through FIG. 361 for generating interrupt codes since recovery is not an interrupt, and appears in the interrupt controls only to achieve interrupt reset conditions, which includes unblocking certain of the IC controls, and is also used in FIG. 358 as an input to the circuits which cause the resetting of the MODAR circuit.

14.2.1.9 Console Interrupt Latch Circuit FIG. 331

In FIG. 331, a signal on a IRPT PB line from the power distribution unit (PDU) control panel area of the system will cause an AND-circuit 1 to set a latch 2 immediately upon its being reset at the start of not BR time. The output of the latch 2 is applied to an AND-circuit 3 which causes an OR-circuit 4 to set a latch 5 at A time due to a running A clock signal on the AR line. The output of the latch 5 is reflected in a bipolar latch 6 upon the occurrence of the NOT LCH PRI signal, which signal indicates that latches within the interrupt input circuitry are allowed to change and to assume states indicative of the inputs thereto. The bipolar latch 6 provides a signal on the CONS IRPT LCH line.

The OR-circuit 4 in FIG. 331 may also respond to an AND-circuit 7 during scanning word 5 due to the presence of signals on the J REG 31 and SCAN GT WD 5 lines. The latch 5 is reset by an OR-circuit 8 in response to a signal on the CPU RST at A time in response to an AND-circuit 10. The AND-circuit 10 recognizes the case where the console interrupt latch has already been set, and the console interrupt has been granted priority as indicated by a signal on the EXT IRPT PRI line, so that the AND-circuit 10 will be operated during cycle 4 of the interrupts due to the signal of IRPT CYC 4 LCH line.

The output of FIG. 331 of the CONS IRPT LCH line is applied to the circuit of FIG. 359, although not shown therein, to be utilized in generating I CPU RST & NOT MCH CHK line, or by an AND-circuit 9 which operates interrupt code bit 25 (see said System/ 360 Manual) in the same fashion that TIM IRPT TGR generates interrupt code bit 24.

14.2.1.10 Mail Check Circuits FIG. 338, FIG. 339, and FIG. 340

In this system, when errors or malfunctions are sensed, the errors are first utilized by the maintenance controls within the power distribution unit (PDU) to cause a "log" operation wherein a large number of conditions within the machine are recorded for examination by a maintenance personnel. When the log is completed, then the maintenance controls sense a scanning control signal to provide a machine check interruption which permits exchanging of PSWS, and performing a diagnostic or other program in response to the new PSW.

In FIG. 338, the maintenance controls call for a machine check interrupt by sending a signal on a SCAN SET MCH CHK line to an AND-circuit 1 which operates when there is also present a signal on the CPU RST line. The signal on the CPU RST line is a function of the log being completed, as is described with respect to the PDU maintenance controls. The AND-circuit 1 causes the OR-circuit 2 to generate a signal on the SET line (this signal being utilized to set a latch 10 in FIG. 340) the output of which comprises a signal on a MCH CHK START line. The MCH CHK START signal is also applied to an OR-circuit 11, so that it will generate a signal on a MCH CHK IRPT line. Shortly after generating the set signal, the signal on the CPU RST line disappears so that there is no longer an input to the AND-circuit 1 and the output from the OR-circuit 2 disappears as well which causes the disappearance of the signal on the SET line, and results in the appearance of a sigan n the SET line, and results in the appearance of a signal on a NOT SET line due to the action of an inverter 3 in FIG. 338.

In FIG. 338, an AND-circuit 4 will not have operated due to the fact that when there was a signal on the CPU RST line to activate the AND-circuit 1, there obviously was no signal on the NOT SCAN SET MCH CHK line since there was a signal ok the SCAN SET MCH CHK line. Also, since the interruption fixed-sequence has not yet begun, there is no signal on a IRPT CYC 6 LCH line so that there is no output from an OR-circuit 5. Thus an inverter 6 will generate a signal on a NOT RST line.

In FIG. 340, an AND-circuit 12 now has applied thereto signals on the NOT SET, NOT RST, and F2 lines. The circuits of FIG. 338 stabilize with the NOT SET, NOT RST, and F2. However, following the CPU reset, the main system clock is essentially started, and the first signal to come from the clock is an L clock which provides a signal on the LC line at the input to the AND-circuit 12 in FIG. 340. This permits the AND-circuit 12 to operate causing the latch 13 to be set. When the latch 13 is set, it applies an input to the OR-circuit 11 so that in the event that the latch 10 is reset, a signal will continue to appear on the MCH CHK IRPT line. At the end of the first L clock signal, a signal appears on a NOT LC line at the input of the AND-circuit 14 in FIG. 340 which also has applied thereto a signal on the F1 line. Therefore, the AND-circuit 14 will cause an OR-circuit 15 to reset the latch 10. With the latch 10 reset, there is no longer an F2 signal, so that the AND-circuit 12 will no longer recognize any L clock signals which is applied thereto. The first L clock signal is therefore defined by the latch 10 being on so that the MCH CHK START signal is apparent; this signal is utilized in FIG. 346 so as to permit an OR-circuit 1 therein to provide an input to an AND-circuit 2 so as to cause an OR-circuit 3 to set a latch 4. Alternatively stated, the machine check start signal permits recognizing the first A clock signal at the AND-circuit 2, but inasmuch as the machine check start signal disappears following the end of the first L clock (an L clock spans an A clock) no further A clocks will permit the AND-circuit 2 to operate as a result of machine check inputs to the OR-circuit 1.

The interruption fixed-sequence will proceed until interrupt cycle 6 is set which provides a signal on the IRPT CYC 6 LCH line in FIG. 338. This permits the OR-circuit 5 in FIG. 338 to generate a signal on the RST line, which signal is applied to an OR-circuit 16 in FIG. 340 which in turn resets the latch 13 so that the signal disappears from the MCH CHK IRPT line. This also causes both latches in the circuits of FIG. 340 to be reset thereby having them ready for another machine check interrupt start sequence should the occasion arise. The MCH CHK IRPT line is used to identify the machine check in contrast to any other type of interrupt throughout the interruption circuits. However, this signal also disappears after IRPT CYC 6 resets F1.

14.2.1.11 Wait Status Latch FIG. 357

In FIG. 357, an AND-circuit 1 may cause an OR-circuit 2 to set a latch 3 which in turn sets a bipolar latch 4 at NOT L time thereby to generate a signal on the WAIT STAT LCH line, which is hereinafter referred to as wait status. The latch 1 will sample bit 14 of the PSW, which indicates that the system is to be put into the wait state whenever bit 14 is a 1. In order to sample the PSW, the AND-circuit 1 must have a signal present on a WAIT STAT COND line, which signal is generated in FIG. 358. In FIG. 358, an OR-circuit 7 responds to either one of the two AND-circuits 8, 9 so as to permit conditioning of the wait status. The AND-circuit 8 is responsive at CTRL L CYC provided there is no B interrupt as indicated by a signal on the NOT B IRPT line. It is to be noticed that this is the converse of the setting condition for the AND-circuit 3 in FIG. 358 which will cause the turn on of EXIT at CTRL L CYC provided that there is a signal on the B IRPT line.

At the last cycle of an interruption fix-sequence, an AND-circuit 9 will respond to a signal on the IRPT CYC LCH line provided there is a signal on the NOT A IRPT line. Thus, whenever EXIT would not be turned on, it is possible to have the WAIT STAT COND signal applied to the AND-circuit 1 in FIG. 357.

In FIG. 357, the OR-circuit 2 can also respond to an AND-circuit 5 which is operated by word 6 in a scanning operation due to signals on the J REG 29, and SCAN GT WD 6 line. The latch 3 is reset by an OR-circuit 6 in response to a signal on the CPU RST line, or in response to an AND-circuit 7 which in turn requires an output of an OR-circuit 8. The OR-circuit 8 recognizes one of the asynchronous interruption signals, which include external interruptions, channel interruptions, and timer advance request, although EXIT is used as an indication of when a timer advance request has been accepted. The purpose of the OR-circuit 8 is described more fully in said System/360 Manual, wherein the wait status is defined as precluding any activity by the system except for timer advance, input output interruptions (CH IRPT) or external interruptions. When one of these interruptions is sensed, the OR-circuit 8 will cause the AND-circuit 7 to operate the OR-circuit 6 so as to reset the latch 3. Thus, the system shifts out of the wait state long enough for PSW exchange and interruption to take place in accordance with the interruption fix-sequence, or long enough to update the timer word. In the case of channel interruptions or external interruptions, PSWs are exchanged, and the new PSW may or may not have a 1 in bit 14 thereof. Thus, the machine may or may not return to the wait state in dependence upon the new PSW which relates to the particular interruption. In many cases, the new PSW will call for a short sequence of instructions in response to the channel or the external interruption, and this short sequence of instructions may well end with a LOAD PSW instruction which causes the return of the original PSW (prior to shifting out of wait) to be returned to the PSW register. At that time, the control last cycle of the last instruction will recognize that PSW bit 14 is a 1, causing the latch 3 to again be set whereby the system returns to the wait state.

Note particularly that a timer advance, since it does not call for the exchange of PSWs, will not remove the system from the wait state other than long enough to permit fetching the timer word, decrementing the timer word in the E unit, and returning the timer word to storage, with or without a timer interruption, in dependence upon whether or not the timer word changed from a positive to a negative value as it was updated.

A simplified, illustrative sketch of the timing of the machine check interrupt start circuits is shown in FIG. 339. This sketch illustrates that CPU reset will cause a SET signal for a short period of time, during which F2 is set, which causes MCH CHK IRPT to appear. The circuits remain in that condition unit the first clock signal appears after the restarting of the clock; this is a LC signal which, together with the presence of F2 causes the setting of F1. When F1 is set, the next A clock will cause the setting of IRPT CYC 1, and the circuits will ignore all future clock signals. Near the end of the interruption fix-sequence IRPT CYC 6 will appear to reset F1. Note that F1 continues to generate the MCH CHK IRPT signal even after F2 is turned off.

Once the latch 3 is reset at the start of either a channel or an external interruption, or at the start of a timer advance, the EXIT latch will be set, control last cycle or interrupt last cycle are no longer available so that the signal is not apparent at the WAIT STAT COND line input to the AND-circuit 1 in FIG. 357. The latch 3 must therefore remain reset until IRPT L CYC appears which permits a further signal on the WAIT STAT COND line.

The exit signal is allowed to come on in response to channel or external interruptions, or in response to a timer advance request by virtue of an AND-circuit 5 in FIG. 358 which does not require either interrupt last cycle or control last cycle, but merely requires that the wait status latch be set and that the halt latch not be set. Then an A interruption (which includes the asynchronous interruptions: channel, external, timer advance) will cause an OR-circuit 2 in FIG. 358 to operate an AND-circuit 1 thereby generating a signal on the TON EXIT signal. This causes EXIT to appear in FIG. 333, and it is applied to set interrupt cycle 1 in FIG. 346, as described hereinafter. Thus, the EXIT signal is also available to operate the OR-circuit 8 in FIG. 357 thereby to reset the latch 3 and remove the system from the wait status. However, no interruptions can be taken since there will be no I to E transfer, no control last cycle, and until timer advancing is completed, there will be no interrupt last cycle; thus, the asynchronous interruptions permit resetting the wait status latch so as to enter into the interruption fix-sequence.

14.2.1.12 INITIAL Program Load Buffer FIG. 347 and FIG. 352

In FIG. 347, an AND-circuit 1 which is effective to reset the interrupt cycle 2 latch upon the receipt of an accept signal from the BCU whenever the interrupt cycle 2 latch is set also provides a signal to an AND-circuit 2 therein. The AND-circuit 2 is additionally responsive to the absence of priority for a timer advance request as indicated by a signal on a NOT TIM ADV REQ PRI line concurrently with a signal indicating that initial program loading is required as indicated by a signal on a IPL A line. The IPL A line is generated in FIG. 290 from the time that the maintenance controls start to turn on and IPL latch in FIG. 289 until the time that the IPL latch itself is turned off. In other words, the IPL A line indicates that initial program loading of the PSW is required.

Thus, in FIG. 347, when initial program loading is required, an interrupt cycle 2 is on, a receipt of an accept signal from the BCU indicates that the program status word which has been fetched for the initial program load operation will be supplied by the BCU, and therefore that the IPL buffer should be turned on as indicated by the TON IPL BFR signal. This signal is applied to an AND-circuit 1 in FIG. 352 which operates at A time to cause an OR-circuit 2 to set a latch 3, the output of which is reflected in a bipolar latch or at NOT L time, so as to generate a signal on a IPL BFR LCH line. The OR-circuit 2 may also respond to an AND-circuit 5 during scan word 6 due to the effect of signals on a J REG 31 and SCAN GT WD 6 lines. The latch 3 is reset by an OR-circuit 6 in response to a signal on the CPU RST line, or in response to an AND-circuit 7. The AND-circuit 7 recognizes the turn on of interrupt cycle 5, which turns on during the normal interruption fix-sequence when the fetched storage word is known to have returned In a case of initial program loading, the turn on of interrupt cycle 5 is affected in FIG. 351 by an AND-circuit 1 which responds to signals on the J LOADED LCH and IPL BFR LCH lines. Since J LOADED appears as a result of a J ADV which is received in the CPU from the BCU, J LOADED indicates that the PSW has been returned to the J register. The AND-circuit 1 in FIG. 351 causes the OR-circuit 2 to generate a signal on the TON IRPT CYC 5 line, which signal appears at the input of the AND-circuit 7 in FIG. 352 so as to permit operation of the OR-circuit 6 at A time, thereby resetting the latch 3.

The IPL latch in FIG. 289, from which, together with the turn on of which, the IPL A signal input to the AND-circuit 2 in FIG. 347, also causes in FIG. 295 the generation of an IE IPL START SEQ signal which is applied to the OR-circuit 1 in FIG. 346, causing interrupt cycle 1 to be set. Interrupt cycle 1 causes the storage request, and when the accept is received from the BCU, interrupt cycle 2 is turned off and the IPL buffer (FIG. 342) is turned on. The buffer remains on while the storage is actually fetching the new PSW and interrupt cycles 3 and 4 are blocked because of the fact that interrupt cycle 3 is normally set by an AND-circuit 1 of FIG. 348, which AND circuit is blocked by the presence of initial program loading due to the effect of a signal on a NOT IPL A line. Since interrupt cycle 3 does not go on, interrupt cycle 4 will not come on; this is desirable because no store cycle is involved in fetching the PSW for an initial program load. When the storage word returns (J LOADED, AND 1, FIG. 351) normal interrupt sequencing resumes by turning on interrupt cycle 5. The turn on of interrupt cycle 5 causes setting of the new PSW, in a normal fashion.

14.2.1.13 Timer Advance Request FIG. 354

In FIG. 354, an AND-circuit 1 responds to a signal on a INT TIM ADV line which is generated in the power distribution unit (CPU) in response to a power line signal (such as the ordinary 60 -cycle power which might be utilized to supply operating current to the system). The circuitry which creates the INT TIM IRPT signal is illustrated in FIG. 356. The AND-circuit 1 will operate at the start of NOT BR time, immediately following the resetting of a latch 2, so as to cause the latch 2 to be set. With the latch 2 set, an AND-circuit 3 will operate on the following A clock due to a signal on the AR line so as to cause an OR-circuit to set a latch 5. The output of the latch 5 is reflected in a bipolar latch 6 so as to generate a signal on the TIM ADV REQ LCH like, provided there is a signal on the NOT LCH PRI line, indicating that the asynchronous input latches for the interrupt circuits are not frozen in the latched state. The OR-circuit 4 may also respond to an AND-circuit 7 whenever there are signals present on the J REG 30 and SCAN GT WD 5 lines. The latch 5 is reset by an OR-circuit 8 in response to a signal on a CPU RST.

14.2.1.14 External Signal Latches FIG. 341 through FIG. 345

In FIG. 341, a plurality of bipolar latches 1 are each operated by a signal on a NOT LCH PRI line to reflect the setting of a corresponding one of a plurality of latches 2, each of which is settable by a related OR-circuit 3 in response to corresponding scan signals, such as on the SCAN EXT SIG 2 line, or in response to a corresponding one of a plurality of AND-circuits 4. Each AND-circuit 4 responds to a running A clock signal on the AR line, and to a related external bus in signal such as on the EXT SIG BUS IN 2 line. Each of the latches 2 is reset by a related OR-circuit 5 in response to a resetting signal from an AND-circuit 6 which responds to signals on the CPU RST and NOT SCAN SET MCH CHK lines, which correspond to the resetting signal used on the timer advance request latch in FIG. 354 and on the console interrupt latch of FIG. 331. Each of the OR-circuits 5 also are responsive to a related AND-circuit 7, the AND-circuit 7 being operated by running A clock signals on the AR line, and by a signal on the EXT IRPT END line concurrently with a related external signal interrupt latch signal such as on the EXT SIG IRPT 2 LCH line. Thus, provided a particular bipolar latch 1 has been set, the appearance of the external interrupt end signal to the AND-circuit 7 will cause the corresponding latch 2 to be reset at A time. External interrupt end merely means that priority has been granted to external interrupt, and interrupt cycle 4 has been reached (FIG. 350).

The nomenclature in FIG. 341 through FIG. 345, is hardware oriented, and differs from that shown in said System/360 Manual in accordance with the chart of FIG. 344. In FIG. 344, the external signals 1-6 (as described in said System/360 Manual) are shown in the first column. In the second column, the identification of the external signal bus in lines is shown to correspond conversely to the external signals which they represent: for instance, external signal 1 appears on external signal bus in line 7, external signal 5 appears on external signal bus in line 3, etc. The third column illustrates that external signal latches of FIG. 341 are numbered to correspond with the external signal bus in lines, such that external signal 1 will be lodged in external signal interrupt latch 7. The final column delineates the interruption code bit assignment for the various external signals, as well as for console interrupts and timer advance requests. In fact, since bits 24-31 of the interruption code may be thought of as bits 0-7 of a particular byte of the interruption code, the hardware herein has been given nomenclature consistent with the 0-7 significance of these bits. For instance, timer advance requests interruptions will cause the setting of interrupt code bit 24, which is bit 0 of the byte shown in FIG. 344; similarly, console interruptions would cause the setting of bit 1 of the byte, and external signal 6 would cause the setting of bit 2 of that byte. It is to be noted, however, that the distinction between the various external signals is manifested in the system only in the setting of the interruption code. Thus, a particular external signal will cause the setting of the corresponding latch in FIG. 341, the output of any of these latches will cause an OR-circuit 1 in FIG. 345 to generate a signal on the EXT SIG IRPT OUTST line, to indicate to the interruption controls that an external signal interruption is requested. The output of the latches in FIG. 341 is also applied to the circuits of FIG. 359 through FIG. 361 so as to generate a particular interruption code in dependence upon which external signal is present, the particular bit of the interruption code being that shown in the rightmost column of FIG. 344. Beyond that, there is no distinction between the particular external signals, any one of them being handled the same way by the interruption circuits.

The output of the external signal interrupt latches in FIG. 341 is applied to an exclusive OR complex 1 in FIG. 342, together with signals on TIM IRPT EGR and CONS IRPT LCH lines. The output of the exclusive OR-circuit complex 1 is passed to an inverter 2 so that, if an even number of bits are present at the input to the exclusive OR-circuit 1, there will be no output therefrom, so that an inverter 2 will generate a parity signal on the EXT IRPT PAR line. The GIM IRPT TGR line comes from the E unit, and represents a trigger which is set whenever the timer advance results in the timer word changing from a positive value to a negative value, thus indicating that the function represented thereby has been completed. This is the same line that is utilized in FIG. 328 in the generation of the signals on the EXT IRPT and EXT IRPT PRI lines.

14.2.1.15 Table of Interruption Masking ##SPC7##

14.2.2 INTERRUPTION FIXED-SEQUENCE

The preceding two sections have described in detail the circuits which provide inputs to the interruption circuit, and which establish the turning on of either the EXIT or I IRPT END latches. The sections hereunder describe fully the basic interruption fix-sequence, and the variations therein which are required in order to handle machine check interruptions, timer advance requests, recoveries, and other special cases. Each of the basic functions of the interruption fix-sequence, some of which are used in all sequences, and others of which are used in only certain of the sequences, are each described.

14.2.2.1 Interruption Reset FIG. 325

Interruption reset comprises a signal on the IRPT RST line which is generated by an OR-circuit 3 in FIG. 325 in response to either I IRPT END LCH or EXIT. The IRPT RST signal is utilized in various places within the system so as to permit performing the interruption fix-sequence, or some appropriate portion thereof, without interference from I unit or E unit functions; particularly, it stops the I unit and the E unit from receiving any further until the new PSW is loaded and the interruption is otherwise completely sequenced. In the case of a recovery, an AND-circuit 10 in FIG. 358 responds to the interrupt reset signal and to a signal indicating recovery priority has been granted provided that there is no outstanding storage request from the CPU, all as indicated by signals on the RCVY PRI, IRPT RST, and NOT CPU STG-BUSY lines. The AND-circuit 10 generates a signal on a IRPT TO RCVY line which is utilized in the IC FETCH circuitry of FIG. 348 to cause an OR-circuit 1 therein to generate the TON IC RCVY signal. Notice that the EXIT signal will not cause the setting of the first interrupt cycle in FIG. 346 in a case of a recovery due to the presence of a signal on a NOT RCVY PRI line. Thus, recovery enters into the interruption circuit merely to provide the interrupt reset signal on the IRPT RST line, so as to achieve a resetting of a number of functions in the CPU, and when the IRPT RST signal appears, then the control is transferred over to the IC control section of the CPU (FIG. 222). Another AND-circuit 11 in FIG. 358 responds to the IRPT RST and NOT CPU STG-BUSY lines to generate a signal on a IRPT PULSE RST line as soon as interrupt reset appears provided that no outstanding fetch has been requested by the CPU of the storage unit. The IRPT PULSE RST signal is applied to the EXIT latch of FIG. 333 to reset EXIT, and is also applied to an OR-circuit 8 in FIG. 346 to reset the IC RCVY REQ latch. Thus, after a single EXIT cycle within which IRPT RST is generated, the A clock following the setting of EXIT will cause the resetting of both EXIT and IC RCVY REQ.

The IRPT PULSE RST which is generated by IRPT RST, is applied to the EXIT and I IRPT END latches in every interruption sequence; in other words, the EXIT and I IRPT END latches are on for only the first machine cycle of an interruption fix-sequence.

Notice that the actual output in FIG. 333 of EXIT and I IRPT END comprises the output of the bipolar latches 4, 13, respectively, which are not set until the end of L time, and since L time completely spans A time, there is no possibility of IRPT RST being generated by the OR-circuit 3 in FIG. 325 until the start of not L time, and therefore there is no possibility of the IRPT PULSE RST being generated by the AND-circuit 11 in FIG. 358 until the start of not L time which is at least half A time, so that a second A clock signal (one following the one which is used to set either the EXIT or I INTERRUPT END) must be achieved prior to the resetting of EXIT or I IRPT END.

When recovery priority has not been granted, an AND-circuit 12 in FIG. 358 responds to IRPT RST and to a signal on the NOT RCVY PRI line so as to generate a signal on an IRPT SET BLK IC & T1 which permits the setting of the BLK ICM latch in FIG. 208, and also permits the setting of the BLK T1M latch FIG. 203.

14.2.2.2 Setting the Interruption Code FIG. 325, FIG. 329 and FIG. 359 through FIG. 361

The setting of the interruption code into the PSW is timed as shown in the chart of Section 14.2.1.6. Specifically, the T1 SET PSW line in FIG. 329 and the T2 SET PSW line in FIG. 325 supply setting for bits 24-31, and the EXEC SET PSW line in FIG. 334 provides late setting for bits 24-31. Bits 16-23 of the interruption code are always set by IRPT RST which occurs at the turn on of interrupt cycle 1. Bits 24-31 are sometimes set at the turn on of interrupt cycle 1 (all except I IRPT FM U or CH IRPT) by the EXEC SET PSW.

IN FIG. 334, a signal is generated on the EXEC SET PSW line by an OR-circuit 1 in response to an AND-circuit 2 or in response to a signal on the MCH CHK START line. The AND-circuit 2 will operate in response to an OR-circuit 3 when there is a signal on the CH IRPT REL LCH, or when there is an output from an AND-circuit 4. The AND-circuit 4 responds to EXIT together with a signal on a NOT CH IRPT PRI line so as to normally control the generation of the EXEC SET PSW signal. The AND-circuit 4 is therefore the means whereby bits 24-31 are set into the PSW in all cases except channel interruptions, and I IRPT FM I interruptions (see the chart of Section 14.2.1.6). The OR-circuit 3 responds to the signal on the CH IRPT REL LCH line in order to define the time when the channel has sent the response back to the CPU telling the CPU that the address of the particular unit which has caused the interruption is on the unit address bus in (UABI), and that therefore it is possible to put the unit address into PSW bits 24-31 as an interruption therefor, which occurs at the time of turning on interruption cycle 2 due to the fact that the CH IRPT REL LCH signal is utilized to turn on interrupt cycle 2 in FIG. 347.

A particular case of a storage address interruptions being initiated by a store request which immediately preceded an I IRPT FM I interruption is handled by OR-circuit 5, 6 in FIG. 334. In the event that a I IRPT FM I has been sensed, and a CPU SAP is received at the interruption controls, the CPU SAP interruption will be handled by the I IRPT END latch rather than by the EXIT latch since this will already have been initiated. In this particular case, the interruption code for CPU SAP will be set into the PSW by the EXEC SET PSW line at the time of the turn on of interrupt cycle 1 as a result of I IRPT END rather than as a result of EXIT. In such a case, bits 24-31 of the interruption code will already have been set for an I IRPT FM I (see the chart of Section 14.2.1.6), but the later setting of the interruption code at the turn on of interrupt cycle 1 will erase what had previously been set therein. Because of the fact that CPU SAP has ultimate priority over I IRPT FM I, interruption code bits 16-23 of the I IRPT FM I will not be set into the PSW at the turn on of interrupt cycle 1 whenever there is a CPU SAP following a I IRPT FM I. Thus, the combination of the timed interruption priority (as between I IRPT FM I) and all other interruptions, combined with the absolute priorities of all of the interruptions (CPU SAP being prior to I IRPT FM I) permits late interruptions of a higher priority from dislodging, or cancelling, previously sensed interruptions of a lower priority, even though the race as between the EXIT latch and the I IRPT END latch has been won by I IRPT END. This race takes place at a time which coincides with the CTRL L CYC and the I TO E XFER, due to the fact that EXIT, through IRPT RST, inhibits the setting of I IRPT END, and due to the fact that the I TO E XFER is about a half cycle later than CTRL L CYC.

The four signals which cause the setting of the interruption code are illustrated in FIG. 131, which shows that IRPT RST is always used for setting bits 16-23 in that it causes an AND-circuit 11 to force an OR-circuit 1 to generate a UNLCH PSW 16-23, P line. FIG. 56 also illustrates that bits 24-31 of the interruption code are set by any one of the following lines: T2 SET PSW, T1 SET PSW, or EXEC SET PSW, by generating a signal on the UNLCH PSW 24-31, P line. The actual setting of the interruption code into the PSW is shown in FIG. 134, where it is illustrated that bits 16-20 are not used as interruption control bits in the present architectural definition of a system in accordance with the description in said System/360 manual. FIG. 134 also illustrates that IRPT RST is utilized for setting channel identification bits into PSW bits 21-23 whenever CH IRPT PRI has been granted, due to the effect of a gating AND-circuit 26.

The PSW register latch circuits shown in FIG. 134 are all connected so as to be reset and then immediately set provided that there is a proper input bit; otherwise, each latch will be reset and left in a reset condition in response to a corresponding UNLCH line. In the case of bits 21-23, the only time that other than 0 is to be set into these bits is in the case of a channel interruption, in which case a particular channel is identified by a proper encoding of the channel interrupt code bit on the CH IRPT CD 1, 2, 4 lines. Thus, for every type of interruption except a channel interruption, the UNLCH PSW 16-23, T line will provide for the resetting of the latches 3-5 in FIG. 134, and nothing will be set into those latches so that those latches will always be set to 0. The same, of course, is true for bits 16-20 of the PSW (shown at the top of FIG. 134) which are not actually used in the interruption code.

When there is a channel interruption, then the IRPT RST together with the CH IRPT PRI will cause the AND-circuit 26 to gate the various channel interrupt code bits through corresponding AND-circuits 20, 21, 22 so as to set related latches 3-5. Bits 24-31 of the interruption code are set by interrupt code input bits from FIG. 359 and FIG. 361. These are gated into the latches by the signal on the UNLCH PSW 24-31, P line, in response to either T1 SET PSW, T2 SET PSW, or EXEC SET PSW, as shown in FIG. 131. Any bit which is not present on one of the interrupt code lines will not cause the corresponding latch 6, 7 to again be set, so that that latch will represent a 0 in the interruption code of the PSW.

Note that only the channel identification information is placed in bits 21-23 of the interruption code, and that bits 24-31 of the interruption code are all supplied by the circuits of FIG. 359 and FIG. 361.

In FIG. 359, a plurality of OR-circuits 1, 2 each generate bits representing interruption codes in response to various inputs. The OR-circuits 1 are each responsive to three AND-circuits 3-5 in response to SUP CALL PRI, CH IRPT PRI, or EXT IRPT PRI, respectively. Each of the OR-circuits 2 also responds to an AND-circuit 3-5, and also responds to an additional AND-circuit 6 which relates to E PGM IRPT PRI, which when granted indicates any one of the E IRPT FM I-type of interruption.

The generation of interruption code bits 24-28 is shown completely in FIG. 359 due to the fact that these bits can be set only by E IRPT FM I, EXT SIG, and CH IRPT types of interruptions. However, bits 29-31 are also utilized in establishing the interruption code for INV OP, PRIV OP, XEQ TO XEQ, INV ADR, and INV SPEC types of interruptions. Therefore, the bit 29-bit 31 output of FIG. 359 is combined in FIG. 361 with additional encoding signals from FIG. 360. The application of the encoding signals to FIG. 360 is such that the invalid operation, privileged operation, execute, invalid address, and specification type of interruptions will each generate a corresponding signal on the output of FIG. 360, whether the interruption be sensed at T1 or T2 (such as SPEC PRI). The output of FIG. 360 is combined with bits 29 through bits 31 and parity of the output of FIG. 359. This takes place in FIG. 361, which comprises merely a plurality of OR-circuits 1, which recognize the output of G 39, or any appropriate output from FIG. 360. The operation of the circuit of FIG. 359 through FIG. 361 is such as to effect the establishment of an interrupt code bit for each one as shown in the table of interruption codes in the following sections. Although not described elsewhere herein, certain of the inputs to FIG. 359 are shown in FIG. 322 and FIG. 323. These comprise signals on the SAP PRI and INV STR PRI lines as well as a signal on the SUP CALL PRI lines. If a signal appears on a CPU SAP line, there is automatically generated a signal on the SAP PRI line. This is due to the fact that whenever a storage address protection interruption occurs, it automatically has priority, since there could not possibly be a machine check (the system having been reset immediately before machine check) and there could not possibly be the need to load the PSW in an initial program loading operation (since the machine has not done anything prior to the loading of the IPL PSW). In FIG. 322, an AND-circuit 1 will generate a signal on a INV STR PRI line provided there is no CPU SAP interruptions as indicated by a signal on a NOT CPU SAP line, and there is a signal on a CPU INV STR line. In FIG. 323, an AND-circuit 2 will generate a signal on a SUP CALL PRI line provided that there is no other interruption, or other input to the interruption circuits. Specifically, the AND-circuit 2 will respond only with signals present on the following lines: BD SUP CALL, NOT IRPT PRI 1-4, NOT IRPT PRI 5-10, NOT IC RCVY REQ, and NOT I PGM IRPT LCH. Other inputs to the circuits of FIG. 359 through FIG. 361 appear in FIG. 326 through FIG. 320 and FIG. 324 through FIG. 329.

14.2.2.3 Table of Interruption Codes

The interruption codes which are generated in FIG. 359 through FIG. 361 are characterized by certain particulars, including the fact that a machine check interruption will set the interruption code to all zeros, and E IRPT FM E will always set a 1 bit into bit 28 of the interruption code, the external interruptions set bits which comprise a single bit in one of the eight interruption code positions, the timer interruption being bit 24, the console interruption being bit 25, and the external signals 1-6 setting bits 26-31, respectively. In the case of a supervisor call instruction, the R1 and R2 fields are set into bits 24-27 and 28-31. When an 10 interruption (CH IRPT) is involved, the unit address bus in supplies the address of a particular unit for the particular channel so that the eight bits 24-31 comprise an identification of the particular unit which has caused the interruption. --------------------------------------------------------------------------- 14.2.2.4 Table of Interruption Codes

PSW bits Interruption E IRPT FM E 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 Machine Check 0 0 0 0 0 0 0 1 Invalid Operation 0 0 0 0 0 0 1 0 Privileged Operation 0 0 0 0 0 0 1 1 Execute 0 0 0 0 0 1 0 0 STG ADR Protection 0 0 0 0 0 1 0 1 Invalid Address 0 0 0 0 0 1 1 0 Specification 0 0 0 0 0 1 1 1 Data 0 0 0 0 1 0 0 0 Fixed-Point Overflow x 0 0 0 0 1 0 0 1 Fixed-point Divide x 0 0 0 0 1 0 1 0 Decimal Overflow x 0 0 0 0 1 0 1 1 Decimal Divide x 0 0 0 0 1 1 0 0 Exponent Overflow x 0 0 0 0 1 1 0 1 Exponent x 0 0 0 0 1 1 1 0 Significance x 0 0 0 0 1 1 1 1 Floating-point Divide x 1 0 0 0 0 0 0 0 Timer 0 1 0 0 0 0 0 0 Console (IRPT key) 0 0 x x x x x x External Signals 1-6 R1 R2 Supervisor Call Unit Address Bits 0-1/0 __________________________________________________________________________

14.2.3 PSW ADDRESS GENERATION FIG. 330

In FIG. 330 are shown circuits which generate address bits for storing the old PSW and for fetching the new PSW. Addresses which represent various interruptions, and the source of the initial PSW, as well as the timer are shown in the following chart: ##SPC8##

In FIG. 330, an OR-circuit 1 provides a gating signal for bits 26-28 of the interruption address. This is operative during interrupt cycle 1 and during the store PSW portion of the interruption sequence due to signals on the IRPT CYC 1 LCH and STR PSW lines. Bits 26-28 are gated by the output of the OR-circuit by corresponding AND-circuits 2-4. Each of the AND-circuits 2, 3, 4 provide an output signal on corresponding IRPT CTRL BITS lines as necessary in order to satisfy the conditions shown in the foregoing chart. For instance, the AND-circuit 4 will generate bit 28 for external, program, or channel interruptions due to the presence of signals on the EXT IRPT PRI, PGM ZRPT PRI, and CH IRPT PRI lines at the input of an OR-circuit 5. In the preceding chart, it is seen that bit 28 is a 1 for external, program, and channel (I/O) interruptions, both when the new PSW is fetched and when the old PSW is stored. Similarly, an AND-circuit 3 responds to an OR-circuit 6 which generates bit 27 and responds to external, machine check, or channel interruptions, or in response to a timer advance request. The AND-circuit 2 responds to an OR-circuit 7 provided there is a program interruption which is indicated by an AND-circuit 8. The AND-circuit 8 responds to an OR-circuit 9 which in turn responds to an AND-circuit 10. The AND-circuit 10 merely recognizes I program interruptions due to the elimination of interruptions having a priority of 1-11, in accordance with the chart in Section 8.2.1.1, and the OR-circuit 9 also responds to E program interruptions and to interruptions having a priority between 1 and 4. However, the AND-circuit 8 removes interruptions having a priority of 1 and 2 due to the presence of signals on a NOT MCH CHK IRPT and NOT IPL LCH lines. Thus, the output of the AND-circuit 8 is equivalent to program interruptions priority, which together with supervisor call machine check or channel interruptions will cause bit 26 to be generated by the AND-circuit 2. An AND-circuit 11 at the top of FIG. 330 recognizes when PSWS are being fetched, with the exception of the IPL PSW, due to signals on the IRPT CYC 1 LCH and NOT IPL LCH lines. This provides a bit 25 for fetching the timer and for fetching all of the PSWs except the IPL PSWS in accordance with the foregoing chart.

At the bottom of FIG. 330, parity bit for bits 25-28 of the PSW address is generated by an OR-circuit 12 in response to either one of two AND-circuits 13, 14. Circuit 13 is operative during interrupt cycle 1 provided there is an output from an OR-circuit 15 which in turn is responsive to an OR-circuit 16. The OR-circuit 16 responds to supervisor call parity or channel interrupt priority, and the OR-circuit 16 is additionally responsive to a T1M advance request or to initial program loading. Thus a parity bit will be generated during cycle 1 for fetch address relating to IPL timer, supervisor call, and output operations.

Circuit 14 is operative during a storing of PSW in response to any interruption-type operation except for the supervisor call and channel (I/O) interruptions due to the effect of an inverter 17 which responds to the OR-circuit 16. A parity bit is provided for external, program, and machine check interrupts when the corresponding PSW is being stored as indicated by a signal on the STR PSW line. Note that the parity bit is not generated in FIG. 330 for the storing of the updated timer, due to the fact that a timer advance inhibits the setting of interrupt cycle 3 since control is transferred to the E unit at that time, and when the E unit is finished, the interruption controls is resumed with interrupt cycle 5. Setting of the address adder for storing the timer word remains the same as it was when the timer word was fetched, and so no new generation is required for the storing of the timer word.

At the bottom of FIG. 330, an AND-circuit 18 provides a signal to cause the setting of the length code in the PSW to 00 whenever the storage address protection interruption occurs, due to the fact that it is impossible to tell whether the storage address protection results from a store instruction currently by an execute or a previous store instruction. This in turn results from the fact that E last cycle can be set (ending previous execution) as soon as a store request is accepted by the BCU even though the actual storage cycle may not commence for some time. Since the correct store instruction cannot be identified, the length is set to 00 to indicate that fact.

14.2.4 INTERRUPTION CYCLES

The interruption cycles within the interruption fixed-sequence are characterized by the various functions which each of the cycles must perform. Interruption cycle 1 provides the address for fetching the PSW or the timer word; interruption cycle 2 provides an interruption fetch together with the setting of marks in anticipation of a later storing of either the old PSW or the updated timer word; interruption cycle 3 automatically follows interruption cycle 2 unless a timer advance initial program loading is involved, and provides moving of the right half of the PSW through the incrementer to the K register high-order half, cycle 3 goes off when an accept signal is received for the interruption fetch request; interruption cycle 4 generates a storage request and resets external signal latches as well as gating the left half of the PSW through the incrementer to the K register; during both interruption cycle 3 and interruption cycle 4, storage keys are inhibited to have a CPU SAP at this time, interruption cycle 5 comes on when an accept is received for the timer word or old PSW store request, and is utilized therefore as a means of recognizing the fetch request must have been previously received, since the storage unit first provides the new PSW and then must be available in order for the accept signal to cause the cycle 5 latch to be set. Interruption cycle 6 automatically follows interruption cycle 5;

The interrupt last cycle provides a means for leaving the interruption fixed-sequence, or entering into another interruption fixed-sequence in the event of an asynchronous interruption.

14.2.4.1 Interruption Cycle 1 FIG. 346

In FIG. 346, an OR-circuit 1 recognizes the various conditions which can cause the setting of interrupt cycle 1. The OR-circuit 1 is responsive to signals on the MCH CHK START and IE IPL START SEQ lines or in response to either one of two AND-circuits 5, 6, the AND-circuit 5 being operated in other than recovery situations whenever the EXIT latch is turned on if there is no storage request outstanding from the CPU. This is effected by signals on the NOT RCVY PRI, EXIT, and NOT CPU COMM-BUSY lines. Similarly, an AND-circuit 6 will operate when the latch is not on due to the effect of an inverter 7, in response to I IRPT END. The inverter 7 provides priority to the exit latch over the I IRPT END latch. The output of the OR-circuit 1 can be gated through an AND-circuit 2 at A time so as to cause an OR-circuit 3 to set a latch 4. The output of the latch 4 is reflected in a bipolar latch 9 at not L time so as to generate a signal on the IRPT CYC 1 LCH line. The OR-circuit 3 may also respond to an AND-circuit 10 during scan operations due to signals on the J REG 24 and SCAN GT WD 5 line. The latch 4 is reset by an OR-circuit 11 in response to a signal on the CPU RST, or in response to an AND-circuit 12 so as to set a latch 4 to be turned off one cycle after it is turned on due to the presence of a signal on the IRPT CYC LCH line.

14.2.4.2 Interruption Cycle 2 FIG. 347

In FIG. 347, an OR-circuit 3 will cause an AND-circuit 4 to operate an OR-circuit 5 so as to set a latch 6, the output of which is reflected in a bipolar latch 7 at not L time so as to generate a signal on the IRPT CYC 2 LCH line. The OR-circuit 3 is responsive to a signal on the CH IRPT REL LCH line, or to an AND-circuit 8 which responds to a signal on the NOT CH IRPT RESP LCH and IRPT CYC 1 LCH lines. The OR-circuit 3 and the AND-circuit 8 differentiate between channel interruptions and other interruptions, due to the fact that in order for a channel interruption to be handled, it is necessary for the interruption control to signal the channel that the interruption has been accepted (granted priority) and a response must propagate from the CPU back to the channel; thereafter, the channel must indicate that it received the response by sending a release signal back to the CPU. This is controlled by the CH IRPT RESP and CH IRPT REL latches which are shown in FIG. 335 and FIG. 336, and described in the next two sections.

The OR-circuit 5 may also respond to an AND-circuit 9 during scanning operations when there are signals present on the J REG 25 and SCAN GT WD 5 lines. The latch 6 is reset by an OR-circuit 10 in response to a signal on the CPU RST line, or in response to an AND-circuit 11 if operated at A time by a signal on the AC line when there is an output from an AND-circuit 1. The AND-circuit 1 is responsive to an accept signal which indicates that the PSW fetch request has been accepted by the BCU, when interruption cycle 2 is on. This is effected by signals on the ACC EPT and IRPT CYC 2 LCH lines.

When interruption cycle 2 is set, an AND-circuit 12 will generate an interruption fetch request by means of a signal on a IRPT FTCH REQ line provided there is also a signal from the OR-circuit 3 (the same signal which causes the setting of the latch 6 in the first place). In other words, during scanning operations, the interruption fetch request will not be generated by the AND-circuit 12 even though interruption cycle 2 is set. Another AND-circuit 13 provides for turning on timer cycle 1 in the E unit by generating a signal on a TON TIM CYC 1 line in response to a signal on the TIM ADV REQ PRI line.

When the AND-circuit 1 generates a signal for turning of the latch 6, it also generates a signal on the TOF IRPT CYC 2 line, which provides inputs to a plurality of AND-circuits 14, 15, 2. The AND-circuit 14 causes mark bits to be set for storing the higher order half of a storage word, and the AND-circuit 15 provides for the setting of mark bits to permit storing of the low-order half of a storage word. The AND-circuits 14 and 15 are responsive to signals on the NOT IPL K line which indicates that initial-program-loading operation is not involved and that therefore a storage operation will be involved. Additionally, the AND-circuit 15 requires a signal on the NOT TIM ADV REQ PRI line so as to prevent the provision of mark bits for the low-order half of the storage word during a timer advance operation; this is due to the fact that the timer word comprises 32 bits which include only the high-order half of a storage word.

In the event that an initial-program-loading operation is involved, then the AND-circuit 2 will cause the turning on of the IPL buffer which substitutes for interruption cycles 3 and 4 (they being storage cycles) and providing a time delay sufficient to assure the fetching of a PSW for initial program loading.

14.2.4.3 Channel Interruption Response and Release FIG. 335 and FIG. 336

In FIG. 335, when the EXIT latch is turned on, an AND-circuit 1 will recognize the situation of a channel interruption having been granted priority, and will cause an OR-circuit 2 to set a latch 3, the output of which is reflected in the bipolar latch 4 at the start of not l time so as to generate a signal on a CH IRPT RESP LCH line. The OR-circuit 2 is also responsive to scanning signals from an AND-circuit 5 which is connected to J REG 26 and SCAN GT WD 5 lines. The latch 3 is reset by an OR-circuit 6 in response to a signal on the CPU RST line, or in response to an AND-circuit 7 which is operated at A time provided there is a signal on the CH IRPT REL LCH line. In other words, when EXIT is turned on as a result of a CH IRPT, the CH IRPT RESP latch is turned on; when the channel release signal is returned from the channel to the CPU, so that the CH IRPT REL latch is turned on, then the CH IRPT RESP latch will be turned off.

In FIG. 336, an AND-circuit 1 senses a CH REL signal which is a signal from a channel indicating that it has received the response and that it is ready to proceed with the interruption. This signal causes the setting of a latch 2 at not B time, the output of which is applied to an AND-circuit 3. The AND-circuit 3 also requires inputs on a AC line, as well as signals indicating that the response latch has set but the release latch has not set on the NOT CH IRPT REL LCH and CH IRPT RESP LCH lines. The output of the AND-circuit 3 is applied to an OR-circuit 4 and is utilized to set a latch 5, the output of which causes a bipolar latch 6 to be set at not L time so as to generate the signal on the CH IRPT REL LCH line. The OR-circuit 4 is also responsive to an AND-circuit 7 which operates during scanning operations due to signals on the SCAN GT WD 5 and J REG 27 lines. The latch 5 is reset in FIG. 336 by an OR-circuit 8 in response to a signal on the CPU RST line, or in response to an AND-circuit 9 which is operative at A time due to a signal on a CH IRPT REL LCH line. In other words, as soon as the bipolar latch 6 in FIG. 336 has been set, a latch 5 will be reset at the following A time. Thus, the CH IRPT REL signal is available for only one cycle.

14.2.4.4 Interruption Cycle 3 FIG. 348

In FIG. 348, an AND-circuit 1 causes another AND-circuit 2 to operate an OR-circuit 3 so as to set a latch 4 the output of which is reflected in a bipolar latch 5 at not L time so as to generate a signal on a IRPT CYC 3 LCH line. The OR-circuit 3 is also operated by scanning signals due to the J REG 24 and SCAN GT WD 6 lines at the input to an AND-circuit 6. The latch 4 is reset by an OR-circuit 7 in response to a signal on a CPU RST line, or in response to an AND-circuit 8 which is operated at A time once the bipolar latch 5 has been set. Thus, interrupt cycle 3 will remain on for just one cycle.

The AND-circuit 1 recognizes an accept signal from the BCU during interrupt cycle 2 when neither a timer advance nor an initial-program-loading operation are involved. This is due to signals on the ACCEPT, IRPT CYC 2 LCH, NOT TIM ADV REQ PRI and NOT IPL A lines. The signal on the IRPT CYC 3 LCH line is completely coincident with a signal on a STR PSW line, which causes the initiation of storage operations so as to store the old PSW in other than timer or initial program loading operations.

The IRPT CYC 3 LCH line is applied to an OR-circuit 2 in FIG. 332 so as to inhibit the storage keys during store operation, whereby there would be no storage address protection check as a result of storing a PSW during an interruption.

14.2.4.5 Interruption Cycle 4 FIG. 350

in FIG. 350, an AND-circuit 1 responds to a signal on the IRPT CYC 3 LCH line at A time so as to cause an OR-circuit 2 to set a latch 3, the output of which is reflected in a bipolar latch 4 at not L time so as to generate the interruption cycle 4 signal on the IRPT CYC 4 LCH line. This line is utilized with an OR-circuit 5 to generate a IRPT STR REQ signal, the other input to the OR-circuit 5 being IRPT CYC 3. Interruption cycle 4 is also applied to an AND-circuit 6 which recognizes the end of an external interruption at that point by generating a EXT IRPT END signal in response to a signal on the EXT IRPT PRI line. This causes the resetting of the external signal latches in FIG. 341.

The OR-circuit 2 is also responsive to an AND-circuit 7 during scan operations due to signals on the J REG 25 and SCAN GT WD 6 lines. The latch 3 is reset by an OR-circuit 8 in response to a signal on the CPU RST line, or in response to an AND-circuit 9. The AND-circuit 9 recognizes an accept signal during A time of interruption cycle 4 due to signals on a AC, ACCEPT, and IRPT CYC 4 LCH lines. In other words, interruption cycle 4 will act until an accept signal is received from the BCU, and then will be turned off.

The same condition is recognized by an AND-circuit 3 in FIG. 351, and causes the turning on of interruption cycle 5, as described in Section 14.2.5.6.

14.2.4.6 Interruption Cycle 5 FIG. 351

In FIG. 351, either one of two AND-circuits 1, 3 can cause a pair of related OR-circuits 2, 4 to generate identical signals on the TON IRPT CYC 5 and IRPT SET PSW lines. The output of the OR-circuit 2 is applied to an AND-circuit 5 so as to cause an OR-circuit 6 to set a latch 7, the output of which is reflected in a bipolar latch 8 at not L time so as to generate a signal on the IRPT CYC 5 LCH and IRPT END RST lines. These lines are applied to an OR-circuit 9 and, together with a SET PSW line, can cause the generation of a signal on a RST CH IRPT line. This line is utilized in the IE unit to reset the channel priority circuits FIG. 189, FIG. 215 and FIG. 217.

The OR-circuit 6 can also be operated by an AND-circuit 10 in response to scan signals present on the J REG 28 and SCAN GT WD 5 lines. The latch 7 is reset by an OR-circuit 11 in response to a signal on the CPU RST line, or in response to an AND-circuit 12 which causes the resetting of the latch 7 at the first A time following the turn on of the bipolar latch 8; this causes IRPT CYC 5 LCH to remain on for a single cycle only.

At the bottom of FIG. 351, an OR-circuit 13 provides for the resetting of the J loaded circuitry in the E unit by providing for the generation of a I TOF J LD signal in FIG. 191.

The turn on of interruption cycle 5 by the OR-circuit 2 in FIG. 351 coincides with the operation of the OR-circuit 4 therein, which provides for the setting of the PSW by generating a signal on the IRPT SET PSW line. The signal is also applied to an OR-circuit 13 so as to provide for the IRPT RST J LOADED signal described hereinbefore.

14.2.4.7 Interruption Cycle 6 FIG. 353

In FIG. 353, the coincidence of A time and IRPT CYC 5 will cause an AND-circuit 1 to operate an OR-circuit 2 so as to set a latch 3 the output of which is reflected in a bipolar latch at the start of not L time so as to generate a signal on a IRPT CYC 6 LCH line. The OR-circuit 2 can also respond to scan signals supplied on J REG 29 and SCAN GT WD 5 lines to an AND-circuit 5. The latch 3 is reset by an OR-circuit 6 in response to a signal on a CPU RST line, or by an AND-circuit 7 at A time of IRPT CYC 6. In other words, interrupt cycle 6 appears at the end of a L time following an A time of cycle 5, and disappears at the end of L time following an A time in cycle 6. The latch is therefore on for one cycle.

14.2.4.8 Miscellaneous Circuits FIG. 332 and FIG. 358

In FIG. 332, an AND-circuit 1 responds to an accept signal during a timer advance store provided that the machine is running as indicated by a NOT PSW 14 signal, thereby causing an OR-circuit 3 to generate a signal on a IRPT TO RCVY 2 line. This is utilized to initiate an IC recovery in the IC fetch control circuits. Another input to the OR-circuit 3 is an AND-circuit 4 which responds when the machine is running to interrupt cycle 4. In other words, by the time that the interruption fixed-sequence has reached cycle 4, it is anticipated that the PSW will be set for the turning on of cycle 5, and that a recovery so as to fetch instructions in accordance with the new PSW can be initiated at that time.

An OR-circuit 2 inhibits the storage protection keys during a timer advance store, or during the regular interruption storage cycle 3 and 4.

An OR-circuit 5 will cause the left half of the PSW to be passed through the incrementer to the K register during interrupt cycle 4, or when there is a signal on a IE GT LH PSW TO INCR line, the purpose of which is described in the IE sections herein.

An OR-circuit 6 responds to either interrupt cycle 4 or interrupt cycle 5 to cause the gating of the incrementer extender error, which error would accompany the high-order bits of either the left half or the right half of the PSW as it is seen passed through the incrementer to the K register. An OR-circuit 7 responds to an interrupt cycle 3 or interrupt cycle 5 to cause the passage of a PSW to the incrementer.

Setting of the PSW can be in response to the power distribution unit, maintenance control changing of the instruction counter, interruptions, or I execution operations. Thus, an OR-circuit 8 will cause the setting of PSW 0- 39 in response to an AND-circuit 9, or in response to interrupt or IE control over the PSW. An AND-circuit 9 responds to the interrupt in IE controls, and additionally to an AND-circuit 10. The AND-circuit 10 will operate when the maintenance controls are setting an instruction counter, by causing the OR-circuit 9 to generate a signal on the SET PSW 40- 63. The manner in which the various PSW controls of FIG. 332 control the PSW are described in more detail in the PSW section.

14.2.5 INTERRUPT CONTROLS IN IC FETCH AND SEQUENCE AREA FIG. 233 AND FIG. 234

In FIG. 233, a signal is generated on a I IRPT BLK BCU line by an AND-circuit 1 in response to I TO E XFER concurrently with I IRPT FM I. An AND-circuit 2 responds to a pair of inverters 3, 4 so that when there is no I IRPT FM I nor any E IRPT FM I, the inverters 3, 4 will cause the AND-circuit 2 to generate a signal on a NOT IRPT FM I line. Another AND-circuit 5 is responsive to the inverter 4 and to a further inverter 6 so as to generate a signal on a NOT E IRPT line in response to the absence of signals on the E IRPT FM I and E IRPT FM E lines. These lines also operate an OR-circuit 7 so as to cause an AND-circuit 8 to generate a signal on a E IRPT BLK BCU line in response to a signal on a CTRL L CYC line. In other words, if there is an I IRPT FM I at the I TO E XFER, or if there is an E IRPT FM E at the CTRL L CYC, then there will be a signal present at the input of an OR-circuit 9 in FIG. 234 on either an E IRPT BLK BCU or an I IRPT BLK BCU line. The OR-circuit 9 is also responsive to IRPT RST, and to a signal on a IRPT BLK BCU REQ line which is generated by an AND-circuit 13 in FIG. 358 in response to a concurrence of signals on the A IRPT and IRPT L CYC LCH lines. In other words, any one of three entrance routes into the interruption fixed-sequence, as well as interrupt reset, can cause the OR-circuit 9 to operate an inverter 10, whereby there will be no signal on the NO IRPTS line. On the other hand, provided that none of the entrance conditions for interruptions have been met, there will of course also be no interrupt reset, so that the OR-circuit 9 will have no signal and the inverter 10 will provide a signal on the NO IRPTS line, which signal is utilized in permitting the advancing of the sequence within the I unit.

15.0 VARIABLE FIELD LENGTH DATA FLOW

15.1 BRIEF DESCRIPTION OF VFL DATA FLOW FIG. 373

The variable field length portion of said environmental system is designed as a semi-independent unit, which is part of the execution unit, but is designated herein as "VFL," whereas the binary portion of the E unit is designated herein as "E unit," as well as the term E unit meaning both the binary and VFL portions. The VFL portion is concerned primarily with SS format instructions, which include primarily data handling, logical operations, and decimal arithmetic.

The data input to the VFL data flow is from the K and L registers in the E unit, which are used as temporary storage buffer registers for complete 64-bit storage words. Source operands for VFL are fetched from main storage through the J register to the K REG or L REG. The K REG is used for operand No. 1 and the L REG is used for operand No. 2. Results of an operation are placed in the K REG, and at proper times, as determined by rules of storage accessing, those bytes of the K REG which were changed as a result of the operations are returned to storage.

There are several main data paths in the VFL data flow. Normal operands are supplied by the K REG or L REG and are gated through the left byte gate (LBG) or the right byte gate (RBG). From the LBG/RBG, operands can be supplied to the main adder, to the "AND, OR EXCLUSIVE OR (mask)," which is referred to herein as the AOE. In addition, operands which pass through the LBG may be supplied to the digit buffer-digit counter (DB/DC) as well as to the VFL TO AA & PSW gate.

Another input to the VFL data flow is through the direct data and outkey ingate, which controls the application of a byte of data from an external, nonconforming unit (see said System/360 Manual) or from the outkeys circuit of the BCU, which supplies storage protection keys derived from the storage unit. As is seen in FIG. 373, the DB/DC, the AOE, and the DA may each supply results to the K BUS GATE for application over the K BUS back to the K register in the E unit. In addition, the DB/DC may receive results from the DA, may receive results with the digits reversed in position from the AOE, and the digit buffer portion (DB) may receive outputs from the digit counter portion (DC) of the DB/DC.

Another data path is from main storage to the J and K registers, through the LBG, to the direct data register (DD REG). This data is kept available until the next time it is loaded as the result of a write direct instruction. A nonconforming external unit can make whatever use it wishes of the byte data which is stored therein.

Byte selection from among the eight bytes of a 64-bit storage word is accomplished under control of the S and T pointers. The S pointer output selects a correct byte from the RBG, and the T pointer selects a correct byte from the LGB. In addition, the output of the T latch is utilized to control gating of the result byte back into the K register; it is to be noticed that this is an unincremented amount so that it would be specifying, for instance, byte 3 while the output of the T register (which, when decoded, is called T PTR) would be selecting byte No. 4 in the LBG.

Still another data path shown in the data flow of the VFL portion is from IOP through the Y and Z registers, to the AOE and to the VFL TO AA & PSW gate.

Other data flow paths and main controls for VFL data flow are apparent in FIG. 373.

15.2 RIGHT AND LEFT BYTE GATES FIG. 374 THROUGH FIG. 376

15.2.1 RBG FIG. 374

In FIG. 374, a plurality of RBG signals 0-7, P are generated by corresponding OR-circuits 1 in response to a plurality of related AND-circuits 2. The AND-circuits 2 will select from the K or L register in dependence upon the presence of a signal on a GATE K WITH S TGR or GATE L WITH S TGR lines, respectively. A particular byte of the select register is then chosen by one of the outputs 0-7 of the S which relates to the parity bit (shown at the bottom of FIG. 374) allows forcing the parity bit of the RBG in response to a signal on a FORCE RBG P line.

15.2.2 LBG FIG. 375

In FIG. 375, a plurality of LBG lines 0-7, P are energized by related OR-circuits 3 in response to corresponding AND-circuits 4. The inputs to the AND-circuits 4 are the eight bytes of the K register and the digit counter/digit buffer (DC/DB). If one of the K register bytes is to be selected, a signal appears on a GT TD OUT line; when the DC/DB is to be gated, a signal appears on a GT DC/DB TO LBG line. Whenever the K register is selected, the particular byte involved is chosen by a corresponding output 0-7 from the T pointer on T PTR lines.

15.2.3 BYTE GATE SIGN DETECT FIG. 376

In FIG. 376, the byte gate sign detect circuit comprises a plurality of AND-circuits 1, 2 each of which is fed by a related OR-circuit 3, 4. The AND-circuits 1, 3 respond to bits 0-2 and 4-6 of the left byte gate so as to generate signals on the LBG HOD SIGN and LBG LOD SIGN lines. The AND-circuits 2 and OR-circuits 4 respond to the RBG to generate signals on the RBG HOD SIGN and LBG LOD SIGN lines. These circuits merely recognize when either the high order digit or the low order digit of either the left or right byte comprises a sign due to the fact that it represents a value of 10 or more in the extended binary coded decimal code, as is fully described in said System/360 Manual.

At the bottom of FIG. 376, right and left minus signs are detected by OR-circuits 5, 6 in response to related AND-circuits 7, 8. The OR-circuit 5 relates to the right byte gate and the OR-circuit 6 relates to the left byte gate. The AND-circuits 7 both respond to bits 4, 5 and not 6 of the related gate, and the AND-circuits 8 respond to not 5, 6 and 7 of the related gate. This detects minus signs as set forth in said System/360 Manual.

15.2.4 EDIT DECODE FIG. 377 THROUGH FIG. 379

15.3 RIGHT AND LEFT DIGIT GATES FIG. 377 THROUGH FIG. 384

At the top of FIG. 377, a plurality of AND-circuits 1 respond to left byte gate signals so as to generate different binary coded combinations thereof in a well-known manner. These are utilized by an AND-circuit 2 in a plurality of OR-circuits 3 at the bottom of FIG. 377 to decode signals on the LBG EXMN DIG, LBG = DIG SEL, LBG = SIG START, and LBG = FLD SEP lines.

At the bottom of FIG. 378, the signals generated by the OR-circuits 3 at the bottom of FIG. 377 are applied to a plurality of AND-circuits 5, each of which is gated by an edit control signal, and by a related one of the outputs from the OR-circuits 3 in FIG. 377. These cause the setting of related latches 6, which generate signals on the EDT DIG SEL LCH, EDT SIG START LCH, and EDT FLD SEP LCH lines.

The outputs of FIG. 377 are also applied to the edit source decode latches of FIG. 379, where a latch 1 indicates that a zero digit has been sensed, a latch 2 indicates other characters sensed, a latch 3 indicates that the digit has been examined and that a low-order digit is a sign digit, a latch 4 calls for the examination of a digit, and a latch 5 indicates that both the high-order digit and the low-order digit of the right byte gate are not equal to zero.

15.3.1 SIGN GENERATOR FIG. 378

In FIG. 378, a sign generator generates sign bits for the low-order digit input to the right digit gate. This comprises a plurality of signals on SIGN GEN lines 4-7. The operation is in accordance with said System/360 Manual, so as to generate the code 11 00 for a BCD +, or generate the code 10 10 for a + in the ASCII code. Thus, the presence of a signal on the FORCE SIGN DA RIGHT generates a bit 4, and generates a bit NOT 7, and operates a pair of AND-circuits 1, 2 in FIG. 378. The AND-circuit 1 is operative during the BCD code so as to generate a bit 5, and the AND-circuit 2 is operative in the ASCII code as to generate bit 6.

15.3.2 RDG FIG. 380

In FIG. 380, a plurality of right digit gate lines 0-7 are each energized by a corresponding OR-circuit 1, each of which responds to a related pair of AND-circuits 2, 3. The AND-circuits 2, 3 permit gating digits from the RBG through the RBG either straight or crossed. The AND-circuits 2 will gate the digits straight in response to a gating signal from an inverter 4 whenever there is no signal on the GT DIGITS ACROSS DA RIGHT line. However, when said signal is present, then the AND-circuits 3 will gate digits across, transposing digits 0-3 of the RBG with digits 4-7 of the RIGHT DIGIT GT. Additionally, all of the OR-circuits 1 which correspond to bits 0-6 of the RIGHT DIGIT GT are also responsive to single inputs. The low-order bits 4-6 respond to SIGN GEN bits 4-6, and the high-order bits 0-3 are all responsive to a signal on the FORCE ZONE DA RIGHT line. The OR-circuit 1 which corresponds with RIGHT DIGIT GT line 7 does not receive the sign input since when signs are being forced, that position is always forced to 0. This occurs by the lack of a signal on the SIGN GEN 7 line due to the fact that there will be a signal on a SIGN GEN NOT 7 line when a sign is being generated in FIG. 378.

15.3.3 LDG FIG. 381

The left digit gate is shown in FIG. 381. It compares a plurality of AND-circuits 1, 2 each of which corresponds to a corresponding bit from the left bus gate, on LBG line 0-7. Bits 0-3 are gated by a signal on the GT HOD TO DA LEFT line which is applied to the AND-circuits 2, and bits 4-7 are generated by an AND-circuit 1 in response to a signal on the GT LOD TO DA LEFT line.

15.3.4 TRUE COMPLEMENT ZERO DETECT FIG. 382

In FIG. 382, a circuit which detects zero in either the high-order digit or the low-order digit of the output of the right digit gate is shown to comprise a pair of OR-circuits 1, 2 which generate signals on NOT RBG HOD = 0 and NOT RBG LOD = 0 lines. The OR-circuit 1 will respond to any one of the bits 0-3 from the right digit gate, and the OR-circuit 2 responds to bits 4-6 of the right digit gate as well as to an AND-circuit 3. The AND-circuit 3 responds to an inverter 4 when there is no output from an AND-circuit 5. When the AND-circuit 5 is operated, that makes it possible to ignore the low-order bit from the right digit gate determining whether or not a zero is present. The AND-circuit 5 operates in response to signals on the DA CARRY TGR, RSLT BYTE NOT ZERO, T3 TGR, VFL T2 TGR, NOT T8 TGR, and IS 2 TGR lines.

15.3.5 PARITY ADJUST FIG. 383 and FIG. 384

Parity is adjusted for both the right and left gates before the parity bit is applied to the decimal adder. In FIG. 383, a right parity adjust circuit comprises essentially an OR-circuit 1 which is set by four AND-circuits 2-5. The AND-circuit 2 permits using the parity as received from the RBG in response to a signal on a GT RBG P TO DA line. The AND-circuit 3 gates the parity of the high-order bit only in response to a GT LOD BIN & NOT GT HOD line. This parity is generated by an EXCLUSIVE OR circuit 6 in response to the high-order bits. The AND-circuit 4 responds to an exclusive OR circuit 7 when there is a signal on a GT HOD DEC & LOD DEC line, the EXCLUSIVE OR circuit 7 sensing the change in the parity bit as a result of the operation of the decimal converter at the input to the decimal adder, which is described in the next following section. The AND-circuit 5 responds to an EXCLUSIVE OR circuit 8 which tests the odd or even character for the combined output of the EXCLUSIVE OR circuit 9 and 10; the AND-circuit 5 is operated on the control of a signal on a GT P LOD V INVRT SIGN V HOD 4-5 line.

Left parity adjust is more simple as illustrated in FIG. 384. A signal on the LEFT P ADJUSTED line is generated by an OR-circuit 1 in FIG. 384 in response to a signal on a FORCE P LEFT line, or in response to any one of three AND-circuits 2-4. The AND-circuit 2 responds to parity from LBG when there is a signal on a GT LEFT P STRAIGHT line. The AND-circuit 3 responds to the output of an EXCLUSIVE OR circuit 5 which senses the parity of the high-order digit, the AND-circuit 3 operating when there is a signal on a GT HOD P LEFT line. The AND-circuit 4 responds to a signal on a GT LOD P LEFT line when there is an output from the EXCLUSIVE OR circuit 6 which in turn is responsive to the parity of the low-order digits and the input parity.

15.4 DECIMAL ADDER

The decimal adder comprises essentially an input decimal converter, a binary adder, and an output decimal converter. Conversion takes into account that the nines complement of decimal + 6 is equal to the ones complement of the raw decimal input. The decimal adder also includes parity prediction circuits in accordance with well-known principles of arithmetic.

15.4.1 TRUE/COMPLEMENT AND EXCESS 6 GATE FIG. 385

The true/complement and EXCESS 6 gate is shown in FIG. 385 to comprise two portions, one for the low-order digits (bits 4-7), and one portion for the high-order digits (bits 0-3).

Bits 4-7 of the true/complement and EXCESS 6 gate of FIG. 385 comprises essentially a plurality of OR-circuits 1, 2 each of which is fed by related AND-circuits 3-5. The AND-circuits 3-5 recognize signals on GT LOD CPMNT, INVRT SIGN TO P ADJ AND T/C GATE, GT LOD BIN TRUE, and GT LOD DEC TRUE lines to gate correct ones of the right digit gate bits and their complements through to the decimal adder in dependence upon whether the low-order digit is to be gated complement (both for binary and decimal) or whether it is to be gated binary true or decimal true. The manner in which this circuit operates is in accordance with well-known principles of EXCESS 6 arithmetic, so as to create those bits at the adder input which are called for as shown in the following table:

DIGIT DIGIT GT GT DEC DEC + 6 4 5 6 7 4 5 6 7 0 0 0 0 0 1 1 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 1 1 0 0 0 1 1 1 0 1 1 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 1 1 1 0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 1 1 0 0 1 0 0 1 1 1 1 0 1 0 1

in FIG. 385, an OR-circuit 6, and an inverter 7 recognize the case where the sign of the low-order digit is to be reversed, and an OR-circuit 8 causes the AND-circuit 4 to operate identically for decimal and binary true insofar as the low-order bit is concerned.

At the bottom of FIG. 385, a plurality of circuits 9 operate identically with the circuits 1-8 with the exception of the fact that high-order bits and high-order control lines are utilized, and there is no invert sign input to the circuit 9.

15.4.2 BINARY ADDER FIG. 386

In FIG. 386, the binary adder portion of the decimal adder is shown. This comprises two eight-bit sections, each of which is identical to the adder groups shown in said environmental system in the address adder and in the main adder. The low-order digit portion is shown in block form, whereas the high-order digit portion is represented by a single block 1 at the bottom of FIG. 387. A carry can be recognized at the low-order portion of the adder by a signal on a DA CARRY IN line. Bits 4-7 of the DA T/C IN lines from the true/complement-- +6 circuit as well as bits 4-7 from the left digit gate are applied to the low-order half of the adder. These bits together with the DA CARRY IN are utilized to generate half sums 4-7 and binary sums 4-7. In addition, a carry generator 2 generates a carry out of the four-bit group which is combined in an OR-circuit 3 with a signal on a FORCE CARRY TO HOD line. Thus, a signal on a C OUT LOD can be generated as a result of the arithmetic in the low-order bit, or as a result of forcing of a carry. The carry out of the low order is applied to the high-order adder portion 1. Bit carries are generated in the circuit 4 in a usual fashion, and are combined with transmit and generate bits from a circuit 5 in an AND-circuit 6 and an OR-circuit 7 so as to compare the predicted carry with a generated carry so as to cause an EXCLUSIVE OR circuit 8 to generate a carry error signal for the low-order digit on a C ERR LOD line.

The high-order half of the adder operates in a same fashion except for the fact that bits 0-3 are applied thereto along with the signal on the C OUT LOD line, and there is no forced carry into the high-order portion 1.

15.4.3 TRUE/COMPLEMENT--DECIMAL CORRECTION CIRCUIT FIG. 387

In FIG. 387, a plurality of latches 1 each correspond to one of the bits 4-7 of the low-order portion of the adder. The input to the latches 1 comprise a plurality of AND and OR circuits which operate so as to correct a binary result, as necessary, for complement outputs, and for decimal outputs. The conversion is in accordance with well-known principles of decimal addition with the exception of the fact that the circuit of FIG. 387 assumes the decimal digits having a value of 10 through 15 as well as decimal digits having a value of 0 through 9 may be applied at the input to the binary adder. This permits the decimal correction circuit to provide correct outputs that will match the predicted parity bit and therefore not cause a parity error even though decimal values greater than 9 are received at the input to the binary adder. Since correct parity results are obtainable, the application of an invalid decimal digit (having a value greater than 9) to the decimal adder will not cause a parity check, but instead will permit the sign detecting apparatus to cause a decimal data interruption as described in said System/360 Manual.

The operation of the decimal correct circuit of FIG. 387 is obvious in view of well-known principles of decimal correction, which are described and illustrated in said copending application of Robert Keslin. The difference in the operation of the circuit in FIG. 387 is apparent in view of the following charts, which illustrate decimal correction for values including decimal digits greater than 9. ##SPC9##

15.4.4 DECIMAL CARRY TRIGGER FIG. 388

In FIG. 388, the signal on the C OUT HOD line which manifests a carry out of the decimal adder causes an AND-circuit 1 to set a latch 2, the output of which is applied to an inverter 3 and an AND-circuit 4. The AND-circuit 4 causes an OR-circuit 5 to set the carry trigger 6 whenever there is a signal present on the REL DA CARRY TGR line concurrently with a signal on the AC line. If there is no output from the latch 2, then the inverter 3 causes an AND-circuit 7 to pass a signal through an OR-circuit 8 so as to reset the trigger 6. The OR-circuit 8 also responds to CPU RST. The output of these triggers 6 on the DA CARRY TGR line can be gated by a signal on a GD CARRY TGR LOD line through an AND-circuit 9 so that an OR-circuit 10 will generate a signal on the DA CARRY IN line, which carry is utilized as a carry into the lowest bit position of the decimal adder. The OR-circuit 10 also responds to a signal on the FORCE CARRY TO LOD line.

15.5 DA CHECKING

15.51 DECIMAL ADDER PARITY PREDICT FIG. 389

In FIG. 389, an ordinary binary parity predict circuit is combined with the output of two AND-circuits 2, 3 and an EXCLUSIVE OR circuit 4 so as to cause an AND-circuit 5 to set a latch 6 whenever the output of the decimal adder requires a parity bit in order to achieve total odd parity. The binary parity predict circuit 1 is the same as illustrated in the address and main adders of said environmental system. The outputs of the AND-circuits 2, 3 take into account the effect of carries in the parity prediction which is made by the circuit 1.

15.5.2 DA HALF SUM CHECK FIG. 390

In FIG. 390, the digit adder half-sums for bits 0-9 are combined in one EXCLUSIVE OR circuit 1 with the adjusted parity inputs from the right and left digit gates which are combined in an EXCLUSIVE OR circuit 2. Thus, an EXCLUSIVE OR circuit 3 will indicate when the total oddness or evenness of the half-sums is not identical to the total oddness or evenness of the adjusted parity bits by generating a signal on a DA HS CHK line.

15.5.3 DA ERROR CIRCUIT FIG. 391

In FIG. 391, carry errors for the high-order digit and a low-order digit are applied to an OR-circuit 1 so that an AND-circuit 2 can set a latch 3 whenever there is a carry error in either the high- or low-order digit. Also, the DA HS CHK signal from FIG. 390 is applied to an AND-circuit 4 so as to set a latch 5 whenever there is a half-sum check. The output of these two latches is gated through a pair of AND-circuits 6, 7 so as to set related triggers 8, 9 whenever there is a signal on a SET DA ERR TGRS. Thus, either a decimal adder carry error or a decimal adder half-sum error will be manifested on the DA C ERR TGR and DA HS ERR TGR lines, respectively. These two lines are fed to an OR-circuit 10 so as to generate a signal on a DA ERR line, which signal is utilized in the I unit so as to effectively alter system response as a result of the error.

15.6 DIRECT DATA AND OUTKEY INGATE FIG. 391a

In FIG. 391a a plurality of OR-circuits 1 will generate high-order bit DD OR OUT KEY bits 0-3 which correspond to direct data bits 0-3, and which corresponds to outkeys 1-4. These are gated respectively by AND-circuits 2, 3 in response to signals on the GT DD IN TO AOE and GT KEY TO AOE lines, respectively. High-order direct data bits are gated through AND-circuits 4 in response to the GT DD IN TO AOE signals.

15.7 AND-OR-EXCLUSIVE OR CIRCUIT FIG. 392-FIG. 393

In FIG. 392, inputs to the A O E circuit are generated by a plurality of OR-circuits 1, 2. The OR-circuits 1 are energized by corresponding AND-circuits 2, 3, 4 in response to signals on the GT Y & Z TO AOE, GT LBG 5-7 TO AOE, and GT LBG 0-4 TO AOE lines, respectively. These lines correspond to inputs from the Z register, from the low-order portion of the LBG, and from the high-order portion of the LBG, respectively. In addition, a plurality of OR-circuits 2 permit gating the right bus gate (RBG) or the DD OR OUT KEY signals 0-7 to the AOE.

In FIG. 393, the AND-OR-EXCLUSIVE OR circuit is shown to comprise a latch 1 settable by an OR-circuit 2 in response to any one of three AND-circuits 3-5 for each of the seven bits of the AOE. This is represented by the circuit 6 which would be identical to the circuits 1-5 except for the particular inputs thereto relating to bit 0 rather than to bit 7. The operation of the circuit is relatively simple, calling for the setting of the latch 1 whenever the particular logical operation being called for has been met by the right and left bits at the input thereto. If a AND OP is called for, an AND-circuit 3 will cause the OR-circuit 2 to set the latch 1 only if bit 7 is present from both AOE IN L and AOE IN R (left and right respectively). If a OR OP is called for, an inverter 7 will block an AND-circuit 8 so that there will be a signal from an inverter 9 enabling either the AND-circuit 4 or the AND-circuit 5 to respond to a right or left bit 7, there also being a signal present on an OR & EXCLSV OR OP line. When the EXCLUSIVE OR is called for, there will be a signal on the OR & EXCLSV OR OP line, but there is no signal on the OR OP line so that an inverter 7 does not block an AND-circuit 8, rendering the AND-circuit 8 responsive to whether or not both bits R and L are present at the input thereto. If they are, then the AND-circuit 8 will operate so that there will be no output from an inverter 9; if one of them is not present, then the AND-circuit 8 will not operate, so that the AND-circuit 9 will operate, and permit either the AND-circuit 4 or 5 to operate in dependence upon which of the two bits is present. Thus, these circuits perform the EXCLUSIVE OR operation as well as the OR and the AND. As is to be expected, when an EXCLUSIVE OR operation is being performed, the latch 1 will be set when either one but not both of the bits are present at the input thereto.

15.8 DIGIT BUFFER DIGIT COUNTER

15.8.1 DIGIT BUFFER (DB) FIG. 394

The digit buffer shown in FIG. 394 comprises a latch register including latches 1 which are settable by OR-circuits 2 in response to related AND-circuits 3-5. The AND-circuits 3 respond to bits from the left byte gate when there is a signal on a GT LBG TO DC/DB line. The AND-circuits 4 respond to bits from the A-O-E when there is a signal on the GT AOE TO DC/DB line. The AND-circuits 5 respond to bits from the digit counter when there is a signal on a GT DC TO DB line. The triggers 1 are reset by OR-circuits 6 in response to an AND-circuit 7 which recognizes the signal on a GT REL DB line indicating that the triggers are to be released (that is not latched up in a frozen condition). Otherwise, the OR-circuit 6 can respond to a signal on a CTRL RST DB line.

15.8.2 DIGIT COUNTER (DC) FIG. 395

The digit counter shown in FIG. 395 comprises essentially three portions: an input portion, a change generator portion, and a latch portion the input to which comprises the EXCLUSIVE OR of the input bits and the change bits.

The input portion of the digit counter comprises a plurality of OR-circuits 1 which recognize different input conditions at AND-circuits 2-5. These AND circuits respond respectively to signals on the GT DA TO DC/DB, GT AOE TO DC/DB, GT LBG TO DC/DB, and GT J TO DC lines. Additionally, the OR-circuits 1 can respond directly to a signal on a FORCE LINE TO DC line. The FORCE 9 line would be operative for bits 0 and 3 only, so as to generate a decimal value of 9 at the output of the OR-circuits 1.

The change portion of the digit counter (shown in the middle of FIG. 395) responds to COUNT DC UP and COUNT DC DN signals so as to generate CHANGE DC signals in a manner which is described in detail with respect to the S pointer, which is shown in detail in FIG. 404, and described in detail with respect thereto.

The latch portion of the digit counter shown at the bottom of FIG. 395 responds to the digit counter inputs, and to the change digit counter bits together with a GT REL DC signal and CPU RST so as to provide an incremented output as described in detail with respect to the Y latch shown in FIG. 399.

15.8.3 DIGIT COUNTER/DIGIT BUFFER PARITY FIG. 396

The digit buffer digit counter parity includes an OR-circuit 1 which is operated by AND-circuits 2 in dependence upon conditions within the digit counter/digit buffer. The AND-circuits 2 recognize cases where parity will change as a result of counting up or counting down, alternatively, in dependence upon the various bits in the counter at the time it is incremented. This is in accordance with well-known rules of binary addition, as is described with respect to the addressing adder and the incrementer in said environmental system. The output of the OR-circuit 1 is applied to an EXCLUSIVE OR circuit 3 which causes an AND-circuit 4 to reflect the change in a latch 5. The latch 5 can respond to the AND-circuit 4 to either have an output or not, in dependence upon an output from the EXCLUSIVE OR circuit except that L time due to the signal on the NOT LC line. The output of the latch 5 is gated by an OR-circuit 6 through an AND-circuit 7 provided there is also a signal from an AND-circuit 8 due to a signal on the GT REL DC line at A time. Additional AND-circuits 9 select parity bits from the digit adder, from the AOE, and from the left byte gate in response to corresponding gating signals, the output of any one of which will cause an OR-circuit 10 to operate a latch 11 so as to provide a signal on the DC/DB P line. The latch 11 is prevented from changing whenever there is no output from the AND-circuit 8, and is permitted to be reset at the start of A time by the AND-circuit 8.

15.9 DIRECT DATA REGISTER FIG. 397

The direct data register comprises a plurality of latches 1 as shown in FIG. 397. The latches 1 are set by AND-circuits 2 in response to a gating signal from an AND-circuit 3 when there is a signal on a GT DIRCT CTRL REG REL line, together with a AC clocking signal. Each of the AND-circuits 2 respond to corresponding bits of the left byte gate.

15.10 Y AND Z REGISTERS AND LATCHES

The byte parity must be adjusted whenever a partial byte is gated to the adder or bits are altered as they are gated to the adder. When gating digits Decimal True, the digits 4 and 5 are the only ones that change parity.

PARITY CHANGE 0000 E 0110 E 0001 O 0111 O 0010 O 1000 O 0010 E 1001 E 0100 O 1010 E X 0101 E 1011 O X 0110 E 1100 E 0111 O 1101 O 1000 O 1110 O 1001 E 1111 E

there are two gating combinations of DT that require parity adjustments:

a. (HOD DT) & (LOD BT)

b. (HOD DT) & (LOD DT)

All other parity adjustments are made because either the HOD or the LOD is not gated to the adder. Following is a chart showing the possible gate combinations and the adjusted parity. ##SPC10##

The LBG is connected straight to the gate into the left side of the adder. This gate is split between bits 3 and 4 for High- and Low-order digits. The parity adjust gate has the following possibilities:

a. P straight

b. P H. adjusted for HOD removed

c. P L, adjusted for LOD removed

Parity is forced to the left side of the adder at the parity adjust gates.

15.10.1 YZ REGISTERS FIG. 398

At the top of FIG. 398, a pair of OR-circuits 1, 2 generate release signals which permit the state of the Y and Z registers to change. These are responsive to signals on the GT REL Z AT A-GT REL Y AT B lines in combination with signals on the AC and BC lines. Thus, the OR-circuits 1, 2 will operate at either A time or B time in dependence upon the particular type of signal received at the input to one of the related pair of AND-circuits 3.

The release signals generated at the top of FIG. 398 are applied to the Y and Z registers shown in the middle, and bottom, respectively of FIG. 398. The Z register comprises essentially a latch 1 which is set by an OR-circuit 2 in response to a SCAN signal or in response to either one of a pair of AND-circuits 3, 4. The AND-circuit 3 recognizes a signal on a GT IOP (12-15) TO Z line so as to gate IOP bit 15; and AND-circuit 4 responds to a signal on a GT Z LATCH TO Z line so as to gate the output of the Z latch back into the Z register. This output is an incremented output whereby the contents of the Z register is incremented as it is passed to the latch, and when returned to the Z register will have a value which is one greater than its originally was. The latch 1 is reset by an OR-circuit 5 in response to the REL Z line, or in response to a signal on a RST Z line. Each bit of the Z register is identical with the exception of the fact that different bit lines are applied thereto, as illustrated by the circuit 6. The Y register is essentially identical to the Z register with the exception of the fact that a pair of AND-circuits 7, 8 response to IOP bits 8-11 and to the Y latch bits, instead of to IOP 12 to 15 and the Z latch. Additional circuits 9 are provided for the other bits of the Y register.

15.102 Y/Z INCREMENTING CIRCUITS FIG. 399

In FIG. 399, circuits which recognize the incrementing or decrementing of the Z register operate in accordance with a truth table, by determining whether or not a particular bit will change as a result of incrementing and/or decrementing, respectively. This is in accordance with well-known principles of binary addition. Concerning the lowest order bit (bit 3) of the Z incrementer, an OR-circuit 1 will generate a signal on a CHANGE 23 line in response to signals on either the COUNT Z 1-3 UP or COUNT Z 1-3 DN lines. Thus, whether counting up or down, any count will cause a change in a low-order bit. Whenever the low-order bit is changed from a 1 to a 0, if an up-count is involved, then bit 2 should be changed on the other hand, when counting down, if bit 3 is changed from a 0 to a 1, then bit 2 ought to be changed. Thus, an OR-circuit 2 and a pair of AND-circuits 3, 4 recognize conditions under which bit 2 should be changed. Bit 1 should be changed or not in accordance with the same principles as bit 2, in dependence upon whether an increment or a decrement is involved, and whether bit 2 is a 1 or a 0 at the start of the incrementing operation. For bit 0, the only difference is that independent count lines are provided which correspond to the count lines for bits 1-3; these are COUNT Z 0 UP and COUNT Z 0 DN.

The Z register is low order in comparison with the Y register, and certain conditions are recognized by an OR-circuit 5 so as to generate a signal on a CARRY TO Y CTR line. An AND-circuit 6 will operate when the high-order bit of Z is being counted down, and the remaining bits of the Z register are 0; similarly, an AND-circuit 7 will operate the OR-circuit 5 when ZO is being counted up and the remaining bits of the Z register are 1. The AND-circuits 6 and 7 only operate when the system is not in transmit mode, meaning that operations are on a byte basic, rather than on a 64-bit storage word basis. When in the transmit mode, the presence of a count Z up signal, together with a ZO bit will cause an AND-circuit 8 to generate the carry. As illustrated by a circuit 9, additional circuitry is provided for the Y incrementer (with the exception of the carry circuit 5), which circuitry is similar to the circuitry 1-4 illustrated at the top of FIG. 399.

15.10.3 Y AND Z LATCHES FIG. 400.

The Y and Z latches comprise essentially latch circuits 1, 2 which are set by related AND-circuits 3, 4 in response to a signal from an AND-circuit 5 which in turn recognizes NOT L time concurrently with a signal on a NOT HOLD Y & Z LCH line. Other inputs to the AND-circuits 3, 4 are related EXCLUSIVE OR circuits 7, 8 which change the setting of the latch with respect to the corresponding register position whenever there is a change signal at the input thereto. The change signals relate to each bit, as is shown in FIG. 399. As an example, if there is a Z register bit 3, and a signal appears on the CHANGE Z 3 line, then the uppermost EXCLUSIVE OR-circuit 7 will cause its related AND-circuit 3 to set the latch circuit relating to bit 3 at the top of FIG. 400. The other circuits operate in a similar fashion. Each of the latches 1 is reset by a related OR-circuit 9 in response to the output of the AND-circuit 5 or in response to a signal on a RESET Z line. Similarly, OR-circuits 10 will reset the latches 2 in response to the AND-circuits 5 or in response to a signal on the RESET Y line.

15.11 VFL TO ADDRESS ADDER AND PSW GATE FIG. 401.

In FIG. 401, a plurality of VFL LGTH lines 23-31 and P 16-23, as well as a plurality of E UNIT ADR Lines 0-7 are energized by a plurality of corresponding AND-circuits 1. Each OR circuits responds to a related set of AND-circuits 2-5. The AND-circuits 2 cause gating of Z latch 0-3 to the low-order OR-circuits 1 (top of FIG. 401) and Y bits 0-3 to the high-order OR circuits (bottom of FIG. 401). The AND-circuits 3 permit gating the Y register to either bits 28-31 of the address adder or to bits 24-27 of the address adder in dependence upon which gating line is utilized. The AND-circuits 4 permit gating the Z register to address adder 28-31, or permit gating the shift counter to address adder bits 28-31, in which case an AND-circuit 6 provides bit 23 to the address adder, and an inverter 7 will in that case not provide a parity bit for the byte of the address adder which includes bit 23. Whenever the shift counter is not gated to the address adder, a parity bit is available to the address adder for bits 16-23 from the inverter 7. The AND-circuits 5 permits gating the left byte gate to address adder positions 24-31. The operation of the circuit of FIG. 401 should be apparent from examination thereof. At the bottom of FIG. 401, an EXCLUSIVE OR complex 8 responds to E unit address bits 1-7 (which of course is also the same as bits 24-31 of the VFL length bits) so that an inverter 9 will generate parity bits whenever the EXCLUSIVE OR is even, thereby having no output so that the inverter 9 will have an output.

15.12 VFL TO K REGISTER BUS

15.12.1 K BUS GATE FIG. 402

In FIG. 402, a plurality of VFL K BUS lines 3-7, P are each energized by related OR-circuits 1-3 in response to corresponding AND-circuits 4-8. The two AND-circuits 4 are operative in the alternative, one recognizing the case when the out keys are being gated to K the other recognizing the case when keys are being gated to K so as to utilize a correct related one of the parity bits. Otherwise, whether the AOE or the keys are being gated to K, and AND-circuits 5 provide gating in response to the output of an OR-circuit 9. The AND-circuits 6 relate to DC/DB, the AND-circuits 7 relate to decimal adder bits 1, 3-7 and P, and the AND-circuits 8 relate to bits 0 and 2 of the decimal adder.

15.12.2 K BUS ZERO DETECT FIG. 403

In FIG. 403, a pair of OR-circuits 1, 2 sense the various bits of the VFL K BUS, so as to determine that the K bus has a value other than zero. The output of the OR-circuit 1, however, is not utilized unless it is gated by an AND-circuit 3 in response to a signal on a NOT BLK SIGN SAMPLE ZERO DET line. An output from the AND circuit or from the OR-circuit 2 will cause an OR-circuit 4 to pass a signal to an AND-circuit 5 for gating by a signal on the EN VFL RSLT ZERO DET TGR line at A time. This causes an OR-circuit 6 to set a latch 7 which generated a signal on a RSLT BYTE NOT ZERO line. The latch 7 may be reset by an OR-circuit 8 in response to CPU RST, or in response to an AND-circuit 9 which is operated by a signal on the ELC LCH line.

15.13 S AND T POINTERS

15.13.1 S AND T LATCHES FIG. 404

The S and T latches each comprise three bits, each of which includes a latch circuit 1 settable by an OR-circuit 2 in response to two AND-circuits 3, 4 in dependence upon whether the H register or the S register is to set the latch. Initial data input to the S and T pointers is from the H register, and the S and T latches feed incrementers which feed the S and T registers. The output of the S and T registers is decoded to provide the S pointer and T pointer controls for selecting bytes at the right byte gate and at the left byte gate. The latch 1 in FIG. 404 is reset by a signal on a RST S PTR line, or by a signal on a NOT LC line, due to the OR-circuit 5. Additional circuits 6, 7 relate to bits 1 and 0 of the S latch, and they would be identical to the circuits 1-5 which relate to bit 2 of the bit latch.

The T pointer comprises a plurality of circuits 8, 10, 11 each of which is identical to the circuits 1-5, the T latch being gated and reset by an OR-circuit 12 which so, S1 only responds to LC time (as does the S latch), but also to a signal on C NOT HOLD T LCH line.

15.13.2 S AND T INCREMENTERS FIG. 405

The S incrementer as shown at the top of FIG. 405 responds to bits 1 and 2 of the S latch so as to provide change signals for bits S0, S1 and S2, which provide incrementing of the S value at the input to the S register. The operation of the S and T incrementers is identical to the operation of bits 1-3 of the Z incrementer shown in FIG. 399. Thus, the OR-circuits 1, 2, 3 in FIG. 405 correspond to the OR-circuits 1, 2, 10 in FIG. 399. The change circuit 4 for the T pointer is identical to the circuits 10-3 in FIG. 405.

15. 13.3 S AND REGISTERS FIG. 406

The S and T registers each comprise three bits, each bit thereof including a latch 1 set by an AND-circuit 2 when there is an output from an EXCLUSIVE OR circuit 3, in the same fashion as the Z and Y latches shown in FIG. 400. Each of these registers is made operable by a signal from an AND-circuit 4, 5, respectively, in response to signals on the REL S PTR and REL T PTR lines. The registers are reset by corresponding signals on RST S PTR and RST T PTR lines.

15.13.4 S AND T POINTER DECODE CIRCUITS FIG. 407- FIG. 409

The output of the S and T registers is decoded in a purely binary fashion by the circuits of FIG. 407-409. The S pointer is decoded in FIG. 407, and the T pointer is decoded in FIG. 409 in purely binary decoders. The T pointer is decoded in FIG. 408 in a binary decoder which has, however, the ability to force a 3 output therefrom in response to a signal on the FORCE K BYTE 3 line which is applied to an OR-circuit 1 in FIG. 408. The S pointer output of FIG. 407 is utilized to gate a correct byte from the K register through the left byte gate, and the T pointer output of FIG. 408 is used to select a correct K or L register byte at the right byte gate. The TD IN output of FIG. 409 is used to gate a correct byte from the VFL data flow back into the K register. In other words, the TD IN signals are utilized to cause the VFL K bus (FIG. 402) to be applied to the correct position of the K register.

16.0 VARIABLE FIELD LENGTH CONTROLS

16.1 INTRODUCTION TO VFL CONTROLS

16.1.1 EXECUTION SEQUENCES AND INTERRUPTS

The execution of an SS instruction is divided into five sequences:

A. set-Up

B. iterations

C. store-Fetch

D. prefetch

E. address Put-Away (TRT and EDMK only)

All sequences of Decimal multiply and divide are described in section 17.0 et seq. and, therefore, this section does not include multiply and divide with the exception of the section on interrupts. The VFL Sequencers are shown in FIGS. 409a- 471.

The execution of all SS instructions start with a Set-Up sequence. For repetitive byte operations, Iteration sequencers are used. Operand one fetching and storing is done by Store/Fetch sequencers. Operand two fetching is done by Prefetch sequencers. The putaway of operand addresses and result bytes in general registers is done by VFL SEQs A, B, C, and D.

The following is a general description of each of these sequences.

16.1.1.1 Set-Up

The Set-Up prepares counters and registers for the start of Iterations. This consists of:

1. address calculation (low-order three bits to T or S) and set fetch requests

2. address comparison for overlapping fields

3. initial setting of Y and Z

4. transfer words, returned from main storage, from J to K and L.

5. set initial values in ER and SC

6. set VFL gating triggers

The address comparison for overlapping fields is made because byte operations must be executed in such a way that the result appears to have been generated by operating one byte at a time from main storage. When the operands do not overlap into the same storage word, there is no difference between operating a byte at a time or eight bytes at a time from main storage.

In Decimal operations, the comparison is made to determine if the destination (operand number one) resides in lower order storage than the source (operand number two). In logical operations, the comparison is made to determine if the destination resides in higher order storage than the source.

If the difference between the starting addresses of the two operands is 0-7, there is a possibility that bytes will be taken from the same storage word during execution. When it is detected that the source and destination are in the same word, the RBG is switched to gate from K instead of L and thus both the LBG and RBG takes bytes from K.

If the difference between the starting addresses of the two operands is 8-15 then the word which would be fetched by a Prefetch is actually being generated in K. Therefore, Prefetch is blocked and K is gated to M during each Store/Fetch sequence.

16.1.1.2 Iterations

The Iterations are the actual processing of data, one byte at a time. Each time a source (operand No. 2) byte is processed, Z and S are stepped. Each time a destination (operand No. 1) byte is processed, Y and T are stepped. As mentioned in the Y and Z description, Y and Z are stepped separately for Decimal operations and stepped as one counter for Logical operations. The Iterations are controlled by sequencers IS 1, IS 2 and IS 3. See FIGS. 444-452.

16.1.1.3 Store/Fetch

The Store/Fetch sequence is initiated whenever a destination word boundary is reached or the end of operation is signaled. The address is calculated and the VFL store request is set. This stores a result word. If there is another word required for the destination, the address is calculated and the VFL fetch request is set. For the end of the operation, SF 5 is the last cycle. If it is not the end of the operation, SF 6 transfers J to K and the sequence returns to Iterations.

The crossing of a destination word boundary is indicated by the T pointer. When moving right to left through a field, the T pointer equals zero at the word boundary. When moving left to right through a field, the T pointer equals seven at a word boundary.

The end of operation conditions vary for different instructions but the most common conditions are Y or Z going to all ones. See FIGS. 438-441.

16.1.1.4 Prefetch

The Prefetch sequence is initiated each time a source word is needed. The Prefetch sequence is normally overlapped with the iterations or setup. The first source word is fetched during Set-Up. The second source word fetch (first Prefetch) is initiated during Set-Up. When the source word returns, it is put in M. The first cycle of Prefetch transfers M to L. The iterations are started again after PF 1. The remainder of the Prefetch sequence is allowed to follow PF 1 if another source word is required. See FIGS. 427-437.

16.1.1.5 Address Put-Away

Two instructions, Translate and Test and Edit and Mark, put information in general registers as part of their result.

Translate and Test inserts the argument address (operand No. 1 address) in the low-order 24 bits of GR 1 and the translated byte (nonzero byte from the translation table, operand No. 2) in the low-order 8 bits of GR 2. These results are inserted in GR 1 and 2 only if a nonzero byte is found.

Edit and Mark inserts the byte address of the first significant result digit in the low-order 24 bits of GR 1.

Sequencers A, B, C, D, IS 1 and IS 3 are used for the TRT address put-away and sequencers A, B, C, D and IS 1 are used for the EDMK address put away.

16.1.1.6 VFL Interruptions

VFL operations can have the following interrupts:

Invalid Address

Data

Specification

Decimal Overflow

Decimal Divide Check

Some of the above conditions are shown in FIG. 515.

The invalid address interrupt can occur on any fetch, and all SS instructions have at least one fetch. The address invalid trigger is reset at the beginning of each SS execution, and when set, remains on, even through valid words may return to J after the trigger is set. For all SS instructions except Multiply and Divide, the address invalid trigger is sampled at SU 7, SU 9, and SF 6. For SS Multiply and Divide, the address invalid trigger is on, the sequence is switched to SF 3. The E interrupt trigger blocks the set of VFL request triggers and cause the VFL end sequence trigger to be set.

The data is checked on each iteration cycle and the interrupt triggers are set if a sign or digit is detected in the wrong place. During the next Store/Fetch sequence, the E interrupt trigger causes VFL end sequence to be set and blocks the set of both VFL request triggers.

The specification interrupt can occur for Decimal, Multiply, or Divide. L 1 and L 2 are checked during SU 2. If L 2 L 1 or L 2 <7, the Store/Fetch trigger is set and the ending sequence follows.

Decimal Overflow can occur on AP, SP and ZAP. The occurrence of the overflow interrupt does not alter the execution of the instructions.

Decimal Divide Check is sampled during SEQ A of Divide Test. A Divide Check switches the sequence to SF 3 which starts the end sequence.

16.1.2 MISCELLANEOUS CONTROL TRIGGERS AND SEQUENCES

16.1.2.0 VFL T 1- 8 Triggers

VFL T 1-8 triggers are a group of multipurpose control triggers. All of these triggers are set at A time and VFL T2, VFL T3, and VFL T5, have latched outputs. The details of each trigger' s use are given in the individual instruction descriptions.

16.1.2.1 VFL Store Request and Fetch Request Triggers

These are two intermediate request triggers use for E unit storage requests. They have two outputs. One output is to the BCU and the other to the I units. The I unit uses store request to initiate an address compare and the fetch request to return the word to J. The BCU sets their request triggers at A time following the rise of the VFL line. The VFL request triggers are set at B time and are reset with A time and Accept. The set for these triggers is latched to generate the gating line "Gate AA to SAR and H."

16.1.2.2 Store/Fetch Trigger

There are 12 sequence triggers used for Set-Up and Store/Fetch. The Store/Fetch trigger is a supervisory trigger which controls which functions the sequences perform. With the Store-Fetch trigger off, VFL SEQs 1-12 are Set-Up sequencers (SU 1, SU 2, etc.). With the Store/Fetch trigger on, VFL SEQs 1-6 are Store/Fetch sequencers (SF 1, SF 2, etc.).

16.1.2.3 Y and Z Counting

The length counters start with the specified operand lengths and count them down to zero for all instructions except DP, ED, EDMK, TR and TRT.

Counting the length down means that the length count maintains the count of the remaining bytes to be processed. The value in the length counter can then be used to determine if another source word should be fetched once a prefetch is started. The first cycle of prefetch transfers the prefetched word from M to L. If another word is needed, (length counter shows more than eight bytes remain), the prefetch continues and prefetches the next word. For EDM EDMK, TR and TRT there is no actual prefetch. The prefetch sequence is used to fetch source words but it is not overlapped with the iterations. For EDMK and TRT, the byte address of a byte in operand one is put in GR 1. The most convenient method of generating this address is to start Y and Z at zero, count them up as operand one bytes are processed, and add Y and Z to B 1 + D 1 when the byte address is required. The end of the operation is indicated by Y and Z equal IOP (8- 15).

In Decimal Divide, the number of quotient bytes to be generated is L 1-L 2. Therefore, L 2 is a set in Y and it is counted up until Y = IOP (8- 11).

When counting down, the counters are stepped with the set conditions for the iteration sequencers. Since the specified lengths are the number of bytes minus one, a counter value of all ones indicates the end of operation instead of a zero value (counter is stepped past zero to 15). Furthermore, the counter latch is decoded instead of the register because the decoder output is used to set and reset triggers at A time. This means that the counter value of 1110 for decimal or 1111-1110 for logical operations indicates all bytes have been processed. See FIGS. 472-474.

16.1.2.4 End Sequence and ELC

The VFL end sequence trigger FIG. 534 is set by all SS instructions. With one exception it is set two cycles before the end of the operation. The one exception is Translate and Test ending in an address put-away sequence. The set for VFL end sequence trigger is also the VFL Thru signal to the I UNIT. The E last cycle trigger is set for the last cycle of every SS instruction. This is done to take advantage of the built-in end operation control functions of the ELC trigger.

16.1.2.5 VFL Zero Detects

The VFL data flow has two zero detects, one on the output of the digit gates (RBG ZD) and the other on the result bus back to K (Result ZD).

The RBG ZD is connected to two latches. The low-order digit is latched for Edits and both digits are ANDed and latched as a Byte Not Zero latch. This is used in TRT and Overflow detection.

The result ZD sets a trigger which has a latched output. The zero detect logic has a control line to force zero in the low-order digit (sign position) for arithmetic operations. The trigger is actually set if a nonzero byte is detected and is in the off state at the end of any operation with a zero result. The Result ZD is used by Decimal Arithmetic and Logical Compare operations.

16.1.3 Sequence Hardware FIG. 409 a

The various sequencers are shown in respective groups of figures, as illustrated by FIG. 409a. In some cases, a particular sequence control (such as PF 1 TGR) may be generated in more than one place. This illustrates the well-known expedient of multiple-generation for powering purposes. In other cases, a particular combination of sequences (such as SU 2 or SF 1) may not be explicitly generated, but the figures referred to in the chart of FIG. 409a fully illustrate how any such combination can be generated.

16.2 VFL SET-UP SEQUENCES

See FIGS. 415-426 and 475-480.

16.2.1 INTRODUCTION TO SET-UP GROUPS

The SS instructions are divided into four groups by Set-Up function:

I. move-With-Offset, Pack, Unpack, Zero-and-Add, Decimal Compare, Decimal Add and Decimal Substrate.

Ii. move Numeric, Move, Move Zone, AND, Logical Compare, OR, EXCLUSIVE OR, Edit, Edit-and-Mark.

Iii. decimal Multiply, Decimal Divide.

Iv. translate, Translate-and-Test.

16.2.2 GROUP I (MVO, PACK, UNPK, ZAP, CP, AP, SP)

16.2.2.1 General Objectives

It is the general objective of Set-Up, for the Group I instructions, to:

a. Fetch the words from storage that contain the first byte to be processed for both operands.

b. Compare the starting addresses for the possibility of overlapping fields. 0 (B 2 +D 2+L 2)- (B 1 +D 1 -L 1)< 8

8 (B 2 +D 2 +L 2)- (B 1 +D 1+L 1)< 16

c. Set the starting byte address in S and T.

d. Initiate first Prefetch, if required.

e. Put fetched words in K and L.

f. Set VFL gating triggers.

g. For Pack and Unpack, put H bits 19 and 20 (the two low-order word address bits, H (21-23) being the byte address) in ER (1, 2) for operand 1 and in SC(1, 2) for operand 2.

h. For pack and Unpack, compare ER to SC for equal as part of overlapping field detection. A few of the relationships used in this Set-Up will be discussed first.

If operand No. 2 is in more than one word in storage, the fetch request for the second word is made during Set-Up. This request is called the first prefetch. The length of the operand along does not indicate how many words operand No. 2 is in. As an example, operand No. 2 could have only two bytes (L 2 = 1) but start at byte address zero and reside in two storage words. However, L 2 could be seven with a starting byte address of seven and the operand resides in one word. Therefore, a comparison between L 2 and S is made to determine if the first prefetch should be initiated. If L 2 is greater than S (operand No. 2 starting byte address), operand No. 2 resides in more than one storage word. A second prefetch is started when the first operand No. 2 word boundary is crossed. At this time, the length counter indicates how many bytes remain to be processed. If Z is greater than 7, a prefetch is initiated, otherwise no request is made.

With the exception of Pack and Unpack, all instructions that require detection or processing of overlapping fields move through both operands at the same rate. This means that the relative position of the two operands at the start of execution remains unchanged throughout the execution.

On Pack and Unpack, the starting address are checked for an absolute difference of 0 to 7. If the difference is 0 to 7, the two low-order word address bits are updated, in the exponent register and shift counter, each time a word boundary is crossed. When these two partial addresses become equal, the crossing of the boundary moves both operands into the same storage word and one register (K) must be used for both operands.

When the difference of the starting addresses is 0-7, i.e. 0 (B 2 +D 2 +L 2)- B 1 +D 1 +L 2)< 8, a comparison of the byte addresses indicates whether or not the two operands start in the same word. The starting byte addresses are in the S and T pointers. If S T, the two operands start in the same storage word. If S <T, the two operands start in adjacent storage words, the first destination word being the second source word required.

When operating in Single-Cycle mode, the first Set-Up fetch request is advanced to SU 1. This allows the word returned to J to be transferred to M during SU 2. The rest of the Set-Up is unchanged with the exception of the start of prefetch. The start of prefetch is delayed to SU 9 so that the word fetched does not return to J and destroy the first word of operand two which returned to J during SU 5. The sequence triggers and latches are denoted as SU T2 for Set-Up trigger two and SU L2 for Set-Up latch two.

16.2.2.2 SU 1

Y is gated to AA with SU L1 or SU T2 to calculate B 1+D 1+L 1. The extended gate is due to the path length from VFL controls to the AA.

16.2.2.3 SU 2

The VFL fetch request trigger is set with the B clock. The output of this trigger goes to the I unit to indicate J as the return address, and to the BCU to set their fetch request. The set of both VFL request triggers (Fetch register and Store register) is latched to generate the gate of the AA to SAR and H.

16.2.2.4 SU 3

Z is gated to the AA with (SU L3 or SU T4) to calculate B 2+D 2+L 2. The VFL address advance line is up during cycle three so that B 2 and D 2 will be in the AA during cycle four. The low-order three bits of H are gated to the T LTCH and T is released with SU L3. This puts the starting byte address of operand one in the T pointer H (0-23) is gated to the incrementer. The latched output of the incrementer and incrementer extension is gated to K (0-31). Since nothing is gated into the incrementer extension its output is zero with correct parity. The AOB (32-63) is gated to K (32-63) at the same time to put zeros with correct parity in the low order half of K.

The sequence is held up here until an Accept is received from the BCU. If an immediate Accept is received, SU 3 takes only one cycle. This prevents a second request being made in SU 5 without an Accept from the first request.

16.2.2.5 SU 4

The VFL fetch request trigger is set and the AA is gated to SAR and H. Operand one address is gated from K to L.

H (19, 20) are gated to AE (1, 2) and AEOB to ER for Pack and Unpack, If the overlap triggers are not set, these bits are not used.

16.2.2.6 SU 5

The second operand byte address is gated from H (21-23) to the S LTCH and S is released. The entire second operand address is gated from H to incrementer to K, as in cycle three.

The sequence waits in SU 5 for an Accept from the BCU.

16.2.2.7 SU 6

The VFL address advance line is up during SU 6 in preparation for the addition of B 2+D 2+DELTA in SU 7. The DELTA can be 0 or 1. If DELTA + 1, a one is forced into AA (28), the low-order word address bit. A 1 is forced to AA (28) if Z (1, 2, 4) is greater than S (1, 2,4) and Z (8) is on.

This fetch request is actually initiating the first prefetch. The following table shows the number of storage words involved for the various length and starting byte address relationships.

Number of Wds. Z (1, 2, 4) Z< (S) (1, 2, 4 ) 1 0 No 2 0 Yes 2 1 No 3 1 Yes

The starting address comparison is started in SU 6 by substrating L from K and putting the result in K. This is the desired result for all instructions except Unpack. In Unpack, if this result is negative, (no AM C Out 1), L is complemented through the adder and put in K at the end of SU 7. This checks the magnitude of the difference since operand one can start to the right of operand two and move to the left during the execution. H(19, 20) are gated to AE(1, 2) and AEOB to SC in anticipation of overlapping fields.

The GT L with S trigger is set here for all instructions. The GT L with S trigger is reset as GT K with S trigger is set.

16.2.2.8 SU 7

If Z (1, 2, 4) <S (1, 2, 4) or Z (8)= 1, the VFL fetch request trigger is set and prefetch trigger 3 is set with SU L7. PF 3 is the Accept Wait cycle of the prefetch sequence and is followed by PF 4, which transfers J to M. L is gated to AM T/C and the complement trigger is set. For Unpack, if there was a carry out of AM (1) at the end of SU 6, AOB is gated to K with SU L7. The AM CArry Out 1 trigger is blocked from changing with SU L7.

16.2.2.9 SU 8

The address comparison is completed in this cycle by setting 0-7 Overlap or 8-15 Overlap trigger if the conditions are met. The k zero detect generates two lines, K O-27 Equal Zero and K 0-28 Equal Zero. Set 0-7 Overlap if k 0-28 Equal Zero. Set 8-15 Overlap if K 0-27 Equal Zero and not K 0-28 Equal Zero.

The GT TD Out trigger is set during SU L8 for the instructions that use data from operand one.

For Pack and Unpack, the ER and SC are gated to AE during SU 8 and SU 9. The AE complement trigger is also set for two cycles. This is done to check the ER/SC for equal. The gates are up for two cycles because the AE HS Equal Zero line has a long path to set the GT K with S trigger at SU L9.

Operand one is gated from J to K when J Loaded is on and not Single-Cycle mode. For Single-Cycle, operand one was put in M during SU 2 and is gated from M to K during this cycle.

16.2.2.10 SU 9

Operand two is gated from J to L when J Loaded is on. SU L9 is enabled with the J Loaded trigger on.

The overlap triggers and AE HS are sampled for a set to GT K with S trigger at SU L9.

For Single-cycle mode, the prefetch storage request is delayed from SU 7 to SU 9. Delayed with the fetch request is the set of PF T3.

SU L9 sets the first iteration sequencer.

16.2.3 GROUP II (MVN, MVC, MVZ, NC CLC, OC, XC, EDT EDMK)

16.2.3.1 General Objectives

It is the general objective of Set-Up, for the group II instructions, to:

a. fetch the words from storage that contain the first byte to be processed for both operands.

b. compare the starting addresses for the possibility of overlapping fields.

0 (B 1 +D 1+L 1)- (B 2 +D 2 +L 2) <8

c. set of the starting byte addresses in S and T.

d. initiate the first prefetch, if required.

e. put fetched words in K and L.

f. set VFL gating triggers.

g. set up the ER and SC to be used as a word count.

h. for Edit and Edit-and-Mark, put the Fill Character in DB/DC.

There are many similarities between the Group I and II Set-Up sequences. Therefore, only the differences will be described for Group II.

All of the instructions in Group II process from low order to order storage and use Op-code bits 8-15 as an eight-bit length which applies to both operands.

A word count is maintained in the ER which is reset to zero during Set-Up The ER register is advanced by one each time a result word is stored. The increment gated to AA for address generation comes from the SC. The amount in the SC is the increment needed for the next fetch, i.e., if operand one is crossing word boundaries ahead of operand two, the SC = ER + 2 for prefetch, and if operand one is crossing word boundaries ahead of operand two, the SC = ER + 1 for prefetch. At completion of prefetch, SC = ER + 1 for the next operand one fetch.

A status trigger (T5) is set during Set-Up if S< T. T5 on indicates that operand two will cross word boundaries ahead of operand one.

The first prefetch is initiated if Z (1, 2, 4) <S NOT (1, 2, 4) or Z (8) or Y (1, 2, 4, 8) is not equal to zero. The Z and S comparison is made with complement S because the operands are processed from left to right (low-order to high-order storage).

The results of an Edit or Edit-and-Mark with overlapping fields are specified to be unpredictable. Therefore, these two instructions are always handled as through their operands do not overlap. Address comparisons are degated during Edit and Edit-and-Mark Set-Up

16.2.3.2 Set-Up Functions

SU 1

No increment is gated to AA since the desired starting address is B 1+D 1)

SU 2

The AEOB is gated to the ER as a means of resetting ER to zero with correct parity.

SU 3

No increment is gated to AA since the desired second operand starting address is B 2+D 2.

SU 4

One is forced to AE (7) and the AEOB is gated to the SC. This is preparing the first address increment required for fetching.

The Y and Z counters are reset to zero during SU 4 for Edit or Edit-and-Mark because Y and Z are counted up in these instructions.

SU 7

The AOB is always gated to K with SU L7 for this group. The add during SU 6 generated (B 2 +D 2)- (B 1 +D 1) and the desired difference to be checked is (B 1 +D 1)- (B 2 +D 2 or NOT (B 2 +D 2) -(B 1 +D 1).

SU 8

If T5 is on, indicating the first word boundary to be crossed will be in operand two, 1 is added to the SC. This puts 2 in the SC, the increment needed for the first prefetch.

SU 9

For Edit and Edit-and-Mark, the first byte of operand one is put in DB/DC, where it is held throughout the execution. This byte is the fill character. The length counters and pointers are not stepped because this character is examined as all other pattern characters are.

The GATE L with S trigger is set with SU L9 for Edit or Edit-and-Mark. This set is delayed because there is no gate for the RBG to AOE and the AOE is used during SU 9 for Edit and Edit-and-Mark.

The T2 trigger is set with SU L9 for MVC if, (T= 0) & (S= 0) & (Y and Z 7). The T2 trigger on causes Move to move 64 -bit instead of eight-bit bytes. This type of Move is called Transmit Mode. Transmit Mode is entered on any MVC when both operands start on word boundaries and there is at least one 64-bit word to be moved. The byte mode is initiated to move any partial words on the end of operand No. 2.

For this group of instructions, SU L9 sets Iteration Sequencer 2 (IS 2) with one exception. For MVC Transmit, SU L9 sets SF 3.

16.2.4 GROUP III (MP, DP)

The description of Multiply and Divide Set-Up is included in the Multiply-Divide description.

16.2.5 GROUP IV (TR, TRT)

16.2.5.1 General

The Translate instructions differ from other SS instructions in that the byte addresses move irregularly through a translation table in storage. Operand one is still processed sequentially starting with the low-order storage byte (B 1+D 1). For this reason, source bytes are fetched one at a time from storage. Each operand two address that is formed is compared to the word address of the operand one word currently in the K register. If the table byte is in K, the GT K with S trigger is set and K is used for the source byte.

When the operand one address is formed, it is transferred to K. From K, bits (24-28) are gated to AOE and the AOE is gated back to K (24-31), thus setting K (29-31) to zero. K is transferred to M and subtracted from each operand two address. If any difference is within 0 to 7, the 0-7 Overlap trigger is set and this causes the GT K with S trigger to be set. When operand one word boundaries are crossed, the Y and Z latch is added to B 1+D 1 to generate the fetch address. Using this method of generation gives an address with the low-order three bits zero.

16.2.5.2 Set-Up Functions

SU 1

The VFL fetch request trigger is set with SU T1 for Single-Cycle operation. This early set is not required for Translate but is used for simplicity since all other SS instructions advance the request for Single Cycle.

SU 2

Set VFL fetch request trigger and gate AA to SAR and H.

SU 3

Gate H(2-23) to the T pointer and H(0-23) to K.

SU 4

The low-order three bits of the address in K are set to zero by gating K(24-28) to AOE and AOE(0-7) back to K(24-31).

The Y and Z counters are reset to zero. For the Translate instructions, Y and Z start at zero and are counted up until equal to TOP(8-15).

SU 5

The adjusted address in K is transferred to M. From there, it will be compared to each operand two address for possible overlap.

SU 8

The first word to be translated is transferred from J to K. The GATE TD OUT trigger is set with SU L8. This allows the byte from K, specified by T to pass through the LBG.

SU 9

The first iteration sequencer, PF T1, is set by SU L9.

16.2.6 INTERRUPTS

The only interrupt that can be initiated during Set-Up is Address Invalid. The Address Invalid trigger is normally set to the value of the Address Invalid line with each J Advance, For SS instructions, the trigger can be set but not reset with J advance. With this arrangement, Invalid Address indications are accumulated and then the trigger is sampled at the end of Set-Up. The Address Invalid trigger is reset with SU 1.

The Address Invalid trigger is sampled at SU 7 and SU 9. If it is on, the sequence is switched to SEQ T4 and the Store/Fetch trigger is set. These two together make SF 3 which is the start of the End Sequence.

16.3 ITERATIONS (AND DIRECT CONTROL)

16.3.1 DECIMAL ITERATIONS

This section describes the iterations for all SS decimal instructions except Multiply and Divide. Multiply and Divide and described in the next section. All iterations start with the following initial conditions:

1. Word B 1 + D 1 + L 1 in K

2. word B 2 + D 2 + L 2 in L

3. iop (8-11) in Y

4. iop (12-15) in Z

5. starting byte address for operand No. 1 in T

6. starting byte address for operand No. 2 in S

7. either GT L with S or GT K with S on, depending on the state of the 0-7 Overlap trigger

8. GT TD OUT trigger on for MVO, CP, AP, SP

The first iteration sequencer is set with the SU 9 latch. The iteration cycles continue until a word boundary is encountered or the execution is complete.

16.3.1.1 Move WITH OFFSET (MVO) Move With Offset is a combination move and shift left one digit as the name implies. The DB/DC is used as a buffer to hold the HOD of each byte until the next cycle when it is gated into the DA as the LOD. The L 1 length determines the end of the operation. If the source is exhausted before the destination, the GT K/L with S triggers are reset and parity is forced to the RBG. All other gates are unchanged. This fills out the remainder of the destination with high-order zeros.

16.3.1.2 PACK (PACK)

The DB/DC is used as an intermediate result buffer. See FIGS. 482 and 496-498. DB/DC must be used because K is used as temporary storage and the result byte cannot be put in storage until it is complete.

One destination byte is put in K at the end of IS 1 and every IS 3. This means that the Store/Fetch sequence is entered from IS 1 or IS 3 and always returns to IS 2. A source byte is used for each cycle, IS 1, IS 2 and IS 3. The prefetch sequence can be entered from any of the three sequencers. Therefore, the VFG T2 trigger is set with (S PTR = 0) & (IS 2 LTCH) to remember which sequencer should be turned on after the prefetch.

The destination length determines the end of the operation. If the source is exhausted before the destination, the GT K/S with S triggers are reset and parity is forced to the RBG. This fills the remaining destination bytes with high-order zeros.

16.3.1.3 Unpack (UNPK)

The first cycle is the same for Pack and Unpack. For Unpack, one source byte generates two destination bytes. The source bytes must be "fetched" from K or L only once because the first destination byte generated for a given source byte may be stored on top of the generating source byte. As an example, assume the two operands were located in the same storage word. The source byte 3 could be generating unpacked destination bytes 3 and 4. For this reason, the source bytes are put in DB/DC during IS 2 and DB/DC is used as the source during IS 3. Here, as in Pack, DB/DC is only needed for overlapping fields. Since it gives the correct result for nonoverlapping fields also, only one method of execution is used.

The Prefetch sequence is entered from IS 1 or IS 3. The Store/Fetch sequence can be entered from IS 2 or IS 3. Therefore, the VFL T2 trigger is set with (T PTR = 0) & is 2 LTCH) to remember which sequence should be set after the Store/Fetch is completed. PSW bit 12 determines which zone code is used for the unpacked result. PSW bit 12 equal to zero gives the BCD zone of 1111 PSW 12 equal to one gives the ASCII zone of 0101. The BCD zone is forced at the digit gates and PSW bit 12 controls the gating of DA bits 0 and 2 back to K. Removing bits 0 and 2 from the BCD zone gives the ASC zone but does not change the parity.

16.3.1.6 Zero and Add (ZAP)

The first source word is set into L with the SU 9 latch and, therefore, IS 3 is used to examine the source sign. The polarity of the sign must be known so that the machine preferred sign can be forced.

When the ZAP source is exhausted and the destination is filled out with high-order zeros, the destination may be exhausted first and the remaining bytes of the source zero-detected for overflow. VFL T 6 trigger is set if an overflow conditions occurs. VFL T 1 and T2 triggers are set when Z and Y are counted down to 1110. These are used to generate gates for exhausted source and destination conditions.

The Conditions Register is set during the last Store/Fetch sequence with the SF 4 latch.

16.3.1.5 DECIMAL COMPARE (CP)

In Decimal Compare, if the two operands have like signs, operand two is subtracted from operand one to determine which is the larger. If the two operands have unlike signs, operand two is added to operand one and the sum is zero detected. If the sum is nonzero, the positive operand is the larger. If the sum is zero, the two operands are both zero and, therefore, equal. The execution is not complete until all bytes in both operands have been examined. Gates are provided for validity checking both operands. The VFL T3 trigger is used as a true/complement trigger for CP, AP and SP. Therefore, VFL T3 controls the true/complement and parity adjust gates. VFL T3 is off for true add and on for complement add. When doing a true add, the right side parity must be adjusted for the excess six gating into DA. When doing a complement add, the right side parity is adjusted for the sign removal only.

The Condition Register is set during the last Store/Fetch sequence with the SF 4 latch.

16.3.1.6 Decimal Add and Decimal Substract (AP and SP)

The only difference between AP and SP is the setting of the True/Complement trigger, VFL T3.

The first cycle (IS 3) is for examining the signs and setting the sign trigger. Since the pointers are not stepped during IS 1, the sign decoding does not need to be latched to set VFL as IT 1 with A time.

When doing a true add, the right side parity adjust must correct for the excess six gating into DA. The GT HOD DEC TRUE TO PAR ADJ line gates HOD Equal 4/5 to an EXLUSIVE OR with INVERT SIGN. The two phases of the EXCLUSIVE OR gate the left parity or its complement, alternatively, as the adjusted parity. This adjusts for the three possible changes to the sign byte: 1 the incoming sign is degated and the machine-preferred plus sign (for BCD or ASCII, alternatively) is forced at the Digit gates; 2 if the high-order digit is gated Decimal True, a 4 or 5 changes the parity; 3 if the LBG sign is negative, the low-order bit of the forced sign is inverted to make the result sign minus. The RBG HOD equal 4 or 5 is derived from RBG 1 and not RBG 2.

The operation is not complete until every byte in both operands has been examined. When operand one is exhausted, VFL T2 is set, the GT TD OUT trigger is reset and parity is forced to the left side of the DA input. When operand two is exhausted, VFL T1 is set, GT K/L with S triggers are reset and parity is forced to the RBG. When both operands are exhausted, SF 1 is set instead of IS 2. During this Store/Fetch sequence, the last result word is stored and one of the following happens:

1. the operation is terminated if the result is correct as stored.

2. the sign of the result is set plus for a negative zero result and the operation is terminated.

3. the first word of operand one is fetched to start recomplementation if the result is in complement form.

The S and T pointers contain the same byte address: the S pointer controls gating of K bytes to the true/complement input of DA; the T pointer controls putting the bytes back in K.

For a true add, the DA CARRY TGR is not released after the destination is exhausted. A carry from the high-order byte of the destination is held in the carry trigger until both operands are exhausted, at which time VFL T6 is set. (VFL T6 is set with DA CARRY TGR and TRUE ADD, T1, T2 and SF 1 latch). For both true and complement adds, the RBG is zero detected after the destination is exhausted. If a nonzero digit is detected, VFL T6 is set. The decimal overflow interrupt is set with: (AP or SP or ZAP) and VFL T6) and (PSW Bit 37) and (VFL END SEQ TGR).

The condition register is set during the last store/fetch sequence with SF 4 latch.

16.3.2 LOGICAL MOVE, CONNECTIVE AND COMPARE ITERATIONS

This section describes all logical SS instructions except the Edits and Translates. One iteration sequencer, IS 2, is used for all these instructions with the exception of Move Transmit Mode. Move Transmit Mode uses the Store/Fetch and Prefetch sequences only. The iterations start with the following initial conditions:

1. Word B 1 + D 1 in K

2. word B 2 + D 2 in L

3. iop (8-15) in Y and Z

4. starting byte address for operand No. 1 in T

5. starting byte address for operand No. 2 in S

6. either GT L WITH S or GT K WITH S on, depending on the state of the 0-7 OVLP TGR

7. the GT TD OUT trigger is on for all instructions except MVC

The first iteration sequencer is set with the SU 9 latch. The iterations continue until a word boundary is encountered or the execution is complete. The CR is set for CLC, NC, DC, XC, TRT and EDMK during the last Store/Fetch sequence with SF 4 latch.

16.3.2.1 Move (MVC)

Move does just what is says: it moves data from one location to another. Normally, its execution is one byte at a time. However, if the two operands are (1) not overlapped, (2) start on word boundaries, and (3) are more than one word in length, the move will be done one (64) -bit word at a time. This is called Move Transmit MOde. If the operands do not end on word boundaries, the Transmit Mode reverts back to the normal byte mode.

The first destination word is fetched during Set-Up because it may be needed for execution of overlapping fields. After Set-Up, the destination is stored but not fetched. When the two operands start within eight bytes of each other, but in different words, the source bytes in the second word that do not actually overlap the destination must be fetched. This is done by fetching the first destination word. Once the source actually moves into the overlap area, no more storage words are required because the source is being generated in K.

Bytes are moved (in a byte type move) from L to K, or from K to K, depending on overlap conditions. Both HOD and LOD are gated Binary on the DA right side and parity is forced to DA left. The DA output is put in K. If both operands (1) start on 64-bit word boundaries, (2) at least two words apart in storage, and (3) there are more than eight bytes to be moved, the Move Transmit Mode is entered. Move Transmit Mode moves 64 -bit words. In the Transmit Mode, the first source word fetched is transferred to the K REG and stored just as soon as an accept is received from the second source fetch. When each store is completed, another Prefetch is started. The first cycle gates the prefetched word from the M REG to AM T/C. The AOB is gated to the L REG as usual, and is also gated to the K REG. This is the next word to be stored. If another source word is to be fetched, the Prefetch sequence continues after PF 1. If the word in the K REG is the last full word to be moved, the Store/Fetch sequence follows PF 1. If a partial word remains, the move reverts back to the byte mode and the IS 2 sequence follows PF 1. The VFL T2 trigger is turned on with SU 9 latch if the conditions are met for Transmit Mode.

The Y/Z length counters are decremented by eight with each setting of the SF 3 latch when the transmit Mode. If an even number of words are to be moved, the low-order three bits of the length would be ones (Z= X 111). Therefore, the Y/Z counters will be equal to 1111- 1111 when one word remains to be stored. This value in Y/Z causes SF 3 to follow PF 1 and the last full word is stored. If there are two odd bytes in addition to the full words to be moved, the three low-order bits of the length will be 001. With this value in Y/Z, IS 2 follows PF 1. The partial word is moved one byte at a time in order to set the mark register correctly. The sequence is switched from IS 2 to SF 3 when the Y/Z latch equals 1111-1110. This is the end of operation condition for the byte move.

16.3.2.3 Move Numerics and Move Zones (MVN and MVZ)

These two moves take a part of each source byte and put it in a destination byte, leaving the remainder of the destination byte unchanged. For MVN, the LOD is gated to DA right and the HOD is gated to DA left. For MVZ, the HOD is gated to DA right and the HOD is gated to DA left. For MVZ, the HOD is gated to DA right and LOD is gated to DA left. Both operands are fetched from the L or K registers, depending on the overlap conditions.

16.3.2.3 AND, OR and EXCLUSIVE OR (NC, OC and XC)

The SS logical connectives use the AOE. The output of the AOE is normally or OR of the two inputs. If either the AND or the EXCLUSIVE-OR function is desired, a gating line must be activated.

Parity is generated for the output of the AOE; the incoming parities are checked by gating the two bytes into the DA and checking the half-sums.

16.3.2.4 Logical Compare (CLC)

The SS logical compare moves from left to right through the operands, making a byte by byte comparison. The operation continues until (1) an unequal comparison is found (DA sum nonzero) or (2) the operands are exhausted.

16.3.3 TRANSLATE AND TRANSLATE-AND-TEST (TR AND TRT)

The initial conditions for TR and TRT are as follows:

1. Word B 1 + D 1 in to K REG

2. address B 1 + D 1 in the M REG (with the low-order three bits zeroed)

3. Y and Z reset to zero

4. Starting byte address for operand No. 1 in the T LCH

5. gt td out trigger on

TR and TRT are very much the same; their differences are:

1. TR does not examine the translated bytes before storing them; TRT translates destination bytes for examination and does not store any bytes.

2. TR is complete when all destination bytes have been translated; TRT is complete when a nonzero byte is found or all bytes have been translated.

For Translate, the word address of the word in the K REG (destination word) is compared with each table address. If the difference is 0-7, the word being fetched is actually in the K REG. In this case, the table byte is taken from K instead of from the word returning from storage. Each time another destination word is fetched, the low-order three bits of the address are set to zero and the address is put in the M REG. Each table address is transferred from the H REG to the K REG and the value in M is subtracted from the value in K. The difference is put in the K REG and is sensed for a value of 0-7. If K does not equal 0-7, GT L WITH S is set; if K does equal 0-7, GT K WITH S is set. While the address comparison is being made, the current destination word is held in the J REG.

Overlapping the table word return with the address calculation for the next fetch requires two destination byte addresses. One is the byte address where the translated byte is to be stored (temporarily in K). The other byte address is that of the next byte to be translated. A hold is used on the T pointer latch to prevent it from changing after the T pointer has been advanced. This holds the store byte address in the T latch which selects the byte to be stored in the K REG. The T register is advanced to control the gating out of the K REG. This gates the next destination byte through the LBG to the AA for the address calculation.

VFL T8 trigger is used to prevent Y/Z from being stepped until after the first byte is translated. Y/Z is stepped until it equals IOP (8-15). Therefore Y/Z is stepped for each byte processed after the first byte. This corresponds to the definition of the operand length, i.e. the number of bytes to the right of the first byte.

After the Set-Up and Store/Fetch sequences, the VFL T1 trigger is off, and is then set with the PF 1 latch. The VFL T1 trigger gates operations on data returned from storage, but in the first sequence after Set-Up or Store/Fetch, there are no words returning.

For TRT, if a nonzero function byte is found, the mark sequence is started. The mark sequence starts with VFL SEQ A. For TRT, the mark sequence ends the operation. The current byte count in Y/Z is added to B 1 + D 1 to arrive at the byte address of the destination byte, which translated to a nonzero byte. This address is put in the low-order 24 bits of GR1. This is accomplished by first putting the address in the K REG and then gating the high-order eight bits of GR1 to the K REG. K (0-31) are then put in GR 1. Then the contents of GR 2 is put in K and the nonzero table byte is inserted in K (24- 31) is then put in GR 2.

Because a General Register is being set during the last cycle, the VFL THRU signal is delayed until the IS 1 latch comes on, just one cycle before the end. VFL THRU sets the VFL EDN sequence trigger.

16.3.4 EDIT AND EDIT-AND-MARK (EDT AND EDMK)

The initial conditions for the Edits are:

1. Word B 1 + D 1 in the K REG

2. word B 2 + D 2 in the L REG

3. y and Z reset to zero

4. Starting byte address for operand No. 1 in T

5. starting byte address for operand No. 2 in S

6. gt l with s trigger on

7. GT TD OUT trigger on

8. SC set to one

9. The first byte of operand No. 1 in DB/DC.

This is the fill character. The two sequences used for Edit iterations are IS 2 and IS 3. The ID 2 sequencer conditions the gates to unpack and validity check the HOD and sign detect the LOD of the source byte. The IS 3 sequencer conditions the gate to unpack the LOD of a source byte. One pattern byte is examined every cycle. Once a sequencer is turned on, it stays on until the conditions are met to unpack a digit. (These conditions being met are referred to as Examine Digit.)

Sequencer IS 2 is set with SU 9 latch. When the HOD is unpacked, IS 2 goes off and IS 3 is turned on. When the LOD is unpacked, IS 3 goes off and IS 2 is turned on. The S pointer is stepped when going from IS 3 to IS 2. The iteration sequencers are on for an unpredictable number of cycles. The pattern bytes and S trigger (VFL T5) determine when a digit is unpacked. When IS 2 is on and the conditions are met to unpack a digit, if the LOD is a sign (1010-1111) the S pointer is stepped and IS 2 remains on. Stepping S and not turning IS 3 on skips over the sign so it is not unpacked into the result. When a positive sign is detected, (1010, 1100 or 1111) the S trigger is reset.

On each cycle that a source digit is not examined, either the fill character is gated from DB/DC to K or K is left unchanged.

The zone that is forced in unpacking digits will be either 1111 for BCD, mode or 0101 for ASCII made depending on the PSW bit 12: if zero, it INDICATES bcd MODE AND IF 1 IT INDICATE ascii MODE. The BCD zone is forced at the RDG, on the DA right side input. If the PSW bit is on, bits 0 and 2 of the AV output latch are degated and do not go to the K REG. This changes the BCD zone to an ASCII zone but does not change the parity since an even number of bits are removed. The VFL status triggers are used for Edits, as set forth in the following paragraphs. Also see FIGS. 453-462. VFL T1 remembers that the S pointer should be stepped when returning to the iterations from a Store/Fetch or mark sequence. VFL 1 is set by:

Is 3 ltch, or

Is 2 ltch and EXAMINE DIGIT LTCH and EDIT SIGN LTCH

It is reset by

Is 2 LTCH (Set blocks reset)

VFL T2 remembers which sequencer should be turned on when returning to the iterations from a Store/Fetch or mark sequence. ON indicates IS 3, and O

VFL T2 is set by:

Is 2 ltch and EXAMINE DIGIT LTCH

VFL T2 is set by:

Is 2 ltch and EXAMINE DIGIT LTCH AND NOT EDIT SIGN LTCH, or

Is 3 ltch and NOT EXAMINE DIGIT

It is reset by: IS 2 LTCH or IS 3 LTCH (Set blocks reset)

VFL T1 and VFl T2 combinations and sequences are as follows:

VFL T3 remembers the zero field condition for a source number. It is used to set the Condition Code.

VFL T3 is set by:

Su 9 ltch or

Edit field sep ltch

it is reset by:

Examine digit ltch and NOT ZERO DIGIT LTCH

VFL T4 remembers that a prefetch is required after a Store/Fetch. The S pointer being equal to seven is not sufficient information to start a prefetch. Examine Digit and Edit Sign LTCH indicate whether the last digit has been used. At the end of a Store/Fetch this information is gone.

VFL T4 is set by:

Is 3 ltch and S PTR = 7 and EXAMINE DIGIT or EDIT SIGN LTCH

It is reset by:

Pf 1 ltch

vfl t5 is used as the S TGR control.

VFL T5 is set by:

Digit select ltch and NOT EDIT ZERO DIGIT LTCH or SIGN START LTCH.

VFL T7 holds the address invalid indication for the source field until a digit is used from the invalid word. VFL T7 and the Examine digit set the interrupt triggers.

VFL T7 is set by:

Address invalid ltch and PF 4 LTCH

It is reset by:

Elc ltch

the following latches are used for Edits to hold the control condition over A time:

Edit digit sel ltch: turned on by LBG EQUAL DIGIT SELECT

Edit sig start ltch: turned on by LBG EQUAL SIG START

Edit field sep ltch: turned on by LBG EQUAL FIELD SEP

Examine digit ltch: turned on by LBG equal to a DIGIT SELECT or SIGNIFICANCE START character.

OTHER CHARACTER LTCH: title which refers to the off output. Turned on by LBG equal to Digit Select or Significance Start or Field Separator character.

EDIT SIGN or RBG NOT ZERO LTCH: turned on by (RBG LOD SIGN and EXAMINI DIGIT and IS 2 TGR and ED + EDMK) or (AP + SP + ZAP + TRT and RBG NOT ZERO and SF 5 is the last cycle. The SF 5 sequencer is the last cycle for all instructions with one exception, TRT. For

Edit positive sign ltch: turned on by ED + EDMK and IS 2 TGR and RBG SIGN PLUS.

The HOD of each source byte is validity checked when it is examined. If it is invalid, the Data Check interrupt triggers are set if T7 is off. T7 on indicates that the word came from an invalid address and the Invalid Address interrupt is given priority.

The byte address is calculated by adding B 1 + D 1 + (Y-Z). The current pattern word is transferred to J while the address is inserted in GR1 and brought back to K during SEQ D. The address is put in K (8-31) and then the high-order eight bits of GR1, which is brought out to the M register, are gated into K (0-7). K (0-31) is then put-away in GR1. IS 1 returns the execution to:

1. IS 2 if NOT T2 and NOT SET (SF 1 or SF 3)

2. is 3 if T2 and NOT SET (SF 1 or SF 3)

3. sf 1 if Y & Z IOP (8-15) and T PTR = 7

4. sf 3 if Y & Z = IOP (8-15)

The Pattern field (Operand No. 1) is:

b SS DS b DS DS DS b DS DS DS b b b FS DS DS DS DS b SS A T

Fs ds ds . ds ds ds fs b DS DS , DS SS DS . DS DS

The source field is:

00 12 34 56 00 02 5 + 00 00 03 4 + 00 00 08 5 +

The result is:

bb0b123b456bbbbbbb25bbATbbbb. 034bbbbbbb0. 85

0 123 456 25 AT . 034 0. 85

where the second line shows how the result would be on a printer when the "b's" are replaced by blanks.

16.3.5 DIRECT CONTROL

The Store/Fetch sequencers are used for the WRD & RRD instructions. The Store/Fetch trigger is set with the E GO condition which also sets VFL SEQ T2. The sequence is SF 1-5 FOR BOTH INSTRUCTIONS.

The timing for the pulsed signals is generated by ORing together three sequencers and their latches. The three sequencers used are A, B and C. To preserve the correct timing when in single-cycle mode, the B and C sequencers are set with the A running clock. This means once the A sequencer is set, the other two follow with the normal timing relationship.

The Y & Z counters are set during the last cycle of every instruction, regardless of format, and during every cycle between ELC and the first cycle of the next instruction. Therefore, at the beginning of either RDD or WRD, Y & Z contain IOP (8-15). Y & Z are gated to the direct data register with the timing signal described above. This timing signal also generates Read Out and Write Out.

16.3.5.1 (write Direct (WRD)

Write Direct fetches a word from storage, puts it in K and gates the addressed byte to the direct control register. The direct control register is set with a running A clock and its release is gated with VFL SEQ LTCH. This maintains the correct relationship between the register setting and the rise of the Signal Out.

Read Direct gates Direct In data lines to the AOE. The AOE generates parity and the AOE output is put in the addressed-byte of K. The parity check on K is blocked until the byte read in has been through the AOE a second time to generate parity. This prevents a data change at the input to the AOE, just before the latch is locked, from causing a machine check (K register parity error). If the data changed just before the latch locked, the parity generator might not have time to adjust before the fall of the A clock that sets K. As the byte goes from K, to the AOE, to K, the VFL store request trigger is set.

The Hold In line being down when SF 1 latch or SF 2 trigger are one, allows VFL T2 to be set. The VFL T2 latch sets SF 3 and resets SF 2. VFL T2 is used as a buffer to prevent timing malfunctions on the Hold In line from causing sequencing faults. VFL T2 LTCH blocks the release of K so that the byte which is set in K when VFL T2 is set, is the byte stored.

16.4 STORE/FETCH (SF)

16.4.1 INTRODUCTION

The Store/Fetch sequence (FIGS. 438-441) handles operand No. 1 storage words. The primary function of the sequence is to store a completed result word and fetch the next word to be processed. There are variations of the sequence that store only, fetch only, make two stores, or make no store or fetch. A store only sequence starts with SF 3. A fetch store sequence and a fetch only sequence start with SF 1.

In all of these sequences, if the end execution conditions exist, VFL End Sequence is set with SF 3 latch and SF 5 is the last cycle. The SF 5 sequencer is the last cycle for all instructions with one exception, TRT. For TRT, if a nonzero function byte is found, the execution is completed with a put-away sequence of A-B-C-D-IS1-IS3.

16.4.2 STORE/FETCH FOR AP, SP

There are two conditions that cause a Store/Fetch to be initiated:

1. T = 0, a word boundary is being crossed.

2. Y = 1110 and Z =1110, both operands have been processed.

Both of these conditions start the Store/Fetch sequence at SF 1. The sequence has three different functions.

16.4.2.1 Crossing a Word Boundary or Last Store

This sequence is used for add/subtract first pass, and the recomplement pass. When crossing a work boundary, a result word is stored and the next destination word is fetched. When Y and Z equal 1110, the result has the correct sign and is in true form, the last result word is stored. Following is a description of the function of each cycle in this sequence:

SF 1

Eight is gated to AA if two destination words remain to be processed (Y < 7). The VFL fetch request trigger is set if another destination word is required (Y 1110). This fetches (B 1+D 1+8) if two words remain and (B 1+D 1+0) if one word remains. If both operands have been processed (Y and Z = 1110) and the last word of the destination has not been stored (T5 on), the VFL store request trigger is set. This stores word (B 1+D 1+0). The Overlap triggers are reset with SF 2 latch, when Y and Z = 1110--1110, in preparation for recomplementing.

SF 2

Sixteen is gated to AA if two destination words remain to be processed (Y < 7). Two words remaining means that the word which was just completed was the third word. Eight is gated to AA if one destination word remains to be processed (Y < 7). The sequence waits in SF 2 for an Accept to come back from the BCU if a request was set during SF 1.

SF 3

T1 is set when Z = 1110 and T2 is set when Y = 1110. If L 2 L 1, the last store will be made during SF 1 of the Store/Fetch sequence when Y and Z = 1110. If T1 and T2 are both on, the store request is blocked at SF 3. This occurs when Y counts down to 1110 and a destination word boundary is crossed before Z counts down to 1110. In this case, T5 blocks any further store request. If L 2=L 1, and Z does count down to 1110 before a destination word boundary is crossed, the last store request is made at SF 1.

The VFL end sequence trigger is set with SF 3 latch if T1 and T2 are on, and the result is in true form or if the E Interrupt trigger is on.

SF 4

The sequence waits in SF 4 for an Accept from BCU if a request trigger was set during SF 3. If Y = 1110, SF 4 latch sets T5 to remember the last store has been made.

If the 0-7 Overlap trigger is on, the GT L with S trigger is set. The 0-7 Overlap trigger on indicates that the source and destination were operating out of the same storage word. The destination crossing a word boundary moves that operand out of the storage word that the source is currently in. During SF 5, the word in K will be put in L where it will continue to be used as a source word. The condition register is set with SF 2 if the VFL end sequence trigger is on.

SF 5

The state of the two overlap triggers indicates the difference between the starting addresses. If the 0-7 Overlap trigger is on, the two operands will move in and out of common storage words. Each time a source word boundary is crossed, the source is moving into the same storage word out of which the destination is currently operating. Each time a destination word boundary is crossed, it is moving out of the word from which the source is currently operating. If the 8-15 Overlap trigger is on, the next word required by the source is being generated as a destination in K. Instead of prefetching, K is transferred to M as it is being stored.

If VFL end sequence is on, the ELC is set with the SF 4 latch, and this is the last cycle.

SF 6

J is gated to K during SF 6. For one case, when the last destination word is being stored and the processing of the source is not complete, no word has been fetched to J. However, J should be valid and it is gated to K.

If the Address Invalid trigger is on, the SF 6 latch sets SF 3 instead of IS 2 and the operation is ended.

16.4.2.2 Change Sign

For the instructions AP and SP, a positive sign is required if the result is zero. If the result is zero, it is in true form and does not require complementing. Therefore, there is never a need to change the result sign and prepare to recomplement during the same sequence.

The Result ZD trigger off when Y and Z = 1110 indicates a zero result. The byte address of the sign byte is calculated. A byte with positive sign and zero digit is generated in the AV and placed in K at the address calculated, setting the Mark corresponding to that byte. This byte is stored and the operation ends with SF 5.

The following is a description by cycle of the Change or Invert sign sequence:

SF 1

With Y and Z = 1110, there is no increment gated to AA. If a store is stored, it is the (B 1+D 1+0) word. If T5 is off, the VFL store request trigger is set.

In preparation for generating the starting byte address (B 1+D 1+L 1), IOP (8-11) is gated to Y.

SF 2

The sequence waits here for an Accept from the BCU if a request trigger was set during SF 1.

The gate of Y to AA (28-31) is started in SF 2 and continues through SF 3.

SF 3

This is the cycle at which the second request is normally set: however, the BCU Mark register must be set at the same time or before the BCU store request is set. To set the Mark register, the address must be calculated, put in H, transferred to the T LTCH and then to the Mark register. For this reason, the request is delayed one cycle. To maintain the normal ending sequence, the VFL SEQ A is inserted between SF 3 and SF 4.

SEQ A

The sign byte address is gated from H to the T LTCH which controls the K byte release and the setting of the Mark register. The positive zero byte is generated and put in K. The VFL store request trigger is set but the normal function of gating AA to SAR and H is blocked. The address was set in SAR and H during the previous cycle.

The SEQ A latch sets VFL end sequence trigger and generates a VFL thru to the I unit. See FIGS. 465 and 466.

SF 4

The sequence remains in SF 4 until the Accept signal returns. The condition register is set with SF 4.

16.4.2.3 Start Recomplement Pass

Decimal data must always be in true form at the start and end of an operation. Therefore, if the result of an AP or SP is in complement form after the first pass, another pass must be made through operand one to recomplement it. Preparation for the recomplement pass is made during what would otherwise be the last store sequence.

A description by cycle of this sequence is as follows:

SF 1, SF 2

These sequences are the same as they are for the Change sign, hereinbefore. The overlap triggers are reset with the SF 1 latch so that none of the overlap functions will be executed during the recomplementing pass.

SF 3

The VFL fetch request trigger is set to fetch (B 1 + D 1 + L 1). This could be the word that was stored during SF 1 of this sequence, but to keep the controls as simple and straightforward as possible, the fetch request is always made.

SF 4

The sequence remains in SF 4 until an Accept for the fetch request is made in SF 3. The starting byte address is gated from H to T LTCH to T. To get the T LTCH into T register unchanged, the Count S and T Down line must be degated with the SF 4 latch.

T4 is set to remember that the following sequences are for recomplementing.

SF 5

The GT K with S trigger is set to gate the K bytes through the RBG to the T/C + 6 gate.

T2 is reset since Y contains L, and is no longer equal to 1110.

The I 3 trigger is set with the SF 5 latch to start the add/subtract sequence in the normal way.

SF 6

The SF 6 latch is enabled with the J Loaded trigger. This means that the sequence will wait here for the word requested at SF 4 to return. IS 3 latch is also enabled with the J loaded trigger for AP or SP and T4.

16.4.3 STORE/FETCH FOR ZAP, CP, MVO

This group of instructions have Store/Fetch functions similar to those of AP AND SP but without all the variations.

16.4.3.1 ZAP

The Zero and Add Store/Fetch sequence only stores. Therefore, if Y and Z 1110--1110 and T = 0, SF 3 is set and the sequence runs SF 3 through SF 6. If Y and Z = 1110--1110, SF 1 is set and the sequence runs SF 1 through SF 5. This last sequence stores a positive sign if the result was a negative zero.

16.4.3.2 CP

The Decimal Compare instruction does not store a result and therefore, the Store/Fetch is a fetch only sequence. The sequence starts at SF 1 and runs to SF 5 or SF 6, depending on whether the operation is complete or not.

The following is a description, by cycle, of the CP Store/Fetch.

SF 1

Eight is gated to AA is Y<7. The VFL fetch request trigger is set if Y 1110. The reset of the Overlap triggers is for AP and SP in preparation for recomplementing.

SF 2

The sequence remains in SF 2b until the Accept signal is received for the fetch request, if it was made.

SF 3

The VFL end sequence trigger is set if Y and Z = 1110--1110.

SF 4

T5 is set if Y = 1110. This blocks Store/Fetch from starting again until Y and Z = 1110--1110.

SF 5

K is gated to L for 0-7 overlap and K is gated to M for 8-15 overlap.

SF 6

J is gated to K when J is loaded.

16.4.3.3 MVO

Move-With-Offset, being a move type instruction, does not fetch the destination. The Store/Fetch routine is started at SF 3 for storing only, and runs to SF 5 or SF 6. The SF 6 sequencer is used to separate SF 5, the last cycle sequencer, and the iterations. The SF 6 is normally used to gate J to K but no fetch is made for MVO.

T5 need not be set, since the VFL end sequence is set when Y = 1110.

16.4.4 STORE/FETCH FOR PACK, UNPK

The PACK and UNPK instructions do not move through both operands at the same rate. This means the starting address relationships do not remain static throughout the execution. Therefore, overlapping fields must be handled differently from other instructions.

16.4.4.1 Nonoverlapping Fields

If it is determined during Set-Up that the starting addresses are not close enough together to have overlapping fields, PACK and UNPK are treated like MVO. The Store/Fetch sequence is entered at SF 3, and the completed result word is stored. The VFL end sequence trigger is set when Y = 1110.

16.4.4.2 Overlapping Fields

The overlap triggers are set during Set-Up as follows:

0-7 if 0 (B 2 + D 2 + L 2)-(B 1 + D 1 + L 1) <8 for PACK

-8<(b 2 + d 2 + l 2)-(b 1 + d 1 + l 1)<8 for UNPK

8-15 if 8 (B 2 + D 2 + L 2)-(B 1 + D 1 + L 1)<16 for PACK and UNPK

With these initial conditions and the field length limitations, it is possible to monitor the two low-order word address bits (H19 and H20) to determine when the operands are in the same storage word. These two bits are put in the ER and SC positions 1 and 2 during Set-Up. Each time a word boundary is crossed, the corresponding address (ER for operand No. 1 and SC for operand No. 2) is decreased by one and then the two registers are compared. If the two registers are equal, the operands are going to be working on the same storage word.

Other details are similar to the AP, SP Store/Fetch sequence.

16.4.5 STORE/FETCH FOR MVN, MVC, MVZ, NC, CLC, OC, XC

The main difference between the Logical and Decimal SS instructions Store/Fetch sequences is the address generation. A word count is maintained in the ER of the words processed. This word count can be used to generate the increments added to the base address for storing and fetching. This word count is advanced each time a result word is stored. The fetch preceding the store uses ER + 1 for the address increment. If the source field is crossing word boundaries ahead of the destination, the prefetch address increment will be ER + 1. Since both operands move through storage at the same rate, a comparison of their starting byte addresses indicates which operand is leading throughout the entire execution. T5 is set during Set-Up of S < T, indicating operand two will cross word boundaries ahead of operand one. At the end of either a Store/Fetch, or a Prefetch, the SC will contain the increment for the next fetch.

MVC does not fetch the destination. Therefore, the Store/Fetch sequence is started at SF 3 and the prefetch must leave the contents of the ER in the SC for the next address increment.

The following is a description of the unique operation of this Store/Fetch sequence:

SF 1

The ER is transferred to SC in preparation for storing result.

SF 3

One is added to the ER for word count advance.

SF 5

One is added to the ER and the sum is put in the SC. This is a prefetch address increment if the destination is leading the source.

SF 6

If T5 is on, one is added to the SC (ER + 2) and the sum is put in the SC. This is a prefetch address increment if the source is leading the destination. This add is also gated with Not Overlap. If either one of the overlap triggers is on, the prefetch is not overlapped with the iterations. When a source word boundary is crossed, the iterations are suspended while the next source word is fetched. For this case, the address increment is ER + 1.

16.4.6 STORE/FETCH FOR ED, EDMK, TR, TRT

It is necessary, for EDMK and TRT, to calculate and put away in GR 1 the full 24-bit operand one address. The easiest way of calculating this address is to count Y and Z up (starting with Y and Z = 0), instead of down, and add Y and Z to B 1 + D 1, when the current byte address is needed. Y and Z register and Y and Z latch can then be used for addressing increments when storing and fetching operand one words at word boundaries.

The two operands move through their storage fields at different rates for ED and EDMK. The stepping of Y and Z corresponds to the processing of operand one bytes. The Y and Z counter has no direct relationship to operand two. Therefore, a word count is maintained in the SC for operand two.

The source storage references move at random through a translation table that can vary in size for TR and TRT. This makes it impossible to make an initial address comparison to determine if there is a possible overlapping of the fields. For this reason, the word address (three low-order bits equal zero) of the word in K is placed in M. If the difference between the table address and the word address of the word currently in K is 0-7, the table byte required is in K. The GT K with S trigger is set, and the word returned from storage is not used.

The address calculated during Store/Fetch for the fetch is the address to be put in M. This address must be transferred to M before the store address is put in H. Therefore, the word in K is transferred to M and H is transferred to K. Then K and M are swapped to put the address in M and the result word being stored back in K.

16.5 PREFETCH SEQUENCE (PF)

16.5.1 INTRODUCTION

The function of the Prefetch sequence is to fetch source words from storage. See FIGS. 427-437. While one source word is being processed, the next word is being fetched from storage and put in the M register. When a source word boundary is encountered, the Prefetch sequence is initiated. The first cycle transfers M to L. After the first cycle, the iterations are started again. If another source word is required from storage, the remainder of the Prefetch sequence is allowed to follow the first cycle.

The Prefetch is initiated for decimal instructions, whenever the S pointer equals zero. For Logical instructions, the Prefetch is initiated whenever the S pointer equals seven. If the T pointer indicates a destination word boundary has been reached at the same time as the source word boundary, the Store/Fetch sequence has priority over the Prefetch.

The Address Advance line is brought up with PF 1. The Gate Select register is set at B of PF 1, and the following A clock sets the third half word of the op code into IOP (16-31). The Addressing Adder sum at the end of PF 2 will be B 2 + D 2 + D, where D is the VFL increment.

16.5.2 FIRST PREFETCH

The first Prefetch is started during Set-Up. Set-Up sequencers control the address generation and set the request trigger. The word returns after Set-Up is completed and the Iterations started. Therefore, PF 3 is set with SU 7 latch and reset with Accept from the BCU. PF 4 is set with the PF 3 latch and the Accept.

Since the first byte in an operand could be located anywhere within a storage word, there may be only one source byte to be processed before a second word is required. This means the first Prefetch would not be complete when the second Prefetch is started. In this case, the PF 1 trigger is turned on but the latch is not enabled until the J Loaded trigger is turned on. When PF 1 is turned on at the same time as PF 4, the M TO AM T/C gating trigger is not set. With PF 1 on, J is being gated to MA T/C at this time, and therefore it is J instead of M that is gated to L with the PF 1 latch.

16.5.3 INTERACTION WITH STORE/FETCH

If both operands come to a word boundary at the same time, the Store/Fetch sequence takes priority over the Prefetch and is executed first. This is done for two reasons:

If the Prefetch was allowed to go first, it would delay the Store/Fetch until an Accept was received and possibly delay it even more waiting for the storage cycle to complete. With the Prefetch following the Store/Fetch, most of it is overlapped with the iterations.

If the End of Operation conditions exist, the Prefetch sequence is not needed, and the Store/Fetch sequence ends the executions.

If a destination word boundary is encountered, or the End of Operation conditions occur while a Prefetch is in process, the start of the Store/Fetch is delayed until an Accept is received for the Prefetch request (PF 3 latch and Accept).

In some cases are shown operands crossing word boundaries at the same time, and the source crossing a word boundary one cycle ahead of the destination. In one example, two Store Fetch sequences are shown for the two possible cases of storage interferences. Another example shows the Prefetch and Store/Fetch fetching from the same storage bank. The second example shows the Prefetch fetching from the same storage bank that the Store/Fetch is storing into.

It should be noted that with multiple storage units, the two requests made during a Store/Fetch sequence are always made to different storage units and therefore do not interfere with each other.

16.5.4 DECIMAL INSTRUCTIONS

16.5.4.1 General

The Prefetch sequence is initiated if S PTR = 0 and SF 1 or SF 3 is not being set.

The first source word, B 2 + D 2 + L 2, is fetched during Set-Up. If a second word is required, the first Prefetch is initiated during Set-Up and this fetches B 2 + D 2 + 0 or B 2+ D 2 + 8 depending on whether the operand is in two or three storage words. When the first word boundary is crossed, if the Z counter is greater than 7, PF 2 is allowed to follow PF 1 and B 2 + D 2 + 0 is fetched. The field length limitation of 16 bytes limits the operand to a maximum of three storage words. If the operand is in two words, the Prefetch initiated at the word boundary consists of only one cycle, PF 1.

The S pointer is stepped even after the Z counter latch is equal to 1110 and the operand no longer enters into the result. It would be possible for a one-cycle Prefetch sequence to occur even though it is not needed. This is allowed because it should not happen very often; it only wastes one cycle out of many, and it is easier to prevent PF 2 from being turned on than it is to prevent PF 1 from being turned on.

16.5.4.2 Overlapping Fields

For AP, SP, ZAP and MVO, if the 0-7 Overlap trigger is on, each Prefetch moves the source into the same storage word that the destination is in. For this reason, the GT K with S trigger is set at the PF 1 latch and the PF 2 is not enabled. If the 8-15 Overlap trigger is on, M is transferred to L as usual. The word to be fetched is being generated in K and will be transferred to M on each Store/Fetch sequence.

Pack and Unpack must be handled differently for overlapping fields. In both instructions, the operands are used at different rates so that the initial address relationships do not hold throughout the execution. The overlap triggers are set according to the address comparisons as follows:

Pack

0 (B 2 + D 2 + L 2)-(B 1 + D 1 + L 1) <8 sets 0- 7 TGR

8 (b 2 + d 2 + l 2)-(b 1 + d 1 + l 1) <16 sets 8-15 TGR

Unpack

-8 < (B 2 + D 2 + L 2)-(B 1 + D 1 + L 1) <8 sets 0-7 TGR

8 (b 2 + d 2 + l 2)-(b 1 + d 1 +l 1) <16 sets 8-5 TGR

When either of these two triggers are on, the two low-order word address bits (H 19 and 20) are put in the ER and SC for the destination and source, respectively. Each time a word boundary is crossed, the corresponding register is decreased by one, and the two registers are compared for equal. If they are equal, it indicates the word boundary crossed moved the two operands into the same storage word. The address bits are in positions 1 and 2 of the ER and SC. They are decreased by adding 11 (the two's complement of 01) to them. The S3 is then subtracted from the ER. If all of the Half Sums of the Exponent Adder are equal to one, the two inputs are equal. Therefore, if HS = 1's, set GT K with S and if HS 1's, set GT L with S.

The Prefetch cannot be overlapped with the iterations when either of the overlap triggers is on. This is because the word being fetched might be in K. The Prefetch would fetch the word before the modified word (the result) had been stored. This would give an incorrect result. Therefore, the source fetches are made after the source word boundary is encountered. The AOB is gated to L as well as M with the PF 4 latch when one of the overlap triggers is on.

16.5.5 LOGICAL INSTRUCTIONS

The two Translate instructions do not use the normal Prefetch sequence because source bytes are fetched one at a time from a table and do not follow in sequence.

The Edit instructions do not overlap Prefetch with iterations. The stepping of Y AND Z does not have a direct relationship to the source bytes used and therefore it is impossible to determine if another source word is needed until a word boundary is encountered. At a word boundary, if Y and Z IOP (8-15), a word is fetched. If Y and Z = IOP (8-15), the Store/Fetch sequence is started and this having priority, suppresses the Prefetch sequence. It is still possible that a source word could be fetched that is not used. Therefore, the Address Invalid latch and PF 4 latch set VFL T7. The first digit that is examined with VFL T7 on sets the Invalid Address Interrupt.

Since Edits use the two operands at different rates, two separate word counts must be maintained. The Shift Counter (SC) is used to hold a word count for operand number two. Each Prefetch sequence adds one to the SC after it is used for the current fetch (the Set-Up sequence sets the SC to one initially). The SC bits 2-7 are gated to the AA positions 23-28 to generate the address B 2 + D 2 + (SC .times. 8). The Prefetch not being overlapped with the Iterations indicates the following:

1. the fetched word is put in L

2. the Iterations start after PF 4 instead of PF 1

The other Logical instructions overlap the Prefetch with the Iterations if there is no overlap and do not fetch if either overlap trigger is on. For the nonoverlap case, the ER + 1 is put in the SC during PF 2 in preparation for the next Store/Fetch sequence. The word count of processed words is kept in the ER. It is updated each time a result word is stored. Therefore, each Store/Fetch stores at B 1 + D 1 + ER and fetches from B 1 + D 1 + (ER + 1). The Store/Fetch sequence leaves either ER + 1 or ER + 2 in the SC, depending on whether the destination is crossing word boundaries ahead of or behind the source. When entering either a Prefetch or a Store/Fetch, the SC contains the address increment to be used for the fetch. Since the instructions move through both operands at the same rate, the two operands cross word boundaries alternately.

The Store/Fetch sequence for MVC starts at SF 3 and does not fetch. Therefore, the ER is transferred to the SC without being incremented.

Crossing a source word boundary, if the 0-7 Overlap trigger is on, moves the source into the same storage word that the destination is currently in. Therefore, the GT K with S trigger is set so that both operands use bytes from the same register.

17.0 VARIABLE FIELD LENGTH OPERATIONS

17.1 FIXED SEQUENCE VFL OPERATIONS

17.1.1 INTRODUCTION

The fixed sequence VFL operations are a group of instructions that in general handle one byte of data. They are considered as a group because they use "Fixed Sequence" sequencers but use the VFL data flow.

The following data is by description only the portion of these instructions that is done by the E Unit.

17.1.2 COMMON OPERATIONS

For the fixed sequence type of instructions, there are some things that can be discussed in common:

1. If the instruction requires a word (byte) from storage, 1ST FXP sequence will loop on itself until J is loaded with that word.

2. If the instruction requires a store, the STORE sequence will loop on itself until the ACCEPT LCH comes on. The ACCEPT LCH will turn on ELC and TOF BLK T2M. The instruction will then be terminated.

3. IOP 8-15 is set into Y and Z before the first E cycle of every instruction. For the S1 format instructions this is the immediate operand (I2). The condition that sets IOP 8-15 to Y and Z is:

(E NOT BUSY or E LAST CYCLE) (B CLK)

4. For most instructions in this group, it is necessary to use the low-order three bits of the address in H. Normally, 1ST FXP LCH would gate the set of H 21-23 to S and T. In the case where the contents of H are available for only one cycle, and 1ST FXP LCH is inhibited by J NOT LOADED, the byte address would be lost. To insure H 21-23 getting set into S and T within one cycle, the VFL T5 trigger is set at the same time as 1ST FXP. T5 stays on for only one cycle. T5 gates H 21-23 to S and T LCH and T5 LCH gates the release of S and T. This is done for all instructions in this group except ISK.

17.1.3 MVI-- MOVE, SI

MVI moves the immediate operand (byte from instruction stream) to the location specified by GR (B1) + D1.

The byte must be stored so that the VFL STORE REQ trigger is set during 1ST FXP sequence. The immediate operand is gated from Y and Z to AOE with HW LGC sequence. HW LGC LCH gates AOE LCH TO K and releases the byte in K that is selected by T PTR. The MARK selected by T is also set.

The byte is now in K waiting to be stored. ELC will terminate the operation.

17.1.4 CLI-- COMPARE LOGICAL, SI

CLI compares the immediate operand to the byte in storage specified by GR (B1) + D1. The Condition register is set according to the results.

During 1ST FXP sequence, the immediate operand is gated through AOE. It is set into K 24-31 with 1ST FXP LCH. When J is loaded, its contents are gated through MA T/C to L.

The two bytes to be compared are now in K and L. Operand No. 2 is in K 24-31 and Operand No. 1 is in the byte in L that is selected by S PTR. During HW LGC sequence the 2's complement of the byte in L is added to K 24-31. The AD CAR TGR and RESULT ZERO TGR are released with HW LGC LCH.

The Condition register is set during ELC. The setting of the bits is determined by the AD CAR TGR and RESULT ZERO TGR as follows:

CR 34 35 Equal compare 0 0 Op No. 1 < Op No. 2 0 1 Op No. 1 > Op No. 2 1 0 CR 34 = NOT CARRY TGR CR 35 = (CARRY TGR) (NOT RESULT ZERO)

17.1.5 ni, oi, xi-- and, or, exclusive or, si

the logical connective is performed between the immediate operand and the byte in storage specified by GR (B1) + D1. The Condition register is set to 00 for a zero result and 01 for a nonzero result.

When J is loaded, its contents are gated through MA T/C to L. Operand No. 1 is now in the byte in L that is selected by S.

The VFL STORE REQ trigger is set during HW LGC sequence. HW LGC gates Y and Z to one side of AOE. GT L WITH S TGR being on gates operand No. 1 from L to AOE. The instruction selects the proper logical connective gate to AOE. HW LGC LCH gates the results from AOE LCH to K and releases the byte selected by T. The MARK is set and the RESULT ZERO TGR is released with HW LGC LCH.

The result is stored, and the Condition register is set with ELC.

17.1.6 TM-- TEST UNDER MASK, SI

TM uses the immediate operand as a mask to test for bits in the first operand. The Condition register is then set to show the results of this test.

When J is loaded, its contents are gated through MA T/C to L. Operand No. 1 is now in the byte of L selected by S.

The AND gate to AOE is up during the operation. Y and Z is gated to AOE during HW LGC and ELC sequences. L WITH S TGR gates operand No. 1 from L to AOE. The gate to AOE is held up during ELC to hold the condition for setting the Condition register.

The Condition register is set as follows:

CR 34 35 AOE OUTPUT Lines All bits selected are 0 0 0 NOT A B Mask all 0 0 0 A or B Selected bits all 1 1 1 A NOT B Other conditions 0 1 NOT A NOT B

the output lines from AOE are:

A = aoe all ones = (no mask) + (mask) (bit)

b = aoe all zeros = (no mask) + (mask) (no bit)

the logical function for each CR bit is:

Cr 34 = a not b = (aoe all ones) (not aoe all zeros)

cr 35 = not b = (not aoe all zeros)

elc sets the Condition register and terminates the operation.

17.1.7 LA-- LOAD ADDRESS, RX

LA takes the address formed by GR (X2) + GR (B2) = D and puts it into the General register specified by R1.

1ST FXP is an idle cycle. H is not gated through the Incrementer to K because the Incrementer may be used at this time for a high order instruction counter advance.

H is gated through the Incrementer to K with HW LGC sequence. During ELC K 0-31 is put away and the operation is terminated.

17.1.8 STC-- STORE CHARACTER, RX

STC stores the low order byte of the GR specified by R1 in the address formed by GR (X2) + GR (B2) + D.

The contents of GR (R1) is set from RBL to M with the set of 1ST FXP. During 1ST FXP M is gated through MA T/C to K. 1ST FXP sets VFL STR REQ trigger.

HW LGC forces T OUT DECODE to byte 24-31 and this byte is gated through the decimal adder. HW LGC LCH gates AD LCH to K and releases the byte selected by T. The corresponding MARK is set.

With ELC the byte is stored and the instruction is terminated.

17.1.9 IC-- INSERT CHARACTER, RX

IC takes the byte from storage specified by GR (B2) + GR (X2) + D2 and puts it into the low-order byte of the General register specified by R1.

GR (R1) is set from RBL into M at the beginning of 1ST FXP and gated through MA T/C into K. During HW LGC the word specified by GR (B2) + GR (X2) + D2 is gated through MA T/C to L.

During HW ADD sequence the byte selected by S is gated from L through AD and set into K 24-31.

During ELC K 0-31 is put-away and the operation is terminated.

17.1.10 SSM-- SET SYSTEM MASK, SI

The byte in storage specified by GR (B2) + D2 is set into bits 0-7 of the PSW.

When J is loaded, its contents are gated through MA T/C to K. The I unit is then signaled that the byte is available.

ELC gates the byte in K selected by T to the VFL left byte gate which has a path to PSW 0-7. The IE unit then terminates the operation.

17.1.11 ISK-- INSERT KEY, RR

The Key of the storage block addressed by GR (R2) is inserted in bits 24-27 of GR (R1).

The E unit loops in 1ST FXP sequence until the TAG ADVANCE line comes back from the BCU.

During 1ST FXP GR (R1) is gated through MA T/C to K. The Key is gated to AOE with HW LGC and set into K 24-31 with HW LGC LCH. Bits 24-27 hold the Key and 28-31 are zero. ELC puts K 0-31 into GR (R1) and the operation is terminated.

17.2 DECIMAL MULTIPLY AND DIVIDE SET-UP

This section is an explanation of the sequencers that set up the registers and control triggers in preparation for the multiply and divide iterations.

17.2.1 MULTIPLY SET-UP FUNCTIONS

Before starting the multiply iterations, the length of the operands must be checked. If they are incorrect, a specification interrupt must occur.

The multiplier may start at any byte within a word and may cross a word boundary. During Set-Up, the entire multiplier is fetched and right-aligned in L. The multiplier is validity checked as it is moved.

The multiplicand digits are used from the low-order digit of J. Therefore, the low-order word of the multiplicand is fetched and right-aligned in J. Subsequent multiplicand words are properly aligned in J when fetched from storage.

K and M are cleared during Set-Up. This is done because the product is formed in these two registers.

17.2.2 DIVIDE SET-UP FUNCTIONS

Before starting the divide iterations, the length of the operands must be checked. If they are incorrect, a specification interrupt must occur.

The divisor may start at any byte within a word and may cross a word boundary. During Set-Up the entire divisor is fetched and right-aligned in L. Each byte is data checked as it is moved.

The high-order one or two words of the dividend are fetched to K and M. The low order of the two will go to K if a word boundary is crossed by the initial alignment of the divisor. If no word boundary is crossed initially, the high-order word will be in K.

17.2.3 SET-UP SEQUENCER FUNCTIONS

SU 1

IOP 8-15 (L1, L2) is set to Y and Z with E Last Cycle of the previous instruction. The gate of Y to AA is opened with SU L1. It is actually added during the next cycle, but because of the path length, the gate is brought up early.

SU 2

The VFL fetch request trigger is set during SU 2. This causes B1+D1+Y (L1) to be set into H and SAR.

L2 is compared to 7 and to L1. If L2 < 7 or L2 L1, the fetch request is blocked and the set of SU 3 is blocked. Termination of the instructions is begun by setting SF 3.

SU 3

VFL address advance is gated so B2 and D2 will be gated to AA during the next cycle. H (B1 + D1 + L1) bits 21-23 are set to T. The gate of Z (L2) is opened to AA. SU L3 is not enabled until the previous fetch request has been accepted.

SU 4

SU 4 sets the VFL fetch request trigger which causes B2 + D2 + L2 to be set to SAR and H.

Multiply

The control trigger T1 is set if T < 4. Trigger T2 is set if T equals 3 or 7. T1 is used during SU 12 to determine if a right shift of 32 is necessary to right-align the multiplicand. T2 determines if a byte shift is necessary during the first time in PF 1.

Divide

T1 is set if T (B1 + D1 + L1) < Y (L1). T2 is set if Y 8. T1 or T2 says that the dividend is in two words. T1 and T2 being on says that the dividend is in three words.

SU 5

H (B2 + D2 + L2) bits 21-23 are set to S. SU L5 is not enabled until the previous fetch request is accepted.

Multiply

The gate of Y TO AA is opened.

SU 6

The VFL address advance is gated so that B2 and D2 will be gated to AA during SU 7. The AD gating triggers, L WITH S and TD OUT are set with with SU L6.

Multiply

AA (B1+ D1 + L1) is set to SAR and H.

Divide

AA (B1 + D1) is set to SAR and H.

SU 7

The actions of SU 7 are inhibited and SU L7 is inhibited until J is loaded. When J is loaded, the contents of J (B1 + D1 + L1) are gated through MA T/C to K and M.

The control trigger T3 is set. T3 will control the setting of the multiplier (divisor) sign trigger during the first time in SU 10.

If S (B2 + D2 + L2) < Z (L2) the multiplier (divisor) is in two words and the VFL fetch request trigger is set. T4 is set to remember that the multiplier (divisor) is in two words.

Multiply

B2 + D2 is set to SAR by the setting of H (B1 + D1 + L1) is blocked.

Divide

B2 + D2 is set to SAR and H.

SU 8

The left byte gate (K) is gated to AOE so that the low-order byte of the multiplicand (dividend) can be decoded for the sign. T6 is set if the sign is negative.

Divide

The Gate of Z (L2) to AA is opened.

SU 9

SU 9 resets the T pointer and counts it down by 1 to 7. When J is loaded, its contents (B2 + D2 + L2) are gated through MA T/C to L. SU L9 is enabled with J loaded.

Divide

If the divisor is in one word, and the dividend is in two words, the VFL fetch request trigger is set. This causes B1 + D1 + L2 to be set to H but the set of SAR (B1 + D1) is blocked.

SU 10

SU 10 right-aligns the multiplier (divisor) by moving a byte at a time from L to K. It loops on itself until the end of the multiplier (divisor) field or a word boundary is reached.

If a word boundary is reached, SU 11 is set to bring the next multiplier (divisor) word to L. When the word is in L, SU 10 is set, and the right-alignment is continued. The multiplier (divisor) is data checked during SU 10.

T3 being on during the first cycle of SU 10 enables the setting of the multiplier (divisor) sign trigger. T3 is reset with SU L10.

SU 11

As stated above, SU 11 gates the second multiplier (divisor) word (B2 + D2) to L. This action depends upon J being loaded. SU L11 is enabled with J loaded.

Divide

If the divisor is in two words, and the dividend is in two words, VFL fetch request is set. The set of SAR (B1 + D1) and H (B1 + D1 + L2) is blocked.

SU 12

Multiply

SU 12 gates the right-aligned multiplier from K to RBL to J. It also gates the low-order multiplicand word (B1 + D1 + L1) from M to MA T/C to K. If T1 is on, the multiplicand will have to be shifted right at least 32 bits to be right-aligned. Therefore, T1 selects the right 32 shift gate during SU 12.

H (B1 + D1 + L1) is set to T. T is incremented in preparation for the first time in PF 1.

Divide

H (B1 + D1 + L2) is set to T and IOP bits 12-15 (L2) are set to Y and Z. The divisor is gated from K to MA to L with a right 4 shift to properly align the divisor for divide test.

17.2.4 PREFETCH SEQUENCER FUNCTIONS

PF 1

Multiply

PF 1 gates K to the shifter to K. T2 being on says that a right 8 shift is necessary the first time in PF 1. PF 1 loops on itself and T pointer is stepped until T equals 3 or 7. PF 2 is then set. Decoding for T = 3 is for the case when the multiplicand was shifted right 32 during SU 12.

Divide

1 is gated to AA (20). The low-order dividend word (B1 + D1 + L1) is gated from M to MA T/C to K.

PF 2

Multiply

PF 2 gates the right-aligned multiplicand from K to RBL to J. It also gates the right-alignment multiplier from J to MA T/C to L. The multiplier and multiplicand are now properly positioned for the iterations.

Divide

If the dividend is in three words, and J is loaded, the VFL fetch request trigger is set. This sets B1 + D1 + 1 to SAR. The set of H (B1 + D1 + L2) is blocked.

PF L2 is enabled with J Loaded or the fact that the dividend is in one word. If there is a request, when J is loaded (B1 + D1) it will be gated from J to MA T/C to M.

PF 3

Multiply

PF 3 increments the shift counter so it will be right for the first iteration. The sign digit is shifted out of J. T7 is set for the product sign gates. T1 and T2 are reset so that they can be used during the iterations.

Divide

If there was no fetch request in the previous sequence, PF L3 will be enabled and nothing will happen during PF 3. If there was a fetch request, when J is loaded (B1 + D1 + L1) it will be gated to MA T/C to K. Then K (B1 + D1 + L1) will be gated to RBL to J where it will be held until needed.

T7 is set for divide test and T1 and T2 are reset for use during the iterations.

PF 4

Multiply

The first multiplicand digit is set to DC. K and M registers are cleared by gating MAOB to them. Seq-D is set, following which the iteration will begin.

Divide

The S pointer is reset. If T (B1 + D1 + L 2) Y (L2) K and M are interchanged to get the proper starting point in K.

The Set-Up is now complete, and the divide iterations are started by setting IS 1.

17.3 MULTIPLY ITERATIONS

17.3.1 METHOD OF MULTIPLICATION

Decimal multiply is done basically the same in the environmental system as the normal "longhand" method. An example of this "longhand" process is shown below:

4976 multiplier .times. 23 multiplicand 14928 partial product +9952 partial product 114,448 product

The entire multiplier is multiplied by each digit of the multiplicand and the results are added with each partial product right-aligned with its corresponding multiplicand digit.

The computer must do each multiplication by adding the multiplier to itself a number of times equal to the multiplicand digit.

When the multiplicand digit is 6 or greater, the operation can be speeded up by multiplying the multiplier by 10 minus the multiplicand digit. The method is shown below.

Note: the use of multiplier and multiplicand may be opposite to the way they are normally thought of. This keeps the terminology consistent with that of said System/360 Manual.

Let A be the multiplier and B be the multiplicand digit. As a numerical example, consider A = 246 and B = 7:

a.times.b = a.times.10-ax(10-B) longhand check = 246.times.10-246.times.(10-7) = 2460-246.times.(3) 246 = 2460-738 .times.7 = 1722 1722

Multiplying the multiplier by 10 is accomplished by adding 1 to the next high order multiplicand digit.

The increase in speed by using this method is shown by the fact that it was necessary to subtract the multiplier only three times whereas it would have taken seven additions.

In general, the multiply process in said environmental system is as follows:

The low-order multiplicand digit is set into a counter and is decoded. If it is 0 (10 following a subtraction) the multiplier is shifted left one digit and the next multiplicand digit is set into the counter. If it is not 0 (10) it is decoded for D > 5 or D <5. As previously shown, this determines whether the multiplier will be added to or subtracted from the partial product.

The multiplier is then added (subtracted) to the partial product field a byte at a time. At the end of each addition of the multiplier, the counter is decremented (incremented) by 1 and decoded. The addition of the multiplier continues until the counter goes to 0 (10). Then the next multiplicand digit is set into the counter and the multiplier is shifted left one digit, etc. This continues until all multiplicand digits are exhausted.

17.3.2 REGISTER FUNCTIONS FOR DECIMAL MULTIPLY

17.3.2.1 J Register

J holds the multiplicand field. J bits 63--63 are sent to DC where counting of the additions takes place. As each multiplicand digit is set into DC, J is shifted right four to position the next digit so it can be set into DC when the present one is completed.

After Set-Up, the portion of the multiplicand that is to the right of the rightmost word boundary of the multiplicand field is right-aligned in J. The sign of the multiplicand has been set into a trigger and the sign digit of the field has been shifted out of J. During Seq-D, between Setup and the first iteration sequence, the first multiplicand digit is set into DC and that digit is shifted out of J.

17.3.2.2 K Register and M Register

K holds the portion of the partial product that is presently being worked on. M holds the portion of the partial products that is on the other side of the word boundary if a word is crossed by the present partial product.

As the multiplicand-product field can be up to 16-bytes long, there can be up to two word boundaries crossed by this field. The portion of this field that must be worked on at any one time is limited by the length of the multiplier which is a maximum of eight bytes. Therefore, two registers are sufficient to hold the portion of the field that is being worked on.

When a word boundary is crossed while making an addition, K and M are swapped. When the portion of the product that is contained within one word of the field is completed, SF 1 is set and that word is stored.

17.3.2.3 L Register

L holds the entire multiplier field right-aligned. This right-alignment is done during Set-Up.

17.3.3 VFL COUNTER AND POINTER FUNCTIONS FOR MULTIPLY 17.3.3.1 Y Counter

Y is initially set with the length of the multiplicand-product field (L1). When a byte of the multiplicand has been processed, Y is stepped down by 1. If Y < L2 the multiplicand field still has bytes left to process. When Y = L2, the product has been completed. All that remains is to check the high-order bytes of the multiplicand for nonzero. When Y = 0 the multiplicand-product field has been exhausted, and the multiplication is ready for termination.

17.3.3.2 Z Counter

Z is set with the length of the multiplier field (L2) at the beginning of every pass through the multiplier. It is stepped down by 1 every time a byte of the field is processed. When Z = 0 the multiplier has been completely added to the partial product.

17.3.3.3 S Pointer

S selects the byte from L that must be added to the partial product. It is reset at the beginning of each pass through the multiplier. As each byte is processed, S is stepped down by 1.

17.3.3.4 T Pointer

T selects the byte from K that must be added to the partial product and the byte of K that the sum must be set into.

The initial setting of T is determined by B1 + D1 + L1. As each byte of the multiplicand is processed, the starting point for the addition must be shifted left by one byte. Y is initially set with L1 and is stepped down by 1 as each multiplicand byte is processed. Therefore, T starting points are determined by B1 + D1 + Y.

When T is set to 0 from B1 + D1 + Y the last byte of a word is being processed. This means that when this multiplicand byte is completed, a new multiplicand word must be fetched. A word of the product field is also complete and must be stored.

17.3.3.5 DIGIT COUNTER

DC is set with the multiplicand digit that is to be processed. It is decoded for D 5 or D > 5. If D > 5 DC is incremented by 1 at the end of each pass through the multiplier. If D 5 DC is decremented at the end of each pass. DC is decoded for 0 or 10 to determine when a digit multiply has been completed.

17.3.4 ODD AND EVEN CYCLE DEFINITION

The basic addressable data unit in the environment system is the byte. In decimal multiply, the basic data unit is the digit. The multiplicand is processed a digit at a time and the effective shift of the multiplier with relation to the partial product must be a digit.

To get this effective shift of one digit to the left, the starting point of T is shifted left by one byte and L is shifted right one digit. Following the next multiplicand digit L is shifted left by a digit without changing the starting point of T.

To differentiate between these two cases, the shift counter is incremented after each multiplicand digit is processed. The odd cycles are defined as those during which the multiplier is in its leftmost position in L. Even cycles are those during which the multiplier is shifted right four in L.

As will be seen later, there are other things that must differ in odd and even cycles.

17.3.5 VFL SEQUENCER FUNCTIONS FROM MULTIPLY

IS 1

IS 1 is the first sequencer in every pass through the multiplier when adding to the partial product. IS 1 controls the gates to AD for sign control and Hot 1 for subtraction.

IS 2

IS 2 is the sequencer after IS 1 during which K and L bytes are added. It loops on itself until a word boundary is crossed or the multiplier field is exhausted.

IS 3

IS 3 is the sequence that is used to propagate a carry into the next byte of the partial product after a pass through the multiplier on odd cycles. IS 3 is not needed during even cycles because the multiplier is shifted right a digit. This leaves a high-order digit to collect the carries.

SF 12

SF 12 is used to swap K and M when a word boundary is crossed during a pass through the multiplier.

SEQ-A

Seq-A (FIGS. 465 and 466) is the first sequence following an addition of the multiplier. It resets S, gates L2 to Z and gates H (B1 + D1 + Y) to T. If a word boundary was crossed during the addition, K and M will be swapped back at this time. DC is stepped down (up when subtracting) during Seq-A and is decoded to determine if the digit multiply is complete. If it is, the next multiplicand digit is set to DC. If not, another addition (subtracting) must be made so IS 1 is set. If the digit multiply is complete, the next even cycle sequence is Seq-D. The next odd cycle sequence is Seq-B.

SEQ-B SEQ-C

When the odd cycle digit multiply is complete, the new Y value must be added to B1 + D1. Seq-B and Seq-C gate Y to AA and release H. See FIGS. 467 and 468.

SEQ-D

Seq-D shifts L right four following odd cycles and left four following even cycles. The shift counter is incremented during Seq-D. Seq-D gates H to T to get the new T starting point if Y was stepped and added to B1 + D1. J is shifted right four to position the next multiplicand digit. See FIGS. 469-471.

17.3.6 VFL CONTROL TRIGGER FUNCTIONS

See FIGS. 453-464.

T2--Dummy Cycle Trigger

Multiplicand digits can have values of 0-9. When a 9 digit is to be processed following a subtract DC will be incremented by one so a digit of 10 must be processed. If the 10 digit is processed during an even cycle, it is only necessary to shift L and proceed to the next multiplicand digit. If the 10 digit is processed during an odd cycle, it is necessary to go to IS 3 to gate 99 to K. To get to IS 3, it is necessary to make a pass through multiplier without adding. T2 is used to block the addition during this dummy cycle.

T3--True/Complement Trigger

T3 is set true if the multiplicand digit is 5 or less. It is set complement if the digit is 6 or more. T3 controls whether addition or subtraction cycles are taken.

T4--Swap Trigger

T4 is set every time a word boundary is crossed during a pass through the multiplier. T4 is being on causes K and M to be swapped during Seq-A. T4 is reset following the swap.

T4--Block Carry Trigger

Following a subtract cycle, the partial product is negative, and therefore, all digits above the significant digits are 9. It is necessary to use at least one of these high-order 9's in any computation.

During even cycles following a subtraction, it is guaranteed that there will be a high-order nonsignificant 9 in the partial product because an entire high-order byte was processed in IS 3 of the previous odd cycles.

During odd cycles following a subtraction, the next high-order byte (the one that will be processed with IS 3) will be 00 instead of 99 as it should be.

The fact that the high-order byte of the partial product is 00 instead of 99 can be compensated for in IS 3 of the first pass. This is done by blocking the carry into this byte as shown below:

is should be K 00 99 L 00 00 addition BLOCK 0 CARRY 1 CARRY

result 00 = 00 K 00 99 L 99 99 subtraction BLOCK 0 CARRY 1 CARRY

result 99 = 99

The carry is blocked by T5 which is set during even subtract cycles. T5 is then reset following the first pass so that the carry will not be blocked in subsequent cycles.

T6--Multiplicand Sign Trigger

T6 is set with the multiplicand sign during Set-Up and is used to force the product sign while multiplying by the first digit.

T7--First Digit Trigger

T7 is set during Set-Up and reset when the first multiplicand digit has been processed. Its function is to gate sign control during IS 1.

T8 Termination Trigger

T8 is set when Y = L2. It controls the multiplicand high-order zero detect.

Multiply Store/Fetch

Multiply store/fetch has two functions. First, a fetch is requested for the next multiplicand word. Then the completed portion of the product is stored from K.

During a store/fetch, the Y counter tells how much of the multiplicand remains to be processed. It is therefore used to determine the address of the words to be stored and fetched. If Y > 7, B1 + D1 + 1 is fetched and B1 + D1 + 2 is stored. If 0 < Y 7, B1 + D1 is fetched and B1 + D1 + 1 is stored.

17.4 DIVIDE ITERATIONS

17.4.1 METHOD OF DIVISION

To show the method of decimal division in said environmental system, consider first the normal longhand method as shown below: ##SPC11##

To generate the quotient the divisor is subtracted from the upper end of the dividend as many times as possible. The number of times it can be subtracted is the value of the first quotient digit. The divisor is then shifted right one digit. The second digit is developed by subtracting from this position.

This process is continued until the divisor has been shifted to the low end of the dividend and the last quotient digit is generated. What remains of the dividend is the Remainder. This may be shown a little more clearly below.

173 R=12 (23) 3991 (1) -23 169 1 - 23 146 2 123 3 -23 100 4 - 23 77 5 - 23 54 6 - 23 31 (7) -23 81 1 -23 58 2 - 23 35 (3) -23 12

for each quotient digit generated above, the divisor was subtracted until the remainder was less than the divisor. This is difficult for the computer to determine. Instead, the computer continues to subtract until the result goes negative. When the result goes negative, the divisor has been subtracted once too often. It must then be added back to get the proper result. The divisor is then shifted right four bits and the next quotient digit is generated in the same manner.

It is possible to speed up the preceding process by nonrestoring division. Instead of adding the divisor back when the dividend goes negative, the divisor is shifted right four in preparation for the next digit. The next digit is then generated by adding the divisor to the dividend until the dividend goes negative.

This is possible because the subtraction that causes the dividend to go negative for one digit is the same as 10 subtractions when the divisor is shifted for the next digit. In this case, the quotient digit counter is set to 9 and counted down.

In said environmental system, both the restoring and the nonrestoring methods are used. The high-order digits of the divisor and dividend are decoded to predict approximately what the next quotient will be. This quotient prediction allows the selection of the method that will be the fastest for each particular digit.

In general, the decimal division process in said environmental system is as follows: First, a divide check is made. The divisor is left-aligned with the left-most-but-one dividend digit. A trial subtraction is made, and if the result does not go negative, the dividend is too large. In this case, the divide check trigger is set and the division process is terminated.

If the result of the trial subtraction is negative, the operation continues. The divisor is shifted right one digit and subtracted from, or added to, the dividend. Whether a quotient digit is generated by addition or subtraction is determined by the positive or negative state of the dividend and the predicted quotient. The quotient digit is generated in a digit counter. When the first digit is completed, it is temporarily stored in a digit buffer. The divisor is then shifted right four and the next quotient digit is generated. Now that a full byte of quotient has been generated, it is put away in the upper end of the dividend-quotient field. This process continues until the divisor is right-aligned with the low-order byte of the dividend. The last quotient digit is then generated and put away. The Division is then terminated.

17.4.2 REGISTER FUNCTIONS FOR DECIMAL DIVIDE

17.4.2.1 J Register

In the decimal divide iteration, J serves no function in developing the quotient. Its only function is to receive any dividend word fetched from memory.

17.4.2.2 K Register and M Register

K holds the portion of the dividend-product field that is presently being worked on. M holds the portion of the dividend that is on the other side of the word boundary if a word boundary is crossed by the present alignment of the divisor.

As the dividend-product field can have a maximum length of 16 bytes, it can cross two word boundaries. The length of the divisor determines how much of this field is used in determining any one quotient digit. As the maximum divisor length is eight bytes, only one word boundary can be crossed by the portion of the dividend field being worked on.

At the beginning of the divide iteration, the high-order two words of the dividend field are in K and M. The first word that will be worked on is in K.

17.4.2.3 L Register

L holds the entire divisor right-aligned. The right-alignment is done during Set-Up.

17.4.3 VFL COUNTER AND POINTER FUNCTIONS FOR DIVIDE

See FIGS. 472-474.

Y Counter

Y is initially set to L2. Every time a byte of the dividend has been exhausted (a quotient byte generated) Y is stepped up by 1. When Y = L1, the last quotient digit is complete and the operation can be terminated.

Z Counter

Z is set with L2 at the beginning of each pass through the divisor. It is stepped down by 1 every time a byte of the divisor in L is used. When Z = 0 the addition has been completed with the exception of the extra byte during odd cycles.

S Pointer

S is reset at the beginning of each pass through the divisor. It is used to select the divisor bytes as they are subtracted from the dividend. S is stepped down by 1 as each byte is processed.

T Pointer

T is set with B1 + D1 + Y at the beginning of each pass through the divisor. It is counted down by 1 as each byte of the dividend is processed.

Y is stepped up by 1 as each byte of quotient is generated. Therefore B1 + D1 + Y provides the T starting point that shifts right while proceeding through the division.

T also selects the K byte in which to set the quotient. At the end of a pass through the divisor when a quotient byte has been completed, it is only necessary to step T down once more to set the quotient byte into K.

Digit Counter

DC is used to generate the quotient digit. It is set to 0 and counted up when the divisor is being subtracted from the dividend. It is set to 9 and counted down when the divisor is being added. It is stepped after every pass through the divisor until the dividend changes signs. When this happens the quotient digit is complete.

Digit Buffer

DB is used to hold one quotient digit while another is being generated in DC. Thus, a full byte of quotient can be stored after every other digit is generated.

Odd and Even Cycle Definition

To effectively shift the divisor right four, the first time it is only necessary to shift L right four. For the next right four shift, it is necessary to shift the starting point of the addition right 1 byte and shift L left four.

To keep track of this shifting, the shift counter is incremented after every digit is generated. The odd cycles are defined as those during which the divisor is in its leftmost position in L. During even cycles, the divisor is shifted right four in L.

An odd cycle quotient digit is put away in DB. When an even cycle quotient digit has been generated in DC, DB and DC are put away in K.

17.4.5 VFL SEQUENCER FUNCTIONS FOR DIVIDE

17.4.5.1 Iteration Sequencers

IS 1

IS 1 is the first sequencer in every pass through the divisor when subtracting (adding) from the dividend. IS 1 controls the gates to AD for sign control and Hot 1 for subtraction.

IS 2

IS 2 is the sequencer after IS 1 during which L bytes are subtracted (added) from K bytes. It loops on itself until coming to a word boundary or the end of the divisor field.

IS 3

IS 3 is used to process an extra byte during an odd cycle pass through the divisor. The extra byte is necessary because the next high-order digit of the dividend may not be zero. The extra cycle is not necessary during even cycles because the high-order divisor digit is the low-order digit of a byte.

17.4.5.4 Other Sequencers

SF 12

SF 12 is used to swap K and M when a word boundary is crossed during a pass through the divisor.

SEQ-A

SEQ-A is the first sequence following a subtraction (addition) of the divisor. It resets S, gates L2 to Z and gates H (B1 + D1 + Y) to T. If the portion of the dividend presently spanned by the divisor is in two words, K and M are normally swapped at this time. DC is stepped during SEQ-A if the quotient digit is not complete.

If the quotient digit is not complete, another subtraction (addition) must be made so IS 1 is set. If not, the next even cycle sequence is SEQ-B. The next odd cycle sequence is SEQ-D.

SEQ-B, SEQ-C

When the even cycle digit is complete, the new Y value must be added to B1 + D1. SEQ-B and SEQ-C gate Y to AA and release H.

SEQ-D

SEQ-D shifts L right four following odd cycles, and left four following even cycles. The shift counter is incremented during SEQ-D. SEQ-D also gates H TO T to get the new T starting point if Y was stepped and added to B1 + D1.

17.4.6 VFL CONTROL TRIGGER FUNCTIONS

T1-- First Word Store Trigger

T1 is set when the first quotient-remainder word has been stored. It is used in generating addresser of subsequent stores.

T2-- Restore Trigger

T2 is set when a quotient digit is complete and the decoding of the divisor, dividend and T/C says to restore the dividend before generating the next digit.

T2 prevents the things that normally happen when a quotient digit is complete until after the restore of the dividend.

T3-- True/Complement Trigger

T3 is set to control whether the divisor is added to, or subtracted from, the dividend.

T4-- Swap Trigger

T4 is turned on when the portion of the dividend that is being worked on moves into two words. It is turned off when the portion of the dividend that is being worked on moves into one word. Its function is to control the swapping of K and M after each pass through the divisor.

T5-- Block Swap Trigger

When generating the last quotient digit of a word, the swap trigger (T4) is still on. However, no word boundaries are actually crossed during these passes through the divisor. T5 is set to block swapping K and M between these passes. T5 also causes the set of SF 6. The store/fetch sequences will store the word that is in K.

T6-- Dividend Sign Trigger

T6 is set with the sign of the dividend during Set-Up. It is used to generate the quotient sign and to force the machine preferred sign to the remainder.

T7-- Divide Test Trigger

T7 is turned on during Set-Up and is reset following the divide test. It blocks setting the AD sum into K during divide test.

T8-- Termination Trigger

As each quotient byte is stored, the mark is set for that byte. When the division is complete, the remainder must be stored. Therefore, the marks must be set. To set the marks, a restore cycle is forced if it is not needed. If the restore is not actually needed, the results will not be set into K.

If the remainder is in two words (T4 on) the marks can only be set for the high-order word. A second restore cycle must be forced to set the marks for the low-order word after the first word has been stored. T8 is set during the store of the high-order if the swap trigger (T4) is on. During the restore of the low-order word, T8 being on when a word boundary is crossed causes the word to be stored and, consequently, the termination of the operation.

17.4.7 DIVIDE STORE/FETCH

The function of divide store/fetch is to store the complete portion of the quotient-remainder field which is in K.

To determine the address of the word to be stored, two triggers are used. T1 is turned on after the first word is stored. T4 (swap trigger) will be on until the last word is to be stored.

The address of the word to be stored is B1 + D1 + DELTA.

18.0 BINARY DATA FLOW (E UNIT)

18.1 INTRODUCTION TO E UNIT DATA FLOW FIG. 535 AND FIG. 536

In FIG. 535, the basic layout of the E unit data flow is shown. The basic input to the E unit is from storage, via the SBO which is located within the BCU to the J register. The J register can feed the main adder to complement input, can feed the main adder latch directly, send signals to the I unit, and also feed the RBL. The main data path in the binary portion of the E unit is through the main adder and via its output bus (AMOB) to the K M and L registers. The M register is utilized as a main buffering register within the E unit. The L register and K register are used as source and result registers for VFL operations, as well as the J register being a primary source register for storage.

The main adder includes a shifter which, as illustrated in FIG. 535, provides bits to the main adder output latch in dependence upon bits derived from the first-level circuitry in the main adder itself.

As illustrated in the lower right of FIG. 535, the IOP register in the I unit provides an input to the EOP register which in turn provides inputs to the E decode circuit (ED) and to the last cycle operation (LCOP). The output of the LCOP is decoded in the L decode circuit (LD).

Outputs 1 through 4 at the bottom of FIG. 535 apply to the exponent adder, which is shown in data flow fashion in FIG. 536. The data flow, as illustrated in FIG. 536, includes an exponent register (ER), a shift counter (SC), a shifter decrementer decoder (SFT/DCR DCDR). A VALUE DETECTOR FOR THE SHIFT COUNTER IS ALSO PROVIDED AT THE OUTPUT TO THE SHIFT COUNTER. The exponent adder has two inputs, which can be provided from the exponent register, from the M, J, and floating point registers (FIG. 535) from the shift counter, from the SFT/DCR DCDR, and from control circuits.

18.2 E UNIT OPERATION DECODERS

18.2.1 EOP REGISTER FIG. 537

In FIG. 537, the EOP register comprises a pair of latches 1, 2 which can be set in response to control signals generated elsewhere herein jointly with corresponding bits of the IOP register in the E unit.

18.2.2 LCOP REGISTER FIG. 538

In FIG. 538, the LCOP register responds to the EOP register in the same fashion as the EOP register responds to the IOP register.

In FIG. 539, a parity check is performed on the LCOP register by an EXCLUSIVE OR complex which can set a LCOP P CHK latch, the latch being reset by CHK RST.

18.2.3 E DECODE CIRCUITS

The E decode circuits are shown in FIG. 540 through FIG. 564. These circuits comprise various combinations of AND and OR circuits so as to generate not only instructions as such, but various combinations of operational bits which permit utilizing E decode output lines as specialized gating circuits to encompass groups of instructions which bear some relationship. The nomenclature of the output is straightforward in general, the outputs being indicative of the particular combination which the signal line name represents. For instance, in FIG. 559, a line designating fixed point AND or OR or EXCLUSIVE OR operations is generated. The input to the OR circuits which generates this line comes from other E decode circuits elsewhere herein. An asterisk (*) is utilized to indicate that any possible combination can take place at the point of the asterisk with respect to a decoded value for the particular line. For instance, in FIG. 555, a line called RX 4* is generated. This means that all RX instructions which include in the code thereof a 4 as the first digit of the code, and include any value from 0 through 9, and A through F as the second digit of the code are to be included within the meaning of that line. In terms of the chart shown in section 9.2.4.2 of said environmental system, this means that all RR instructions which have a code of 40, 41, 4A, etc. would be included.

Since the E decode circuits are obvious, no detail in the description thereof will follow. In certain instances, a particular configuration of E decode or L decode outputs may be utilized, and this configuration may not be shown directly in the circuits of FIGS. 540-564, or in the L decode circuits of FIGS. 565-580, but these configurations could be supplied in a manner similar to the manner in which those configurations which are shown are supplied. In other cases, a particular configuration may be generated more than once, which illustrates the possibility of powering decode lines by multiple generation thereof.

18.2.4 L DECODE CIRCUITS

The L decode circuits shown in FIGS. 565-580 are similar to the E decode circuits described in the last section. In other words, various combinations of particular outputs and "don't care" outputs (indicated by an asterisk) are provided. These are utilized throughout various parts of the E unit for generating further control lines.

18.3 FLOATING POINT REGISTERS FIGS. 581-586

In FIG. 581, the release controls for the floating point registers are shown. These permit changing the setting of the floating point register when the signals are present.

In FIG. 582, the circuit which responds to the SET FR2 signal from the I unit causes gating of the floating point register to transfer from response to BR 1 to response to IR2.

In FIG. 583, the actual registers are shown. As illustrated, the floating point registers are responsive to the K register and to the exponent register.

In FIG. 584, controls for selecting which floating point register will provide an output are shown.

In FIG. 585, the floating point register output gate is shown. This feeds a floating point register bus as shown in FIG. 586.

18.4 REGISTER BUS LATCH FIG. 587-FIG. 589

The register bus latch provides a buffer for general bus outputs and for floating point register bus outputs. In FIG. 587, the gating of the RBL is shown generally; this is shown in detail in FIG. 588 and FIG. 589. The register bus latch is a simple latching circuit which is enabled by the appearance of the NOT LC signal as shown in FIG. 587; therefore, the latch is not shown in greater detail.

18.5 J REGISTER

The J register is the input register from the storage via the SBO. It also has other inputs as illustrated by the J register gate circuit of FIG. 590. The input to the J register is shown in detail in FIG. 591 and FIG. 592. Release lines which permit changing of the contents of the J register are illustrated in FIG. 593, and the J register itself is shown in detail in FIG. 594.

18.6 K REGISTER FIG. 595 THROUGH FIG. 598

The input gating to the K register is shown briefly in FIG. 595, and in greater detail in FIG. 596. Circuits for generating unlatched lines that permit changing the contents of the K register are illustrated in FIG. 597, and the K register itself is shown in FIG. 598.

18.7 L REGISTER FIG. 599 THROUGH FIG. 601

The L register input gates are shown generally in FIG. 599, the release circuits therefor in FIG. 600, and L register details are shown in FIG. 601.

18.8 M REGISTER FIG. 602 THROUGH FIG. 606

The M register gating is shown in FIG. 602, and the M register input is shown in detail in FIGS. 603 and 604. Release lines for the M register are generated in FIG. 605, and the M register itself is shown in detail in FIG. 606.

18.9 EXPONENT REGISTER FIG. 614 THROUGH FIG. 616

Exponent register gates are shown in FIG. 614, the release line therefor in FIG. 615, and a brief illustration of the exponent register is shown in FIG. 616.

18.10 SHIFT COUNTER FIG. 617 THROUGH FIG. 620

The shift counter input gates are shown generally in FIG. 617, and in detail in FIG. 620. The release lines of the shift counter are shown in FIG. 618, and the shift counter register itself is shown in FIG. 619.

18.11 FIGS. 607-613 AND FIGS. 621-658

18.11.1 MAIN ADDER INPUT CIRCUITS

18.11.1.1 MA Input Gates FIG. 607

The left-hand input to the main adder is called "MA INPUT," whereas the right-hand input to the main adder is called "MA T/C IN." The MA input is shown in FIG. 607. Therein, the output of the various registers that can feed the left-hand side of the adder are illustrated as providing bits to particular gates at the input of the adder (from the center of FIG. 607 down) the condition under which the gate will be opened to the main adder being indicated by the gating lines drawn at the extreme left of FIG. 607. The main adder input would comprise a large OR circuit together with a plurality of AND circuits, one for each of the particular gates, much as in the same fashion as is illustrated, for instance, with respect to the K register in FIGS. 595 and 596. No further detail for this circuit is therefore shown.

18.11.1.2 MA T/C In Gates FIG. 608

A circuit similar to FIG. 607 is illustrated in FIG. 608, and represents the input to the right-hand half of the main adder. The various registers are gated to the main adder whenever signals appear on the lines illustrated to the left of each of the gating lines by lettering at the left-hand side of FIG. 608. No further detail of this circuit is shown.

18.11.1.3 Standard Main Adder Gating Triggers FIGS. 609 and 610

At the top of FIG. 609, a standard main adder gating trigger is shown. This is a trigger which may have one or two set inputs, one or two enable inputs, each of the enable inputs being valid only when there is an accompanying condition input. In the remainder of FIG. 609 and FIG. 610, either one, two, three or four inputs are shown in dependence upon whether one set input, one enable and one condition, or other combinations are utilized. The set inputs are so marked, the enable inputs are so marked, and any other input is a condition input. All of the circuits 1 in FIG. 609 and FIG. 610 represent standard gating triggers shown at the top of FIG. 609 with as many inputs thereto as are required, said inputs being indicated.

18.11.1.4 CVB Compacter FIG. 611 and FIG. 612

In FIG. 607, the CVB compacter is shown to receive inputs from bits 0 to 4 of the K register and to provide inputs to bits 61-63 of the main adder together with bits to the main adder to complement an input. The bit to the main adder through complement input is applied to bit 63 thereof, and an additional bit is provided to generate a "Hot 1" into the low order of the main adder. The general purpose of the CVB compacter is to convert a four-bit input to the main adder into a three-bit input to one part of the main adder together with one bit to the other input to the main adder and a carry. This is illustrated more clearly in FIG. 612. Whenever the CVB compacter is to be utilized, bits through bit 60 are supplied by the L register, leaving only bits 61-63 left for use as an input from the K register; since this is only three bits, the input cannot be applied directly to the main adder and the compactor must be used. The operation of the compacter is basically to convert four inputs (decimal 8 or greater) into three inputs (decimal 7) at the MA input, together with a single bit at the MA T/C IN which when added to the decimal 7 value will cause a result of 8, and if a carry is also forced at the main adder, this can cause a decimal 9. Thus, whenever bit 0 of the K register is a 1, decimal 7 is forced into the MA input by forcing bits 61-63 thereof to 1's, and a 1 is added to this result by forcing bit 63 of the MA T/C input to 1. In fact, the oddness and evenness of the values applied to the MA input are not accounted for by bit 63, but are rather accounted for by the Hot 1 which is applied to the main adder. This means that oddness and evenness has absolutely no parity effect with the single exception of the case where a 2 bit and a 4 bit appear with no other bits thereby causing the MA input to be odd. In this case, a parity correction factor is applied to account for the oddness of the total input thereto. This parity correction takes place only for decimal 2 and decimal 4, all other inputs comprising a combination of bits such that the total number supplied to the main adder and MA T/C inputs is an even number in all cases; only the Hot 1 input varies from even to odd. The CVB compacter is used in the convert to binary instruction only.

18.11.1.5 CVD Corrector FIG. 613

In FIG. 607, the output of the L register is passed through a CVD CORRECTOR for application to the main adder input. As illustrated briefly in FIG. 613, this corrector is merely an ordinary excess six-correction circuit of a well-known type. This permits converting binary values to decimal values as is well known in the art.

18.11.2 MAIN ADDER CIRCUITS FIG. 621

A brief description of the main adder circuits such as illustrated in the block diagram of FIG. 621. The main adder is a normal carry look-ahead adder which utilizes 4-bit groups and 16-bit carries so as to provide double level carry look-ahead in generation of bit carries. The operation of this adder is identical in principle in the operation of the address adder of said environmental system. The only difference is the position of section carries as is well known in the art. Apart from its carry look-ahead characteristics, however, the main adder does have special features which are described in later sections. As seen in FIG. 621, the main adder is seen to comprise a bit function generator (top of FIG. 621) which feeds a carry look-ahead section, the output of which controls a sum generating section; there is also provided a sum parity predicting section and an adder checking section. The total checking provided is sufficient to check every possible combination of inputs, and all circuit failures, for single or odd errors. This is described in somewhat more detail in later sections.

18.11.2.1 Introduction to Divide Decoder

The Main Adder high order byte, positions 0-7, has been implemented as a carry select adder. Basically, this differs from the seven lower order bytes in the resolution of the sums. The other adder functions--input-ORs, bit functions, half sums, sum parity, and checking, are the same.

18.11.2.2 Sum Generation

Each sum is a function (EXCLUSIVE OR) of the associated half sum and bit carry. The bit carries, in the lower order bytes, are functions of the group carry and the bit functions. The group carry, of course, has two states: 1 (carry) or 0 (no carry). For positions 0-7, two sets of bit carries are generated. One set (AC) is generated assuming the group carry in the 1 state; the other set (NAC) assuming the group carry in the 0 state.

The bit carry sets are then combined with the half sums, producing two sum sets. One sum set is associated with a group carry of 1 and is selected as the result sum if the look-ahead group carry result is a 1. The other set, associated with a group carry of 0, is selected if the look-ahead group carry is 0. The carry and sum sets are generated with positions 0-7 united as one group rather than two, as is the case in the lower order bytes. The entire eight position sum is selected dependent upon the carry into group 4-7 (GG 4-7).

FIG. 621 is a block diagram of the general components of the main adder, showing the sum generation path.

18.11.2.3 Divide Decoder

The divide decoder serves to determine the proper divisor multiple to be selected for each divide iteration cycle. The main adder high order byte is implemented as a carry select adder to provide early sums to compare with the divisor, generating the new multiple within the basic clock cycle. This saves at least a quarter of a cycle, and permits one divide iteration per machine cycle.

18.11.2.4 Multiple Resolution

The high order divisor bits, contained in the DB/DC registers, are compared with each of the sum sets according to the relationship required by the divide algorism. As the new dividend (ADDER RESULT) may be in either true or complement form, four functions are generated for each divisor multiple.

Example: 1/2 Multiple

1/2 Multiple & Result True & GG 4-7

1/2 multiple & Result True & NOT GG 4-7

1/2 multiple & Result Complement & GG 4-7

1/2 multiple & Result Complement & NOT GG 4-7

There are, therefore, four multiple sets generated. The selection is made in dependence upon the add result. If the add result is true (defined by the MA CPMNT TGR and the carry from position 0) and a carry into group 4-7 occurs, than the related set is selected for setting of the multiple latch. Similarly, the remaining combination of add result and C IN 4-7 select the other multiple sets. This is illustrated in the following tables:

Divisor Leading Zeros

The divide execution sequencing does not bit normalize the operands. However, the divide decoder adjusts for leading zeros in the divisor by comparing different bit groupings dependent upon these leading zeros.

First Cycle Multiple Selection

Prior to the first iteration cycle, the dividend may be positioned in different locations. Therefore, to determine the multiple for the first iteration cycle, the decoder is able to examine the dividend as it appears in these different locations. This is accomplished by ORing the possible first cycle dividend sources, under control of the execution hardware, prior to entering the comparison circuitry.

High Order Zeros Detector

Positions 0-3 of the two sum sets (AC and NAC) are examined for All Zeros and All Ones conditions. The correct function is selected by the carry to group 4-7 (GG 4-7), producing the two functions:

Ma 0-3 equal Zero

Ma 3-3 equal Ones

These functions are used by the execution control circuitry in determining instruction sequence. ##SPC12## ##SPC13##

18.11.2.5 Main Adder-Shifter

The main adder-shifter shown in FIG. 621 takes part in most data transfers within the E unit.

18.11.3 DATA PATHS AND CONTROL

The adder performs all of its operations with a minimum of control. The true add operation is the basic function of the adder and is performed with no control other than input and output gating. When operands are gated to each of the inputs, and no adder control is exercised, the sum of the operands is generated and gated to the MA latch. From the MA latch the sum can be delivered to the K, L, or M registers.

To perform an operation other than the true add, one or more controls is used. For example, to perform a shift, a control sets the shifter to give the desired output, gates the shifter to the MA latch and blocks gating of the final sum to the MA latch. The data path is from the bit functions to the normally selected ORE gate, through the shifter and the shift gate to the MA latch.

On adder operations, input parity is checked and output parity is generated. The check circuits require that correct parity be gated to both input OR's. For this reason, on single-operand operations, such as shifting, parity is forced to the input OR not receiving the operand.

18.11.4 DATA FLOW AND TIMING, EXAMPLE

The adder is a one-cycle data path. The sum of operands gated to the adder during a machine cycle is latched in the MA latch at L time following the cycle. The add takes place on the "first fixed point" cycle. The sum is delivered to K at A time of the next cycle.

On the AR ADD the adder receives inputs of two 32-bit operands and delivers a 32-bit useful sum. The operands are gated to the left or high order end of the adder input OR's. Parity is forced to the low order half of each input OR. A 64-bit sum having all significant digits in the high order 32 bits is delivered to K. Only the left 32 bits of K is gated to the general register R1.

The control of gates to the adder is external to the adder. The gating depends not only on the adder operation being performed but also upon the context of the operation. The gating for the true add performed when the AR instruction is being performed is as shown hereinbefore. The gating for a true add being performed during the execution of a multiply or divide instruction will be different and may involve shifted as well as straight gates.

18.11.5 BIT FUNCTIONS AND THE ADD OPERATION

Two operands are combined to generate bit functions; the bit functions then produce the final sum along two independent paths. One path produces the sum before carries. The other path produces the carries to each bit position.

The carry to each position is determined without waiting for the generation of the final sums in lower order positions. This fact is the time saver in the look-ahead circuits.

The Sum Before Carries for any bit position is a function of the input bits which follows these rules:

MA Bit + MA T/C Bit = sum before carries (HS) 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0

the sum before carries is the EXCLUSIVE OR of the input bits.

The Carry to any Bit Position is a function of the input bits to all lower order bit positions and is developed by the look-ahead circuits using two bit functions from each bit position.

Any single position will deliver a carry to the next higher order position according to the following rules.

0 + 0 will never produce a carry.

1 + 0 will produce a carry if the

0 + 1 position receives a carry.

1 + 1 will always produce a carry.

Note that two different predictions concerning a carry from any position can be made.

1. If either input bit is present, the position will produce a carry if it receives a carry. The position is said to transmit (T).

2. if both input bits are present, the position will always produce a carry. The position is said to generate (G).

The OR rather than the ORE is used in producing the transmit function. This does not interfere with operation of the look-ahead circuits since whenever both bits are present, the carry out is determined by the generate function and is not dependent upon the transmit.

The Transmit and Generate Functions for each bit position are delivered to the look-ahead circuits. The look-ahead circuits deliver a carry to any bit position if two conditions are met.

1. some lower order bit position generates.

2. all bit positions between the bit position to receive the carry and the generating bit position transmit.

The Final Sum is generated from the HS and the carry by the same rules used to produce the HS from the two input bits. That is, the final sum is the EXCLUSIVE OR of the carry and the HS.

18.11.6 LOOK AHEAD FOR THE FULL ADDER

To predict the carry into the high-order position of our 64 position adder using the logic thus far described would require 63 AND circuits any one of which could produce the carry. Further, the circuit testing for the condition in which the low-order bit generates and all other bits transmit would require 63 inputs. An adder using such circuits is said to have one level of look-ahead. By one level is meant that only bit functions are used to predict the carries to all positions. Three levels of look-ahead are used in said environmental system and thus avoids the cumbersome circuits described above.

To achieve three levels of look-ahead, the adder is divided into groups and sections, and the carries out of groups and sections are predicted by group and section functions.

A group contains four bit positions.

A section contains four groups.

Generate (G) and Transmit (T) functions are developed for each group and section. These functions have the same meanings as the bit functions generate and transmit.

Generate (g) means that the section or group will deliver a carry out.

Transmit (t) means that the section or group will deliver a carry out if it receives a carry in.

18.11.7 VARIATIONS OF THE ADD OPERATION

The true add is performed with no internal adder controls. Three other adder operations use the same data paths as the true add but require some control.

18.11.7.1 Complement Add

Complement addition is used to find the difference between two numbers. For the floating point instructions ADD and SUBTRACT, one's complement addition is used when the difference is required. Other operations requiring the difference between numbers use two's complement addition.

For two's complement addition one operand is changed to its two's complement and all other adder operation is as for true add. The two's complement is the inversion of the number with a 1 bit added to the low order position. Controls 1 and 2 change the operand entering the T/C input OR to its two's complement.

Control 1 SEL MA T/C CPMNT selects the inversion of the operand for the generation of the bit functions for the entire adder.

Control 2 HOT 1 adds a one bit to the low order position by forcing a group carry to group 63 to 63 and also causing the group to generate if all positions transmit.

For one's complement addition, one of the operands is changed to its one's complement and all other adder operation is as for true add. The ones complement is generated by inverting one of the operands and allowing a carry from the high-order position, if generated, to be fed to the low-order end.

Control 1 SEL MA T/C CPMNT selects the inversion of the input for the generation of the bit functions.

Control 3 ALLOW END CARRY enters the look-ahead logic at the section level and allows a carry out of the high-order position to be fed back to the low-order position.

18.11.7.2 Adder as a Straight Data Path

To use the adder as a data path, the operand to be moved is gated to either input, and all parity bits and no data bits are gated to the other input. The operation is exactly as for the add. The sum is equal to the single input operand.

18.11.8 PARITY GENERATION

The final sum of two operands is generated by EXCLUSIVE OR'ing the HS of the operands and the carries generated by the operands. The generation of parity for the final sum depends on a relationship that exists between the parity of the HS, the parity of the carries and the parity of the final sum. The relationship is:

Hs p V- = NOT Sum p

For example:

DEC Bit positions 1 2 3 4 Equiv 3 A 0 1 0 1 5 1 B 0 1 0 0 4 0 HS 0 0 0 1 0 Carries 1 0 0 0 0 Sum 1 0 0 1 9 1

In practice the HS and the carries within each group are available early in the adder cycle. The carries into groups come from look-ahead and are not available until later. The parity of the final sum is, therefore, generated in four stages.

1. The HS parity on each byte is generated.

2. The carry parity within each group is generated.

3. The parities generated in steps (1) and (2) are combined according to the relationship previously sighted to generate the parity of the final sum before group carries.

4. When the group carries are available they are used to change the parity generated in (3) dependent on properties of the final sum before the group carries. The parity changes can be predicted by examining certain of the HS within each group and the carry into the group.

Entering into the generation of parity for each byte, therefore, are three things:

1. The HS parity of the byte.

2. The parity of the carries within each of the two groups of the byte.

3. Two Change Parity Group (CPG) lines generated by examining the carry into the group from look-ahead and certain of the HS within the group. The output parity for group 8 to 15 is located hereinbefore in said environmental system.

18.11.9 INPUT PARITY CHECKING (BYTE HS PARITY ERROR)

The checking of input parities depends on a relationship that exists between the input parity of each operand and the HS of the operands. The relationship is:

Parity of A + Parity of B = NOT Parity of HS

For example:

1 2 3 4 Parity A 0 1 0 1 1 B 1 0 0 0 HS 0 0 0 1 0 P A + P B = NOT P HS 1 + 0 = NOT 0 1 = 1

to check input byte parity therefore:

1. The HS parity is generated for each byte.

2. The EXCLUSIVE OR of the input parities for each byte is generated.

3. (1) and (2) are compared. If they are the same, an input parity error has occurred.

The "Byte HS Parity Error" indicator is set.

The circuit generating Byte HS Parity Error for byte 8 to 15 is on said environmental system.

18.11.10 BIT FUNCTION ERROR

All outputs of the main adder-shifter depend upon bit functions generated for each input bit position. The adder contains circuits that will detect any single bit function error.

The bit function check is performed in the following steps:

1. The AND and OR bit functions and their complements are generated.

2. From these, the HS and complement HS are generated, independently of each other, for each bit position.

3. From the HS and complement HS generated in (2), the HS parity for each byte and its complement are generated.

Any single error in steps (1) to (3) will be detected by either the "Byte HS Parity Check" or the "Bit Function Error" circuits as follows:

A. Single error in (1) will cause either HS=NOT HS, or HS and NOT HS to be inverse of the proper result.

B. Single error in (2) will cause HS=NOT HS.

C. Single error in (3) will cause HS parity=NOT HS parity.

In A and B, when HS=NOT HS then HS parity=NOT HS parity and the Bit Function Error circuit will detect the error.

In A, when HS and NOT HS are inverse, the HS parity predicted HS parity and the HS Parity Check will detect the error.

In C, the Bit Function Check circuit will detect the error.

The HS Parity Error, Bit Function Error, and Byte Error circuits for byte 8 to 15 are on said environmental system.

18.11.11 LOOK-AHEAD CHECK

The look-ahead circuits predict the carry into each group. The low order bit position of any group receiving a group carry will always receive a bit carry. In order to check the look-ahead circuits, the adder predicts this same carry dependent only on the bit functions of, and the carry into, the next lower order bit. The carry from look-ahead and the predicted carry (KC) are compared: if they are unequal, an error has occurred.

18.11.12 SHIFTING AND LOGICAL CONNECTIVES

Shift operations and the performance of the logical connectives use data paths that differ from those of the add operation. The same bit functions used on the add operation are renamed and moved along different data paths to accomplish operations other than add. The logical EXCLUSIVE OR is the same function as the HS. The logical AND is the same function as the Generate.

Either or both of these functions can be gated to the shifter. The OR E gate to the shifter is normally conditioned, and is used to deliver the single operand to the shifter on shift operations, or to deliver the ORE of the two input operands to the shifter when the logical connective ORE is being executed.

To execute the logical connective AND, the line SEL LOG AND gates the AND function to the shifter and also degates the ORE function so that it does not reach the shifter.

To execute the logical connective OR, both the ORE and the AND functions are gated to the shifter. The SEL LOG AND line is conditioned, and the SEL LOG ORE line is allowed to remain conditioned.

When the data path is to be through the shifter, the output of the shifter must be delivered to the MA latch and the final sum must be blocked from reaching the latch.

18.11.12.1 Data Shifting

The relationship of input bits to output bits of the shifter for the various combinations of control lines that may occur is shown in said environmental system. The control scheme used and the operation of the shift control lines (R32, R8, R4, and L8) and the Inhibit bits 28 to 35 line are shown in said environmental system. Also are shown the operation of the Save Sign, Propagate Sign, and Propagate 16 control lines, and the operation of the Overflow control lines.

18.11.12.2 Shifter Parity Generation

Parity generation in the shifter depends upon the fact that when a single operand is gated to the adder, the HS of the operand is equal to the operand. On the logical connectives when two operands use the shifter path correct parity is not generated.

Parity generation for the shifter output takes place in four stages:

1. The adder delivers to the shifter the HS parity of each four-bit group and of the 3 bit left extension (bits 64-66).

2. The shifter combines the HS group parities into byte parities for all combinations of groups that may form output bytes. This is done by the Byte Parity Regeneration circuits. These circuits also take into account the effect of the Save Sign control on the bytes that may become byte 0 to 8.

3. The parity shifting circuits select the properly combined group parities for each output byte depending upon the shift being executed.

4. When any one of the four controls (Prop Signs, Prop 16, Overflow, or Inhibit bits 28-35) that may force output bits is active the Parity Shifter circuits adjust the parity accordingly.

Shifter Overflow Detector

When fixed point numbers are being shifted left, it is possible to shift out high order bits. This condition is detected by the shifter overflow detector.

The Save Sign line active indicates that a fixed point number is being shifted. With the save sign line active and a left shift taking place, all bits being shifted off are compared to input bit 0. If any bit to be shifted off differs from bit 0 the overflow condition is indicated.

Logical Connectives

The following is a summary of the adder-shifter's part in the execution of the logical connective instructions:

Two cycles are required for the operation.

On the first cycle:

1. Both operands are gated to the left end of the adder, and parity is forced to the right end.

2. One or both of the bit functions (Logic ORE or Logic A) are gated to the shifter depending on the connective to be performed.

3. The shifter is controlled to shift R4. Since the operands are 32 bits long, no bits are shifted out.

4. The right 4 shift control also serves to gate the shifter to the MA latch, and to disable the gate used by the final sum to reach the MA latch.

5. Both operands have been checked for correct input parity, but correct parity has not been generated on the output.

6. The output is delivered to the K register.

On the second cycle:

1. K having incorrect parity is gated to the adder.

2. The logic ORE function is gated to the shifter. This delivers the operand as received to the shifter.

3. The L4 shift control causes the connective to be delivered to the high order positions of the MA latch.

4. The connective now with generated parity is gated to K.

5. The left end of K is put away in general register R1.

18.12 EXPONENT ADDER

18.12.1 INTRODUCTION

The Exponent Adder provides a nine bit, fully checked data path between the source registers and the Exponent AND/OR Shift Counter registers. The low order positions (1-7) comprise a seven-bit binary adder, the eighth position (0) is used for floating point sign operations, and the ninth position is parity.

The primary function of the Exponent Adder is to perform exponent arithmetic and sign control functions, and to serve as a transfer path during floating point instructions. It also performs binary arithmetic for such purposes as incrementing and decrementing of shift amounts and iteration counts.

18.12.2 DATA FLOW FIG. 536

The basic data path is: source register to the Exponent Adder input ORs through the adder to the AEOB latch, and then to the Exponent or Shift counter registers. The input ORs are referred to as the AE-OR and the AE T/C-OR. The source registers to the adder inputs are:

AE INPUT AE T/C IN J 0-7 M 56-63 J 32-39 FLP 56-63 ER 0-7 SC 0-7

additional inputs to the AE-OR are received from the M and SC/H Decrement Decoder, and from the control area. The AE T/C-OR receives inputs from the VFL area in addition to the source registers listed.

18.12.3 BINARY ADDER

The seven-position adder employs parallel carry look-ahead to resolve the bit carry functions. The sums are generated as the EXCLUSIVE OR of the data inputs and the bit carries. Note that the two operands are combined to generate bit functions. The bit functions then produce the sum along two independent paths. One path produces the sum before carries (Half Sum). The other path, carry look-ahead, resolves the carries to each bit position.

Half Sum

The half sum for each bit position is a function of the input bits which follows these rules:

AE BIT AE T/C BIT = Half Sum 0 0 = 0 0 1 = 1 1 0 = 1 1 1 = 0

The half sum is the EXCLUSIVE OR ( +) of the data inputs.

18.12.4 BIT FUNCTIONS

The carry to each bit position (Bit Carry) is a function of the input bits and is developed by the look-ahead circuits. Each position will deliver a carry to the next higher order position according to the following rules:

AE BIT AE T/C BIT 0 0 Will never produce a carry. 0 1 Will produce a carry if the 1 0 position receives a carry. 1 1 Will always produce a carry.

Not that two different predictions concerning a carry from each position can be made.

1. If either input is in a "one state," the position will produce a carry if it receives a carry. The position is said to Transmit (T).

2. if both input bits are in a "one state," the position will always produce a carry. The position is said to Generate (G).

The OR function, rather than the EXCLUSIVE OR function, is used in producing the transmit. This does not interfere with the operation of the look-ahead circuits since the generate function determines the carry whenever both bits are present.

18.12.5 CARRY-LOOK-AHEAD

The bit functions for each position are delivered to the look-ahead circuits. The look-ahead circuits deliver a carry to each bit position if two conditions are met.

1. Some lower order bit position Generates.

All bit positions, between the generating bit position and the position to receive the carry, Transmit.

To implement the logic to resolve the bit carry to the high order position, as thus far described, would require six AND circuits, any one of which could produce the carry. Further, the circuit testing for the condition in which the low order bit generates and all other bits transmit would require six inputs. These cumbersome circuits are avoided by uniting the adder into two groups: three positions to the first (5-7) and four positions to the second (1-4). Generate and transmit functions are produced for each group and these are combined to produce a carry into the groups (Group Carry). The bit carries are developed from the group carries and the bit functions.

18.12.6 END AROUND CARRY

The end around carry function, when enabled, essentially removes the high/low-order relationship of the adder positions with respect to the carry functions. That is, to resolve the carry to each bit position, all other positions are treated as lower order positions. For example, if position 4 were to generate and positions 3, 2, 1, 7 and 6 were to transmit, a carry would be delivered to position 5. (D 4 & T 3 & T 2 & T 1 & T 7 & T 6 = C 5)

The end around carry function is incorporated in the group carry generation and is enabled or disabled by the Allow End Carry (AEC) control function.

18.12.7 SUM GENERATION

The final sum is generated from the half sum and the bit carry, following the same rules used to produce the half sum. That is, the final sum is the EXCLUSIVE OR of the bit carry and the half sum.

18.12.8 SUM PARITY

The generation of the sum parity depends upon a relationship that exists between the parity of the half sums, the parity of the bit carries, and the parity of the final sum. This relationship is:

Parity HS Parity Carries = NOT Parity Sum

The half sum parity and the parity of the carries within each group may be determined comparatively early in the adder path. The group carries, developed by look-ahead, are not available until later in the adder path. Therefore, the sum parity is developed as follows:

1. The parity of the carries within each group is generated (Internal Carries Parity).

2. The parity of the half sum is determined from the parities of the input operands (Predicted Half Sum Parity). The relationship of the half sum parity to the parities of the input operands is:

AE T/C Parity AE Parity = NOT HS Parity

The predicted half sum parity is the NOT EXCLUSIVE OR of the input parities.

3. The parities generated in (1) and (2) are combined according to the relationship previously sighted to produce the parity of the final sum before group carries (Internal Sum Parity).

4. The parity generated in (3) is changed if the number of sums changed by the group carries is odd (Change Parity). This condition is determined by examining certain half sums within each group, and the group carries.

The sum parity, therefore, is a function of the following, and is generated independently of the sums themselves:

1. The parity of the internal carries

2. The predicted half sum parity

3. The change parity

4. The sign control and AEOB complement functions, not related to the add function. The manner in which these functions modify the parity are defined hereinafter.

18.12.9 CHECKING

The checking functions are designed to detect the following:

1. A mismatch of the input data and its associated parity.

2. A failure within the adder which could result in multiple sum failures.

Input Parity Check

The checking of the input parities depends upon the relationship of the input parities and the half sums, as previously stated. To check the input parities:

1. The parity of the half sums is generated

2. The parity generated in (1) is compared with the predicted half sum parity. An inequality defines an error condition.

Bit Function Check

The adder contains circuitry which will detect all single bit function failures.

The half sum functions are generated in a manner such that a bit function failure will cause:

1. The half sum functions to be inverse of the proper result. This failure will be detected by the input parity check.

2. The half sum and its complement to be equal. This failure, as well as a failure within the half sum parity generation circuitry, will cause the half sum parity and its complement to be equal. A comparison is made of the half sum parity and its complement. An equality defines an error.

Group Carry Check

The group carry developed by the look-ahead circuits is equivalent to a carry from the high order bit position of the lower order group. This carry (K G) is developed from the bit functions of, and the carry into, the high order position of each group. The predicted group carry (K G) is compared with the equivalent group carry and an inequality defines an error.

Byte Check

The bit function check and the group carry checks are ORed to produce the function Byte Check. This function defines a failure internal to the adder circuitry.

18.12.10 SIGN CONTROL

Sum 0 (sign) is a function of its half sum and the sign control functions. If the resulting sum is different from the half sum, the sum parity is changed. The following chart defines these relationships: ---------------------------------------------------------------------------

Control Function HS 0 Sum 0 Change Parity __________________________________________________________________________ None 0 0 No None 1 1 No Set Sign Plus 0 0 No Set Sign Plus 1 0 Yes Set Sign Minus 0 1 Yes Set Sign Minus 1 1 No Invert Sign 0 1 Yes Invert Sign 1 0 Yes __________________________________________________________________________

18.12.11 COMPLEMENT GATES

Complement gates at the Exponent Adder input and output provide ability to perform complement arithmetic in both binary and excess 64 form.

AE Complement

A complement gate is implemented in the Exponent Adder following the AE T/C OR. This gate extends the full width of the AE T/C OR, including position 0 (sign). This allows for complementing the AE T/C input operand, and is enabled by the Select AE Complement control function.

AEOB Complement

A complement gate is incorporated in the AEOB latch, providing for the recomplementation of the adder sum. It extends from position 1-7 (position 0 is excluded) and is "split" after position 1. The two components Complement AEOB1 and Complement AEOB2-7, may be selected singly or together. The selection of the Complement AEOB1 gate causes the inversion of an odd number of sums (1), and a corresponding change in the sum parity. This feature provides the ability to perform the arithmetic operations defined hereinafter.

18.12.12 OUTPUT SIGNALS

Certain conditions are detected by the Exponent Adder circuitry which are of significance in the performance of particular instructions.

Half Sum One's Detector

A signal is generated when the half sums of positions 1-7 are all "one." With the AE Complement gate selected, this signal indicates the equality of the two input operands (positions 1-7).

High Order Carries Detector

The carries from positions 1 and 2 are detected by the adder look-ahead circuits.

Overflow/Underflow Detector

The result of exponent arithmetic can, of course, exceed the limits of exponent values. This occurrence is detected by the adder circuitry. A result in excess of the upper value limit defines an overflow condition. A result which exceeds the lower value limit defines an underflow.

Floating Point Operation

For all floating point operations, the Exponent Adder performs excess 64 arithmetic. All adder operands, including increment and decrement amounts, are considered as "excess 64" values. Four operations are performed by the Exponent Adder:

1. Exponent Transfer

2. Exponent Comparison

3. Exponent Subtraction

4. Exponent Addition

Exponent Transfer

The Exponent Adder serves as a data path through which the operand passes to the Exponent or Shift Counter registers.

Exponent Comparison

The adder result is equal to the absolute difference of the input operands. The result is obtained as follows:

A complement add, with end around carry enabled, is performed. The result will be the true binary difference if the AE input operand was the larger. Complementing Sum 1 (CPMNT AEOB1) yields the desired result.

The result will be the complement of the binary difference if the AE T/C input operand was the larger. Recomplementing yields the true binary difference. Complementing Sum 1 again would yield the desired result. However, this is the same result as is obtained by complementing sums 2-7 (CPMNT AEOB2-7).

Therefore, the sums are complemented dependent upon the form of the add result, defined by the carry from position 1.

Exponent Subtraction

The adder result is equal to the algebraic difference of the AE input operand subtracted from the AE T/C input operand. The result is obtained as follows:

A complement add is performed and sums 2-7 are complemented (AEOB CPMNT 2-7).

Exponent subtraction is performed to resolve the result exponent for divide, and to decrement exponents, preshift amounts and iteration counts.

Exponent Addition

The adder result is equal to the sum of the input operands. The result is obtained as follows:

A true add is performed and Sum 1 is complemented (CPMNT AEOB1).

Exponent addition is performed to resolve the result exponent for multiply, and to increment exponent values.

Binary Operation

For all nonfloating point operations, the Exponent Adder performs as a conventional binary adder.

19.0 BINARY CONTROLS

19.1 INTRODUCTION TO BINARY CONTROLS

The sections hereunder cover general control philosophy in the binary area of the E Unit. Since the points covered apply to many instructions, they are not repeated in the description of each individual instruction.

19.1.1 CONTROL TRIGGERS

Three basic types of control triggers are used in the E Unit. All three types are in general set and reset by a controlled A clock pulse.

19.1.1.1 Gating Triggers

Gating triggers are used to gate operands from the working registers into main adder and exponent adder. The combination of gating triggers needed for a particular cycle is set at the beginning of that cycle. The triggers stay on for one cycle and then return to the OFF state unless they are set again for the next cycle.

19.1.1.2 Status Triggers

Status triggers store the results of operations. Some typical status triggers are listed below:

MA C OUT O TGR: this trigger is set when a carry out of the high order bit of the main adder occurred in the previous cycle.

SELECTED K ZERO TGR: this trigger is set if an operand in the K register is all zeros.

E IRPT TGR: this trigger is set whenever the E Unit detects a program interrupt.

Status triggers may stay on, once they are set, until the end of the instruction; they may be set more than once during an instruction, or they may be set every cycle. Status trigger setting depends on the particular trigger and its usage in the instruction.

19.1.1.3 Sequence Triggers

Sequence triggers define the sequence of operations that the machine will go through to execute an instruction. The latched output of a sequence trigger together with operand decoding and status trigger outputs determine:

a. where the results of the current cycle will be placed;

b. what gating triggers will be set at the beginning of the next cycle; and

c. what sequence trigger will be set at the beginning of the next cycle.

In general, only one sequence trigger is on at a time. Exceptions to this are the triggers used for the multiply iteration and the last cycle of some instructions.

19.1.2 FUNCTIONAL ORS

The circuits that develop the control functions used in the data flow are called functional ORs. These functional ORs fall into the following classes:

In Gate and Release, lines gate the operands to the desired registers and release those registers. They must bracket the A pulse that releases the register. Thus, sequence and status trigger inputs that may change at the next cycle must be latched.

Gating Trigger Set Conditions, when active, unconditionally set the gating triggers. They must bracket the A pulse.

Gating Trigger Enable Condition lines are ANDed with late data conditions to set a gating trigger. The timing is the same as the set conditions.

Status Trigger Enable condition lines are ANDed with late data conditions to set a status trigger. The timing is the same as the set condition.

Control During Cycle: some control functions are accomplished during the cycle. Examples of this are selecting a constant shift amount in the shifter, or selecting a complement output of the exponent adder. All inputs to these functional ORs are unlatched.

19.1.3 TIMING

19.1.3.1 Generally

The path from a working register through the shifter and back to the register will provide an overall picture of the timing. The op decoding, possible status conditions, and the output of the previous sequence latch combine with an A clock to set a gating trigger. The gating trigger raises a gate and allows the data in one of the working registers (K, L, M or J) to enter the adder, where it flows simultaneously through the adder and shifter. The sequence trigger is set at the same time as the gating trigger. An output of the sequence trigger raises a gate which shifts the data by the required amount, and raises a gate which allows the shifted data (instead of the data which went through the adder) to enter the main adder latch. The L clock locks the shifted data in the adder latch so that it cannot change as it is being transferred back into the register. The same L clock locks the sequence latch to preserve the sequence through the next A clock. The output of the sequence latch, along with possible status conditions, selects a gate which allows the data in the adder latch to flow to the input of the desired register. Finally, the sequence latch and status conditions are combined with an A clock to set the data into the register. With the same A clock, of course, the sequence trigger and gating trigger are set for the next machine cycle.

In a general description it is impossible to discuss all the various control lines which may enter into the decisions to set a trigger or raise a gate. Therefore, the conditions described should be taken as a general guidance only.

The most important general timing rule is that all transfers of data or control are protected. For example, if a trigger is to be set with an A clock, the combinational logic that controls the setting of the trigger must be made up of lines that do not change during that A clock.

19.1.3.2 Timing Example: FLP LOAD (LD, LE)

An example of the timing of instruction operation is explained below:

1. 1ST FXP and ELC are the sequence triggers used in these instructions. Each stays on for only one cycle. This discussion assumes that the storage operand is in the J Register at, or before, the start of the E-time instruction.

2. During the first cycle, the J Register is transferred, left eight, through the shifter to the K register. To do this, a gating trigger from J is set to MA T/C and a gating trigger is set to force parity to MA. These triggers are both set at the same time as the first sequence trigger.

3. During the first cycle, the left eight shift line is raised. Since the shift occurs later in the cycle, a gating trigger is not needed for this gate. This line illustrates the delay in getting the signal from the output of the sequence trigger, through a functional OR and across to the point where it is used.

4. At the end of the first cycle, the shifted result is gated from the output of the adder latch to the input of K, and the K register is released. The control line straddles the A clock because it is formed by the latched output of the 1ST FLP sequence trigger.

5. During the first cycle, parity is forced to EA T/C. Since this is a shorter path than the data path, a gating trigger is not used. Therefore, the line is similar in timing to (3) above and the same comments apply.

19.1.4 STARTING OF AN INSTRUCTION

The starting of an instruction in the E Unit is conditioned by two functions, EN 1ST CYC and E GO. Both conditions must be satisfied simultaneously to start an instruction. The logic for EN 1ST CYC is:

(ELC LCH or NOT E BUSY LCH) & T2 LCH & NOT E IRPT

EN 1ST CYC is used to condition the functional ORs to gate prefetch operands into the J and M registers, to release the J and M registers when they are to hold the prefetch operands, and to set the gating triggers that would be used during the first E cycle. EN 1ST CYC is also ANDed with E GO to set the first sequence trigger.

If there is a delay of one or more cycles between the time that the E unit finishes one instruction and starts the next, EN 1ST CYC may be active without E GO. This could set invalid operands into M or J and could set first cycle gating triggers using an invalid operand code. However, when EOP does become active, those registers and gating triggers will be reset properly and no invalid condition will be retained.

If the I unit finishes the preparation of the next instruction before the E unit has finished the execution of the current one, the E GO line will become active before EN 1ST CYC. In this case, nothing happens until ELC LCH allows EN 1ST CYC to rise.

There are three different sequence triggers that can be used for the first E cycle. All floating point instructions use 1ST FLP TGR, all SS format instructions use VFL SEQ, T1, and all other instructions use 1ST FXP TGR. The following discussion will apply only to instructions which use 1ST FXP or 1ST FLP triggers.

If the instruction to be executed involves an operand coming from storage (generally an RX instruction), the operand may not be back from storage at the time of the I to E transfer. In this case, the completion of the first E cycle is delayed until the operand has been set into the J register. The reset of 1ST FXP or 1ST FLP and the setting of the next sequence trigger to be used is conditioned upon the rise of the latched output of the first cycle trigger. Also the setting of the first cycle results into registers is conditioned on the latched output of the first cycle trigger. The latch of 1ST FXP or 1ST FLP is blocked with NOT J LOADED TGR in all instructions using operands from storage during first cycle. Thus the E unit stays in 1ST FXP or 1ST FLP until the operand is in J. Of course, the operand could have been prefetched by the I unit so that it is in J before the I to E transfer. In this case, the J LOADED TGR would be ON and there would be no delay in completing the first E cycle.

In most binary instructions involving memory operands, the store or fetch request is made by the I unit. However, in some exceptional cases (for example, HW stores to some memory locations), the store request is made in the E unit. Store requests by the E unit for binary instructions are made through the VFL STR REQ TGR.

19.1.5 PREFETCH

Operands are prefetched to the RBL from the general and floating point registers by the I unit during T2 of the instruction preparation. During the I to E transfer, the RBL is gated to the M or J registers. Thus, the register operations are normally available in the working registers of the E unit during the first E cycle.

19.1.5.1 Fixed Point Instructions

Two general registers are gated to RBL and set into M. The left half of RBL will be the R1 operand, and the right half will be either the R2 operand or the R1 + 1 operand. Only those operands necessary for the execution of the instruction will be gated into M.

19.1.5.2 Floating Point Instructions

Since floating point operands may be 64 bits in length, only one operand is gated to the RBL at a time. In an RX instruction, the R1 operand is gated from RBL to M during the I to E transfer. In an RR instruction, the R2 operand is gated to J (with transformation to storage format) during the I to E transfer. The R1 operand is then gated to M during the first E cycle.

For a more complete discussion of operand gating from the registers see the Instruction Sequencing section of said environmental system.

19.1.5.3 Flush Path

A register operand that is used in one instruction may have been the result register for the previous instruction. In order to maintain speed in these cases, the path from the K register to a general or floating point register and back through the RBL to J or M must be made in one cycle. This path is called the "flush path" and is critical to the timing of the operation of the E unit. Because of the "flush path," it is not usually necessary to compare the result register of instruction (n) with the operand registers to be prefetched for instruction (n + 1). However, this is not true for a general register which is: (1) the result register for instruction (n) and (2) is specified as an element of an address for instruction (n + 1). In this case, the address calculation must be delayed until the register holds the valid result of instruction (n).

19.1.6 J LOADED TRIGGER

The J LOADED TGR is set at the same time as a storage word is set into the J register. The set condition is the same as for releasing the J register: J ADV and AR clock. The J LOADED TGR is set from a running clock so that it will be able to handle a storage fetch in the single-cycle mode. The reset of the J LOADED TGR, however, is with a controlled A clock.

The J LOADED TGR is generally reset at the end of the cycle in which the memory operand is transferred from J to another register. The reset logic makes the J LOADED TGR set or reset dominant as the situation warrants.

In general, a memory operand in J will be transferred through the MA T/C to some other register in the E unit during the performance of an arithmetical or logical operation. In this case, all the gating triggers from J to MA T/C are OR'ed and used to reset the J LOADED TGR. Since this transfer may in some cases not occur until one cycle after the word comes back to J, and the minimum memory bus rate is two cycles, this case requires a set dominant trigger. In all other cases, the J loaded trigger is reset dominant.

In FXP or FLP RX MPY and in some cases of SS MPY, the memory operand is not transferred from J through the adder. These cases are handled through separate inputs to the reset logic.

19.1.7 REGISTER RELEASE

19.1.7.1 General Registers

The results of most instructions except FLP or SS are placed in the general registers. This is accomplished by sending the result from K to the input of all registers, then releasing only the register selected by the ER 1 field. This release control line is generated during every PA or ELC cycle except when the BLOCK PA TGR is turned on. In the Multiple Load instruction, the register is also released during the EM1 and EM2 cycles.

19.1.7.2 Floating Point Registers

The floating point registers are released in a manner similar to the GR. Bits 0-55 of the input to the registers come from K and bits 56-63 come from ER (exponent register). For single FLP operations, bits 24-55 of the selected register are not released.

19.1.7.3 Block PA TGR

The BLOCK PA TGR is turned on whenever a result is not to be stored back in the registers. Store and compare are examples of operations which do not return the result to a register. In addition, any E-detected program interrupt which causes instruction suppression will turn on the BLOCK PA TGR.

19.1.7.4 Timing

Both registers are released with a special clock line. This clock will be basically a B clock but will be optimally timed for each set of registers. The release timing is critical because of the flush path. The flush path is the path from the K register, through any GR or FR and back through the RBL to the M or J register-all in one cycle. If this path were not used, it would be necessary to delay a cycle if one instruction called for a register that had been the result register of the previous instruction.

19.1.8 INSTRUCTION ENDING

The ELC (E Last Cycle) sequence trigger is turned on for the last cycle of every instruction. It may be on alone during the last cycle, or it may be on with the PA sequencer. In general, when the time of the last cycle can be determined unconditionally, the ELC trigger is turned on alone, When the last cycle is determined by data conditions, the ELC trigger is enabled from control logic, and ELC is then turned on with a late data condition from the data flow. For all binary instruction, the only trigger that is ever on with ELC is PA.

19.1.9 RESETS

All control triggers in the E unit (except the E RESET TGR) are reset by one or more of the four reset lines that enter the E unit. The reset of the triggers is DC-- in other words, it does not depend on the state of the clock lines. A table of the four reset lines and the triggers that they affect is shown below: ##SPC14##

Each trigger receives only one reset line which is the OR of the appropriate resets. The CPU RST line, as it enters the E unit, consists of the OR of the computer reset and system reset functions. Likewise, the CHK RST line is the OR of the computer reset, system reset, and check reset functions. (See the Manual Controls and Maintenance section of said environmental system.)

No registers in the E unit are reset directly from any of the above reset lines. Some registers, for example L, M, and J, are never reset. Other registers must be reset initially because they could cause the setting of a machine check trigger before they are loaded with valid data. These registers are K, ER, SC, EOP and LCOP. CPU RST is used to set the E RST TGR. The output is latched and used to perform the following functions:

Gate AMOB to K:

Release K:

Gate AEOB to ER and SC:

Release er and SC:

Reset EOP and LCOP.

The first clock pulse after the CPU RST will thus set K, ER, and SC to zeros with correct parity from the adder and busses. The EOP and LCOP will be DC reset until the E RST TGR is turned off. The first clock pulse also resets the E RST TGR.

19.1.10 SINGLE-CYCLE MODE

During normal operation, a fetch to J can be requested while J has an operand in it. In the time it takes for the new operand to get to J, the previous operand can be removed from J and placed in another register. This type of operation is not possible during single-cycle mode. When the machine is in single-cycle mode, the return of the operand to J is effectively instantaneous following a fetch request.

The situation described above occurs during binary instructions when an early TOF BLK T2M signal is generated to allow an earlier fetch of the operand for the next instruction. This early signal is blocked during single cycle mode and a late signal is unconditionally generated at the end of ELC. Thus, during normal operation, the TOF BLK T2M line is raised twice, once for the early TOF and once with ELC LCH.

19.1.11 MODAR

The MODAR trigger (in the Interruptions section) is turned on by the E unit whenever an addressable register is changed. An addressable register includes the condition registers as well as the general or floating point registers, or storage. If MODAR has not been set before, it is set during ELC, since some addressable register is always changed at the end of ELC.

19.1.12 OPERAND FORMATS

19.1.12.1 Fixed Point Format

Fixed point operands enter the E unit as 32-bit register operands set into either half of M, or as 32- or 16-bit memory operands in J. All 16-bit (or half word) operands are always expanded to 32 bits by propagating the sign position, 16 bits to the left, before any other operation is performed on them. Straight or left 32-bit gates from M and J to the adder allow the result operand to be left-aligned in K. Result operands are put in the GR from the high-order 32 bits of K.

Double operands (64 bits) can be fetched from the GR at one time (via GBL and GBR) stored in both halves of M. Double results, however, must be put in the GR in two sections. The high-order half of the result is put in GR R1 while the low-order half is being shifted left 32 bits from M to the adder so that it will be positioned for storing into GR R1 + 1 during the next cycle.

Although fixed operands are shifted for proper positioning, not bits are ever transposed and there is no basic difference in the format of a fixed operand in storage from that of one in the E unit.

19.1.12.2 Floating Point Format

Floating point operands enter the E unit (J register) as either single (32 bit) or double (64 bit) operands. In either case, the high-order bit is the fraction sign, the next seven bits are the excess 64 hexadecimal characteristic and the remaining 24 or 56 bits constitute the fractions. This format is called the storage format. Floating point operands within the E unit are converted to a new format called the working format. The conversion of a floating point operand from storage format to working format is accomplished by left ring shifting eight bits on a 64-bit base. Thus, in working format, the fraction occupies bits 0-23 of a single operand, and bits 0-55 of a double operand. In both cases, the exponent (fraction sign and characteristic) occupies bits 56-63. Operands located in the floating point registers are always in working format. Operands fetched from the FLP registers to M are likewise in working format. However, an operand fetched from the FLP registers to J is transformed to the storage format, then is retransformed to working format during the transfer from J to K. In addition to the two basic FLP formats, the exponent is generally separated from the rest of the word and store in the ER. The result fraction is loaded into the FLP registers from K, and the exponent from the ER into K.

The purpose of the transformation of FLP operands to working format is to align the high order bits of fixed and floating operands into the adder, thus simplifying gating and detection circuits and allowing the use of a 64-bit adder.

19.1.1.13 BINARY CONTROL CIRCUITS

The binary control circuits are not readily grouped for discussion. These include a large number of different controls which are interdependent, but which are not arranged in sets. The controls which are described in sections 18, 19, 20 are shown in FIG. 535 through FIG. 672, in conjunction with the binary data flow, as well as in FIG. 673 through FIG. 858.

19.2 INTRODUCTION TO FIXED SEQUENCE INSTRUCTIONS

Fixed sequence instructions are executed in the binary section of the E unit. These include the fixed point (FXP) instructions, excluding Multiply, Divide, Convert instructions, Multiple Load/Store, full word logical operations, Shift, and Branch instructions.

19.2.1 I TO E TRANSFER-INITIAL OPERAND LOCATION

The I unit controls the outgating of the general registers (GR) to the register bus latch (RBL), and makes the store and fetch requests to the bus control unit bcu) PRIOR TO TRANSFERRING THE INSTRUCTION TO THE E unit. Initial RBL to J and M register gating is determined by the EOP decoder, which is valid at least one cycle before the first execution cycle. Exceptions to the above are defined in the description of the instruction in which they occur.

When E GO is received by the E unit, the first execution cycle is initiated and the initial gating configuration is set. This finds the operand in M and/or J at the location hereinafter referred to as the "initial operand location."

19.2.3 FXP FULL-WORD INSTRUCTIONS

This section includes the load/store, sign control, and algebraic and logical arithmetic operations.

19.2.3.1 Load

This instruction is a two-cycle sequence consisting of an operand transfer and a result put-away.

At the start of the instruction execution, the R2 operand is located as follows:

Instruction Format R2 Operand RR M 32-63 RX-even J 0-31 RX-odd J 32-63

instruction sequencing is controlled by the two triggers listed below, in the order in which they occur:

1st FXP R2 transfer ELC termination

The R2 transfer, defined by the 1st FXP trigger, is a one-cycle operation. The R2 operand is gated from the J or M register to the Main Adder and returned to the K register.

The instruction termination, defined by the ELC trigger, is a one-cycle put-away. At the end of the R2 transfer cycle, the ELC trigger is set, the result operand is set into the GR, specified by R1, and the instruction is terminated.

19.2.3.3 Load Type Instructions

Load and Test, Load Positive, Load Negative, Load Complete

These instructions are two-cycle operations consisting of an operand transfer, with sign modification, and a result put-away. The result is examined to determine its relationship to zero.

At the start of the instruction execution, the R2 operand is located in M 32-63.

Instruction sequencing is controlled by the two triggers listed below, in the order in which they occur:

1st FXP R2 transfer ELC termination

The R2 transfer, defined by the 1st FXP trigger, is a one cycle operation. The R2 operand is gated from the M register to the Main Adder, two's complemented if the sign is to be changed, (see said System/360 Manual) and returned to the K register.

The instruction termination, defined by the ELC trigger, is a one-cycle put-away. At the end of the R2 Transfer cycle, the ELC trigger is set, the result operand is set into the GR specified by R1, and the instruction is terminated.

19.2.3.3 Add/Subtract (Algebraic & LOGICAL)

These instructions are two-cycle operations consisting of an operand addition and a result put-away. The result is examined to determine its relationship to zero.

At the start of the instruction execution, the operands are located as follows:

Instruction Format R1 Operand R2 Operand RR M 0-31 M 32-63 RX-even M 0-31 J 0-31 RX-odd M 0-31 J 32-63

instruction sequencing is controlled by the two triggers listed below, in the order in which they occur:

1st FXP add ELC termination

The add cycle, defined by the 1st FXP trigger, is a-one cycle operation. The R1 operand is gated to the main adder from the M register. The R2 operand is gated to the main adder from the J or M register, two's complemented if the instruction is Subtract, and added to the R1 operand. The sum is then returned to the K register.

The instruction termination, defined by the ELC trigger, is a one-cycle put-away. At the end of the add cycle, the ELC trigger is set, the result operand is set into the GR specified by R1, and the instruction is terminated.

19.2.3.4 Compare (Algebraic & Logical)

These instructions are two cycle operations consisting of an operand addition and the testing of the result to determine the relationship of the two operands.

At the start of the instruction execution, the operands are located as follows:

Instruction Format R1 Operand R2 Operand RR M 0-31 M 32-63 RX-even M 0-31 J 0-31 RX-odd M 0-31 J 32-63

instructions sequencing is controlled by the two triggers listed below, in the order in which they occur:

1st FXP add ELC termination

The add cycle is identical to the Add cycle as described in Add/Subtract, for the Subtract case above.

The instruction termination, as defined by the ELC trigger, is a one-cycle test of the result. At the end of the Add cycle, the ELC trigger is set and the instruction is terminated.

19.2.3.5 Store

This instruction is a multiple cycle operation consisting of the store preparation, wait cycle and result store.

At the start of the instruction execution, the R1 operand is located in M 0-31.

Instruction sequencing is controlled by the two triggers listed below, in the order in which they occur:

1st FXP store preparation and wait Store termination cycle

The store preparation cycle is defined by the 1st FXP trigger. The R1 operand must be properly positioned in the K register, depending upon the store address: if the store address is odd, the operand must be placed in the low order half of the K register.

The R1 operand is gated from the M register to the main adder, shifted R32 if the store address is odd, and set into the K register.

The instruction termination, as defined by the store trigger, is a variable cycle operation depending upon the ACCEPT signal from the BCU.

If, at the end of the store preparation cycle, the ACCEPT signal has not been received, a wait cycle is taken. Wait cycles are continued until the ACCEPT is received. Gating is not performed during the Wait Cycle and the operand is not modified.

At the completion of either the store preparation cycle or a wait cycle, the ELC trigger is set if the ACCEPT signal has been received. With the ELC trigger on, the instruction is terminated.

19.2.4 FXP HALFWORD INSTRUCTIONS

The halfword instructions work with halfword operands (two bytes, one syllable) and are essentially separable into two classes. These are:

Class 1 --Register to Storage

The halfword Store is unique to this class. The basic operation is the positioning of the operand, depending upon the store address. If the store address indicates a store to the high order half of a full word, the E unit makes the store request during the first execution cycle. This is an exception to the usual operation: in all other cases, the I unit makes the store request.

Class 2 --Storage to Register

All halfword instructions, except halfword Store, belong to this class. The operation is the expansion of the halfword operand to full word length, and then the completion of the instruction function as though it were its full word counterpart.

19.2.4.1 Halfword Expansion

At the start of the instruction execution, the R2 operand is located in dependence upon the operand address as follows:

H REG 21 22 R2 Operand 0 0 J 0-15 0 1 J 16-31 1 0 J 32-47 1 1 J 48-63

the R2 halfword operand may occur in any of the four halfword locations (0-15, 16-31, 32-47, 48-63) within the double-word J register. The operand is gated from either the high-order half (if H 21=1) or the low-order half (if H 21=0) of J to either 0-15 or 16-31 of the high-order half (0-31) of the main adder, in dependence upon the operand address. If the operand address is odd (H 22=0), the operand is then at MA 0-15 and the operand is shifted eight bits to the right (R8) into bits 8-23 of the K REG. In each case, the sign is inserted (propagated) into the eight high-order positions (0-7) of the K REG. This partially expanded operand, consisting of eight bits of sign followed by the halfword operand, is gated from the K register to the RBL, and the RBL is gated R8 to the J register, with the sign inserted into the high-order eight positions. This completes the expansion of the R2 operand to full word length, with the halfword operand being in bits 16-31 of the J REG, and the sign of the operand filling bits 0-15 of the J REG.

19.2.4.2 Load

This instruction uses a four-cycle sequence. The operation consists of the expansion of the R2 operand to full word length, and result put-away.

Instruction sequencing is controlled by the four triggers listed below, in the order in which they occur:

1st FXP sign propagation HW or LGC K to J transfer HW ADD R2 transfer ELC termination

The sign propagation cycle is defined by the 1st FXP trigger. The R2 operand is gated from the J register to the main adder. The sign is propagated in the high-order byte as the operand is shifted, in dependence upon the operand address; the result is then returned to the K register, as described above.

The K to J transfer cycle is defined by the HW OR LGC trigger. The partially expanded R2 operand is gated from the K register to the register bus latch (RBL), which is then gated, R8, to the J register, with the sign propagated through the high-order byte. At the completion of this cycle, the fully expanded operand is in bits 16-31 of the high-order half of the J register.

The R2 transfer cycle is defined by the HW ADD trigger. The R2 operand is gated from the J register to the main adder, and returned to the K register.

The instruction termination, defined by the ELC trigger, is a one-cycle put-away. At the end of the R2 transfer cycle, the ELC trigger is set, the result operand is set into the GR specified by R1, and the instruction is terminated.

19.2.4.3 Add/Subtract

These instructions are four cycle sequences. The operation consists of the expansion of the R2 operand to full word length, the addition of the two operands, and result put-away. The result is examined to determine its relationship to zero.

At the start of the instruction execution, the operands are located by the operand address as follows:

H REG 21 22 R2 Operand R1 Operand 0 0 J 0-15 M 0-31 0 1 J 16-31 M 0-31 1 0 J 32-47 M 0-31 1 1 J 48-63 M 0-31

instruction sequencing is controlled by the four triggers listed below, in the order in which they occur:

1st FXP sign propagation HW + Log. K to J transfer HW ADD add ELC termination

The sign propagation cycle is identical to the sign propagation cycle as described for Load, above.

The K to J cycle is identical to the K to J transfer cycle as described for Load, above.

The add cycle is defined by the HW ADD trigger. The R1 operand is gated to the main adder from the M register. The R2 operand is gated to the main adder from the J register, is then two's-complemented if the instruction is Subtract, and thence added to the R1 operand. The sum is then returned to the K register.

The instruction termination, defined by the ELC trigger, is a one-cycle put-away. At the end of the add cycle, the ELC trigger is set, the result operand is set into the GR specified by R1, and the instruction is terminated.

19.2.4.4 Compare

This instruction is a four cycle sequence. The operation consists of the expansion of the R2 operand to full word length, the addition of the two operands, and the testing of the result to determine the relationship of the two.

At the start of the instruction execution, the R2 operand is located as follows:

H REG 21 22 R2 Operand R1 Operand 0 0 J 0-15 M 0-31 0 1 J 16-31 M 0-31 1 0 J 32-47 M 0-31 1 1 J 48-63 M 0-31

instruction sequencing is controlled by the four triggers listed below, in the order in which they occur:

1st FXP sign propagation HW OR LGC K to J transfer HW ADD add ELC termination

The sign propagation cycle is identical to the sign propagation cycle as described for Load, above.

The K to J cycle is identical to the K to J transfer cycle as described for Load, above.

The add cycle is identical to the add cycle as described in Add/Subtract, for the Subtract case, above.

The instruction termination, as defined by the ELC trigger, is a one-cycle test of the result. At the end of the Add cycle, the ELC trigger is set and the instruction is terminated.

19.2.4.5 Store

This instruction is a multiple-cycle operation consisting of the store preparation cycle, wait cycle, and result store cycle.

At the start of the instruction, the expanded R1 operand is located in M 0-31. The low-order half, M 16-31, contains the R1 operand.

Instruction sequencing is controlled by the three triggers listed below, in the order in which they occur:

1st FXP store preparation HW + Log. K to K transfer Store termination

The R1 operand must be properly positioned in the store operand, dependent upon the store address. This positioning may be separated into two cases. Case 1-- Address with H 22=1

If the store address includes H 22=1, then a store to the low-order half of a full word is required. For this case the R1 operand is properly positioned within the low half of the full word boundary as it exists in the GR specified by R1. If the store address is odd (H 21=1), the operand is shifted R32 to place it in the odd, or low-order half of the double-word store operand.

Case 2 -- Address with H 22=0

When the store address includes H 22=0, a store to the high-order half of a full word is required. As the R1 operand is initially in the low-order half, a shift of L16 is required to position it properly within the full word boundary. As in Case 1, above, if the store address is odd, the operand needs to be shifted R32 in order to position it within the low-order half of the store operand.

For this case, the resulting shift of the R1 operand is either L16 or R16: these shift amounts are actually attained by a successive pair of shifts of L8 or R8, respectively.

The store preparation cycle is defined by the 1st FXP trigger. The R1 operand is gated to the main adder from the M register, shifted by an amount dependent upon the store address, and returned to the K register.

At the completion of this cycle, the operand is either properly positioned in the K register, or further shifting is required.

If a store to the high-order half of a full word is required (H 22=0), the operand is not properly positioned at the completion of the store preparation cycle. This being the case, a K to K transfer cycle, defined by the HW OR LGC trigger, is taken. The R1 operand is gated from the K register to the main adder, and shifted by an amount dependent upon the store address. The result is then returned to the K register, completing the positioning of the operand.

The instruction termination, as defined by the STORE trigger, is a variable cycle operation dependent upon the ACCEPT signal from the BCU. The instruction termination is begun at the completion of the cycle which properly positions the operand.

Wait cycles are taken while awaiting the ACCEPT signal from the BCU. Gating is not performed during the wait cycle and the operand is not altered.

The ELC trigger is set upon receipt of the ACCEPT signal. With the ELC trigger on, the instruction is terminated.

19.2.5 LOGICAL CONNECTIVES

AND

OR

EXCLUSIVE OR

These instructions are three-cycle sequences consisting of the generation of the logical connective, parity generation, and result put-away. The result is examined to determine its relationship to zero.

The logical connective functions are performed in the main adder, using the "AND," and/or the "EXCLUSIVE OR" gates. The functions are attained as follows:

Logical AND AND Gate Logical OR AND and EXCLUSIVE OR Gates Logical EXCLUSIVE OR EXCLUSIVE OR Gate

As these functions use the shifter as a data path, a shift amount must be selected. A shift of R4 is used to provide this path through the shifter.

The parity generated as a result of the AND instruction or the OR instruction may be incorrect. A cycle is taken to generate proper parity, and to shift the result operand L4 to compensate for the shift during the generation of the connective.

At the start of the instruction execution, the operands are located as follows:

Instruction Format R2 Operand R1 Operand RR M 32-63 M 0-31 RX-even J 0-31 M 0-31 RX-odd J 32-63 M 0-31

instruction sequencing is controlled by the three triggers listed below, in the order in which they occur:

1st FXP connective generation HW OR LGC parity regeneration ELC termination

The R1 operand is gated from the M register to the main adder. The R2 operand is gated to the main adder from the M or J register. The connective function is performed in accordance with the particular instruction, and the result is shifted R4 and then returned to the K register.

The connective operand is gated to the main adder from the K register, shifted L4 and returned to the K register. The K register parity check, and the main adder half-sum parity check are disabled during this cycle for the AND instruction and for the OR instruction.

This cycle completes the connective operation. At this time, the result operand is located in the high-order half of the K register, properly aligned and with correct parity.

The instruction termination, as defined by the ELC trigger, is a one cycle put-away. At the completion of the parity regeneration cycle, the ELC trigger is set, the result operand is set into the GR (R1), and the instruction is terminated.

19.2.6 SHIFT INSTRUCTIONS-- SINGLE, DOUBLE

Shift Right

Shift Left

Shift Right Logical

Shift Left Logical

These instructions are variable cycle sequences, consisting of the shifting of the operand and result put-away.

Operand shifting consists of two separate operations. These are:

1. First Cycle Shift

2. Shift Iteration

The H register 18-23 contains the shift amount, which is valid through the first execution cycle. H REG 18-20 is set into the shift counter register 4-6 at the start of the first execution cycle. The shift counter register 4-6 and the H register 21-23 define the shift amount, and are decoded to determine the shift and decrement amounts.

The M register out-gates (R1, R2, R3), referred to as the "bit shift" gates, and the main adder shifter amounts, are selected so that the sum of the two will equal the shift amount required for the cycle.

Examples:

Required Shift M REG Shifter R5 R1 R4 L5 R3 L8

the shift amount required for the first cycle may range from zero to a maximum shift of eight. If there is a shift of eight, the shift counter register is decremented by two.

After the first cycle shift, the remaining shift amounts, if any, will be some multiple of 8. During shift iteration cycles, the operand is shifted by eight and the shift amount decremented by two, since a shift of eight bits is manifested by a 1 in bit 6 of the SCR, and bit 6 has a value of binary 2, being second from low order.

At the start of the instruction execution, the R1 operand is located as follows:

Instruction FoR 1 Operand Single M 0-31 Double M 0-63

instruction sequencing is controlled by the three triggers listed below, in the order in which they occur:

1st FXP shifting PA termination--first put-away ELC termination--final put-away

In a first cycle shift, the R1 operand is gated from the M register to the main adder, shifted, and then returned to the K and M registers. The M register outgate is selected, and the shift amounts are determined by the SFT/DCR DCDR as shown in the following table: ##SPC15##

X = can be either one or zero: effect is accounted for in successive cycles.

When SCR 6 = 1, and H REG = 000, successive cycles are required.

The shift counter register is gated to the exponent adder (EA), decremented by two if the R1 operand is being shifted by eight, and returned to the shift counter register.

If, after the first cycle shift is completed, additional shifting is required, a shift iteration cycle is taken. The R1 operand in the M register is gated to the main adder, shifted eight, and returned to the K and M registers.

The shift counter register is gated to the Exponent Adder, decremented by two, and returned to the shift counter register. Iteration cycles are continued until a shift counter register value of two is detected, indicating a value of zero after completion of the current cycle. Notice that at least one cycle is taken to shift the amount specified by the H REG, which is not decremented; successive cycles are controlled by the SCR which is decremented.

The instruction termination is either a single or double put-away, depending upon the instruction. When a shift counter register value of 2 is detected (such that the shift being performed will decrement the shift counter register to zero), shifting is terminated and result put-away is begun.

At the completion of the final single put-away shift cycle, the PA and ELC triggers are set, the result operand set into GR (1), and the instruction is terminated.

If double put-away is required, at the completion of the final shift cycle, the PA trigger is set, and the result operand (R1) is set into GR (R1). The low-order half of the M register, containing the R1 + 1 result operand, is gated L32 to the main adder and returned to the K register.

The ELC trigger is then set, the result operand (R1 + 1) is set into GR (R 1 + 1), and the instruction is terminated.

In algebraic shifting, the sign of the R1 operand is maintained by the "save sign" function which inhibits shifting into the sign position. If a left shift occurs in which a bit different from the sign is shifted out of position 1, the shifter overflow trigger is set. The instruction sequencing is not altered due to this occurrence.

The M propagate sign trigger is set equal to the R1 operand sign at the beginning of the first cycle. This trigger controls the propagation of the sign in the bit shift gating from the M register. The propagate sign function, generated during algebraic shifts, controls the propagation of the sign in the shifter.

19.2.7.1 Branch on Count

19.2.7 BRANCH INSTRUCTIONS

The function of the execution unit in the performance of branch instructions includes the put-away of operands, and the calculation and comparison of operands to determine the status of the branch condition.

This instruction is a two cycle operation consisting of the decrementing of the R1 operand, and result put-away. The I unit is signaled as to the result of the decrementing.

At the start of the instruction execution, the R1 operand is located in M 0-31.

Instruction sequencing is controlled by the two triggers listed below, in the order in which they occur:

1st FXP count ELC termination

The count cycle, as defined by the 1st FXP trigger, is a one cycle operation. The R1 operand is gated to the main adder from the M register, added to complement zero (all ones), and returned to the K register.

The instruction termination, defined by the ELC trigger, is a one cycle put-away. At the end of the count cycle, the ELC trigger is set, the result operand is set into the GR specified by R1, and the instruction is terminated.

A branch successful condition (E BR SUCC) exists when the result operand is not reduced to zero. This is indicated by an initial operand value greater than one, detected by the M zero detector during the count cycle. The E unit branch successful trigger is set if this condition is detected.

19.2.7.2 Branch and Link

This instruction is a two cycle sequence consisting of the transfer of the low-order half of the PSW to the K register, and result put-away.

At the start of the instruction, the operand is located in the low-order half of the PSW in the I unit.

Instruction sequencing is controlled by the two triggers listed below, in the order in which they occur:

1st FXP ICR to K ELC termination

The ICR to K cycle, defined by the 1st FXP trigger, is a one cycle operation. The low-order half of the PSW is gated to the INCR, and the INCR is gated to the high-order half of the K register. Both of these gating operations are controlled by the E unit.

The instruction termination, defined by the ELC trigger, is a one-cycle put-away. At the end of the ICR to K cycle, the ELC trigger is set, the result operand set into the GR specified by R1, and the instruction is terminated.

19.2.7.3 Branch on Index (BXH and BXLE)

These instructions are three cycle sequences, consisting of the addition of the R1 and R3 operands, comparison of this sum with the third operand, and put-away of the R1 and R3 operands sum. The I unit is signaled as to the result of the comparison.

At the start of the instruction execution, the operands are located as follows:

R1 Operand M 0-31 R3 Operand M 32-36 Third Operand GR (R3 or R3 plus 1)

Instruction sequencing is controlled by the three triggers listed below, in the order in which they occur:

1st FXP add PA compare ELC termination

The add cycle, defined by the 1st FXP trigger, is a one-cycle operation. The R1 and R3 operands are gated to the main adder from the M register, added, and returned to the K register.

The third operand is gated from the general registers to the low-order half of the M register, under the control of the I unit.

The compare cycle, defined by the PA trigger, is a one-cycle operation. The K register, containing the sum of the R1 and R3 operands, is gated to the main adder. The third operand is gated from the M register to the main adder, two's complemented, and added to the sum of R1 and R3. The result is returned to K register.

The R1 and R3 sum is set into GR (R1) during this cycle.

The instruction termination, as defined by the ELC trigger, is a one-cycle operation. At the end of the compare cycle, the ELC trigger is set, and the instruction is terminated.

A branch successful condition exists when the R1 and R3 operands sum is related to the third operand as follows:

Branch on Index High = R1 + R3 greater than third operand

Branch on Index Low-Equal = R1 + R3 equal to or less than third operand

The relationship of the R1 and R3 sum to the third operand is defined in the table below.

Signs Carry from MA 0 sum VS 3rd opnd Alike 1 Greater than Alike 0 Equal/Less than Unalike 1 Equal/Less than Unalike 0 Greater than

The branch successful trigger in the E unit is set at the end of the compare cycle, if the branch condition is satisfied.

19.3 INTRODUCTION TO FLOATING POINT INSTRUCTIONS

Floating Point instructions are executed by the binary section of the E unit. Floating point operations, excluding Multiply and Divide, are described in this section. Multiply and Divide, along with their fixed point counterparts, are covered in another section.

19.3.1 I TO E TRANSFER

The I unit controls the outgating of the floating point registers (FPR) to the register bus latch (RBL), and makes the store and fetch requests to the BCU prior to transferring the instruction to the E unit. Initial RBL to J and M register gating is determined by the EOP decoder, which is valid at least one cycle before the first execution cycle. This provides the initial operand location.

When E GO is received by the E unit, the first execution cycle is initiated and the initial gating configuration is set.

19.3.2 INTERRUPTS AND CONDITION CODE

Interrupt handling and condition code are not described generally in this section, but the changes in the sequencing and the result of an instruction caused by particular interrupts are defined. In cases not specifically defined, the sequencing and the result are not altered.

19.3.3 FLOATING POINT ADD/SUBTRACT

These instructions consist of a characteristic comparison, fraction preshift, and the algebraic addition of the operand fractions. The result fraction is examined to determine its relationship to zero.

19.3.3.1 Initial Operand Locations

At the start of the instruction execution, the operands are located as follows, where SP and DP refer to single precision and double precision:

Instruction Format R1 Operand R2 Operand RR-SP FLP (R1) J 0-31 RR-DP FLP (R1) J 0-63 RX-SP-Even M 0-23, 56-63 J 0-31 RX-SP-Odd M 0-23, 56-63 J 32-63 RX-DP M 0-63 J 0-63

19.3.3.2 instruction Sequencing

Instruction sequencing is controlled by the three triggers listed below, in the order in which they occur:

1ST FLP characteristic comparison Preshift-Add preshifting and fraction addition PA termination

19.3.3.3 Characteristic Comparison

The characteristic comparison cycle, defined by the lST FLP trigger, is a one-cycle operation consisting of the exponent subtraction and the transfer of the R2 fraction from the J register to the K register.

In the exponent subtraction cycle, the R2 exponent is gated to the exponent adder from the J register. The R1 exponent is gated to the exponent adder from the FLP or M registers, complemented, and added to the R2 exponent. The result, the exponent difference, is then set into the shift counter register and exponent register.

The R3 fraction is gated from the J register to the main adder, shifted L8, and set into the K register. The R1 operand, gated from FPR (R1) to the RBL, is set into the M register, if the instruction format is RR.

The preshifting and fraction addition sequence, defined by the preshift-add trigger, is a variable cycle operation. If the exponents are equal, subtraction of the two will result in "exponent adder half-sums all equal to one." The exponents are unequal if this condition is not satisfied, the larger being defined by the carry from the high-order position of the exponent adder.

An exponent difference sets the preshift trigger defining, within the preshift-add sequence, the preshifting operation. The register containing the fraction of the smaller exponent (M IF A CARRY, K if none) is gated to the main adder, shifted R4 or R8 dependent upon the shift counter value, and returned to the register from which it came.

The shift counter register is gated to the exponent adder, decremented by an amount equal to the number of hexadecimal digits that the fraction is being shifted, and returned to the shift counter register. The decrement amount and the shift amount are determined by the SFT/DCR decoder. The shift counter register is gated to the SFT/DCR decoder during preshifting.

Preshifting continues, in the normal case, until the SFT/DCR decoder detects a shift counter register value equal to or less than two. This is the indication that the exponents of the two operands will be equal at the end of the current cycle, and, therefore, this cycle completes the preshifting operation. The preshift trigger is turned off at this time, ending preshifting.

Fraction addition is performed if the characteristic comparison indicates equal exponents or, in the case of unequal exponents, preshifting is completed and the exponents have been equalized. The fraction addition cycle, within the preshift-add sequence, is defined by the OFF condition of the preshift trigger.

The operand fractions, contained in the K and M registers, are gated to the main adder, added algebraically, and the result is returned to the K and M registers. The following chart describes the form of addition performed, dependent upon the operand signs and the instruction itself:

Operation Instruction R1 Sign R2 Sign Performed ADD + + True ADD ADD + - Complement ADD - + Complement ADD - - True ADD SUBTRACT + + Complement SUBTRACT + - True ADD SUBTRACT - + True ADD SUBTRACT - - Complement

The exponent of the intermediate fraction sum is the larger of the operand exponents. The R1 exponent is contained in the M register. The R2 exponent has been lost. The R2 exponent, if the larger, is equal to the R1 exponent plus the exponent difference obtained during the exponent comparison cycle.

The R1 exponent is gated to the exponent adder from the M register during the fraction addition cycle. The exponent register, containing the exponent difference, is gated to the exponent adder if the R2 exponent is the larger. The adder result, which is equal to the larger exponent, is returned to the shift counter and exponent registers.

If the exponent difference is equal to or greater than 14, (meaning that one operand is very much greater than the other) the preshifted fraction will be zero. Addition of the two fractions would yield a result equal to the fraction with the larger exponent. Therefore, if an exponent difference of this magnitude is obtained, the result fraction is known to equal the fraction with the larger exponent. Preshifting and fraction addition are omitted in this case.

The occurrence of an exponent difference, but not the magnitude of this difference, is detected during the characteristic comparison cycle. The exception here is an exponent difference greater than 63, which cannot be represented in the shift counter or exponent registers. This condition is detected during the exponent comparison cycle, setting the exponent overflow trigger if the R2 exponent is positive, or setting the exponent underflow trigger if the R2 exponent is negative.

Preshifting is initiated in dependence only upon the occurrence of an exponent difference, and not the magnitude of that difference. If the shift counter register is equal or greater than 14, or if the exponent overflow trigger or exponent underflow trigger is on, it will be detected by the SFT/DCR decoder during the first preshift cycle. The preshift trigger is turned off, the exponent overflow and exponent underflow triggers are reset, and preshifting is terminated after one cycle.

The register which is not preshifted contains the fraction with the larger exponent. This register is gated to the main adder, added algebraically to zero, and returned to the K and M registers. The determination of the result exponent is the same as in the normal case fraction addition.

The fraction addition cycle completes the preshift-add sequence. The intermediate sum, in either true or complement form, is contained in the K and M registers. The exponent and sign of the intermediate sum are contained in the shift counter and exponent registers.

19.3.3.5 Termination

The termination sequence, defined by the PA (put-away) trigger, is also a several-cycles operation. The functions of this sequence include fraction recomplementation, normalization, exception handling, and result put-away.

A fraction overflow carry is indicated by a carry from the high-order position of the main adder during a true add cycle. The M register, which contains the intermediate sum, is gated to the main adder, shifted R4, a "one" is forced into position 3, and the result returned to the K and M registers. The exponent register is gated to the exponent adder, incremented by a "hot one" and returned to the exponent register.

The ELC trigger is then set, the result fraction and exponent set into FPR (R1) and the instruction terminated.

If there is no fraction overflow carry, an unnormalized sum is assumed and a normalization cycle is taken. The M register is gated to the main adder and complemented (if the intermediate sum is in complement form). It is shifted by an amount which depends upon the instruction and the number of high-order zeros in the M register. The adder result is then returned to the K and M registers. The exponent register is gated to the exponent adder, decremented by an amount equal to the number of hexadecimal digits the fraction is being shifted and returned to the exponent register. The decrement and shift amounts are determined by the SFT/DCR decoder. The M register is gated to the SFT/DCR decoder for the add subtract normalized instructions only. Therefore, for the add subtract unnormalized instructions, the shift and decrement amounts are zero and the intermediate sum and exponent are not altered. Normalization continues, for the normalized instructions, until the fraction is normalized or an exceptional condition is detected.

If the intermediate sum is normalized, the ELC trigger is set, the resultant exponent and fraction set into FPR (R1) and the instruction is terminated after one cycle of normalization. In the case of an unnormalized instruction with an unnormalized intermediate sum, the ELC trigger is set if lost significance is not detected. In the case of a normalized instruction with an unnormalized intermediate sum, the ELC trigger is set when the fraction becomes normalized if exponent underflow is not detected. With the ELC trigger ON, the result exponent and fraction are set into FPR (R1) and the instruction is terminated.

Lost significance is detected during the first normalization cycle, after recomplementation of the intermediate sum, if required, by the K register zero detector. The entire K register is examined for lost significance except for the case of single precision, unnormalized add/subtract. For this case, only the six high-order hexadecimal digits are examined. This is due to the possible appearance of a significant seventh digit, the guard digit, which is not part of the result fraction.

When lost significance is detected, normalization is terminated and a significance adjustment cycle is taken. If the significance mask bit is one, the exponent of the intermediate sum is to be the exponent of the result. The shift counter register, which contains this exponent, is gated to the exponent adder and returned to the exponent register. When the significance mask bit is zero, the shift counter register is not gated to the exponent adder; the exponent adder, whose output is zero, is returned to the exponent register.

The ELC trigger is then set, the result exponent and fraction set into the FLP (R1) register and the instruction is terminated.

Exponent overflow may be caused when the exponent is incremented due to a fraction overflow carry. The exponent overflow trigger is set but the sequence is not altered by this occurrence.

19.3.3.6 Sign Handling

The sign of the intermediate sum is determined from the R2 sign and the instruction is performed. For add, the sign of the intermediate sum is set equal to the sign of R2 as defined by the R2 sign trigger. For subtract, the intermediate sum sign is set inverse to the R2 sign. If the intermediate sum is in true form, its sign is correct. If the intermediate sum is in complement form, the sign is inverted during the recomplement cycle.

The sign of the result fraction is set to zero if lost significance or exponent underflow occurs. This is done during the adjustment cycle respective to each.

19.3.3.7 Supplementary Description

Some details have been omitted in the description of the instruction sequencing in an attempt to maintain continuity. These are covered in this section.

During single precision preshifting, zeros are forced at the Main Adder output in positions 28-35. This maintains the seventh or guard digit required for the single precision instructions, while insuring zeros will appear in the remainder of the output.

The intermediate sum must be examined for lost significance if this sum is not normalized. For this reason, a normalization cycle is taken. Alteration of the exponent and fraction must not occur and, therefore, the shift and decrement amounts are caused to be zero. At the end of this cycle, the intermediate sum has been examined for lost significance and either the significance adjustment or the put-away cycle will follow.

19.3.4 FLOATING POINT COMPARE

This instruction consists of a characteristic comparison, fraction preshift, and the algebraic addition of the operand fractions. The intermediate fraction sum and operand signs are examined to determine the relationship of the two operands.

19.3.4.1 Initial Operand Locations

At the start of the instruction execution, the operands are located as follows:

Instruction Format R1 Operand R2 Operand PR-SP FLP (R1) J 0-31 PR-DP FLP (R1) J 0-63 RX-SP-Even M 0-23, 56-63 J 0-31 RX-SP-Odd M 0-23, 56-63 J 32-63 RX-DP M 0-63 J 0-63

19.3.4.2 instruction Sequencing

The sequencing of this instruction is identical to that of FLP subtract through the fraction addition.

19.3.4.3 Termination

The termination sequence, defined by the PA trigger, includes fraction recomplementation and result testing.

The M register is gated to the Main Adder, complemented if the intermediate sum is complement, and returned to the K and M registers.

The ELC trigger is set if the intermediate sum is in true form or, in the case of a complement sum, after recomplementation; terminating the instruction.

19.3.5 FLOATING POINT LOAD

This instruction is a two-cycle sequence consisting of an operand transfer and a result put-away.

Initial Operand Location

At the start of the instruction execution, the R2 operand is located as follows:

Instruction Format R2 Operand PR-SP J 0-31 RR-DP J 0-63 RX-SP-Even J 0-31 RX-SP-Odd J 32-63 RX-DP J 0-63

instruction Sequencing

Instruction sequencing is controlled by the two triggers listed below, in the order in which they occur:

1ST FLP R2 Transfer ELC Termination

R2 Transfer

The R2 transfer, defined by the 1ST FLP trigger, is a one cycle operation. The R2 fraction is gated from the J register to the Main Adder, shifted L8, and set into the K register. The R2 exponent is gated from the J register to the Exponent Adder, and set into the Exponent register.

Termination

The instruction termination, as defined by the ELC trigger, is a one-cycle put-away. At the end of the R2 transfer cycle, the ELC trigger is set, the result fraction and exponent are set into the FLP (R1) register, and the instruction is terminated.

19.3.6 FLOATING POINT LOAD TYPE

FLP Load and Test-S/D

FLP Load Positive-S/D

FLP Load Negative-S/D

FLP Load Complement-S/D

Introduction

These instructions are two cycle sequences consisting of an operand transfer, with sign modification, and a result put-away. The result fraction and sign are examined to determine their relationship to zero.

Initial Operand Location

At the start of the instruction execution, the R2 operand is located as follows:

Instruction Format R2 Operand PR-SP J 0-31 RR-DP J 0-63

instruction Sequencing

Instruction sequencing is controlled by the two triggers listed below, in the order in which they occur:

1ST FLP R2 Transfer ELC Termination

R2 Transfer

The R2 transfer, defined by the 1ST FLP trigger, is a one cycle operation. The R2 fraction is gated from the J register to the Main Adder, shifted L8, and set into the K register. The R2 exponent is gated from the J register to the Exponent Adder, and set into the Exponent register. The fraction sign is set positive, negative, or inverted, dependent upon the instruction.

Termination

The instruction termination, as defined by the ELC trigger, is a one-cycle put-away. At the completion of the R2 transfer cycle, the ELC trigger is set, the result fraction and exponent are set into the FLP (R1) register and the instruction is terminated.

19.3.7 FLOATING POINT HALVE

This instruction is a two-cycle sequence consisting of an operand transfer, halved by shifting, and a result put-away.

Initial Operand Location

At the start of the instruction execution, the R2 operand is located as follows:

Instruction Format R2 Operand PR-SP M 0-23, 56-63 RR-DP M 0-63

instruction Sequencing

Instruction sequencing is controlled by the two triggers listed below, in the order in which they occur:

1ST FLP Halve ELC Termination

Halve

The Halve cycle, defined by the 1ST FLP trigger, is a one-cycle operation. The R2 fraction is halved by gating the M register "right one" to the Main Adder and returning the result to the K register. The R2 exponent is gated from the J register to the Exponent Adder, and set into the Exponent register.

Termination

The instruction termination, as defined by the ELC trigger, is a one-cycle put-away. At the completion of the Halve cycle, the ELC trigger is set, the result fraction and exponent are set into the FLP (R1) register, and the instruction is terminated.

19.3.8 FLOATING POINT STORE

This instruction is a multiple-cycle sequence consisting of the store preparation, wait cycle and result store.

Initial Operand Location

At the start of the instruction execution, the R1 operand is located as follows:

Instruction Format R1 Operand RX-SP-Even J 0-31 RX-SP-Odd J 0-31 RX-DP J 0-63

instruction Sequencing

Instruction is controlled by the two triggers listed below, in the order in which they occur:

1ST FLP Store Preparation Store Termination

Store Preparation

The R1 operand must be properly positioned in the K register, dependent upon the store address. If the store address is odd, the operand must be placed in the low-order half of the K register.

The R1 operand is gated from the J register, shifted R32 if the store address is odd, and set into the K register.

Termination

The instruction termination, as defined by the Store trigger, is a variable cycle operation dependent upon the "Accept" signal from the Bus Control unit (BCU).

Wait Cycle

If, at the end of the Store Preparation cycle, the Accept signal has not been received, a Wait cycle is taken. Wait cycles are continued until the Accept is received. Gating is not performed during the Wait cycle, and the operand is not modified.

Store

At the completion of either the Store Preparation or a Wait cycle, the ELC trigger is set if the Accept signal has been received. With the ELC trigger ON, the instruction is terminated.

20.0 BINARY OPERATIONS

20.1 BINARY DIVISION

20.1.1 DIVISION METHODS

Let us start by taking a simple example of binary division:

Dividend 0110 0000 Divisor 1010 2's comp Divisor 0110 (a) Restoring 01001 1010)01100000 0000 1100 1010 0100 0000 1000 10000 1010 0110 Remainder (b) Nonrestoring 01001 1010)01100000 0110 11000 1010 00100 1010 10100 1010 11100 1010 0110 Remainder

Example (a) demonstrates division using a simple restoring algorithm. In other words, the dividend is always kept in true form. The divisor is subtracted from the dividend and the result is examined. If the result is true, a one quotient bit is entered and the result becomes the new partial dividend. If the result is complement, a zero quotient bit is entered and the result is discarded. In either case, the position of the partial dividend is shifted left one bit with respect to the divisor and a new subtraction is attempted. This method is basically the one that would be used if the division were to be done longhand.

Example (b) shows the same division problem done using a simple nonrestoring algorithm. In this case, the dividend may be in true or complement form. The divisor is subtracted from the dividend and the result is examined. If the result is true, a one quotient bit is entered; and if the result is complement, a zero quotient bit is entered. In either case, the result of the subtraction becomes the new partial dividend, and the position of this dividend is shifted left one bit with respect to the divisor. The next iteration is identical to the first if the new partial dividend is true. If the new partial dividend is complement, however, the divisor is added to the dividend. Again, if the result is true, a one quotient bit is entered; and if the result is complement, a zero quotient bit is entered. In either case, the result of the subtraction becomes the new partial dividend, and the position of this dividend is shifted left one bit with respect to the divisor. The next iteration is identical to the first if the new partial dividend is true. If the new partial dividend is complement, however, the divisor is added to the dividend. Again, if the result is true, a one quotient bit is entered; and if the result is complement, a zero quotient bit is entered. This can be seen from the fact that shifting the dividend left one bit with respect to the dividend is equivalent to dividing the divisor by two. Thus,

Dividend-Divisor + 1/2Divisor (nonrestoring) is equivalent to

Dividend-1/2 divisor (restoring)

The first two iterations of the example illustrate this, and it is seen that the remainder after the first two iterations is the same for both the restoring and nonrestoring methods.

This simple nonrestoring division algorithm may be speeded up by skipping over zeros, and ones. Subtractions need only to be performed in those positions in which the quotient cannot be predicted. If the divisor is bit normalized (of the form 1xxx) and a true dividend has a high-order zero, then a subtraction of the divisor from the dividend would always yield a complement result with a corresponding zero quotient bit. Thus, in example (b) the leading zero of the dividend could have been shifted without a subtraction and a zero entered as the first quotient bit. Likewise, if the dividend is complement with a high-order one bit, the addition of a bit normalized divisor will always yield a true result with a corresponding one quotient bit. More than one high-order bits can be shifted over if quotient bits can be predicted for each dividend bit that is shifted. For example, if a true dividend had three high-order zeros, a shift of three bits could be taken before the subtraction, since a subtraction of a bit normalized divisor from any of the dividend positions containing zeros would always yield a complement result.

It is obvious that if the divisor and the dividend are close together in absolute magnitude, then a subtraction of the divisor from the dividend would yield a large number of leading partial dividend bits that can be skipped. One way to accomplish this is to generate multiples of the divisor and subtract these multiples from the dividend instead of subtracting the divisor itself. The specific multiples to subtract are chosen to give the maximum amount of shift. For example, if the dividend were 1000x--x and the divisor were 1111x--x, simple decoding would show that a greater shift would be developed if one-half times rather than one times the divisor were subtracted from the dividend.

All of the techniques mentioned above are aimed at increasing the average number of shifts that are developed per subtraction. To take maximum advantage of these methods, the dividend must be passed through a variable shifter before each pass through the adder. The approach taken by said environmental system is to use a divide method which will guarantee at least an allowable shift of two. Under certain circumstances, the result of an addition would allow a shift of more than two to be taken, but no attempt is made to take advantage of this. Thus, a uniform shift of two bits can be taken each iteration and there is no need to pass the dividend through a variable shifter during the divide iteration.

The division method used in said environmental system will be explained in three parts. The first will be concerned with the development of a divide scheme that will allow a uniform shift of two. The second part will cover the procedure for positioning of the operands, and the third will cover divide termination.

20.1.2 DIVISION WITH UNIFORM SHIFT OF TWO BITS

One requirement for a two-bit divide scheme is that each iteration develop at least two high-order zeros if the result is true, or two high-order ones if the result is complement. Thus, the result of any iteration must have an absolute value of less than one-fourth. All possible combinations of the four high-order bits of a true dividend are listed at the left and all possible combinations of the three high-order bits of the divisor are listed across the top. Within the table (expressed in 60/40 is shown the range of the result obtained when the divisor is subtracted from the dividend. For example, take a dividend whose high-order four bits are 1010. This dividend can represent a value ranging from equal to or greater than 40/64 to less than 14/64 depending on the lower order bits. In like manner, a divisor whose high-order three bits are 101 represents a value ranging from equal to or greater than 40/64 to less than 48/64. Thus this dividend and a divisor can be expressed as follows:

40/64 Dividend<44/64

40/64 Divisor<48/64

It can be shown that the range of the result obtained by subtracting the divisor from the dividend is:

(40/64)- (48/64)<R<(44/64)- (40/64) or -(8/64)<R<+(4/64)

Thus, this particular dividend and divisor combination satisfies the requirement that the result be less than one-fourth. The heavy line encloses all combinations of dividend and divisor whose result lies entirely within the allowable range.

To obtain a uniform shift of two, an additional requirement must be met. For every multiple selected, it must be possible to predict at least two quotient bits. The one-fourth and five-fourths multiples are not used in the two-bit divide.

If the 1 times multiple is subtracted from a true dividend and the result is true, the first quotient bit must be a one. The result of this subtraction is less than one-fourth. The divisor is always greater or equal to one-half, since it has been normalized. Therefore, a further subtraction of one-half times the divisor from the dividend would always yield a complement result, and the second quotient bit will be a zero. If the result is complement, the first quotient bit must be a zero. However, if the 1 times multiple produced a complement result, an addition of one-half times the divisor to that result would have returned the partial dividend true, since the result is greater than - (1/4) and one-half times the divisor is greater than one-fourth

if -1/4<R<0 and M<1/4

then R + M<0

Thus, the second quotient bit is a one.

By the same reasoning, it can be shown that with a true dividend, the 1/2-times multiple is only selected when the use of the 1 times multiple would have yielded a complement result. Thus, the first quotient bit is always a zero and the second quotient bit is a one if the result is true and a zero if the result is complement. Likewise, with a true dividend, the 3/2 multiple is only selected when the use of the 1 times multiple would have yielded a true result. Thus, a first quotient bit is a one. The second quotient bit is then a one or a zero depending on whether the use of the 3/2 times multiple produces a true or complement result.

The use of the 3/4-times multiple with a true dividend has been restricted to cases where the use of the 1 times multiple would have produced a complement result, and the use of the 1/2-times multiple would have produced a true result. Therefore, the first two quotient bits are 01. In addition the 3/4-times multiple produces a third quotient bit which is a one if the result is true and 1 zero if the result is complement. This third quotient bit is a valid bit and thus must be used instead of the first quotient bit developed on the next iteration.

If a zero multiple is chosen, the dividend will not change and the quotient bits will be 00 since a subtraction of either one times or one-half times the divisor from a true dividend would produce a complement result. The quotient prediction for the addition of a true multiple to a complement dividend can be developed in the same manner as above and the results are tabulated. The actual circuitry and gates used to generate the divisor multiples will be covered later.

20.1.3 DIVIDE POSITIONING

The following general comments apply to both fixed and floating point division. The divisor (R2) is first brought into J if RX or M if RR. The divisor is then hex-normalized, and placed in K and L. 3/2 times the divisor is generated by adding K plus L shifted R1 and placed in L. The dividend (R1) is now brought into M, shifted the proper amount and swapped with K. Now the dividend is in K, the divisor is in M and three-halves times the divisor in L. The straight gates from M and L to the adder give the 1X and 3/2X multiples respectively and the right one gates from M and L give the one-half and three-quarters multiples. The OX multiple is obtained by gating no data to the T/C side of the adder.

The J register is used to accumulate the quotient. Every second iteration J is shifted left four bits through the RBL to provide space for new quotient bits to be inserted.

The divide method has been developed assuming a bit normalized divisor. Since the divisor has only been hex-normalized, some adjustment must be made for the high-order bit zero's in the divisor. During the time that the divisor is in K, the high-order eight bits are transferred via the decimal gates to DB and DC. The high-order bit zero's of the divisor are decoded from DB and the divisor and dividend bits gated into the divide decoding are adjusted accordingly. This accomplishes the same operation as bit normalizing the divisor and bit shifting the dividend the same amount. The shift counter is set to the number of iterations to be taken.

A FLP divide

An RX FLP divisor is converted to the working format in the usual manner so that the FLP operands are lined up with the high order end of the adder. The divisor exponent is transferred to the exponent register and adjusted for the divisor normalization. As the dividend is brought into M, the ER is subtracted from the dividend exponent and placed in the ER and the ER is then adjusted for the dividend normalization. This results in the expected quotient exponent in the ER This expected exponent may have to be adjusted by one if the dividend is larger than the divisor. This is detected in two ways. First, the hex-normalized dividend high-order bit zeros are compared to the divisor high-order bit zeros. If the dividend bit zeros are less, the ER is adjusted and the dividend is shifted right four bits to make the fraction smaller than the divisor. In this case the ER is adjusted by one and the number of divide iteration cycles to be taken is reduced by 2. This results not only in the correct quotient exponent but also guarantees that the quotient developed will be hex-normalized.

B FIX Divide

Fixed point division is done with true operands only. Thus both the divisor and the dividend must be 2's complemented if they are negative. Both the quotient and the remainder are developed in true form and must be complemented if they are negative.

The fixed divisor is hex-normalized in the same manner as in FLP divide, except that the normalization amount is accumulated in the SC. The dividend is then hex shifted by the amount in the SC. Any one bit shifted off the left end of the dividend is a divide check. Fewer high-order bit zeros in the dividend than the divisor is also a divide check. The first two quotient bits developed are examined. A divide check is indicated if the first quotient bit is a one, or if the second quotient bit is a one except if the quotient will be maximum negative number. This can be predicted by second quotient bits = 1, quotient negative, and result of the first iteration all zeros.

20.1.4 DIVIDE TERMINATION

The divide iteration for FIX and FLP is identical. At least two quotient bits are developed each cycle and inserted into the low-order end of J. Every other iteration the quotient that has been developed thus far is shifted left four bits through the RBL. This continues until the required number of iterations has been taken. If the last iteration did not involve the use of a 3/4X divisor multiple, one more quotient bit must be developed.

In FLP divide no remainder is developed, so that as soon as all quotient bits have been developed, the quotient is transferred from J to K and put away in the FLP registers. During the put away cycle, the checks are made for exponent overflow, exponent underflow, and lost significance traps. A divide check trap would have been detected early in the instruction by zero detecting the divisor.

In FIX divide a remainder must be developed. If the original dividend were negative the remainder must be 2's complemented. If the quotient is negative, it must also be 2's complemented. The remainder and quotient are swapped and the quotient is put away in R1. On the next cycle, the remainder is put away in R1 + 1.

20.2 FIXED AND FLOATING POINT MULTIPLICATION

20.2.1 BINARY MULTIPLICATION

Floating Point Multiplication in said environmental system consists of the addition of exponents and the multiplication of fractions. The fractions being either single precision or double precision. Said environmental system also incorporates Fixed Point Multiplication. The integer field of a fixed point operand is either a word or a half word. For the case where a half word is specified, the half word is expanded to a full word before multiplication.

Multiplication consists of the repetitive addition of the multiplicand to itself the number of times specified by the multiplier. A partial product is obtained by using each digit of the multiplier as a separate multiplier. The partial products are offset according to the position of the multiplier digit used with respect to the total multiplier and added together to obtain the product. Binary multiplication is performed in the same manner with the multiplier digit or bit being a one or a zero. This requires an addition for each bit in the multiplier. In the method of multiply as used in said environmental system, the multiplier and the partial product are shifted four bits for each iteration; the multiplier with respect to the multiplier decoding and the partial product with respect to the multiplicand. The multiply operation is started at the low-order end of the multiplier. Whether Floating Point Multiply or Fixed Point Multiply is specified, the method is the same.

Consider part of the multiplier to be:

Xxxx0110010101000011xxxx

this multiplier can be separated into hexadecimal groups:

-6 +5 +4 +3 __________________________________________________________________________ XXXX 0110 0101 0100 0011 XXXX

with this decoding, a product could be obtained by adding three times the multiplicand, shifting the partial product four positions right and adding four times the multiplicand, shifting this new partial product four positions right and adding five times the multiplicand, and then shifting this new partial product four positions right and adding six times the multiplicand. Thus, if 16 multiples of the multiplicand were available, it would require only one addition to take care of four multiplier bits.

In the binary number system, the two times, four times, eight times and 16 times multiples are easily obtained by shifting the multiplicand. The digit normalized multiplicand is defined as the 16 times multiple. The eight times multiple is therefore the 16 times multiple shifted right one. The four times multiple is the 16 times multiple shifted right two, and the two times multiple is the 16 times multiple shifted right three. If all the even multiples of the multiplicand were provided, the hexadecimal groups of the multiplier could use only the even multiples and then the one times multiple could be subtracted when an odd multiple was actually required.

Consider again, the above part of a multiplier. Through the use of only even multiples of the multiplicand and the one times multiple subtraction, a product could be obtained from four additions and two subtractions. For the +3 hexadecimal group the four times multiple would be added and then the one times multiple subtracted. The partial product shifted four positions right and the four times multiple added for the +4 hexadecimal group. This new partial product again shifted four positions right and the six times multiple added and then the one times multiple subtracted for the +5 hexadecimal group. Finally this new partial product shifted four positions right and the six times multiple added for the +6 hexadecimal group. Thus the number of multiples needed is reduced but the number of operations required to obtain a product is increased.

Consider now the hexadecimal 5 group of the multiplier in conjunction with the hexadecimal 4 group. The low-order bit position in the hexadecimal 5 group is the position which determines whether or not the group hexadecimal number is odd. If this position contains a one bit, the number is odd which means that the one times multiple must be subtracted from the partial product to compensate for the higher even multiple which was used in that hexadecimal group. The one bit in this position has a one times multiple value with respect to the hexadecimal 5 group. This same bit position with respect to the hexadecimal 4 group has a 16 times multiple value. Thus subtraction of the one times multiple in the hexadecimal 5 group is the same as subtraction of the 16 times multiple in the hexadecimal 4 group. The original procedure for the hexadecimal 4 and hexadecimal 5 groups in the multiplication was to add the four times multiple to the partial product in the hexadecimal 4 group, shift the new partial product four positions right and add the six times multiple and then subtract the one times multiple. The same result is obtained by adding the four times multiple to the partial product and then subtracting the 16 times multiple for the hexadecimal 4 group. Then shifting the new partial product four positions right and adding the six times multiple for the hexadecimal 5 group; adding the four times multiple and then subtracting the 16 times multiple is the same as subtracting the 12 times multiple. Therefore, the same result is obtained by subtracting the 12 times multiple for the hexidecimal 4 group, shifting the new partial product four positions right, and then adding the six times multiple for the hexadecimal 5 group.

Correction is thus made to a partial product for an overmultiplication before the overmultiplication occurs. Consider once again the original example of part of a multiplier. It requires five bits to be decoded to obtain a hexadecimal group multiple. Correction before overmultiplication is possible for all hexadecimal groups of the multiplier except the low-order group. When the low-order hexidecimal group contains an odd number, it is decoded as though the low-order bit of the group were a zero and the one times multiple is added for that group. In all other groups, correction is taken care of automatically through the decoding of five bits and the resultant use of complements of the existing even multiples.

The multiplier group decoding for this method of multiply is such that five bits of multiplier are examined to determine the multiple to be used. The four low-order bits of the five-bit group need not be looked at again. The high-order bit of this group is the low-order bit of the next multiplier group.

Since in the binary number system, the two times, four times, eight times, and 16 times multiples are easily obtained by bit shifting the multiplicand, the six times, 10 times, 12 times and the 14 times multiples must somehow be obtained so that all of the even multiples are available. The 12 times multiple is generated by subtracting the four times multiple from the 16 times multiple. The six times multiple is then the 12 times multiple shifted right one. When the 10 times or 14 times multiples are decoded, the two times or six times multiples are used and the iteration sequence is interrupted to allow the eight times multiple to be added to or subtracted from the partial product. Thus, two additions or subtractions are required to handle four bits of multiplier when the 10 times or 14 times multiple is decoded. ---------------------------------------------------------------------------

Desired 1st 2nd Multiplier Multiple Cycle Cycle __________________________________________________________________________ 00000 + 0 + 0 00001 + 1 + 2 00010 + 2 + 2 00011 + 3 + 4 00100 + 4 + 4 00101 + 5 + 6 00110 + 6 + 6 00111 + 7 + 8 01000 + 8 + 8 01001 + 9 + 2 + 8 01010 + 10 + 2 + 8 01011 + 11 + 12 01100 + 12 + 12 01101 + 13 + 6 + 8 01110 + 14 + 6 + 8 01111 + 15 + 16 __________________________________________________________________________ ---------------------------------------------------------------------------

Desired 1st 2nd Multiplier Multiple Cycle Cycle __________________________________________________________________________ 10000 - 16+ 0= -- 16 10001 - 16+ 1= -- 6 - 8 10010 - 16+ 2= -- 6 - 8 1011 - 16+ 3= -- 12 10100 - 16+ 4= -- 12 10101 - 16+ 5= -- 2 - 8 10110 - 16+ 6= -- 2 - 8 10111 - 16+ 7= -- 8 11000 - 16+ 8= -- 8 11001 - 16+ 9= -- 6 11010 - 16+ 10= - 6 - 6 11011 - 16+ 11= - 5 - 4 11100 - 16+ 12= - 4 - 4 11101 - 16+ 13= - 3 - 2 11110 - 16- + 14= - 2 - 2 11111 - 16+ 15= - 1 - 0 __________________________________________________________________________

After any addition or subtraction, the partial product will be either correct or the one times multiple less than the correct partial product. The one times multiple less being with respect to the multiplier group for the next addition or subtraction. When the first multiplier group is decoded, the low-order bit being a one or a zero is decoded as a zero. If it is a 1 bit, the one times multiple is gated to the true input of the main adder instead of the partial product which at this time would be zero. Thus, for the first five-bit multiplier group decoding, if the group is 0XXX0 or 0XXX1 the partial product will be correct. If the multiplier group is 1XXX0 or 1XXX1, the partial product will be the one times multiple less than the correct partial product. For multiplier group decoding other than the first time, the partial product will be correct if the group is 0XXX0 or 0XXX1. Although the multiplier group 0XXX1 is decoded as the one times multiple greater than the group multiple, the low-order one bit of this group means that after the previous subtraction which resulted from this bit being the high-order bit of the previous multiplier group, the partial product was the one times multiple less than the correct partial product. Thus, the partial product will now be correct. For the multiplier group 1XXX0 and not the first group decoding, the partial product is again the one times multiple less than the correct partial product. The multiplier group 1XXX1 produces a partial product that is also the one times multiple less than the correct partial product. This is because the low-order 1 bit of this multiplier group when decoded with the previous multiplier group had produced a partial product which was the one time multiple less than the correct partial product. Now this low-order 1 bit decodes a multiple which is the one times multiple greater than the correct multiple. However, the high-order 1 bit of this multiplier group produces a partial product which is the one times multiple less than the correct partial product. Thus for the multiplier group 1XXX1, the partial product remains the one times multiple less than the correct partial product. The decoded multiple is either added to or subtracted from the partial product depending only on whether the high-order bit of the five-bit multiplier group is a zero of a 1 bit respectively.

20.2.2 FIXED POINT MULTIPLY (MR-M-MH)

Fixed Point Multiply starts with the transfer of the for the MR and M instructions and to M register positions 0 to 31 for the MH instruction. During the first Fixed Point Multiply cycle, identified by the 1ST FXP trigger being on, the multiplicand is transferred from the M register through the main adder to K register positions 0 to 31 and to M register positions 0 to 31. Also during this cycle the multiplier is transferred from the RBL to J register positions 32 to 63 for the MR instruction. For the M instruction this cycle is held up until the J register is loaded from storage. For the case of the MH instruction, the half word from storage is expanded to a full word and placed in J register positions 0 to 31 prior to the start of Fixed Point Multiply.

The next Fixed Point Multiply cycle, identified by the Iteration preparation trigger being on, is the first preparation cycle for the multiply iterations. The 12 times multiple of the multiplicand is generated by gating M register positions 0 to 61 R2 (four times multiple) to the T/C input of the main adder and K register positions 0 to 63 straight (16 times multiple) to the other main adder input. The MA hot one trigger is set and the T/C input selected complement. The AOB (12 times multiple) is gated to the L register. The low-order group of the multiplier is gated to the multiplier decoding. The multiplier group is either J register positions 27 to 31 if the instruction is MH or M with an even address or J register positions 59 to 63 if the instruction is MR or M with an odd address. To position the multiplier for the next multiplier group the J register positions 0 to 63 are gated L4 to the RBL and then the RBL positions -4 to 55 are gated R8 back to the J register. The shift counter, used as an iteration counter, is set to 8 for the number of multiplier digits. The multiplier shifting and the iteration count for both Fixed Point Multiply and Floating Point Multiply are shown hereinbefore. Also during the first iteration preparation cycle, the J register positions 0 to 31 or 32 to 63 and the K register positions 0 to 63 are zero detected to determine if either the multiplier or the multiplicand are zero which means that a zero product will result. J register positions 0 to 31 are zero detected for the MH instruction and the M instruction with an even address. Positions 32 to 63 are zero detected for M with an odd address and for the MR instruction. If the K register (multiplicand) is zero, the Put-Away 1 trigger is turned on. During this cycle, K register positions 0 to 31 are put in the general registers and M register positions 32 to 63 are gated to T/C input positions 0 to 31 of the main adder and the AOB gated to the K register. Then the ELC (E Last Cycle) trigger is set, and K register positions 0 to 31 are put in the general registers. If the J register (multiplier) is zero, the Test Cycle trigger is turned on. During this cycle, both the K register and the M register are set to zero by forcing parity to both inputs of the main adder and gating the AOB to them. Then the Put-Away 1 trigger is set and the sequence is the same as for a zero multiplicand.

When a multiplier group is gated to the multiplier decoding, an M register or l register gating trigger is set which gates the decoded multiple of the multiplicand to the T/C input of the main adder during the next cycle. Whether the true of complement gate of the T/C input is selected depends on whether the high-order bit of the multiplier group was a 0 bit or a 1 bit respectively. The MA hot one trigger is also set if the complement gate is selected. The Iteration trigger being on identifies the cycle in which a decoded multiple is being added to or subtracted from the partial product. K register positions 0 to 63 (partial product) are gated R4 to the other input of the main adder and the AOB which is the new partial product is gated to the K register. The first time the iteration trigger is on, the K register contains the 16 times multiple rather than the partial product. Thus, the K register is gated R4 to the main adder during the first iteration cycle only if the low-order bit of the low-order multiplier group is a 1 bit. When a two cycle multiple is decoded, the Iteration Preparation trigger is turned off so that the next multiple is not decoded until the two times multiple or the six times multiple is added to or subtracted from the partial product. Then the Add trigger is turned on which identifies the cycle in which the eight times multiple is added to or subtracted from the partial product. During the add cycle, M register positions 0 to 62 are gated R1 (eight times multiple) to the T/C input of the main adder and K register positions 0 to 63 are gated straight (partial product plus or minus the two times or six times multiple) to the other input of the main adder. The result (new partial product) is gated to the K register. If the multiplicand is a complement number, one bits must be inserted at the high-order positions of the main adder T/C input which are vacated due to the multiple generation. If the multiplier is a complement number, the last multiplier group must be decoded as though the high-order bit of the group is a 1 bit.

Thus, the multiply iteration is identified by three different triggers. The Iteration trigger which identifies the cycles in which the decoded multiple is being added to or subtracted from the partial product; the Add trigger which identifies the cycles in which the eight times multiple is being added to or subtracted from the partial product; and the Iteration Preparation trigger which identifies the cycles in which the multiplier group is being gated to the multiplier decoding; the multiplier is being shifted R4 with respect to the multiplier decoding, and the shift counter is being decremented and used as an iteration count.

20.2.3 FIXED POINT PUT-AWAY

When the shift counter is equal to a value of one, the last multiply iteration is being executed. At the end of this cycle the partial product which is now the complete product is put into both the K register and the M register. The Put-Away 1 trigger is set and K register positions 0 to 31 are put into the general registers if the instruction is M or MR. If the instruction is MH no put-away is done this cycle. M register positions 32 to 63 are gated to the main adder T/C input positions 0 to 31 and the AOB is gated to the K register. Then the ELC trigger is set, and K register positions 0 to 31 are put into the general registers for instructions M, MR, and MH.

20.2.4 FLOATING POINT MULTIPLY (MER, ME, MDR, MD)

Floating Point Multiply starts with the transfer of the multiplicand from the RBL to the M register. M register positions 56 to 63 will contain the exponent. A single precision floating point fraction will be contained in M register positions 0 to 23 and a double precision floating point fraction in M register positions 0 to 55. Since a normalized product must be obtained, the multiplicand is digit prenormalized. The multiplier is not prenormalized but is decoded only until the remaining multiplier groups are zero. This produces the same result as a normalized multiplier.

20.2.5 FLOATING POINT MULTIPLY PRENORMALIZATION

In the first FLP multiply cycle, identified by the 1st FLP trigger being on, M register positions 0 to 55 are transferred through the main adder to both the K register and the M register. M register positions 56 to 63 are transferred through the exponent adder to the exponent register. The M norm trigger being on sets up a shift of 0, L4, or L8 depending on whether the multiplicand has 0, 1, or 2 leading zero digits. It also allows 0, 1, or 2 to be subtracted from the exponent when it is transferred from the M register through the exponent adder to the exponent register. Also during the first FLP multiply cycle, the multiplier is transferred from the RBL with a right ring shift of eight to the J register if the instruction is MER or MDR. If the instruction is ME or MD this first cycle is held up until J is loaded from storage. A single precision floating point multiplier fraction will be contained in J register positions 8 to 31 and the exponent in J register positions 0 to 7 for the MER instruction and the ME instruction with an even address. The multiplier fraction for an ME instruction with an odd address will be in J register position 40 to 63 with its exponent in positions 32 to 39. A double precision floating point multiplier fraction will be in J register positions 8 to 63 with its exponent in positions 0 to 7.

The next FLP multiply cycle will be either another prenormalization cycle identified by the 1st FLP trigger being on or it will be the first preparation cycle for the multiply iteration identified by the Iteration Preparation trigger being on. It will be a prenormalization cycle if the M register is not normalized. The K register positions 0 to 63 will be a zero detected to determine if the multiplicand is zero. If it is not zero, prenormalization cycles will occur until the multiplicand is normalized. If the multiplicand is zero, the Test Cycle trigger will be turned on and the exponent register will be made zero during the third cycle. Then the ELC trigger will be turned on and the zero product put into the floating point register during the fourth cycle. The product fraction from K register positions 0 to 55 and the product exponent from the exponent register.

20.2.6 FLOATING POINT MULTIPLY FIRST ITERATION PREPARATION CYCLE

After the multiplicand is normalized, the Iteration Preparation trigger is turned on. During this cycle, the operand exponents are added together; the 12 times multiple is generated; the low-order multiplier group is decoded; the multiplier is gated to the RBL and back to the J register in an effective R4 shift; the multiplier fraction in the J register is zero detected to determine if the multiplier is zero; and the shift counter is set up for use as an iteration count. The exponent sum less 64 is obtained by transferring the exponent register to the T/C input of the exponent adder and the multiplier exponent to the other input. The multiplier exponent from the J register will be positions 0 to 7 for instructions MER, MDR, MD, and ME with an even address. For an ME instruction with an odd address, the multiplier exponent will be in J register positions 32 to 39. Since the operand exponents are excess 64 numbers, the AEOB position 1 is complemented to produce the exponent sum less 64. The exponent sum is placed in the exponent register. The 12 times multiple is generated by gating the M register positions 0 to 61 R2 to the T/C input of the main adder and by gating the K register positions 0 to 63 to the other input. The MA hot one trigger is set, and the T/C input is selected complement so that the M register gated R2 (four times multiple) is subtracted from the K register gated straight (16 times multiple). The difference (12 times multiple) is placed into L register positions 0 to 63. The low-order multiplier group is gated to the multiplier decoding which selects a multiple gating trigger. The gating trigger gates the decoded multiple to the main adder the next cycle. The multiplier group is in J register positions 27 to 31 for instructions MER and ME with an even address and positions 59 to 63 for instructions ME with an odd address, MD and MDR. The low-order multiplier group is decoded as though the low-order bit of the group is a zero. If it is a one bit the K register positions 0 to 59 are gated R4 (one times multiple) to the main adder the next cycle. To shift the multiplier R4 with respect to the multiplier decoding, J register positions 8 to 63 are gated L4 to the RBL for instructions ME with an even address, MD, MER, and MDR. J register positions 40 to 63 are gated to the RBL L4 for the ME instruction with an odd address. RBL register positions +4 to 55 are gated back to the J register R8. The shift counter is set to a value of 6 for a single precision multiply and to 14 for a double precision multiply. For each multiply iteration, the shift counter is decreased by one. Also during the first iteration preparation cycle, the multiplier fraction is zero detected to determine if the multiplier is zero. J register positions 8 to 31 are zero detected for the MER instruction and the ME instruction with an even address. Positions 8 to 63 for the MDR and MD instructions and positions 40 to 63 for the ME instruction with an odd address. If the multiplier is zero, a zero product will result and the Test Cycle trigger will be set. The K register and the exponent register are made zero and then the ELC trigger is turned on and the zero product put into the floating point register. If the multiplier is not zero, the Iteration Preparation trigger will be set again along with the Iteration trigger which identifies the cycle in which the first multiply iteration occurs.

20.2.7 FLOATING POINT MULTIPLY ITERATION

The Floating Point Multiply Iteration is identical in method to the Fixed Point Multiply Iteration. The decoded multiple is gated from the M register or the L register to the T/C input of the main adder and K register positions 0 to 59 (partial product) are gated R4 to the other main adder input when the Iteration trigger is on. M register positions 0 to 63 are gated R1 (eight times multiple) to the T/C input of the main adder and K register positions 0 to 59 are gated straight (partial product plus or minus the two times or six times multiple) to the other main adder input when the ADD trigger is on. The multiplier group is gated to the multiplier decoding, the multiplier is gated from the J register to the RBL and back to the J register in an effective R4 shift, the multiplier is zero detected so that the multiplier groups are decoded only until the remaining groups are zero, and the shift counter is being decreased by one when the Iteration Preparation trigger is on.

20.2.8 FLOATING POINT MULTIPLY PUT AWAY

During the iteration preparation cycle in which the remaining multiplier groups are detected as being zero, the last multiply iteration is taking place and either the Iteration trigger or the Add trigger will be on along with the Iteration preparation trigger. At the end of this cycle, the partial product which is now the complete product is gated to both the K register positions 0 to 63 and the M register positions 0 to 63. The product may have one leading zero digit thus being unnormalized because the multiplicand was digit normalized but not bit normalized and the last nonzero multiplier group may have had leading zero bits. The shift counter may or may not be equal to zero. If it is not zero, it contains a value equal to the number of leading zero digits that were in the multiplier fraction since it was originally set to a value equal to the total number of multiplier digits. The Put-Away 1 trigger is set and K register positions 0 to 55 (product fraction) and the exponent register (product exponent) are put into the floating point register. However, the product is not valid if the product fraction is unnormalized or the shift counter is not equal to zero. If the fraction is unnormalized, M register positions 0 to 55 are gated to the T/C input of the main adder, the L4 shift is selected, and the AOB is gated to both the K register positions 0 to 63 and the M register positions 0 to 63. The shift counter is gated to the T/C input of the exponent adder and the exponent register (product exponent) is gated to the other input. The T/C input is selected complement and the AE hot one trigger is set so that the shift counter is subtracted from the exponent register. The AEOB position 1 is complemented because exponents and floating point multiply shift counter values are excess 64 numbers and the result is put into the exponent register. The AE hot one trigger is not set if the product fraction is unnormalized. This reduces the product exponent by the shift counter value plus one. The shift counter is set to zero with the next A sample. The Put-Away 1 trigger is set again with the same sample along with the ELC trigger and the product fraction and exponent are put into the floating point register.

If an exponent underflow occurs, the ELC trigger is not turned on with the Put-Away 1 trigger. The Test Cycle trigger is set which indicates that the K register (product fraction) and the exponent register (product exponent) are being set to zero. The ELC trigger is then set, and the zero product is put away.

20.3 MULTIPLE LOAD EXECUTIONS

Multiple Load is one of the instructions that is executed simultaneously in both IE and E units. In this respect, timing becomes an extremely important criterion in designing the logic.

A storage word (bits 0-63) fetched from storage is set into the J register. From the J register, either bits 0-31 or bits 32-63 are gated through the main adder and set into the left half of the K register (0-31). Finally, the proper GR is loaded with K register bits 0-31.

Like other fixed point instructions, the first sequence trigger to be turned on in the E unit is the 1ST FXP TGR, which will stay on until the 1ST FXP LCH comes on in response to the J LOADED TGR. During the 1ST FXP cycle (or cycles), J (0-31) to MA T/c C (0-31) gate is open if H bit 21 is 0 J (32-63) to MA T/C (0-31) gate is open if H bit 21 is 1 . The next sequence trigger to be turned on will be the EM2 trigger if H bit 21 is 0 (it will be the EM1 trigger if H bit 21 is 1). Gate J (32-63) to MA T/C (0-31) is open for EM2 cycles, and gate J (0-31) to MA T/C (0-31) is open for EM1 cycles. During the process of loading the general registers, EM1 and EM2 triggers alternate. The latched outputs of the EM1 and EM2 triggers control gating AMOB to the K REG at A clock, and the following early B clock sets the data into the designated GR. The only exception is for the E last cycle. The put away trigger for this cycle is blocked. ER 1 is stepped up by one every time the GR is loaded. When ER 1 is equal to IR2 the compare latch will be up and the next cycle will be the E last cycle.

The following items deserve some special attention:

1. EM1 trigger stays on for two cycles except the cycle before the E last cycle. This is because E unit has to wait for the word to come back from memory. In single-cycle cases, EM1 will stays on for three cycles because I unit will not make a fetch request at the end of the IM2 cycle. EM2 trigger in all cases stays on for only one cycle and is turned off by EM2 LCH.

2. Since J LOADED TGR is conditioned with A running clock, in cases of single cycle operation accept trigger (conditioned with a control clock) has to be used to replace the J LOADED TGR in all applications.

3. If the cycle before the ELC is EM2 cycle, then incrementing ER 1 is not blocked even after the compare latch line is up. In this case, at the end of the execution, ER1 will always be one greater than IR2. However, if the cycle before the ELC is the EM1 cycle, then there will be no increment for ER 1 Except in the case of single cycle and loading only one register, at the end of execution, ER 1 is 1 greater than IR2.

20.3.1 TIMER UPDATE

In the environmental system, the timer consists of a full (32 bits) word in the Main Storage location 80. The Initial Timer word is set by the program. The word is counted down at the rate of 50 or 60 cycles per second, depending on the line frequency. An External Interruption condition is signaled when the value of the timer word goes from positive to negative. The subtraction is done in the fixed-point arithmetic in the E unit.

The data flow path for timer updating is in the E unit. The timer word fetched from storage is set into the J register. Since the timer word is stored in the storage with even address, it always appears in the left half of the J register. At the same time as the word is transferred to the left half of the M register from the J register through the Main Adder, a ONE is forced into bit positions 53 and 55 of the M register if the line frequency is 60 c.p.s. (one is forced into bit positions 53 and 54 of the M register if the line frequency is 50 c.p.s. The subtraction M 0-31 thru M 32-63) is done next in the Main Adder, and the result is set into the K register. From the K register, the new timer word is restored into the Main Storage location 80.

21.0 MANUAL CONTROLS AND MAINTENANCE

The manual controls and maintenance sections of said environmental system are contained within the bus control unit which is shown in FIG. 812 through FIG. 858. The power distribution unit comprises several functional portions, a first portion being the control panel itself which includes switches and indicator lights, another section including the start and stop control circuits along with the reset circuits, another section including miscellaneous functional hardware, and a final section including the maintenance control word portion which provides functional controls and data flow for the diagnostic analysis of said system. Another main portion of the power distribution unit comprises fault locating test controls, which are now shown in detail herein, but are referred to only as a block at the top of FIG. 855.

21.1 CONTROL PANEL FIG. 812 THROUGH FIG. 820

In FIG. 812, the general layout of a control panel which may be utilized in said environmental system is shown. This has the various indicators broken down into groups, and includes three main sections of controls for engineering and fault locating tests, for operator intervention, and for operator control. As illustrated in FIG. 816, the system may also include an operator console which is remote from the CPU itself. Thus, the CPU as shown in FIG. 1 contains the control panel shown in FIG. 812, and the operator console (not shown other than in FIG. 816 herein) would have the same configuration as the operator control portion shown in the lower right-hand part of the control panel of FIG. 812. The operator console would not have the remaining functions of the control panel.

In the control panel, a plurality of switches, such as lever switches, provide certain selectable static functions by the movement thereof, and the rotary type selector switches are also utilized for static functions. In addition, a plurality of pushbuttons are provided for momentary actuation of functions which are latched elsewhere in said system.

21.2 PUSHBUTTON NETWORK FIG. 821

In FIG. 821, the normally closed normally open contacts of all of the pushbuttons are applied to a single pulse-shaping circuit which provides correct pushbutton output pulses for use throughout the system. Each of the normally closed contacts is applied to an OR circuit, the output of which will reset a latch. The latch is a set dominant latch, so that the presence of a setting signal will always provide an output from the latch even though there is an output from the OR-circuit 1. Each of the normally closed contacts is also applied to an inverter, such that when that switch has operated, there will be an output from the inverter to energize a respectfully corresponding AND circuit. The other input to each of the AND circuits is from a 350-nanosecond single shot which is fired by the latch. The input to the latch is a single integrating network which can be fed by any one of the normally open contacts. The sorting out of which normally open contacts has become closed is effected by means of the inverters connected to the related normally closed contacts. Therefore, the circuit of FIG. 821 provides an integrating and shaping function for all of the pushbuttons in a system with but a single integrater and a single singleshot, together with corresponding inverters and AND circuits for each of the switches.

21.3 INDICATOR CONTROL NETWORK FIG. 815

In FIG. 815 is shown an indicator control network which provides power to light an indicator lamp, as well as to test the lamp without disturbing the logic to which the lamp is connected. The circuit of FIG. 815 is utilized by a plurality of different functions as indicated in FIG. 814. FIG. 814 is merely illustrative of a large number of indicator lights (referred to as INDS) in FIG. 812.

In FIG. 815, a pair of resistors provide voltage division from some logical function (such as PSW 14), the logical function also being applied to other areas in the system. In other words, the indicator network of FIG. 815 is connected in parallel with logical circuits which utilize the function being monitored by the indicator network. The voltage divider applies a potential of the functional line (such as PSW 14) to the cathode of a diode as well as to a lamp. The other side of the lamp may be connected to a positive voltage or to a negative voltage, and correspondingly, the anode of the diode may be connected to a positive voltage or to ground. Thus, in a quiescent state, a small amount of current is passed through the lamp so as to avoid glow-resistant shock when the lamp is actually illuminated with a larger amount of current. The diode provides voltage clamping so that the potential across the lamp can be maintained at a guaranteed amount. Whenever the logic line goes negative, then the voltage drop across the lamp is greater, so that an illuminating current will flow therethrough.

When a lamp is to be tested, the switch is thrown so as to connect the anode of the diode to ground and so as to connect the other side of the lamp to a minus potential. This permits flow of a test current through the lamp, which, however, is buffered from the logic line by the voltage divider.

21.4 THE STARTING STOPPING AND RESET CIRCUITS FIG. 822-FIG. 829

In FIGS. 822 through 829 are shown signals which cause the machine to start in response to the start pushbutton, the starting of the system including the generation of a sequence of different reset signals as shown in FIG. 827. The actual start circuit, and the control for single-cycling is shown in FIG. 822. The circuit of FIG. 823 provides a signal to the main clock (in the CPU) which permits the clock to run. The circuit of FIG. 828 includes forced repeat timing, and the circuit of FIG. 829 includes special clock signals used in the PDU.

21.5 MISCELLANEOUS PDU CIRCUITS FIG. 830 THROUGH FIG. 841

Miscellaneous PDU control circuits are shown on FIG. 830 through FIG. 841. These include, among other things, signals to cause manual storage requests, fetching to the instruction buffers under manual control, displaying of registers, the enable panel key fetch control, and manual storage controls. Additionally, initial program loading controls, forced repeating, meter controls, disabling of the invalid, condition sensing, the interval timer advance, and other functions are shown herein.

12.6 MAINTENANCE CONTROL WORD AND DIAGNOSE CIRCUITS FIG. 842 THROUGH FIG. 854

Diagnostic control over said environmental system is accomplished in part by the diagnostic circuits, which include the maintenance control word and its related circuitry, as shown in FIG. 842 through 854. A three-stage ring is shown in FIG. 842, the proceed signal is generated in FIG. 843, and diagnostic controls are generated in FIGS. 844 and 845. In FIG. 846, a plurality of controls for the maintenance control word register, incrementer, and latch are shown. These provide for setting of the diagnostic select code portion of the maintenance control word as shown in FIG. 847a, the setting and resetting of the count register, and causing the count latch to respond to the MCW counter so as to increment the setting of the register. The output of these circuits is decoded in FIG. 854 for use throughout the system.

21.7 PDU DATA FLOW FIG. 855-FIG. 858

In FIG. 855, the address bus portion of the PDU data flow is shown. This permits connection of the address keys to various parts of the system, with parity bits generated therefor. The data flow also illustrates the generation of mark and other functions which cause the maintenance controls to be equivalent to a "maintenance channel."

In FIG. 856, the data bus portion of the PDU data flow is shown. This permits the data keys to be integrated and to be gated to several points in the system with correct parity bits.

In FIG. 857, the initial program loading channel selecting and unit selecting switches are applied to integraters and then selectively gated on to the unit address bus in and as channel addresses, both of which is handled in the channel portion of the IE unit.

FIG. 858 illustrates the interface between the PDU and the channel.

22.0 STORAGE

Storage in said environmental system comprises essentially two main units 1a, 1b, each comprising an even and an odd half, and a storage protection hardware. Each half comprises logical portions as well as a basic operating memory, all as shown in FIG. 859. The logical portion of each of the storage units 1a, 1b comprises a certain amount of common hardware and a certain amount of hardware which relates only to the particular even or odd half thereof. This logic is shown in FIGS. 860 through 875. The basic operating memory is the term used to describe the actual core storage elements themselves and the circuitry for driving the elements and for sensing signals therein. The basic operating memory for said environmental system is illustrated in a copending application of the same assignee entitled DRIVE-SENSE LINE WITH IMPEDANCE DEPENDENT ON FUNCTION, Ser. No. 445,306, filed Apr. 5, 1965 by Anatol Furman, now U.S. Pat. No. 3,413,622, issued Nov. 26, 1968.

An illustration of storage protection circuitry which might be utilized in said environmental system is shown in a simplified block diagram for in FIG. 876. The basic element therein is a small core storage device, or other addressable registering device, wherein protection keys may be stored in association with portions of addresses, said portions specifying the blocks in memory which may be reached by those portions of addresses, together with other low-order portions which specify particular storage words. The storage protection feature is utilized to generate a storage address protection signal indicating that an unreachable portion of storage is being addressed.

While the improvement herein has been shown and described with respect to an illustrative embodiment thereof, it should be obvious to those skilled in the art that various enumerated changes, and other changes and omissions in the form and detail thereof, may be made therein without departing from the spirit and the scope of the invention.

Claims

What is claimed is:

1. In a data processing system having a plurality of addressable storage locations for storing, inter alia, manifestations of instructions to be performed by said system, said manifestations hereinafter referred to as instructions, said system including addressing means and storage request means for controlling the fetching and storing of data from and to said storage locations, said storage locations sending an accept signal in response to accepted requests, certain of said instructions calling for a branch from a point in a sequence of instructions to a different point, said points being defined by the addresses of storage locations in which said instructions are stored, a branch control device, comprising:

means responsive at a first period of system operation to the presence of a branch instruction to cause a fetch for the subject instruction thereof;

a data buffer register, said buffer register being connected to said storage locations so as to be capable of receiving manifestations therefrom;

instruction buffer registers, said instruction buffer registers being responsive directly to said storage locations and to said data buffer register;

control means in said system for transferring from instruction predecoding to instruction execution, said control means being settable after sensing of a branch instruction only in response to an accept signal from said storage locations;

branch testing means effective after said transfer for determining the presence or absence of conditions upon which branching is to be effected;

and means responsive to a successful branch for loading said instruction buffer registers from said storage or from said data buffer register, alternatively, in dependence upon the time at which the successfulness of said branch is known.

2. A device described in claim 1 additionally comprising:

means to provide an additional fetch request to a storage word next in sequence to the storage word related to said branch request.

3. A device described in claim 2 wherein the storage word resulting from said additional fetch is not routed in the event that the unsuccessfulness of said branch.

4. A device described in claim 3 additionally comprising:

means to cancel said additional branch fetch in the event that the branch fetch resulted in branch instruction.

5. In a data processing system in which addressable storage locations are referenced in order to derive instructions which govern the operation of said system, a branch control device, comprising:

means for sensing an instruction which calls for a branch, said means including means to determine a condition upon which branching is to be effected;

means responsive to said sensing means to initiate a storage fetch for the subject instruction;

a data buffer register and instruction buffer register means, said buffer registers all being responsive to said storage means, said instruction buffer register means being responsive to said data buffer register conditionally, in dependence upon branch control thereover;

accept means in said storage means for indicating the fact that it will provide a storage word in response to said branch fetch;

means responsive to said accept means to perform operations which determine the fulfillment of the branch condition;

and routing means for controlling the route of said branch instruction, said routing means directing the storage word resulting from said branch fetch directly to said instruction buffers in the event that said storage word is available at the input to said buffers after the determination of fulfillment of the branch is made, said routing means routing said storage word to said data buffer prior to the determination of the fulfillment of said branch, and said routing means directing said storage word from said data buffer to said instruction buffers when the determination of the fulfillment of the branch is known only following the routing of said storage word to said data buffer.

6. The device described in claim 5 wherein said storage word is automatically routed to said data buffer, whether or not it is simultaneously routed through said instruction buffer means.

7. In a data processing system in which addressable storage locations are referenced in order to derive instructions which govern the operation of said system, a branch control device, comprising:

means for sensing an instruction which calls for a branch, said means including means to determine the condition upon which branching is to be effected;

means responsive to said sensing means to initiate a storage fetch for the subject instruction;

a data buffer register and instruction buffer register means, said buffer registers all being responsive to said storage means, said instruction buffer register means being responsive to said data buffer register conditionally, in dependence upon branch control thereover;

means to perform operations which determine the successfulness of the branch instruction;

routing means for controlling the route of said branch instruction, said routing means directing the storage word resulting from said branch fetch directly to said instruction buffers in the event that said storage word is available at the input to said buffers after the determination of successfulness of the branch is made, said routing means routing said storage word to said data bus prior to the determination of the successfulness of said branch, and said routing means directing said storage word from said data buffers to said instruction buffers when the determination of the successfulness of the branch is known only following the routing of said storage word to said data buffer.

8. The device described in claim 7 wherein said storage word is automatically routed to said data buffer, whether or not it is simultaneously routed through said instruction buffer means.

9. In a data processing system having a plurality of storage locations which are accessible by storage control means including addressing means and fetch request means, said data processing system operating in an overlapped execution fashion, whereby certain functions performed in the execution of a first instruction are overlapped in time with the performance of other functions for a second instruction, said system including controls for effectively transferring control over two groups of functions from a first instruction to a second instruction, a first group of functions being transferred from a previous instruction to a first instruction concurrently with a second group of functions being transferred from a first instruction to a second instruction, said transfer hereinafter referred to as I to E transfer, said system including an accept manifestation indicating that a storage request has been accepted, a branch control apparatus, comprising:

means for sensing the presence of a branch instruction and for sensing a condition upon which said branch is to be effected, said condition if met resulting in a successful branch, the failure of said condition to be met resulting in an unsuccessful branch;

means responsive to said sensing means to initiate a fetch request for the subject instruction of a branch instruction;

means responsive to an accept signal resulting from said branch request to commit said I to E transfer, whereby functions to determine the successfulness of said branch may be performed;

a data buffer register connected to said storage means; instruction buffer registers connected to said storage means and to said data buffer register;

means responsive to various functions in said system for designating a successful branch;

and deriving means responsive to said last-named means providing a storage word to said data buffer register and to said instruction buffer means in response to a successful branch, for routing said storage word to said buffer register in response to a lack of indication from said last-named means as to whether or not the branch was successful, for routing said storage word from said data buffer register to said instruction buffers in the event that the successfulness of said branch is indicated by said last-named means after said storage word is loaded in said buffer, said storage word not being routed from said data buffer register in the event an unsuccessful branch is determined after the setting of said storage word into said data buffer register, said routing means also blocking the transfer of said storage word to either said data buffer register or said instruction buffer means in the event that the unsuccessful character of said branch is determined at the time said storage word becomes available to said buffers.

10. The device described in claim 9 additionally comprising:

means responsive to the I to E transfer to provide an additional branch plus one fetch request to a storage word next in sequence to the storage word related to said branch request.

11. A device described in claim 10 wherein the storage word resulting from said branch plus one fetch is not routed in the event of the unsuccessfulness of said branch.

12. A device described in claim 11 additionally comprising:

means concurrently responsive to said accept signals and to said sensing means to cancel said additional branch fetch in the event that the branch fetch resulted in a branch instruction.

13. In a data processing system having storage means and a plurality of functional units capable of accessing said storage means, said storage means comprising at least two portions, said portions being independently operable so that storage references may be made alternately to first one and then the other, said storage references being performed in an interleaved fashion, said data processing system including a storage control device for initiating storage references, and for generating a select signal upon the initiation of a storage reference, said storage devices generating an advance signal indicative of the performance of a storage reference by the related storage device, a storage return control apparatus, comprising:

a first binary trigger having first and second alternate states of operation, responsive to said select signals for alternating states in response to successive select signals received thereby;

a second binary trigger having two alternate states of operation, responsive to said advance signals for alternating states in response to successive advance signals received thereby;

a pair of registers, one of said registers being responsive to said functional units to store manifestations indicative of a functional unit which has initiated a storage reference when said first trigger is in said first state, the other of said registers being responsive to said functional units to store manifestations indicative of a functional unit which has initiated a storage reference when said first trigger is in said second state;

connection means responsive to both of said registers, said connection means being selectively responsive to either a first one of said registers or to the second one of said registers, alternatively, in dependence upon the setting of said second binary trigger;

means for checking, at identifiable times, the states of said first and second binary triggers; and

means for indicating an error in the event that said triggers do not exhibit a proper phase relationship with one another.

14. In a data processing system in which addressable storage means are referenced in order to derive instructions which govern the operation of said system, a branch control device, comprising:

means for sensing at a first period of system operation, the presence of a branch instruction and for causing a fetch for the subject instruction thereof;

a buffer register, said buffer register being connected to said storage means so as to be capable of receiving manifestations therefrom;

instruction buffer registers, said instruction buffer registers being responsive directly to said storage means and to said buffer register;

branch testing means responsive to conditions within said data processing system for determining the presence or absence of conditions upon which branching is to be effected;

means responsive to a successful branch for loading said instruction buffer registers from said storage or from said buffer register, alternatively; and

means to provide an additional fetch request to a storage word next in sequence to the storage word related to said branch request.

15. A device described in claim 14 wherein the storage word resulting from said additional fetch is not routed in the event that the unsuccessfulness of said branch.

16. A device described in claim 15 additionally comprising:

means to cancel said additional branch fetch in the event that the branch fetch resulted in a branch instruction.

17. In a data processing system in which addressable storage means are referenced in order to derive instructions which govern the operation of said system, a branch control

means for sensing the presence of a branch instruction to cause a fetch for the subject instruction thereof;

a buffer register, said buffer register being connected to said storage means so as to be capable of receiving manifestations therefrom;

instruction buffer registers, said instruction buffer registers being responsive directly to said storage means and to said buffer register;

branch testing means responsive to conditions within said data processing system for determining the presence or absence of conditions upon which branching is to be effected;

means responsive to a successful branch for loading said instruction buffer registers from said buffer register; and

means to provide an additional fetch request to a storage word next in sequence to the storage word related to said branch request.

18. A device described in claim 17 wherein the storage word resulting from said additional fetch is not routed in the event that the unsuccessfulness of said branch.

19. A device described in claim 18 additionally comprising:

means to cancel said additional branch fetch in the event that the branch fetch resulted in a branch instruction.

20. In a data processing system of the type having a plurality of addressable storage locations which may be accessed by initiating store and fetch requests and through the provision of an addressing adder which provides address manifestations to the storage address register, said system having a PSW register, an other register and means for checking the PSW, a control device for the handling of interruptions and for providing other functions to said system, comprising:

means including first gating means connected between said addressing adder and said storage address register;

means including second gating means connected between one half of said PSW register and said other register;

means including third gating means connected between the other half of said PSW register and said other register;

means including fourth gating means connected between a first half of said PSW register and said means for checking;

means including fifth gating means connected between the second half of said PSW register and said means for checking;

a plurality of stable stages, each of said stages providing certain functions when in a first state, only one of said stages at a time being in said first state, each of said stages performing no function when in a second state, said stages being as follows:

stage 1 provides address bits to the addressing adder and provides a signal to enable said first gating means to gate the addressing adder to the storage address register,

stage 2 initiates a storage request,

stage 3 provides a further address manifestation to the addressing adder, and provides signals to enable said first and second gating means to gate the addressing adder to the storage address register and to gate the right-hand half of the PSW to said other register,

stage 4 initiates a storage request and also provides a signal to enable said third gating means to gate the left-hand half of the PSW to corresponding parts of said other register, the PSW half previously loaded into said other register being shifted to the low-order portion thereof,

stage 5 receives new storage word from storage, loads it in said PSW register and provides a signal to enable said fourth gating means, half of said PSW register being gated to said means for checking,

stage 6 provides signals to restore conditions established by said stages 1 through 5 and enable said fifth gating means to cause the other half of said PSW register to be gated to said means for checking,

last stage resets blocking conditions and resumes normal system operations;

and means to select from among said stages.

21. The device described in claim 20 additionally comprising;

means for generating a timer advance request to select said first and second stages;

means responsive to said second stage to decrement a storage word fetched thereby;

means responsive to said last-named means at the completion of the decrementing of said storage word to select for operation said last stage.

22. The device described in claim 20 additionally comprising:

means to sense a machine failure;

means responsive to said last-named means to reset portions of said system and to generate a starting signal;

means responsive to said starting signal to select said first stage.

23. The device described in claim 20 additionally comprising:

means external to said system for generating a stable external interruption signal;

and means responsive to said last-named means for selecting said first stage.

24. The device described in claim 20 additionally comprising:

input/output means having the capability of presenting a signal to said system indicating that interruption handling is required of said system by said input/output means;

means responsive to said signal generated by said last-named means to select said first stage;

means responsive to said first stage to generate a channel interrupt response signal for transmission to said input/output means said input/output means presenting to said system in response thereto, a channel release signal;

means responsive to said channel release signal for selecting said second stage.

25. The device described in claim 20 additionally comprising:

Ipl means for initiating an initial program loading operating for said system;

means responsive to said last-named means for selecting said first stage;

means responsive to said IPL means and to said second stage for setting an initial program load buffer device;

means responsive to said initial program load buffer device and to the reset of a new PSW to select said fifth stage.

26. The device described in claim 20 additionally comprising:

instruction-responsive means for selecting said first stage.

27. In a data processing system of the type having a plurality of addressable storage locations which may be accessed by initiating store and fetch requests and through the provision of an addressing adder which provides address manifestations to the storage address register, said system including a PSW register, an other register and a point for checking the PSW a control device for the handling of interruptions and for providing other functions to said system, comprising:

means including first gating means connected between said addressing adder and said storage address register;

means including second gating means connected between one half of said PSW register and said other register;

means including third gating means connected between the other half of said PSW register and said other register;

means including fourth gating means connected between a first half of said PSW register and said point for checking;

means including fifth gating means connected between the second half of said PSW register and said point for checking;

first means to provide address bits to the addressing adder and to enable said first gating means to gate the addressing adder to the storage address register;

second means to initiate a storage request;

third means to provide a further address manifestation to the addressing adder, and to enable said first gating means to gate the addressing adder to the storage address register, and to enable said second gating means to gate the right half of the PSW register to said other register;

fourth means to initiate a storage request, to enable said third gating means to gate the left half of said PSW to a corresponding part of said other register, to shift the PSW half previously loaded into said other register to the low-order portion thereof;

fifth means to receive a new storage word from storage and to store it in said PSW register, and to enable said fourth gating means to gate half of said PSW register to said point for checking thereof;

sixth means to reset conditions established by said first through fifth means and to enable said fifth gating means to cause the other half of said PSW register to be gated to said point where it can be checked;

and last means to reset blocking conditions and resume normal, operations.

28. The device described in claim 27 additionally comprising:

means for generating a timer advance request to select said first and second means;

means responsive to said second means to decrement a storage word fetched thereby;

means responsive to said last-named means at the completion of the decrementing of said storage word to select for operation of said last means.

29. The device described in claim 27 additionally comprising:

means to sense a machine failure;

means responsive to said last-named means to reset portions of said system and to generate a starting signal;

means responsive to said starting signal to select said first means.

30. The device described in claim 27 additionally comprising:

means external to said system for generating a stable external interruption signal;

and means responsive to said last-named means for selecting said first means.

31. The device described in claim 27, additionally comprising:

input/output means having the capability of presenting a signal to said system indicating that interruption handling is required of said system by said input/output means;

means responsive to said signal generated by said last-named means to select said first means;

means responsive to said first means to generate a channel interrupt response signal for transmission to said input/output means, said input/output means presenting to said system in response thereto, a channel release signal;

and means responsive to said channel release signal for selecting said second means.

32. The device described in claim 27, additionally comprising:

Ipl means for initiating an initial program loading operation for said system;

means responsive to said last-named means for selecting said first means;

means responsive to said IPL means and to said second means for setting an initial program load buffer device;

and means responsive to said initial program load buffer device and to the reset of a new PSW to select said fifth means.

33. The device described in claim 27 additionally comprising:

instruction responsive means for selecting said first means.

34. In a data processing system of the type having a plurality of addressable storage locations which may be accessed by initiating store and fetch requests and through the provisions of an addressing adder which provides address manifestations to the storage address register, said system having a PSW register, an other register and means for checking the PSW a control device for handling of interruptions and for providing other functions to said system, comprising:

means including first gating means connected between said addressing adder and said storage address register;

means including second gating means connected between one half of said PSW register and said other register;

a plurality of stable stages, each of said stages providing certain functions when in a first state, only one of said stages at a time being in said first state, each of said staged performing no function when in a second state, said stages being as follows:

stage 1 provides address bits to the addressing adder and enables said first gating means to gate the addressing adder to the storage address register,

stage 2 initiates a storage request,

stage 3 provides a further address manifestation to the addressing adder, and enables said first gating means to gate the addressing adder to the storage address register,

stage 4 initiates a storage request and also enables said second gating means to gate the left-hand half of the PSW to corresponding parts of said other register,

stage 5 receives new storage word from storage and loads it in said PSW register,

stage 6 restores conditions established by said stages 1 through 5,

last stage resets blocking conditions and resumes normal system operations; and means to select from among said stages.

35. The device described in claim 34 additionally comprising:

means for generating a timer advance request to select said first and second stages;

means responsive to said second stage to decrement a storage word fetched thereby;

means responsive to said last-named means at the completion of the decrementing of said storage word to select for operation said last stage.

36. The device described in claim 34 additionally comprising:

means to sense a machine failure;

means responsive to said last-named means to reset portions of said system and to generate a starting signal;

means responsive to said starting signal to select said first stage.

37. The device described in claim 34 additionally comprising:

means external to said system for generating a stable external interruption signal;

and means responsive to said last-named means for selecting said first stage.

38. The deice described in claim 34 additionally comprising:

input/output means having the capability of presenting a signal to said system indicating that interruption handling is required of said system by said input/output means;

means responsive to said signal generated by said last-named means to select said first stage;

means responsive to said first stage to generate a channel interrupt response signal for transmission to said input/output means, said input/output means presenting to said system in response thereto, a channel release signal;

means responsive to said channel release signal for selecting said second stage.

39. The device described in claim 34 additionally comprising:

Ipl means for initiating an initial program loading operation for said system;

means responsive to said last-named means for selecting said first stage;

means responsive to said IPL means and to said second stage for setting an initial program load buffer device;

means responsive to said initial program load buffer device and to the reset of a new PSW to select said sixth stage.

40. The device described in claim 34 additionally comprising:

instruction responsive means for selecting said first stage.

41. In a data processing system of the type having a plurality of addressable storage locations which may be accessed by initiating store and fetch requests and through the provision of an addressing adder which provides address manifestations to the address register, said system including a PSW register and another register, a control device for the handling of interruptions and for providing other functions to said system, comprising:

first means to provide address bits to the addressing adder and gate the addressing adder to the storage address register;

second means to initiate a storage request;

third means to provide a further address manifestation to the addressing adder, and gate the addressing adder to the storage address register,

fourth means to initiate a storage request,

fifth means to receive a new storage word from storage and to store it in said PSW register;

sixth means to reset conditions established by said first through fifth means;

and last means to reset blocking conditions and resume normal operations.

42. The device described in claim 41 additionally comprising:

means for generating a timer advance request to select said first and second means;

means responsive to said second means to decrement a storage word fetched thereby;

and means responsive to said last-named means at the completion of the decrementing of said storage word to select for operation of said last means.

43. The device described in claim 41 additionally comprising:

means to sense a machine failure;

means responsive to said last-named means to reset portions of said system and to generate a starting signal;

means responsive to said starting signal to select said first means.

44. The device described in claim 41 additionally comprising:

means external to said system for generating a stable external interruption signal;

and means responsive to said last-named means for selecting said first means.

45. The device described in claim 41 additionally comprising:

input/output means having the capability of presenting a signal to said system indicating that interruption handling is required of said system by said input/output means;

means responsive to said signal generated by said last-named means to select said first means;

means responsive to said first means to generate a channel interrupt response signal for transmission to said input/output device, said input/output device presenting to said system in response thereto, a channel release signal;

and means responsive to said channel release signal for selecting said second means.

46. The device described in claim 41 additionally comprising:

Ipl means for initiating an initial program loading operation for said system;

means responsive to said last-named means for selecting said first means;

means responsive to said IPL means and to said second means for setting an initial program load buffer device;

and means responsive to said initial program load buffer device and to the reset of a new PSW to select said fifth means.

47. The device described in claim 41 additionally comprising:

instruction responsive means for selecting said first means.

48. In a data processing system which includes a plurality of multistate indicating means for indicating conditions in said system, one state of each of said indicating means being a reset state; abnormal condition recovery means, comprising:

means for comparing a fetch address and a store address;

means responsive to said last-named means for manifesting, in a stable condition, the result of said comparison;

an interruption entrance latch;

means responsive to said manifested result for testing said system for interruptions and for conditionally setting said interruption entrance latch;

and means responsive to said interruption entrance latch for resetting a plurality of said indicating means in said system.

49. In a data processing system which includes a plurality of multistate indicating means for indicating conditions in said system, one state of each of said indicating means being a reset state; abnormal condition recovery apparatus, comprising:

instruction responsive means for designating a single step branch instruction;

a recovery-required latch;

means responsive to said last-named means for setting said recovery-required latch;

means responsive to said recovery-required latch for testing said system for interruptions;

means alternatively responsive to interruptions or to said recovery-required latch for entering into an interruption sequence;

means responsive to said interruption sequence for selectively resetting a portion of said indicating means; fewer of said indicating means being reset in the absence of an interruption when said recovery-required latch is set than would otherwise be reset thereby;

and means operative after said last-named means for fetching an instruction.

50. In a data processing system which includes a plurality of multistate indicating means for indication conditions in said system, one state of each of said indicating means being a reset state:

means for comparing a fetch address and a store address;

means responsive to said last-named means for manifesting, in a stable condition, the result of said comparison;

an interruption entrance latch;

means responsive to said manifested result for setting said interruption entrance latch;

and means responsive to said interruption entrance latch for resetting a plurality of said indicating means in said system.

51. In a data processing system which includes a plurality of multistate indicating means for indicating conditions in said system, one state of each of said indicating means being a reset state; abnormal condition recovery apparatus, comprising:

instruction means for designating a single step branch instruction;

a recovery-required latch;

means responsive to said last-named means for setting said recovery-required latch;

means responsive to said recovery-required latch for testing said system for interruptions;

means responsive to said recovery-required latch in the absence of an interruption for entering into an interruption sequence;

means responsive to said interruption sequence for selectively resetting a portion of said indicating means;

and means operative after said last-named means for fetching an instruction.

52. In a data processing system which includes a plurality of multistate indicating means for indicating conditions in said system, one state of each of said indicating means being a reset state; abnormal condition recovery means, comprising:

instruction responsive means for designating a single step branch instruction;

means responsive to said last-named means for manifesting, in a stable condition, an execute operation;

an interruption entrance latch;

means responsive to said execute operation for testing said system for interruptions and for conditionally setting said interruption entrance latch;

and means responsive to said interruption entrance latch for resetting a plurality of said indicating means in said system.

53. In a data processing system which includes a plurality of multistate indicating means for indicating conditions in said system, one state of each of said indicating means being a reset state; abnormal condition recovery apparatus, comprising:

means for comparing a fetch address and a store address;

a recovery-required latch;

means responsive to said last-named means for setting said recovery-required latch;

means responsive to said recovery-required latch for testing said system for interruptions;

means alternatively responsive to interruptions or to said recovery-required latch for entering into an interruption sequence;

means responsive to said interruption sequence for selectively resetting a portion of said indicating means; fewer of said indicating being reset in the absence of an interruption when said recovery-required latch is set than would otherwise be reset thereby;

and means operative after said last-named means for fetching an instruction.

54. In a data processing system which includes a plurality of multistate indicating means for indicating conditions in said system, one state of each of said indicating means being a reset state:

instruction means for designating a single step branch instruction;

means responsive to said last-named means for manifesting, in a stable condition, an execute operation;

an interruption entrance latch;

means responsive to said execute operation for setting said interruption entrance latch;

and means responsive to said interruption entrance latch for resetting a plurality of said indicating means in said system.

55. In a data processing system which includes a plurality of multistate indicating means for indicating conditions in said system, one state of each of said indicating means being a reset state; abnormal condition recovery apparatus, comprising:

means for comparing a fetch address and a store address;

a recovery-required latch;

means responsive to said last-named means for setting said recovery-required latch;

means responsive to said recovery-required latch for testing said system for interruption;

means responsive to said recovery-required latch in the absence of an interruption for entering into an interruption sequence;

means responsive to said interruption sequence for selectively resetting a portion of said indicating means;

and means operative after said last-named means for fetching an instruction.

56. In a data processing system, apparatus for moving groups of data from a source point in said system to a result location therein, comprising:

means to sense boundary conditions of source point of said data and the result location of said data;

means responsive to like boundary conditions for moving said data a plurality of groups at a time, in parallel;

and means responsive to unlike boundary conditions for moving said data one group at a time.

57. The device described in claim 56, additionally comprising:

means operative during a multigroup move to sense unlike boundary conditions after moving one set of groups;

and means responsive to said last-named means for moving data one group at a time.

58. The device described in claim 57 additionally comprising:

means operative during a multicharacter move to sense unlike boundary conditions at terminal boundaries thereof;

and means responsive to said last-named means for moving data in single-character groups.

59. In a data processing system, apparatus for moving data from one point in said data system to another, comprising:

means to sense boundary conditions of the source of said data and the result location of said date;

and instruction responsive means responsive to like boundary conditions for moving said data in multicharacter groups and

responsive to unlike boundary conditions for moving said data in single-character groups.

60. In a data processing system, apparatus for moving groups of data from one multigroup location in said data system to another multigroup location therein, comprising:

means to sense boundary conditions of the source of said data and the result location of said data;

and means responsive to said boundary conditions being coextensive with said locations for moving said data in multigroup sets, each set coextensive with said locations, said means responsive to unlike boundary conditions for moving one group at a time.

61. The device described in claim 60, additionally comprising:

means operative during a multigroup move to sense unlike boundary conditions after moving between a first pair of locations;

and means responsive to said last-named means for moving one group at a time.

62. In a data processing system of the type having a plurality of addressable storage locations which may be accessed by initiating store and fetch requests and through the provision of an addressing adder which provides address manifestations to the address register, said system including a PSW register and another register, a control device for the handling of interruptions and for providing other functions to said system, comprising:

means to provide address bits to the addressing adder, gate the addressing adder to the storage address register, and

to initiate a storage request;

means to provide a further address manifestation to the addressing adder, gate the addressing adder to the storage address register, and

to initiate a storage request;

and means to receive a new storage word from storage,

to reset certain conditions in said system,

and to reset blocking conditions and resume normal operations.