Data Processing Network And Improved Terminal

Abstract

A data processing system having a central or main data processor and a plurality of remote data terminals each having at least one selectively changeable terminal address. The central processor is coupled in a poll-select environment to the various remote terminal processors via a communication link. The respective remote terminals are able to modify the poll-select sequence as set up by the central processor by selectively changing its terminal address for either the poll or select mode. Additionally, groups of the remote terminals may be assigned a selectively changeable group or broadcast address which may be changed either locally at the remote terminal or remotely by the central processor.

Description

CROSS-REFERENCE

This invention relates to the extended structure and improved method of using a remote terminal disclosed and claimed in U.S. Pat. No. 3,564,509, issued Feb. 16, 1971, in the name of Perkins et al. which is assigned to the assignee of the present invention and incorporated herein by reference.

BRIEF DESCRIPTION

This invention relates to an on-line data processing system and more particularly to an improved on-line multiterminal data processing system in which the remote terminals individually have a selectively changeable address capability. The address of the remote terminals may be altered locally at the remote terminal or remotely in response to a command from the central processor.

BACKGROUND

As is well known, computers are being utilized at an ever increasing rate to perform various functions in the commercial, manufacturing and scientific world. The application of computers to various operations may be divided into two operating modes, namely: on-line data processing systems and off-line or batch processing systems. A real time or on-line system is generally defined as a data processing system in which the time delay in a central processor responding to an input stimulus from a remote terminal is negligible in the time reference of the remote users equipment.

The terminal disclosed and claimed in the hereinabove identified Perkins et al. patent permits a wide variation in the system discipline of an on-line data processing system. Essentially the improved remote terminal, sold commercially as the Burroughs TC500, greatly facilitates on-line systems by permitting the communication line-discipline function to be handled remotely at each remote terminal and by providing computational capability at each such terminal. These additional terminal capabilities in effect relieve the central processor of the time consuming task of establishing communication line-discipline as was necessary in the prior art systems using for example the teletype-type terminals at the remote station.

Upstream communication between ones of the remote terminals and a central data processor may be blocked in effect by the poll or sequence routine established in the system in view of a particular communication backlog. For example, in the morning after the central processor has been operating during off-hours, the central processor or the terminals may have a backlog of information to be sent over the communication net. During this period in which the central processor is in a select mode of operation for an extended period of time, one or more remote terminals may wish to communicate over the same line with the central processor. This of course is not possible in a normal poll or select environment as the central processor generally establishes the routine or frequency with which the respective terminals are selectively addressed, for example in a poll or select sequence.

In this mode of operation a terminal must await its turn as determined by the frequency with which the central processor addresses the respective terminal in either a poll or select mode. The problem of a remote terminal obtaining access to the computer via the communication link is further compounded in those instances in which for one reason or another various high traffic terminals are polled more frequently than low traffic terminals or the central processor goes into an extended select mode sequence. In prior art systems in instances such as these the one or more remote terminals desiring access to the central processor on a particular mode basis would simply have to await their normal turn as determined by the computer controlled inquire message sequence.

Accordingly, it is an object of the present invention to improve the transmission efficiency of data between a plurality of remotely situated data terminals and a central data processor.

It is a further object of the present invention to increase the operating efficiency of a plurality of remotely situated data processors which are coupled on-line with a central data processor.

It is a further object of the present invention to improve the upstream communication between a plurality of remotely situated terminal processors and a central data processor.

It is a further object of the present invention to provide means for selectively changing a remote terminal's address either locally or upon command from a central data processor in an on-line environment.

It is a further object of the present invention to provide apparatus for selectively varying the address of one of a plurality of remote terminals in an on-line environment.

It is yet another object of the present invention to provide remote terminals with capability of responding to ones of a plurality of machine addresses and of selectively changing ones of such addresses in either a poll-select or broadcast communication environment.

It is yet another object of the present invention to provide improved means for controlling communication on-line between the central data processor and a plurality of remotely situated remote terminal processors in a poll and select environment.

BRIEF STATEMENT OF THE INVENTION

The above objects and other desirable aspects are achieved in accordance with applicant's invention by employing logic means at each remote terminal of an on-line data processing system to selectively control the address of that terminal. This address controlling logic has the capability of selectively changing the remote terminal address either locally at the terminal or upon command from the central processor and thus permits the terminal to communicate more efficiently in the on-line data processing mode. This system architecture relieves the remote terminal and the central processor from slavishly following a transmission mode established at, for example, the central data processor while one or more terminals has an urgent message to be transmitted. Further, in accordance with another aspect of applicant's invention a group of terminals may be selectively designated to receive and respond to a message without individually addressing such terminals of the group in a poll or select mode.

For a more complete understanding of applicant's invention as to its preferred structure and method of operation reference may be had to the following detailed description in conjunction with the drawings wherein:

FIG. 1 is a block diagram of a data processing system utilizable in accordance with the principles of the present invention;

FIG. 2 is a block diagram of a remote terminal embodying the principles of the present invention;

FIG. 3 is a logical block diagram of a remote terminal computer embodying the principles of the present invention;

FIG. 4 is a logic flow diagram of one method of operating applicant's remote terminal in an on-line communication net with a central data processor; and

FIG. 5 is a logic flow diagram of yet another method of operating applicant's selectively addressable remote terminal in accordance with another aspect of the principles of the present invention.

Referring now to FIG. 1 there is shown a block diagram of a typical on-line data communication system in which the principles of the present invention are utilizable. A central data processor 11, with its associated complement of input/output storage devices 13, 15, 17, 19 and 21, is connected via a communication link 22 to a plurality of remote data terminals 23. The central data processor may be located, for example, in the main business office of a commercial firm and the remote terminals 23 may be located in the branch offices of the commercial firm. The branch offices may be in the same general location or remote therefrom and in each case the remote terminals 23 are connected via a modem or line communication adapter 25 to the communication link 22. The communication link 22 may include for example standard telephone lines connecting the remote data terminals 23 via a central communication dial exchange 27 to the site of the central processor 11. The remote data terminals are preferably arranged in a multidrop or multipoint poll and select transmission environment whereby the respective remote data terminals 23 are arranged to perform data processing functions in accordance with their respective programs off-line and to communicate with the central data processor 11 whenever the remote terminal is addressed by an inquiry message.

Referring now to FIG. 2 there is shown a simplified block diagram of a remote terminal incorporating the principles of the present invention. The remote terminal 23 may be described as comprising three major sections: a remote processor 33, including a main memory 35 and an input/output keyboard 37; a line discipline processor 41, with its auxiliary memory 43 and terminal address control logic 45; and a terminal buffer store 47. The output of the buffer store 47 is coupled by an appropriate device, for example, a modem 25 to the input of the communication line 22. The structure and operational interrelationship of the sections of the terminal 23 is discussed in detail hereinafter in conjunction with FIGS. 3, 4 and 5 with similar reference numerals being used to designate the respective sections of the terminal 23.

Now referring to FIGS. 1 and 2 in conjunction with table I below, the format and function of the various portions of inquiry and response messages transmitted between the central processor and the remote terminals may be understood. ##SPC1##

Entries A through D of table I illustrate typical examples of messages exchanged between the remote terminal 23 and the central processor 11. The remote terminal 23 is preferably capable of operating in either an off-line or an on-line mode. In the off-line mode, processing tasks are accomplished by the remote processor 33 in accordance with program and object data stored in its memory. In the on-line mode, the remote processor 33 relies upon communications with the central processor over the communication link for at least a portion of its operation. In the on-line mode, the remote terminal 23 preferably operates in a poll and select environment.

A poll inquiry message or poll is defined as a message by which the central data processor 11 interrogates one of a plurality of addressed remote terminals, for example in a predetermined sequence, and inquires whether the addressed remote terminal has a message ready for transmission to the central processor. A select inquiry message or select is defined as a message by which the central data processor interrogates one of a plurality of addressed remote terminals in the communication net informing the addressed remote terminal that the central processor has a message ready for transmission to the addressed remote terminal.

In either the poll or select mode, if an addressed remote terminal is not ready to receive a message, i.e., it is either being operated off-line or it is otherwise not ready to receive or send a message in response to the received inquiry message addressed to it, the line-discipline processor 41 automatically responds with an appropriate "not ready" message to the central processor 11. As shown in entries B and D of table I, the line-discipline processor 41 responds to a poll with an EOT and to a select with a NAK to indicate that it is not ready to send or receive a message respectively. Upon receiving the negative acknowledgement from the addressed remote processor, the central processor either retransmits its message which may have been garbled in the transmission channel or it may continue on its poll or select sequence to the next remote terminal in the normal addressing sequence.

Referring to entries A through D of table I, the function or explanation of the message is written above the signal indicating waveform-type line and the message format is indicated below the line. The message format includes, reading left to right, characters 1, 2, 3 ... N. The respective characters indicated are those of The USA Standard Code For Information Interchange (USASCII).

Entry A of table I illustrates a message exchange for a typical poll operation. The first character in the message transmitted by the central data processor 11 comprises an end of transmission character EOT. All transmissions may begin with this EOT character or another suitable character. Following the EOT character are two address characters AD1 and AD2. In a typical multiterminal line environment each remote terminal 23 would have assigned to it a plurality of dual character addresses which are for example stored in an expected message portion of the memory of the line discipline processor 41. Following the address characters are the poll POL and inquiry ENQ characters. Entries C and D of table I show a similar message from the central data processor 11 as assembled and transmitted for the select message with the SEL character replacing the POL character of the poll message format illustrated in entries A and B.

Referring again to FIGS. 1 and 2 it may be seen that each terminal 23 through its line discipline processor 41 responds only to the messages specifically addressed to that terminal even though the communication network is in what is known as a multipoint or multidrop mode. In the multidrop mode each terminal 23 receives all messages transmitted by either a remote terminal or the central processor. If as in prior systems each terminal 23 has only a single address, the terminal is in effect a slave to the central processor which establishes the poll and select routine and the frequency with which each respective terminal 23 in the net will receive a poll or select message addressed to it.

In accordance with applicant's invention, the terminal address control logic 45, which may comprise a shift register or other memory store and logic gating for storing an address generated either by the arithmetic unit of the remote processor 33 or of line discipline processor 41, expands the capabilities of the remote terminal by permitting either the remote terminal operator or the central processor to determine in advance the address of the terminal. This in turn determines which subsequently received messages the remote terminal will respond to by determining when the present, i.e., altered, address of the remote terminal corresponds with the message address characters of the inquiry message transmitted from the central processor. As hereinafter is more fully explained in conjunction with FIGS. 3, 4 and 5, by selectively changing the address of the remote terminal, a remote terminal is enabled to gain access to the central processor by interrupting the poll-select sequence established by the remote processor. Basically this interruption of the poll or select mode may be accomplished by either programming the central processor to change the inquiry transmission mode if it does not receive either a positive or negative acknowledgment from the terminal to which the last message was addressed or by having the remote terminal transmit a control character message if its address has been modified.

Referring now to FIG. 3 there is illustrated a logic block diagram of applicant'remote data terminal 23. As hereinabove described the remote data terminal 23 comprises three major sections: the remote processor 33, the line discipline processor 41 and the terminal buffer 47.

The remote or terminal processor 33 preferably comprises a stored program machine in which object data is manipulated in an arithmetic unit 51 in accordance with a sequence of microprogram instructions stored in and withdrawn from the main memory 35 in a predetermined sequence. The input channel 36 and keyboard 37 are arranged to selectively enter program and object data into the processor 33 via an input buffer register 39. The main memory 35 may comprise, for example, a rotatable magnetic disk having a plurality of read/write heads for accessing an unrestricted general memory section and a plurality of read only heads for accessing a restricted stored program portion of the memory. The information and object data stored in the main memory is processed in the arithmetic unit 51 which may include, for example, a full adder and appropriate input gating selection networks, not shown. A memory address register (MAR) 53 is operatively associated with the memory select matrix via gates 55 and 57 to access an appropriate portion of memory in response to an address loaded in the MAR by the instruction decoder 59.

In operation of the remote processor in accomplishing its tasks as designated by the program being run, the memory address register 53 periodically addresses and interrogates the main memory and withdraws therefrom an appropriate program instruction indicated by the address located by the instruction decoder 59. The micro instructions withdrawn from the read only portion of memory are sequentially loaded into the instruction decoder 59. The output of the instruction decoder 59 enables appropriate control logic for controlling various gating functions in the processor in accordance with the contents of the instruction decoder register 59. The instruction decoder in response to withdrawn program instructions controls the state machine 61 via gate 63. The state machine 61, which may comprise a counter generates a sequence of timed machine state levels or timing pulses for controlling the various logic functions of the processor including, for example, the operation of an adder or the exchange of information between the memory the input buffer 39, the instruction 59 or the printer 65. As shown the arithmetic logic 51 or the memory 35 of the processor 33 may directly actuate the printer 65 via gates 67 and 69 thus providing a hard copy output of the results of the processor's computation.

As in a normal stored program machine, after each instruction is decoded by the instruction decoder 59 and executed by the memory 35 and the arithmetic logic 51, the processor 33, for example through its adder logic, generates an advance signal to increment an instruction counter associated with the instruction decoder thereby stepping the instruction counter to the next count in its orderly count sequence. In response to the new contents of the instruction counter, the next in a series of micro instructions would be withdrawn from main memory 35 and serially fed to the instruction decoder 59. In this manner, the respective sequential syllables of a memory word of a program instruction would be transferred to the instruction decoder to properly energize the control matrix for withdrawing the appropriate program steps and/or data from memory. Thereafter the instruction decoder in response to the decoded program instruction would appropriately energize the state machine 61 to generate appropriate logic timing signals to enable the processor to accomplish the task indicated by each decoded program instruction. As the various sequential steps of the serial program are sequentially executed an appropriate output is generated on printer 65.

In addition to being able to operate off-line, the remote processor 33 is capable of operating on-line and communicating with the central processor 11 as shown in FIG. 1. This communication with the central processor is controlled by the line-discipline processor 41. The line-discipline processor 41 is preferably a stored program machine and may be similar in structure and operation to the remote processor 33. The function of the line-discipline processor is to establish line-discpline in accordance with a stored microprogram for controlling the assembly, editing, formatting and parity generation-check of messages to be transmitted to and as received from the central processor for the remote processor 33.

The line-discipline processor is preferably similar in structure and operation to the remote processor 33. An auxiliary or message memory 43 is arranged to store messages to be sent to and received from the central processor and to store a series of micro instructions for controlling the operation of the arithmetic unit 75 of the line-discipline discipline processor 41. The message memory 43 may for example comprise a rotatable memory having a read-write portion for storing messages and a read only memory for storing micro instructions. A head selection matrix, not shown, which is responsive to the memory address register 77 is used to control the accessing of the memory 43 to withdraw micro instructions and to withdraw messages stored therein. The memory address register 77 of the line-discipline processor 41 controls the access to and reading of the micro instructions from the message memory to a decode register 79. The micro instructions withdrawn from the memory 43 are decoded in the decode register 79 with the output of the decode register 79 controlling the state machine 81 in accordance with the contents of the decoded program step. In this manner the decode register 79 controls the generation of appropriate logic gating signals for controlling the operation of the arithmetic unit 75, which may comprise a full adder and appropriate gating for manipulating data in accordance with the decoded micro instructions.

As is known in the art, state machine 81 generates appropriate timing signals in response to a signal from the oscillator 83 to control the operation of the logic gates 85, 87 and 89 and for example logic gate 85 which control the exchange of information between the memory address register 77 and arithmetic unit 75. The operation of the state machine which may comprise a counter may be further controlled by appropriate control signals TX and RX which designate a function of the transmit or receive state of the line-discipline processor 41 and buffer 47.

When the remote processor 33 has a message to be transmitted to the central processor 11, the message to be transmitted is originally assembled by the remote processor 33 in a specific area of the memory 35. After monitoring and determining the condition of the transmit and receive flag registers 91 and 93 respectively, the remote processor selects an appropriate time and transfers the message from the memory 35 of the remote processor 33 to the memory 43 of the line discipline processor 41 for example via arithmetic logic 51 and decoder 59. Thereafter the remote 33 is free to return to its off-line task, and the line discipline processor 41 awaits the receipt of a poll from the central process 11 to initiate the transmission of the message stored in the message memory 43. The sequence and format of inquiry and response messages transmitted between the line-discipline processor 41 and the central processor 11 has been discussed hereinabove in detail in conjunction with FIGS. 1 and 2 and Table I.

When the line-discipline processor 41 receives an inquiry message from the central processor 11, the appropriate RX signal, i.e., a signal for example, signifying carrier detect, actuates the logic gate 95 thereby initiating the operation of the state machine 81 in the receive mode. The received inquiry message is transferred bit serially from the modem 25 to the buffer storage 47 as it is received serially from the line. The information stored in the buffer 47 is then compared in the comparator 101 with an expected message format previously stored, for example, in an expected message store 103, which may comprise any memory, for example, an array of flip-flops arranged to store encoded information in the form of the expected message format as hereinabove described in conjunction with table I.

As shown the logic gates 105 and 107 in conjunction with suitable timing signals for example tO through t5 may be employed to transfer or couple the contents of the respective stages of the buffer store 47 and the expected message store and 103 to the comparator 101. In this manner, the respective binary bits of the appropriate portions of the received message and expected message store may be compared bit by bit to check and determine the equivalence therebetween. Additionally, the respective bits of the received message comprising the parity bit and the address bits may be compared to determine whether parity of the received message checks and whether the message as received is addressed to the receiving terminal.

In the event the parity and address portions of the received message compare with that information or data stored in the expected message store, the output of the comparator 101 would be logically true and gate 109 would appropriately signal the arithmetic unit 75 of the line-discipline processor 41. In response to this indication of comparison, the arithmetic unit 75 of the line discipline processor appropriately sets the memory address register 77 to withdraw from memory 43 an appropriate positive acknowledgement if it was determined that the line-discipline processor 41 is properly conditioned to respond to the inquiry message i.e., either a poll or select inquiry. Thereafter the message to be transmitted to the central processor may be read from message memory 43 via the logic gate 89 with an appropriate timing signal to the buffer store 47 for transmission to the central processor 11 via the communication link 22.

In connection with the above description, it is to be understood that only the remote terminal 23 to which a particular inquiry message is addressed responds by sending a positive or negative acknowledgement to the central processor via the communication link. In this manner the central processor 11 is able to establish and maintain a sequence or series of inquiry messages thereby providing orderly data transmission. However, as hereinabove explained this slave-type response from the addressed remote terminal does not permit flexibility in those instances, for example, where the terminal requires a mode of transmission different than that characterized by a particular received inquiry message.

In accordance with the principles of the present invention, a terminal is given increased flexibility by providing logic circuitry, responsive either to the operator or to a received message, for selectively modifying or changing the address of the terminal. Referring to FIG. 3 it may be seen that the gates 121 and 123 couple the expected message store 103 to terminal address control register 125. The input to the terminal address control register 125 is coupled via the gates 127 and 129 to the instruction decoder 59 of the remote processor 33 and the decode register 79 of line-discipline processor 41. In this manner either the operator attending the remote terminal 23 or the line-discipline processor 41 under its microprogram control or in response to a received command, may appropriately energize the gates 127 and 129 to effect a change in the address of the remote terminal as stored in the expected message store 103.

This change may be accomplished by withdrawing the address from the expected message store 103 and replacing it with a new address determined by the line-discipline processor and transferred to the terminal address control register 125. As shown the gates 121 and 123 are arranged to interchange data between the terminal address control register 125 and the store 103. The gate 121 when energized couples information from the expected message store 103 to the register 125 while the gate 123 is arranged to couple information from the terminal address control register 125 to the expected message store 103. In this manner the addressed portion of an expected message format, as described hereinabove in conjunction with table I, may be modified or replaced. In modifying the terminal address it is of course desirable that the address not be changed so as to correspond with any other terminal then presently in the communication net link. This control function could of course be assigned to the microprogram of the line-discipline processor 41.

By including terminal address control logic 45 (FIG. 2) which as shown in FIG. 3 may comprise a terminal address control register 125 and appropriate logic gating 121, 123, 127 and 129 for controlling the exchange of address data in the expected message store 103, greatly enhances the communication responsiveness and capability of the remote terminal. This terminal address control logic 45 relieves the terminal from the necessity of slavishly responding to each inquiry of the central processor. For example if the operator is performing a particular routine during which it is undesirable to be interrupted, the operator may appropriately enter information via the keyboard 37 which through decoder 59 energizes the gate 127 to initiate the exchange of terminal address information between the terminal address control register 125 and expected message store 103. By changing the address portion of the expected message stored in the expected message store 103, the operator for example insures that the terminal will not recognize a message which the central processor 11 has transmitted to the terminal under its unmodified or normal terminal address.

In accordance with another aspect of applicant's invention, when the terminal 23 is adapted to operate in a poll and select mode of transmission, it is preferable to have separate message address storage locations in the expected message store 103 for the respective poll and select inquiry messages. Thus by changing the terminal address for either a poll or select as determined by the operator or upon command from the central processor, the terminal 23 may continue to respond to the inquiry messages for which the remote terminal address portion of the expected message has not been modified. As will hereinafter be discussed in conjunction with FIG. 5, the central processor's inquiry message program may be designed to include an automatic branch or jump to the other type or mode of inquiry message in the event an addressed terminal fails to respond by sending either a positive or negative acknowledgement. In this manner an addressed remote terminal may cause the central processor to change from one mode of inquiry message to the other by changing its address for a particular mode thereby causing the terminal to fail to recognize any message which is addressed to it under its old address thereby inhibiting the transmission of a response, i.e., ACK or NAK, from the addressed terminal.

Referring now to FIGS. 4 and 5 in conjunction with the logic diagram shown in FIG. 3 two methods of operating applicant's remote terminal in a communication net will be explained. The flow diagrams of FIGS. 4 and 5 represent the states or sequential steps that the logic of the terminal performs in order to determine whether a received inquiry message is addressed to it, and if so what action should be taken.

As shown in the flow diagrams of FIGS. 4 and 5, the line-discipline processor as determined by the state machine 81 normally resides in the idle mode 135. In the idle mode, the state machine 81 conditions the logic of the line-discipline processor 41 to look for an expected message format. As shown the receipt of a transmission reception signal RX, for example a carrier detect, takes the line-discipline processor out of the idle mode and into the message receive state 137. In the message receive state the inquiry message is stored in the buffer 47. After, for example, an appropriate number of data bits are received, as determined by the inquiry message format the state machine 81 generates an appropriate signal to put the line-discipline processor 41 in the parity check mode 139. As shown in FIG. 3 this might be accomplished by withdrawing the appropriate parity bit from the expected message store 103 and comparing it in comparator 101 against the received parity bit. If the parity checks properly, the state machine 81 sequences or steps the line-discipline processor to the address check routine stage 141, while if the parity check is negative the line-discipline processor would be returned to the idle state 135.

If the terminal address has not been changed and the receiving terminal is the terminal to which the inquiry message is addressed, then as shown in FIG. 4 the remote processor would move to the respond-to-inquiry state 143 in which the line-discipline processor 41 would through its microprogram generate the appropriate acknowledgement, i.e., ACK or NAK, in accordance with its state of readiness at that time. If for example the message was a poll and the address terminal had a message to be sent to the central processor 11, the state machine 81 would move the line-discipline processor to its text transfer state 145 wherein the sequence of withdrawing the message from memory 43 and transferring it to the buffer store 47 would begin. In accordance with its microprogram, the line-discipline processor would generate an appropriate check bit or sequence for inclusion in the message as hereinabove described in conjunction with table I. If the message were properly received at the central processor 11, it would respond with an acknowledgement stating that the message had been properly received whereupon the line-discipline processor 41 would move to state 147 to recognize that the parity either checked or did not check and go through the appropriate retransmit or return to its idle state 135.

If in the address message check state 141, the address of the received message did not favorably compare with the address portion of the expected message stored in expected message store 103, then either the message was not intended for the receiving terminal, or it was garbled during transmission which would be an error, or the message portion of the expected message format stored in store 103 has been changed.

The response of the terminal 23 at this junction would depend upon whether the response was to be active or passive. As shown in FIG. 4 if the response is active then upon failure of the inquiry message check to correspond, the line-discipline processor would move to state 149 at which it would determine whether its terminal address had been changed or modified. If it had not, the terminal, under control of the state machine 81, would ignore the message by returning to the idle state 135. If the terminal address of the receiving terminal 23 had been changed and it was in the active response mode, the line-discipline processor 41 would move to the control character state 151 in which it would generate an appropriate control character for transmission to the central processor 11. This control character, for example, could signify to the central processor 11 from the addressed terminal to change transmission modes, i.e., poll to select or the reverse and to again address an inquiry message to it. In this mode of transmission, the addressed terminal would then return to the idle state 135 and await the receipt of the next inquiry message from the central processor.

As hereinabove described it is desirable in accordance with one aspect of the present invention to have separate poll and select addresses stored in the expected message store 103 whenever the terminal operates in the poll-select mode. As shown in FIG. 5 after the terminal has progressed to the parity check state 139 if the parity checks positively then the line-discipline processor moves to state 155 in which the received inquiry message is compared to determine whether it comprises a poll or select inquiry message. This comparison is made as hereinabove described by comparing appropriate bits of the received inquiry message with correspondingly designated bits that are stored in the expected message store 103. If a true comparison is made between the received and stored message, the gate 109 (FIG. 3) signals the arithmetic unit 75 of the line-discipline processor 41 as to which type of inquiry message has been properly received. Thereupon the line-discipline processor advances to the appropriate retrieve message address state 157 or 159, depending upon the type message received. As shown the retrieve address states may be independently modified by either an operator input or the remote command by placing the state machine in the modify address mode state 161.

As hereinabove described in conjunction with FIG. 4 the activity of the line-discipline processor 41 whenever the address portion of the receive message fails to compare with that of the stored inquiry message format is determined by whether the communication system and particularly the terminals are in the active or passive mode. As described in conjunction with FIG. 4, in the active mode the remote line-discipline processor 41 transmitted a control character to the central processor in place of the normal ACK or NAK response thereby alerting the processor of its new address.

Referring now to FIG. 5, if the message address and stored terminal message address compare, state 141 is positive (yes) and the line-discipline processor moves successfully through states 145 and 147, as hereinabove described in conjunction with FIG. 4 to complete the transfer of the message from the terminal 23 to the central processor 11. However if the remote terminal 23 is in the passive mode, i.e., no control address signal is to be sent to the central processor, and the address portion of the inquiry message does not compare with the terminal address in state 141, the terminal returns to the idle state 135 whether the address of the remote terminal was altered or not as shown by state 165. However in the passive state the central processor is preferably programmed to change the message inquiry mode of transmission, i.e., from poll to select or from select to poll, and to readdress the terminal 23 which failed to respond to a previous inquiry message addressed to it as shown in state 167. Actually, in the passive mode the remote terminal 23 returns to the idle state 135 and the central processor 11 after it changes inquiry mode readdresses the terminal which failed to respond to the previous inquiry message thereby accommodating the terminal with the type inquiry message which it requested by its passive action, i.e., its failure to respond to an inquiry message addressed by the central processor to it.

In the foregoing description and drawings applicant's invention has been described in conjunction with a remote terminal operating in the poll and select environment. It is to be understood that this description is by way of explanation and is in no way intended to limit applicant's invention. Thus, for example, in addition to separate poll and select addresses as illustrated in conjunction with FIG. 5, the remote terminal may be adapted to have an additional address for use for example in a broadcast mode. The broadcast mode may be defined as that transmission mode in which a predetermined number of remote terminals are grouped under a common broadcast address with each terminal of the broadcast group being able to respond appropriately, for example in a predetermined sequence, in response to the receipt of a broadcast message addressed to that group.

Claims

What is claimed is:

1. An improved addressable data terminal operatively coupled in a data communication system with a central processor through a communication net, said improved addressable data terminal comprising:

terminal address control means at each one of the data terminals including memory storage means for storing a designated terminal address data for such one terminal, said address data being in coded form and distinguishable from respective data of others of the data terminals in the system,

comparator means for comparing the address portion of each received inquiry message with the terminal address stored in said terminal address control means to determine if the portion of the received message corresponds to the address data of said receiving terminal, and

terminal address modifying means for selectively modifying said terminal address data so as to change the address data used by said comparator means for determining whether the address portion of a received inquiry message corresponds to the stored terminal address data.

2. The improved addressable data terminal defined in claim 1 wherein said terminal address modifying means includes

expected message storage means for storing remote terminal address data in binary coded form, and

means for selectively storing the modified terminal address data in place of previously stored terminal address data in said expected message storage means.

3. The improved addressable data terminal as defined in claim 1 wherein said terminal address modifying means comprises

register means for storing a sequence of data bits uniquely designating the original data terminal address in a predetermined coding system,

means for modifying said data bits stored in said register means for selectively altering said original data terminal address data to generate a new data terminal address data bit sequence different from the terminal data bit sequence of other terminals in said system, and

means for selectively restoring said original data terminal address data bit sequence to said register means.

4. The improved data terminal as defined in claim 1 wherein said terminal is operable in a poll-select transmissiom mode and additionally including

separate storage means for storing distinct terminal address data designating respectively a poll-inquiry message address and a select-inquiry message address.

5. The improved data terminal as defined in claim 4 wherein said terminal address modifying means includes means for selectively and independently modifying the address data representing the poll-inquiry message address or the select-inquiry message address respectively.

6. A system for transmitting data between a central data site and plurality of remote data terminal sites, said system comprising

means at the central data site adapted to transmit a sequence of inquiry messages having an address portion and non-address portion to the remote terminal data sites,

means at each remote terminal data site to temporarily store said received inquiry messages,

means at each remote terminal data site to store terminal designating address data representing the remote terminal data site,

means at each remote terminal data site for comparing said address portion of said received inquiry messages and with the stored terminal address data, and

means for selectively modifying the terminal address data stored at at least one of said remote sites.

7. A method of transmitting data over a communication link between a central processor site and designatable ones of a plurality of addressable remote data terminals coupled via said communication link to said central processor site, said method comprising the steps of

generating a sequence of inquiry messages at said central data processor site,

transmitting said inquiry messages from said central processor site to said remote data terminals via said communication net in a multidrop mode,

storing terminal address data at each remote terminal, said terminal address data uniquely designating the address of the remote terminal at which it is stored,

temporarily storing received inquiry messages at each of said terminals receiving said inquiry message,

withdrawing from storage at each remote terminal receiving an inquiry message the terminal address data designating the address of that terminal,

comparing said terminal address data with an address portion of said inquiry message at each remote terminal receiving said inquiry message to determine whether such received message is addressed to the terminal receiving such inquiry message,

enabling the addressed terminal to respond to said received inquiry message, and

selectively changing the terminal address data stored at at least one of said remote data terminals to selectively inhibit such terminal from recognizing an inquiry message having an address portion corresponding to the original terminal address data of said terminal before said terminal address data was altered.

8. The method defined in claim 7 additionally including the steps of

recognizing the failure of an addressed terminal to respond to an inquiry message addressed to it, and

changing the type poll-select inquiry message whenever an addressed terminal fails to respond to an inquiry message of one type addressed to it.

9. The method of claim 7 additionally including the step of transmitting a control character from a data terminal to said central site whenever said data terminal receives an inquiry message addressed to it and its normal terminal address data has been modified.

10. The improved addressable data terminal defined in claim 1 additionally including means responsive to said comparator means for transmitting a predetermined message to the central processor.