Display Device Including Roll And Crawl Capabilities

Abstract

Data display apparatus is provided with the capability for moving the lines of data vertically upward across the face of the display tube, or characters of data from right to left across the face of the display tube. Characters stored in a memory are read out by addressing the memory in synchronism with a TV display scan.

Description

BACKGROUND OF THE INVENTION

In an application for a display system by Martin N. Kite, Robert E. Gettings and Roman A. Adams, which was filed on Jan. 2, 1968, Ser. No. 704,967 and which is assigned to a common assignee, there is described a display system which functions at frequencies such as those used in home television receivers, and displays data, which is entered into this system, either by means of a keyboard or tape, which are received over a wire. The display system has a storage facility into which the incoming data is entered. The data is thereafter read out, decoded, converted into signals which can be displayed and thereafter displayed.

This invention relates to display apparatus which functions to produce the appearance of lines of data being displayed moving upward from the bottom towards the top of a display tube. Apparatus is also provided for producing the effect of characters of being displayed, the data moving in lines from the right to the left across the face of the display tube.

A feature of this invention is the provision of a display system which operates at frequencies used in home television receivers and affords the ability to display information moving in lines vertically across the face of the display tube, or characters moving in lines from right to left across the face of the display tube.

Another feature of this invention is the ability to effectuate such motion of the data, smoothly and at different rates.

In accordance with this invention, data is called out of a memory to be displayed from an address which is provided by a line display counter and a character display counter. Means are provided, when it is desired to roll the data upward, to increase the count of the line counter by one, at the end of a predetermined time whereby the data appears to be moving upwardly.

Where it is desired that the data perform a character crawl operation, then at the end of a line of data which is displayed, the character counter has its residual count incremented by one rather than being reset to zero, whereby a character which, ordinarily for example is at the end of the line which is displayed, successively is displayed in positions from the right side to the left side of the line.

Other features are provided for ensuring the proper blanking, avoiding a "jumping" of the data, and also providing for the display of new or incoming information while in the roll or crawl mode of operation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating the general layout of a display system wherein this invention is employed.

FIG. 2 is a detailed block diagram of a display control unit which is employed herein.

FIG. 3 is a block schematic diagram of the display counter control circuit 32.

FIG. 4 is a block schematic drawing of the X- and Y-matrix counters.

FIG. 5 illustrates a character constructed at selected dots in a dot matrix in accordance with this invention.

FIG. 6 is a block schematic of the display line and character counters.

FIG. 7 is a block schematic diagram of the cursor generator and line character counters.

FIG. 8 is a block schematic diagram of the memory address generator.

FIGS. 9A, 9B and 9C and 9D constitute block schematic diagram of the roll and crawl circuits in accordance with this invention.

FIGS. 10 and 11 are schematic diagrams of logic circuits used in the invention.

FIG. 12 is a block schematic diagram of roll and crawl loading logic.

FIG. 13 is a block schematic diagram of another arrangement for achieving roll and crawl.

FIG. 14 is a waveform diagram shown to assist in an understanding of this invention.

FIG. 15 is a block schematic diagram of a circuit used for generating logic signals used in the invention.

FIG. 16 is a block schematic of logic circuits used to generate the address-incrementing pulse.

FIG. 17 is a block schematic diagram of a circuit used to generate extra pulses for smoothing the roll operator.

FIG. 18 is a block schematic circuit of a blanking signal generator.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The descriptions of FIGS. 1 through 8 are substantially identical with the descriptions of FIGS. 1 through 8 found in the previously indicated application for the display system by Martin Kite et al. This description is being repeated here in order to afford a better understanding of the invention.

Referring now to FIG. 1, a general arrangement in accordance with this invention would comprise a standard TV monitor 10, (more than one may be used if required,) which displays human readable data. Digital data may be entered into the system from any data source, illustrative of which there is shown a tape reader 12 and/or a typewriter keyboard 14. This data is fed into a display control unit 16 whose function it is to store the data in a manner so that it may be properly read out for display on the TV monitor or sent to some other utilization device 18, such as keypunch, a printout device, etc. The display control unit also includes a novel character generator which, in response to the data representative code produces the video signals which are displayed as readable data on the TV monitor 10.

FIG. 2 is a block schematic diagram illustrating details of the display control unit. A tape reader 12 or a typewriter keyboard 14 are well known, and commercially available pieces of hardware. For the purposes of this invention, and in the manner that they function normally, the tape reader produces as an output eight binary signals together with a strobe pulse, each time a character is read out. Seven of the eight bits represent an alphanumeric character. The eighth bit is parity. The keyboard 14, which can be a facsimile typewriter, also produces at its output seven-bit character signals with an eighth bit having parity significance, together with strobe pulse. In each of these cases, the signals are produced in parallel on eight data lines and a strobe pulse is produced on a ninth line. The signals are applied to interface circuits 60.

Basic operating synchronization signals for the display control unit may be obtained from an external source of sync signals 16. This external sync signal source may comprise either a television station sync generator, or a composite video signal such as may be obtained from a videotape device. Signals from either of these may be processed to provide horizontal sync signals and vertical sync signals. If composite video is provided, this is applied directly to an OR-gate 18 the output of which goes to a sync separator circuit 22. This functions in well-known manner to separate the horizontal sync from the vertical sync. If composite video is provided by the external video signal source, then this is applied to a video blanking circuit 20, which constitutes well-known circuitry for applying a blanking pulse to the composite video during the video interval. This leaves composite sync signals. These are applied to the OR-gate 18 and thereafter to the sync separator circuit to be separated into horizontal and vertical sync signals.

The composite sync signals, which are the output of the OR-gate 18 are supplied, at the output of the display control unit, to the TV monitor which is used to reproduce the video signals. The vertical sync or vertical drive pulse which is the output of the sync separator 22 is used to reset a display character counter 24, and a display line counter 26, to assure that each field which is to be displayed starts properly. The display character counter has its count advanced by one for each character being displayed on a line of characters. The display line counter 26 has its count advanced by one for each line of characters which is displayed. Thus, the address of the last character being displayed is always available from the output of these counters. Actual video display commences after the first 24 horizontal sync pulses which follow the vertical sync pulse and continues until 16 rows of character video are displayed.

There are 24 characters on each line. The first horizontal sync pulse initiates the operation of a display counter control circuit 32. The counter control circuit can start a gated clock circuit 28 where frequency equals the picture element rate of 8 megacycles. The start of the operation of the gated clock is delayed, following the horizontal drive pulse, by approximately 12 microseconds until the first character position in a line of characters is reached. The clock turns on and then continues to operate until the final character in a line is completed. Each character position is defined by a dot matrix in which only those dots are illuminated which form a desired character. Each character uses nine dot positions along a line for the actual character display plus five guard band positions. The total number of clock pulses generated per line is therefore 14 times 24 (24 characters per line) or 336 pulses. The clock is turned off by a clock clamp pulse at the end of a line and is turned on again at the beginning of the next line.

The display counter control also receives vertical sync pulses which are used for reset purposes. The gated clock output is used to drive an X-matrix counter 34, causing it to count through 14 counts, nine counts of which correspond to nine horizontal positions in a character dot matrix starting from left to right, and the three further counts provide for the guard band or character spacing. The X-matrix counter 34 therefore goes through a full cycle of operation for each character. Count output signals from X1 to X12 are derived therefrom. Each time the X-matrix counter completes a cycle of 12 counts, it overflows. Its overflow is applied to the display character counter 24 to cause it to advance one count. The display character counter has a count capacity totaling 24, corresponding to the number of characters displayed in each row. Each time the display character counter overflows, it sends the overflow pulse back to the display counter control 32 which in turn uses this overflow pulse, also termed a clock clamp pulse, to turn off the gated clock 28. The gated clock then waits for the next horizontal sync pulse before commencing operation again. The overflow output pulse of the display counter control also enables a Y-matrix counter 36 to be advanced one count in response to the next horizontal sync pulse.

The Y-matrix counter has a total count capacity of 14 counts. Eleven of these are used to count the vertical dot matrix locations of a character. Three of these are for a guard band space between lines of characters. Count outputs designated from Y1 to Y14 are derived therefrom. The overflow output of the Y-matrix counter 36 is applied to the display line counter 26 to cause it to advance one count. The display line counter has a total count capacity of 16 corresponding to the 16 lines of characters which are displayed in one field of this invention.

A character generator 38 is provided which has applied thereto the count outputs of the X- and Y-matrix counters. In response to these, the character generator generates video signals representing each one of the alphanumeric characters which the system is capable of displaying. In an embodiment of the invention which has been built and successfully operated, the character generated created 64 alphanumeric characters. The output of the character generator is applied to the video selector 30. This functions to select, in response to a seven-bit alphanumeric code derived from the core memory 40 of the system, a specific character from all of those being applied to the video selector, which character is represented by that alphanumeric code. More specifically, the core memory 40 supplies coded signals, one character at a time to an output register 42, which in turn applies them to a data decoder 44 which decodes them successively and enables the video selector to select the proper video character signals. In addition, the video selector 30 is capable of being modulated by a flash control circuit 46. The flash control circuit contains an oscillating circuit that may be turned on by a flash code which is stored in the memory and which is a "nonviewable" character. The flash control 46 remains on until either the next following horizontal drive pulse appears or a space code which separates the following word appears. Operation of the flash control 46 causes all characters of a word that are displayed thereafter to flicker and thus call attention to itself.

After each character is displayed, an unload cycle of the core memory 40 is made to occur to place the alphanumeric signals corresponding to the next character of a row in the output register 42. The address from which the character in core memory is read is provided by the count conditions of the display character counter and display line counter. A specific core memory address is provided for each of the 384 counts which these counters provide. The display character counter 64 and display line counter 66 have their outputs connected to a memory address generator 67, which produces the address information for the core memory 40.

The output of the video selector 30, which comprises the character video signals, is applied to a mixer circuit 50 and to an output terminal 52. The mixer circuit combines character video signals with a cursor signal which is provided from a cursor generator 54. The cursor video signal has approximately one-half of the intensity of the character signals. The cursor video signal indicates, on the pattern displayed on the face of the television monitor, the corresponding character signal address in the memory into which the next input character digital signals will be placed when the system is in the write mode. The mixer output is applied to an output terminal 55. In addition, composite sync signals from the output of the OR-gate 18 are made available at a terminal 56. These three signals, namely composite sync, character video with cursor, and character video without cursor, are thus available at the three output terminals for being applied to a television monitor for display.

The tape reader 12 and the keyboard 14 have their outputs connected to the interface circuitry 60, The interface circuitry serves to check the incoming data lines from either of the two inputs upon receipt of its associated data strobe presented on the strobe lines. If the data is alphanumeric data to be displayed, the input strobe signal triggers a single load cycle of the core memory. This function is provided by the data input control circuit 62. In the load cycle operation, the input character is loaded into the core memory at an address which is determined by the count outputs of the cursor character counter 64 and the cursor line counter 66. The cursor generator 54 detects coincidence between the cursor counters and the display counters and causes the load operation to occur when these counters have the same count. As previously indicated, this occurs at an address in memory corresponding to the position visually indicated by the cursor on the output monitor. Thus, the load operation into the core memory occurs at a location which corresponds to the location of the cursor. From the foregoing it will be appreciated that the memory should provide storage for 512 alphanumeric characters of eight bits per character.

Other signals from the interface circuit are provided in response to the incoming control codes. These specific control codes do not result in a memory load cycle but rather generate signals on appropriate lines out of the interface circuit. These lines perform such functions as cursor on-off, cursor right, cursor left, cursor new line, cursor home, cursor up, cursor down, etc. This will become more clear as this explanation progresses.

During the write mode, as each character is loaded into the core memory, a single pulse advances the cursor character counter by one count. When the cursor character counter overflows, its output advances the cursor line counter. Input load operations therefore, cause the cursor to be advanced character by character and line by line in a manner similar to the typing operation of a typewriter.

The output register 42 may also be used if desired to transmit data which is within the memory to an external utilization device 19 such as tape or a transmitter or an external printer. An "end of line" or "end of message" circuit 69 driven by the cursor counters, may be used in conjunction with external transmission of data to signal their occurrences to external equipment.

DISPLAY COUNTER CONTROL CIRCUIT 32

FIG. 3 is a block schematic diagram of the display counter control circuit. This circuit arrangement functions to initiate operation of the gated clock oscillator at the proper time so that the subsequent matrix and display counters may commence to operate at the proper time and in the proper time sequence. In a television-type display both a top margin as well as a left side margin must be provided for. Essentially the display counter control circuit provides for these delays. The first vertical sync pulse which is delivered by the output of the sync separator 22 is applied to a flip-flop 102 to drive it to its set state. This causes the Q output of the flip-flop to become high. The Q output of the flip-flop enables an AND-gate 104 whereby it can pass horizontal sync pulses which are received from the sync separator. These are applied to drive a 24-count counter 106. This counter provides a top margin delay. The 24th count of the counter is used to reset the flip-flop 102 and sets a flip-flop 108. The next vertical sync pulse enables flip-flop 102 again and simultaneously resets the 24-count counter so it can begin counting again.

The Q output of flip-flop 108 enables an AND-gate 110 to pass horizontal sync pulses. The output of the AND-gate 110 is applied to a delay circuit 112. The delay circuit provides a delay whose duration is determined by the size of the desired left-hand margin on the display tube. The output of delay circuit 112 sets a flip-flop 114. The Q output of the flip-flop 114, which is high in response to its set input being enabled, is applied to the gated clock oscillator to cause it to commence to produce clock pulses.

Flip-flop 114 is reset by a B16 output, also called a clock clamp pulse, which is received from the display character counter which counts the number of characters displayed on a line. After the last character has been displayed flip-flop 114 is reset so that at the commencement of the next line, signaled by the appearance of another horizontal sync pulse, a delay is provided on the left-hand side of the display tube. The flip-flop 108 is reset by a W8 signal which is provided by the display line counter. This signal occurs after the last character on the last line has been displayed. Accordingly, flip-flop 108 cannot be set again until the counter 106 counted through its next 24 counts to provide the top margin delay.

X- AND Y-MATRIX COUNTERS (34-36)

FIG. 4 is a block schematic diagram of the X- and Y-dot matrix counters. A character, in accordance with this invention, is made by illuminating selected dots in a dot matrix that extends nine dots in a horizontal direction and eleven dots in a vertical direction. There are five dot spaces allowed between characters on a line to serve as a guard band, and three dot spaces between lines of characters, also to serve as a guard band. Thus, the counter that counts for the horizontal dot placement will have a count capacity of 14 and the counter that counts for the vertical dot placement will have a count capacity of 14.

In FIG. 4, there is shown a horizontal counter 116 which is made up of six flip-flops, respectively 116A through 116F. Each one of these flip-flops is of the type known as "JK" flip-flop. It is well known and commercially purchasable.

Each flip-flop has J, K and C inputs, and Q and Q outputs. When a clock pulse is applied to its C input the flip-flop will transfer to its outputs the state of its J and K inputs. Thus, if the J input is high and the K input is low when a C or clock pulse is applied to the C input, the Q output will be high and the Q output will be low. The J and K inputs are applied to the respective flip-flops from the Q and Q outputs of the respective flip-flops through NAND gates. A NAND gate behaves like an AND gate followed by an inverter. Accordingly, when the two inputs to the NAND gate are high, its output is low and when the inputs to the NAND gate are low, its output is high. When one of the inputs is high and the other is low, the NAND gate output is high.

The counter 116 has the Q and Q outputs of the respective flip-flops 116A through 116E respectively connected to the J and K inputs of the immediately following flip-flops through the respective NAND-gates 117A and 117A' through 117E and 117E'. NAND-gates 118A and 118A' are connected to the respective J and K inputs of flip-flop 116A. The NAND-gate 118A has one input connected to the Q output of flip-flop 116F which is designated as H6. The NAND-gate 118 has its inputs respectively connected to the Q outputs of respective flip-flops 116E and 116F. These Q outputs are respectively designated as H5 and H6.

It should be noted that whenever a designation is shown for only one NAND gate input, the other input of the NAND gate is connected to a bias source 120. As the result, a one-input NAND gate acts as an inverter to invert the input.

The respective Q and Q outputs of flip-flops 116A through 116F are respectively designated as H1 through H6 and H1 through H6. These are collected by the 12 NAND gates, respectively 121 through 135, to provide 14 output count indications in their not form. These are designated by X1 through X14. Thus, upon the occurrence of an H1 and H2 input to NAND-gate 121, it will produce an output designated as X1, which is the first output count of the counter. H6 and H7 occurring at the input of NAND-gate 126 produce an X6 output, H5 and H6 occurring simultaneously at the input of NAND-gate 132 produces an X12 output or a not 12 count output.

The manner in which the counter 116 functions is for each one of the flip-flops to successively assume its one state or state with its Q output high and thereafter each flip-flop successively returns to the state with its Q output high. The counter is cyclic and will repeat this operation in response to successive applications or clock pulses from the gated clock oscillator 134. This oscillator comprises a circuit which, in the presence of an enabling input from flip-flop 114 in FIG. 3, provides successive clock pulses to the counter 116.

To illustrate how the counter works, assume initially that all the flip-flop stages are in their zero state. The Q output of flip-flop 116F is high. Upon the occurrence of the first clock pulse from the gated clock oscillator 134, flip-flop 116A will be driven to its one state with its Q output high, since its J input is now high and its K input is low. Upon the occurrence of the next clock pulse, flip-flop 116B assumes a one state. This progresses with successive clock pulses until flip-flop 116F assumes its one state. Since, the K input to flip-flop 116A is driven to its high state in response to H6 and H5 which are connected to the NAND-gate 118A being high, flip-flop 116A is driven to its zero state with its Q output high. This zero state of the counter 116A is successively passed with the occurrence of each clock pulse to all of the flip-flops in the counter. From an understanding of the operation of this counter, it should now be understood how the inputs to the NAND-gates 121 through 132 operate to produce the indicated count outputs.

Counter 140 is identical in construction with counter 116. Accordingly, it can produce 14 count outputs. It advances in respect to pulses obtained from the output of gate 110 in FIG. 3. These are essentially horizontal sync pulses. The NAND-gates 141 through 150 are connected to the flip-flop outputs for the purpose of deriving the respective counts one through 14 which are in their "not" form. The Q and Q outputs of the respective flip-flops of the counter 140 are respectively designated from V1 through V7 and from V1 to V7. The counter 140, which counts for the vertical dot positions, is given a count capacity of 14 counts. Since it is customary to reference the bottom line of a character as a first position and the top of a character as the last position, assuming each location or position of a line were given a number, the bottom of a character would be considered in the Y1 location and the top would be considered in the Y11 location. Therefore, while the present invention displays a character in television raster form, where the top of the character appears first and the bottom last, the count output of the Y-matrix counter is given a reverse count designation. That is, the first count of the counter is designated as Y11, the 11-count of the counter is designated as Y1, V1 and V7, which are generated when all of the stages of the counter are in their zero state, are combined to produce a Y14 count. The reasoning for this arrangement will become more clear with a description of FIG. 5.

FIG. 4 shows how pulse signals X1 through X14 and Y1 through Y11 and Y14 are generated. In addition to these signals, other logic signals are required for the operation of this invention. Thus, in FIG. 4, a NAND-gate 152 is used to collect X10, X11, X12, X13 and X14 together with the Q output of a flip-flop 154. The Q output of the flip-flop 154 is enabled when a Y14 signal is applied to its clock input. The flip-flop remains set until the occurrence of a Y12 signal (Y5 and Y6). This is produced when counter 140 provides a V5 and V6 output to a NAND-gate 156. Thus, flip-flop 154 is set at the end of a counting cycle of counter 140 and is reset upon the occurrence of the 12th count output of the flip-flop 140. The output of NAND-gate 152 is inverted by NAND-gate 158 to produce a signal designated as PP1. The X12 of "not 12" count of the counter 116 is inverted by a NAND-gate 160 to produce an X12 count.

EXAMPLE OF A DOT MATRIX CHARACTER

FIG. 5 shows the appearance of a character, A, constructed to selected dots in a dot matrix in accordance with this invention, with the appropriate designations applied to the possible dot locations which may be used for representing a character. There may be as many as 32 of these characters displayed in a line across the face of the display tube. There may be as many as 16 of these lines displayed vertically. These values are given by way of illustration of an operative embodiment of the invention which has been built, and are not to be construed as a limitation upon the invention.

DISPLAY LINE COUNTER AND DISPLAY CHARACTER COUNTER

The display line counter and the display character counter (FIG. 6) respectively 26 and 24 are each the usual binary counters with respective count capacities of 16 and 32. Each time an X10 signal is generated by the X-matrix counter 34, the display character counter is advanced one count. Each time a Y14 signal is generated by the Y-matrix counter 36, the display line counter is advanced one count. The display character counter has its respective outputs designated B1, B1, B2, B2, . . . through B16, B16. The display line counter has its outputs designated as W1, W1, W2, W2, . . . W8, W8. The character counter is the one which keeps track of the number of characters on a line, for which 24 are allowed. The B16 output of the character counter, referring back to FIG. 3, is the output which turns off the gated clock oscillator. This occurs when the last character in a line has been displayed. The last output of the display line counter, which is designated as W8, is the one which turns off flip-flop 108 in FIG. 3. This occurs at the end of the last line which is displayed.

CURSOR GENERATOR 54 AND COUNTERS 64, 66

The cursor X-counter 64, as shown in FIG. 7, is a reversible counter having any of the well-known reversible counter constructions. Its 32 outputs are respectively designated at A1, A1, through A16, A16. This counter is advanced by receiving a signal from whatever external data input device is employed. A signal for advancing the counter is supplied with each character when the display control is is in its write mode. Such a signal is supplied from the typewriter to the "cursor right" input of the counter. The counter may be made to count in reverse by receiving an input signal on its "cursor left" terminal, from the typewriter keyboard. The cursor signal, which by way of example has been indicated as a background display of half intensity for a character, will occur at the proper time, at a location along a line determined by the count output or by the address represented by the count output of counter 64.

A cursor Y-counter, which is similar in construction and operation to the cursor X-counter, has a 16-count capacity and is also reversible. This counter is advanced by signals from the keyboard applied to its "cursor down" terminal and is caused to count backwards in response to pulses received which are applied to its "cursor up" terminal. This counter establishes, by its output, the line address on which the cursor signal is displayed. The output of this counter is designated by Z1, Z1 to Z8,Z8, with the Z8 signal being the 16th or highest count output of the counter.

The cursor is displayed only when there is a concurrence in the address indicated by the cursor counters and the display counters. To achieve this operation, a comparator circuit 162 compares the address outputs of the counter 64 and the counter 24, shown in FIG. 6, and when there is an identity it provides an output signal to a NAND-gate 164. Another input to this NAND gate is the PP1 signal which is generated by the logic shown in FIG. 4. This PP1 signal, in view of the presence of the inverter 158, (in FIG. 4), is present from X1 through X9 time. From X10 through X14 time, the PP1 signal is not present and no output is obtained from NAND-gate 164. Upon the occurrence of a comparator signal and a PP1 signal, a JK flip-flop 166 is driven so that its Q output is high. This flip-flop is reset upon the occurrence of an X10 signal.

The occurrence of the cursor on a particular line is determined by the output of a comparator 170. This comparator compares the address provided by the output counts of the cursor counter 66 and the display line counter 26. The output of the Y-comparator 170 is applied to the NAND-gate 168. The typewriter keyboard 14 will have a key which can be operated to actuate a circuit which can provide a voltage to a third input to the NAND-gate 168 designated as the "cursor on-off" input. When this voltage is not present, no cursor is provided. This circuit is shown subsequently herein in FIG. 18.

Therefore, NAND-gate 168 functions to provide a cursor signal output when there is a concurrence in the addresses at the outputs of the cursor X- and Y-counters and the display character and line counters. Since the display counters are sequenced continuously through their count states, there will be concurrence of cursor and character counters only at one location over the entire face of the display tube. Accordingly, the cursor will be displayed at one character location only.

The memory storage device which is employed with this embodiment of the invention should be able to store, for readout onto the face of a display tube, as many characters as will be displayed across the face of the tube. The example given by way of illustration herein is 24.times.16 or 384 characters, or more correctly the code bits to represent 384 characters. Thus a total of at least 8.times.384 or 3,072 bits is required. There should be a character location in the memory which corresponds to the location on the display tube face at which that character is to be displayed. The memory must be addressed successively for the purpose of successively reading out the characters for display. The successive addressing of the memory is a function of the display counters.

The address of a location in the memory into which data is to be entered is indicated by the address of the cursor. This address can be changed by applying signals to the cursor counters which establish the line and the location along the line desired for the cursor, and thereby the location in the memory into which data will be introduced. The cursor counters may be advanced by actuation of the typewriter keyboard in a normal manner for the purpose of writing character by character into the memory. Provision may also be made for advancing the cursor counters when input of characters is from a tape reader or any other source.

MEMORY ADDRESS GENERATOR 67

FIG. 8 is a schematic representation of a memory address generator. By way of illustration, and not to serve as a limitation, a magnetic core memory was employed with an embodiment of this invention which was built and operated.

The memory address generator addresses the memory for the purpose of reading out the data stored therein which is converted into video signals and then displayed. The address generator also provides the address of the locations into which incoming data is stored. The display character and line counters provide the address information for instructing the memory as to the location from which readout is to occur. The cursor X- and Y-counters provide the address information for instructing the memory as to the location at which data is to be entered.

As may be seen in FIG. 6, the memory address generator merely comprises a number of gates which are connected to the outputs of the respective display and cursor counters. The set of gates connected to the display counters are enabled during the process of readout whereby the address presented to the memory is that indicated by the display counters. Alternatively, the gates connected to the cursor counter are enabled when write operation is desired. The outputs from the flip-flops making up the display character counter 24 are respectively applied to each one of the NAND-gates 171 through 175. It should be remembered that the counter 24 is a binary counter and its output presents a pulse pattern in binary code representative of one of its 32 counts. The inputs to these NAND gates are designated by the terminology B1, B2, B4, B8 and B16, which corresponds to the outputs shown for the counter 24 in FIG. 6. Similarly, the W1, W2, W4 and W8 outputs of the line counter 26 are respectively applied to the NAND-gates 176, 177, 178 and 179.

The five outputs of the cursor character counter 64 are respectively applied to the respective NAND-gates 180, 181, 182, 183 and 184. The outputs of the cursor line counter 66 are respectively applied to the respective NAND-gates 185, 186, 187 and 188. NAND-gate 189 receives the output of NAND-gates 171 and 180. NAND-gate 190 receives the output of NAND-gates 172 and 181. NAND-gate 191 receives the output of NAND-gates 183, 182. NAND-gate 192 receives the outputs of NAND-gates 174 and 183. NAND-gate 193 receives the outputs of NAND-gates 175 and 184. NAND-gate 194 has applied to it the outputs of NAND-gates 176 and 185. NAND-gate 195 receives the outputs of NAND-gates 177 and 186. NAND-gate 196 receives the outputs of NAND-gates 178 and 187. NAND-gate 197 receives the outputs of NAND-gates 179 and 188.

An inverter 199 receives a signal from a read-write signal source 199' which is actuated by the typewriter keyboard or other input data source, when it is desired to write. Otherwise, and normally, a low signal is received from the read-write signal source. Accordingly, the output of inverter 199 is high when in the read mode and is low when in the write mode. The output of inverter 199 is applied to an inverter 201 as well as to all of the NAND-gates 171 through 179. The output of inverter 201 is applied to all of the NAND-gates 180 through 188.

In the read mode, the output of inverter 199 is high whereby the NAND-gates 171 through 179 are all enabled. The high input to inverter 201 results in a low output whereby NAND-gates 180 through 188 are not enabled. Thus, the outputs of NAND-gates 189 through 197 will be the outputs of NAND-gates 171 through 179 or the address data from the display counters. In the WRITE mode of operation, a high signal is applied to the input of inverter 199. This is inverted, thus holding NAND-gates 171 through 179 disabled. However, the inverter 201 will provide a high or enabling input to the NAND-gates 180 through 188. As a result the NAND-gates 189 through 197 will provide an address to the memory which constitutes the count outputs of the two cursor counters.

The memory which is to be employed with this invention may be any digital storage-type memory. One that is preferred is the well-known magnetic core memory. The operations of addressing such a memory, entering data for storage and addressing such memory for readout and reading out the stored data are well known and accordingly need not be discussed here.

SUMMARY OF ROLL OPERATION

In the vertical roll operation the data displayed on the face of the cathode-ray tube appears to roll upward as new information is entered from the bottom. The top and bottom character row positions are blanked out giving the effect of rows of data appearing gradually from behind a mask at the bottom and gradually disappearing behind a mask at the top. New data is written into memory during the time the address of data would be displayed in the area that is blanked. Provision is made for several roll speeds. Choice of speed depends on capabilities of the data source which feeds new data to be displayed and visual effect desired.

The circuitry provided achieves the indicated effects by blanking the first and last line positions on the display tube, and by periodically incrementing the count of the display character counter by one before the commencement of the first line to be displayed in the succeeding field. In order to avoid the appearance of jumping, provision is also made for delaying the start of the first line to be displayed by intervals ranging for the interval of 14 horizontal sync pulses, down to one sync-pulse interval, and thereafter repeating the cycle from 14 to one again. The speed of display is handled by varying the rate of change of the amount that the first line of display is delayed.

HORIZONTAL CRAWL

In horizontal crawl a single row of characters may be made to appear from the right side of the screen and crawl gradually across the screen from right to left, disappearing at the left. The extreme left- and right-hand character column position are blanked producing a curtain, from which characters appear from the right and into which they disappear on the left. New data is entered during a time a memory address would be displayed in the blanked area. Provision is made for three crawl speeds, choice depending on the capabilities of the data source and the visual effect desired.

The accomplishment of the crawl is done in a somewhat similar manner to the accomplishment of the roll. The character display counter which establishes the address in the memory from which a readout occurs has its starting count incremented by one periodically before the beginning of the display of the first line in a field. Provision is made for delaying the start of a line, first 14 clock pulses, then 13, etc. and down to one, and then starting back at 14 again. Crawl speed may be varied by changing the rate at which the delay is changed.

ROLL OPERATION

Referring now to FIGS. 9A, 9B, 9C and 9D, there may be seen block schematic diagrams of the apparatus for forming the roll and crawl operation.

In order to initiate operation, a roll key 200 is depressed at the typewriter keyboard. Also, either a slow roll key 202, a slow range key 203, or a fast roll key 204, may be depressed as determined by the speed of the roll desired. When none of these keys is depressed, the roll speed is between that of slow and fast roll. Depressing the roll key 200 causes a flip-flop 206 to be set, upon the occurrence of the next vertical sync pulse, (RR1), which is applied to its clock input terminal. When it is no longer desired to have the roll operation, the roll key is opened. An inverter 208, which is connected to the reset input of the flip-flop 206, applies an input such that flip-flop 206 will be reset at the next vertical sync pulse.

When flip-flop 206 is set, its output is applied first to an inverter 210, whose output provides a VR DC level, then directly to an output terminal whose output provides a VR DC level, and then to a NAND-gate 214, which causes its output to go from low to high, indicative of either VR of HC (horizontal crawl).

In the vertical roll mode, as well as in the horizontal crawl mode, since the line and character display counters 26 and 24 will be operated in a manner so that they are not reset and at the beginning of each successive display field the counters will not have a beginning count, in order to provide the necessary W8 and B16 signals to the flip-flop 108 and 114, shown in FIG. 3, a substitute row and column counter 216 is employed. When in the roll mode, the output of this counter is provided when it attains the count of 16. When in the crawl mode, the output of this counter is used when it attains the count of 24.

When the VR signal goes high, then a NAND-gate 218 can apply pulses, designated as Y14', to drive the substitute Row 1 column counter 216. The Y14' pulses are derived from a one-shot circuit 220 which is driven in response to Y14 pulses. It will be recalled that the Y14 pulses are derived from the output of the Y-character matrix counter.

The substitute row-column counter 216, when it reaches the count of 16, provides an output to an AND-gate 222. This AND gate has as its second required input the VR output of the flip-flop 206. It will be noted that another AND-gate 224 is blocked at this time, since one of its required inputs VR is low. The other input to this AND-gate 224 is the regular W8 output from the display line counter 26. Therefore, when the system is not in the roll mode, the W8 output causes an output from the AND gate which is connected to an OR-gate 226. The AND-gate 222 is also connected to this OR-gate 226. The output of the OR gate is a W8* signal. This is the signal which is applied to flip-flop 108 to cause it to reset whereby the gated clock oscillator, which drives the X-counter 116 is terminated, and horizontal sync pulses are no longer applied to advance the Y-counter 140.

From the foregoing, it should be appreciated why the counter 216 is designated as a substitute row-column counter. In the roll mode, or in the crawl mode, as will be seen later, its output is substituted for the line counter or the character counter for the purpose of keeping track of the number of lines or characters which have been displayed, but not for the purpose of addressing the memory for readout.

Referring back to the one-shot 220, it will be seen that its output Y14* is also applied to an AND-gate 230. Another input to this gate is VR. The third required input to this gate, which enables it to apply a pulse to the display line counter, increasing its count by one, is an RS2 pulse. The output of gate 230 to the display line counter is in addition to the regular flow of Y14 pulses which advance the counter count by 16. It occurs each time an RS2 signal occurs and causes the roll effect. How the RS2 signal is derived will be described subsequently. At this point it should suffice to state that an RS2 pulse is generated immediately upon going into a roll or a crawl mode of operation, and also after predetermined intervals as determined by the roll or crawl speed selected.

Aside from the time the RS2 pulse is provided, the display line counter advances in its normal manner in response to the Y14 pulses. Accordingly, at the end of a predetermined number of display fields in the roll mode, the display line counter ends up with a one count. Another count is added by the application of a Y14* pulse. Thus, at the beginning of the next display field, the third line of data in the register will be displayed. After the next predetermined number of display fields have occurred, another Y14* pulse is applied to the counter and the fourth data line in the memory will be shown at the top of the display field.

The foregoing operation gives the displayed data the appearance of rolling upward across the face of the display tube. The substitute row-column counter 216 provides the necessary W8* pulse at the end of the 16th display line which is applied to the clock control in FIG. 3, at the right time, despite the face that the regular display line counter provides the W8 pulses at the wrong time.

Blanking signals for blanking out the top and bottom lines is provided by structure which will be described subsequently herein.

From the structure described thus far, while the roll effect is provided, it is not very smooth and gives the appearance of jumping up the space by one line. The roll effect can be made much smoother by dividing up the increment of one line into smaller increments of motion. That is, by starting the top line being displayed down the distance of 14 scan lines with the rest of the display following thereafter, then displaying the next top line for the next display 13 scan lines, then 12, etc., returning again to 14 after there has been a one-scan-line delay, the roll mode of display is made smooth.

This operation is achieved by inhibiting a certain number of clock pulses from the Y-counter, and gradually decreasing the number of clock pulses withheld from the Y-counter for each field being displayed, in the manner previously described.

Now if the clock pulses are withheld from the Y-counter for the interval required for 14 scan lines to occur, the display that would follow would be displaced down by 14 scan lines or one row and the data that would be displayed at that time would be the line of data that would otherwise have been displayed in the preceding row. However, the Y14* pulse adds a count to the counter to ensure that the line displayed is the proper one. The line that would have been displayed is now the bottom line and does not appear.

The indicated delay of clock pulses is produced simply by counting the HCP pulses (horizontal clock pulses) and after a certain number of them, which are counted by a counter, a flip-flop is reset which in turn allows the HCP pulses to be applied to the Y-counter. A delay counter 232 counts 14 HCP pulses and then resets a flip-flop 234 with its output. The set output of the flip-flop is applied to two NAND-gates respectively 236 and 238. NAND-gate 236 requires as its other input a VR signal. A following NAND-gate 240 is inhibited in the presence of an output from the NAND-gate 236. The other input to the NAND-gate 240 is an input from an inverter 242, which is driven in response to horizontal clock pulses which are received from the NAND-gate 110 in FIG. 3. The output of the NAND-gate 240, when it is enabled, constitutes the clock pulses which drive the Y-counter shown in FIG. 4.

The delay counter 232 establishes the amount of delay until clock pulses are applied to the Y- (or X- ) counters. Control of the variation in such delay is achieved by changing the count of the delay counter so that it has a different value each time it starts counting to establish the amount of the delay. Establishment of the initial count of the counter is achieved by a delay reference counter 242. The delay reference counter count is transferred into the delay counter through transfer gates, which are enabled during the vertical retrace period. The count in the delay reference counter is established in response to a multivibrator 246 output. The multivibrator is under the control of a programmable counter 248 and associated logic 250, designated as counter control gates.

The variable delay interval provides an opportunity to obtain speed control since, the more rapidly the delay is decreased the more quickly the display appears to move. Accordingly, provision is made for counting through the delay interval at different rates in accordance with signals derived by depressing the slow roll key 202 or fast roll key 204.

The slow roll key 202 output is applied to a NOR-gate 252 to which the slow crawl key 254 output is also applied. The output of the NOR-gate 252 is applied, to an inverter 258 whose output is connected to the set input of the flip-flop 256, and also to the reset input of the flip-flop 256. The application of the RR1 signal to the clock input terminal of the flip-flop 256 enables it to be reset whereby its output is an S signal. Otherwise its output is an S signal. The fast roll key 204 and a fast crawl key 260 are connected to a NOR-gate 262. The output of the NOR-gate is connected directly to the reset input of a flip-flop 264 and also through an inverter 266 to the set input of the flip-flop. The application of the RR1 signal to the clock terminal of the flip-flop, in the presence of a fast roll or fast crawl input, causes the flip-flop to be driven to its reset state thereby producing an F output. Otherwise, the flip-flop is in its set state and its output is F.

There is also provided a slow roll range key 203 which is used when a very slow operation is desired.

The function of the counter control gates 250 is to determine the total count capacity of the programmable counter 248 by inserting a starting count in response to its input each time a W8* pulse occurs. The number of pulses applied by the multivibrator to the programmable counter may be thus determined.

Counters whose count capacity cam be varied by presetting the starting count are well known in the art. The overflow output of the programmable counter is used to stop the multivibrator 246. It restarts upon the occurrence of the W8* pulse. The multivibrator is driven by horizontal sync pulses which it receives through a NOR-gate 268. Other inputs to this NOR gate are the outputs of two AND-gates respectively 270 and 272. One of these has as its input the HC (horizontal crawl) clock clamp pulses. The other has as its input the VR and vertical sync pulse.

In summary, therefore, the number of pulses which the multivibrator can supply to the delay reference counter, at a horizontal sync rate, is determined by the count to which the programmable counter can be set, which is a function of the settings of the counter control gates. The programmable counter is reset to an initial count state each time a W8* pulse occurs. This pulse is applied to the gates through a differentiator circuit 271.

To review the operations described thus far the programmable counter is preset to an initial count state, upon each occurrence of a W8* pulse. This initial count state is established by the settings of the counter control gates which in turn are established by the setting of the keys on the keyboard. The programmable counter can then count pulses from the multivibrator until it fills. When it fills, it stops the multivibrator. During the counting interval, the output of the multivibrator is applied to the delay reference counter. The number of pulses which are permitted to be introduced into the delay reference counter during each field may be one, two, or three, depending upon the desired roll speed.

At the end of each frame, the count of the delay reference counter is transferred by the transfer gates 244 into the delay counter 232. The apparatus which produces the transfer pulse comprises a NAND-gate 274 which has as one input the direct output of the NOR-gate 268 and as a second input the output of differentiator 276. This delay circuit serves the function of preventing the NAND-gate 274 from producing an output during CRS. Accordingly, NAND-gate 274, output in the roll made, enables transfer gates 244 to transfer the delay reference counter output upon the occurrence of a vertical sync pulse. In the crawl mode, the transfer gates are enabled upon the occurrence of a horizontal sync pulse.

The output of the differentiator circuit 276 is designated as CRS which is a "clock reset signal." This is applied to the delay counter 232, to a blanking counter 278 and to the substitute row-column counter 216, to cause these counters to be reset. It is also applied to a flip-flop 234 to cause it to be set. The set output of the flip-flop 234 comprises a clock inhibit signal which prevents the HCP pulses from reaching the Y-counter until flip-flop 234 is reset again by the fill output of the delay counter.

Considering now the full count of the delay reference counter 242, it is applied to an AND-gate 280, which also receives output from the multivibrator 246. In the presence of the delay reference counter output, the AND-gate 280 can apply an output to an OR-gate 282. This OR-gate output is designated as RS2. This RS2 pulse is used to enable the gate 230 whereby the extra count signal (designated as Y14*) is inserted into the display line counter, each time the delay time for the commencement of the display shifts from one horizontal line time to 14 line time.

For the smoothest possible motion in either the roll or the crawl mode, it is necessary to make the rate of advance, for the pulses that advance the delay reference counter, occur in integral multiple or submultiples of the frame rate of the scanning system, in order to produce a really smooth roll appearance. In order to achieve such rate of advance of the delay counter, it is necessary to detect odd and even fields and frames and to advance the delay reference counter accordingly. In the roll mode, frames are counted using an odd and even field-detecting circuit which includes a flip-flop 284. The flip-flop is set in response to the RR1, vertical sync pulse. A one-shot circuit 286 also receives the vertical sync pulse and provides as an output a "stretched" vertical sync pulse designated as RR1'. This is the pulse which is also applied to the AND-gate 272. A NAND-gate 288 has the RR1' output of the one-shot 286 applied thereto and also the output of inverters 290 and 292. The inverter 290 has applied to its input a horizontal sync pulse from FIG. 3. The inverter 292 has applied to its input a clock clamp pulse.

In order to detect an odd field, one looks for a horizontal drive pulse in the first 35 microseconds after the occurrence of the leading edge of the vertical sync pulse. If this occurs, then it is known that there is an odd field present. The width of the output of the one-shot circuit 286 is 35 microseconds. Thus, if the horizontal sync occurs within the duration of the output of the one-shot circuit, then the NAND-gate 288 can reset flip-flop 284. Accordingly, the reset output of flip-flop 284 is indicative of the presence of an odd field, and the set output is indicative of the presence of an even field. The reset outputs of flip-flop 284 are applied to a frame counter 294. This counter has two outputs. FC01 is an output which occurs at the end of every second frame, and FC02 is an output which occurs at the end of every four frames in the divide-by-two mode, i.e., FC01 occurs once for every three frames and FC02 occurs on the next frame in the divide-by-three mode. It will be seen that FC01 is another input to the counter control gates as well as the set output of flip-flop 284 whereby the counter control gates 250 are controlled to alter the programmable counter count either once per field, once per frame, every two frames, or once for every three frames as determined by the desired roll speed. The details of the counter control gates are shown in FIG. 10. The timing is such that the delay reference counter is arranged to advance immediately preceding an even field. The NAND-gate 295, in the presence of slow roll, S and an FC02 output, causes the counter 294 to divide by three.

To advance the count of the delay counter 232, as well as the blanking counter 278, CP1 pulses are generated and applied to the counters. In the vertical roll mode, an AND-gate 296 has as its three required inputs a VR signal, an output from control gates designated as CP1 control gates 298, and an HCP or NOT horizontal clock pulse input. These are derived by applying the HCP pulses to an inverter 300.

The output of the AND-gate 296 is applied to an OR-gate 302. The other input to the OR gate is an AND-gate 304 output. The AND-gate 304 provides an output in response to the HC signal and clock pulses. The OR-gate 302 output constitutes the CP1 pulses.

One other problem which occurs in the presentation of a roll display is that although two identical fields (odd and even) are generated per frame, they are displaced by half a horizontal line between the odd and even fields. As a result the odd field dot that is used to make a character is immediately above the even field dot that is used to made the same point. In moving these dots to produce a roll motion it is essential that the bottom dot move first or it will give the appearance of separating and then coming together again with the upper dot which is not too pleasing a presentation. The odd/even field detector takes care of this problem.

In slower roll speed it is necessary to delay the next odd field after an even field advance in order to produce the most linear possible motion by one HCP pulse time. In other words, the CP1 control gates do not provide an enabling output to the NAND-gate 296, in the presence of a slow roll until after 1 HCP pulse time on the first odd field following a delay reference counter advance.

Considering now the blanking problem, in the roll mode, the substitute row-column counter 216 provides some signals necessary for deriving the blanking signals. It will be recalled that there should be blanking at the top and the bottom of the display. A flip-flop circuit 310, when in its reset state, applies its output to a NAND-gate 312, whose other input is either a VR or an HC signal. The output of the NAND-gate 312 or the output of another NAND-gate 314 can constitute the blanking signal.

Assume now that the flip-flop 310 is in its reset state as a result of which the blanking signal is present and there is no display shown on the face of the tube. It is desired to unblank at the time that the display system is ready to provide the first line of characters. Since the blanking counter 278 is always reset at vertical sync time and always starts counting from the same point, and since it counts 14 HCP pulses, its output provides a stable reference. Upon the occurrence of the 14th count, there is an output which is applied to a NAND-gate 316 having as its other inputs the set output of a flip-flop 318 and a CP1 pulse input. Flip-flop 318 is set by a CRS pulse and is reset by the reset output of flip-flop 310. Accordingly, flip-flop 310 is driven to its set state and the display tube is unblanked after the first 14 counts, and is ready to display thereafter.

At the bottom of the display tube, because of the variable delay in starting the Y-counter which provides Y14 pulses, the placement of the bottom blanking becomes problematical. However, the 15th count of the substitute row and column counter can be combined with the 14th count of the blanking counter to provide a blanking signal which is within a scan line interval from where it belongs, which is sufficiently stable. An AND-gate 320 combines the 14th count of the blanking counter with the 15th count of the substitute row and column counter and together with a VR and CP1 signal, produces an output which resets flip-flop 310 and thereby provides blanking again until the next field when unblanking will occur again after the occurrence of the 14th CP1 clock pulse.

CRAWL MODE

A crawl key 320 when operated causes a flip-flop 322 to be driven to its set state upon the occurrence of a vertical sync signal. When the crawl key is open then the flip-flop 322 is reset in response to the output of the inverter 324 and an RR1 vertical sync signal. The set output of the flip-flop 322 constitutes an HC signal and HC is derived from its reset output. The reset output is applied to a NAND-gate 214 whose output is VR+HC. The reset output is also applied to an inverter 326, its output is designated as "inhibit current line step." The RR1 vertical sync signal is applied to an inverter 328, whose output constitutes the RR1 signal. The inverter 326 output is also applied to NAND-gates respectively 330 and 332. NAND-gate 330 has as its second input VR and thus its output is RR1+VR. NAND-gate 332 has as its other input HC, thus its output is RR1+HC. The use of these signals will be shown subsequently.

In the crawl mode X10 signals are applied to the substitute row and column counter 216 to drive it to its 24th count. X10 signals are applied to an inverter 334 whose output is applied to a NAND-gate 336. The other input to the NAND-gate 336 is an HC signal. The output of the NAND-gate 336 is used to drive the substitute row-column counter 216.

As in the case of roll, the RS2 pulse, when it occurs, is used to increase the count of the display character counter by 1. An AND-gate 338 has applied to its input X10, HC and RS2. Its output is an X10* which is applied to the character display counter in place of the regular X10 pulse. The substitute row and column counter is now being operated at the character rate. Its 24-count output (24 characters in a line), is applied to a NAND-gate 340, which is enabled in the presence of an HC signal, and its output is applied to a NOR-gate to provide a B16* clock control signal. This takes the place of the usual B16 clock control signal, which is applied to the flip-flop 114 in FIG. 3 to turn off the gated clock oscillator.

The NAND-gate 342 receives the B16 pulse produced by the display column counter and is enabled in the presence of HC signals to apply the usual B16 signals to the flip-flop 114 in FIG. 3.

The counter control gates 250 in the crawl mode operate in response to FF, S and HC signals for the purpose of establishing a starting count for the programmable counter, in the same manner as was described in connection with roll. The programmable counter also controls the number of multivibrator pulses which are generated for each frame whereby the delay reference counter has its count established for the purpose of being introduced into the delay counter 232 during horizontal retrace time.

The delay of the clock pulses to the X-counter is established by the output of the delay counter 232, which resets the flip-flop 234 when it fills, thereby removing the clock inhibit pulse signal from the input to the NAND-gate 238. The output of NAND gate then goes high enabling the AND-gate 342 to apply clock pulses to the X-counter. These clock pulses, it will be appreciated, start anywhere from one clock pulse to 14 clock pulses delay as determined by the count established in the delay counter prior to the beginning of a line. The frequency of operation of the programmable counter and the delay reference counter 242 is determined by W8 which occurs at the field rate inhibited by the horizontal sync pulses rather than by the vertical sync pulses. This is achieved by the output of the NAND-gate 270 which is applied to NOR-gate 268. The CRS pulse this time occurs at horizontal sync time rather than at vertical sync time. The transfer of the delay reference counter count into the delay counter occurs at each horizontal sync time. The transfer of a count into the programmable counter still occurs in response to the W8 pulse at the end of a field. The delay reference counter counts at a free-running MV rate and the transfer from the delay reference counter into the delay counter occurs immediately following horizontal sync. In the crawl mode the delay reference counter is advanced one, two, or three counts for each field of display. The CP1 control gates and the frame counter logic are not used in the crawl mode.

In the crawl mode the 14 counts of the delay counter correspond to the space of one character. Thus, when the delay reference counter overflows and goes from its 14th count to its first count, an RS2 pulse is generated which, as previously described, is inserted into the display character counter to advance its count by one at the beginning of a line.

The blanking function is carried out basically by logic which includes the blanking counter 278, which this time is operating at the clock pulse or 8-megacycle rate. Flip-flops 310 and 318 operate as before. An AND-gate 350 collects the 23-count output of the substitute row column counter 216 which is "ORED" together with the 14-count output of the blanking counter, 278, a CP1 clock pulse, and the reset output of the flip-flop 352. In view of the fact that the blanking counter 278 is operating at an 8-megacycle rate, in order to insure that the AND-gate 350 output can occur when it attains the 14th count, its count output is applied through a delay circuit 354 to the flip-flop 352 causing it to toggle and thus divide the output of the blanking counter by two. Accordingly, the output of the AND-gate 350 operates to cause blanking when the 24th character time arrives in response to the output of the substitute row and column counter. Unblanking occurs in response to the first 14-count output of the blanking counter after CRS (horizontal sync).

Conditions may arise when it may be desirable to write into the memory during the 15th-line display time, when it is not desired to display the information left in memory from the previous display. Only new information is desired to be displayed. This operation is taken care of by the two NAND-gates respectively 356, 358, in conjunction with the flip-flop 360. If a cursor signal, indicating that the cursor is visible, is present, it is applied to both of the NAND-gates 356 and 358. The 16th-line output is applied to the NAND-gate 356 and the 24th character output is applied to the NAND-gate 358 from the row and column counter. The third required inputs to these NAND gates are the HC and VR signals. Both of these NAND gates cause the flip-flop 360 to be driven to its set state, and the output is applied to the NAND-gate 314 which, in the presence of either VR or HC causes a blanking signal to be applied to the display tube.

Accordingly, if a cursor appears during the roll mode somewhere in the region where the 16th count output of the substitute row and column counter is obtained, the display tube is blanked until the next horizontal sync pulse occurs at which time flip-flop 360 is reset. Similarly, upon the occurrence of the last character of a line, in the crawl mode, if the cursor signal is present, that is the cursor appears on the right-hand half of the screen, the character is blanked until the occurrence of the next horizontal sync pulse.

FIG. 10 is a block schematic diagram of the counter control gates 250 as shown in FIG. 9. The roll speeds which are achieved with the logic shown in FIG. 10 is one HCP advance for three frames; one CP advance for two frames; one HCP advance per frame; and 1 HCP advance per field.

In FIG. 10 the counter control gates 250 include a NAND-gate 360 to which the F and HC signals are applied. Another NAND-gate 362 has the HC, F and S signals applied to its inputs. Another NAND-gate 364 has the F and S and slow roll signal applied to its input. A NAND-gate 366 has the F and an inverted slow roll signal applied to its input. The output of NAND-gate 364 is applied to a NAND-gate 368, together with an S signal. The output of NAND-gate 368 is applied to a NAND-gate 370 together with a VR signal and an FCO2 signal. The output of NAND-gate 366 is applied to an AND-gate 372, together with a VR signal and the set output of the flip-flop 284. A NAND-gate 374 collects the W8* signal, together with the output from NAND-gate 360 and NAND-gates 370 and 372. A NAND-gate 376 collects the W8* signal together with the outputs from NAND-gates 362 and 370 and 372. A NAND-gate 376 collects the W8* signal together with the outputs from NAND-gates 362 and 370 and 372. Output from NAND-gate 374 resets the first stage of the programmable counter and output from NAND-gate 376 resets the second stage of the programmable counter. When both stages of the counter are reset, it counts one count and is full. When the first stage is reset it counts two counts and is full, when the second stage is reset it counts three counts and is full.

When a vertical roll key is depressed the VR signal is high. If none of the fast roll, slow roll or slow roll range keys are depressed, then NAND-gate 372 is enabled to provide an output each time an even field signal arrives from flip-flop 284, which is every second field. The output of NAND-gate 372, when it occurs, and when the W8* signal occurs, enables an output from NAND-gates 374 and 376, whereupon the programmable counter is completely reset. Thus, after the occurrence of every second field, the programmable counter counts one count and a total of one count pulse is applied, in response thereto to the delay reference counter.

If the fast roll key is depressed, then the F signal goes low and the F signal goes high. As a result, NAND-gate 366 output goes high. This enables NAND-gate 372 to apply an output to NAND-gates 374 and 376 each time flip-flop 284 provides a set output. Accordingly, the programmable counter will be reset in response to outputs from NAND-gates 374 and 376 upon the occurrence of every field.

When the slow roll key is actuated, the S signal goes high. This results in enabling NAND-gate 368. NAND-gate 372 is also enabled. Their outputs follow FC01 and even fields respectively. Accordingly, each time a W8* signal occurs, on every fourth field, the programmable counter will be reset.

When the slow roll range key 203 is actuated, this changes the frame counter 294 to .div.3. NAND-gate 372 is enabled two out of three frames and the NAND-gates 374 and 376 will therefore reset the programmable counter each time an output is provided from flip-flop 284 on every third frame.

In the operation of the counter control gates for horizontal crawl, in the presence of the HC signal and with none of the speed keys depressed, NAND-gate 362 enables NAND-gate 376 whenever a W8* pulse occurs and thus the first stage of the programmable counter will be reset.

In the presence of a fast crawl key actuation, NAND-gate 360 inhibits 374 in the presence of a W8* signal, and the first stage of the programmable counter will be reset.

When the slow crawl key is operated then NAND-gates 376 and 374 are enabled to provide an output in the presence of a W8* signal, and both stages of the programmable counter will be reset upon the occurrence of a W8* signal.

FIG. 11 shows the CP1 control gate structure. The CP1 control gates include a NAND-gate 380 which receives S, FC02 and slow roll range key inputs. This NAND gate is connected to an inverter 382, the output of which is applied to a NAND-gate 384. Two other inputs are applied to NAND-gate 384, these are the pause and set output from flip-flop 306. The output of NAND-gate 384 is applied to NAND-gate 296.

In the presence of a pause signal or a set output from flip-flop 306, then NAND-gate 384 allows the occurrence of CP1 pulses by blocking NAND-gate 296. Should the output of the inverter 382 go from a low to a high state then in the presence of a set output from flip-flop 306 NAND-gate 296 will be blocked by the output of NAND-gate 384 going low. The inverter 382 will go from a low to a high output each time an FC02 output is received, in the presence of an S signal and when the slow roll range key is not actuated. Otherwise, the output of the inverter 382 remains low.

PERIPHERAL OPERATION

Referring back to FIG. 9, a mode change one-shot circuit 390 performs three different operations. In going from the normal mode of operation of the system into either the roll or the crawl mode of operation, the delay reference counter 242 is reset by either the VR or the HC signal to its starting condition. It was pointed out that in order to obtain the crawl or roll effect an RS2 pulse is required to enable an additional count into either the display line counter or into the display character counter. The one-shot 390 enables this to occur. The one-shot is driven in the presence of either a VR or an HC pulse to apply an output to an AND-gate 392, which is also enabled by the presence of VR or HC. The output of the AND gate is applied to the OR-gate 282 whose output is the RS2 pulse.

The output of the one-shot 390 also operates to send the cursor to its home position except when the crawl mode is initiated. Otherwise, all other mode changes operate to send the cursor back to its home position in the upper left-hand corner of the display tube. This is accomplished by taking the one-shot output and applying it to an AND-gate 394. The AND gate is inhibited in the presence of an HC input. The output of the AND gate is applied also to an OR-gate 396 whose output resets the cursor line and row counters to their starting positions.

In the normal mode of operation, a cursor home signal, which is derived from the keyboard, is ANDED together with a VR+HC signal by an AND-gate 398. Its output is applied to the OR-gate 396.

The one-shot circuit also serves to stop the automatic character request signal from the interface board upon switching into the normal mode from either the roll or the crawl mode. The VR+HC input to the one-shot, which arises when switching into the normal mode from VR or HC, causes the one-shot to apply an output to an AND-gate 400, whose other input is VR+HC. The output of the AND-gate 400 is applied to an OR-gate 402. The output of the OR-gate 402 stops the operation of the character request multivibrator on the interface board of the display apparatus. Another input to the OR-gate 402 is the output from an AND-gate 404. This provides an output in the presence of the VR+HC signal together with an RM signal. This is a signal signifying the end of a message which has been entered into memory for display. It is usually placed at the end of the data.

LOADING LOGIC

To produce a continuous roll or a continuous crawl effect, it is necessary to enter new information into the memory, and to enter this information into the memory when the display tube is blanked, which would be in the case of roll during the 16th line, and the case of crawl during the 24th character display intervals.

Accordingly, the data input requirement for roll is that one line of characters be provided every time the RS2 signal occurs. The data requirement for crawl is one character for every RS2 signal.

Referring now to FIG. 12, each time an RS2 pulse occurs, it sets a flip-flop 404. The set output of the flip-flop actuates a one-shot circuit 406. The output of this one-shot operates to reset the flip-flop 404 and also is steered to set either a flip-flop 408 or a flip-flop 410, depending upon the conditions of two other flip-flops respectively 412 and 416. If flip-flop 408 is set, its output is applied to an AND-gate 418, which in the presence of a character request signal is enabled to send a write strobe signal to the memory controls. The output of the flip-flop 408 also enters a null code into the input register, so that the effect is to write nothing into the particular memory address at the time. If flip-flop 410 is set, its output is applied to an AND-gate 420. The output of this AND gate, in the presence of a character request signal at the interface board, sends a character request signal to the data source which is supplying signals at the time. This data source can be punch tape or magnetic tape, etc., depending upon the source of data being used for writing into the display apparatus.

The respective AND-gates 422 and 424, whose outputs are connected to an OR-gate 426, operate to reset the two flip-flops. In the crawl mode, the AND-gate 422 provides an output when an SU signal is entered into the AND gate. This is a signal which is provided by the memory after a character has been entered thereinto. In the vertical roll mode the flip-flops are reset in response to the output from AND-gate 424, which occurs when an HR signal is provided. This is a "head return" signal, provided by the cursor character counter when a complete line of data has been loaded into the memory.

In effect, the operation of the circuitry described so far, in the roll mode, in response to each RS2 signal either a line of characters is commanded from an external data source to be entered into the display system, or a line of nulls is written into the memory. In the crawl mode, in response to an RS2 signal, either a character is commanded to be written into the display system from the external data source, or a blank is written into the location in memory.

The status of flip-flops 412 and 416 to begin with is that flip-flop 412 in the normal mode, as indicated by VR+HC being applied to its reset input, is in its reset state. The reset output of flip-flop 412 is applied to an AND-gate 428. The other input to this AND gate is the set output of flip-flop 416. With these two inputs, AND-gate 428 can enable AND-gate 430, and disenable an AND-gate 432, so that the output of the one-shot 406 is steered to set flip-flop 410. In the absence of an output from AND-gate 428, AND-gate 432 is enabled and the one-shot 406 output will set flip-flop 408.

Flip-flop 416 provides what is known as a double space option. This means that the data is displayed on the display tube on every other line instead of an every line. This is accomplished by actuating a double space key 434, on the typewriter input keyboard. This output through an OR gate, or in the alternative, an HC signal, releases flip-flop 416 from its reset state and enables it to toggle in response to head return signals. These head return signals, as previously indicated, are the signals provided by the memory upon the completion of the recording of a line of characters.

The result of the toggling of flip-flop 416 is to enable the loading logic circuitry described to alternatively load a line of data from the outside source into memory and display it, and then to write nulls into the next line, and then to load and display on the following line.

Flip-flop 412 is set upon receiving an RM signal from a signal source 436. The RM signal is a signal which indicates the end of the message. As a result, no more data is written into memory and the data which has been previously entered rolls off of the top of the data display tube out of sight. Flip-flop 412 in the normal mode is reset in response to a VR and HC signal. Since no RS2 pulses are used in the normal mode, this circuitry is not employed.

One other function of the output of the AND-gate 430 is to transmit a load request signal to the data source supplying the data.

In the event that the data source cannot provide data at a sufficient rate to supply the needs of the system, a pause signal is generated which is applied to the CP1 control gates and the counter control gates and stops the advance of the delay reference counter until the data source can provide the required data. All that happens is that motion stops and when data is finally received, it is entered into memory and thereafter displayed and motion resumes. The pause signal generating logic is shown on FIG. 12. This includes a first AND-gate 438, which receives the combination of an HC and an S signal. This is applied to an OR-gate 440. Another input to the OR gate is the output of an AND-gate 442, which receives a VR and an S signal. The output of the OR gate is applied to a NAND-gate 443. This NAND gate receives the reset output of either flip-flop 408 or flip-flop 410, and also an S14 signal. The S14 signal is the output of the delay reference counter 242 when it attains its 14th count. In the presence of all of these signals, a pause signal is generated by the output of NAND-gate 442. A pause signal is also generated when flip-flop 404 is in its set state (in response to an RS2 pulse) and an S14 signal is received.

ANALOG ROLL AND CRAWL SYSTEM

The preceding description shows how the roll and crawl operation may be performed using an all-digital technique. It is possible to also do this using analog techniques. For both roll and crawl, in the analog system, a variable delay signal is generated. In the crawl mode this variable delay signal is employed for inhibiting the start of the operation of the gated clock oscillator which feeds pulses to the X-matrix counter. In the case of the roll mode, the variable delay signal is used to gate extra pulses through to the 24-count counter 106 in FIG. 1, which delays the start of the operation at the beginning of each field. A substitute row and column counter is required for the generation of W8* and the B16* signals, as was the case in the digital system.

FIG. 13 shows in block diagram form how the variable delays are generated. This is done by generating a longtime sawtooth wave with a longtime sawtooth generator 445. In the case of the vertical roll mode, a VR shorttime sawtooth generator 447 is employed. In the case of the horizontal crawl mode, an HC shorttime sawtooth generator 449 is employed. Sawtooth generators are well-known circuits.

The longtime sawtooth generator can have the interval required for one "saw" waveform varied in response to keyed inputs which can be a fast roll key, a fast crawl key, a slow roll key or a slow crawl key. For the vertical roll mode, a vertical roll key must be also depressed. The generation of the shorttime sawtooth waveform is synchronized with vertical sync. Upon the occurrence of a VR signal, and vertical sync, the shorttime sawtooth generator commences operation. FIG. 14 shows a shorttime sawtooth waveform 451, and a longtime sawtooth waveform 453. It will be seen that upon each occurrence of an RR1 pulse, a shorttime sawtooth waveform is generated. This is applied to a sum amplifier 455. Its output is applied to a differential amplifier 457. The other input to the differential amplifier is the longtime sawtooth generator. The differential amplifier has two outputs, one indicated as delay positive, the other delay negative. The differential amplifier will provide the positive and negative outputs for an interval commencing with the RR1 signal and terminating when the shorttime sawtooth crosses the longtime sawtooth, or from the beginning of the generation of the shorttime sawtooth waveform until its amplitude reaches the amplitude of the longtime sawtooth waveform.

For horizontal crawl, the same operation obtains. Upon the application of the H and HC signals, the HC shorttime sawtooth generator commences generating. FIG. 14 shows the waveforms which are derived from the delay-positive output. The waveform 451A is a shorttime waveform, and the waveform 453A is a longtime waveform. An output is derived from the differential amplifier from the commencement of the horizontal sync pulse until such time as a shorttime sawtooth waveform equals the amplitude of the longtime sawtooth waveform.

FIG. 15 shows how certain other needed signals are generated. These other needed signals are an RS1 signal and a VRS signal. An RR1 or vertical signal is applied to a NAND-gate 457 whose other input is the output of a NAND-gate 459. The output of NAND-gate 457 is connected to the input to NAND-gate 459. The output of NAND-gate 457 is also an RS1 signal. The output of NAND-gate 457 is connected to another NAND-gate 461. The other input to NAND-gate 461 is an H signal, which is obtained by applying horizontal sync to an inverter 463. The output of NAND-gate 461 which, when enabled, comprises horizontal sync signals, is applied to a counter 465. The 15th count output of the counter 465 is applied as a second input to NAND-gate 459. The 10th count output of the counter is applied to a NAND-gate 467 whose other input is a CC signal (the output of an inverter 469 in FIG. 16, to whose input a clock clamp signal has been applied). The output of the NAND-gate 467 is a VRS signal. The counter is reset by vertical sync. The VRS signal can only occur when the display system is in the vertical roll mode since, as will be shown in describing the crawl mode, the CC signal is not present at the 10th count of counter 465 when the display system is in the crawl mode.

Upon the occurrence of the RR1 or vertical sync pulse, the flip-flop consisting of cross-connected NAND-gates 457 and 459 is set. This produces an RS1 signal and this enables the NAND-gate 461 to pass H signals to drive the counter. Upon the occurrence of the 15th count, the output of the counter is applied to NAND-gate 459 resetting the flip-flop and terminating the RS1 signal. Upon the occurrence of the 10th count, a VRS signal is generated if the NOT clock clamp signal (CC) is present.

As shown in FIG. 16, the clock clamp signal (CC) is applied to an inverter 469, producing a CC signal. The output of the inverter 469 is applied to a delay circuit 471 and also to enable a NAND-gate 472. The output of this NAND-gate 472 is used to clamp the gated clock oscillator in place of the usual clock clamp pulse. In order to obtain an output from NAND-gate 472, there must be an output from another NAND-gate 474. This NAND-gate 474 requires three inputs. One of these is an RS2 signal, another is a horizontal crawl signal, and the third is the output of an inverter 476. The delay positive signal is applied to the inverter 476 input.

The operation of the circuitry described is to delay for varying periods of time starting with a long period of time and gradually decreasing to a short period of time until a predetermined minimum normal CC signal at which time the delay interval cycle starts again. The varying delay is used to inhibit the clock clamp signal applied to the gated clock oscillator, in the presence of the horizontal crawl signal, and in the absence of an RS2 pulse. Accordingly, a character is started at a maximum distance, on the order of one character space, from the left edge of the data line at the top of the display tube and this space gets less and less during the crawl mode of operation until the character space is used up, then the cycle starts all over again.

The output of the inverter 476 is also applied to a NAND-gate 478, which has as its other input the output of the delay circuit 471 and a horizontal crawl signal. The output of NAND-gate 478 is applied to a flip-flop consisting of cross-coupled NAND-gates 480 and 482. NAND-gate 482 requires two other inputs besides the output of NAND-gate 480. One of these is the horizontal sync signal, H, and the other is the RS2 signal. In the presence of a delayed CC signal, an HC signal, and a delay signal, NAND-gate 478 drives the flip-flop consisting of NAND-gates 480 and 482 so that there is an output from NAND-gate 480.

The output of NAND-gate 480 is coupled through a capacitor 484 to another flip-flop comprising cross-coupled NAND-gates 486 and 488. The output of NAND-gate 486 will constitute an RS2 signal. The output of NAND-gate 488 will constitute an RS2 signal. The NAND-gate 486 provides an RS2 output in the presence of either a VR or HC signal, the cross-connected output of NAND-gate 488, and either an output from NAND-gate 480 or VRS signal. The RS2 signal is applied to the character display counter to increase its count by one in the manner described previously herein.

The flip-flop consisting of NAND-gates 486 and 488 is reset after a short delay. The output of NAND-gate 488 is applied to an inverter 490. The output of the inverter 490 is applied to a delay circuit 492. The output of delay 492 goes to two NAND-gates 494 and 496. These NAND gates have their outputs connected together and to the input to NAND-gate 488. The NAND-gate 494 has as its other required inputs the HC signal and the H signal. The NAND-gate 496 has as its other required inputs the VR signal and the RR1 signal. Thus, within a short time after the RS2 signal is generated, the flip-flop is reset again providing the RS2 signal.

When the display system is placed in the vertical roll mode, an RS2 signal is generated each time a VRS signal is received on the input of NAND-gate 486. The output of the NAND-gate 486 is applied to NAND-gates 500 and 502. NAND-gate 500 is enabled to pass RS2 signals in the presence of the VR signal. The output of NAND-gate 500 enables NAND-gate 504. Its output is applied to the character line counter to increase the line count by one in the presence of Y14 signals. The output of NAND-gate 502 is applied to a NAND-gate 506. In the presence of an X10 signal the RS2 is applied by the NAND-gate 506 to increase the character column counter count by one.

FIG. 17 is a block schematic diagram for varying the delay at the beginning of the display when the display system is in the vertical roll mode. Horizontal sync pulses, H, are applied to a synchronized frequency multiplier 508. The output of this circuit, which is a train of pulses at a frequency which is three times that of the horizontal sync frequency is applied to a NAND-gate 510. The other inputs to this NAND gate are an RS1 signal, a VR signal, and the negative delay output of the differential amplifier. Thus, NAND-gate 510 is enabled to pass pulses to the delay after vertical sync counter 106 (FIG. 4) for gradually increasing intervals immediately after each vertical sync pulse until a maximum delay has occurred at which time the system is recycled. This has the effect of causing the display to initially start at a maximum delayed position from the top of the display and then during successive fields to gradually move closer to the top of the display up to a predetermined position, and then to start from the maximum displaced position downward again.

FIG. 18 illustrates the manner in which the blanking signals are obtained. This is very simple. In the roll mode, an AND-gate 512 applies its output to the first of a series of one-shot circuits 514, 516, 518. The output of the last one-shot circuit in the train, 518, is applied to a NAND-gate 520, whose output, in the presence of the VR signal, constitutes the blanking signal.

In the horizontal crawl mode, similarly, a NAND-gate 522, in the presence of an H or horizontal sync signal, applies its output to the first of a train of one-shot circuits, 524, 526. The last of the one-shot circuits in the train, 526, applies its output to a NAND-gate 528. This NAND gate is enabled in the presence of an HC signal to provide an output constituting the blanking signal in the horizontal crawl mode.

From the foregoing description, it will be seen that there has been provided a novel and useful arrangement for effectuating horizontal crawl operation and vertical roll operation with a display system which operates at commercial television frequencies.

Claims

What is claimed is:

1. In a continuous data display system of the type wherein a memory stores data in the form of characters in predetermined lines of characters and there is a means for addressing said memory for reading characters out of said memory at a time so that they are displayed at locations on the face of a continuously scanned display system corresponding to the locations in said memory,

means for providing a continuously moving effect to the data being displayed comprising:

means for periodically generating an address-incrementing signal in synchronism with said continuously scanning display system, and

means for applying said address-incrementing signal to said means for addressing said memory for reading a character out of said memory at a time to be displayed by said continuously scanning display system at a location displaced from the location of the character in said memory.

2. In a continuous display system as recited in claim 1 wherein there is provided a means for blanking the first and last display line locations of said continuously scanning display system and the characters read out of said memory by said means for addressing said memory are displaced to line locations which are different than the line locations in memory from which they are read out.

3. In a continuous display system as recited in claim 1 wherein there is provided a means for blanking the first and last character position of each display line of said continuously scanning display system and the characters read out of said memory by said means for addressing said memory are displaced to locations along a line which are different than the line locations in memory from which they are read out.

4. In a continuous data display system as recited in claim 2 wherein there is included means for recurrently and successively delaying a display of lines of data on said display device face by varying intervals of time until a predetermined interval has been reached.

5. In a continuous data display system as recited in claim 3 wherein there is included means for recurrently and successively delaying a display of characters of data on each line of data on said display device face by decreasing intervals of time until a predetermined interval has been reached.

6. In a continuous data display system of the type wherein a memory stores data in the form of characters and there is provided

means for displaying said characters on the face of a continuously scanned display tube at address locations corresponding to those in memory, said means for displaying including line counter means for indicating the line address of a character, a character counter means for indicating the address of a character along a line,

first means for altering the count in said line counter means in synchronism with the display of lines of data by said display device,

second means for altering the count of said character counter in synchronism with the display of characters along a line by said display device, and

read means responsive to the counts of said line counter means and said character counter means for addressing said memory for reading characters out of said memory for display at locations on the face of said display device corresponding to locations in said memory,

means for providing a continuously moving effect to the data being displayed comprising:

means for periodically generating an address-incrementing signal in synchronism with said continuously scanning display system, and

means for applying said address-incrementing signal to one of said line and character counter means to cause the readout of characters from said memory by said read means at a time to be displayed at a location by said continuously scanning display system which is displaced from the location in said memory.

7. In a continuous data display system as recited in claim 6 wherein there is provided a delay means for recurrently and successively delaying the initiation of operation of one of said first and second means for altering the count for decreasing intervals of time until a predetermined minimum interval has been attained for delaying the display by said display device and thereby preventing a jumpy display appearance.

8. In a continuous data display system as recited in claim 6 wherein there is provided a means for blanking the first and last display line locations of said continuously scanning display system and the characters read out of said memory are displayed by said display system on line locations which are displaced from the line locations of readout from memory.

9. In a continuous data display system as recited in claim 6 wherein there is provided a means for blanking the first and last character position of each display line of said continuously scanning display system and the characters read out of said memory are displayed at locations along a line which are different than the line locations in memory from which they are read.

10. In a continuous display system as recited in claim 6 wherein said means for periodically generating an address-incrementing signal in synchronism with said continuously scanning display system includes delay reference counter means,

means for periodically incrementing the count of said delay reference counter means by a predetermined amount in synchronism with said continuously scanning display, and

means responsive to said delay reference counter means recycling from a full count to an initial count for generating an address-incrementing signal.

11. In a continuous display system as recited in claim 7 wherein said delay means includes a delay reference counter means,

means for periodically incrementing the count of said delay reference counter means by a predetermined amount in synchronism with said continuously scanning display,

a delay counter means,

means for continuously advancing the count of said delay counter means in synchronism with said continuously scanning display,

means for entering the count in said delay reference counter means as an initial count into said delay counter means in synchronism with said continuously scanning display, and

means for initiating the operation of one of said first and second counter means responsive to output from said delay counter means when it has a full count.

12. In a continuous display system as recited in claim 6 wherein there is included a means for generating repetitively, recurrently and in synchronism with said display, delay signals having delay intervals varying from a predetermined maximum to a minimum value, and

means for delaying the start of operation of said second means for altering the count of said character counter means in response to each of said delay signals to thereby prevent a jumpy display.

13. In a continuous display system as recited in claim 6 wherein there is included a means for generating repetitively, recurrently and in synchronism with said display, delay signals having delay intervals varying from a predetermined maximum to a minimum value, and said first means for altering the count of said line counter means in response to each of said delay signals to thereby prevent a jumpy display.

14. In a continuous data display system of the type which operates to provide a scanning raster on the face of a display device in response to horizontal sync signals being provided for each line of a scanning raster and vertical sync signals for each frame of a scanning raster,

a memory stores data in the form of characters at address locations corresponding to address locations on the face of said display device on which they are displayed in the form of lines of data, and there is provided a means synchronized by said vertical and horizontal sync signals for reading characters out of said memory to be displayed on the face of said display device, said means for reading including line counter means for indicating the line address of a character, a character counter means for indicating the address of a character along a line,

first means for applying pulses altering the count in said line counter means synchronized by said horizontal sync signals,

second means for applying pulses for altering the count in said character counter means synchronized by said horizontal sync signals,

display delay counter means responsive to the occurrence of a vertical sync signal and horizontal sync signals for delaying the application of pulses by said first and second means to said respective line and character counter means until it has reached its full count capacity, and

read means responsive to the counts of said line counter means and said character counter means for reading characters out of said memory for display at locations on the face of said display device corresponding to locations in said memory,

means for providing a continuously moving effect to the data being displayed comprising:

delay reference counter means,

means for periodically incrementing the count of said delay reference counter means by a predetermined amount for each vertical sync signal,

means responsive to said delay reference counter means attaining a full count for generating an address-incrementing signal, and

means for applying said address-incrementing signal to said line counter means to increment its address to cause readout of characters from said memory at a time to be displayed on a line location which is different from the line location in memory.

15. In a continuous data display system as recited in claim 14 wherein said means for periodically incrementing the count of said delay reference counter means includes a programmable counter means,

means for establishing the count capacity of said programmable counter means,

means for applying pulses to be counted to both said programmable counter means and said delay reference counter means in response to a vertical sync pulse, and

means for terminating the application of pulses by said means for applying pulses responsive to said programmable counter means attaining a full count.

16. In a continuous data display system as recited in claim 14 wherein there is included means for delaying the application of pulses by said first means for applying pulses for altering the count in said line counter means, said means comprising a delay counter means,

means for transferring the count of said delay reference counter means into said delay counter means in response to each vertical sync pulse,

means for applying pulses responsive to horizontal sync pulses to said delay counter to cause it to increase its count, and

means responsive to said delay counter means attaining a full count for enabling the application of pulses by said first means for applying pulses to said line counter means.

17. In a continuous data display system as recited in claim 14 wherein there is included a means for blanking the first and last line positions of said display device including:

a blanking counter means having the same count capacity as said delay counter means,

means for applying pulses responsive to horizontal sync pulses to said blanking counter to advance its count,

flip-flop means having a first state during which it produces a blanking signal output and a second state during which it does not produce an output,

means responsive to said blanking counter means attaining its full count for driving said flip-flop means to its second state,

substitute row-column counter means for indicating a count of the number of lines of data which are being displayed on said display device face, and

means responsive to said substitute row-column counter means indicating the count of the last display line of data on said display device face for driving said flip-flop means to its first state.

18. In a continuous display system as recited in claim 17 wherein there is included means for alternately writing data from a data source into memory during the blanking of the last line of data on said display device face or writing null signals into said memory during said blanking of the last line.

19. In a continuous display system as recited in claim 17 wherein there is included means for sensing an insufficient data flow into said memory and producing a pause signal, and

means responsive to said pause signal to hold further operation of said delay reference counter and delay counter until said pause signal terminates.

20. In a continuous data display system of the type which operates to provide a scanning raster on the face of a display device in response to horizontal sync signals being provided for each line of a scanning raster and vertical sync signals for each frame of a scanning raster,

a memory stores data in the form of characters at address locations corresponding to address locations on the face of said display device on which they are displayed in the form of lines of data, and there is provided a means synchronized by said vertical and horizontal sync signals for reading characters out of said memory to be displayed on the face of said display device, said means for reading including line counter means for indicating the line address of a character, a character counter means for indicating the address of a character along a line,

first means for applying pulses altering the count in said line counter means synchronized by said horizontal sync signals,

second means for applying pulses for altering the count in said character counter means synchronized by said horizontal sync signals,

display delay counter means responsive to the occurrence of a vertical sync signal and horizontal sync signals for delaying the application of pulses by said first and second means to said respective line and character counter means until it has reached its full count capacity, and

read means responsive to the counts of said line counter means and said character counter means for reading characters out of said memory for display at locations on the face of said display device corresponding to locations in said memory,

means for providing a continuously moving effect to the data being displayed comprising:

delay reference counter means,

means for periodically incrementing the count of said delay reference counter means by a predetermined amount for each horizontal sync signal,

means responsive to said delay reference counter means attaining a full count for generating an address-incrementing signal, and

means for applying said address-incrementing signal to said character counter means to increment its address to cause readout of characters from said memory at a time to be displayed on a line location which is different from the line location in memory.

21. In a continuous data display system as recited in claim 20 where said means for periodically incrementing the count of said delay reference counter means includes a programmable counter means,

means for establishing the count capacity of said programable counter means,

means for generating clock pulse signals in response to horizontal and vertical sync signals,

means for applying said clock pulses to be counted to both said programmable counter means and said delay reference counter means, and

means for terminating the application of pulses by said means for generating clock pulses responsive to said programmable counter means attaining a full count.

22. In a continuous data display system as recited in claim 20 wherein there is included means for delaying the application of pulses by said first means for applying pulses for altering the count in said character counter means, said means comprising a delay counter means,

means for transferring the count of said delay reference counter means into said delay counter means in response to each horizontal sync pulse,

means for applying said clock pulses to said delay counter to cause it to increase its count, and

means responsive to said delay counter means attaining a full count for enabling the application of pulses by said first means for applying pulses to said character counter means.

23. In a continuous data display system as recited in claim 20 wherein there is included a means for blanking the first and last character positions on each line displayed by said display device including:

a blanking counter means having the same count capacity as said delay counter means,

means for applying clock pulses to said blanking counter to advance its count,

flip-flop means having a first state during which it produces a blanking signal output and a second state during which it does not produce an output,

means responsive to said blanking counter means attaining its full count for driving said flip-flop means to its second state,

substitute row-column counter means for indicating a count of the number of characters of data which are being displayed on each line on said display device face, and

means responsive to said substitute row-column counter means indicating the count of the last character on a line of data on said display device face for driving said flip-flop means to its first state.

24. In a continuous data display system of the type which operates to provide a scanning raster on the face of a display device in response to horizontal sync signals being provided for each line of a scanning raster and vertical sync signals for each frame of a scanning raster,

a memory stores data in the form of characters at address locations corresponding to address locations on the face of said display device on which they are displayed in the form of lines of data, and there is provided a means synchronized by said vertical and horizontal sync signals for reading characters out of said memory to be displayed on the face of said display device, said means for reading including line counter means for indicating the line address of a character, a character counter means for indicating the address of a character along a line,

first means for applying pulses altering the count in said line counter means synchronized by said horizontal sync signals,

second means for applying pulses for altering the count in said character counter means synchronized by said horizontal sync signals,

display delay counter means responsive to the occurrence of a vertical sync signal and horizontal sync signals for delaying the application of pulses by said first and second means to said respective line and character counter means until it has reached its full count capacity, and

read means responsive to the counts of said line counter means and said character counter means for reading characters out of said memory for display at locations on the face of said display device corresponding to locations in said memory,

means for providing a continuously moving effect to the data being displayed comprising:

counter means,

means responsive to a vertical sync signal to enable the application of horizontal sync signals to said counter means, to be counted thereby,

means responsive to a predetermined count of said counter means to generate an extra count signal, and

means for applying said extra count signal to said line counter means to thereby cause the readout of a character from said memory at a time to be displayed on a line location different than the location in memory.

25. In a continuous data display as recited in claim 24 including means responsive to said vertical sync signals for generating successive delay signals cyclically varying from predetermined minimum to maximum delay intervals,

a source of high-frequency pulses at a frequency higher than said horizontal sync frequency,

gate means responsive to said successive delay signals for applying high-frequency pulses from said source to said display delay counter means over the interval of each said delay signal to alter the time of commencement of each display to thereby prevent a jumpy display.

26. In a continuous data display system of the type which operates to provide a scanning raster on the face of a display device in response to horizontal sync signals being provided for each line of a scanning raster and vertical sync signals for each frame of a scanning raster,

a memory stores data in the form of characters at address locations corresponding to address locations on the face of said display device on which they are displayed in the form of lines of data, and there is provided a means synchronized by said vertical and horizontal sync signals for reading characters out of said memory to be displayed on the face of said display device, said means for reading including line counter means for indicating the line address of a character, a character counter means for indicating the address of a character along a line,

first means for applying pulses altering the count in said line counter means synchronized by said horizontal sync signals,

second means for applying pulses for altering the count in said character counter means synchronized by said horizontal sync signals,

display delay counter means responsive to the occurrence of a vertical sync signal and horizontal sync signals for delaying the application of pulses by said first and second means to said respective line and character counter means until it has reached its full count capacity, and

read means responsive to the counts of said line counter means and said character counter means for reading characters out of said memory for display at locations on the face of said display device corresponding to locations in said memory,

means for providing a continuously moving effect to the data being displayed comprising

means responsive to said horizontal sync signals for generating successive delay signals cyclically varying from predetermined maximum to predetermined minimum delay intervals,

means responsive to a delay signal for generating an extra count pulse, and

means for applying said extra count pulse to said character counter means to thereby cause readout of a character from said memory at a time to be displayed at a different location along a line than the one in memory.

27. In a continuous data display as recited in claim 26 including means responsive to a delay signal to delay operation of said second means for applying pulses for the interval of said delay signal, to thereby alter the time of commencement of the display of a line of characters to avoid a jumpy display.