U.S. patent number 3,610,943 [Application Number 05/035,981] was granted by the patent office on 1971-10-05 for vehicle operation inhibitor control system.
Invention is credited to Trevor O. Jones.
United States Patent |
3,610,943 |
Jones |
October 5, 1971 |
**Please see images for:
( Certificate of Correction ) ** |
VEHICLE OPERATION INHIBITOR CONTROL SYSTEM
Abstract
A noise generator is energized from the ignition switch of a
vehicle to generate a random frequency which is gated at fixed
intervals to a plurality of binary counters and decoders which
convert the frequency to a digital representation of a random
number. The random number is displayed for a fixed interval of time
after which the number is removed. In order to energize the starter
circuit of the vehicle, the operator is required to operate
keyboard pushbuttons corresponding to the digits previously
displayed and in their proper sequence. The number entered by the
operator is converted to a binary representation thereof and
compared with that stored in the binary counters. The correct
number must be entered within a fixed interval of time in order to
provide a control signal which energizes the vehicle starter
circuit.
Inventors: |
Jones; Trevor O. (Milwaukee,
WI) |
Family
ID: |
21885910 |
Appl.
No.: |
05/035,981 |
Filed: |
May 11, 1970 |
Current U.S.
Class: |
307/10.4;
361/172; 180/272 |
Current CPC
Class: |
B60K
28/063 (20130101) |
Current International
Class: |
B60K
28/06 (20060101); B60K 28/00 (20060101); H02g
003/00 () |
Field of
Search: |
;180/99,82,82.7,114
;307/9,10 ;317/134 ;340/63,64,164,164A,164B |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Duggan; D. F.
Claims
Having thus described my invention, what I claim is:
1. In a motor vehicle provided with a source of voltage, an
ignition switch and a starter circuit, inhibitor means connected
between sad ignition switch and said starter circuit for
controlling the energization of said starter circuit and
comprising; random noise-generating means, clock means for
generating a timing signal, counter means, gate means responsive to
the output of said clock means for gating the output of said
noise-generating means to said counter means at fixed intervals of
time to store in binary form a first plurality of random numbers in
said counter means, display means, means connected to said counter
means for energizing said display means to display code symbols
related to said first plurality of random numbers, means for
deenergizing said display means a predetermined interval of time
after said first plurality of random numbers are displayed,
manually actuable switch means including a plurality of selectively
actuable switches corresponding to said code symbols, encoder means
for providing a binary output in response to actuation of said
switches, shift register means responsive to the output of said
encoder means for storing a second plurality of binary numbers,
means for comparing said first binary numbers in said counter means
with said second binary numbers in said shift register means and
for developing a first logic output indicative of the comparison,
means responsive to deenergization of said display means for
providing a second logic output a predetermined interval of time
after deenergization of said display means, means for performing a
logical AND function and responsive to said first and second logic
outputs for providing a control signal to said starter circuit.
2. The system defined in claim 1 further comprising means
responsive to simultaneous actuation of two or more of said
switches for disabling said logical AND function performing
means.
3. In combination a clock mechanism, means cooperating with said
clock mechanism to produce during a sequence of clock intervals a
succession of random symbols in code, means for respectively
storing each of the coded symbols in the sequence produced, means
for respectively decoding each of the coded symbols and for
respectively displaying each of the symbols in visible form and in
the sequence in which the coded symbols were produced,
operator-actuable means bearing indicia corresponding to respective
ones of each of the symbols displayed and actuable to produce coded
symbols of sequence selected by the operator, means effective to
compare respective ones of the coded symbols produced by said
operator-actuable means and in the sequence produced thereby with
respective ones of the stored coded symbols and in the sequence
stored, and elements operable when the compared coded signals
coincide.
4. Apparatus for preventing operation of a motor vehicle by an
incapacitated person comprising means for displaying a succession
of random ones of predetermined symbols in spaced positions for a
fixed interval of time, operator-actuable selector means including
individual actuable members provided with indicia corresponding to
the predetermined symbols, means providing a control signal when
the operator actuates the individual members in sequential order
corresponding to the sequence of the symbols displayed and within a
predetermined interval of time, and means responsive to said
control signal for preventing operation of said vehicle.
5. In a motor vehicle provided with a starter circuit apparatus for
controlling starting of the motor vehicle comprising bistable means
coupled to the starter circuit and normally preventing energization
of said starter circuit but actuable to permit energization of the
starter circuit, display means capable of displaying one of a
plurality of symbols in any one of a plurality of positions,
display control means including first time-delay means coupled to
said display means for generating a control signal effective to
cause a succession of random symbols to be displayed for a first
interval of time and removed after said first interval of time, a
plurality of manually actuable switch means energizable after said
first interval of time, each switch means provided with a symbol
corresponding to respective ones of said plurality of symbols,
means coupled to said display control means and said manually
actuable switch means for actuating said bistable means in response
to actuation of said switch means in a sequence corresponding to
the symbols displayed, second time-delay means energizable at the
conclusion of said first interval of time for preventing actuation
of said bistable means after a second interval of time.
6. Apparatus for preventing operation of a motor vehicle by an
incapacitated person comprising control means coupled to operating
apparatus on said vehicle, said control means having an enabled
condition permitting operation of said vehicle and a disabled
condition preventing operation of said vehicle, a display unit
mounted on said vehicle in a position to be viewed by an operator
thereof, means connected with said display unit for providing
unanticipated different sequences of graphical information in the
form of a position sequence of symbols to be displayed on said
display unit for a predetermined length of time, manually operable
means having indicia which correspond to the symbols respectively
so that a person with capacity can manually actuate the same in
timed succession in response to the symbols displayed and their
position sequence, comparator means coupled to said manually
operable means of said display unit and said control means for
causing said control means to assume its enabled condition when an
operator of said vehicle manipulates said manually operable means
at successive times in exact correspondence with the position
sequence of the symbols previously displayed on said display unit
within a predetermined length of time after said information is
removed from said display unit, said control means remaining in its
disabled condition in the event the operator of said vehicle fails
to manipulate said manually operable means at successive times in
exact correspondence with the position sequence of the symbols
previously displayed on said display unit so as to prevent
operation of said vehicle by an incapacitated person.
Description
This invention relates to a vehicle operation inhibitor control
system, and more particularly to such a system which inhibits
vehicle operation until the operator has performed a test to
determine whether his ability to safely operate the vehicle has
been impaired.
An object of this invention is to provide a system which prevents
starting of a motor vehicle until the operator has successfully
performed a physiological test involving visual recognition, short
term memory, and coordinated motor response.
Another object of this invention is to provide a vehicle operation
inhibitor which requires the operator to accurately respond to a
randomly generated display each time the vehicle is to be operated
so that the test does not become a conditioned response.
In accordance with the present invention a random number is
generated and displayed to the vehicle operator for a fixed
interval of time subsequent to closure of the ignition switch.
Generation of the number is accomplished by gating a random
frequency signal to binary counters where the number is stored. The
number stored is decoded and employed to drive a digital display
unit, After the aforementioned interval of time, the display is
disabled and a keyboard unit is enabled. In order to start the
vehicle, the operator must be able to remember the number displayed
and actuate the appropriate numbered key of the keyboard unit
within a fixed interval of time. Each key number depressed by the
operator is encoded in binary form and compared with the stored
number to provide a starter circuit control signal indicative of
whether the operator has depressed the correct keys. Means are also
provided for preventing the starter circuit energization in the
event the operator depresses more than one key at a time.
Other objects and features of this invention will be apparent from
the following detailed description which should be read in
conjunction with the drawings in which
FIG. 1 is a functional block diagram of the system;
FIG. 2 is a more detailed block diagram of the system;
FIG. 3 is a partial schematic and partial block diagram of the
random-number-generating portion of the system;
FIG. 4 is a logic diagram of the encoder employed in the
system;
FIG. 5 is a diagram of a portion of the disabled logic employed in
the system;
FIG. 6 is a logic diagram of the key advance employed in the
system;
FIG. 7 is a more detailed block diagram of the comparator employed
in the system.
Referring now to the drawings and initially to FIG. 1, the
inhibitor system is shown as connected between an ignition switch
10 and the starter circuit of the vehicle. The ignition switch 10
is connected to the positive terminal of a battery 12 the negative
terminal of which is grounded. The system includes a random number
generator 14 which controls a display unit 16. The random number is
displayed for a time interval determined by a display time selector
18. After this time interval has elapsed, the displayed number is
removed from the display 16 and a keyboard unit generally
designated 20 is illuminated. The operator of the vehicle is
required to depress the appropriate pushbuttons switches 1-0 within
a time interval determined by a write time selector 22 in order to
energize the starter circuit. To meet this requirement the selector
22 provides one input to an AND gate 24. A comparator 26 compares
the number displayed with that generated by the operator from the
keyboard unit 20, and if the number displayed and the number
generated by the keyboard are identical, a second input to AND gate
24 is provided which actuates a set-reset flip-flop 27 to energize
the starter circuit. If the number displayed is not accurately
generated from the keyboard 20 or is accurately generated but not
within the time fixed by selector 22, the flip-flop 26 is not set
and the starter circuit cannot be energized.
Referring now to FIG. 2 the system is shown in greater detail. The
random number generator 14 comprises a 0.1-second clock 28 which
drives a decade counter 30. The decade counter 30 provides seven
outputs at 0.1-second intervals to gate a random frequency signal
from a noise generator 32 through a gate 34 to respective ones of
seven 4-bit counters 36. The binary output of each of the counters
36 is fed to a decoder/driver unit 38 which decodes the binary
signal and energizes a segmented display unit 40 to display the
number. The final output of the decade counter 30 which occurs at
0.8 seconds sets a flip-flop 42 which provides an input to data
flip-flop 43. The data flip-flop 43 has its clock input C connected
with the output of the flip-flop 42, and its data input D connected
with B+. The flip-flop 43 is initially reset to provide a "zero" at
its Q output terminal and a "one" at its Q output terminal. The Q
terminal of flip-flop 43 provides one input to an AND gate 44. The
other input to the AND gate 44 is received from the clock 28. The
output of the AND gate 44 is fed to a divider 46 which divides the
output pulses by 5 to provide a 0.5-second clock input to the
display time selector 18.
The display time selector 18 comprises a decade counter 48 which
provides 10 outputs. Any one of which is selectable by a select
switch 50 for the purpose of selecting a display time between 0.5
and 5 seconds. The select switch 50 is connected with the reset
terminal R of flip-flop 42 to reset flip-flop 42 at the conclusion
of the display time selected. The carry output of the decade
counter 48 sets a flip-flop 52 which inhibits further operation of
the decade counter 48. The 0.8-second output from decade counter 30
sets the flip-flop 42 which clocks the flip-flop 43 to produce a
"one" at its Q terminal. This transition of the display gate signal
from a "zero" to a "one" starts the 0.5-second clock input to the
decade counter 48 and enables the decode/driver unit 38 thereby
displaying the random number on the unit 40. Upon passage of the
interval of time selected by the select switch 50 the flip-flop 43
is reset producing a "zero" at the Q terminal and a "one" at the Q
terminal. This removes the 0.5-second clock input to the decade
counter 48, disables the decode/driver unit 38, removing the random
number from the display unit 40.
The Q terminal of flip-flop 43 is connected with an AND gate 54
which also receives an input from the carry output of decade
counter 30. The AND gate 54 thus provides a 1-second clock input to
the write time selector 22 which comprises a decade counter 56
providing ten separate outputs at 1-second intervals, a select
switch 58 is adapted to select a write time of between 1 second and
10 seconds, and a flip-flop 59 which inhibits further operation of
the decade counter 56 upon receipt of the carry signal from the
decade counter 56. A data flip-flop 60 has its clock input terminal
connected with the Q terminal of data flip-flop 43 and its data
terminal D connected with B+. The flip-flop 60 is normally reset to
provide a "zero" at its Q output terminal. At the conclusion of the
display time as selected by the switch 50, the "one" at Q terminal
of flip-flop 43 is fed to the C input of data flip-flop 60 to
transfer the "one" on the D terminal to the Q terminal. This
provides a "one" input to the AND gate 24 as well as energizing the
keyboard light which illuminates the keyboard switches 1-0 and
signals to the operator that the write time has now commenced and
he should begin pressing the appropriate pushbutton switches.
The pushbutton switches 1-0 control a keyboard encoder 64 providing
a binary output to seven 4-bit shift registers 66. The binary
numbers from the encoder 64 are inserted into the individual shift
registers under the control of a key advance 68 which responds to
the pushing of each individual switch 1-0. The outputs of the shift
registers 66 are compared with the outputs of the counters 36 in
the comparator 26 and the results of that comparison are fed to the
AND gate 24. The output of comparator 26 is a "one" if the operator
has actuated the correct pushbutton in the proper sequence.
Otherwise, the output of comparator 26 is a "zero." The AND gate 24
also receives an input from disable logic 70 which provides a
"zero" input to the AND gate 24 in the event that the operator
attempts to press more than one key at a time.
At the conclusion of the write time as determined by the position
of the select switch 58 the data flip-flop 60 is reset to establish
a "zero" on the Q output terminal deenergizing the keyboard light
in the unit 20 and disabling the gate 24.
Referring now to FIG. 3 the noise generator 32 comprises a zener
diode 72 which is connected to the B+ through a resistor 74. The
zener diode 72 generates white noise which provides the random
frequency required for the random number generation and which is
amplified by a two-stage transistor amplifier 76 to a level
compatible with the threshold level of the gate 34. The gate 34 is
shown to comprise a plurality of AND gates 34a-34g which receive
one input from the generator 32 and a second input from set-reset
flip-flops 34a'-34g'. The set-reset flip-flops 34a'-34g' are reset
from individual output terminals of the decade counter 30 at time
0.2 seconds through 0.8 seconds respectively. During the 0.7-second
interval the AND gates 34a-34g are sequentially enabled and,
therefore, gate a random number of pulses, to the respective 4-bit
counters 36a-36g, determined by the frequency variations in the
output of generator 32 during the time the respective gates 34a-34g
are enabled. The output of the bit counters 36a-36g are fed to
respective decode/drivers 38a-38g. The decode/drivers 38 are
enabled and disabled by the "one" and "zero" output respectively
from the Q terminal of data flip-flop 43.
Referring now to FIG. 4 the keyboard encoder 64 comprises OR gates
78, 80, 82, and 84 which provide a binary representation of the
particular pushbutton switch actuated. By way of example, the
generation of the binary number representing closure of pushbutton
5 is accomplished in the following manner. Pushbutton switch 5 is
connected only to OR gates 78 and 82 and thus upon closure of
pushbutton switch 5 a "one" output is obtained from OR gates 78 and
82 and a "zero" output is obtained from OR gates 80 and 84
generating the binary number 5 (0101).
Referring now to FIG. 5 the disable logic 70 is shown to comprise a
plurality of set-reset flip-flops 86a, 86b, 86c, etc., connected
with respective ones of the pushbutton switches 1-0. The outputs of
the flip-flops 86b and 86c are connected as inputs to AND gates
88a, 88b respectively. The output of 86a is connected to both AND
gates 88a and 88b. The outputs of gates 86a and 86b are connected
to an OR gate 90. The output of the OR gate 90 is connected to a
set-reset flip-flop 92, the output of which is inverted by an
inverter 94 and applied to AND gate 24. Should the operator depress
both pushbutton switches 1 and 2 a "one" output occurs at AND gate
88a which is passed through the OR gate 90 to set flip-flop 92 and
provide a "one" input to the inverter 94 which provides a "zero"
output. The "zero" output from inverter 94 will prevent setting of
the flip-flop 27 thereby preventing operation of the vehicle
starter circuit. The same sequence of events will occur should the
operator actuate pushbuttons 1 and 3 simultaneously, since a "one"
output would be obtained from AND gate 88b. The remaining portion
of the disable logic operable in response to simultaneous actuation
of others of the pushbuttons will be apparent to those skilled in
the art, and in the interest of brevity is omitted.
Referring now to FIG. 6 the key advance 68 is shown to comprise in
OR gate 96 which receives an input from each of the pushbutton
switches 1-0. The output of OR gate 96 clocks a decade counter 98
which enables the appropriate shift registers 66 to receive the
coded number corresponding to the key depressed.
Referring now to FIG. 7, the comparator 26 is shown to comprise
nine individual comparators 26a-26i. The binary numbers from four
of the shift registers 66 are compared with the binary numbers from
four of the counters 36, in the comparators 26a-26d. If the binary
numbers are the same, outputs from each of the shift registers
26a-26d are fed to the comparator 26e which provides an output to
the comparator 26i. The binary numbers from the three remaining
shift registers 66 are compared with the binary numbers from the
three remaining counters 36 in the comparators 26f-26h. If the
binary numbers are the same, outputs from the comparators 26f-26h
are fed to the comparator 26i which produces a logic "one" output,
if all seven binary numbers are the same, and a "zero" output, if
any of the numbers are not the same. The output of comparator 26i
is fed to the AND gate 24.
* * * * *