U.S. patent number 3,603,844 [Application Number 04/846,398] was granted by the patent office on 1971-09-07 for electronic delay multiperiod initiating system.
This patent grant is currently assigned to Hercules Incorporated. Invention is credited to Fred A. Fritz.
United States Patent |
3,603,844 |
Fritz |
September 7, 1971 |
**Please see images for:
( Certificate of Correction ) ** |
ELECTRONIC DELAY MULTIPERIOD INITIATING SYSTEM
Abstract
A device for providing electronically delayed multiple point
initiating current to electrical initiators in blasting circuits is
provided. The device has a plurality of firing circuits each of
which employs a firing capacitor connected to a silicon controlled
rectifier. A plurality of buffer circuits connected in parallel are
provided, each buffer circuit having at least one capacitor which
is connected to the control gate of a silicon controlled rectifier
of a firing circuit. A timing circuit sequentially actuates
discharge of each buffer capacitor into the gate of the silicon
controlled rectifier of a corresponding firing circuit whereby the
silicon controlled rectifier is made conductive allowing the firing
capacitors to discharge into the firing circuit.
Inventors: |
Fritz; Fred A. (Hockessin,
DE) |
Assignee: |
Hercules Incorporated
(Wilmington, DE)
|
Family
ID: |
25297816 |
Appl.
No.: |
04/846,398 |
Filed: |
July 31, 1969 |
Current U.S.
Class: |
361/249; 307/108;
327/473; 102/217; 361/251 |
Current CPC
Class: |
G01V
1/08 (20130101); H03K 17/292 (20130101); F42D
1/055 (20130101) |
Current International
Class: |
F42D
1/055 (20060101); F42D 1/00 (20060101); H03K
17/292 (20060101); G01V 1/02 (20060101); H03K
17/28 (20060101); G01V 1/08 (20060101); F23q
007/02 () |
Field of
Search: |
;307/106-108,112,110,252.53,252.54 ;317/148.5B,151,139,80 ;102/70.2
;373/275C ;320/1 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Duggan; D. F.
Claims
What I claim and desire to be secured by Letters Patent is:
1. A device for providing electronically delayed multiple point
initiating current to electrical initiators of a blasting circuit
for initiation thereof, said system comprising
a. a plurality of firing circuits connected in parallel between a
first DC power source and a common base connection, said firing
circuits comprising resistance means, blocking diode and firing
capacitor connected in series and a silicon controlled rectifier
having an anode, cathode, and control gate, said firing capacitor
being charged through the resistance means by the first DC power
source to the potential desired in the blasting circuit, one lead
of the firing capacitor being connected to the cathode of the
silicon controlled rectifier, the anode of the silicon controlled
rectifier being connected to the blasting circuit,
b. a plurality of buffer circuit means connected in parallel
between a second power source and the common base connection, each
buffer circuit means comprising at least one buffer capacitor
connected to the gate of the silicon controlled rectifier of the
firing circuit, said buffer capacitor being charged by the second
DC power source and
c. timing circuit means connected to each of the buffer circuit
means for sequentially actuating discharge of the buffer capacitors
into the firing circuits whereby the silicon controlled rectifiers
in the firing circuits are made conductive thereby sequentially
discharging the firing capacitors into the blasting circuit.
2. The device of claim 1 wherein the buffer circuit means comprises
a resistance means connected in series with the buffer capacitor, a
second silicon controlled rectifier having an anode, cathode and
control gate, and a blocking diode having an anode and a cathode,
the anode of the second silicon controlled rectifier being
connected to the junction of the resistance means and buffer
capacitor, the anode of the blocking diode being connected to the
cathode of the second silicon controlled rectifier, the cathode of
the blocking diode being connected to the control gate of the
silicon controlled rectifier of the firing circuit, said buffer
capacitor being charged through said resistance means by the second
DC power source.
3. The device of claim 2 wherein the timing circuit means is
comprised of plurality of timing circuits connected in series, said
timing circuits comprising a first variable resistance means and
timing capacitor connected in series, a Shockley diode, having an
anode and a cathode, and a third silicon controlled rectifier
having an anode, cathode and control gate, the anode of the
Shockley diode being connected at the junction of the timing
capacitor and first variable resistance means and the cathode of
the Shockley diode being connected to the control gate of the third
silicon controlled rectifier, the cathode of the third silicon
controlled rectifier being connected to the control gate of the
second silicon controlled rectifier of the succeeding buffer
circuit and to the variable resistance means of the succeeding
timing circuit; the anode of the third silicon controlled rectifier
being connected to a third DC power source, the timing circuit
being activated upon application of the third DC power source
whereby potential is built up on the timing capacitor until the
avalanche breakdown voltage of the Shockley diode is exceeded
whereby voltage is applied to the control gate of the third silicon
controlled rectifier making it conductive and permitting current to
flow to both the silicon controlled rectifier of the succeeding
buffer circuit making it conductive and to a succeeding timing
circuit.
4. The device of claim 3 in which a radio frequency suppression
circuit is connected between said first DC power source and the
firing circuit.
5. The device of claim 4 in which the radio frequency suppression
circuit comprises a switching means, a first resistance means and
at least one inductor connected in series with the first DC power
source, a plurality of capacitors connected in parallel between the
first DC power source and the common base connection, each
capacitor having one lead thereof connected to a lead of each
inductor, a second and a third resistance means connected in series
across the switching means, and another capacitor connected between
the common base and the junction of the second and third resistance
means.
Description
This invention relates to an electrical initiating system for
explosive charges and more particularly to a multiperiod
electronically delayed initiating device for initiation of blasting
caps.
An improved method and system for detonating an explosive
composition to enhance its explosive characteristics in a borehole
is disclosed in U.S. Pat. No. 3,457,859 to R. G. Guenter. This
improvement is accomplished by detonating the explosive composition
at more than one point along its length within a time interval
sufficient to produce more than two coexisting detonation fronts.
This technique is now more commonly referred to as multiple point
initiation.
Of primary importance in multiple point initiation is the ability
of the initiation device to detonate all the caps within a given
delay period within about 50 microseconds. This order of detonation
simultaneity is required to have the caps detonate the explosive
and not vice versa; and have all the caps detonate before this
detonation severs lead wires to undetonated caps. The term "delay
period" as used herein is defined as the time interval allowed for
any number of preceding charges to be initiated and to act upon
their assigned target such as rock areas in order to fragment and
move out the rock prior to detonation of succeeding charges.
Delay blasting caps such as short-period delay blasting caps lack
the detonation simultaneity within a given delay period required
for multiple point initiation and the delay precision required for
multiple point initiation. Commercially available switching devices
lack the current switching capability required to fire large
parallel cap loads generally required in blasting operations.
Accordingly, a primary object of this invention is to provide an
electronically delayed multiple point initiating device having the
capability to provide for continuous adjustment of the delay
intervals between any series of initiations of blasting caps and
having high current carrying capacity to reliably initiate large
numbers of blasting caps connected in parallel.
Other objects of the invention will appear hereinafter the novel
features and combinations being set forth in the appended
claims.
Broadly, in accordance with this invention an electronically
delayed multiple point initiating device for providing current to
electrical initiators of a blasting circuit is provided comprising
a) a plurality of parallel connected firing circuits comprising
resistance means, blocking diode and capacitor connected in series
and a silicon controlled rectifier, said capacitor being charged to
potential desired in the blasting circuit when a first switching
means is positioned conductive between a first DC power source and
the capacitor, said capacitor being connected through the normally
open silicon controlled rectifier to the blasting circuit, b) a
plurality of buffer circuit means connected in parallel, each
buffer circuit comprising at least one capacitor connected to the
gate of the silicon controlled rectifier of the firing circuit,
said buffer capacitor being charged when a second switching means
is positioned conductive between a DC power source and the buffer
capacitor, and c) timing circuit means connected to a power source
and to each of the buffer circuit means for sequentially actuating
discharge of the buffer capacitors into the firing circuit whereby
the silicon controlled rectifiers in the firing circuit are made
conductive thereby sequentially discharging the firing capacitors
into the blasting circuit.
Representative embodiments of the invention have been chosen for
purposes of illustration and description and are shown in the
accompanying drawings wherein:
FIG. 1 illustrates a representative power supply system for
providing power to the timing, buffer, and firing circuits shown in
the form of block diagrams.
FIG. 2 illustrates a typical timer and buffer circuit for use in
this invention.
FIG. 3 illustrates the firing circuit of the electrical initiating
system of this invention.
FIG. 4 illustrates a circuit for suppression of transients in the
cable connecting the power supply with the buffer, timing and
firing circuits.
Referring now to FIG. 1, a battery B-1 is shown connected to a
power inverter 10. A power switch S1 having contacts a,b on power
input lead 12 to the inverter and contacts c and d on power output
lead 14 from the inverter is shown in the open position. Power
switch S1 connects power output lead 14 to ready switch S2 and to
charge switch S3. Two batteries, B-2 and B-3, are connected to the
negative lead 16 (common base connection) of the inverter. Upon
closing of switch S1 and S2, capacitors C1-1 to C1-N in the buffer
circuit (shown in FIG. 2) are charged to the output voltage of B-2
through conductor 18. Upon closing of charge switch S.sub.3, energy
storage capacitors C3-1 to C3-N of the firing circuit (shown in
FIG. 3) are charged to the voltage required for discharge into the
blasting circuit. Upon closing of firing switch 4 relay K1 is
activated which in turn applies voltage from power source B-3
through conductor 20 to both the first buffer circuit and to the
first timing circuit whereby the storage voltage E1 is discharged
through output contacts 1 into the first blasting circuit. Through
subsequent operation of the timing and buffer circuits, the storage
voltages E2- EN are sequentially discharged through output contacts
2 to N into the blasting circuit.
In FIG. 2 the buffer and timing circuits are shown. Buffer circuit
1 is connected in parallel with buffer circuit 2 and buffer circuit
N; N being used to designate any given number of buffer circuits
identical with buffer circuit 1 and connected in parallel
therewith. Each buffer circuit is connected to power from battery
B-2 through conductor 18.
Buffer circuit 1 which is illustrative of the other buffer circuits
comprises resistors R1-1, R2-1, R3-1; capacitor C1-1; diode D1-1 is
and silicon controlled rectifier SCR1-1. Resistor R1-1 is connected
to battery B-3 through conductor 18 and to capacitor C1-1. One lead
of resistor R3-1 is connected to the control gate of silicon
controlled rectifier SCR1-1, and the other lead is connected to
conductor 20.
The cathode lead of silicon controlled rectifier SCR1-1 is
connected in series to resistor R2-1 which in turn is connected to
common bast 16. One lead of capacitor C1-1 is connected at the
junction of resistor R1-1 and the anode lead of silicon controlled
rectifier SCR1-1 and the other lead is connected to common base 16.
The anode lead of diode D1-1 is connected to the junction of
silicon controlled rectifier SCR1-1 and resistor R2-1. The cathode
lead of diode D1-1 is connected to the control gate of a silicon
controlled rectifier in the firing circuit fully described
hereinafter.
Timing circuit 1 of FIG. 2 which is illustrative of the timing
circuits is comprised of variable resistor R4-1, capacitor C2-1,
Shockley Diode D2-1, silicon controlled rectifier SCR2-1 and
resistors R5-1 and R6-1. This timing circuit provides the delay
period between discharge of firing capacitors in the firing
circuits. In the timing circuit, one lead of variable resistor R4-1
is connected through conductor 20 to battery B-3 and the other lead
is connected to capacitor C2-1. The anode of Shockley diode D2-1 is
connected at the junction of capacitor C2-1 and variable resistor
R4-1, and the cathode of Shockley diode D2-1 is connected to the
gate of silicon controlled rectifier SCR2-1. R5-1 connects the gate
of silicon controlled rectifier SCR2-1 to the common base 16 and is
used to establish bias conditions for both the gate of silicon
controlled rectifier SCR2-1 and Shockley diode D2-1. The cathode of
silicon controlled rectifier SCR-1 is connected through resistor
R3-2 to the gate of silicon controlled rectifier SCR1-2 of the
second buffer circuit and to variable resistor R4-2 of the second
timing circuit. The anode of silicon controlled rectifier SCR2-1 is
connected through conductor 20 to battery B-3.
In FIG. 3 the firing circuit is illustrated. Firing circuit 1 which
is illustrative of the firing circuits connected in parallel
therewith comprises resistors R7-1, R8-1, R9-1 and R10-1; diode
D3-1; silicon controlled rectifier SCR3-1; capacitor C3-1; and
output connections. One lead of resistor R7-1 is connected to the
output from inverter 10 through switches S1, S2 and S3 and through
conductor 14. The other lead of resistor R7-1 is connected to diode
D3-1 which is connected in series to capacitor C3-1. A bleeder
resistor R9-1 is connected across capacitor C3-1 to common base 16.
One lead of resistor R8-1 is connected at the junction of capacitor
C3-1 and diode D3-1 and the other lead is connected to the anode of
silicon controlled rectifier SCR1-1. Capacitor C3-1 is connected to
the output connections through resistor R8-1 and silicon controlled
rectifier SCR3-1 which in its natural state is nonconductive.
Resistor R10-1 is used to establish bias conditions for the gate of
silicon controlled rectifier SCR3-1.
FIG. 4 illustrates a typical radio frequency suppression circuit
which serves the function of suppressing transients which otherwise
could establish a high frequency oscillation within the cable
connecting the power means for operation of the device with the
buffer, timing and firing circuits which comprise the output unit
of the device. The radio frequency suppression circuit comprises
capacitors C1-F, C2-F, C3-F and C4-F; resistors R1-F, R2-F and
R3-F; and inductors L1-F and L2-F. The capacitors are all connected
in parallel with common base 16 and with inverter 10 through
conductor 14. Capacitor C1-F is connected at the junction of
resistors R1-F and R2-F which are connected across switch S1.
Inductors L2-F and L1-F are connected in series to resistor R3-F
which is connected to switch S3.
Charging of Capacitors of the Buffer and Firing Circuits
Capacitors C1-1 through C1-N of the buffer circuits previously
described are charged by closing switch S1 and ready switch S2.
Current flows through conductor 18 through resistors R1-1 to R1-N
charging capacitors C1-1 to C1-N to the voltage value of power
source B2. Following charging of the capacitors of the buffer
circuit (FIG. 2), the capacitors of the firing circuit (FIG. 3) are
charged by closing switch S3. When switch S3 is closed, current
flows through conductor 14 into the firing circuits charging the
capacitors C3-1 to C3-N. For example, current flows through
resistor R7-1, through diode D3-1 and charges capacitor C3-1. In
like manner the other firing capacitors are charged.
Operation of Buffer, Timing and Firing Circuits
The buffer control and period delay circuits described and
energized by closing of switch S4 (after switches S1, S2 and S3 are
closed). When switch S4 is closed relay K1 is activated closing the
associated contacts and the voltage from battery B3 is applied
through resistor R3-1 to the control gate of silicon controlled
rectifier SCR1-1 of the buffer circuit and to variable resistor
R4-1 of the first timing circuit. The voltage applied to the gate
of silicon controlled rectifier SCR1-1 makes it conductive thereby
allowing capacitor C1-1 of the buffer circuit to discharge
immediately through resistor R2-1 and diode D1-1 into the gate of
silicon controlled rectifier SCR3-1 of the first firing circuit.
Through operation of the firing circuit hereinafter described,
output voltage is sent immediately into the blasting circuit. The
delay period from discharge of the first storage capacitor until
discharge of the second storage capacitor in the second firing
circuit is determined by current flow through the timing circuit,
and more specifically by the time required to build up the voltage
on the capacitor C2-1 of the timing circuit to a higher voltage
than the breakover voltage of Shockley diode D1-1. When the
breakdown voltage of the Shockley Diode D2-1 is exceeded this diode
becomes conductive and voltage is immediately applied to the gate
of SCR2-1 of the timing circuit thereby making it conductive. With
silicon controlled rectifier SCR2-1 conductive current flows to
both silicon controlled rectifier SCR1-2 of the second buffer
circuit which becomes conductive and discharge capacitor C1-2
through resistor R2-2 and diode D1-2 into firing circuit 2 and
current flows to the second timing circuit which responds in the
same manner as timing circuit 1 previously described. Operation of
the timing circuit then continues to sequentially activate the
buffer circuit discharging the buffer capacitors into the firing
circuit and initiating the next timing sequence until ultimately
the last firing capacitor is discharged. Diodes D1-1 through D1-N
isolate the buffer circuits from transients which appear at the
gates of silicon controlled rectifiers SCR3-1 and SCR3-N.
The firing circuit is energized by discharge of the voltage of the
buffer capacitors such as C1-1 through resistor R2-1 and diode D1-1
into the gate of silicon controlled rectifier SCR3-1 thereby making
SCR3-1 conductive. With silicon controlled rectifier SCR3-1
conductive capacitor C3-1 previously charged to the voltage
necessary for operation of the blasting circuit is discharged.
The foregoing descriptions of a buffer circuit, timing circuit, and
radio frequency suppression circuit are illustrative of circuit
means that can be employed in combination with the firing circuit
heretofore described to provide the multiperiod electronically
delayed initiating system of this invention. The timing circuit can
be replaced with other suitable timing circuits such as a ring
counter circuit, or a shift register. Any suitable means for
supplying direct current to the electronic delay multiperiod
initiating device can be employed.
A typical multiperiod initiating device is prepared having the same
circuits as set forth in FIGS. 1, 2, 3 and 4. The parts parameters
utilized in these circuits are as follows:
FIG. 1--Power Circuits
__________________________________________________________________________
B-1 12-volt battery B-2 45-volt battery B-3 12-volt battery K1
Potter and Brumfield; Potter and Brumfield; KRP11AG, 12 DC Inverter
G.E. P1-S494787-G1
fig. 2 --buffer and Timing Circuits
__________________________________________________________________________
R1 10K .OMEGA. R2 1K .OMEGA. R3 10K .OMEGA. R4 10K .OMEGA. R5 10K
.OMEGA. R6 1000 .OMEGA. C1 8 .mu.fd., 50 DC C2 5 .mu.fd., 15 DC D1
IN 2071 D2 D1301 SCR-1 G.E.-C106F1 SCR-2 G.E.-C106F1
fig. 3 --firing Circuit
__________________________________________________________________________
R.sub.7 -R.sub.8 470 .OMEGA./2w. R.sub. R.sub.9 120K .OMEGA./2w.
R.sub.10 10K .OMEGA./1w. D3 Hitron-CR 2000 C3 860 .mu.fd., @ 450 DC
SCR3 G.E. No. C178M
fig. 4 --transient Suppressant Circuit
__________________________________________________________________________
C1, C2, C3, C4 0.05 .mu.fd., @ 600 v. R1-F, R2-F 47K .OMEGA./2w.
R3-F 1K .OMEGA./2w. L1-F, L2-F 10 h. @ 200 m.
__________________________________________________________________________
The foregoing multiperiod initiating system successfully detonates
in excess of 50 Vibrocaps (a static resistant, No. 8 strength E.B.
cap manufactured and sold by Hercules Incorporated) connected in
straight parallel without period overlap and with the required
simultaneity so that all caps detonated the explosive charge as
desired.
* * * * *