Production Of Justified Coded Tape For Page Printing

Abstract

Equipment for editing electrically coded page printing information which accepts an input from a keyboard (or tape reader) and stores coded information in an ultrasonic delay line. While the information is circulating, it is displayed on a Cathode Ray Tube by character generating circuits. The basic information is inserted in front of the displayed information and the whole is transferred to a secondary line ready to be fed out to a tape punch or type-setting machine. The spacing or justifying information is inserted directly in the second delay line or into the output stage.

Description

BACKGROUND OF THE INVENTION

When setting justified type by a tape-operated system, it is necessary to know the required width of spaces before starting the casting process, or photographic exposure, but this information is not available until the whole line has been keyed by the operator and some calculations made. Further, it is desirable that the operator can see what he has keyed, both for editing and for making decisions about ending the line and hyphenating, where necessary.

Typographic characters are of varying widths, such widths being described as fractions of the width of the widest character, the em quad.

Typically, the em is allocated a width of 18 units and other characters in the related fount will carry widths of between 5 and 18 units. An interword space may be allocated a basic minimum width of 3 or 4 units, but this space must be expanded by additional units in order to fill a particular line measure exactly and thus produce justified typesetting. Alternatively, or additionally, it may be desirable to add one or more units between individual characters (letter spacing expansion).

In those typesetting systems which require numerical information to expand lines as described, the operation of the typesetting machine is controlled by tape, carrying a function code ` Line end` . If the characters are to be read from the end of the tape and set backwards, it is simple to allot values to two codes X, Y read after the ` Line End` , of which code X is a number which is to be added to each word-space unit count equally across the line (the quotient obtained by dividing ` unit value of space unfilled ` by ` the number of interword spaces in the line` ) and Code Y represents the remainder, if any, resulting from said division. This remainder can then be distributed as desired, normally by adding one additional unit to the successive interword spaces read from the tape while, counting the number down until the remainder is exhausted.

If the characters are to be read in forward sequence from the tape, the ` Line End` function code and associated quotient and remainder codes, occur at the wrong end of a keyboard sequence, and must therefore be transferred, either by reversing the tape and rereading the characters once the justifying instructions codes have been reached, or by a storage system.

In the case of letterspacing as an alternative or additional means of line expansion, another function code is chosen which will cause one or two units to be added to all or some character widths=.

The object of the present invention is to simplify the procedure necessary to develop coded and edited line information in which the justifying codes common to a line precede the line-content codes for that line.

An important aspect of the invention is the use of intermediate high-speed storage, the use of line display equipment controlled by the intermediate storage, and the interpolation of justifying information preceding the line-content information.

The invention will be described with reference to an embodiment shown in the accompanying drawings, in which:

FIG. 1 shows a schematic layout of the equipment forming the embodiment;

FIG. 2 shows schematically the manner of storage of line of type character information and justifying information; and

FIG. 3 shows the method of forming characters on a Cathode Ray Tube, or other, Display. In serial operation on the CRT, lines 1-- 17 of the Union Jack outline occupy successive equal time intervals, and are selectively brighted up in the combinations shown on the chart for the individual characters.

The device about to be described accepts an unjustified continuous coded character input from a keyboard (or tape reader) and stores successive blocks of coded information of line length one at a time in turn in an ultrasonic delay line continuously-circulating store. While the information is building up in the s=tore and is circulating therein, the current continuously-varying store content is displayed on a cathode ray tube by means of character generating circuits. When the content of a line is determined, and the spacing or justifying information therefor is determined, the justifying codes are inserted in the store in front of the displayed information, and the whole transferred to a second delay line store ready to be fed out.

The insertion of the spacing or justifying information, could be directly into the second delay line store or even into the Output stage. The incoming word string is also sent in known manner to line justifying equipment of known type which also receives Line End, and transmits the justifying information for each line to the above equipment.

A typical typographic requirement is for 7 alphabets, i.e. upper and lower case in Roman, Italic and Bold style, and Small Capitals (one case only), plus a group of 32 numerals and special characters (` Alphabet No.8 ` ). For this, up to 256 character identities are made available, by means of an 8 -bit binary code. In order to accommodate up to 90 characters, the delay line stores must each store approximately 9 .times. 8 bits and this means using a store having a circulation or cycle time approximately between 3mS (for a 250 Kc/s bit rate) and 750 uS (for a 1 Mc/s bit rate). It is a great convenience if the characters are written one at a time, in turn, on the Cathode Ray TUbe, at a rate such that persistence of vision allows the whole line to be displayed since this gives considerable economy of circuitry. However, of only one character out of 90 in a displayed line is brightened during each delay line cycle the 90 characters will be brightened in turn during each 90 -cycle period and there will be a 90 .times. 3 mS (or 90 .times. 750 uS) interval between successive writing of each character, which gives rise to an objectionable flicker in the display. This flicker can be reduced by using a long persistence Cathode Ray Tube, but this is liable to give a double image when replacing one line with another. If the characters are stored in the delay line in sequence as they are put in, and each letter is displayed every time it circulates, then the writing rate is one letter per 32 uS (for a 250 Kc/s bit rate) or 8 uS (for a 1 Mc/s bit rate), which makes an inconveniently high speed for generating the waveforms required for writing the character.

Accordingly a novel method of storing letters in the delay line is hereafter described, whereby individual characters are stored in the delay line in every 12th set of eight bits, or character position for example, with a shift of one character position after every eighth character. This shift of one position can be produced in one way by making the number of character positions in the delay line 95 or 97, for example, instead of 96 so that the 9th, 17th, 25th characters are stored in the positions 2, 3, 4 assuming that the first letter was in position 1, or in positions 97, 96, 95, respectively. Alternatively, the divide-by-twelve circuit is advanced or retarded by one after 8 positions have been selected when the delay line contain 96 character positions.

The method of accomplishing this is as follows. It is, a well-known principle, when using delay lines, to have a counter, controlled by a ` clock` which synchronizes the transmission of pulses circulating in the line, and to constantly compare the state of the counter with that of an address register: when concidence is detected, the position in the information circulating in the delay line corresponding to the address in the register has been reached, and the relevant information can be inserted, extracted, or displayed--according to the requirements of the system. Again it is normal practice to advance the address register by one whenever a new group of information pulses is to be inserted or extracted, and in consequence the register is conveniently made in the form of a counter.

The use of the numbers 8 and 12 is not essential, and any suitable combination could be used of which the product equals the required number of groups circulating in the line. For instance, for 100 groups 10 and 10 could be used; for 85 17 and 5 could be used, etc.

The equipment includes time cycle control apparatus comprising a clock pulse generator CPS, an eight element character code counter DVI, a cycle controller in two parts, the first part being designated CPC 1 which divides the pulse output of DVI by twelve and the second part being designated CPC 2 which divides the pulse output of CPC 1 by eight, input and output coincidence detectors ICD and OCD each connected to the first and second cycle controller parts CPC 1 and CPC 2 and respectively connected to input address registers IAR 1 and IAR 2 and the output address registers OAR 1 and OAR 2.

An input register IR is fed from a keyboard KB or tape reader TR. Signals from the input register IR are fed through a gate IG, controlled from the input coincidence detector ICD, and through an OR gate IOG to an input delay line store IDL, which may preferably be an ultrasonic delay line, an additional input of the OR gate IOG being connected to the output of the delay line store IDL so that signals are continuously recirculated in the delay line store IDL. The output of the input delay line store IDL is additionally connected through a gate TG to an output delay line store ODL, gate TG being controlled from a final position detector FPD connected to the first and second parts IAR 1 and IAR 2 of the input address register. The output delay line store ODL is connected through a gate OG to an output register OR having an output line OCH. Gate OG is controlled from the output coincidence detector and signals from the output register OR are applied to the first output address register part OAR 1.

Display apparatus is provided comprising a display sequence controller DH operated from the pulse output of DVI through a pulse suppressor gate HG controlled from the first and second cycle controller parts CPC 1 and CPC 2, for staggering successive character subcycles extracted from the input delay line IDL. A display register DR receives characters to be displayed from the input delay line IDL. A character decoder LD is connected to the display register DR and to a bright-up register BUR, connected to a cathode ray tube CRT. An alphabet decoder AD is connected to the display register DR and to the cathode ray tube CRT. Flag generator UJG and an X-deflection ramp generator XC are connected to the display sequence controller DH. Display sequence controller DH is connected to a gate DH. Display sequence controller DH is connected to a gate DG to control application of signals from the input delay line store IDL to the display register DR.

A careful analysis of the requirements of the sequence controller DH shows that if it is allowing a group to pass to the display circuits when it attains the number 11, it should be retarded by one every time the main counter or cycle controller CPC 1, CPC 2 passes 7-- 9 (the first digit is in octal radix and the second digit is in duodecal radix).

If this is done, the indexing of the letters on the Cathode Ray Tube can be conveniently done by means of a digital-to-analogue converter controlled by the sequence controller DH. The coincidence detector ICD between the address register IAR and the main counter CPC can consist of diode or resistor logic gates arranged to give an output when every bistable flip-flop in CPC is in the same state as the corresponding bistable flip-flop in the IAR. The use of counters formed from bistable flip-flops connected as binary dividers is not an essential part of the system, and the same result could be achieved by using ring counters, also with a method of detecting coincidence between them: or any other suitable technique.

The address register IAR is started off-normal; for example at 0-- 3 (first digit duodecal, second digit octal) which corresponds with the group counter 3-- 0 (first digit octal, second digit when the justifying information; instead of the `Line End` code, the increment to be added to every space, and the unit remainder increments which must be added to some spaces only; is determined, the address register IAR is reset to 00, and the justifying codes are fed into the delay line. Thus the justifying information occurs in front of the letter information in the delay line. When the coded information is received from a keyboard, it could be arranged for the `Line End` code to be sent by the operator and to be directly inserted in the delay line at the end of the line formation so information so as to apply to its own line instead of to the preceding line, the justifying information being separately determined and inserted in the delay line in front of the line information to which it relates.

When all the justifying information has been received, the contents of the delay line are transferred to a second delay line ODL which is clocked in synchronism with IDL, and is of the same length; consequently, the main counter CPC can be used for identifying the position of information in the second line also. A second address register OAR, constructed similarly to the first, is used to remove the groups one by one in the correct sequence and feed them out, either to a photographic typesetting machine, to a tape punch, or to another sequential storage medium.

The operation of FIG. 1 will be described in detail:

The clock pulse source CPS is continuously supplying electrical DC pulses at a rate of 255 Kc/s. The pulses are divided by 8 in DVI, so that taking 255 Kc/s as the bit rate, the output to the Clock Pulse Counter CPC is at an `8-bit word` rate.

CPC has a cycle of 96 pulses which is adequate for handling the line lengths of the order of 90 characters which are contemplated.

Thus the time period of a CPC cycle is 8.times. 12.times. 8/255,000 seconds = 768/255,000 or roughly 3 milliseconds, and a delay line store will be provided having a length giving a delay of that order.

For any other clock pulse rate, the delay line length would be correspondingly chosen; thus for 1 MHz, the time period would be of the order of 768 seconds.

CPC 1, CPC 2 imposes its own cycle timing on each delay line store and thereby is able to control input to the Input Store IDL; application of the contents of the Input Store IDL to the Display Tube CRT; transfer from the Input Store to the output store ODL; and output from the Output Store ODL; since the stores operate in synchronism under control of CPC 1, CPC 2.

Operation of the keyboard KB or tape reader TR for transmission of a character causes in well-known manner, the transmission of an eight-bit binary code to the Input Step-up Register IR, which receives at keyboard speed and transmits at clock speed.

At the same time, a single pulse is sent to the Input Address Register IAR 1, IAR 2.

As stated previously, the first Delay Line character storage position is to be spaced from the beginning of the Delay Line Cycle, so as to leave room for Justification, and possibly Line End, Information.

IAR is therefore arranged to set up a condition identifying the spaced starting position in response to the first signal received from KB, and to take equal steps in response to succeeding signals.

Assuming that the Stores and the Registers are empty, with the counter CPC cycling, transmission of a character from KB or IR is accompanied by a signal to IAR, which is set to the off-normal first character position. When CPC arrives at the same position, the Input Coincidence Detector ICD responds, primes the Input Gate IG, and signals to IR to send the stored character at clock speed into IDL via IG, and via an OR-gate IOG, via which circulation of the contents of IDL also takes place.

On the next character transmission, a second pulse is received by IAR. For the Divide-by-8 part CPC 2 to move from one position to another in a cycle, its Divide-by-12 part CPC 1 will have received 12 character-period pulses from DV1, so that since the CPC cycle and the IDL cycle are in synchronism, ICD will detect the No. 2 character position coincidence, when the character position in IDL, which is twelve positions removed from that in which the first character was stored, is positioned to receive input from IR via IG.

It will be seen that since KB (or TR) is pulsing the Divide-by-8 part IAR 2 of the Address Register direct, it is in effect stepping the Address Register to the same extent as the Counter CPC 2 would step in response to 12 character pulses from DVI to CPC 1.

The pulses from KB to IAR occur, of course, at arbitrary times in relation to the repetitive pulse cycle of the counter, and each time a character indication is inserted into IR, and the setting of IAR is correspondingly changed, ICD is operated when the counter CPC 2 next achieves the same setting as IAR and the character in IR is transferred into the twelfth character position in IDL beyond that in which the last character code was inserted.

The character display sequence using straight numbering, for the whole content of a 96 -character store is to be 1, 13, 25, 37, 49, 61, 73, 85; 2,...., 86;....; 12, ...., 96 .

The sequence could be made to begin at any desired point within the delay line.

The above numbering presupposes some form of intersequence stepping device external to the delay line to cater for the 13-character steps 85..2; ...; 95...12. A similar result can be obtained by making the delay-line 95 or 97 ` character times ` long, instead of 96, in which circumstances, the character positions automatically precess by 1 at the end of each `run` through the store; e.g. 85 +12= 95+ 2; or 97 (after which the delay line steps to position 12).

While a line is building up in IDL, the characters are displayed, one at a time, in turn, in correct order, on the display CRT in the following manner.

The `character` clock pulses from DV1 are also routed to a Divide-by-12 display sequence controller DH via an OR-gate HG for character display control.

The contents of delay line IDL are constantly circulating therein via IOG, and at the same time are offered to 2-gate DG, which is also connected to DH. The display sequence controller DH also pulses an X-deflector control XC, and a Union-Jack X and Y deflection generator UJG which generates deflections for successive lines, or successive nonconflicting sets of lines (in an x-deflection sense), of the so-called Union-Jack composite character, FIG. 2, in synchronism with a cycle of a corresponding number of X-deflection cycles controlled by XC in response to a single stimulation from DH. A Union-Jack character basis consists of the two peripheral horizontal segments 3, 6, the four peripheral half-verticals 7, 8, 13, 14; the four radiating lines of the St. George's Cross (upright) 10, 11, 16, 17; and the four radiating lines of the St. Andrew's Cross (diagonal) 1, 2, 4, 5, selections from which give a recognizable imitation of all the alphanumeric characters required.

Each time DH has counted 12 pulses, it primes gate DG to allow a character to pass from IDL to a Display Register DR, which takes one multibit character at a time.

Of the eight bits of a character, three identify which of the various alphabets required in printing is to be used for the character, while the other five identify the character itself, and determine which lines of the Union-Jack Basis are required.

The Display Register DR applies three of its bits in parallel to an Alphabet Decoder AD and the other five bits to a character decoder LD.

Counting upper and lower case for each of roman; italic; and bold; together with small capitals, and treating numerals as an alphabet, there are eight different `alphabets` , which can be catered for with three binary digits.

The 26 letters of an alphabet can be catered for by five binary digits. The ten figures are catered for by using the same binary digits in a different decode matrix, selected when `figures` is detected by the Alphabet Decoder.

The alphabets are identified on the Display as follows: by way of example; `lower case` , `upper case` , and `small caps` are respectively shown on the line; above the line; and below the line. `Italic` characters are tilted by feeding a proportion of the `X` deflection signal into the Y deflection coils: and `bold` characters are made brighter than any of the others.

THe letter decoder LD controls the BRIGHT-UP register BUR, which is arranged to bright-up the CRT only for those deflection cycles in which the UJ segments forming the respective character, as indicated in FIG. 2, are traced, the complete character being seen by persistence of vision. It will be remembered that the character codes are inserted into every 12th character position of the Input Register IDL in turn; and the `Divide-by-12` Hopper DH ensures that each 12th character in IDL is extracted in turn during each Register cycle. If the number of character positions in the cycle is 95 or 97 , the positions from which characters are extracted in successive cycles will be automatically staggered by one from cycle to cycle so that the successive interpolated sets of characters in, for example; 1, 13, 25,...; 2, 14, 26,...; and so on; will be extracted in turn, as previously stated.

If however, IDL has a number of character positions which is a multiple of 12, then the `stagger` between sets of characters must be electrically introduced. This is done by arranging, for example, that the Clock Pulse Counter CPC applies an inhibition signal via lead IHL to gate HG after each complete 12.times. 8 character positional cycle so as to suppress the next pulse from DV1, whereby the ensuing character extraction cycle extracts the characters immediately succeeding the individual characters extracted during the preceding cycle: 1,13,..85;13, 2,14,..86;...;12,24,..96.

The spacing of the characters extracted from IDL allows sufficient time for each character to be adequately displayed on the CRT, and all the characters forming a line are brightened in turn cyclically, so that the whole line is displayed on the cathode ray tube CRT, and a linear array of characters are brightened in turn cyclically and displayed as a whole by persistance of vision.

By examination of the characters displayed serially in turn on CRT, the compositor is enable to decide where to end his line; to determine character spacing; to insert justifying and line-end codes, and to cancel and replace incorrect text.

Operation of the usual `Line End` key on keyboard KB will send a special signal to IAR to set it to zero, and adjust it so that Line End and subsequent justifying information is inserted serially in front of the line information.

FIG. 2 shows diagrammatically the positioning of information in the input delay line store IDL after insertion of justifying and line end information therein, it being noted that the justifying and line end information is inserted serially in front of the line information. It is also noted that the groups of information, each of which corresponds to a type character, are in staggered or time interleaved relationship, a plurality of other groups being interposed between each group and the next successive group. Thus between groups 1 and 2, eleven groups 9, 17, 25, 33, 41, 49, 57, 65, 73, 81 and 89 are interposed, another series of eleven groups are interposed between groups 2 and 3, and so on.

A Final Position Detector FPD is connected to IAR so that the complete receipt of the Justification Information is detected, and is used to prime a Transfer Gate TG thru which the line contents of IDL pass to a second recirculating Output Delay Line ODL, so as to free IDL for receipt of the succeeding Line Information. Store ODL is connected by a 2-gate OG to an Output Register OR. Gate OG is primed by a second Coincidence Detector OCD between the Clock Pulse Counter CPC 1, CPC 2 and the Output Address Register OAR 1, OAR 2 impulsed from the Output Register OR.

Whereas IAR is arranged primarily to select staggered cycles of spaced clock positions for storing characters, followed by serial recording of the Line End and Justifying Information, OAR is arranged primarily to extract the (Line End and) Justifying information, followed by the character codes in the order in which they were recorded.

The Output Register OR is arranged to send a pulse to OAR each time it receives a code, and OAR controls OG in such a manner that OG is opened for a period sufficient only for a single character code to pass form ODL into OR.

Register OR can be organized in any desired manner: for example, as a `single character` repeater; or to transmit a complete line with correct layout spacing via output channel OCH for the control of a photographic typesetting machine, or a tape punch.

The use of the second delay line can be obviated by using either a double-length line or a double-frequency line. With a double-length line the two addresses have one extra bit at the most significant end and the coincidence detector logic includes the first bit of the extra duodecal divider on the end of the group counter. In this system the change of position in the delay line can be achieved by adding or subtracting one from the first stage of the duodecal divider, or by changing the extra bit at the most significant end of the addresses. The effect of either change is to reverse the relative positions of the two addresses with respect to the information in the delay line. With a double-frequency line, either the groups can be interleaved, or the bits of the groups can be interleaved; in these cases extra bits are added at the least significant ends of the addresses, and the changeover is effected in a similar manner to that described above, i.e. either the address or the counter can be changed.

Though these two alternatives have been designate double-length and double-frequency, the method of operation described for a doublE-length line can be applied to a double-frequency line if the basic character writing rate for the whole system is doubled; similarly, the method of operation described for the double-frequency line can be applied to the double-length line if the character writing rate is halved.

By varying the length of line, the basic clock rate, the character writing rate, the number of characters stored, and the number chosen for the `hopper` , a variety of systems can be produced to meet the requirements of the input and output devices used.

The display system makes use of the fact that the legible letters can be formed by selecting certain portions of a figure consisting of a rectangle, FIG. 2, bisected vertically, horizontally, and in both diagonal directions. Such a figure is sometimes known as a Union-Jack or simply as a `flag.`

The flag can be `written` on the face of a CRT by ramp generators made with transistor-capacitor charging circuits which are arranged to give the appropriate X and Y deflection of the electron beam. The timing of the charging circuits is controlled by a counter fed by a pulse generator which also drives a shift register containing the bright-up information required to write a given letter; thus the bright-up circuits and the flag generator are synchronized, and any letter can be written as required.

The appropriate bright-up information can be fed into the shift register by diode/transistor/resistor matrices which decode five bits of the letter code circulating in the delay line and then generate the bright-up code.

The remaining three bits of the letter code describe which alphabet is required, and these are used to indicate the alphabet.

The input to the line stores and display has been described above as being from a keyboard. However, the machine has further application as an editing machine, and for this purpose switches can be provided to enable the input to be taken from a tape reader or similar automatic input, under the control of the operator. When any lines which require alteration are fed in automatically, the operator can stop this input in well-known manner, erase the unwanted information by the use of the Address Register and transfer gates similar to TG, insert the corrections by means of the keyboard, and then restore the machine to automatic input. Thus the output tape contains the corrected information.

As stated the output can be fed direct to a high-speed photographic type-setting machine. The method of packing the information in the delay line enables a high rate of character readout to be obtained, if required.

As described above, the tape controlling method presupposes that justifying instructions have been calculated by associated equipment, such as the keyboard, or a computer. It is also advantageous, however, to read an unjustified or word-string tape into the delay line store and display the characters, while sampling character widths and minimum word-space widths, so that a high-speed justifying calculation can be made at each `code-read` , and the line ended by inserting the appropriate function and numerical codes at a chosen word-space encountered within the desired justifying tolerance. If no word-space is encountered before the line length is overfilled, the display will indicate by bright marker the maximum permitted line width so that an attendant may hyphenate at a suitable point, or alter the justifying tolerance.

The justifying information can of course be automatically generated by adding up the individual character and intercharacter widths, subtracting from the line length, and dividing by the number of intercharacter spaces, so as to obtain an intercharacter space width and a remainder, constituting the justifying information.

Keyboard KB can be switched over to the initial part of Output Store ODL, or to the Output Register OR, in place of Input Register IR, and the justifying information can be set up on KB for transmission into such store or register.

Claims

I claim:

1. A typesetting control system or the like for sequentially responding to a plurality of series of coded input signals each series representing a line of type characters, comprising: input register means, means for supplying a series of coded input signals to said input register means, storage means having an information storage capacity greater than the maximum information in any one of a series of said coded input signals to permit insertion therein of justifying information in addition to line of type information therein, said storage means being arranged to cyclically recirculate information stored therein at a relatively high speed, first gate means between said input register means and said storage means, first control means for said first gate means arranged for gating coded signals from said input register means to said storage means during a plurality of successive recirculatory cycles of said storage means to store in a predetermined order coded signals corresponding to said series of said coded input signals, means for feeding justification code signals to said storage means to be stored therein in a predetermined ordered relationship to said signals corresponding to said input signals, an output channel, second gate means between said storage means and said output channel, and second control means for said second gate means which is operative during a plurality of successive recirculatory cycles of said storage means for feeding to said output channel a first series of output signals representing a line of type characters and a second series of output signals representing justifying operations to be performed with respect to said first series of output signals, said second series of output signals being fed to said output channel in advance of said first series of output signals.

2. A system as defined in claim 1, comprising: display means, means operable before justification and during a plurality of successive recirculatory cycles of said storage means for feeding coded signals from said storage means to said display means and for developing a visual indication of a line of type characters corresponding to said coded input signals.

3. A system as defined in claim 1, wherein said series of coded input signals comprises a succession of groups of signals, each group corresponding to a type character, said first control means being arranged to direct said groups into said storage means in time interleaved relationship with a certain time spacing between each group and the next successive group substantially greater than the total time storage capacity of said storage means divided by the total number of said groups and with a plurality of other groups being interposed between each group and the next successive group.

4. A system as defined in claim 1, said storage means having an information storage capacity greater than the maximum information in any two successive series of coded input signals, and said second control means being operative to control gating of output signals representing one series of said signals through said second gate means while said first control means is operative to control gating of a successive series of input signals through said first gate means to said storage means.