Variable Speed Line Adapter

Abstract

A variable speed line adapter for receiving start-stop data transmission is normally set for reception at one speed and will examine the starting characters of received data at that speed. If the first received character is not a complete and valid starting character for the initial receiver speed, a shift is made to another receiver speed and the next data character examined. By a proper selection of starting characters, the adapter may be switched from one speed range to another until the line adapter is set to receive at the speed of the transmitted signal.

Description

OBJECTS OF THE INVENTION

Line adapters are well-known communications devices and are installed between a commercial data set and a data processor. A line adapter functions in data reception to sample the line voltage levels as provided by the data set and to supply the samples to the data processor with the required signal characteristics. In data transmission, the line adapter will function to convert the signals from the processor into data set controlling pulses. In both of such functions, it is necessary that the line adapter be operated at the correct speed so as to synchronize with incoming signals and to provide outgoing signals at the proper speed for the terminals connected to the transmission line.

In private wire systems, a terminal can be permanently connected to the main processor through a line adapter which will always operate at a single speed. If, however, a system includes a plurality of terminals of mixed transmission speeds, each of which can be connected to the processor over the commercial switched telephone network, it has heretofore been necessary to restrict each terminal to connection to only those line adapters which are operating at its transmission speed. Such a restriction forces a complicated arrangement for the system which must provide sufficient line terminals at each transmission speed to accommodate the expected traffic at that speed, effectively determining a separate transmission system for each speed rather than a single system as required for the total expected traffic.

By providing line adapters each of which will automatically adjust itself for reception of any speed of transmission within the system and which can be adjusted to send at any transmission speed used within the system, a simplification of the system and a reduction in the number of transmission lines can be effected. In such an adapter, there is no need for more line adapters than is required by the overall traffic load and a less expensive, more efficient transmission network results.

It is then an object of this invention to provide a variable speed line adapter for a start-stop transmission system to enable selective connection of terminals of different transmission rates to said line adapter.

It is also an object to develop a line adapter responsive to predetermined signal combinations transmitted from a terminal to adjust itself into synchronism with the transmission speed of said terminal.

Another object is to provide a line adapter having clock control circuits to adjust the clock speed of the adapter to one of a plurality of discrete rates under control of preliminary characters transmitted to said adapter from any one of a plurality of transmitting terminals having different rates.

A still further object is to provide a line adapter with clock control circuits responsive to reception of predetermined control characters to set said line adapter clock to one of a plurality of discrete operating speeds.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawing.

DRAWINGS

FIG. 1 shows a part of the pertinent circuits of a line adapter.

FIG. 2 shows the remainder of the pertinent line adapter circuits and an oscillator control to pass a selected oscillator output to the line adapter.

FIG. 3 is a diagram of the timing between two received characters.

FIG. 4 is a modification of the oscillator control circuits of FIG. 2 when more than two speeds of transmission are received.

FIG. 5 is another embodiment for selecting a proper one of a plurality of oscillator speeds.

DESCRIPTION OF THE INVENTION

The line adapter of this invention is herein described in a configuration which it would have if connected to a transmission control unit such as the commercial IBM Model 2702,one model of which is set out in the Richard et al. U.S. Pat. No. 3,337,855 issued on Aug. 22, 1967. The present line adapter could be used as one of the line adapters 54 shown in FIG. 1 of the patent. The line adapter will, in a start-stop system, be normally inactive with the transmission line at a mark level, i.e., with a significant voltage thereon. When the line drops to a space level the line adapter starts operation and sends successive samples of the line voltage to the attached transmission control unit (TCU) for assembly into a character. When a character has been assembled in the TCU, it sends a stop signal, see the bottom of FIG. 47 of the above Richard et al. patent, to terminate operations in the line adapter until another start signal, i.e., space, is received.

In the pertinent structure of the line adapter as indicated in FIG. 1, a stop flip-flop 11 will have been set by a pulse on a Set Stop line 12 from the TCU, see FIG. 47 of the above patent, to put a control voltage on its upper output 13. A transmit flip-flop 14 will be set for receive by a pulse on its initiate receive line 15, see FIG. 46 of the Richard et al. patent and can be set for transmission by a pulse on its initiate transmit line 16, see FIG. 47 of the patent. The output line 18 of transmit flip-flop 14 will be at a significant level when the flip-flop has been set for receiving.

Data will be received on a line 20 which may be either a switched private wire or, more usually, the output of a commercial data set and will be in the form of mark and space signals. A converter 21 will change the signal levels on line 20 to voltages appropriate to a date processing unit and will supply such voltages to its output line 22 where a mark will be represented by a significant voltage level. An inverter 23 is responsive to the voltage levels on line 22 and has an output on line 24 where a significant voltage level represents a space signal.

The line adapter will be controlled by a pair of oscillators, not shown, with the output of the fast oscillator received on line 25, FIG. 2, and the output of the slow oscillator being received on a line 26. The oscillator frequencies will be set at some multiple, seven in the described embodiment, of the pulse repetition rate of the signals to be received or transmitted. Each line 25, 26 is an input to an AND circuit 27, 28 respectively whose outputs are combined in an OR circuit 29. A flip-flop 30 has its outputs as the other inputs of ANDs 27 and 28 so that depending on the setting of flip-flop 30, one or the other of the oscillator inputs on lines 25 and 26 will be gated through the OR 29 to the oscillator line 31. The flip-flop 30 may be set to gate the fast oscillator output on line 25 by a pulse on a set fast oscillator line 34 or by the initiate receive pulse on line 15, the two inputs being combined in OR 35 on the set input of flip-flop 30. The flip-flop 30 may be set to pass the slow oscillator signal on line 26 by a pulse on the set slow oscillator line 36 or by a pulse on a line 37 from an AND circuit 38 to be described at a later point. The two pulse inputs are combined in OR circuit 39 on the reset input of flip-flop 30. The flip-flop 30 will initially be set to gate the Fast Oscillator pulses on line 25 by the initiate receive pulse on line 15. The set pulses on lines 34 and 36 are supplied by the connected TCU, usually during transmit operations, at which time the TCU knows the receiving speed of the terminal with which it will be communicating.

When set to receive, the line adapter will be set into operation by receipt of a space signal on line 20, FIG. 1. The antecedent mark signal on line 22 is one input of an AND circuit 41 which has a strobe count 0 signal on line 42 and an inverted oscillator signal on line 43 as its other inputs. The inverted oscillator signal is derived from the oscillator signal on line 31 by an inverter 44 connected between the two lines. The output pulses of AND 41 reset the stop flip-flop 41 and will set a start flip-flop 45 so long as the signal input remains a mark. As soon as the input signal on line 20 changes to a space level, the significant voltage on space line 24, the inverted oscillator signal on line 43, the Receive output on line 18 of flip-flop 14 and the output on line 46 of start flip-flop 45 are combined in AND circuit 47 on the set input of a force five flip-flop 48 to set flip-flop 48. The set output of flip-flop 48 on line 50 together with the Oscillator signal on line 31 pass through an AND 51 to put a force five signal on line 52 and force a strobe counter 53 to a count of five. The strobe counter 53 comprises three binary flip-flops 54, 55 and 56, each having an upper set input and a lower reset input together with a central input lead shown as double to indicate that a pulse on the lead will change the flip-flop to its opposite state. Each flip-flop has an upper set output which is at a significant voltage when the flip-flop is set to represent a one and a lower reset output terminal which is at a significant voltage when the flip-flop is reset to represent a zero.

The three flip-flops 54, 55, and 56 are connected to form a binary counter with the reset output on line 57 of flip-flop 54 connected to the central input of flip-flop 55 and the reset output line 59 of flip-flop 55 connected to the central input of flip-flop 56. The counter is advanced by Oscillator pulses on line 31 which pulses are gated through an AND circuit 61 by a circuit to be later described, and over line 62 to the central input of flip-flop 54. The strobe counter 53 can be forced to an initial setting of 101 representing a five by a pulse on the force five line 52 which connects to the set input of flip-flop 56, to OR 63 on the reset input of flip-flop 55 and to OR 64 on the set input of flip-flop 54. The counter 53 can also be forced to a setting of 001 representing a one by a pulse on a force one line 65 which connects to the OR 64, the OR 63 and to the reset input of flip-flop 56. On the outputs of flip-flops 54, 55, and 56, an AND circuit 68 has as inputs the three reset outputs of the flip-flops of the counter 53 and will give a significant voltage output on line 42 when the counter is at 000 representing a zero. A second AND circuit 69 receives the set outputs of flip-flops 54 and 56 and the reset output of flip-flop 55 to give a significant voltage output on line 75 when the counter reads 101 representing a five and a third AND circuit 70 receives the set inputs of all flip-flops and gives an output on line 78 when the counter is at 111 representing seven. The Count 0 output of AND 68 on line 42 is returned to an OR circuit 72 which also receives the force one signal on line 65 and the force five signal on line 52. The output of OR 72 is inverted in an inverter 73 whose output is a second input of AND 61. This signal will block incrementing of counter 53 whenever the counter is at a count of zero and whenever the counter is being forced to either a one or a five reading.

When the force five signal on line 52 sets strobe counter 53 to a reading of five, the output line 75 of AND 70 becomes high and will gate a pulse from the inverse oscillator line 43 through AND 76 to the reset input of the force five flip-flop 48 to terminate the force five signal. The force five signal on line 52 is also passed into the reset input of start flip-flop 45 to terminate the start signal as soon as the first start bit is detected at input terminal 20. Another setting of the start flip-flop 45 is prevented for the remainder of the data character time by the lowering of the count zero signal on line 42 which is an input to AND 41 which cannot then pass an oscillator signal to the flip-flop 41.

After strobe counter 53 has been set to five, the oscillator pulses on line 31 pass through AND 61 to advance the counter to six and then to seven. When the count of seven is decoded by AND 70, the count seven line 78 has a significant voltage and will gate a pulse on inverse oscillator line 43 through AND 79 on the set input of strobe flip-flop 80 to put a voltage on its strobe output line 81. This strobe signal together with the receive signal on line 18 will pass an oscillate pulse on line 31 through AND circuit 82 and to sample line 83. The sample pulse on line 83 will be gated by the not stop signal on the reset output line 84 of stop flip-flop 11 through an AND 85 to the force 1 line 65 to set the strobe counter 53 to a reading of one. A pulse on this line 65 notifies the TCU that a line bit has been sampled and corresponds to a request for bit service similar to a pulse on the set bit service line of FIG. 91 of the patent above. As soon as the strobe counter 53 has been set to a one, the voltage on count seven output 78 drops and after passing through an inverter 90, the resulting positive voltage is applied to AND circuit 91 on the reset input of strobe flip-flop 80 and will gate the next inverse oscillator pulse on line 43 to reset the strobe flip-flop 80. After strobe counter 53 has been forced to one, the counter is incremented by the oscillator pulses through AND 61 until it again reaches seven and causes another data sample to be taken. The data sample is taken by a flip-flop 95 which is set to a mark condition by the gating of a mark voltage on line 22 through AND 96 on the set input of flip-flop 95 under control of the sample pulse from AND 82 or is alternatively reset to indicate a space condition when the space voltage on line 24 is high to gate the sample pulse from AND 82 through AND 97 on the reset input of flip-flop 95. The upper output 98 of flip-flop 95 represents received data and is transmitted to the TCU for further processing.

If a terminal connected to data line 20 can have any one of a plurality of different transmission rates, the line adapter of this invention can automatically adjust itself to receive data at the transmitting speed if restrictions are placed on the initial characters transmitted at the slower speeds. The general restriction is that no slower speed character in the initial transmissions may have a bit at the mark level when it is time for the stop bit of a high speed transmission to be received. It is evident that this requirement can be satisfied if all characters transmitted for adjusting the line adapter speed consist of only space levels prior to the stop bit which is at the mark level. The restriction can be relaxed somewhat by allowing the early part of the transmitted characters to have any configuration so long as the characters do not have mark levels overlapping the stop bit of a faster transmission speed. A second restriction where more than two transmission rates are used is that none of the initializing character may have a transition from a mark to a space after the time for sampling the stop bit of the character of highest transmission rate. This will enable the next mark to space transition to identify the next character start. As a specific example, FIG. 3 indicates the characters transmitted by two commercial terminals, i.e., an IBM 1050 and a model 33/35 Teletypewriter. The 1050 terminal operates at 134.5 baud and transmits the PTTC/BCD code of seven bits, identified as B A 8 4 2 1 C between the start and stop bits where as the teletypewriter terminal will use an 8 bit data interchange code of eight bits, 1 2 3 4 5 6 7 8 between the start and stop signals. At a 134.5 baud rate, a bit time for the IBM 1050 terminal is about 7.4 ms per bit or a total of 63.2 ms from the transition to a space level until the sampling of the stop bit mark level. A TTY 33/35 character could, with about a 35 percent bit time allowance for line distortion as indicated by the lined part of the timing diagram, be in either the sixth or seventh bit at this time and therefor the initial characters of the TTY 33/35 must be at a space level for these bits. This will normally be the situation where the first group of signals sent by a TTY 33/35 is its terminal identification which starts with a carriage return code, i.e., start 10110001 stop. This code is at the required space level for the sixth and seventh bits. Other systems may require special characters for the start of transmission.

The switching of the line adapter to a slower speed is controlled by an initialize flip-flop 100, FIG. 2. This flip-flop 100 will be set by the initiate receive pulse on line 15. When the set stop signal is received on line 12 to indicate that the next sampled signal will be the stop bit if the character is transmitted at the highest transmission rate, the status of the data line 20 is tested. If the line 20 is at the mark level and the stop flip-flop 11 has been set, a sample pulse on line 83 will pass through AND 101 and OR 102 on the reset input of flip-flop 100 to reset the flip-flop. Since this mark level is the correct stop bit for the higher oscillator rate which was assumed as being transmitted, no other change is needed and the higher speed signal is continued on line 31.

If, however, the data line 20 is at a space level at this time, it indicates that a slower speed character is being received and that the oscillator signal on line 51 should be changed to a slower speed. This is performed by AND 38 which receives the initialize signal on output line 103 from the flip-flop 100, the stop signal on line 13, the space level signal on line 24 and the sample signal on line 83 to put a signal on line 37 to OR 39 to reset flip-flop 30. This will block AND 27 to stop the faster oscillator signal on line 25 and condition AND 28 to pass the slower oscillator signal on line 26. The switching of flip-flop 30 to the slower speed oscillator, will condition AND 104 to pass an inverted oscillator signal on line 43 to OR 102 to reset the initialize flip-flop 100.

A stop error detector flip-flop 106 is provided to put a signal on its output line 107 if at any time after the rate of transmission is determined, a character is not at the mark level when the stop flip-flop 11 is set. Flip-flop 106 is reset when the line adapter is set to receive by the initiate receive signal on line 15 or by a special reset stop error signal from the attached TCU on a line 108, both signals being fed into an OR 109 on the reset input of flip-flop 106. If a stop error is present at a later time, the stop flip-flop 11 will have been set to put a signal on line 13, the initialize flip-flop 100 will have been reset to put a signal on its reset output line 110 and if the data line 24 is at a space level when the sample signal appears on line 83 the stop error flip-flop 106 will be set by the sample signal through AND 111 to indicate to the attached TCU that an incorrect character format has been received, see FIG. 56 of the above Richard et al. patent.

Two further embodiments are shown diagrammatically in FIGS. 4 and 5 to enable reception by the line adapter of messages of more than two different transmission rates. The embodiment of FIG. 4 shifts to the next lower oscillator speed each time a space level is detected at the time the transmission would be at a mark level if the connected terminal were transmitting at the speed for the oscillator which is then connected. As shown in FIG. 4, a type of shift register is utilized for connecting one of a plurality of oscillators to the line adapter oscillator line 13. Each oscillator output is received on a line 125A, 125B--125N and is gated through an AND 127A, 127B--127N to OR 129 whose output is line 13. Each AND gate 127 is gated to pass its oscillator signal when a corresponding flip-flop 130A, 130B--130N is set. The initiate receive signal on line 15 is used to control the flip-flop 130A by being passed through OR 135A on its set input to flip-flop 130A to gate the highest oscillator signal and to reset all other flip-flop 130B--130N by being passed through the OR's 139B--139N on their reset inputs. The same signal will also set the initiate flip-flop 100. Each flip-flop 130 can be set to gate its associated oscillator output on line 125 through AND 127 to line 13 by a signal applied on a line 134 to the OR 135 on its set input and can be reset to block such AND gate 127 by a signal on a line 136 to the OR 139 and its reset input. The signals on lines 134 and 136 will normally be controlled by the associated TCU for selecting a proper oscillator for transmission purposes, it being assumed that the TCU will be aware of the data speed of the terminal to which a message is being sent.

The flip-flops 130 are connected as a shift register by a connection from the set output of each flip-flop 130 to the OR 139 on the next earlier flip-flop of the register and to an AND 140 whose output goes to the OR 135 on the set input of the next later flip-flop. The AND's 140 also receive inputs from lines 83, 24, 13, and 103 so that each time the TCU sets the stop flip-flop 11 and the data line 24 is at a space level when sampled by the signal on line 83, the register will shift to set the next flip-flop 130 for the next slower transmission speed. It will be understood that the shift register will also include such other connections between the flip-flops 130 as are conventionally provided to prevent race conditions. The AND circuit 204 has its output fed back into the OR 102 on the reset input of flip-flop 100 to reset the initialize flip-flop when the flip-flop 130N is set for reception of the slowest speed of transmission. For any other speed, the initialize flip-flop 100 will be reset by the sampling of a stop bit when the flip-flops 130 are set to receive data characters at the transmission speed of the connected terminal.

Another embodiment is shown in FIG. 5 to make a selection of the proper receiving speed on the first transmitted character. In this embodiment, a counter is driven by the highest speed oscillator and has its outputs decoded to successively test the data lines to detect the first mark level at a possible stop time. In this FIG. as in FIG. 4, each oscillator output for a possible transmission speed is received on a line 125A--125N and is passed through a gate 127A--127N to an OR 129 and to oscillator line 31. Each gate 127 is controlled by a flip-flop 130A--130N with only one flip-flop 130 being set at any time to gate only one oscillator output to line 31. Each flip-flop 130 has an OR 135 circuit on its set input and an OR circuit 139 on its reset input with an input 134 136 respectively, going to the connected processor so that the line adapter can be set to any transmission speed under central processor control. Normally, the flip-flops 130 will be initially conditioned so that flip-flop 130A is set and the remaining flip-flops 130B--130N are reset so that the highest frequency oscillator output on line 125A is gated to line 31. This initial setting is done by the initiate receive pulse on line 15 which is passed through OR 135A and OR's 139B--139N.

To select the correct oscillator output for the signals being received, a counter 150 is provided to count the oscillator signals on line 31 for a period equal to at least the length of the slowest character to be received. A connection from line 15 to counter 150 is provided to set the counter to a reading of zero whenever the initiate receive line 15 is pulsed to set the line adapter to a starting condition. The counter is incremented by oscillator signals on line 31 passing through AND 151 which receives the signal on line 103 from initiate flip-flop 100, the not-stop signal on line 84 from flip-flop 11 and the output from an OR circuit 152. OR 152 receives the Force 5 signal on line 52 from flip-flop 48 and a not-zero signal on a line 153 from a decoder 154 on the outputs of counter 151. Normally both inputs to OR 151 are low but when a space signal is received on line 24, the line 52 becomes high to pass the first oscillator pulse into counter 150 after which line 153 becomes high to maintain AND 151 gated to continue counting.

Decoder 154 has a number of outputs 155, one for the stop bit in each possible received character and puts a signal on the associated output at the time a possible stop bit can be received. If the character being received is at the highest transmission rate, output line 155A is up when the stop bit for this character is received and the mark level on line 22 together with the signal on line 155A will pass through AND 101 and OR 102 to reset initialize flip-flop 100 and drop the signal on line 103 to stop the counter 150. If the line 22 is at a space level, the counter continues to count until output 155B receives a signal. At this time AND 156B will be gated by a mark level on line 22 and the initialize signal on line 103 to set flip-flop 103B and gate out the second fastest oscillator signal on line 125B to line 31 if a mark level was detected. Setting of flip-flop 130B will put its output signal through OR 139A to reset flip-flop 130A and will send a signal through OR 157 to reset flip-flop 100. If the mark level is not detected at this time, the other output lines 155 receive signals in turn to set their associated flip-flop 130 when a mark level is detected. Each flip-flop 130 when set will reset flip-flop 130A through OR 139A and will reset flip-flop 100 through OR 157 and will also notify the central processor what data receiving speed has been selected. The processor will then be enabled to set the stop flip-flop 11 at the appropriate times. If an erroneous condition has occurred on the transmission lines and the counter 150 counts to a reading higher than any possible interval for any connected terminal, an error line 157 will receive a signal to notify the processor that an error has occurred and the line adapter needs to be reset.

It will be thus apparent that the line adapters disclosed will automatically select the correct speed for reception from terminals of either of two different speed terminals or for systems having terminals of more than two different speeds connectable to a line adapter.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. In a line adapter for communication systems of the start-stop type wherein a character is represented by a signal having a plurality of selectively coded bits preceded by a start bit and followed by a stop bit and wherein terminals transmitting character signals at different speeds may be selectively connected to a line adapter, the combination of: a plurality of oscillators, one for each of said different speeds; gating means to pass the output of each of said oscillators to a common line adapter control lead; signal decoding means initiated by reception of said start bit and controlled by the oscillator signals on said control lead; initializing means to set said gating means to pass a predetermined one of said oscillator outputs to said control lead; character control devices to indicate when a stop bit should be present in a received character transmitted at the transmission rate of said predetermined oscillator output; and a gating means control circuit activated by said character control devices to prevent alteration of said gating means if said received character signal is at a stop bit level or to alter said gating means to pass the output of a different oscillator to said control lead if said character

2. A line adapter as recited in claim 1 wherein: said gating means comprises a plural state circuit; said gating means control circuit comprises a bistable device initially set to one stable state; a circuit gated by said bistable device when in said one state to change the state of said plural state circuit if the received character signal does not have a stop bit when sampled by said character control devices; and another circuit to set said bistable device to its other state if the

3. In a line adapter for communications of the start-stop type in which a character is represented as a predetermined number of selectively variable bits preceded by a start bit and followed by a stop bit and wherein any one of a plurality of terminals transmitting at different rates may be connected to a line adapter, the combination of: a plurality of adapter timing circuits, one for each of said different rates; gating means to pass the timing signals on one of said timing circuits to a common timing lead; an adapter initiating means to set said gating means to pass a predetermined one of said timing signals to said timing lead; a transmission rate detecting device set by said initiating means and activated by reception of a start bit of a character to enable selection of one of said timing signals for control of said line adapter by indicating the time for reception of the stop bit of a character transmitted at the rate corresponding to said predetermined one of said timing signals; means under control of said initiating means and said rate detecting device to test for the occurrence of a stop bit; and gating control means activated when said controlled means does not detect a stop bit to set said gating means to pass the timing signals corresponding to the transmission rate of the character representations being received.