Program Controlled Data Processing System

Abstract

A program controlled telephone switching system is shown as an example of a real time program controlled data processing system. The system work functions of the telephone switching system are performed at assigned levels of a priority hierarchy. This hierarchy includes a base level at which routine jobs are performed, timed interrupt levels at which input-output jobs, which require a fair degree of timing precision, are performed and a plurality of trouble interrupt levels (maintenance interrupt levels), which are employed to initiate remedial actions in accordance with a prescribed remedial plan. The telephone functions which are performed at the base level are allocated processor time in accordance with a base level executive program frequency table. The base level executive program provides time for execution of certain low priority maintenance functions. In the absence of trouble the processor time is shared by the timed interrupt level programs and the base level programs. The trouble interrupt programs are initiated upon the detection of corresponding classes of trouble.

Parent Case Text

CROSS-REFERENCES TO RELATED APPLICATIONS

This is a division of copending application Ser. No. 334,875, filed Dec. 31, 1963 and relates to a program controlled data processing system.

Description

BACKGROUND OF THE INVENTION

There are many applications for data handling systems which require a careful allocation of data processing time. The extremely high cost of operating data handling systems imposes a requirement that such systems be used to their fullest capacity. Additionally, the nature of the jobs assigned to data handling system may impose even stricter requirements on the utilization of machine time. Data handling systems which must serve a number of input and output devices on a near real time basis and which must be continuously operable because of the nature of job assigned the system exhibit the strictest requirements for careful allocation of machine time. There are many types of data handling systems to which the principles of this invention apply; however, for purposes of illustration, these principles are described with respect to a particular type of data handling system, namely, an electronic program controlled telephone switching system.

By way of illustration a telephone switching system serves a large number of lines and trunks which must be served without unreasonable delays. Every line and trunk comprises a separate input to the data processor and the rendering of service to a line or trunk may be considered to be an individual problem comparable to the problems fed to the data processor of other data handling systems, for example, a computing center. Obviously, in a large telephone switching system having but a single data processor work functions with respect to many calls must be interleaved in time since inordinate delays would occur if each demand from a line or trunk were completely served before moving to other demands.

A telephone switching system is an extreme example of a data handling system which must be continuously operable; however, there are many other data handling systems such as those controlling a production line or critical scientific operations which must similarly be continuously operable. In such systems constant surveillance of system operation must be maintained and whenever a possible trouble is detected remedial maintenance actions must be undertaken. Accordingly, surveillance of the system operation and any resulting remedial maintenance actions are work functions which must be interleaved with the other tasks of the system, in the illustrative example, serving the demands of the lines and trunks of the system.

It is an object of this invention to efficiently allocate the processor time of a program controlled data processing system to meet the demands of continuous real time operation.

SUMMARY OF THE INVENTION

In accordance with this invention the programs for a program controlled telephone switching system comprise: base level program sequences, timed interrupt program sequences and maintenance interrupt program sequences. The processor for the system comprises: interrupt timing arrangements which are responsive to output signals of processor clock circuits and which are arranged to generate timed interrupt signals for timed interrupt sources which, when set, serve to momentarily halt the execution of base level program sequences and initiate execution of the timed interrupt program sequences. The processor further comprises: a plurality of operational checking circuits which generate discrete trouble signals upon detection of faulty system operation and a plurality of maintenance interrupt sources which are responsive to such trouble signals for momentarily halting the execution of both timed interrupt program sequences and base level program sequences and for initiating execution of the maintenance interrupt program sequences.

In accordance with one feature of this invention, the gathering of information from the lines and trunks to detect requests for service call signaling information, hangups, requests for additional service and the transmission of information via trunks, such as the transmission of dial pulses or multifrequency tones, is performed at timed interrupt processor intervals. Advantageously, the necessary timing precision required for these functions is achieved.

In accordance with another feature of this invention, the further processing of information which is gathered from the lines and trunks at timed interrupt time periods is performed at base level processor time intervals. Advantageously, therefore, this subsequent processing does not interfere with the work functions which must be performed with a fair degree of timing precision.

In accordance with another feature of this invention, the maintenance interrupt sources comprise: a plurality of interrupt sources, each source being assigned a relative interrupt priority in an ordered priority plan. The maintenance interrupt program sequences comprise a plurality of different interrupt program sequences discretely assigned to corresponding interrupt sources and the control arrangement is responsive to output signals of the interrupt sources to initiate execution of the interrupt program sequences assigned to the active interrupt source having the highest relative priority.

There is a distinct possibility that several types of trouble will be simultaneously indicated. It is important to limit the amount of processor time in performing remedial actions and the remedial actions must follow an orderly pattern. Advantageously, the assignment of relative priorities insures completion of the remedial actions.

In accordance with another feature of this invention, the data in the memory includes an ordered list of classes of work to be performed, the ordered list defining a base level executive program and comprising a plurality of sublevel entries. Identical sublevel entries are included in the ordered list for each time a class of work of that sublevel is to be performed in the execution of the base level executive program and the base level program sequences in the memory include sequences for performing work functions in accordance with the base level executive program.

Although the work functions which are completed at the base level need not be completed within a rigid framework of time, there is, however, the need to efficiently allocate base level time. Advantageously, the base level executive program, as implemented by the ordered list of classes of work to be performed, serves to efficiently allocate base level time.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a general block diagram of a telephone switching system as an illustrative data processing system;

FIG. 2 is a general block diagram of a program store which is a portion of the processor of FIG. 1;

FIG. 3 is a general block diagram of a call store which is a portion of the processor of FIG. 1;

FIG. 4 is a general block diagram of the central control of FIG. 1;

FIGS. 5 and 6 are flow charts;

FIGS. 7 through 9, arranged as shown in FIG. 72, illustrate the operation of the processor of FIG. 1;

FIGS. 10 through 63, arranged as shown in FIG. 71, are a detailed diagram of the central control of FIG. 1 and FIG. 4;

FIG. 64 is a time diagram showing the fundamental pulses employed in the central control;

FIG. 65 is a time diagram which illustrates the processing of three successive program order words;

FIG. 66 illustrates the interrupt hierarchy of the illustrative data processor;

FIGS. 67 through 72 are flow charts of control functions; and

FIGS. 73 and 74 are key sheets showing the arrangement of portions of the illustrative embodiment as enumerated earlier herein.

GENERAL DESCRIPTION

FIG. 1 shows the organization of a telephone system which is employed herein as an illustrative data processing system. The Central Processor 100 comprises a Central Control 20 101, the Program Store 102, and the Call Store 103. The work functions of the telephone system are accomplished by the various units of the input-output system, under control of the Central Processor 100.

The input-output system in the case of the illustrative telephone switching system comprises the Central Pulse Distributor 143, the Master Scanner 144, the TELETYPE 145, the program store writer 146, the AMA 147, the various elements of the Switching Network 120, the Junctor Frame 126, including the Junctor Scanner 127, the Signal Distributor 128 and the Cable Receiver 129, and the Trunk Frames 134 and 137, including the associated Trunk Scanner 135 and 139, the Trunk Signal Distributors 136 and 140, and the Cable Receivers 137 and 141. These elements of FIG. 1 correspond to the Input-output System 270 of the generalized block diagram of FIG. 2.

In accordance with the invention, the system work functions are assigned to various levels of a priority hierarchy. FIG. 66 shows the priority or interrupt hierarchy for the system work functions of the illustrative data processor. This hierarchy includes a base level at which routine jobs are performed, timed interrupt levels at which input-output jobs, which require a fair degree of timing precision, are performed and a plurality of system trouble interrupt levels (maintenance interrupt levels), which are employed to initiate remedial actions in accordance with a prescribed remedial plan. The base level jobs are allocated processor time in accordance with the base level executive program frequency table which is described in the application. The base level executive program includes sublevel L.sub.e, which provides time for execution of certain maintenance functions. In the absence of trouble, the trouble interrupt levels G through A remain inactive and processor time is shared by the timed interrupt level programs and the base level programs. The trouble interrupts are initiated upon the detection of corresponding classes of trouble. By organizing the troubles into this interrupt hierarchy, the system work functions, both normal call processing and maintenance, can be accomplished within the real time demands of the system.

FIG. 4 is a general block diagram of the central control of the illustrative data processor. The block diagram schematically shows the system elements which are employed in the implementation of this interrupt system. The operational check circuits of FIG. 4 comprise the Error Detection and Correction Circuit 2400, the Call Store Error Detection Circuit 2200 and the Matching Circuits 3121 and 3622. These are merely illustrative examples of trouble sources which may be organized into the interrupt hierarchy of FIG. 66. In this illustrative example, the remedial circuits of FIG. 4 comprise the Error Correction Circuit of 2400, the Call Store Reread Sequencer 5700 and the Program Store Reread Sequencer 5301.

In the absence of an interrupt request, the central control operates at the base level in accordance with the base level executive program. A timed interrupt is initiated by setting the H or J Interrupt Source 5604, 5605. Upon the occurrence of a timed interrupt, the program instruction presently being executed is allowed to go to completion and then a transfer is made to the appropriate timed interrupt program sequence.

In the case of the detection of trouble, one of the Maintenance Interrupt Sources 5209, 5210, 5211 is set to request initiation of the corresponding interrupt level program sequences. The Interrupt Level Activity Register 6302, 6307 serves to assure that the interrupt program sequences are executed within the framework of the interrupt hierarchy. That is, this register assures that an interrupt level program is not interrupted by an interrupt level program of lower priority in the hierarchy and similarly assures that a high level interrupt program sequence does in fact interrupt a lower level interrupt program sequence. In each instance, the Interrupt Sequencer 4901 is the mechanism for initiating the interrupt program sequences.

The Interrupt Inhibit Control Register 6002, 6003 is employed to inhibit selectively the initiation of the interrupt program sequences during certain procedures.

CENTRAL PROCESSOR (100)

The Central Processor 100 is a centralized data processing facility which comprises three basic elements:

1. Central Control 101;

2. Program Store 102;

3. Call Store 103.

Functionally, the Central Control 101 may be divided into three parts:

1. Basic data processing facilities;

2. Facilities for communicating with input and output equipment; and

3. Maintenance facilities.

As far as possible common circuits within the Central Control 101 are employed to accomplish all of these functions.

The Program Store 102, in the illustrative embodiment, is a permanent magnet-magnetic wire memory (Twistor) and therefore affords nondestructive readout of the information stored therein. The Program Store 102, being semipermanent in nature, is employed to store the less volatile system information including the system programs. Information is written into the Program Store 102 by means of the Program Store Card Writer 146.

The Call Store 103, in the illustrative embodiment, is a ferrite sheet memory; therefore, information may be written into or read from the Call Store 103. Since information in the Call Store 103 is readily changed at the normal system speed, the more volatile system information is stored therein.

CENTRAL CONTROL (101)

The Central Control System 101 comprises two independent central controls for purposes of system reliability. The independent central controls are both arranged to perform all of the necessary system actions. In the usual mode of operation both independent central controls carry on the same work functions on the basis of duplicate input information. This is termed the in-step mode of operation. However, only one of the two central controls can alter the system status or control the execution of telephone functions at any given instant. That is, the two independent central controls provide control and maintenance information to the remainder of the system on a mutually exclusive basis. The manner in which the decision is reached as to which of the two central controls is in control of the system at any given instant is described later herein.

In the illustrative embodiment the Central Control 101 executes one order, other than a transfer, a program store data word reading or a variety of work operations which require the use of the special purpose sequence circuits, which are described later herein, per basic 5.5 microsecond instruction cycle, which is the time cycle of the Program Store 102 and of the Call Store 103. A microsecond clock in the Central Control 101 provides one-half microsecond pulses at one-quarter microsecond intervals which pulses permit the Central Control 101 to perform a series of sequential actions within one basic 5.5 microsecond instruction cycle.

The design of the Central Control 101 is predicated upon the demands of real time, the internal functions it must perform and the basic instructions necessary to accomplish these ends.

Communications between major divisions of this system are by way of bus systems and by way of multiple conductor cables which provide discrete communication paths between selected divisions of the system. The buses and cables are detailed later herein.

Communication within a major division of this system, such as a Central Control 101, may be by way of bus systems; however, such internal bus systems comprise a plurality of single rail parallel paths and are not intended to be covered by the following discussion.

A bus system, as defined herein, comprises a plurality of pairs of conductors which may, in many respects, be compared to a tapped delay line. The time delay of a bus system is not necessarily an advantageous aspect of the bus system but, rather, is an inherent characteristic thereof. A bus is a transmission means for transferring information from one or more sources to a plurality of destinations. A bus is transformer coupled to both the information source or sources and to the destination loads. The information sources are connected to the bus conductors in parallel and the loads are coupled to transformers which are serially connected in the bus conductors. Dual winding load transformers are employed and the two windings of the pair of windings are connected in series with the individual conductors of a pair of conductors of a bus. The load is lightly coupled to the bus as are the taps of a delay line and the bus is terminated in its characteristic impedance also in a manner well-known in the manufacture of delay lines.

A bus system is connected to a number of equipments which may be physically separated by distances which are large compared to the distances between taps of a normal delay lines line. Data transmitted over a bus is in pulsed form and in this particular embodiment extremely short pulses in the order of one-half microsecond are transmitted. Information on a bus system is transmitted in parallel, that is, a data word or a command is transmitted in parallel over the plurality of pairs of conductors of the bus and it is important that such parallel data elements arrive at a given load equipment at a common time. Accordingly, the pairs of conductors of a bus system are arranged to follow similar physical paths and their lengths are kept substantially identical.

There are a number of bus systems and these are described with respect to the major divisions of the system along with the general description of those divisions. Although the buses of this illustrative embodiment are shown in the drawing to be a single continuous path from a source to one or more destinations, there are, in fact, many special techniques employed to minimize propagation time from an information source to a destination point and to equalize propagation times between an information source and similar destinations. Such techniques are not discussed herein as they are not essential to an understanding of this invention; however, in a large office the routing of buses and the special techniques which are designed to achieve the above-noted desirable result are relatively important to an optimum system.

A bus system generally comprises two duplicate buses which in the drawing are labeled bus O and bus 1. In that there are a number of bus systems as will be set forth later herein, there are a number of buses labeled bus 0 and bus 1; however, each bus system is identified in the drawing.

In addition to the bus systems there are a plurality of multiple conductor cables which provide discrete communication paths between selected divisions of the switching system. The conductor pairs of these cables are in many instances transformer coupled both to the information source and the destination load; however, there are also a number of cables wherein DC connections are made to both the source and the destination load.

While a bus is a unidirectional transmission means, there are specific instances wherein a cable pair comprises a bidirectional transmission means.

The multiple conductor cables generally provide unduplicated paths between the selected divisions of the system while, as previously noted, the buses of a bus system generally provide duplicated paths between selected divisions of the system.

SWITCHING NETWORK (120)

The Switching Network 120 serves to selectively interconnect through metallic paths lines to lines via junctor circuits, lines to trunks, trunks to trunks, lines and trunks to tones, signal transmitters, signal receivers, am maintenance circuits, and, in the case of lines, to provide connections to coin supervisory circuits, et cetera. Two-wire paths between the above enumerated equipments are provided through the network of this one specific illustrative embodiment.

The Switching Network 120 only provides communication paths, means for establishing such paths and means for supervising such paths. The Central Processor 100 maintains a record of the busy and idle states of all network links and a record of the makeup of every established or reserved path through the network. These records are maintained in the Call Store 103 of the Central Processor 100. The record relating to the busy-idle states of the network elements is generally referred to as the Network Memory Map. The Central Processor 100 interprets requests for connection between specific pieces of equipment and determines a free path through the network by examining the connection requirements and the above-noted busy-idle states of the possible paths.

The network is divided into two major portions, namely, line link networks which terminate lines and junctors (both wire junctors and junctor circuits) and the trunk link networks which terminate trunks and wire junctors, service circuits such as tone circuits, signal receivers, signal transmitters, et cetera. A line link network comprises four switching stages, the first two stages of which are concentrating stages, while a trunk link network comprises four stages generally without concentration. In this one specific illustrative embodiment there is a single path provided between a line and each of a plurality of line link network junctor terminals. There are four paths through a trunk link network between a trunk terminal and each of a plurality of trunk link network junctor terminals.

Certain junctor terminals of each line link network are connected directly through wire junctors (a pair of wires without other circuit elements) to certain junctor terminals of the trunk link networks; others of the line link network junctor terminals are interconnected either by way of junctor circuits (which provide talking battery and call supervision facilities) or, in very large offices, by way of junctor circuits and additional stages of switching.

Junctor terminals of a trunk link network which are not connected to junctor terminals of a line link network are directly interconnected by wire junctors or, in extremely large offices, by way of wire junctors and additional switching stages.

Control of the network and the control and supervision of the elements connected to the network are distributed through a number of control and supervisory circuits. This disbursement provides an efficient and convenient buffer between the extremely high speed Central Processor 100 and the slower network elements. The principal control and supervisory elements are:

1. The network control circuits which accept commands from the Central Processor 100 and, in response to such commands, selectively establish portions of a selected path through the network or, in response to such commands, execute particular test or maintenance functions.

2. The network scanners which comprise a ferrod scanning matrix to which system elements such as lines, trunks and junctor circuits are connected for purposes of observing the supervisory states of the connected elements; the network scanners, in response to commands from the Central Processor 100, transmit to the Central Processor 100 indications of the supervisory states of a selected group of circuit elements.

3. The network signal distributors which, in response to commands from the Central Processor 100, provide an operate or a release signal on a selected signal distributor output terminal which is termed herein a signal distributor point. A signal of a first polarity is an operate signal and a signal of the opposite polarity is a release signal. Signal distributor output signals are employed to operate or release control relays in junctor circuits, trunk circuits, and service circuits. A magnetically latched wire spring relay is used generally throughout the junctor circuits and trunk circuits for purposes of completing the transmission paths through these elements and for circuit control in general. The magnetically latched relay operates in response to an operate signal (-48v.) from a signal distributor and releases in response to a release signal (+24v.) from a signal distributor. The network signal distributors are relatively slow operating devices in that they comprise pluralities of relays. Signal distributor output signals are pulsed signals and a single signal distributor can be addressed to only one of its output points at any given instant.

Of the three above-noted network control and supervisory elements (there are pluralities of each of these) the network controllers and the signal distributors are relatively slow operating devices and to assure completion of a task, each of these devices is addressed at the maximum repetition rate of once every 25 milliseconds. This period of time is sufficient to assure completion of the work function associated with a network controller or signal distributor command. Therefore, there is no need for the Central Processor 100 to monitor these devices to assure completion of their assigned tasks before transmitting a subsequent command to the same controller. However, to assure continued trouble free operation scan points which reflect the successful completion of a preceding order are examined before sending a new command to the controller. The network scanners, however, are relatively fast operating devices and these may be addressed at a maximum rate of once every 11 microseconds.

SUBSCRIBER CIRCUITS

The subscriber sets such as 160, 161 are standard sets such as are employed with present day telephone switching systems. That is, these are sets which connect to the central office via a two-wire line, respond to normal 20 cycle ringing signals and may be arranged to transmit either dial pulses or TOUCH-TONES or may be arranged for manual origination. Subscriber stations comprising one or more subscriber sets such as 160, 161 all terminate at line terminals of a line link network. A subscriber line may have either TOUCH-TONE sets or dial pulse sets or combinations of TOUCH-TONE and dial pulse sets. Information concerning the type of call signaling apparatus associated with a subscriber's line is included in the class of service mark which is maintained normally in the Program Store 102; however, after a recent change this information is found in whole or part in the Call Store 103.

Supervision of a subscriber's line is by way of the line scanners which are located in the vicinity of a line link network. Such scanners, however, are generally employed only to detect requests for service. After a request for service has been served and a subscriber's line has been connected through the network to a trunk or to a service circuit such as a subscriber's dial pulse receiver, subscriber's TOUCH-TONE receiver, a tone source, et cetera, or to another subscriber via a junctor circuit, the scanning element associated with a subscriber's line is disconnected and subsequent supervision for answer and disconnect is transferred either to the trunk, the service circuit, or the junctor circuit. The subscriber's line scanning element is reconnected only after the subscriber's line has been released from the prior connection.

Service circuits such as subscriber call signaling receivers and subscriber information tone sources such as busy tone, ringing tone, ringing induction tone, recorded announcements, vacant level tone, et cetera, are terminated at trunk terminals of the trunk link network. Connections between a subscriber's station and a service circuit such as a dial pulse receiver or a TOUCH-TONE receiver and connections between a subscriber's set and a tone source include the four stages of a line link network and the four stages of a trunk link network.

Communication with a distant office or an operator is by way of two-way trunks, outgoing trunks, incoming trunks, operator trunks, et cetera, which are located in the Trunk Frames 134, 138 and which all terminate at trunk terminals of a trunk link network. In the case of a call between a subscriber's station and a trunk or service circuit, talking battery to the subscriber is provided through the trunk or service circuit and supervision for disconnect is accomplished by scanning the scanning elements of the connected trunk or service circuit.

CENTRAL PULSE DISTRIBUTOR (143)

The Central Pulse Distributor 143 is a high speed electronic translator which provides two classes of output signals in response to commands from the Central Processor 100. The two classes of output signals are termed unipolar signals and bipolar signals and are respectively associated with central pulse distributor output terminals designated CPD unipolar points and CPD bipolar points. Both classes of signals comprise pulses transmitted from the CPD output points to the using devices via individual transmission pairs which are transformer coupled both to the CPD output points and to the load devices.

Central pulse distributors for purposes of reliability are employed in pairs and corresponding bipolar output points of the two central pulse distributors of a pair are employed to address the same circuit element. Similarly, unipolar points are associated in pairs to accomplish related system functions.

The address coding associated with each central pulse distributor is sufficient to define 1,024 CPD points. Of these 1,024 points, 512 are assigned to unipolar points while the other 512 are assigned to 256 pairs of bipolar points.

The most common use of the unipolar signals is to momentarily enable a particular piece of equipment such as a Network Controller 122, a Network Scanner 123, et cetera. The enablement signals comprise relatively important information; therefore, in response to an enablement signal the enabled circuit, shortly after the receipt thereof, tram transmits a verify signal back to the Central Pulse Distributor 143 over the same pair that was used to transmit the enable signal. The verify signal is received at the Central Pulse Distributor 143 and is translated to the same form as the address portion of the command which was transmitted from the Central Control 101 to the Central Pulse Distributor 143. The translated verify signal is transmitted to the Central Control 101 where it is compared against the address which was transmitted. A match assures enablement of the correct unit of equipment. Not all unipolar output signals represent information which is as important as the enable signals; therefore, certain unipolar signals are not verified.

Both unipolar output signals and bipolar output signals comprise pulses and, as in the case of the signal distributors, only one CPD output point, either unipolar or bipolar, can be enabled at any given instant. Unipolar output signals while generally employed to provide transient gating signals to enable the receiving circuit are also used to set and reset flip-flops in particular instances. Bipolar output signals are employed to both selectively set and reset flip-flops at the receiving circuits. A bipolar signal is accompanied by a "WRMI" security signal when employed to control certain critical circuits. A signal of the first polarity serves to set a flip-flop and a signal of the other polarity serves to reset a flip-flop. The system generally has means for verifying the setting or resetting of a flip-flop in response to CPD bipolar signals; therefore, bipolar signals are not directly verified in the manner employed in the case of unipolar signals.

The Central Pulse Distributor 143 is an electronic device; therefore, its output signals are employed to control other relatively high speed circuits. For example, central pulse distributor output signals are employed to control the sending of both multifrequency signals and dial pulses from a switching center to a distant office via a trunk circuit and central pulse distributor output points are also employed to set or reset control flip-flops in a variety of system equipments. Generally these control flip-flops must be set or reset at speeds which approach a basic system instruction cycle; therefore, the slow speed signal distributor output signals are not adequate.

MASTER SCANNER (144)

The Master Scanner System 144 so comprises a ferrod matrix for terminating circuits to be supervised and means for selectively transmitting to Central Control 101 the supervisory states of a selected group of supervised circuits in response to a command from the Central Processor 100. The scanning element employed is the ferrod device. A ferrod comprises an apertured stick of ferromagnetic material having control, interrogate, and readout windings. The control windings are placed in series with electrical connections which indicate the supervisory state of the supervised circuit. For example, where a ferrod is employed to supervise a subscriber's line, the ferrod is placed in series with the line conductors and the subscriber's subset. When the subscriber's subset is in the on-hook state there is no current flowing in the ferrod control winding, while when the subscriber is in the off-hook state current does flow in the ferrod control winding. The interrogate and readout windings merely comprise individual conductors which thread through the two apertures of the ferrod, that is, both the interrogate conductor and the readout conductor are threaded through both apertures of the ferrod. An interrogate signal comprises a bipolar pulse which when applied to the interrogate conductor causes an output signal in the readout conductor of every ferrod which is supervising a circuit which is in the on-hook state. If the ferrod is supervising a circuit in the off-hook state, a readout pulse is not generated due to saturation of the ferrod.

The Master Scanner System 144 comprises one or more scanners each capable of supervising 512 circuits. The scanners of the Master Scanner 144 are not duplicated; however, there is a complete duplication of access circuitry within a scanner to provide system reliability. The Master Scanner 144 is generally like the Network Scanners (123, 127, 135, 139) which are distributed through the network frames; however, the Master Scanner 144 is employed to supervise certain circuit elements which reflect the operating state of the system and, therefore, the supervisory states of these elements are helpful in system maintenance and trouble diagnosis. For example, scan points of the Master Scanner 144 are employed to monitor the voltage levels of critical voltage supplies, and the states of control relays and logic packages such as flip-flops to assure proper operation thereof. In addition, the Master Scanner 144 is employed to monitor a few circuits which terminate on the Switching Network 120 and which for efficiency of grouping are more conveniently examined by way of the Master Scanner 144.

TELETYPE UNIT (145)

The Teletype Unit 145 provides means for communicating information from maintenance personnel to the switching system and for transmitting information from the switching system to maintenance personnel.

By means of the Teletype Unit 145 maintenance and operating personnel may request limited specific system actions. Included in the system actions is the ability to enter in the Call Store 103 recent change translation information. That is, in the course of daily routine business there are often requirements for changes in directory number to line equipment number translations. For example, when a line is disconnected for any reason, a new line is added, or changes are made in the service afforded a line, a recent change entry is required. Recent change information is held in a Call Store 103 until such time as the coding of a Program Store 102 is changed to reflect the recent change information.

In the course of routine operations the system may encounter abnormal or trouble operating conditions and information relating to such abnormal or trouble conditions is printed out on the teletype for the information of the maintenance personnel.

PROGRAM STORE CARD WRITER (146)

The Program Store Card Writer 146 provides means for coding the information cards of the Program Store 102. Information to be placed on the magnet cards is obtained either from a magnetic tape source or from the Central Processor 100. The card writer serves to magnetize the card magnets whenever a 0 is to be inserted in the memory and to demagnetize the card magnets wherever a 1 is to be inserted in the memory.

MESSAGE ACCOUNTING TAPE UNIT (147)

The automatic Message Accounting Tape Unit 147 is utilized by the system to store telephone charging information. This information is stored in a single complete entry on magnetic tape. The tapes or the information on the tapes are subsequently transmitted to a data processing accounting center where the charge information is employed in computing a subscriber's cumulative charges.

The switching system collects certain data pertaining to both message rate and toll calls and this data is assembled in a Call Store 103. After all of the information which the data processing accounting center will require to compute a subscriber's charge has been collected, the information is transferred from the Call Store 103 to the tape unit.

The tape units are employed in a pairs to assure system reliability.

GENERAL DISCUSSION

The Central Processor 100 always comprises two central controls. In the usual mode of operation both central controls are performing the same work operations. Whenever possible the central controls obtain the same input information from different sources and over different transmission facilities. That is, in that the information in both the Program Stores 102 and the Call Stores 103 is duplicated in separate stores of the respective store systems, the first central control will receive information from a first store having the desired information and via a first bus of a bus system, while the second central control will receive information from the other store having the desired information via the other bus of the bus system. Assuming that the information obtained from the two stores, either Program Store 102 or Call Store 103, is identical and that the communication paths, i.e., buses are operating properly, the two central controls will perform the same work functions. However, at any given instant only one central control can alter the connections through the network or, in general, control the operation of the system. There are a few exceptions whereby the other central control may perform off line work functions which are different from those which are performed by the central control which is in control the of the system functions.

In the normal in-step mode of operation set forth above the two central controls theoretically are operating upon identical input information; therefore, their operation should be identical. Correspondence of action of the two central controls is carefully checked by routinely comparing the flow of data through each central control. In the event that a mismatch is found between the data as it flows through the two central controls, the system is altered.

In addition to matching the flow of data through the two central controls each central control performs a plurality of checks on the data which it processes. That is, information which is obtained from both the Program Store 102 and the Call Store 103 is protected by means of parity bits and, in the case of the Program Store 102, information is further protected by means of Hamming encoding which permits the detection of errors and the correction of single errors. In the event that either central control detects an error, either single or double, in the information received from a program store, the operation of the system is momentarily halted. In the event of a single error, the correction is made and in the case of a double error, the information is reread from the program store information source. In the case of call stores, a parity failure causes the system to momentarily halt and the information is reread from the call store.

At this point it might be well to differentiate between trouble indications which represent errors and faults. An error as defined herein is a malfunction of equipment which the system is not able to reproduce by a systematic logical procedure, while a fault is a malfunction of equipment which the system is able to reproduce repeatedly by a systematic logical procedure. When a trouble indication is first noted it is not known whether this indication represents an error or a fault; therefore, the system must undertake steps to make this determination. For example, as previously noted, if an error is detected in reading the Call Store 103 or an address error or a double error in the case of the Program Store 102, the system temporarily halts and rereads the particular store. If the trouble indication persists, a possible fault is indicated, while if the trouble indication does not persist, a mere transient error is indicated and the central controls proceed with their assigned tasks. It should be noted, however, that the central control increments a physical binary counter each time an error is noted and from time to time this counter is reset. At some time before resetting the counter, however, the output of the counter is examined to assure that the number of errors which have occurred in a fixed unit of time have not exceeded a certain maximum number. This procedure assures that the system is not overly burdened by large numbers of single nonrepeatable errors which probably indicate a system trouble. Nonrepeatable errors reduce the call processing capacity of the system in that the rereading operation requires additional time.

The realization of system maintenance objectives relies heavily on maintenance programs. Upon detection of trouble, a fault recognition program is called upon to recover the system's call processing ability. The fault recognition programs are assigned a high priority; however, their length is held to a minimum to avoid disrupting call processing. The fault recognition programs control any necessary switching or rearrangement of equipment; and request, for subsequent execution, an appropriate low priority diagnostic program which is designed to localize the fault within the faulty unit of equipment. The results of the diagnostic programs are printed out via the Teletype Unit 145 for the use of the maintenance personnel.

In addition to making routine checks on the validity of information which is received from the stores and to making routine checks upon the flow of information through the Central Processor 100, the system also performs a plurality of routine test programs. The test programs have a low execution priority and are designed to search for system faults which are likely to go undetected in normal call processing. The routine test programs can be initiated either automatically on a scheduled basis or as a function of other programs or may be manually requested by means of the Teletype Unit 145.

PROGRAM STORE (102)

The Program Store of the Central Processor comprises a plurality of independent memory units. FIG. 2 is a block diagram of one such independent memory unit.

The Program Store of FIG. 2 is passive in the absence of commands from the Central Control.

In the illustrative embodiment, the Program Store is a permanent magnet-magnetic wire memory (Twistor) which affords nondestructive readout of the information stored therein. The Program Store, being semipermanent in nature, is employed to store certain system data which is changed only at relatively long intervals and the system programs. Information is written into the Program Store by means of the Program Store Card Writer 146 (FIG. 1) under commands from the Central Control 101.

Commands for controlling the Program Store are transmitted from the Central Control to the Program Store via the Bus System 6400, which comprises a 0 bus and an identical 1 bus. As seen in FIG. 2, information can be selectively gated from the 0 bus or the 1 bus to the Control 701 via the Input Path Selection Gates 702 and 703, respectively. The Gates 702 and 703 are selectively enabled in accordance with the contents of the Route Register 501. The Control 701 responds to commands from the Central Control to: (a) enable the Timing Circuit 7800, 7801 to initiate a memory timing cycle, (b) generate control signals for the Access Circuit 7401, 7402, and (c) generate signals for the Operational Check Circuit 7728. Output signals of the Timing Circuit 7800, 7801 serve to advance the Control 701 through a fixed sequence and to provide gating signals for the Access Circuits 7401, 7402 and for the Readout Circuit 7703 through 7706. The Memory 704 of the Program Store of FIG. 2 comprises a plurality of memory (Twistor) modules not to exceed 16 in number. Each memory words a module comprises 8,192 44 bit words. The memory words are associated in pairs at 4096 discrete word pair addresses. The readout circuits 7703 through 7706 have provisions for selecting a chosen 44 bit word of the pair of words which are obtained by addressing one of these discrete word pair addresses. The Operational Check Circuit 7728 monitors the internal operation of the Program Store of FIG. 2 and generates a check signal (termed an all seems well ASW signal), which is returned to the Central Control along with the information which is read from the memory module. Output signals of the Timing Circuit 7800, 7801, along with signals generated within the Control 701, provide gating signals for selectively transmitting information read from the Memory 704 to one of the two identical buses of the Program Store Response Bus System 6500. That is, the Output Path Selection Gates 705 and 706 are selectively enabled to gate the information read from the Memory 704 to the 0 bus and to the 1 bus, respectively.

As seen in FIG. 2, the Route Register 501 is selectively controlled by signals received over the Cables 6700, 6701. The Cables 6700 and 6701 are output cables of the Central Pulse Distributor 143. The Central Pulse Distributor 143 selectively generates output signals on conductors of these cables in ad accordance with commands received from the Central Control 101.

The Central Control 101 manipulates the information in the Route Register 501 to achieve a desired association of an independent Program Store memory unit and the buses of the Command Bus System 6400 and of the Response Bus System 6500.

In summary, the independent Program Store memory unit, such as is shown in FIG. 2, accepts command signals from the Central Control over a selected one of the buses 0 or 1 of the Program Store Command Bus System 6400 and transmits responses to the Central Control via a selected one of the buses 0 or 1 of the Response Bus System 6500. The Program Store of FIG. 2, through the Operational Check Circuit 7728, monitors the internal operation of that program store memory unit and generates check signals for transmission to the Central Control along with information read from the Memory 704. The internal operation of a program store unit is in accordance with timing signals generated by the Timing Circuit 7800, 7801 and information is transmitted to the Central Control at times determined by such internally generated timing signals. The timing circuit is arranged to initiate a timing sequence when a command is received from the Central Control.

The Memory System 371 comprises a plurality of independent Program Stores and a plurality of independent Call Stores. The organization of the long term data and program information into one type of memory unit and the rapidly changing data into the other types of memory units is not essential to the present invention, but rather is a characteristic of the illustrative data processing system which is described herein. That is, the Memory System 371 could comprise a plurality of independent read and write memories in which all of the system information was stored.

The number of Program Stores is determined principally by the size of the switching system, i.e., the number of lines and trunks served by the system and the variety of services rendered the lines and trunks. However, at least two program stores are always used to achieve system dependability through the teachings of this invention.

The information capacity of a program store is divided into a left half and a right half. Where the number of program stores employed exceeds two, the information in the right half of the first store is duplicated in the left half of the second store; the information in the right half of the second store is duplicated in the left half of the succeeding store; and the information in the right half of the last store is duplicated in the left half of the first store. This arrangement permits full duplication of information with either an even or an odd number of stores.

CALL STORE (103)

The Call Store of the Central Processor comprises a plurality of independent memory units. FIG. 3 is a block diagram of one such independent memory unit.

The Call Store of FIG. 3, like the Program Store of FIG. 2, is passive in the absence of commands from the Central Control.

In the illustrative embodiment, a word organized ferrite sheet memory is employed as the memory element of the Call Store 103. The Call Store of FIG. 3 is a destructive readout type memory and information may be read from or written into this memory in a time cycle which corresponds to the time cycle of the Central Control 101. The Call Store, being temporary in nature, is employed to store the system data which is subject to rapid change in the course of processing calls through the system.

Commands for controlling the Call Store are transmitted from the Central Control to the Call Store via the Bus System 6401, which comprises a 0 bus and an identical 1 bus. Such commands comprise an address defining a location within the Memory 8500 of FIG. 3 and an instruction portion which indicates that the command is to read information from the memory or to write information into the memory. In the case of commands to write information into the memory, the data to be placed in memory is transmitted from the Central Control to the Call Store via the Bus System 6402, which comprises a 0 bus and an identical 1 bus. As seen in FIG. 2, information can be selectively gated from the 0 bus and the 1 bus of the Bus Systems 6401 and 6402 for use in controlling the memory unit of FIG. 3. The Gates 802 through 805 are controlled in accordance with the contents of the Route Register 806 of FIG. 3. The Control 801 responds to commands from the Central Control to: (a) enable the Timing Circuit 8800 to initiate a memory timing cycle, (b) generate control signals for the Access Circuit 8501, 8502 and the Readout Circuit 8503, 8504, (c) enable the Operational Check Circuit 807, and (d) provide control signals for the Output Path Selection Gates 808. Output signals of the Timing Circuit 8800 serve to advance the Control 801 through a fixed sequence and to provide gating signals for the Access Circuit, the Readout Circuit and the Operational Check Circuit of FIG. 3. The Output Path Selection Gates 808 are selectively enabled by the Control Circuit 801 in accordance with the state of the Route Register 806 to gate data read from the Memory 8500 to the 0 or the 1 Call Store Response Bus of the Bus System 6501.

As seen in FIG. 3, the Route Register 806, like the Route Register 501 of the Program Store of FIG. 2, is controlled by signals over the Cables 6700, 6701. That is, the Route Register is controlled by output signals of the Central Pulse Distributor 143 in accordance with commands received by the Central Pulse Distributor from the Central Control 101.

The Central Control 101 manipulates the information in the Route Register 806 to achieve a desired association of the independent call store memory units and the buses of the Command Bus System 6401, the Data Bus System 6402 and the Response Bus System 6501.

In summary, an independent call store memory unit, such as is shown in FIG. 3, accepts command signals and a data from the Central Control over a selected one of the buses 0 or 1 of the Call Store Command Bus System 6401 and the Call Store Data Bus System 6402 and transmits responses to the Central Control via a selected one of the buses 0 or 1 of the Response Bus System 6501. The Call Store of FIG. 3, through the Operational Check Circuit 807, monitors the internal operation of the call store memory and generates check signals for transmission to the Central Control along with the information read from the Memory 8500. The internal operation of a Call Store unit is in accordance with timing signals generated by the Timing Circuit 8500 and information is transmitted to the Central Control at times determined by such internally generated timing signals. The Timing Circuit 8500 is arranged to initiate a timing sequence when a command is received from the Central Control 101.

As previously discussed, the Call Store 103 comprises a plurality of independent Call Stores. The number of call stores is determined, like the program store is determined, by the size of the switching system and the variety of services rendered the lines and trunks of the system. At least two call stores are always used to achieve system dependability. The information capacity of a call store is divided into a left half and a right half. Where the number of call stores employed exceeds two, information is duplicated in the stores in the pattern described with respect to the storage of information in the program stores.

EQUIPMENT DESCRIPTION

The drawing employed herein in many instances shows single lines as the connections between blocks; it is to be understood that single lines are merely symbolic and may indicate numerous connections such as a cable or a bus as previously defined herein.

In certain instances, the binary states of a circuit are provided on a pair of output conductors which are alternatively energized. Such an arrangement is called a 2-rail circuit and binary devices which provide individual 0 and 1 state output signals are called 2-rail logic elements herein. In other instances, only one of the two states of a binary device is employed as an output signal, and such arrangements are called single rail circuits. Throughout the drawing gates, symbols of amplifiers, et cetera, are understood to be in many cases a plurality of gates or amplifiers comprising a number of channels equal to the number of individual signals to be transmitted therethrough. For example, in FIG. 11 an the AND gate 1104 when enabled, transmits the 10 information bits A0--A5, S1, S2, W, and CM from the output of the Cable Receiver 1102 to the input of the symbolic plural OR gate 1109. Accordingly, Cable Receiver 1102 comprises 10 transformers and 10 amplifiers; AND gate 1104 comprises 10 AND gates, and OR gate 1109 comprises 10 OR gates. Further, in the drawing there are two types of AND gates such as AND gate 3006 shown in FIG. 30. This symbol represents a plurality of AND gates equal in number to the number of information paths included in a cable. If the cable conveys information on a single rail basis, then there is one AND gate per information bit; however, if the cable conveys information on a 2-rail basis, then the number of AND gates represented by the symbol equals 2 times the number of information bits.

The second type of AND gate which converts information from 1-rail to 2-rail is symbolized in FIG. 30 wherein gate 3008 is shown as a conventional AND gate with a bar included inside the symbol. This type of AND gate is shown in schematic detail in FIG. 30A. The data on cable 30A04 is on a single rail basis, that is, the cable 30A04 comprises one conductor for each of the information bits included in the data and these conductors are energized when a 1 is transmitted and are deenergized or held near ground when a 0 is transmitted. The single rail data on cable 30A04 is inverted on a bit-by-bit basis by the symbolic inverter 30A03, the output conductors of which comprise the input cable to conventional AND gate 30A02. The input signals to the AND gate 30A02 are the complement of the input signals to the AND gate 30A01. The AND gates 30A01 and 30A02 may be enabled by a signal on conductor 30A05 and the output terminals of these gates represent the 1 and 0 rails which are employed to set and reset registers. The symbol for this type of converting AND gate is shown in FIG. 30A and is labeled 30A06.

CENTRAL CONTROL (101)

The Central Control 101, which is shown in simplified block diagrams form in FIG. 4 and in detail in FIGS. 10 through 63, is the system data processing unit. For the purpose of discussion the Central Control 101 may be divided into three basic parts:

1. Basic data processing facilities;

2. Facilities for communicating with central control input sources and output devices; and

3. Maintenance facilities.

The central control performs system data processing functions in accordance with program orders which are stored principally in the Program Store 102. In a few specialized instances program orders are found in the Call Store 103. The program orders are arranged within the memories in ordered sequences. The program orders fall into two general classifications, namely, decision orders and nondecision orders.

Decision orders are generally employed to institute desired actions in response to changing conditions either with regard to lines or trunks served by the switching system or changing conditions with respect to the maintenance of the system.

Decision orders dictate that a decision shall be made in accordance with certain observed conditions and the result of the decision causes central control to advance to the next order of the current sequence of order words or to transfer to an order in another sequence of order words. The decision to transfer to another sequence may be coupled with a further determination that the transfer shall be made to a particular one of a plurality of sequences. Decision orders are also termed conditional transfer orders.

Nondecision orders are employed to communicate with units external to Central Control 101 and to both move data from one location to another and to logically process the data. For example, data may be merged with other data by the logical functions an of AND, OR, EXCLUSIVE-OR, product mask, et cetera, and also data may be complemented, shifted, and rotated.

Nondecision orders perform some data processing and/or communicating actions, and upon completion of such actions most nondecision orders cause the Central Control 101 to execute the next order in the sequence. A few nondecision orders are termed unconditional transfer orders and these dictate that a transfer shall be made from the current sequence of program orders to another sequence of order words without benefit of a decision.

The sequences of order words which are stored principally in the program store comprise ordered lists of both decision and nondecision orders which are intended to be executed serially in time. The processing of data within the central control is on a purely logical basis; however, ancillary to the logical operations, the Central Control 101 is arranged to perform certain minor arithmetic functions. The arithmetic functions are generally not concerned with the processing of data but, rather, are primarily employed in the process of fetching new data from the memories such as from the Program Store 102, the Call Store 103, or particular flip-flop registers within the Central Control 101.

The individual order words are designed to complement the physical characteristics of the central processor and to complement each other. Thus, through careful design of the program order word structure it is possible to maximize the data process capacity of the central processor.

The Central Control 101, in response to the order word sequences, processes data and generates and transmits signals for the control of other system units. The control signals which are called commands are selectively transmitted to the Program Store 102, the Call Store 103, The the Central Pulse Distributor 143, the Master Scanner 144, the network units such as the Network Scanners 123, 127, 135, 139, Network Controllers 122, 131, Network Signal Distributors 128, 136, 140, and the miscellaneous units such as the Teletype Unit 145, the Program Store Card Writer 146, and the AMA Unit 147.

The Central Control 101 is, as its name implies, a centralized unit for controlling all of the other units of the system. A Central Control 101 principally comprises:

A. A plurality of multistage flip-flop registers;

B. A plurality of decoding circuits;

C. A plurality of private bus systems for communicating between various elements of the central control;

D. A plurality of receiving circuits for accepting input information from a plurality of sources;

E. A plurality of transmitting circuits for transmitting commands and other control signals;

F. A plurality of sequence circuits;

G. Clock sources; and

H. A plurality of gating circuits for combining timing pulses with DC conditions derived within the system.

The Central Control 101 is a synchronous system in the sense that the functions within the Central Control 101 are under the control of a multiphase Microsecond Clock 6100 which provides timing signals for performing all of the logical functions within the system. The timing signals which are derived from the Microsecond Clock 6100 are combined with DC signals from a number of sources in the Order Combining Gate Circuit 3901. The details of the Order Combining Gate circuit 3901 are not shown in the drawing as the mass of this detail would merely tend to obscure the inventive concepts of this system.

SEQUENCE OF CENTRAL CONTROL OPERATIONS

All of the system functions are accomplished by execution of the sequences of orders which are obtained from the Program Store 102 or the Call Store 103. Each order of a sequence directs Central Control 101 to perform one operational step. An operational step may include several logical operations as set forth above, a decision where specified, and the generation and transmission of commands to other system units.

The Central Control 101 at the times specified by phases of the Microsecond Clock 6100 performs the operational step actions specified by an order. Some of these operational step actions occur simultaneously within Central Control 101, while others are performed in sequence. The basic machine cycle, which in this one illustrative embodiment is 5.5 microseconds, is divided into three major phases of approximately equal duration. For purposes of controlling sequential actions within a basic phase of the machine cycle each phase is further divided into one-half microsecond periods which are initiated at one-quarter microsecond intervals.

The basic machine cycle for purposes of designating time is divided into one-quarter microsecond intervals, and the beginning instants of these intervals are labeled TO through T22. The major phases are labeled phase 1, phase 2, and phase 3. These phases occur in a 5.5 microsecond machine cycle as follows:

A. Phase 1-- T0 to T8;

B. Phase 2-- T10 to T16;

C. Phase 3-- T16 to T22.

For convenience in both the following description and in the drawing, periods of time are designated bTe where b is the number assigned the instant at which a period of time begins and e the number assigned the instant at which a period of time is ended. For example, the statement 10T16 defines phase 2 which begins at time 10 and ends at time 16. The division of time is shown in FIG. 64.

As seen in FIG. 61, each central control has a 2 2 megacycle Clock Oscillator 6106. The Clock Oscillator 6106 of the active central control serves to drive the Microsecond Clock 6100 in both the active central control and the standby central control. The Oscillator 6106 of the active central control is connected to the input of the Microsecond Clock 6100 of the active central control via AND gate 6108 and OR gate 6110. AND gate 6108 is enabled by a signal on order cable conductor 61AU which indicates that the active unit flip-flop 55AU is in the 1 state. The output of the Oscillator 6106 is transmitted to the other central control via conductor 6111, amplifier 6112, transformer 6113, and an interconnecting transmission pair. In the other central control the oscillator output signal is received via a transformer such as 6114, an amplifier such as 6115, conductor 6116 and in the standby central control this signal is transmitted to the Microsecond Clock 6100 via a path which includes AND gate 6109 and OR gate 6110. AND gate 6109 is enabled by a signal on order cable conductor 61AU. The Microsecond Clock 6100 in the active central control generates a clock phasing pulse labeled Clock Phase-I which is transmitted from the active central control to the standby central control via conductor 6117, amplifier 6118, transformer 6119 and an interconnecting transmission pair. In the standby central control the phasing signal is received over transformer 6120, amplifier 6121 and is transmitted to the microsecond clock reset terminal via AND gate 6122. AND gate 6122 is enabled by a signal on order cable conductor 61AU. The clock phasing signal serves to keep the two microsecond clocks in correspondence.

The Microsecond Clock 6100 generates output signals as shown in FIG. 64. These output signals are transmitted to the Order Combining Gate 3901. Further, the Microsecond Clock 6100 provides input signals to the Millisecond Clock 6101 via conductor 6105. These input signals occur once every 5.5 microseconds.

The Millisecond Clock 6101 comprises 12 binary counter stages along with counter recycling circuitry. The 12 stages are arranged as a series of recycling counters, the output of each counter providing an input to the next succeeding counter. Stages 1 through 4 provide a count of 13 and thus, with 5.5 microsecond input signals, provide an output signal once every 71.5 microseconds. Stages 5 through 7 provide a count of 7 and thus, with an input once every 71.5 microseconds, provide an output once every 500.5 microseconds (once per half millisecond). Stage 8 provides a count of 2 and thus, with a half millisecond input interval, provides an output pulse once every millisecond. Stages 9, 10, and 11 provide a count of 5 and, with input pulses once per millisecond, provide output pulses once every 5 milliseconds. Stage 12 provides a count of 2 and thus, with input pulses once every 5 milliseconds, provides an output pulse once every 10 milliseconds.

The output conductors of the 1 side of each counter stage of the Millisecond Clock 6101 are connected to the Order Combining Gate Circuit 3901 and these conductors appear in FIG. 42 as inputs to symbolic AND gate 4200. Thus, the states of these 12 counters may be gated to the buffer register input bus system via AND gate 4200 when enabled by a signal on order cable conductor 13R-BR.

As explained later herein, the 704 microsecond output conductor of the Millisecond Clock 6101 is employed to count up to 128 machine cycles.

In order to maximize the data processing capacity of Central Control 101 three cycle overlap operation is employed. In this mode of operation central control simultaneously performs:

A. The operational step for one instruction;

B. Receives from the Program Store 102 the order for the next operational step; and

C. Sends an address to the Program Store 102 for the next succeeding order.

This mode of operation is illustrated in FIG. 65. Three cycle overlap operation is made possible by the provision of both a Buffer Order Word Register 2410, an Order Word Register 3403 and their respective decoders, the Buffer Order Word Decoder 3902 and the Order Word Decoder 3904. A Mixed Decoder 3903 resolves conflicts between the program words in the Order Word Register 3403 and the Buffer Order Word Register 2410. The Auxiliary Buffer Order Word Register 1901 absorbs differences in time of program store response.

The initial gating action signals for the order X (herein designated the indexing cycle) are derived in the Buffer Order Word Decoder 3902 in response to the appearance of order X in the Buffer Order Word Register 2410. The order X is gated to the Order Word Register 3403 (while still being retained in the Buffer Order Word Register 2410 for the indexing cycle) during phase 3 of cycle 2; upon reaching the Order Word Register 3403 the final gating actions (herein indicated as the execution cycle) for the order X are controlled via Order Word Decoder 3904.

The indexing cycle and the execution cycle are each less than a 5.5 microsecond machine cycle in duration. In the executing of the operational steps of a sequence of orders like those shown in FIG. 65 each order remains in the Order Word Register 3403 and the Buffer Order Word Register 2410 each for one 5.5 microsecond cycle. The Buffer Order Word Decoder 3902 and the Order Word Decoder 3904 are DC combinational circuits; the DC output signals of the decoders are combined with selected microsecond clock pulses (among those indicated in FIG. 64) in the Order Combining Gate Circuit 3901. This Order Combining Gate Circuit 3901 thus generates the proper sequences of gating signals to carry out the indexing cycle and the execution cycle of each of the sequence of orders in turn as they appear first in the Buffer Order Word Register 2410 and then in the Order Word Register 3403.

The performance of the operational steps for certain orders requires more time than one operational step period, i.e., more than 5.5 microseconds. This requirement for additional time may be specified directly by the order; however, in other instances this requirement for additional time is imposed by indicated trouble conditions which occur during the execution of an order. Where an order specifies that the execution thereof will require more than one operational step period, the additional processing time for that order may be gained by:

1. Performing the additional data processing during and immediately following the indexing cycle of the order and before the execution cycle of the order; or

2. Performing the additional data processing during and immediately after the normal execution cycle of the order.

The performance of these additional work functions is accomplished by way of a plurality of sequence circuits within Central Control 101. These sequence circuits are hardware configurations which are activated by associated program orders or trouble indications and which serve to extend the time in the operational step beyond the normal operational step period illustrated in FIG. 65. The period of time by which the normal operational step period is extended varies depending upon the amount of additional time required and is not necessarily an integral number of machine cycles. However, the sequences which cause delays in the execution of other orders always cause delays which are an integral number of machine cycles.

The sequence circuits share control of data processing within the Central Control 101 with the decoders, i.e., the Buffer Order Word Decoder 3902 (BOWD), the Order Word Decoder 3904 (OWD), and the Mixed Decoder 3903 (MXD). In the case of orders in which the additional work functions are performed before the beginning of the execution cycle, the sequence circuit or, as more commonly referred to, the "sequencer" controls the Central Control 101 to the exclusion of decoders BOWD, OWD, and MXD. However, in the case of orders in which the additional work functions are performed during and immediately after the execution cycle of the order, the sequencer and the decoders jointly and simultaneously share control of the Central Control 101. In this latter case there are a number of limitations placed on the orders which follow an order which requires the enablement of a sequencer. Such limitations assure that the central control elements which are under the control of the sequencer are not simultaneously under control of the program order words.

Each sequence circuit contains a counter circuit, the states of which define the gating actions to be performed by the sequence circuit. The activation of a sequence circuit consists of starting its counter. The output signals of the counter stages are combined with other information signals appearing within Central Control 101 and with selected clock pulses in the Order Combining Gate Circuit 3901 to generate gating signals. These signals carry out the required sequence circuit gating actions and cause the counter circuit to advance through its sequence of internal states.

Sequence circuits which extend the period of an operational step by seizing control of a Central Control 101 to the exclusion of the decoders BOWD, OWD, and MXD are arranged to transmit the address of the next succeeding program order word concurrently with the completion of the sequencer gating actions. Thus, although the execution of the order immediately succeeding an order which enabled the sequencer of the above character is delayed, the degree of overlap shown in FIG. 65 is maintained.

Sequence circuits which do not exclude the decoders BOWS BOWD, OWD, and MXD provide additional overlap beyond that shown in FIG. 65. That is, the transmission of the address of and acceptance of the order immediately succeeding an order, which enabled a sequencer, are not delayed. The additional gating actions required by such sequence circuits are carried out not only concurrently with the indexing cycle of the immediately succeeding order, but also concurrently with at least a portion of the execution cycle of the immediately succeeding order.

A few examples will serve to illustrate the utility of the sequence circuits. A program order which is employed to read data from the Program Store 102 requires an additional two 5.5 microsecond machine cycle periods for completion. This type of order gains the additional two cycles by delaying the acceptance of the immediately succeeding order and performs the additional work operations after termination of the indexing cycle of the current order and before the execution cycle of the current order.

When errors occur in the reading of words from the Program Store 102, the Program Store Correct-Reread Sequencer 5301 is enabled to effect a correction or a rereading of the Program Store 102 at the previously addressed location. This sequence circuit is representative of the type of sequence circuit which is enabled by a trouble indication and which seizes control of the Central Control 101 to the exclusion of the decoders.

The Command Order Sequencer 4902 which serves to transmit network commands to the Switching Network 120 and to the miscellaneous network units, i.e., Master Scanner 144, AMA Tape Unit 147, and Card Writer 146, is representative of the sequence circuits which, when enabled, increase the degree of overlap beyond that shown in FIG. 65. That is, the transmission of network commands extends into the execution cycle of the order following the network command order.

In the processing of certain multicycle orders a plurality of sequence circuits may be activated so that the processing of the multicycle order may include both kinds of gating actions; first additional gating cycles may be inserted between the indexing cycle and the execution cycle of the order, and then a second sequence circuit may be activated to carry out gating actions which extend the degree of overlap to an additional cycle or cycles.

CENTRAL CONTROL RESPONSES TO PROGRAM ORDER WORDS

FIG. 4, which is a simplified sketch of the Central Control 101, aids in understanding the basic operational step actions that are performed by Central Control 101 in response to various program order words. Each program order word comprises an operational field, a data-address field, and Hamming error detecting and correcting bits.

The operation field is a 14 or a 16 bit binary word which defines the order and specifies the operational step actions to be performed by the Central Control 101 in response to the order. The operation field is 14 or 16 bits long, depending on the particular order which is defined by the operation field.

There are sets of "options" that may be specified with each of the program order words. The operational step of each order consists of a specific set of gating actions to process data contained in Central Control 101 and/or communicate information between the Central Control 101 and other units in our system. When an option is specified with the program order being executed, additional data processing is included in the operational step. The specific gating actions and the data processing performed for each of the options are described elsewhere herein. Accordingly, a portion of the 14 or 16 bit operation field of a program order word specifies the program order, and the remaining portion of the field may select one or more of the options to be executed.

Certain of the options are compatible with and provide additional data processing for nearly all of the orders. An example of such an option is that of "indexing" in which none or one of seven flip-flop registers within Central Control 101 are selected for additional data processing. In the orders which permit indexing a three bit portion of the operation field is reserved as the indexing field to indicate the choice of none or the one of seven registers to be employed.

Other options are limited to those orders for which the associated gating actions do not conflict with other portions of the operational step and are also excluded from those orders to which the options do not provide useful additions. Accordingly, portions of the operation field are reserved for those options only where applicable. That is, Central Control 101 is responsive to such options only if the program order word being executed is one to which the options are applicable. If an option is not applicable, then that portion of the operation field instead serves in the specification of other program orders or options. The assignment of the binary codes in portions of the operation field to options is therefore selectively conditioned upon the accompanying program order if the option is to have limited availability. This conditional assignment advantageously permits the inclusion of a larger variety of orders and options than could otherwise be included in the 14 to 16 bit operation field.

The data-address field of a program order word is either a 23 bit data word to be placed in a selected flip-flop register in Central Control 101 or a 21 bit word which may be used directly or with indexing to form a code-address for addressing memory. In all order words the sum of the bits of the operation field (16 or 14) plus the bits of the data-address field 21 or 23 is always 37 bits. If the order word has a 16 bit operation field, its data-address field will be 21 bits long; if the operation field is 14 bits long, the data-address is a 23 bit number. The shortened DA field is utilized to obtain more combinations in the correspondingly lengthened operation field and therefore a larger and more powerful collection of program order words.

The Central Control 101 performs the operational steps for most orders at the rate of one order per 5.5 microsecond cycle. Although such orders are designated single cycle orders, the total time involved in obtaining the order word and the central control responses thereto is in the order of three 5.5 microsecond cycles. The overlap operation previously noted herein permits Central Control 101 to achieve the stated rate of performing one such single cycle order every 5.5 microseconds.

The sequence of gating actions for a typical order, order X, and their relationship to the gating actions for the preceding order, order X-1, and a succeeding order, order X+1, are shown in FIG. 65. As shown on line 2 of FIG. 65, during phase 1 of a 5.5 microsecond cycle that is arbitrarily designated cycle 1, the code and address of program order word X appears in the Program Address Register 4801 (PAR) and is gated to the Program Store 102 via the Program Store Address Bus 6400. The code and address is interpreted by the Program Store 102 and the order word X is returned to central control over the Program Store Response Bus 6500 sometime during phase 3 of cycle 1 or phase 1 of cycle 2. The operation field portion of the program order word is gated into the Auxiliary Buffer Order Word Register 1901 (ABOWR), and the data-address field, and the Hamming bits of the order word are gated into the Buffer Order Word Register 2410 (BOWR).

The operation field is first gated into the Auxiliary Buffer Order Word Register 1901 (ABOWR) since it is possible that the program order word which is returned from the Program Store 102 reaches Central Control 101 prior to completion of the gating actions by the Buffer Order Word Decoder 3902 (BOWD) on the preceding order word, in this case order word X-1. This may be seen by reference to FIG. 65 where in the line labeled X-1, the gating directed by the Buffer Order Word Decoder 3902 (BOWD) for the order word X-1 is completed at the end of phase 3 of cycle 1; and, as shown in the line labeled X, the program order word X may reach central control in the latter portion of phase 3 of cycle 1. The Auxiliary Buffer Order Word Register 1901 (ABOWR) resolves this conflict. The same situation does not obtain with respect to either the Hamming encoding bits or the data-address word as by the end of phase 2 of cycle 1 all of the actions with respect to both the Hamming encoding bits and the data-address bits for the order X-1 have been completed.

The time at which a program order word reaches the Central Control 101 is subject to variation as a result of a number of factors. For example, since there are two central controls and a number of program stores, the physical distance between particular central control and each of the program stores is different and this difference is reflected in both the Program Store Address Bus 6400 and in the Program Store Response Bus 6500. Further, there may be differences in the response times of the various program stores and their access circuits and these variations may be cumulative with the differences in bus lengths.

The decoded outputs of the Buffer Order Word Decoder 3902 (BOWD) are combined with selected clock pulses from the Microsecond Clock 6100 (CLK) in the Order Combining Gate Circuit 3901 (OCG) which operates selected gates within Central Control 101 in the proper time sequence during phase 2 and phase 3 of the second cycle to perform indexing, index modification, and certain other gating actions with respect to order X.

During phase 3 of the second cycle the operation field of order X (FIG. 65) is gated from the Buffer Order Word Register 2410 (BOWR) to the Order Word Register 3403 (OWR). The Order Word Decoder 3904 (OWD) decodes the operation field of the order X which is in the Order Word Register 3403 (OWR) for the performance of the remaining gating actions. DC output signals from the Order Word Decoder 3904 (OWD) are combined with selected pulses from the Microsecond Clock 6100 (CLK) in the Order Combining Gate 3901 (OCG) to complete the gating actions of the single cycle order X during phase 1 and phase 2 of the third cycle.

During phase 2 of the third cycle order X is completing its last gating action from the Order Word Register 3403 (OWR) and the Order Word Decoder 3904 (OWD), and order X+1 is simultaneously performing the indexing step from the Buffer Order Word Register 2410 (BOWR) and the Buffer Order Word Decoder 3902 (BOWD). Since the simultaneous gating actions may conflict in the use of the flip-flop registers such as XR, YR, ZR, et cetera, the Mixed Decoder 3903 (MXD) decodes the contents of both the Buffer Order Word Register 2410 (BOWR) and the Order Word Register 3403 (OWR). The Mixed Decoder 3903 (MXD) outputs, which are DC signals, are combined with the outputs of the Buffer Order Word Decoder 3902 (BOWD) in the Order Combining Gates 3901 (OCG) to modify gating actions so as to resolve conflicts in the two operational steps.

A conflict which is resolved by the Mixed Decoder 3903 occurs when a first order specifies a particular one of the index registers as the destination register for a memory word obtained by the execution of that order while the immediately succeeding order specifies that the contents of that same index register be employed in indexing. In the performance of indexing, the contents of the specified index register are normally gated from the output of the specified index register to the Unmasked Bus 2014 and from there to the Augend Register 2908. However, where successive orders specify the same index register as a destination register for memory reading and as a source register, there is insufficient time to complete the transfer of the information to the destination register; therefore, the Mixed Decoder 3903 in these instances transfers the desired information from the Masked Bus 2011 directly to the Augend Register 2908 at the same time that this information is being transmitted to the specified destination index register.

MASK AND COMPLEMENT CIRCUIT 2000 (M&C)

The internal data processing structure is built around two multiconductor buses, the Unmasked Bus 2014 (UB) and the Masked Bus 2011 (MB), which provide a link for moving a multibit word of data from one of a specific group of flip-flop registers to another. This group consists of the K Index Registers 2601 (BR), 5801 (FR), 5802 (JR), 4001 (KR), 2501 (XR), 3001 (YR), and 3002 (ZR) and the Logic Register 2508 (LR).

The Mask and Complement Circuit 2000 (M&C) connects the Unmasked Bus UB to the Masked Bus MB and provides means for logically operating upon the data as it passes from the Unmasked Bus UB to the Masked Bus MB. The logical operation to be performed, product masking (AND), union masking (OR), exclusive OR masking (EXCLUSIVE-OR), and complementing is prescribed by the operation field of the program order as decoded by either the Buffer Order Word Decoder BOWD or the Order Word Decoder OWD. Only one masking operation may be performed in a single pass of data through the circuit M&C; however, the masking operation may be followed by a complementing operation in gating data through the circuit M&C. Each of the masking operations requires two operands and the contents of the Logic Register LR always comprises one of the operands.

The Mask and Complement Circuit M&C (2000) which is shown in greater detail in FIG. 20 also provides a convenient means for connecting the Data Buffer Register 2601 and the Index Adder Output Register 3401 to the Masked Bus 2011. The data word which appears at one of the input AND gates 2001--2003 of the Mask and Complement Circuit 2000 may be selectively gated directly to the Masked Bus 2011 without alteration or may be a masked and/or complemented during transmission through the mask and complement circuit. The AND-OR Circuit 2005 serves to "Union" mask or "Product" mask the input data word when enabled by order cable signals on conductors 20UMASK and 30PMASK, respectively. The word appearing at the output of the AND-OR Circuit 2005 may be complemented in the Complement Circuit 2006 by enabling order cable conductor 20COMP or may be transmitted directly to the Masked Bus 2011 by enabling order cable conductor 20MPASS.

The input data word may be gated directly to the Masked Bus 2011 by enabling AND gate 2012 by an order cable signal on conductor 20PASS or may be complemented in the Complement Circuit 2007 by enabling order cable conductor 20COMP.

Exclusive OR masking may be achieved in the EXCLUSIVE-OR Circuit 2008 by enabling order cable conductor 20XMASK. It should be noted that it is not possible to complement the data word appearing at the output of the EXCLUSIVE-OR Circuit 2008.

K REGISTER 4001 (KR); K LOGIC (KLOG; DETECT FIRST-ONE CIRCUIT 5415 (DFO)

The K Register KR, the K Logic KLOG, and the Detect First-One Circuit 5415 (DFO) provide a second major internal data processing facility. The K Logic KLOG comprises input and output circuitry surrounding the K Register 4001. The K Logic KLOG includes the K A Input Register 3502, the K B Input Register 3504, the K Input Logic 3505, the K Logic Homogeneity Circuit 4502; and at the output of the K Register 4001 the Rotate Shift Circuit 4500 and the K Register Homogeneity Circuit 4503. The K Logic KLOG may be directed by output signals of the Order Combining Gate OCG to perform one of four logical operations on two operands. One operand is the content of the K Register KR; the other is the information on the Masked Bus MB. The Order Word Decoder OWD and the K Register Sequence Circuit (part of SEQ) generate signals which cause the K Logic KLOG to combine the two operands in the operations of AND, OR, EXCLUSIVE-OR, or ADDITION. The word resulting from the logical combination, according to the order in the Order Word Register OWR, may either be gated to the K Register KR or to the Control Homogeneity Circuit CH and the Control Sign Circuit CS.

A word appearing on the Masked Bus MB may in some instances be gated directly to the K Register KR via the K Logic KLOG. The K Register KR may thereby be employed as a simple destination register for data like other flip-flop registers in central control such as XR, YR, ZR, et cetera.

In carrying out the ADDITION operation in the K Logic KLOG the two operands are treated as 22 bit signed numbers. The 23 bit of each operand is the sign bit. If this bit has the value 0 the number is positive, and the magnitude of the number is given by the remaining 22 bits. If the sign bit is 1 the number is negative, and the magnitude of the number is given by the one's complement of the remaining 22 bits. (The magnitude is determined by inverting each bit of the 22 bit number.) The add circuit within K Logic KLOG can correctly add any combination of positive and negative operands as long as the magnitude of the algebraic sum of the two operands is equal to or less than 2hu 22 -1.

The K Logic KLOG and the K Register KR can perform other logical operations on the contents of the K Register KR. One of these operations is given the name "SHIFT." The gating action performed by SHIFT is based, in part, on the least significant six bits of the number that appears in the Index Adder IA at the time the shift is to be performed. The least significant five bits constitute a number that indicates the magnitude of the shift, and the sixth bit determines the direction of the shift. A 0 in the sixth bit is interpreted as a shift to the left, and the remaining five bits indicate the magnitude of this shift. A 1 in the sixth bit is interpreted as a shift to the right, and the one's complement of the remaining five bits indicates the magnitude of the shift to the right. Although in shifts to the right the least significant five bits contain the one's complement of the magnitude of the shift, the six bit number will be referred to hereafter as comprising a sign and a magnitude.

A shift of one to the left results in the contents of each flip-flop in the K Register KR being gated to the adjacent flip-flop to the left where the register is viewed as in FIG. 40. (The most significant bit of the K Register KR, bit 22, is on the extreme left; and the least significant bit, bit 0, is on the extreme right.) A 0 replaces the contents of the least significant bit position of the K Register KR (there is no flip-flop to the right of the 0 position flip-flop) and the most significant bit is shifted out of the register. That is, the bit 22 flip-flop has no flip-flop to its left and the information is not retained.

A shift of two to the left is equivalent to two successive shifts of one to the left, a shift of three to the left is equivalent to three successive shifts of one to the left, et cetera. A shift of 23 to the left causes all zeros to be placed in the K Register KR. A shift of one to the right results in the contents of each flip-flop in the K Register KR being gated to the adjacent flip-flop to the right. A 0 replaces the contents of the most significant bit of the K Register KR, and the original least significant bit of the K Register KR is thus not retained.

A shift of two to the right is equivalent to two successive shifts of one to the right, a shift of three to the right is equivalent to three successive shifts of one to the right, a shift of 23 to the right results in the contents of the K Register KR being made all zeros.

A logical operation similar to the shift is the operation "ROTATE." As in shifting, the six bits of the Index Adder IA are treated as a direction and magnitude for the rotation just as described for the shift.

A rotate of one to the left is identical to a shift of one to the left except for the gating of the flip-flops at each end of the K Register KR. In a rotation of one to the left the content of bit 22 is not lost as in the shift but instead replaces the content of the least significant zero bit of the K Register KR. A rotate of two to the left is identical to two rotates of one to the left in succession, a rotate of three to the left is identical to three rotates of one to the left, et cetera. A rotate of 23 to the left has the same effect on the K Register KR as no rotation. A rotation to the right bears a similar relation to a shift to the right.

In summary, the gating action of rotation is identical to that of shift except that the register is arranged in a circular fashion wherein the most significant bit is treated as being to the right of the least significant bit of the K Register KR.

A complement option may be employed with shift and rotate orders and, where specified, the significance of the sign bit is inverted, that is, where the complement option is specified a 0 in the sixth bit is interpreted as a shift to the right while a 1 in the sixth bit is interpreted as a shift to the left.

A special purpose rotate order applies rotation to only bits 6 through 21 of the K Register KR and leaves the remaining positions of the K Register KR unchanged.

Another logical gating action is the determination of the rightmost one in the contents of the K Register KR. This action is accomplished by gating the contents of the Detect First-One Circuit DFO to the F Register FR via the Unmasked Bus UB, the Mask and Complement Circuit M&C, and the Masked Bus MB. The number gated is a five bit binary number corresponding to the first stage (reading from the right) in the K Register KR which contains a 1. If the least significant bit of the K Register KR contains a 1, zero is the number gated to the F Register FR. If the first 1 reading from the right is in the next position, one is the number gated to the F Register FR. If the only 1 appearing in the K Register KR is in the most significant position, 22 is the number gated to the F Register FR. If the K register contains no 1's, then nothing is gated to the F Register FR.

INDEX ADDER (IA)

A third major data processing configuration within the Central Control 101 is the Index Adder IA which is used to:

1. Form a quantity designated herein as the indexed DAR word consisting of the sum of the DA field of the program order word being executed and the contents of an index register specified in an order; or

2. To perform the task of a general purpose adder; the operands in this latter instance may be the contents of two index registers or the DA field and the contents of an index register.

The outputs of the Index Adder IA are selectively connected to the Program Address Register PAR, the Memory Address Decoder MAD, and the Call Store Address Bus System 6401 when employed for indexing; the outputs of the adder may also be connected to the Masked Bus MB via the Mask and Complement Circuit M&C when employed as a general purpose adder. Access to the Masked Bus MB permits the word formed to be employed for a number of purposes, for example:

1. Data to be placed in the K Register KR without modification or to be combined with the contents of the K Register KR in the K Logic KLOG;

2. A number for determining the magnitude and direction of a shift or rotate;

3. Data to be placed in a specified index register;

4. Data to be transmitted over the Network Command Bus 6406 via the K Logic KLOG and the Network Translator NETW-T;

5. Data to be sent to the Central Pulse Distributor 143 via the F Register FR and the Central Pulse Distributor Translator CPD-T.

Indexing is the adding of two numbers in the Index Adder IA. The D-A field of the order as it appears in the Buffer Order Word Register BOWR is one operand used in indexing and the other operand, if required, is the contents of one of the seven Index Registers BR, FR, JR, KR, XR, YR, and ZR. For orders which include the indexing option a three bit number within the operation field specifies either 1) no indexing, or 2) indexing on one of the seven flip-flop registers according to the following table. ##SPC1##

If no register is specified for indexing, then only the DA field is gated to the Index Adder IA and the output of the Index Adder IA will be the DA field (the sum of the DA field and zero). If an index register is specified, the contents thereof are normally gated onto the Unmasked Bus UB and from there directly into the Index Adder IA.

If the order X specifies indexing, and if the index constant is obtained by a memory reading operation of the preceding order X-1, then the Mixed Decoder MXD substitutes the Masked Bus MB for the index register. The Mixed Decoder MXD insures that the Index Adder IA always has the correct operands to perform the timely addition to complete the operational step for order X.

A number of the orders have as an option specified by a combination of bits in the operation field the loading of the DA field into the Logic Register LR. This option permits the placing of specified new data into the Logic Register LR for use in subsequent masking operations. If the DA field is used to load the Logic Register LR, then it is considered not available for indexing and the only operand gated to the Index Adder IA is the contents of a specified index register.

The sum appearing at the output of the Index Adder IA is referred to as the DAR address or word. If indexing is not specified in an order, the DAR address or word is the DA field of that order. If indexing is specified and the DA field is not gated to the Logic Register LR, the DAR address or word will be the sum of the DA field and the contents of the specified index register. If the DA field is used for loading the Logic Register LR, the DAR will be the contents of the specified index register.

The Index Adder IA, as well as the add circuit within the K Logic KLOG, utilizes one's complement binary arithmetic. All inputs of the index adder are treated as 22 bit numbers with the 23rd bit a sign bit. A positive number is indicated by a 0 in the 23rd bit and a negative number by a 1 in the 23rd bit. End-around-carry is provided so that the Index Adder IA can correctly handle all four combinations of positive and negative operands as long as the algebraic sum of the two operands does not exceed 2.sup.22 -1.

Some orders, as previously mentioned, have a 23 bit DA field, and others have a 21 bit DA field. If the DA field is only 21 bits long, then the 21st bit is treated as the sign bit; this bit is expanded to also become the 22nd and 23rd bits of the effective DA field gated to the Index Adder IA. Expansion converts a 21 bit DA field to an effective 23 bit DA field for indexing. Expansion preserves the end-around-carry for indexing with 21 bit DA fields.

DECISION LOGIC 3906 (DECL)

The Central Control 101 in the execution of a decision order in a sequence of orders either continues with the current sequence of orders or transfers to a new sequence of orders. The decision is made by the Decision Logic 3906 (DECL) in accordance with the order being processed. The order specifies the information to be examined and the basis for the decision. The information may be obtained from the Control Homogeneity Flip-Flop 5020 of the Control Homogeneity Circuit CH, the Control Sign Flip-Flop 5413 of the Control Sign Circuit CS or selected outputs of the K Logic KLOG. The basis of the decision may be that the information examined is (or is not) arithmetic zero, less than zero, greater than zero, et cetera. A decision to advance does not disturb the current sequence of obtaining and executing orders. A decision to transfer to a new sequence of orders is coupled in accordance with the particular word being executed to a determination of whether the transfer is an "early transfer" or a "late transfer." Accordingly, if the decision is made to transfer, either the early transfer conductor ETR or the late transfer conductor LTR will be energized and thereby activate the Transfer Sequencer 4401. Transfer signals from these conductors lead to the gating of the transfer address to the Program Address Register PAR. This causes the next program order word to be obtained from a new sequence of order words. The transfer address may be obtained from a number of sources and the source is indicated by the order being executed. In the case of "early transfer" orders, the transfer address comprises the contents of a preselected one of the J Register JR or the Z Register ZR. In the case of "late transfer" orders the transfer address may be obtained directly, in which case the DAR code-address which is formed in the index adder is employed, or indirectly, in which case the transfer address comprises a memory reading at the location specified by the DAR code-address which is formed in the Index Adder IA. This latter case is referred to herein as indirect addressing.

The distinction between "early transfer" and "late transfer" orders is based on whether or not the decision order requires a memory reading or writing in the event of an advance. A decision order which requires a memory to be read or written into after a decision to advance is an "early transfer" order. If the decision on such an early transfer order is to advance, then the memory reading or writing operation is carried out as a normal gating action under control of the Buffer Order Word Decoder BOWD and the Order Word Decoder OWD. However, if the decision is to transfer, the decision is advantageously made "early" to inhibit the gating associated with the memory reading or writing operation.

Other transfer orders which do not require a memory reading operation but which do require extensive data processing prior to making the decision are termed "late transfer" orders. These orders cannot employ the early transfer timing sequence in that the data processing operations required thereby are not necessarily completed by the time the early transfer signal would be generated.

Two input information sources for the decision logic comprise the output signals of the control homogeneity flip-flop and the control sign flip-flop which are employed to register homogeneity and sign information which is obtained from a number of locations. For example, a 23 bit data word appearing on the Masked Bus MB may be transmitted to the Control Homogeneity Circuit CH. If the data word comprises either all 0's or all 1's, the Control Homogeneity Flip-Flop 5020 will be set to its 1 state, otherwise the flip-flop will be reset. The Control Sign Circuit CS serves to retain the sign of the data word; the Control Sign Flip-Flop 5413 is set if the word is negative and is reset if the word is positive.

The Control Homogeneity Circuit CH and the Control Sign Circuit CS are utilized by some decision orders by gating the output of a selected index register onto the Unmasked Bus UB, through the Mask and Complement Circuit M&C, onto the Masked Bus MB, and from there into the Control Homogeneity Circuit CH and the Control Sign Circuit CS. The contents of one of the seven index registers specified in the decision order being processed are thereby summarized in the Control Homogeneity Flip-Flop 5020 and Control Sign Flip-Flop 5413. Further gating actions associated with a decision order carry out the transfer or advance according to the output of the Decision Logic DECL.

Similar homogeneity and sign circuits comprise part of the K Logic KLOG to provide facilities for a class of decision orders which transfer or advance according to combinations of the homogeneity and sign of 23 bit words contained in the K register KR.

COMMUNICATION BETWEEN THE CENTRAL CONTROL 101 AND CONNECTING UNITS

A second base function of Central Control 101 is the communication between itself and various other units such as the various memories within the Central Processor 100, the Switching Network 120, the Master Scanner 144, the Central Pulse Distributor 143, et cetera. Generally, communication is accomplished by way of the various bus systems of FIGS. 64--69 and logic circuits which are located in both Central Control 101 and the connecting units.

This communication consists of three general classes. The first class comprises the obtaining of program order words which determine the sequence of actions within Central Control 101. Program order words are primarily obtained from the Program Store 102; however, in special instances program order words for limited actions may be obtained from a Call Store 103. The second class comprises the obtaining of data (excluding program order words) from the memory units within the Central Processor 100, and the third class comprises the generation and transmission of commands to the various network units such as the Switching Network 120, the Master Scanner 144, the Central Pulse Distributor 143, et cetera.

The several memories within the Central Processor 100, namely the Program Store 102, the Call Store 103, the Auxiliary Buffer Registers 3105, 3118, 3605, 3617, 4103, 4603, 5105--5107, 5500, 5902, 6205, 3206, 3703--3708, 4206, 4211, 4717, 4725, 5201, 5209--5211, 5604, 5605, 6002, 6003, 6302 and 6307 (ABR-1...ABR-N [FIG. 9]), and certain other special locations within Central Control 101 are treated as a memory unit and distinct blocks of addresses are individually assigned to each of the memories. There are a number of memory orders which are employed to selectively obtain information from the above memories and to place this information in selected registers within Central Control 101; these are memory reading orders. There are other memory orders which are employed to selectively transmit data from designated registers within Central Control 101 to one of the above memories; these are memory writing orders. The order structure is thus simplified since access to all of the above-mentioned memory locations is by way of a single memory address format.

A memory code-address within Central Control 101 always comprises a 20 bit word consisting of:

1. A code to define a block of information; and

2. An address within the specified block.

The code and the address each vary in length according to the memory unit addressed. For example, the codes for specifying information blocks in the program store are 4 bits long, and the corresponding address is 16 bits long; the codes for specifying information blocks in the Call Store 103 are 8 bits long and are accompanied by 12 bit addresses. However, as will be seen later, the code-address which is transmitted to the Call Store 103 comprises an 18 bit portion of the word, namely a 6 bit code and a 12 bit address.

PROGRAM ORDER WORDS

The communication between the Central Control 101 and the Program Store 102 to obtain program order words may be understood generally with reference to FIG. 4 and in greater detail through a consideration of the central control detail drawings FIGS. 10 through 63 and the timing diagram FIG. 65. The Program Address Register 4801 (PAR FIG. 9) and the Auxiliary Storage Register 4812 (ASR FIG. 9) are selectively employed in transmitting commands to the Program Store 102. The Program Address Register 4801 is employed in the absence of uncorrectable program store reading errors. The Auxiliary Storage Register 4812 is employed whenever a Program Store 102 must be reread. When a command is transmitted from the Program Address Register 4801 to the Program Store Address Bus System 6400 the code-address of the command is also transmitted to the Auxiliary Storage Register 4812. The Auxiliary Storage Register 4812 thus serves to temporarily hold the code-address which is employed in the performance of Hamming error checks. These checks are supplied simultaneously to the order returned and the address employed in obtaining the order. Commands to the Program Store 102 to read information from the memory proper as opposed to test points within the memory access and control circuitry comprise 25 bits as follows:

A. 16 address bits AO through A15;

B. 4 code bits KO through K3;

C. 4 mode bits CM, HM, GM, CRW;

D. a single synchronizing bit SYNC.

The code bits KO through K3 define the block of information in which the selected program store word is located and the address bits AO through A15 define the memory location within the above defined block of information. The four mode bits specify the mode of operation of the program stores as set forth below. It should be noted that the Program Store 102 is always operated in the normal mode in the course of obtaining program order words. The two maintenance modes and the read control and write control modes are reserved for obtaining from the program store information which is to be treated as data as opposed to program order words. ##SPC2##

The sync pulse SYNC (FIG. 33) is employed as a gating signal at the program stores and serves to reduce the time during which the program stores are vulnerable to noise signals on their command buses.

The code and address portions of the program store commands are obtained from the Program Address Register 4801 or the Auxiliary Storage Register 4812 and the four mode bits and the synchronizing bit are obtained from the Order Cable 3900. The four mode bits are required to be selectively other than 0 in all modes other than the normal mode and in these modes the mode bits are defined by the program order word being executed.

The contents of the Program Address Register 4801 (PAR) or the contents of the Auxiliary Storage Register 4812 (ASR) are selectively gated via AND gates 4805 and 4813, respectively, to the input terminals of the OR gate 4806. AND gate 4805 is enabled by an order cable signal on conductor 48PAPS and AND gate 4813 is enabled by an order cable signal on conductor 48ASPS. Information appearing on selected output conductors of OR gate 4806 is encoded, and the encoded information is transmitted to the cable 4804. Bits 0 through 11 and 13 through 15 are passed without modification; however, bits 6 and 12 are combined in the EXCLUSIVE-OR gate 4803 to form bit 12 of the command address. The EXCLUSIVE-OR function involving bits 6 and 12 of the address provides information which is required at the program store to choose the appropriate program store tape, i.e., the A tape or the B tape. Bits 16 through 19 as received from the OR gate 4806 are translated from the 4 bit binary code to a 2-out-of4 code in the Translator 4802. As previously explained, the Program Store 102 is arranged to selectively respond to 2-out-of-4 code signals.

The translated code-address is transmitted via cable 4804 to the Program Store Transmit Bus Selection Gates 3300. The remaining information signal inputs to the Program Store Transmit Bus Selection Gates 3300 comprise the mode bits CM, HM, GM, and CRW which are received from the Order Cable 3900 via conductor group 3317 and the synchronizing bits PS-BIT (FIG. 33) and PS-BOT (FIG. 33).

The Program Store Transmit Bus Selection Gates 3300 are divided into two groups, namely, those employed for transmitting to the 0 bus 3306 of the Program Store Address Bus System 6400 and those associated with the 1 bus 3307 of the Program Store Address Bus System 6400. The command information is selectively transmitted to the 0 bus and/or the 1 bus of the Program Store Address Bus System 6400 in accordance with the Program Store 102-Central Control 101 bus configuration which is being employed. That is, if information is being transmitted from the Central Control 101 to the Program Store 102 via the 0 bus 3306, AND gates 3302, 3308, and 3312 and amplifier 3310 are employed; however, if commands are being transmitted by the 1 bus 3307, AND gates 3303, 3309, and 3313 and amplifier 3311 are employed. The address bits AO through A15 are selectively gated through the AND gates 3302 and 3303 by signals on order cable conductors ADRPS-BO and ADRPS-B1 (FIG. 33), respectively. Similarly, the K bits KO through K3 and the mode bits are selectively transmitted via AND gates 3308, 3312, 3309 and 3313 by order cable signals on conductors PS-BOT and PS-B1T, respectively. Signals on PS-BOT and PS-B1T are also transmitted through their associated amplifiers 3310 and 3311 to provide the synchronizing bit of the program store command.

The output conductors of AND gates 3302, 3308, and 3312 and amplifier 3310 are transmitted via the Cable Driver 3304 to the 0 bus 3306; and the output conductors of AND gates 3303, 3309 and 3313 and amplifier 3311 are transmitted via the Cable Driver 3305 to the 1 bus 3307. The Cable Drivers 3304 and 3305 each comprise a plurality of pulse inverting amplifiers and transformers which couple the Program Store Transmit Bus Selection Gates 3300 to the 0 bus 3306 and the 1 bus 3307.

The Program Store Transmit Bus Selection Gates 3300 are selectively enabled in accordance with the setting of the central pulse distributor controlled status and routing register flip-flops Au, PBO, PBA, and PBT (FIG. 55). The state of flip-flop AU indicates which of the two units is the active central control. The flip-flops PBO, PBA, and PBT (except for commands to read or write control or maintenance data) have the following significance: ##SPC3##

In the above table the X indicates that the standby CC is to send on neither the 0 nor the 1 bus as the active CC is engaged in transmitting to both buses.

The status and routing flip-flops AU, PBO, PBA, and PBT are selectively set and reset by pulses received from the Central Pulse Distributor 143 via selected pairs of the Bipolar Cable 6700, the transformer 1707, amplifiers 1708 and 1711, AND gates 1709 and 1712 and the CPD cable 1719.

The flip-flops PBO, PBA, and PBT in the two central controls are driven by the same CPD points, that is, when the flip-flop PBO in the first central control is set its counterpart PBO in the other central control is also set. The flip-flops AU (active unit) in the two central controls are controlled by a single central pulse distributor bipolar signal point; however, the bipolar signal which serves to set the AU flip-flop in the first central control serves to reset the AU flip-flop in the second central control. Similarly, the CPD signal which serves to reset the AU flip-flop in the first central control serves to set the AU flip-flop in the second central control.

The information required to define the code-address of a program store command is transmitted to the Program Address Register 4801 by one of three possible paths, the chosen path being determined by the sequence of events which lead to the determination of the desired address and code. The desired code-address is selectively obtained by one of the following methods:

A. In the course of executing a sequence of program order words and in the absence of a transfer decision, the code-address of the next order word in the sequence is obtained by incrementing the code-address of the preceding order word by a count of 1. This incrementing function is accomplished by means of the Add-One Register 4304 and the Add-One Logic 4305. The contents of the Program Address Register 4801 are transmitted via cable 4821, AND gate 4301, and OR gate 4303 to the Add-One Register 4304. The AND-gate 4301 is enabled by an order cable signal on conductor PAAO (FIG. 43) at time OT2. The code-address in the Add-One Register 4304 comprises the input to the Add-One Logic 4305 which when enabled by signals on conductor INCR (FIG. 43) serves to increment the input word by a count of 1. The output of the Add-One Logic 4305 is gated to the Program Address Register 4801 via AND-gate 4807 and OR-gate 4808 at time 3T5 by a signal on order cable conductor AOPA (FIG. 48).

From the above sequence it is seen that a very small portion of the 5.5 microsecond operational step cycle is employed in incrementing the address in the Program Address Register 4801. That is, the total time required to increment the address and to return the incremented address to the PAR 4801 is the period of time OT5. Completion of address incrementing in this period of time frees the Add-One Register 4304 and the Add-One Logic 4305 to permit their use for other work functions during the remainder of the cycle. The Add-One Register 4304 and the Add-One Logic 4305 are arranged to operate with 23 bit words for these other work functions.

B. The second source of program store code-address words is the Index Adder Output Register 3401. The Index Adder Output Register 3401 is provided to store the DAR word as described earlier herein. The contents of the Index Adder Output Register 3401 are transmitted via cable 3402, AND gate 4307, and OR gate 4808 to the Program Address Register 4801. This transfer of information is accomplished by enabling order cable conductor IRPA (FIG. 43).

C. The third source of code-address information is the Masked Bus 2011, the contents of which are gated to the Program Address Register 4801 via cable 4313, AND gate 4308, and OR gate 4808 at time 3T5 by enabling order cable conductor MBPA (FIG. 43). This path is employed in the case of interrupts to gate code-address words to the Program Address Register 4801 from the Interrupt Address Source 3411 and is also employed on early transfer orders to gate the contents of the J register 5802 or the Z Register 3002 to the Program Address Register 4801.

The transmittal of commands from the Central Control 101 to the Program Store 102 and the transmittal of the program store responses to the central Control 101 may be understood by reference to FIG. 65. In FIG. 65 the three horizontal lines represent functions which occur with respect to arbitrary orders X-1, X, and X+1, respectively. A machine cycle, as employed in the time scale of this FIG., comprises a 5.5 microsecond period of time. A portion of an arbitrary cycle 1 and all of the following cycles 2 and 3 are shown. As seen in FIG. 65, the period of time between the transmission of the command to the Program Store 102 and the completion of the operational step associated with that command require greater than one 5.5 microsecond machine cycle. However, also as seen in FIG. 65, there are work functions relating to three separate orders being simultaneously performed; therefore, it is possible to complete single cycle orders at the rate of one order per 5.5 microsecond cycle.

At line X of FIG. 65 the code-address of order X is shown as being transmitted to the Program Store 102 during phase 1 of cycle 1 and the program store response thereto returned to the central Control 101 sometime during the latter portion of cycle 1 or the early portion of cycle 2. The program store response comprises parallel one-half microsecond pulses which represent the 44 bit program order word, the response synchronizing signal and the All Seems Well signal.

The exact time at which the program store response arrives at the Central Control 101 depends on central control response times, the lengths of the buses connecting the Central Control 101 and the Program Store 102 and the variations in the response times of the program stores of the Program Store System 102. These variations can result in the program store response arriving at the Central Control 101 as early as T19 of the same cycle in which the program store command was transmitted or as late as T6 of the following cycle. Accordingly, the Program Store Response Bus Selection Gates 1200 are activated by order cable signals on conductors PSBO and PSB1 (FIG. 12) in the period 19T8. This assures the acceptance of the full pulse width (approximately .5 microseconds) of the program store response. The Program Store Response Bus Selection Gates 1200 are selectively enabled to accept the response from the 0 bus 6500-0 or from the 1 bus 6500-1 of the Program Store Response Bus System 6500. The particular gates enabled are determined in accordance with the setting of the CPD controlled status and routing flip-flops, as enumerated in the earlier table. If the response is to be accepted over the 0 bus 6500-0, the AND-gates 1204, 1206, and 1208 are enabled by a signal on order cable conductor PSBO and if the response from the 1 bus 6500-1 is to be accepted, the AND-gates 1203, 1205, and 1207 are enabled by a signal on order cable conductor PSB1.

The 44 bit response word is transmitted through OR-gate 1209 and cable 1210 for insertion in the Auxiliary Buffer Order Word Register 1901 and the Buffer Order Word Register 2410. Bits 0 through 20 (the data-address field) and bits 37 through 43 (the Hamming encoding bits) are gated directly into the Buffer Order Word Register 2410 via AND gates 1907 and 1906, and OR gates 2428 and 2425, respectively. Bits 21 through 36 (the operation field) are inserted into the Auxiliary Buffer Order Word Register 1901 via AND gate 1905. The synchronizing signal is transmitted through OR gate 1211 and is employed to enable AND gates 1905, 1906, and 1907 which serve to gate the received 44 bit word to the Auxiliary Buffer Order Word Register 1901 and the Buffer Order Word Register 2410.

The All Seems Well Signal, if received from the 0 bus 6500-0, serves to set flip-flop 1214 to its 1 state and if received from the 1 bus 6500-1, sets the flip-flop 1213 to its 1 state. The flip-flops 1213 and 1214 comprise two of the inputs to the Error Detection and Correction Circuit 2400. Failure to receive an All Seems Well signal along with a program store response is an indication of possible trouble within the Program Store 102 therefore the validity of the response is in question. The All Seems Well signals summarize a number of hardware checks made within the Program Store 102, and the utilization of the All Seems Well signal as a maintenance tool is discussed later herein.

The data-address field and the Hamming encoding bits are gated directly to the Buffer Order Word Register 2410 as the portions of the register which are employed to store this information are no longer required by the immediately preceding order; however, the work operations with respect to the operation field of the preceding order may not have been completed by the time the program store response has arrived at the Central Control 101. Therefore the operation field is first inserted into the Auxiliary Buffer Order Word Register 1901 and then at time 6T8 by means of signal on order cable conductor AUBO (FIG. 19) is gated via AND gate 1900, cable 1903 and OR gates 2426, and 2427 to the Buffer Order Word Register 2410.

The information which is received both by the Auxiliary Buffer Order Word Register 1901 and the Buffer Order Word Register 2410 is on a single rail basis; therefore, both the Auxiliary Buffer order Word Register 1901 and all of the portions 2401, 2402, 2403 of the Buffer Order Word Register 2410 are selectively reset prior to the time of the inserting of new information. A signal on order cable conductor REBB (FIG. 24) at time 19T20 serves to reset the data address portion 2403 and the Hamming portion 2401 of the Buffer Order Word Register 2410 and to reset the Auxiliary Buffer Order Word Register 1901. An order cable signal on conductor REBA (FIG. 24) at time 3T5 serves to reset the operation field 2402 of the Buffer Order Word Register 2410.

In a few special instances (principally in the course of maintenance actions) a transfer may be made to one of a number of short sequences of program orders which are located in the Call Store 103. The program sequences in the Call Store 103 may be reached through a system interrupt or through a transfer. In either event, the call store code-address corresponding to the first program order word of the sequence is gated into the Index Adder Output Register 3401 and from there to the Call Store Transmit Bus Selection Gates 1000. The detailed control of the call store bus selection gates will be described with respect to the reading and writing of data from and into the Call Store 103. The call store, in response to a program order command, returns a 23 bit reading to the Central Control 101 via the Call Store Response Bus System 6501. This response is gated through the Call Store Response Bus Selection Gates 1300 to the Buffer Order Word Register 2410.

The Call Store 103 returns approximately one-half of a program order word with a single reading. Therefore, two successive call store locations must be read. Conveniently, the Program Address Register 4801 and the add-one circuit comprising the Add-One Register 4304 and the Add-One Logic 4305 are employed to obtain the second code-address and subsequently the code-addresses for the following program order words to be obtained from a Call Store 103. To provide protection against an unwanted response from a Program store 102 the call store code-addresses are not gated from the Program Address Register 4801 to the Program Store Address Bus System 6400.

The first call store word of a pair of words comprising a program order word is transmitted from OR gate 1309 via cable 1310, the right AND gate 1909, cable 1913 and the OR gates 2427 and 2428 to bits 22 through 0 of the Buffer Order Word Register 2410. The second call store word of the pair os transmitted from the OR gate 1309 via cable 1310, the left AND gate 1910, cable 1912 and the OR gates 2425 and 2426 to the bits 43 through 23 of the Buffer Order Word Register 2410. The reading of program order words from the Call Store 103 is most unusual. Two successive readings are required to obtain a single program order word. Therefore, the fetching of program order words from the Call Store 103 is under the control of the Call Store Program Sequencer 5302 which is described in greater detail later herein. It should be noted that Call Store Program order word responses are gated directly to the Buffer Order Word Register 2410 and not via the Auxiliary Buffer Order Word Register 1901. This simplification is permissible since the code-addresses for the next succeeding order are not transmitted until after the operational step for the preceding order has been completed.

DATA WORDS

As previously described, a large body of information organized as data words as opposed to program order words is stored principally in the Call Store 103 and the Program Store 102. The more volatile information is stored principally in the Call Store 103, while the more stable information is stored in the Program Store 102. Additionally, maintenance data which is stored internally in the control and access circuits of the Program Store 102, the Call Store 103, and the standby central control is treated as data for purposes of communication.

Data words may be read from a memory location or written into a memory location by the execution of program orders termed "memory orders." Includes in this term are "memory read orders" and "memory write orders." Memory orders cause the generation and transmission of commands to the various memory locations as follows: ##SPC4##

The above table shows that both memory read and memory write commands apply to many of the data memories; however, memory write commands cannot be employed with respect to the memory proper of the Program Store 102 nor can memory read commands be employed with respect to the standby Central Control 101.

CALL STORE MEMORY ORDERS

Memory reading (writing) orders which obtain (store) data from the Call Store 103 include call store reading (writing) commands as part of their operational step. The operational step of such orders is indicated by the example of order X in FIG. 65; in that example call store commands are generated and transmitted during phase 3 of the indexing cycle. If X is a memory reading order, the call store response will be transmitted from the Call Store 103 to the Data Buffer Register 2601 during phase 1 of the execution cycle; if X is a memory writing order, the word to be stored is transmitted from the Data Buffer Register 2601 to the Call Store 103 during phase 1 of the execution cycle. Call Store commands are also generated for multicycle orders under control of sequence circuits, but the command and data generation and transmission have the same format and relative time sequence as described below.

A call store command comprises:

A. 12 address bits AO through A11;

B. 6 code bits KO through K5;

C. 3 mode bits HM, GM, CM;

D. A first synchronizing bit Sync 1;

E. 2 order bits R and W;

F. 1 address parity bit;

G. A second synchronizing bit Sync 2.

The code bits KO through K5 define the block of information in which the selected call store data word is located and the address bits AO through A11 define the memory location within the above defined block of information. The code bits KO through K5 and the address bits AO through A11 comprise the call store code-address. The three mode bits specify the mode of operation of the Call Store 103 and the order bits specify whether the command is to read or to write. It should be noted that the Call Store 103 is always operated in the normal mode in the execution of memory read and memory write commands relating to call processing. The maintenance read and write commands and the control read and write commands are reserved for obtaining information from the Call Store 103 and writing into the Call Store 103 in the execution of special memory read and memory write orders relating to system maintenance. Pulses on the leads HM, GM, and CM specify the mode of operation of the Call Store 103 as follows: ##SPC5##

Pulses on the R and W conductors specify that the order is a call store read command or a call store write command, respectively.

The twelve address bits AO through A11, the six code bits KO through K5, and the address parity bit comprise a 19 bit segment of the command in which odd parity is maintained.

The first synchronizing signal Sync 1 accompanies the address, code, and mode bits and the second synchronizing signal Sync 2 accompanies the information on the R, W, and parity conductors. The synchronizing pulse S1 and S2 are employed as gating signals at the Call Store 103 and serve to reduce the time during which the Call Store 103 is vulnerable to noise signals on its command buses.

The execution of memory orders by Central Control 101 to move data words between the Call Store 103 and the Central Control 101 is initiated by the transmission of call store commands from Central Control 101 to the Call Store 103 via the Call Store Address Bus System 6401. If the command is to write a data word into the Call Store 103, then the command is followed by the transmission of the data word via the Call Store Write Data Bus System 6402. If the command is to read a data word, then the call store read command is followed by the transmission of the data word from the Call Store 103 to Central Control 101 via the Call Store Response Bus System 6501.

In executing a call store command the code-address is always composed in the Index Adder Output Register 3401 which is connected to the Call Store Transmit Bus Selection Gates 1000 via the cable 3402. Bits 17 through 12 of the index adder output register comprise the code portion of the command and bits 11 through 0 comprise the address portion of the command. The three mode bits, the synchronizing bits, and the read-write bits are all obtained from the Order Cable 3900. The three mode bits are required to be selectively other than zero in all modes other than the normal mode and in these modes the mode bits are defined by the program order word being executed. In all mode of operation the read and write bits and the synchronizing bits are also obtained from the Order Cable 3900 according to the call store command required.

The parity signal generated as part of the call store command is generated in the Index Adder Parity Generator 2415 in response to the code-address appearing at the outputs of the Index Adder Outputs Register 3401 and transmitted thereto via the cable 3402.

The Call Store Transmit Bus Selection Gates 1000 are divided into two groups, namely, those employed for transmitting to the 0 bus 1004 of the Call Store Address Bus System 6401 and those associated with the 1 bus 1003 of the Call Store Address Bus System 6401. The command information is selectively transmitted to the 0 bus 1004 or the 1 bus 1003 in accordance with the Call Store 103--Central Control 101 bus configuration which is being employed. That is, whenever information is being transmitted from the Central Control 101 to the Call Store 103 via the 0 bus 1004, AND gates 1006, 1008, 1012, 1014, and 1016 and amplifiers 1010, 1018 are employed; however, when commands are transmitted via the 1 bus 1003, AND-gates 1005, 1007, 1011, 1013 and 1015 and amplifiers 1009 and 1017 are employed. The address bits AO through A11 and the code bits KO through K5 are selectively transmitted through AND-gates 1016 and 1015 enabling order cable conductors ADRCSBO and ADRCSB1 (FIG. 10), respectively. Similarly, the mode bits HM, GM, and CM and the first of the two synchronizing pulses S1 are transmitted to the 0 and 1 buses under the control of the same order cable conductors. It should be noted that the order cable conductors ADRCSBO and ADRCSB1 are enabled at time 17T19. Order cable conductors RWCSBO and RWCSB1 are enabled at time 19T21 and serve to gate the READ, the WRITE, the ADDRESS PARITY and SYNC 2 pulses to their respective buses.

The Call Store Transmit Bus Selection Gates 1000 are selectively enabled in accordance with the setting of the central pulse distributor controlled status and routing register flip-flops AU, CBO, CBA, and CBT (FIG. 55). The state of flip-flop AU indicates which of the two central controls is active. The flip-flops CBO, CBA, and CBT (except for commands to read or write maintenance data) have the following significance: ##SPC6##

In the above table the X indicates that the standby CC is to send on neither the 0 nor the 1 bus as the active CC is engaged in transmitting to both buses.

The status and routing flip-flops AU, CBO, CBA, CBT are selectively set and reset by pulses from the Central Pulse Distributor 143 which are received via selected pairs of the Bipolar Cable 6700, the transformer 1707, amplifier 1708 and 1711, AND gates 1709 and 1712, and the CPD cable 1719.

CALL STORE WRITING COMMAND

A call store writing command utilizes as data to be stored a 23 bit word in the Data Buffer Register 2601. The outputs of the Data Buffer Register 2601 are transmitted via the cable 2606 to the Call Store Write Data Bus Selection Gates 1020, and from there to the selected one, or both, of the duplicated buses of the Call Store Write Data Bus System 6402. The selection of the 0 bus or the 1 bus for the transmission of data is determined by the appearance of signals on the order leads BRCSB0 and BRCSB1 (FIG. 10). The selection of signals on one, or both, of BRCSB0 and BRCSB1 is determined by the setting of the CPD controlled status and routing flip-flops as enumerated in the send column of the earlier table. In the execution of the call store command to write data into the memory signals appear on one or both, of BRCSBO or BRCSB1 during 5T7 following the transmission of the initial parts of the call store command onto the Call Store Address Bus System 6401. Accordingly, a synchronizing signal, S3, is transmitted via the amplifiers 1024 or 1023, and the 23 bit data word is transmitted via the AND-gates 1028 or 1027, and a data parity signal is transmitted via the AND gates 1026 or 1025.

THE D A PARITY GENERATOR (2609)

The 12 address bits A0 through A11, the 6 code bits KO through K5, the 23 bit data word DO through D22, and the data parity bit comprise a 42 bit command segment in which odd parity is maintained. The signal on the conductor DA PARITY (FIG. 26) is generated by the DA Parity Generator 2609 as required to maintain odd parity for call store writing commands. The Index Adder Parity Generator 2415 serves to examine the 18 bit segment of the command which comprises the 12 address bits and the 6 code bits and provides an appropriate output signal on conductor 2418. If the parity of the code-address bits at the input of the Index Adder Parity Generator 2415 are even, a signal will appear on conductor 2418; however, if the parity of these bits is odd, there will be no signal on conductor 2418. Conductor 2418 thus serves to summarize the parity of the code-address bits and is employed as an input signal to the DA Parity Generator 2609 along with the data bits at the output of the Data Buffer Register 2601. All 24 bits of the Data Buffer Register 2601, that is, bits 0 through 23, are connected to the input of the DA Parity Generator 2609; however, the 24th bit which appears in the Data Buffer Register 2601 is always a zero as stage 23 is reset at time 21T1 by enabling cable conductor REBRP (FIG. 26). Summarizing, in executing a call store writing command the DA Parity Generator 2609 provides the data parity signal on conductor DA PARITY which is transmitted along with the data from the output of the Data Buffer Register 2601 via cable 2606 to the Call Store Write Data Bus Selection Gates 1020.

The DA Parity Generator 2609 is also employed in the execution of call store reading commands which either (1) obtain a data word and store that word in the Data Buffer Register 2601, or (2) obtain a transfer code-address which is placed in the Buffer Order Word Register 2410. In the case of indirect addressing bits 0 through 22 of the Buffer Order Word Register 2410 and the state of the Parity Flip-Flop 1911 are employed as the input signals to the DA Parity Generator 2609. An order cable signal on conductor CSDACK (FIG. 26) serves to substitute these conductors for the contents of the Data Buffer Register 2601. In checking a call store response for data readings the contents of the Data Buffer Register 2601 serve as the input information to the DA Parity Generator 2609.

ALL SEEMS WELL SIGNALS

In response to call store commands (both reading and writing), the Call Store 103 executes the command and, upon the successful completion of the execution responds by transmitting All Seems Well and synchronizing signals via the Call Store Response Bus System 6501 to Central Control 101. These signals are transmitted via Cable Receivers 1302 and 1301 (according to their appearance on the 0 bus 6501-0 or 1 bus 6501-1, respectively) to conductors SYNCO, AWSO, and SYNC1 and ASW1 (FIG. 13). The synchronizing and All Seems Well signals appearing at the inputs of AND gates 1308 and 1307 generate corresponding signals to set the flip-flops 1314 and 1313. Since the All Seems Well and the synchronizing signals are provided on a single rail basis, these flip-flops are previously reset in preparation by enabling order cable conductor RECER. The All Seems Well signals summarize a number of hardware checks which are made within the Call Store 103; the utilization of these signals as a maintenance tool is discussed later herein.

CALL STORE READING COMMANDS

In the execution of call store reading commands the response includes a 24 bit word of data, an All Seems Well signal, and a synchronizing signal appearing as one-half microsecond pulses on the Call Store Response Bus System 6501. The 24 bit word includes 23 bits of information to be utilized for data processing within Central Control 101 and a data parity bit. The call store response signals appear in parallel at the input terminals of the Call Store Response Bus Selection Gates 1300. The Call Store Response Bus Selection Gates 1300 are selectively enabled to accept the response from the 0 bus 6501-0 or from the 1 bus 6501-1, and the gates enabled are determined in accordance with the setting of the CPD control status and routing flip-flops as enumerated in the earlier table. If the response is to be accepted from the 0 bus 6501-0, the AND-gates 1304 and 1306 are enabled by a signal on order cable conductor CSBO and if the response from the 1 bus 6501-1 is to be accepted, the AND gates 1303 and 1305 are enabled by a signal on conductor CSB1.

Signals on order cable conductors CSBO and CSB1 occur at time OT11.

In FIG. 65 it is indicated that within Central Control 101 the data processing of reading from a memory other than a Program Store 102 occurs in phase 2 during the execution cycle and with the Call Store Response Bus Selection Gates 1300 enabled for the time OT11 the call store response is returned prior to this time, that is, it is returned during phase 1 during the execution cycle. It should be noted that the Call Store Response Bus Selection Gates 1300 are enabled for a period of time which greatly exceeds the period, i.e., one-half microsecond of the call store response signals. This greater period of time permits acceptance of the full pulse width (approximately .5 microseconds) of the call store bus response signals without regard for variations in time of response of the Call Store 103 and variations in length of cable connecting the Call Store 103 and the Central Control 101.

The 24 bit response word is transmitted through OR gate 1309, cable 1310, and AND gate 2102. The synchronizing signal is similarly transmitted to AND gate 2102. When the call store response is to be placed in the Data Buffer Register 2601 the gating of data readings from the Call Store Response Bus System 6501 via AND gate 2102 and OR gate 2106 is controlled by enabling order cable conductor CSBR (FIG. 21).

The information which is received both by the Data Buffer Register 2601 and the special flip-flops 1313 and 1314 is on a single rail basis; therefore, the Data Buffer Register 2601 and the special flip-flops 1313 and 1314 are reset prior to the time at which the information is received. Enabling order cable conductors REBR and REBRP (FIG. 26) resets the Data Buffer Register 2601, and a signal appearing on the order cable conductor 13RECER resets the special flip-flops 1313 and 1314. Both of these signals occur during OT1 prior to the receipt of information from the Call Store Response Bus System 6501.

CALL STORE ERROR DETECTION CIRCUIT 2200

In the performance of obtaining data from the Call Store 103 for memory reading orders the DA Parity Generator 2609 is utilized to check the parity of the data received and the address transmitted to obtain that data. The state of conductor 2418 indicates the parity of the 18 bit code-address, and the contents of the Data Buffer Register 2601 including the 24th bit comprise the remaining inputs to the DA Parity Generator 2609. The parity of the returned data and the address which was employed in obtaining that data should be odd. In the event of failure of parity, a signal on the PF conductor 2607 is transmitted to the Call Store Error Detection Circuit 2200.

The Call Store Error Detection Circuit 2200 serves to summarize the hardware checks which are made in carrying out call store commands. The input signals to the Call Store Error Detection Circuit 2200 comprise the call store synchronizing signal conductors CSS1 and CSSO (FIG. 13), the call store All Seems Well conductors ASWCSO and ASWCS1, the Parity Failure conductor 2607 and order cable conductor CSCK, and READCK (FIG. 22) The Call Store Error Detection Circuit 2200 is enabled by a signal on order cable conductor CSCK and if the parity check of a data reading is to be made order cable conductor READCK (FIG. 22) is also enabled. If one or more of the hardware checks enumerated above fails, the Call Store Error Detection Circuit 2200 enables output conductor CERI (FIG. 22). A signal on conductor CERI sets the CSEI flip-flop 2201 which in turn activates the Call Store Reread Sequencer 5700, the operation of which will be described later herein. The AND-gate 2700 is enabled by a signal on order cable conductor CSX and serves to transmit to the other terminal control the error indication on conductor CERI. The Call Store Error Detection Circuit 2200 is enabled for normal call store memory commands; it is not enabled for maintenance and control read and write commands.

PROGRAM STORE MEMORY ORDERS

Memory reading orders may also address memory locations within the Program Store 102. In such instances the indexing step produces a code-address corresponding to a program store memory location to be read. Memory reading orders for obtaining the data from a Program Store 102 utilize the same channels for addressing the store and for receiving the response employed in obtaining program order words. When data is to be read from a Program Store 102 the Data Reading Sequencer 4903 is activated. The sequencer is required since the obtaining of data from a Program Store 102 must be interleaved with the obtaining of program order words. Accordingly, this sequencer responds by storing the code-address of the next program order word temporarily in the Add-One Register 4304 and placing into the Program Address Register 4801 the data code-address by gating the outputs of the Index Adder Output Register 3401 thereto. The Data Reading Sequencer 4903 extends the processing time of a memory reading order by two 5.5 microsecond cycles. These two cycles are inserted in the operational step as set forth in FIG. 65 at the end of the indexing cycle and before the execution cycle. In the first cycle injected by the Data Reading Sequencer 4903 the order following the memory reading order is ignored and the data code-address is transmitted to the Program Address Register 4801. From there this code-address is transmitted as part of a program store command onto the Program Store Address Bus System 6400. In the second machine cycle injected by the Data Reading Sequencer 4903 the data reading is returned from the Program Store 102 via the Program Store Response Bus System 6500 to the Buffer Order Word Register 2410. From there a selected half of the 44 bit data reading is transmitted to the Data Buffer Register 2601, the selected half determined by bit 20 of the code-address formed in the indexing step of the order. When these functions are completed the Data Reading Sequencer 4903 is returned to the inactive state, and the memory reading order proceeds to its execution cycle wherein the data (now appearing in the Data Buffer Register 2601) is utilized to complete the operational step.

AUXILIARY BUFFER REGISTER MEMORY ORDERS

Memory reading and writing orders may also address a selected one of the auxiliary buffer registers such as DRO (3118), ARO (3105) (FIG. 31), DR1 (3617) (FIG. 36), et cetera. In such instances the DAR word is a code-address corresponding to the selected one of the auxiliary buffer registers. This code-address appears in the Index Adder Output Register 3401 and is utilized to transmit data from the Data Buffer Register 2601 to a selected one of the auxiliary buffer registers for memory writing orders or to transmit data from a selected one of the auxiliary buffer registers to the Data Buffer Register 2601 for memory reading orders.

A memory reading order which addresses a selected one of the auxiliary buffer registers selects by means of a signal appearing on one of the order cable leads ARO-BR, DRO-BR (FIG. 31), AR1-BR (FIG. 36), et cetera, to transmit the contents of a selected one of the auxiliary buffer registers via the AND gates 3108, 3120, 3608, et cetera, via the Buffer Register Input Bus 3209 and the OR gate 2106 to the inputs of the Data Buffer Register 2601. This gating action occurs during OT8 (phase 1) of the execution cycle.

Memory writing orders which place data into a selected one of the auxiliary buffer registers utilize the contents of the Index Adder Output Register 3401 to generate a signal on a selected one of the order leads BR-ARO, BR-DRO, BR-AR1, et cetera, to transmit the contents of the selected one of the registers via the Data Buffer Register 2601 and the Buffer Register Output Bus 2600 to a selected one of the AND-gates 3103, 3116, 3601, et cetera, to the inputs of the selected one of the auxiliary buffer registers ARO, DRO, AR1, et cetera. In that certain of the auxiliary buffer registers 3105, 3118, 3605, and 3617, have a 24 bit capacity as opposed to the 23 bit length of data words as processed within Central Control 101, the additional bit is provided in one of the bits of the indexed code-address as it appears in the Index Adder Output Register 3401.

The address which selects the particular auxiliary buffer register for reading or writing appears in bit positions 1 through 5 of the Index Adder Output Register 3401 during the execution of the memory order. When a memory writing order specifies a 24 bit auxiliary buffer register, then bit 0 of the code-address appearing in the Index Adder Output Register 3401 serves as the 24th bit of data. Order cable conductor 23 or 23 of cable 2611 is enabled according to contents of the least significant bit of the Index Adder Output Register 3401 thereby supplying the 24th bit of data on the Buffer Register Output Bus 2600. The 24th bit of this bus is transmitted whenever a memory writing order specifies one of the Match Registers ARO, AR1, DRO and DR1 (FIGS. 31, 36).

Memory writing orders which place data into a selected one of the auxiliary buffer registers utilize the contents of the Index Adder Output Register 3401 to generate a signal on a selected one of the order leads BR-AR0, BR-DR0, BR-AR1, et cetera, to transmit the contents of bits 0 through 22 of the Data Buffer Register 2601 via the cable 2600 to a selected one of the AND gates 3103, 3116, 3601, et cetera, to the inputs of the selected one of the auxiliary buffer registers AR0 3105, DRO 3118, AR1 3605, et cetera.

COMMUNICATION VIA COMMAND ORDERS

The third major class of communication involves the generation and transmission of "commands" to the Central Pulse Distributor 143, the Switching Network 120, the Master Scanner 144, et cetera. These commands are employed in controlling the noted units in the performance of both telephone and maintenance functions.

The Central Control 101 utilizes program orders designated herein as "command" orders to generate such commands. Certain of these orders generate commands to be transmitted only to the Central Pulse Distributor 143; these orders are designated herein as "CPD orders" and the commands associated with these orders are designated as "CPD commands." Other command orders generate information on the Network Command Bus 6406; these are designated as "network command orders" and the generation of information on the Network Command Bus 6406 is designated herein as "network commands." Network command orders are utilized to transmit information to not only the Switching Network 120 but to all units connected to the Central Control 101 via the Network Command Bus 6406 such as the Master Scanner 144, the Teletype Unit 145, et cetera. For convenience these units which are controlled by way of the Network Command Bus System 6406 are termed "Network Command Units" herein. The network command order employs the CPD command to designate a particular network command unit which is to respond to the network command.

In that the Central Pulse Distributor 143 is employed in the execution of both CPD orders and network command orders, communication with the Central Pulse Distributor 143 will be described first. The Central Pulse Distributor 143 is a high speed electronic translator which provides two classes of output signals in response to CPD commands. The first class of output signals is termed unipolar signals and the second class is termed bipolar signals. Commands are transmitted from the Central Control 101 to the Central Pulse Distributor 143 in the form of half microsecond pulses. The information required to control a Central Pulse Distributor 143 is transmitted in three successive waves which are each separated by 1.25 microseconds. The bus choice information which indicates that the central pulse distributors are to accept information from either the 0 or 1 bus of the CPD Address Bus System 6403 is transmitted in the first wave to all central pulse distributors via the CPD Bus Choice Bus 6405. This bus choice information is determined by the state of flip-flops CPDB (FIG. 59) and OL1 (FIG. 55) as described subsequently herein. The second wave consists of the CPD address transmitted on a selected 0 or 1 bus of the CPD Address Bus System 6403 to all central pulse distributors. The CPD address consists of signals which are to be translated by the Central Pulse Distributor 143 into a half microsecond output pulse appearing on a selected unipolar or bipolar output. The third wave consists of a half microsecond execute pulse transmitted on one of a plurality of cable pairs in the Execute Cable 6404. Corresponding to each cable pair in the execute cable is a discrete unit of the Central Pulse Distributor 143, and the execute pulse serves to select the unit which is to carry out the translation of the CPD address signals. The central pulse distributor units which do not receive the execute pulse do not carry out this translation, and the third wave serves thereby as part of the translation of the coded data within Central Control 101 into a pulse appearing on a selected discrete unipolar or bipolar output of the Central Pulse Distributor 143.

The operational step of command orders includes the information of data to specify the CPD address, the CPD execute signal, and/or the network command information. If, for example, the order X in FIG. 65 is a command order, the data is placed in the appropriate flip-flop registers within Central Control 101 during phase 2 of cycle 3, and accordingly the second and third wave information is generated only after this data is so registered. The generation of the three waves of CPD command information for the order X is correspondingly generated during 10T12, 15T17, and 20T22 of cycle 3.

The Central Pulse Distributor 143 in executing commands returns responses to the Central Control 101 as half microsecond pulses; the time of arrival of these pulses at Central Control 101 is dependent on the response time of the Central Pulse Distributor 143 and the lengths of the buses connecting the Central Control 101 and the Central Pulse Distributor 143. In the example of FIG. 65 gating signals lasting from T19 of cycle 3 until T12 of cycle 4 (a 3.75 microsecond span) are employed to gate these responses of the Central Pulse Distributor 143. It may be noted that this last gating action as well as the transmission of the second and third waves of the CPD command are generated after the order X has been replaced by the orders X+1 and X+2 in the Central Control 101; the Command Order Sequencer 4902 is therefore activated in the execution of the order X to carry out those gating actions.

If the order X is a network command order, the Command Order Sequencer 4902 is also employed to carry out the gating actions associated with the CPD command, and further the gating actions associated with the transmission of address information to the network command bus. In the execution of network command orders the network command unit returns responses to the Central Control 101 within a span of time that may extend to T5 of cycle 5. Accordingly, the Command Order Sequencer 4902 remains active to carry out all of the gating actions of the network command order which may extend to the end of phase 1 of cycle 5. It is with the aid of the Command Order Sequencer 4902 that the Central Control 101 extends the degree of overlap beyond that exhibited in FIG. 65. If the order X is a network command order, then gating actions associated with the operational step of order X will be simultaneously occurring with the execution cycle of the order X+2, at the time the order X+3 is arriving at the Buffer Order Word Register 2410, and at the time the address of the order X+4 is being transmitted on the Program Store Address Bus System 6400.

CPD COMMAND GATING ACTIONS

The choice of the 0 or 1 of the CPD address bus system is made according to the state of special flip-flops CPDB (FIG. 59) and OL1 (FIG. 55) within the Central Control 101. These flip-flops are set and reset under control of program sequences to indicate the routing of CPD address information as indicated in the following table: ##SPC7##

In the above table the entry X indicates that the command is transmitted on neither bus. According to the choice of bus, signals appear on one of the order cable conductors BCO or BC1 (FIG. 38) during 10T12 and are transmitted via the Cable Driver 3801 to the Bus Choice Bus 6405.

Signals to select a unipolar or bipolar output (the CPD address) are generated either by the CPD translator 5422 in response to the binary representation of the CPD address appearing in a portion of the First-One Register 5801 or (according to the command order) the CPD address is generated directly from outputs of portions of the K Register 4001 and the KA Input Register 3502. The CPD translator 5422 is employed in most instances; the outputs of the K Register 4001 and the KA input Register 3502 are used in transmitting special test or control signals to the Central Pulse Distributor 143.

A signal appearing on the order cable lead CPDA (FIG. 54) causes the CPD translator 5422 to generate the CPD address on the output conductors 5425 which is transmitted to the OR gate 4004 onto a second bus 4005 and from there to the input of the CPD Transmit Bus Selection Gates 3812. The CPD address is in this instance determined by the contents of bit positions 9, 14--22 of the First-One Register 5801 which are transmitted to the CPD translator via connecting cable 5810. Here the "bus choice" is implemented by the appearance of a signal on AOB or A1B (FIG. 38) during 15T17 to transmit the CPD address via the AND gates 3814 and 3815 and the Cable Driver 3802 to the 0 bus 3804 or via the AND-gates 3816 and 3817 and the Cable Driver 3803 to the 1 bus 3805.

A signal appearing on the order cable conductor 3810 and signals appearing on the output conductors 7, 8 and 9 of the First-One Register 5801 indicates the alternative of deriving the CPD address or special signals TEST or RESET (FIG. 38) from information contained in portions of the K Register 4001 and the KA Input Register 3502. The outputs of the K Register 4001 and the KA Input Register 3502 are gated via the buses 4006 and 3519, the AND-gates 4002 and 4003 (and in part via the OR-gate 4004) to the bus 4005. From there the gating of the CPD address, TEST and RESET signals to the CPD Address Bus System 6403 is as previously described.

The third wave of information is generated by the appearance of a signal on CPDX (FIG. 54) during 20T22; the execute signal appears on one of the conductors 5426 according to the contents of bit positions 10 through 13 of the F Register 5801. The execute signal is transmitted via the conductors 5426 and the Cable Driver 3800 to the CPD Execute Cable 6404.

In the execution of CPD commands the bipolar output signals are in some instances accompanied by a synchronizing security signal (WRMI). In such instances the CPD command utilizes the outputs of the CPD translator 5422 and the appearance of the synchronizing security signal is specified by the appearance of a 1 in bit position 8 of the First-One Register 5801. if the synchronizing security signal is so specified, a pulse appears during 20T22 on order cable conductor CPD INPUT SYNC (FIG. 38) and is transmitted through the Cable Drivers 3806 and 3807 to both the 0 bus 3808 and the 1 bus 3809 of the CPD Input Sync Bus System 6702.

In response to the bus choice, CPD address, and execute signals the Central Pulse Distributor 143 generates an output pulse on the selected unipolar or bipolar output point. In addition, the Central Pulse Distributor 143 generates maintenance signals that are transmitted to the Central Control 101 to permit a check on the execution of the CPD command. These signals comprise the execute response signals transmitted via the Execute Response Bus System 6502, an All Seems Well signal transmitted via the CPD Verify Bus System 6704, and CPD maintenance signals transmitted via the CPD Maintenance Response Bus 6904.

The execute response signals appear as half microsecond pulses on the Execute Response Bus 6502 and are transmitted through the Cable Pulse Receivers 1600. Signals appearing on the order cable conductor CPDEW (FIG. 16) during 19T12 (a 3.75 microsecond interval from time T19 of one machine cycle to time T12 of the following machine cycle) transmit the execute response through AND-gate 1601 to the CPD Execute Response Cable 1605 and the set inputs of bit positions 0 through 15 of the Command Order Maintenance Summary Register 6205. The All Seems Well signal is returned to the Central Control 101 via the 0 bus or 1 bus of the CPD Verify Bus System 6704 and the Cable Receivers 1502 or 1501. A signal appearing on CPDEW (FIG. 15) serves to transmit these All Seems Well signals through the AND gates 1506 and 1505 and the OR gate 1509 of the CPD Verify Bus Selection Gates 1500 to conductor 1510 of the Error Summary Cable 1218. The further appearance of the same signal on order cable conductor CPDEW (FIG. 62) transmits the All Seems Well signal from the Error Summary Cable 1218 and the bus 6200 through the AND gate 6203 to the set input of the flip-flop 62ASW CPD.

The maintenance response of a Central Pulse Distributor 143, appearing as the signals APAR, BPAR, CPAR, and M1 (FIG. 16), is returned via the CPD Maintenance Response Bus 6904 and the Cable Receiver 1603 to the Error Summary Cable 1218. From there these signals are transmitted as previously described to the set inputs of the flip-flops PCA, PCB, PCC, and MCE, respectively.

The execute response signals, the All Seems Well signals, et cetera, appear on the Error Summary Cable 1218 and the CPD Execute Response Cable 1605 as single rail half microsecond pulses sometime within the previously defined 3.75 microsecond interval 19T12. Accordingly, bits 0 through 21 of the Command Order Maintenance Summary Register 6205 are reset prior to this interval by the appearance of a signal on the order cable conductor RCPD (FIG. 62) during 17T19.

CPD COMMAND HARDWARE CHECKS

In the execution of CPD commands the proper response of the Central Pulse Distributor 143 includes the transmitting of the All Seems Well signal to Central Control 101 and the transmission of execute response signals which match the execute signals sent in the third wave of the CPD command. Accordingly, the command order sequencer interrogates the flip-flop ASW CPD (FIG. 62) and the output of the Execute Match Circuit 5033 sometime after the 3.75 microsecond interval 19T12 in which the execute response and All Seems Well information appear. The Execute Match Circuit 5033 compares the signals appearing on the conductors 5424 (the execute signals appearing at the output of the CPD translator 5422) and the signals appearing on conductor 6210 (the execute response as registered in bits 0 through 15 of the Command Order Maintenance Summary Register 6205). If a match occurs, a signal appears on the conductor EXM (FIG. 20), and if the All Seems Well signal is returned to Central Control 101, a signal appears on ASW CPD (FIG. 62). Failure of Signals to appear on these leads causes the Command Order Sequencer 4902 to set the flip-flop PUEI (FIG. 52) which results in ensuing maintenance program designated to determine the nature and location of the trouble.

The response of the Central Pulse Distributor 143 stored in the flip-flops MCE, PCA, PCB, and PCC (FIG. 62) are not examined by the Command Order Sequencer 4902, but serve as additional maintenance information in the event of troubles indicated by improper execute response signals or the failure of the appearance of an All Seems Well signal.

NETWORK COMMAND GATING ACTIONS

The operational step of network command orders include the generation of a network command on cable 3516 and the transmission of these signals through the Network Command Transmit Bus Selection Gates 2800 to the Cable Drivers 2804 and 2805 and the bus 0 2806 and bus 1 2807 of the Network Command Bus System 6406. If the order X in FIG. 65 is a network command order, then signals appearing on NCTBO or NCTB1 (FIG. 28) during 4T6 of cycle 4 (not shown in FIG. 65) transmits the command to the or 1 bus, respectively, of the Network Command Bus System 6406. The selection of the duplicate bus for transmission is controlled by the state of the flip-flops OL2 (FIG. 55) and bit position 14 of the First-One Register F14 as indicated in the following table: ##SPC8##

In the above table the entry X indicates that the command is transmitted on neither bus.

The network command generated on the cable 3516 is obtained from portions of the contents of either the KA input Register 3502 or the K Register 4001 and the K A Input Register 3052 depending on the command order being executed and the contents of bit positions 7, 8, and 9 of the First-One Register 5801. That is, according to the combination of signals on 7, 7, 8, 8, 9, and 9 conductors of cable 5811 and the state of order cable conductors 10, FINH, and SR (FIG. 35), the network command is obtained from:

1. Portions of the KA Input Register 3502 via AND gates 3511, 3512 and OR gates 3514, 3515;

2. Portions of the K Register 4001 and the KA Input Register 3502 via AND gates 3513, 3511 and OR gates 3514, 3515; or

3. From portions of the KA Input Register 3502 via the command Translator 3509 and OR gates 3515.

In the last instance, signals on cable 5811 further select the portion of the KA Input Register 3502 that are translated and the translation to be employed.

Whenever a network command is generated it is simultaneously transmitted to all network command units. The CPD command performed in the execution of a network command order serves to select which of the network command units is to execute the network command. Associated with each of the network command units are distinct unipolar outputs of the Central Pulse Distributor 143. A pulse appearing on a selected one of these unipolar outputs causes the corresponding network command unit to execute the transmitted network command. In carrying out this network command certain of the network command units transmit responses to the Central Control 101. These responses may include verify signals transmitted on the CPD Verify Bus System 6704 and data transmitted on the Scanner Answer Bus System 6600. With reference to FIG. 65, if the order X is a network command order, these responses appear as half microsecond signals within a 6.25 microsecond span of time beginning with T4 of cycle 4 and ending with T7 of cycle 5. The time interval is designated herein as 4T29 to emphasize that the time interval is in excess of one machine cycle.

The enable verify signals appear on the 0 bus 6704-0 or 1 bus 6704-1 of the CPD Verify Bus System 6704 and are transmitted via the Cable Receivers 1502 and 1501, respectively, to the CPD Verify Bus Selection Gates 500. Accordingly, signals appearing on the order cable conductors CPDBO or CPDB1 (FIG. 15) during 4T29 serve to transmit the CPD verify signals through the AND gate 1504 or 1503 and the OR gate 1507 to the cable 1508. Single rail signals appearing on the bus 1508 are thereby transmitted to the set inputs of the Y Register 3001 via the AND gate 3004 and the OR gate 3005. A signal on order cable conductor VBYR (FIG. 30) enables AND gate 3004. The CPD verify signals so placed in the Y Register 3001 must be identical in form to the CPD address appearing on the output leads 5423 of the CPD Translator 5422. The leads 5423 and the outputs of the Y register (transmitted on the cable 3013) are inputs to the Enable Verify Match Circuit 5027. In the performance of network commands orders for which the CPD verify signals are to be placed in the Y Register 3001 the Command Order Sequencer 4902 interrogates the output of the Enable Verify Match Circuit 5027 upon the receipt of the CPD verify signals. This interrogation serves as a check on the proper operation of the network command; if improper operation is indicated by a mismatch, this mismatch information appearing on the lead EVM is transmitted under control of the Command Order Sequencer 4902 to set the interrupt source flip-flop PUEI (FIG. 52). The setting of this flip-flop may lead to an ensuing interrupt program designed to determine the circuit trouble causing the detected improper operation.

The selection of the 0 bus or the 1 bus as determined by the appearance of signals on the order cable leads CPDBO or CPDB1 (FIG. 15) are determined by the state of flip-flop CPDB (FIG. 59). This flip-flop serves to indicate the state of connections of the CPD Verify Bus System 6704 and indicates that the 0 bus is to be used if the flip-flop is reset, otherwise the 1 bus is to be examined for CPD verify signals.

The operational step of certain of the network command orders results in the returning of data on the Scanner Answer Bus System 6600 to the Central Control 101. In such instances gating signals under the direction of the Command Order Sequencer 4902 transmit scanner answers from the 0 bus 6600-0 or 1 bus 6600-1 through the Scanner Answer Bus Selection Gates 1400 onto the bus 1408 through the AND gate 2100 to the inputs of the Logic Register 2508. The 0 bus 6600-0 or 1 bus 6600-1 is examined by the appearance of signals on the order cable lead SCAO or SCA1 (FIG.14), respectively, during 4T29. The scanner answer is transmitted through the AND gate 1404 or 1403 and the OR gate 1407 to the bus 1408. The simultaneous appearance of a signal on the order lead SCLR (FIG. 21) transmits these single rail signals through the AND gate 2100 to the set inputs of the Logic Register 2508.

The selection of the 0 bus or 1 bus is determined by the states of flip-flops AU (FIG. 55), SCBA and 59SCBB according to the following table. ##SPC9##

In the execution of network command orders on All Seems Well signal is returned in some instances via ASWO or ASW1 of the Scanner Answer Bus System 6600. This signal serves to indicate the proper response to the command by the selected network command unit. In such instances a signal on order cable conductor SCAO or SCA1 (FIG. 14) transmits the All Seems Well signal through the AND gates 1406 or 1405 and the OR gates 1409 to the Error Summary Cable 1218. The All Seems Well signal is thereby transmitted to the set input of the flip-flop ASWS (FIG. 62). When specified by a network command order being executed, the output of the flip-flop ASWS is interrogated by the Command Order Sequencer 4902 to determine the appearance of the All Seems Well signal; if this signal is not so registered in the flip-flop further gating actions are undertaken by the Command Order Sequencer 4902 which lead to an ensuing interrupt program to examine the system for the cause of the trouble.

The CPD verify signals, and information returned on the Scanner Answer Bus System 6600 appear as single rail half microsecond pulses which are to set selected flip-flop registers within Central Control 101. To prepare for the reception of such single rail information the corresponding flip-flop registers are previously reset. If information is to be transmitted from the Scanner Answer Bus System 6600 to the Logic Register 2508, then a signal appearing on the order lead RELR (FIG. 25) during 4T6 of cycle 4 resets that register. Similarly, signals appearing on order cable leads REYR (FIG. 30) and RASWS (FIG. 62) provide the initial resetting of the Y Register 3001 and the flip-flop ASWS (FIG. 62)

CROSS-CONNECTION OF ERROR SIGNALS IN CENTRAL CONTROL 101

The Central Control 101 is duplicated, and at any time one of the two units is designated the "active unit" and the remaining unit is referred to as the "standby unit." The active unit serves to execute all of the call processing and most of the maintenance program sequences. That is, in most instances the control of the telephone switching system emanates from the execution of program sequences within the active central control unit; the standby central control unit may also be executing the same program sequences, but the standby central control unit does not transmit CPD commands or network commands and therefore has no direct influence in the operation of the telephone switching system.

When difficulties in the operation of the Central Processor 100 are detected by one of more of hardware or program checks remedial maintenance programs are called in which may determine that the difficulty lies within the active central control unit. If this is the case the Emergency Action Sequencer 5702 or a program sequence executed in the active central control "switches" the units. That is, the active central control unit is made to be the standby unit, and the standby central control unit is simultaneously designated the active unit. This switch is made by a CPD command which simultaneously changes the states of the CPD command which simultaneously changes the states of the CPD controlled status flip-flops AU (FIG. 55) in both central control units. The state of this flip-flop places its central control in the standby or active state. By resetting flip-flop AU an active central control is switched to the standby state.

In the absence of trouble the various duplicate units (the Central Control 101, the Program Store 102, the Call Store 103, and connecting address and response bus systems) may be assembled into two distinct or partially shared duplicates of a central processor. The active central control unit is the nucleus for an "Active Central Processor," and the standby central control serves in the "Standby Central Processor." The duplicate central processors are advantageously used in our system in two modes. The first mode is the running of the duplicate central processors in "step." That is, both active and standby central processors are executing the same program sequences (from the same or duplicate program store units), reading and writing data (from the same or duplicate call store units), but only the active central processor is controlling the Central Pulse Distributor 143 and the network command units. In the second mode of operation the active central processor is carrying on the call processing function using one set of program sequences while the standby central processor is performing diagnostic exercises utilizing different program sequences and only "unshared" units of the duplicate central processors.

In the first mode the execution of program sequences in duplicate within the Central Processor 100 is employed to detect the occurrence of circuit troubles therein by periodically matching strategic data processing modes in both central control units. (In this embodiment two pairs of words are matched per 5.5 microsecond cycle.) The nodes matched include the Unmasked Bus 2014, the Masked Bus 2011, the Index Adder Output Register 3401, and the Data Buffer Register 2601, the Program Address Register 4801, the Buffer Order Word Register 2410, and sequencer test points.

When circuit troubles occur in one central processor unit and cause the data processing to be altered this alteration results in a mismatch of two like nodes in the duplicate central processors. The detection of the mismatch will lead to a maintenance interrupt and program sequences designed to determine the unit in trouble. It should be noted that the matching scheme works only if the duplicate program sequences are running in step. That is, if the execution of one program sequence falls behind its "twin," then mismatches of like nodes may occur as a result of different data processing steps rather than circuit troubles. The result would be the occurrence of the C level maintenance interrupt leading to the above-mentioned program sequences which is not only unnecessary but also may cause subscriber dissatisfaction by a lengthy interruption of call processing to execute exhaustive program sequences which search for a nonexistent trouble.

As previously indicated, there exist partially or wholly independent "loops" of communication between the two central control units and two or more units in the Program Store 102 and/or the Call Store 103. It is therefore possible that an error be generated in one such loop while no corresponding error occurs in the duplicate loop. For example, one central control unit may detect an error in reading program words or data while the second unit receives a valid word of program or data. In such instances one central processor unit inserts one or more 5.5 microsecond cycles to correct or reread the program or data word; to keep the two program sequences in step, for purposes of matching, the duplicate unit must also insert the same one or more 5.5 microsecond cycles. The duplicate central processors are kept in step by the "cross-connecting" of error information so that correction or rereading actions are initiated in both central processors in response to hardware troubles detected in either duplicate central processor. That is, when one central control unit detects a failure of one or more hardware checks in reading or writing words in the Program Store 102 or the Call Store 103 or in executing a CPD command and/or a network command, the information is transmitted to the second central control unit. A similar transmission of information from the second central control unit to the first is included to provide the "cross-connection."

This cross connection of trouble information is only relevant when the two central controls are running in step. When the central processors are executing independent programs matching is dropped. In this independent mode trouble information transmitted from one central control unit to another is irrelevant and must be ignored. This is accomplished by setting the CPD controlled status flip-flop DI (FIG. 55) which, as described below, disables the cross connection.

The hardware check of program or data words read from the Program Store 102 by the Central Control 101 is performed in the Error Detection and Correction Circuit 2400. Checks are also made therein of program words obtained from the Call Store 103. When a correctable error is detected, a signal appears on the I Correct conductor 2420; when an error requiring a rereading is detected, a signal appears on the I Reread conductor 2421.

A signal appearing on conductor 2420 sets the I correct flip-flop 2312, and a signal on conductor 2421 sets the I Reread flip-flop 2313. The flip-flops 2312 and 2313 serve as the indication of hardware check failures within the central control unit. The setting of either of these flip-flops results in a signal being transmitted through the OR gate 2317 and the conductor 2322 to the Error Detection and Correction Circuit 2400 which in turn generates signals leading to the required actions of correcting or rereading.

Signals appearing on conductors 2420 and 2421 are transmitted through the AND-gates 2302 and 2303, respectively, by the appearance of a signal on order cable conductor PSX (FIG. 23) during 12T14 of the 5.5 microsecond cycle in which the program store reading is being checked. These signals are thereby transmitted as half microsecond pulses through the Cable Drivers 2304 and 2305 and the bus 2300 to the other central control unit. The bus 2300 in each central control unit is the bus 2301 in the other central control unit; the half microsecond signals corresponding to conductors 2420 and 2421 generated in one central control unit appear on the bus 2301 of the other central control unit and are transmitted via the Cable Receivers 2310 and 2311 to the set inputs of the E Correct flip-flop 2314 and the E Reread flip-flop 2315, respectively. The setting of either the E Correct or E Reread flip-flops causes a signal to be transmitted via the OR gate 2317 and the conductor 2322 to the Error Detection and Correction Circuit 2400. Thus errors detected in reading the Program Store 102 for program words or data or the Call Store 103 for program words within one central control unit are transmitted to the other central control unit to cause the Program Store Correct-Reread Sequencer 5301 or the Call Store Program Sequencer 5302 in both units to insert the same number of machine cycles and thereby keep the program execution in step.

When the duplicate central processors are executing different program sequences the flip-flop DI (FIG. 55) must previously be set in both central control units; a signal then continually appears on the order cable lead DI (FIG. 23) and is transmitted through the OR gate 2316 to the reset inputs of the E Correct and E Reread flip-flops. This reset signal overrides any trouble signals transmitted from the other central control so that the Error Detection and Correction Circuit 2400 does not respond to any externally generated trouble signals.

A similar cross connection applies to the reading or writing of data from the Call Store 103. In this instance hardware check failures are summarized in the Call Store Error Detection Circuit 2200 and appear as a signal on the CERI output conductor 2220 which sets the CSEI flip-flop 2201 and is transmitted via the AND-gate 2700 and Cable Driver 2701 to the bus 2706. The bus 2706 in each central control unit is connected to the bus 2208 of the other central control unit; the call store error signal generated as a half microsecond pulse in AND gate 2700 of one central control is thereby transmitted through Cable Receiver 2205 of the other central control unit to the CERE conductor 2212 and to the set input of the CSEE flip-flop 2202. The setting of either the CSEI or CSEE flip-flops cause a signal to be transmitted through the OR gate 2203 to the conductor CER (FIG. 22); a signal appearing on CER leads to the activation of the Call Store Reread Sequencer 5700.

Setting the flip-flop DI (FIG. 55) causes a signal to continually appear on DI (FIG. 22) and be transmitted through the OR gate 2209 to the reset input of the CSEE flip-flop 2202; the setting of DI (FIG. 55) serves to disable the cross connection of call store error information.

A cross connection of hardware check failure information is also provided as part of the execution of CPD commands and network commands. These commands and the hardware checks are executed under control of the Command Order Sequencer 4902; upon completion of a CPD command or a network command any hardware check failures are summarized as a half microsecond pulse appearing on the order cable conductor PUEI (FIG. 27) which is connected via the bus 5205 to the set input of the Maintenance Interrupt Source Flip-Flop PUEI (FIG. 52). This same signal is transmitted via the Cable Driver 2701 and bus 2706 to the other central control unit. This signal is transmitted to the bus 2208 of the other central control unit and within that unit through the Cable Receiver 2205 to the conductor PUEE (FIG. 22). Unless the flip-flop DI (FIG. 55) is set the signal appearing on PUEE (FIG. 22) is transmitted through the AND gate 5218 to the set input of the Maintenance Interrupt Source Flip-Flop PUEE (FIG. 52); setting either PUEI or PUEE leads to a level F maintenance interrupt and interrupt program sequences which investigate difficulties in CPD command or network command communications.

INTERRUPT LEVELS

Each of the telephone and maintenance program sequences which are initiated via the interrupt system are ranked in one of nine levels according to the relative urgency of the components. These levels are designated herein Level A, Level B...Level J (level I is excluded) in descending order. Corresponding to each of these levels is a discrete program sequence to which program control is transferred whenever the Interrupt Sequencer 4901 is activated, and this transfer is accompanied by the setting of a corresponding flip-flop in the Interrupt Level Activity Register 6302. For example, when the Interrupt Sequencer 4901 is activated to transfer control to a level E interrupt program sequence, order cable conductor 63LE S is enabled to set the level E activity flip-flop 63LE. Accordingly, each time an interrupt is generated the "level" of that interrupt is recorded in the Interrupt Level Activity Register 6302.

When the Central Control 101 is not executing any of its interrupt program sequences all of the flip-flops in the Interrupt Level Activity Register 6302 are reset and the Central Control 101 is said to be executing its "main program" and is operating in the "base level." When a specific program sequence is required, then a corresponding one of the flip-flops in the Maintenance Interrupt Sources 5209, 5210, 5605, and the H and J Clock Interrupt Sources 5604 is set. The setting of the Interrupt source flip-flop, unless inhibited by a means described elsewhere herein, activates the Interrupt Sequencer 4901 to effect the required interrupt.

INTERRUPT SOURCE FLIP-FLOPS

Each of the above-mentioned interrupt source flip-flops is associated with a discrete interrupt level. However, there may be a number of interrupt source flip-flops assigned to a particular level. For example, there are two interrupt source flip-flops 52MMI1 and 52 MMI0 both associated with the C level. Setting either of these flip-flops constitutes a request for a C level interrupt. The C level interrupt program sequences include orders to examine the interrupt source flip-flops 52MMI1 and 52 MMI0 to determine a specific set of program sequences to which a transfer is to be made, the sequence transferred to depending on the interrupt source flip-flop which was set to initiate the interrupt.

The assignment of interrupt source flip-flops to the corresponding level is as indicated below. ##SPC10## It is to be noted that there is no A level interrupt source flip-flop. The A level interrupt program sequences are generally employed only for initial testing of program sequences. An A level interrupt is initiated by operating a manual switch not shown which directly activates the Interrupt Sequencer 4901.

The activation of the Interrupt Sequencer 4901 depends not only on the setting of one of the above listed interrupt source flip-flops but also upon the states of the Interrupt Level Activity Register 6302 and the Interrupt Inhibit Control Register 6002, 6003. Assuming first that all of the flip-flops within the Interrupt Inhibit control Register 6002, 6003 are reset, then an interrupt is generated whenever an interrupt source flip-flop is set unless (with exceptions to be noted) the level activity flip-flop in the Interrupt Level Activity Register 6302 corresponding to that level or any higher level as indicated in the above table is set. This "lock-out" control of the interrupt levels is accomplished by combining the outputs of the Interrupt Source Flip-Flops 5209, 5210, 5604, and 5605 via conductors 5216 and 5608 and the OCG Cable 1812 and outputs of the Interrupt Level Activity Register 6302 as transmitted via cable 6303 and the OCG Cable 1812 within the Order Combining Gate Circuit 3901. Accordingly, when an interrupt request is registered and not "locked-out," order cable conductor 49IS GO is enabled to activate the Interrupt Sequencer 4901.

The Interrupt Inhibit Control Register 6002, 6003, permits the selective inhibition of interrupt requests as registered in the interrupt source flip-flops. For example, if the flip-flop 60I05 is set, then setting of the interrupt source flip-flop 56-ODD 5 is inhibited from activating the Interrupt Sequencer 4901. The assignment of inhibit signals to the flip-flops within the Interrupt Inhibit Control Register 6002, 6003 are as shown in the following table. ##SPC11##

In the performance of particular telephone and maintenance functions the occurrence of certain selected level interrupts are to be inhibited and be delayed or not executed. In these instances memory writing orders serve to selectively set one or more of the flip-flops in the Interrupt Inhibit Control Register 6002, 6003 as required. A subsequent resetting of the flip-flops in this register returns the ability to request interrupts to the corresponding interrupt source flip-flops.

As noted above, the setting of flip-flops in the Interrupt Level Activity Register 6302, with exceptions to be noted, serve to lockout subsequent interrupts corresponding to that level and all levels below. For example, the setting of the interrupt level activity flip-flop 63LG in the execution of a level G interrupt prevents further response of the Interrupt Sequencer 4901 to the setting of any interrupt source flip-flops corresponding to the levels G, H, and J. However, the Interrupt Sequencer 4901 remains responsive to the setting of interrupt source flip-flops corresponding to levels F or higher. If one of the higher level interrupt source flip-flops is set, the Interrupt Sequencer 4901 will execute the transfer of program control from the G level interrupt program sequences to the interrupt program sequence corresponding to the higher level. The sequencer also carries out the storing of the return code-address and other information and a pair of locations in the Call Store 103 reserved for this higher level. The occurrence of the higher level interrupt is also recorded by setting the appropriate flip-flop in the Interrupt Level Activity Register 6302.

The base level program may be interrupted in the manner just described to begin execution of any one of the nine level interrupt programs, and once one of these program sequences is initiated it, in turn, may be interrupted to permit the performance of higher level interrupt functions. However, with two exceptions noted below any given level interrupt program sequence may not be interrupted to perform an interrupt function of the same or lower level.

The Interrupt Level Activity Register 6302 serves to completely record the history (unless the noted exceptions occur) of any such occurrence of interrupts upon interrupts. Accordingly, even when such interrupts upon interrupts occur, when each of the interrupt program sequences are completed the Central Control 101 can be returned to the state it enjoyed at the time of the associated interrupt (including the resetting of the appropriate flip-flop in the Interrupt Level Activity Register 6302) and program control be returned to the lower level interrupted program.

The above-noted exceptions to the hierarchy of interrupt levels may occur in the execution of A and/or B level interrupts. The A level interrupt program sequences are provided as a tool in the initial testing of program sequences; the Interrupt Sequencer 4901 may be activated to generate an A level interrupt by manual means not shown. This program test sequence is assigned to the highest interrupt level so that it can be initiated to an interrupt and examine the state of Central Control 101 for any program sequence being tested. The programs to be tested can therefore include all interrupt program sequences other than the A level interrupt program sequence itself.

The B level interrupt is generated whenever the Emergency Action Sequencer 5702 is activated, and the B level interrupt program sequence continues the execution of the emergency action functions initiated by the Emergency Action Sequencer 5702. In some instances the functions performed by the Emergency Action Sequencer 5702 and the B level interrupt program sequences will not resolve the difficulty; in such instances hardware and/or program checks result in the reactivation of the Emergency Action Sequencer 5702. In such instances the Interrupt Sequencer 4901 must again be activated to reinitiate the B level interrupt program sequences. Accordingly, B level interrupts are allowed to interrupt both A level and B level program sequences as indicated in FIG. 66.

INTERRUPT ADDRESS SOURCE (3411)

Associated with each interrupt level are three discrete code-addresses; for the nine interrupt levels there are a total of 27 such code-addresses, no two of which are alike. Two of the code-addresses associated with each interrupt level correspond to the pair of reserved call store locations used by the Interrupt Sequencer 4901 for the storage of the contents of the Data Buffer Register 2601, the Auxiliary Storage Register 4812, et cetera. The third code-address comprises the transfer code-address which corresponds to the location of the first program order word in the interrupt program sequence.

The Interrupt Address Source 3411 generates these code-addresses under control of the Interrupt Sequencer 4901 and in response to the state of the Interrupt Level Activity Register 6302 which indicates the level of the interrupt being executed. The Interrupt Address Source 3411 receives these indications via order cable conductors 3420 and generates the required outputs as follows:

1. During the first machine cycle of the interrupt the call store code-address of the first reserved storage location is generated and transmitted to the Index Adder Output Register 3401 via AND gate 3412 and the OR gate 3410. The Interrupt Sequencer 4901 enables the order cable conductor 34ISIR to effect this step; the code-address is then transmitted as part of the call store writing command;

2. During the second machine cycle of the interrupt, the Interrupt Address Source 3411 responds to the corresponding internal state of the Interrupt Sequencer 4901 to generate the second call store code-address; and

3. Signals on order cable conductors 34INMB and 43MBPA transmit the transfer code-address from the outputs of the Interrupt Address Source 3411 via the Masked Bus 2011 to the Program Address Register 4801 to effect the transfer.

MODIFIED INTERRUPT ADDRESS FLIP-FLOP (4717)

In performing the maintenance functions within our system various interrupt program sequences carry out the required remedial actions. To perform these actions certain portions of the hardware within Central Control 101 must be functioning properly at the time the remedial action is required. Since these remedial actions are required at random instances, a number of base level program sequences are periodically executed tp perform various "preventive" maintenance functions. These functions include the testing or "exercising" of those portions of the central control hardware not otherwise used in call processing program sequences but which must be functioning properly to carry out remedial maintenance functions. These exercises include check of the Interrupt Sequencer 4901 utilizing the Modified Interrupt Address Flip-Flop 4717 for such exercises.

In our system it is possible to cause a setting of a selected one of the maintenance interrupt source flip-flops even when the system has in reality no associated circuit troubles. For example, the successive execution of the orders BMOP and MB to the same call store location result in the experiencing of a rereading failure by the Call Store Rereading Sequencer 5700 and the subsequent setting of the D level interrupt source flip-flop 52CSRRF. Accordingly, the ability of the interrupt system to respond to the setting of 52CSRRF can be exercised; however, to avoid burdening the D level interrupt program with determining whether the interrupt was initiated as a result of the preventive maintenance test or as a result of a trouble condition in communication with the Call Store 103 the modified interrupt address flip-flop 4717 is provided.

In the exercising of the Interrupt Sequencer 4901 the Modified Interrupt Address Flip-Flop 4717 is first set and then the setting of the selected interrupt source flip-flop is achieved shortly thereafter. As a result all of the steps of the interrupt are performed by the Interrupt Sequencer 4901, but one bit of the transfer code-address generated in the Interrupt Address Source 3411 is changed so that a transfer is made not to the maintenance interrupt program sequence but to a special program interrupt sequence which is part of the program sequences to exercise the Interrupt Sequencer 4901.

After the transfer code-address is placed in the Program Address Register 4801 the Interrupt Sequencer 4901 resets the Modified Interrupt Address Flip-Flop 4717. Thus, the access to the maintenance interrupt program sequences is rapidly and conveniently returned to maximize the security of access to the remedial maintenance functions.

DELAYS IN ACTIVATING THE INTERRUPT SEQUENCER (4901)

Whenever an interrupt source flip-flop is set and the state of the Interrupt Level Activity Register 6302 and the Inhibit Interrupt Control Register 6002, 6003 do not otherwise lockout or inhibit the interrupt request, the Interrupt Sequencer 4901 is activated to perform the corresponding level interrupt. This response may occur within one machine cycle after the setting of the interrupt source flip-flop or a delay of several machine cycles may be experienced. This delay is dependent on the state of Central Control 101 as follows:

1. If the Central Control 101 is executing a multicycle program order in the Order Word Register 3403 when the interrupt request is registered, the corresponding interrupt is delayed until the operational step of that order is completed and the Buffer Order Word Decoder 3902 and the Mixed Decoder 3903 are inhibited to prevent the processing of the next order in sequence. Thus, the interrupt follows the completion of the order in the Order Word Register 3403 but occurs before the next program order in sequence is processed.

2. Whenever the Central Control 101 is rereading and/or correcting program order words or data, any interrupt request are not served until the corresponding sequencer actions are completed.

3. When the Central Control 101 is executing an EXC order any simultaneous occurrence of the setting of an interrupt source flip-flop is not recognized by the Interrupt Sequencer 4901 until the order word specified by the EXC order has either been obtained and executed or encounters a rereading failure. This delay is provided so that the code-address stored by the interrupt always comprises the correct return code-address.

In addition, when the execution of any of the orders ENTJ, MCII, and MKII are accompanied by simultaneous H or J level interrupt requests, the interrupt is delayed until the order following the ENTJ, MCII, or MKII is executed. It is to be noted that maintenance interrupts (Level G or higher) are not delayed so that circuit troubles detected in the execution of any of these order words leads to the immediate occurrence of the required interrupt.

The delay for the ENTJ order is provided for reasons similar to that stated above for the order EXC. That is, the appropriate return code-address can be determined only with the aid of a special program sequence. The operational delay provided for levels H and J eliminates the need for executing the special program sequence in returning to the base level from the H or J interrupt levels. Thus, the time consumed for the noncall processing portions of the frequently executed H and J level interrupt programs is reduced.

The orders MCII and MKII are also provided with this delay feature to circumvent a different problem. In the base level there are program sequences which read certain data words from the Call Store 103 and with the following program order modify and return the modified data to the same location in the Call Store 103. The program sequence would consist of a memory reading order followed by a memory writing order.

The H and/or J level interrupt level program sequences may also modify this data word in a similar manner. If the base level program sequence is interrupted to perform such an H or J level function after the data has been read in the base level program sequence but prior to the modification and writing of that data word, then upon return to the base level the execution of the memory writing order will destroy the modification of data performed at the H or J level. By utilizing the order MCII or the order MKII of the above-mentioned two word base level program sequence the H and J level interrupts are delayed until the memory writing order following MCII or MKII is completed thereby eliminating the hazard described above.

RETRIAL OF INTERRUPT STORING OPERATIONS

When the Interrupt Sequencer 4901 carries out the two call store writing operations each operation is accompanied by a hardware check and if either of these checks fail, the Call Store Reread Sequencer 5700 is enabled. The Call Store Reread Sequencer 5700 provides an automatic retrial of the storage operation. If the retrial succeeds, the Call Store Reread Sequencer 5700 returns to the inactive state and the interrupt proceeds as previously described. If, however, the retrial fails, the interrupt also proceeds to completion but before the Call Store Reread Sequencer 5700 is returned to the inactive state sets the maintenance interrupt source flip-flop 52CSRRF and a special flip-flop 63CSFI associated with the failure of the retrial of interrupt storage actions.

The D level interrupt program sequences interrogate the flip-flop 63CSFI to determine if the interrupt had been generated in response to the repeated failure of one or both of the storage operations for an interrupt. The state of the flip-flop 63CSFI serves as a warning related to the information contained in the storage locations reserved for interrupts. The D level interrupt program sequences thereby recognize situations in which circuit troubles have led to the potential loss of the return code-address of one or more interrupt program sequences. In such instances upon completion of the D level interrupt program the interrupt storage locations in the Call Store 103 are not used to obtain the return code-address. Instead program control is returned to a convenient beginning point in the base level program, the point selected to minimize adverse effects on call processing and subscriber satisfaction.

PROTECTED AREA

A "protected area" is provided as a part of our system, and this protected area refers to a selected block of memory within the Call Store 103. Unless the Protected Area Flip-flop 5201 is set, the execution of a call store writing command to a code-address within the "protected block" cannot be transmitted from the Central Control 101. The call store writing command is converted into a call store reading command before transmission to the Call Store 103 to preserve the information in the Call Store 103, and the maintenance interrupt source flip-flop 52 PTAV is set.

Critical data such as recent change information relating to equipment number or directory number translations are placed in the protected area. Thus, difficulties in the Central Processor 100 may momentarily cause the Central Processor 100 to lose its sanity, but even in these instances the information stored in the protected area is safeguarded against protection.

Since new information must be placed in the protected area from time to time, the Protected Area Flip-flop 5201 may be set and once this flip-flop is set, then call store writing commands can be addressed to the protected area.

To maximize the security provided by the protected area the Protected Area Flip-Flop 5201 should be set only for short intervals of time and only as required to modify information contained in the protected area. Accordingly, whenever an interrupt occurs the Interrupt Sequencer 4901 first stores the state of the Protected Area Flip-flop 5201 and then resets this flip-flop so that the above-mentioned security is maintained in the presence of randomly occurring interrupts.

INTERRUPT HAS OCCURRED FLIP-FLOP 63IHO

In the performance of certain work operations Central Control 101 executes program sequences for which the execution must be performed in near-real-time. That is, if the time elapsed between the beginning and end of such a program sequence is greatly increased by the occurrence of an intervening interrupt, then the function may be incorrectly performed. The Interrupt Has Occurred Flip-Flop 63IHO is included to permit the detection of the occurrence of the intervening interrupts. Program sequences requiring this detection execute a memory writing order which serves to reset flip-flop 63IHO. The program sequence then continues with the required work operation. However, before the conclusive steps of this program sequence are executed a memory reading order interrogates the state of flip-flop 63IHO. If flip-flop 63IHO is reset, then it is determined that the program sequence was not interrupted and control can proceed to those conclusive steps. If, however, flip-flop 63IHO is set, the occurrence of an intervening interrupt is indicated and, according to the work operation being performed, the program sequence may be repeated immediately or abandoned for subsequent convenient repetition.

ORDER GBN AND THE GO BACK SEQUENCER (5300)

Whenever an interrupt is initiated under control of the Interrupt Sequencer 4901 a number of special actions are taken as follows:

1. Store information pertinent to the interrupted program into the call store locations which are discrete to the interrupt level and which are reserved for this purpose;

2. Update the Interrupt Level Activity Register 6302; and

3. Generate a transfer address which is then placed in the Program Address Register 4801 to effect the transfer to the interrupt program.

In many instances, upon completion of the interrupt program, control is to be returned to the interrupted program; therefore, certain of the flip-flop registers within Central Control 101 must be returned to the state they had at the time the interrupt occurred. The flip-flop registers to be restored include the Interrupt Level Activity Register 6302, the Control Sign Flip-Flop 5413, the Control Homogeneity Flip-Flop 5020, the Protected Area Flip-Flop 5201, and the Data Buffer Register 2601. In addition, the code-address of the return order word of the interrupted sequence must be placed in the Program Address Register 4801 to effect return to the interrupted program. The return to the interrupted program is most conveniently accomplished by the provision of the Go Back Sequencer 5300.

When all tasks in a given level interrupt level program are completed, and it is determined that program control is to be returned to the interrupted program, then the order GBN is executed to activate the Go Back Sequencer 5300 by enabling order cable conductor 53GBS GO.

In response to this signal the Go Back Sequencer 5300 is activated and remains active for two or more 5.5 microsecond cycles during which time it generates signals on its output conductors 53GBS, 53GBS1, et cetera, to carry out the following:

1. Inhibit the decoder outputs until control has been returned to the interrupted program. 2. In the first cycle of operation read the Call Store 103 at the second reserved location to obtain the return program code-address and the information to be placed in the PTA Flip-Flop 5201, the Control Sign Flip-Flop 5413, and the Control Homogeneity Flip-Flop 5020. The Interrupt Address Source 3411 is utilized to obtain the code-address of the first reserved location.

The reading so obtained is placed in the Data Buffer Register 2601 and moved from there via the Mask and Complement Circuit 2000 to the Masked Bus 2011. From there the 20 bit return code-address is transmitted via the AND-gate 4308 and the OR gate 4808 to the inputs of the Program Address Register 4801. The information appearing on bit 21 of the Masked Bus 2011 is transmitted to the Control Homogeneity Flip-Flop 5020, the information appearing on bit 22 is transmitted to the Control Sign Flip-Flop 5413, and the information appearing on bit 20 enables the appropriate one of the two order cable conductors 52PTA S and 52PTA R. 3. In the second 5.5 microsecond cycle the Go Back Sequencer 5300 again utilizes the Interrupt Address Source 3411 to obtain the code-address of the first reserved memory location. The Go Back Sequencer 5300 places the reading obtained at this code-address in the Data Buffer Register 2601 which is the state this register enjoyed at the time of the interrupt. 4. The Go Back Sequencer 5300 resets the flip-flop in the Interrupt Level Activity Register 6302 associated with the interrupt program from which the return is being made and returns to the inactive state.

DETAILED TELEPHONE AND MAINTENANCE FUNCTIONS

We have described the major divisions of a telephone switching office in accordance with our invention as shown in FIG. 1 and have explained in general terms the completion of intraoffice and interoffice calls with respect thereto.

All of the work functions mentioned above are implemented by means of the various program orders which have been previously described herein. The present discussion is without regard for detailed discussion of the program steps employed as such detail would merely tend to obscure an understanding of the inventive concepts of this system. Further, the detailed manner in which work operations are interleaved is also omitted on the same basis.

A telephone switching system in performing the telephone functions must accurately respond to input signals from information sources such as lines and trunks without delay. In our telephone switching system a single Central Control 101 is time-shared not only by a large number of input sources such as lines and trunks but also by the maintenance requirements of the system. In order to assure timely performance of all of the telephone functions which are required to render service to customers on a near real time basis and the timely performance of the necessary maintenance functions, a system or hierarchy of interrupt actions is provided. The interrupt hierarchy is shown schematically in FIG. 66. This hierarchy comprises three basic sections, namely:

A. The base level;

B. The 5 millisecond clock interrupts; and

C. The maintenance interrupts.

The interrupt plan employed herein is termed a graceful interrupt system in that when an interrupt is indicated, the interrupt action is momentarily delayed until the order which is being processed is completed.

The work functions which must be performed by the telephone switching system may be broadly divided into two classes, namely, deferrable work functions and nondeferrable work functions. Both of these classes include both telephone work functions and maintenance work functions. The nondeferrable telephone work functions are repetitive actions which must be done at set intervals of time such as examining dial pulse and TOUCH-TONE receivers, the control of outpulsing on trunks, other tasks involving the collection of information from both lines and trunks and the control of trunks and the network controllers. Deferrable telephone functions include the processing of information which has been previously collected by means of the nondeferrable telephone functions.

The nondeferrable maintenance functions include the immediate steps which are undertaken upon detection of possible trouble within the system and the necessary remedial actions required to bring the system into proper operation. The nondeferrable maintenance functions are implemented by means of fault recognition program sequences and the priority assigned such program sequences exceeds the priority assigned any normal call handling sequence. The fault recognition program sequences are kept as short as possible and their actions are limited to the steps required to determine if the possible trouble is indeed a fault and to take the faulty duplicate unit out of service. If a fault is detected in the currently active unit the standby unit is switched to the active state and the active unit to the standby state. After the high priority fault recognition and remedial functions have been completed the Central Control 101 immediately returns to the processing of calls. The deferrable maintenance functions include routine preventive maintenance programs and the detailed diagnosis of a fault which was previously detected by means of a nondeferrable maintenance function. The deferrable maintenance functions are implemented by means of program sequences which have a lower priority than the lowest priority assigned to call handling program sequences.

As noted earlier herein the terms "trouble," "error," and "fault" have definite meanings as follows:

1. Trouble is defined as a failure to perform an expected action. For example, a program order for reading information from a store location fails and this failure is considered to be a trouble.

2. Error is defined as a trouble which cannot be reproduced by fault check program sequences.

3. Fault is defined as a trouble which can be reproduced by fault check program sequences.

INTERRUPT PLAN

The system interrupt plan provides for 10 work levels which are designated A through L with I and K omitted. The highest priority is assigned level A with priorities descending to L which is the "base level." Levels A through G are associated with the maintenance interrupts, Levels H and J are assigned the odd and even 5 millisecond clock interrupts and L is the lowest or base level.

Corresponding to each interrupt level is a program sequence, which, when executed, causes the Central Control 101 to perform specific sequences of maintenance and/or telephone functions. For each interrupt level there is a different set of such functions and corresponding programs; a request for one of these functions is made by the occurrence of signals which set a corresponding one of the interrupt source flip-flops. The Central Control 101 responds to interrupt source signals by activating the Interrupt Sequencer 4901, which initiates the following actions:

1. The data which is found in the Data Buffer Register 2601 is stored in a reserved location in the Call Store 103;

2. The code-address of the next program order word in the interrupted sequence and the states of the C Flip-Flops 5020, 5413 and the Protected Area Flip-Flop 5201 are stored in a second reserved location in the Call Store 103;

3. Transfers program control to the interrupt level program corresponding to the energized interrupt source flip-flop.

The above-noted first and second reserved locations are associated in pairs in the Call Store 103 and there is one such pair for each of the nine interrupt levels excluding the base level L. In addition, for each of the interrupt levels G, H, and J there are blocks of word organized memory capacity comprising eight words each. These are also found in the Call Store 103. Similarly, there is a larger block of words which is common to the six interrupt levels A through F inclusive. This word block of memory capacity is provided to permit the interrupting program to preserve data which is found within Central Control 101 at the time the interrupt program assumed control of Central Control 101. This transfer of information under program control is limited to the transfer of information which clears the Central Control 101 elements which are required in the execution of the interrupt programs.

The interrupt plan includes a means for attending to the functions performed by the interrupt level program sequences in order of their urgency and maintains an orderly execution of these sequences.

The interrupt action just described, is initiated only if the transfer is to a higher level program sequence than the one currently being executed within Central Control 101.

BASE LEVEL

Within the base level of the interrupt plan the executive program (a) establishes the rate at which the various types of base level jobs are served, (b) serves to examine or monitor job requests and, in the event of a job request, to initiate the appropriate program subroutines. This relationship is illustrated in FIG. 66 under the heading "base level." The base level executive program initiates job supervisory programs under which job activity registers which are located in the store memory are examined to determine whether or not there are jobs of a particular class to be performed. The term "job" as defined herein is a system work operation which is performed at the base level. Each type of job requires a separate program subroutine for execution of that job, and job activity memory locations are assigned in the Call Store 103 to the various classes of jobs. The number of job activity memory locations assigned is a function of the call handling capacity of the particular office. If in the course of the execution of the job supervisory program it is determined that there are no jobs of a particular class to be performed, the supervisory program indicates "no job" and the executive program immediately advances to a different supervisory program. However, if in the course of execution of a supervisory program it is determined that there are jobs to be performed, the supervisory program will serve to initiate performance of such jobs up to a predetermined maximum number of jobs within a class and then return control to the executive program. When it is determined that a job is to be performed, the supervisory program initiates execution of a job program subroutine for each of the jobs to be performed. Upon completion of the subroutine the supervisory program advances through the activity memory associated with the particular class of job under consideration until either all jobs of that class have been completed by means of successive execution of the job program subroutine or until the fixed maximum number of jobs have been performed. At these times the job supervisory program returns control to the executive program by an indication that "job or jobs are done."

Within the base or L level there are five sublevels designated L.sub.a through L.sub.e and the jobs served at each of these sublevels are performed at rates which are discrete to the sublevel. There are more than five types of jobs to be performed at the base level; however, the various types of jobs are grouped in the five individual sublevels for administrative purposes. The grouping within base sublevels is in accordance with the frequency with which the job buffers must be examined to determine whether or not there are any jobs to be performed. That is, jobs which are handled at sublevel L.sub.a are associated with buffers which are examined more frequently than the buffers which are examined during sublevels L.sub.b and L.sub.c, et cetera. The base level executive program is implemented by means of a table of L level frequency addresses. This table comprises the list of the head address positions within the program store of each of the program subroutines required to execute the various sublevel job supervisory subroutines. The length of the table is determined by the rate at which the lowest or L.sub.e sublevel supervisory job was monitored. The following ordered list shows the relative frequencies at which the buffers associated with the various sublevels are considered:

SUBLEVEL FREQUENCY LIST

A, B, A, C, A, B, A, D, A, B, A, C, A, B, A, B, A, C, A, B, A, D, A, B, A, C, A, B, A, E.

Here it is seen that the supervisory programs for sublevel L.sub.a occur most frequently in the table and sublevels L.sub.b, L.sub.c, and L.sub.d occur less frequently and sublevel L.sub.e occurs only once in the table. The table is reentrant and, after the job supervisory program for sublevel L.sub.e had been executed, the table is again entered at the beginning.

As previously noted above herein, within each base sublevel there are a number of types of jobs which may be performed. Certain of these types may statistically require attention each time the associated sublevel job supervisory program is executed, while other jobs which are considered for performance during a particular sublevel job supervisory program may occur infrequently and randomly, and still other jobs require only attention at relatively long time intervals. To efficiently handle these three types of jobs which may be handled by any given sublevel job supervisory program, three different techniques are employed, as follows:

1. Jobs which statistically and consistently require attention are considered for activity during each occurrence of the associated sublevel supervisory program.

2. The jobs which occur infrequently and randomly are considered by the sublevel job supervisory program only on demand from other program sequences which indicate a need for this particular job performance. That is, if in the course of executing a program sequence it is determined that a job of a particular class is required, a flag, which comprises a memory cell associated with a particular job buffer, is marked and subsequently during the associated sublevel job supervisory program, this mark is recognized and such jobs are considered for execution.

3. The third type of job which requires infrequent but regular attention is initiated by means of long interval timing sequences which periodically request consideration of this type of job by the associated job supervisory program. Such a request is indicated by placing in a general purpose buffer located in the call store the address within the program store of the job subroutine which is required to perform the requested job.

In addition to these three types of jobs which are handled at the base level there are certain jobs which generally require a relatively few machine cycles to execute and which must be executed with only a moderate degree of timing precision. To accommodate such jobs a function termed herein "interject" is employed. The interject function is implemented by means of an interject register which is located in the Call Store 103. The interject register comprises an activity spot which is flagged if an interject job is requested and further comprises memory space to record sufficient information to perform the interject job. During the course of execution of the base level executive program the activity spot of the interject register is examined from time to time to determined determine whether or not an interject job request is present. If such a request is present the interject is served. However, the interject job may be accomplished without the time consuming enablement of the Interrupt Sequencer 4901. Similarly, in the course of execution of relatively long time sublevel job supervisory programs, the interject register is examined to determined determine whether or not an interject request is present and if present, it is served.

Jobs are planted in the interject register conveniently during the course of H or J level interrupt sequences. The H and J level interrupt sequences occur at five millisecond intervals. Thus it is possible to plant interject requests with a fair degree of timing precision.

CLOCK INTERRUPTS

In the absence of detection of a fault the H and J clock interrupt levels of operation take control away from the base level executive program to perform the nondeferrable telephone functions, i.e., those functions associated with the gathering of information concerning calls, for example, dial pulse and TOUCH-TONE supervisory scans, outpulsing scans, et cetera. The clock interrupts occur at 5 millisecond intervals and for the purpose of assigning work functions to be performed at a particular clock interrupt level these interrupts are divided into odd and even interrupts, H and J each occurring at independent 10 millisecond repetition rates. While most such jobs are performed at a 10 millisecond rate or at a rate that is some multiple of 10 milliseconds, and are thus associated only with the odd or the even interrupts, some jobs are performed every 5 milliseconds and are therefore performed during both 5 millisecond interrupts.

Indications of the jobs to be done at any given H or J interrupt are derived from counters. Jobs which are to be performed at regular intervals are discretely associated with the states of these counters. For example, there is a 100 millisecond counter which is incremented every 10 milliseconds. This counter comprises a plurality of cells in the call store and is recycled after 10 intervals, that is, after 100 milliseconds. This action is illustrated in FIG. 67. The states of the 100 millisecond counter serve to initiate job jobs which are performed regularly at intervals such as 10 milliseconds, 20 milliseconds, 30 milliseconds, et cetera.

When the 100 millisecond counter is recycled other counters comprising other cells in the call store are incremented to count fractions of a second, et cetera, to provide indications of times when jobs which are performed at longer intervals are to be initiated.

Associated with each discrete state of these counters are the starting addresses of the programs which are to be executed at the associated interrupt level to perform the desired jobs.

MAINTENANCE INTERRUPTS

The seven maintenance interrupts, levels A through G, are assigned to specific classes of potential trouble. Level A, which has the highest interrupt priority, is reserved for manual interrupts which are employed at the time the system is first installed and occasionally during the life of the system in the diagnosis of troubles which may escape automatic detection.

Level B, which is the highest automatic interrupt level, is associated with the "emergency action" functions. The emergency action functions are always associated with an active central control and program store. The Emergency Action Sequencer 5702 modifies the active combinations of program stores, central controls and the connecting bus circuits to achieve an operable combination of these elements.

As shown in FIG. 66, the A level programs and the B level programs are of approximately equal importance as it is possible for an A level program to interrupt a B level program and, similarly, it is possible for a B level program to interrupt an A level program. Furthermore, a B level interrupt may interrupt a B interrupt level program. If an A level program interrupts a B level program, the A level program is completed and central control proceeds to operate at an appropriate lower interrupt level and does not return to the B level program. Similarly, when a B level interrupt occurs during either an A level or a B level interrupt program the B level program is completed and the central control then continues with a lower level program rather than returning to the interrupted A or B level program.

Level C is associated with the Central Control Match Circuits 3122 and 3621. The dependability of program controlled telephone switching systems which employ highly time-shared control instrumentalities is greatly enhanced by operating the two central controls of the Central Control System 101 in the normal "in-step mode" of operation, which is also known as the "match mode" of operation. In this mode of operation the two central controls process identical input data and one of the two central controls, which is designated the active central control, is arranged to control the network. However, both central controls, while operating in this mode, read information from their associated stores such as the program store and the call store, and individually process the information so derived.

The program orders, for the purpose of defining the points within Central Control 101 to be matched, are divided into five classes. The internal points within the Central Control 101 which are to be routinely matched are defined by the order being executed. In the event that the matching of identical internal points within the paired central controls results in a mismatch indication, a C level interrupt is generated which initiates nondeferrable maintenance actions. These actions determine whether an error or a fault is present and if a fault is present, steps are taken to eliminate faulty elements from the active combination of equipments.

Level D is associated with a call store reread failure. As previously described herein, a number of hardware trouble indications such as parity failure, absence of an "All Seems Well" signal, et cetera, will initiate a call store reread function by means of the Call Store Reread Sequencer 5700. If the same or other trouble indication occurs in response to the reread function, a D level interrupt is immediately generated as the data which was derived from the Call Store 103 or the data which was written into the Call Store 103 is suspected. The D level program is calculated to isolate the source of trouble and to eliminate faulty apparatus from the central control, call store, bus combinations. After the D level interrupt program actions have been completed, the Central Control 101 returns to a lower level program.

Level E is associated with a program store reread failure. As previously noted, a number of hardware trouble indications, such as detection of a double error in a word obtained from the Program Store 102, or absence of a program store "All Seems Well" signal, will initiate a program store reread function by means of the Program Store Correct-Reread Sequencer 5301. The Program Store Correct-Reread Sequencer 5301 serves to extend the operating cycle of an order word both to correct single errors and to initiate a reread function upon the occurrence of one of the trouble conditions such as noted above. The E level interrupt programs, like a D level interrupt program, undertakes maintenance actions to isolate the source of trouble and take steps to rearrange the central control, program store, bus combinations to permit trouble-free operation.

Level F is associated with an indicated trouble in the execution of a command to one of the network units such as the Network Controllers 122, 131, Signal Distributors 128, 136, 140, Scanners 123, 127, or one of the miscellaneous frames being addressed via the network command bus, or the Central Pulse Distributor 143 and, in addition, is initiated upon detection of a "protected area violation" in the writing of data into the c Call Store 103. Upon completion of a level F interrupt program, the central control returns to the interrupted lower level work or to a program reference point in the base level.

Level G interrupts are special demand programs which are initiated by abnormal conditions such as a high rate of errors in the reading of the program store or a high rate of call store reading errors. G level interrupt programs are employed to isolate the sources of indicated trouble and, upon completion of such programs, the central control returns to the lower level of operation which was interrupted.

CONNECTION TO CALL SIGNAL RECEIVER AND DIAL TONE

One of the base level L.sub.b checks initiated by the job supervisory program, as seen in FIG. 68, is the interrogation of the service request buffer area in the Call Store 103 to determine whether or not there are any service request jobs to be performed. If a service request was previously detected and recorded by the service request recording program, then the job supervisory program must initiate a program to serve the recorded request. This information is referred to herein as a service request program. This program, among other functions, assigns a section of the call store memory, which is called an originating register, to provide means for recording information associated with a service request. The originating register is a collection of memory cells with the call store memory.

The originating registers are functionally divided into two major portions. The first portion is referred to herein as a basic originating register and the second portion as an auxiliary originating register. The basic originating registers are associated on a one-to-one basis with call signal receivers and are employed to collect information relating to service requests and, in the case of dial pulse calls, are employed in the counting of dial pulses and interdigital time-out.

The auxiliary originating registers are selectively associated with the basic originating registers as the requirement for their use is determined. An auxiliary originating register is employed to assemble the call signal information which has been detected under the control of the basic originating register, and is further employed during the time that the desired call is being established as it serves to store and thus provide the information required to determine the necessary network paths.

The basic originating registers each comprise a plurality of memory cells within the Call Store 103. The originating registers are arranged in groups of sixteen each and the memory locations associated with a register are distributed in an ordered fashion throughout an assigned portion of a Call Store 103. Each group of sixteen basic originating registers comprises:

A. Five call store words wherein one bit of each of the words is discretely part of a particular basic originating register;

B. Two call store words which are common to a group of sixteen basic registers; and

C. Three call store auxiliary words per register.

The first bit of each of the five common words is part of the first basic originating register, the second bit of each of the five words is part of the second basic originating register, et cetera. The five bits, which are so organized are assigned the following functions:

1. Supervisory last look spot;

2. Supervisory change spot;

3. Supervisory change last look spot;

4. Permanent signal-partial dial spot; and

5. Register activity spot.

The other two call store words, which are common to a group of 16 basic originating registers, are employed to register:

1. The identity or scanner address of the master scanner scan points, which are employed to supervise the signal present scan points on TOUCH-TONE receivers and looping scan points on dial pulse receivers; and

2. The call store starting address of the first basic originating register auxiliary words.

The auxiliary words are arranged in three word groups within the Call Store 103, that is, the first of the three words for all of the basic originating registers of a group are arranged in a first memory block, the second words for all of the registers of a group are in a second block, et cetera. These words are employed to store the following information:

Word 1. The program store address of the program which is required to perform the functions associated with the basic register;

Word 2. The call store address of the auxiliary register which has been assigned to the basic register and a four bit counter for accumulating dial pulses; and

Word 3. The scanner address of the TOUCH-TONE numerical interrogation points of a TOUCH-TONE call signal receiver which has become associated with the basic register.

The service request program locates an idle basic originating register and its associated call signal receiver by examining a linked list which is associated therewith. As previously noted herein, the basic originating registers and the call signal receivers are associated on a one-for-one basis and therefore a single linked list is employed to show the availability of a particular type of both basic originating registers and call signal receivers. Separate linked lists are employed to show the availability of dial pulse call signal receivers and combined dial pulse TOUCH-TONE call signal receivers. The type of call signal receiver which is assigned to a particular call is predicated upon the type of equipment which is located at the subscriber's premises, i.e., dial pulse subscriber station or TOUCH-TONE subscriber station, or in certain instances a subscriber may be served by both dial pulse subscriber sets and TOUCH-TONE subscriber sets on a single line. In the latter two cases, the subscriber's combined dial pulse TOUCH-TONE receiver is assigned to the call. In the case of dial pulse call signal receivers, a single basic originating register, as set forth before herein, is associated with a dial pulse call signal receiver. However, in the case of combined dial pulse TOUCH-TONE receivers, two basic originating registers, as set forth before herein, are associated with a single combined call signal receiver. The two originating registers are always employed on a mutually exclusive basis as one of the registers is employed when the receiver is responding to TOUCH-TONE signals and the other register is employed when the receiver is responding to dial pulse signals.

The linked list is stored in the Call Store 103 and comprises a two-word entry which is common to the list and numerical entries which are individual to each of the articles which may be assigned, i.e., in this case, basic originating registers. The two-word entry comprises the identities of the next article to be assigned and the most recently released article. The numerical entries are linked in that the entry associated with an article identifies the next article in the group which is to be assigned after the present article has been seized. After each article seizure the numerical entries are altered to continuously reflect the availability of articles within the group.

After an idle call signal receiver and an associated basic originating register have been found, these must both be assigned to the specific service request and the records in the Call Store 103 altered to reflect the change from busy to idle. That is, upon the seizure of an article from the list, the list is altered in accordance with the rules set forth above. The type of apparatus which is found at a subscriber's premises is stored in the Program Store 102 in a memory location which is discretely associated with the subscriber's line equipment number identification. In our telephone switching system, subscribers' lines are randomly assigned equipment locations on the network without regard for the directory number which is assigned to a subscriber's line. Separate translation tables are employed for call origination and for call termination. In the case of call originations, the memory location which is discretely associated with a subscriber's line is ordered in the memory in accordance with the subscriber's line equipment number identification. The translation information which is required for call origination is commonly called "originating class of service information." This information describes not only the type of call signal receiver which is required to serve an origination from the associated subscriber's line but, in addition, provides other information such as subscriber "denied service" or subscriber "manual origination", both of which indicate to the system that the call origination must be handled in a manner which is uniquely different from normal call originations. A subscriber with manual origination class of service (usually someone suffering from a physical handicap) is connected directly to an operator who will then set up the desired call. A person who is "denied service" is not connected to a receiver.

In a highly flexible telephone switching system such as ours there are a large variety of types of equipment which may be associated with a subscriber's line and a large number of special services which may be offered. By way of example only, in this one specific illustrative embodiment separate class of service information characterizes the equipment and services rendered a subscriber's line for call origination and call termination. For example, for purposes of call origination a six bit binary class of service indication is employed in the most usual instances. This six bit binary number is stored in the Program Store 102 in association with a seventeen bit number from which the subscriber's directory number can be obtained. Where a six bit binary number is not adequate to define the subscriber's class of service, the space normally reserved for translation information which comprises a six bit class of service indication and the seventeen bit directory number information is employed instead to store an indication that the class of service and directory number information is located elsewhere in the memory and to set forth that other memory location address.

The six bits which comprise the class of service mark are adequate to define up to 56 separate combinations of equipments and services rendered, while reserving eight combinations to indicate that the information in the class of service mark area is, in fact, part of an address at which the complete class of service information will be found.

The six bit class of service is expanded by program use of a look up table into a much larger group of bits which detail information on subjects such as the following:

1. Type of receiver (TOUCH-TONE, dial pulse, or both);

2. Special treatment at time of origination (PBX lines, two-party lines, denied service, manual origination);

3. Special services which the customer may have (abbreviated dialing, privilege of having the calls transferred to another number); and

4. Special routing information associated with unusual classes of service (wide area telephone service, PBX whose lines may only dial local calls, et cetera).

A discussion of the class of service indications and their significance on terminating calls is detailed later herein.

DIAL TONE CONNECTION

In order to set up a connection from a line requesting service to a call signal receiver we must first hunt for a path through the network between these two terminals. The path hunt operation is accomplished through the use of the Call Store 103 memory map of the present state of the network. The memory map comprises an ordered set of information wherein one memory bit position is associated with each link in the network.

The end product of the line link network path hunt and the trunk link network path hunt is an indication of the links and the junctor which may be employed in establishing a path between a selected line switch frame line termination and trunk switch frame trunk termination. These links must then be marked busy so that they will not be seized by subsequent path hunts and a series of instructions to the network must be created which will operate the crosspoints connecting these links. These instructions are then stored in the network command buffer which serves as a discipline to send instructions to network frames at the appropriate time and with the appropriate guard intervals between instructions.

When a path has been found and selected in memory we must not only mark the links of the path busy but we must also keep a record of the path in a special section of memory called the path memory. This consists of one word per trunk terminal and one word per line link network junctor terminal. The word contains the number of the junctor or line connected with this trunk or junctor terminal. This memory is necessary in order to release the proper links at the time when a path may be cleared.

FIG. 69 shows how the contents of the network command buffer are used to set up connections in the network. Every 20 milliseconds as determined by the clock interrupt programs of the H and J levels, a string of orders may be sent to the network controllers and the signal distributor controllers. The discipline of the command program is such that only one instruction is sent to an individual network controller or signal distributor controller in a given 20 millisecond interval. That is, a plurality of commands may be sent in a string, however, only one command of each string is directed to a single controller either network or signal distributor. Subsequently approximately 20 milliseconds are allowed to elapse in order to insure that all controllers have finished their present task before giving them another command. After the commands have been transmitted and executed by the respective controllers a trunk signal distributor command is generated to connect the call signaling receiver. The trunk signal distributor command is delayed for a period of time which is sufficient to assure that the network ferreed contacts have operated. Thus the current path between the originating subscriber and the call signal receiver is closed by the relays in the call signal receiver and not by the contacts of the ferreeds.

The operation of the network command program is such that it proceeds independently of the originating register which requested the connections set forth in the buffer and the command program only informs the originating register when it has completed the requested task or when it has gathered information of interest to the register.

The following is a detailed description of how a command is generated by means of the network command buffer. The network command buffer (illustrated in FIG. 69) comprises a group of work lists, each work list comprising a number of consecutive call store words, each work list being associated at any particular time with only one call. In addition, a master work location file within the call store comprises one word per work list.

If, while examining the work location file, an active entry is found, a transfer is made to a program which carries out the following steps: The first step is to read data word at the code-address specified by the work location file. If the word so read is positive (bit 22 of that word is a 1) the word is the address of central pulse distributor enable information for the particular controller to be employed in executing the subject network command.

Since some of the actions required by the information which is found in the work list are not simply requests to send a command to a network controller or a signal distributor controller but may, in addition, require additional actions such as a delay or a request for a scanner command, this information is placed in the J Register 5802.

A work list may also contain the addresses of programs for carrying out a particular function as opposed to code-addresses as indicated above. A program entry as opposed to a command is indicated when the first entry is negative rather than positive.

The second step is to make a decision based on the sign bit of the word read in the first step. If the result of the previous reading was a negative value, an earlier transfer to a program order at the code-address stored in the J register is indicated. This address is the address that was set up by the previously described order.

If the word at the first entry is positive, it is the address of the enable information and memory reading to the F register is a carried out. The address of the enable information is determined on the basis of which controller is to be enabled. For example, in the case of a signal distributor the first 384 points are normally controlled by its 0 controller whereas the last 384 points are normally controlled by the 1 controller. In the case of trouble, the 0 controller or the 1 controller may be arranged to control all of the points. Thus the enable information must be selected on the basis of whether the selected point is within the first 384 points or the last 384 points. In addition, where two identical enable entries occur, steps must be taken to assure that the controller to be enabled is used only once per 20 milliseconds cycle.

Thus the busy-idle indication is determined by considering which controller is actually to be used not by which unit is being requested.

Associated with each controller, both network and signal distributor, is a busy-idle word. This word is at a constant displacement from the enable information normally associated with the controller. The word which stores the enable information also stores whether the 0 or 1 controller is being used and this information is stored in the least significant bit.

By use of an instruction, which has the designation MCLF, a reading is made of the busy-idle word associated with the controller actually being used. For example, if the 0 controller is defective and the 1 controller is being used for the entire single distributor, then the enable information for both the 0 and the 1 controllers would point to controller 1. The order MCLF is used for reading this information and by substituting the least significant bit of the contents of the F Register 5801 for the second least significant bit of the DAR word, a reading of either enable information leads to the busy-idle word of the 1 controller. The busy-idle words of the 0 and the 1 controllers are stored at locations which are separated by three intervening addresses. That is, the busy-idle word of the 0 controller is at an address having a 0 in the second least significant bit while the busy-idle word of the 1 controller is at a location whose code address has a 1 in the second least significant bit. Thus, by means of the MCLF order a masked reading of the busy-idle word is gated to the control flip-flops.

The next step is to transfer to an order, the code-address of which is found in the Z register if the state of the Control Flip-Flops 5020 and 5413 indicate that the word examined by the preceding order was other than arithmetic zero. The program which is located at the address specified by the contents of the Z Register 3002 is the program associated with encountering a particular controller which had already received a command in the current 20 millisecond interval. This program adjusts the address in the work location file so that in the succeeding 20 millisecond interval an attempt will again be made to generate and transmit this command.

If the Homogeneity Flip-Flop 5020 is in the 1 state, the contents of the Logic Register 2508 are stored back in the location reserved for the busy-idle word. By this means the subject controller is made busy for the current 20 millisecond interval so that if a subsequent request to use this controller is made during this same interval, the latter request will encounter a busy controller.

As the program advances from one 20 millisecond interval to the next, the contents of the logic register during the execution of the word list are changed. The contents always comprise a word in which one, and only one bit, is equal to 1 and as the program advances from one interval to the next, the position of this bit is rotated by one position.

Having ascertained that the controller is idle, the busy-idle word for that controller is altered to make the controller appear busy.

The enable information is found in the F Register 5801. Three bits (bits 7, 8, 9) of the enable information in conjunction with the output of the Order Word Decoder 3904 specify the type of unit, i.e., network controller, signal distributor controller, and if a network controller, the type of frame served by that controller. Therefore, this information determines the form of the command which is transmitted.

FIG. 70 illustrates the process of detecting and counting dial pulses. This process is accomplished during the H and J level interrupt programs. Every 10 10 milliseconds each group of sixteen call signal receivers is scanned. Associated with these 16 receivers is a 16 bit entry in the Call Store 103 and in this entry there is retained a record of the supervisory state of the receivers as determined by the immediately preceding scan. Dial pulses are detected by checking for off-hook to on-hook transitions and if there is disagreement between the previous state of the receiver and the present state, as determined by the most recent scan, this fact is recorded as it indicates a dial pulse. The scanning program marks the change bit in each basic originating register for which a change has been recognized and updates the call store memory cells associated with the digit receiver scan points to reflect the states recognized by the last scan. Further, when off-hook to on-hook transitions are recognized, a transfer is made to a subroutine for recording such changes in the basic originating registers. The subroutine increments the pulse counters in each of the basic originating registers in which the change spot was marked.

At the time that the first change from off-hook to on-hook is detected, dial tone must be removed. The program for accumulating digits recognizes this fact and initiates a request for the removal of dial tone by making an entry in the dial tone remover buffer. This entry comprises the address of the basic originating register assigned to this call.

FIG. 71 illustrates the process of removing dial tone. The job supervisory program of sublevel L.sub.b checks to determine if there are any requests entered in the dial tone removal buffer. If a request is found, the dial toe tone removal program must be entered. The address of the originating register associated with the call requesting removal of the dial tone is obtained from the dial tone removal buffer. This originating register is interrogated to find the identity of the call signaling receiver which is associated with the call. The dial tone removal program then generates a signal distributor command to release relay 102A in the selected call signaling receiver. The signal distributor command is placed in the network command order buffer and this command is subsequently transmitted under control of the network command program.

FIG. 72 illustrates the process of recognizing the end of a digit in the case of dial pulse signaling. Every 100 milliseconds (as indicated by a count of 20 successive 5 millisecond intervals in the H and J interrupt programs) an interdigital timing program is initiated at the base level by means of an interject. This program examines the dial pulse activity spot associated with each active dial pulse receiver to detect digit receivers which did not experience a change during the last 100 millisecond interval but which did experience a change during the immediately preceding 100 millisecond interval. This condition is considered to represent the completion of a digit and upon detection thereof the pulse count accumulated in the originating register is transferred to the proper digit location in the auxiliary originating register and the pulse count is restored to 0 in preparation for receipt of the next digit. The transfer of pulse count information is accomplished by way of a digit buffer in which the pulse count obtained from the basic originating register is a stored along with the address of the originating register associated with that digit. Subsequently, the digit buffer program which is executed at sublevel l.sub.b examines the digit buffer. If there is an entry therein, the digit buffer program serves to transfer the digit to the appropriate auxiliary originating register wherein the other digits that have been previously accumulated are also stored. The digit location counter of the auxiliary originating register is incremented by a count of 1 to summarize the number of digits which have been received.

An analysis must be made of the digits that have been dialed at several key points in the receipt of these digits (see FIGS. 5 and 6). For example, after the first digit is dialed a check must be made to see if the first digit was a zero since an initial zero completely defines the destination of the call as an operator call. For other calls the first three digits are examined and in accordance with the translation of these digits it is determined how many digits will be forthcoming. Subsequently, when all digits have been received, a further translation is made which indicates the routing and treatment to be afforded the call. For example, it must be determined whether the call is an intraoffice call or an interoffice call since different control actions taken place under these circumstances. If the call is an interoffice call, the following information must be obtained in order to complete the call:

1. The identity of a trunk group connecting the originating office to the terminating office;

2. An indication of how many digits must be sent to the terminating office;

3. The type of pulsing which is used in communicating with the terminating office and, thus, the type of call signaling transmitter which is to be connected to the selected trunk for outpulsing; and

4. Other information necessary to indicate to the system whether or not the calling subscriber is permitted to be connected to the terminating office.

The first three elements of information are obtained by a translation of the office code digits, while the fourth element is obtained from the combination of the class of service information associated with the originating subscriber and the office code translation information.

If the call is an intraoffice call, a terminating translation must be made. That is, the class of service information associated with the called subscriber will give the following information:

1. If the called party is on a party line, it gives the type of ringing to be used to reach the desired party;

2. If the called number is that of a PBX, it provides a list of line equipments associated with the PBX so that these line equipments may be examined to find an identical one;

3. If the called line is one that has requested that incoming calls be transferred to another line, it provides the directory number of the line to be transferred to; and

4. If the called line is one which has associated therewith a series completion feature, it provides the directory number of the line to which the call may be completed if the called line is busy.

If the called number is neither a valid intraoffice nor interoffice code but, rather, some nonexistent number, the translation indicates that the calling subscriber is to be connected to no such number tone and/or announcement circuit.

Assuming that examination of the registered call signaling information indicates an intraoffice call to another subscriber's line served by the office and assuming that examination shows that this line is idle, steps must be taken to signal the called subscriber. The busy-idle condition of the called subscriber's line is determined by examining the busy-idle bit associated with the called line.

The called line is signaled by means of a ringing connection. That is, two paths are established through the network to supply ringing current to the called subscriber and to supply ringing induction to the calling subscriber. In order to establish these connections, path hunts must be made to find idle paths between the originating subscriber and a tone circuit for applying ringing induction and a path between the called subscriber's station and a ringing circuit. Further, in order to assure that once the called subscriber answers that a path exists between the originating and terminating subscribers, a path between these two stations must be sought and reserved in the memory (this reserve path cannot be set up immediately as each subscriber is connected to a different service circuit at the trunk link network). If the path hunts are successful, central control generates the network commands for:

1. Disconnecting the calling line from the call signaling receiver;

2. Connecting the calling line to the tone circuits supplying ringing induction; and

3. Connecting the called line to the ringing circuit. The instructions for setting up these connections are placed in the network command buffer and subsequently the network command buffer program will send these commands in proper sequence to the network controllers and to the signal distributors. At the same time a ringing register, which comprises a group of memory bits in the call store, is seized and assigned to the call. Central control places in the ringing register the addresses of both the originating and terminating subscriber lines and the identities of the ringing circuit and the tone circuit. In addition, the program modifies the linked lists associated with the ringing circuit and the tone circuit which are employed in this connection and modifies the trunk busy-idle bits.

When the above two connections are established, supervision of both the calling line and the called line is transferred to the tone circuit and to the ringing circuit, respectively.

One of the sublevel L.sub.c programs initiated by the job supervisory program is a trunk supervisory scan program. This program is arranged to detect seizures and disconnects on trunk circuits. Among the trunks scanned by this program are the tone circuits which apply ringing induction and ringing circuit. Service circuits such as the tone circuit of FIG. 106 and the ringing circuit of FIG. 109 are not capable of accepting bids or requests for service; however, these circuits are arranged to supervise the connected lines or trunks to detect disconnect. If the trunk supervisory scan program recognizes that a disconnect has taken place on a busy trunk or service circuit, or that a seizure has occurred on an idle trunk, it enters a record in the trunk disconnect buffer or the trunk service request buffer, respectively.

Another one of the sublevel L.sub.b programs initiated by the job supervisory program is a program for serving the trunk seizure and the trunk disconnect buffers. When this program recognizes that a trunk or service circuit disconnect has taken place it examines the record in the call store path memory associated with that trunk or service circuit. In the event that the trunk scan program detects that the called subscriber as monitored by the ringing circuit has gone from the on-hook to the off-hook state, steps must be taken to break down the connections between the calling subscriber and the connected tone circuit and between the called subscriber and the connected ringing circuit and to establish a talking path between the calling and called subscribers. In this event, the program will examine the ringing register associated with the call to initiate a program for making the transition from the ringing connection to the talking connection. That is, this program will generate commands to be placed in the network command buffer and these commands will:

1. Serve to release the tone circuit which was employed to provide ringing induction to the calling subscriber;

2. Release the ringing circuit which was employed in supplying ringing current to the called subscriber; and

3. To break the connections to both the originating and terminating subscribers at the first stage of the line link network.

Further, commands will be generated and placed in the network command buffer to establish a connection between the calling and called subscribers via a junctor circuit. After the paths are established through the network the junctor circuit is enabled to complete the transmission path between the calling and called subscribers and supervision of both the calling and called lines is transferred to the junction circuit. Further, at this time the ringing register is released.

When one or both of the subscribers hangs up, the supervisory scan of the junctor circuits detects this condition and registers a request for disconnection in the disconnect buffer. Subsequently, a sublevel L.sub.d program is initiated by the base level supervisory program and this program serves to generate and place in the network command buffer the commands which are required to restore the originating and terminating subscriber's lines to the idle state, to disconnect these lines from the network by opening the first stage crosspoints which were associated with the released call, and to release the junctor circuit which was employed in the call.

MAINTENANCE

A commercial telephone switching system is measured on the basis of both subscriber satisfaction and economic considerations. The illustrative data handling system comprises many major elements or subsystems and, generally, these major elements or subsystems are time-shared by a large number of subscribers and by the maintenance functions of the system. Accordingly, a failure in any of the major elements or subsystems may result in complete system failure or severe degradation of service.

In prior art electromagnetic telephone switching systems, such as the Bell System crossbar systems, a plurality of control circuits, i.e., markers are provided in sufficient numbers to serve the traffic requirements of the switching center. Each marker is time-shared by a large number of lines and trunks. However, in such arrangements any marker may serve any line or trunk and the loss of a single marker, or of a relatively few markers of the group, results only in a reduction in system traffic handling capacity and such a loss is not fatal to system operation.

Subscriber satisfaction demands that calls be handled accurately without unreasonable delays. Further, a commercial telephone switching system must be continuously available during all hours of the night and the day.

Before describing the measures which we have taken to insure subscriber satisfaction in an economically feasible system, it is necessary to define a number of terms which will be employed in the following description:

System Dependability, as employed herein, is a measure of the system's ability to continue to accurately perform its assigned functions (both call processing and maintenance), even in the presence of component and subsystem failures.

Maintainability, as employed herein, is a measure of the ease with which component and subsystem failures can be detected, diagnosed, and repaired.

Reliability of an item, i.e., component (as opposed to a subsystem) is a measure of the probability that the item will perform a specified function for a required period of time without a failure.

System dependability requires that even though the system may experience both component and subsystem failures, the existence of these failures is not reflected in the service which is rendered to a subscriber.

Maintainability is closely related to the economics of a switching system since a system which is easily maintainable requires a minimum of operating manpower. In addition, maintainability is also directly related to system dependability. That is, if a system has a high degree of maintainability, system components and subsystems are out of service a minimum amount of time, and it is recognized that subsystem downtime must be minimized if duplication of facilities is to be effective. That is, statistically two subsystems may fail simultaneously or within an extremely short period of each other. Therefore, it is important that, once a subsystem fault has been recognized, this fault be cleared and the subsystem returned to readiness to provide effective subsystem redundancy.

We have economically achieved system dependability by a number of measures which we will now describe. Certain of these measures are similar to techniques employed in prior art systems. However, as will be seen from the following description, even where similar measures are employed, we have devised improved techniques for implementing these known measures.

The first and most obvious measure to achieve system dependability is redundancy or subsystem duplication. As in any telephone switching system, certain redundancy or equipment duplication is inherent in a subsystem. For example, a telephone switching network provides inherent redundancy both in the switching paths which serve the individual subscriber lines and in the trunks and service circuits which are always provided in groups large enough to handle the system traffic requirements. For example, each subscriber's line has access to four A links in the line switch frame of the line link network in which that subscriber's line is terminated. Accordingly, in the event of a failure of one of the crosspoints which serves to connect a subscriber's line to a particular A link, there remain three other paths available for providing connections to that subscriber. Therefore, a plurality of paths remain available to connect the subscriber to the midpoint of the network, i.e., to the junctor terminals of the line junctor switch frame.

Similarly, since it is possible to have a plurality of simultaneous connections to any given trunk group or to any given type of service circuit, both trunk circuits and service circuits are provided in groups rather than on an individual basis. The loss of a single trunk circuit or a single service circuit, therefore, will not cause system failure, but rather merely decrease the system traffic handling capacity of that one particular trunk group or service circuit group.

It should be noted that, as is the practice in other telephone switching systems, apparatus which is individual to a subscriber is not duplicated since failure of this equipment affects the service to a single subscriber. Furthermore, the apparatus which is provided on a per subscriber basis is generally extremely rugged and reliable and therefore does not pose a major problem in providing system dependability.

In the illustrative embodiment entire subsystems or portions of subsystems are duplicated to provide system dependability. The following is a summary of the various subsystems of our switching system which is an illustration of a data handling system and the duplication employed with respect to each of these subsystems.

1. Central Control 101 Central controls are always provided in pairs. Further, the more important input and output communication paths (buses), are duplicated and provision is made for switching between certain duplicated buses at system cycle speeds (within one basic 5.5 microsecond system cycle).

2. Program Store 102 Program stores are provided in accordance with the semipermanent memory capacity requirements of the system. However, there are always at least two program stores employed in a system to provide duplicate copies of the information stored. Further, as in the case of the central control, both the input and output communication paths (the buses which connect the program stores to central control) are duplicated and provision is made for rapidly switching between both input and output buses.

3. Call Store 103 The number of call stores employed is based upon the temporary memory requirements of the system. However, again there are always at least two call stores employed in a system and in the absence of trouble all of the information stored is duplicated. Furthermore, both the input and the output communication paths are duplicated.

4. Network Units The network control and supervisory units comprise the Network Controllers 122, 131; the Network Scanners 123, 127, 135, 139; and the Network Signal Distributors 136, 140. The network controllers are provided in pairs and these pairs are each associated with a relatively small segment of the network. Further, one controller of a pair normally controls approximately one half of its associated network, while the other member of the pair normally controls the remaining portion of the network. However, in the event of failure of one member of a pair, the other member may be called upon to control the entire associated network portion. Similarly, the network signal distributors are provided in pairs and normally one member of the pair of signal distributors serves a first portion of associated circuits, while the other member serves the remaining portion of associated circuits. Again, however, in event of failure of either of the members of the pair, the remaining member may be called upon to control all of the associated circuits. This is true both in the case of the Signal Distributor 128 which serves the Junctor Frame 126 and the Signal Distributors 136 and 140 which serve the universal trunk frame and the miscellaneous trunk frame, respectively.

The Network Scanners 123, 135, and 139, are not duplicated in their entirety. The ferrod matrix which comprises a plurality of ferrods which are individual to the supervised circuit are not duplicated. However, the access circuitry which comprises core matrices for interrogating the ferrods and the control circuitry associated with the individual core matrices are completely duplicated as a failure in either a core matrix or its associated control circuitry would seriously affect system operation.

Further, in the case of all of the network elements, namely, the network controllers, the network scanners, and the network signal distributors, duplicated command communication paths are employed; and in the case of the network scanners a pair of scanner response communication paths are also provided.

5. Master Scanner 144 The master scanner comprises a number of independent scanners sufficient in number to serve the system capacity. However, entire scanners are not duplicated, but rather the arrangement set forth with respect to the network scanners is followed.

6. Central Pulse Distributor 143 Central pulse distributors are provided in numbers sufficient to serve the traffic handling capacity of the system. There is a complete duplication of central pulse distributors. Further, all of the central pulse distributors are connected to the Central Control 101 by means of a duplicated command communication bus system.

7. Miscellaneous Units The Automatic Message Accounting Apparatus 147, the Program Store Card Writer 146, and the Teletype Unit 145 comprise the miscellaneous units. The Automatic Message Accounting facilities 147 are provided in duplicate and there are a plurality of teletypewriters. Certain of the teletypewriters are assigned specific tasks such as maintenance, traffic records and service while others, while which are primarily employed for maintenance, may on request be used for any of the normal teletypewriter functions. However, the Program Store Card Writer 146 is not duplicated. Furthermore, all of the miscellaneous units employ the duplicated command transmission paths which serve the various network units and there is provision for rapidly switching between the input communication paths.

As seen from the above summary in the illustrative embodiment, system elements which affect a single line are not duplicated. There is inherent redundancy in certain other portions of the system, for example, in the network and the trunk circuits and service circuits. However, major elements, the failure of which would affect a large number of subscribers or would cause either a major degradation in service or a complete failure of service, are duplicated.

The manner, however, in which the duplicated facilities of our system are pressed into service advantageously differs markedly from the arrangements employed in prior art systems. That is, in prior art telephone switching systems and, similarly, in data processing systems which are somewhat analogous to our invention, subsystems which are duplicated are generally categorized as regular and standby and such subsystems are connected to and disconnected from other system subsystems by way of either manual switches or multicontact relays. These arrangements are not satisfactory in a system such as ours as the time required to switch between subsystems is inherently too long to be practical since not only is system data processing capacity or traffic handling capacity markedly decreased, but, also, there may be a substantial loss of important transient input data. For example, if dial pulse or TOUCH-TONE scanning is interrupted for periods of time sufficient to permit manual or relay switching of subsystems, calls are mutilated and this is reflected in subscriber dissatisfaction. Furthermore, mechanical contact switching of subsystems may generate random noise on the switched conductors which can introduce errors in system operation.

Accordingly, in our system a number of private communication bus systems provide the necessary input and output communication paths to the various subsystems and these communication paths are transformer coupled to both the subsystem sources and the subsystem loads. Transformer coupling serves to isolate subsystem faults from the communication paths serving that subsystem, the connecting subsystems and the duplicate of that subsystem.

Furthermore, the use of transformer coupled communication paths permits different subsystems to address a particular communication path without incurring switching time delay and permits addressed subsystems to accept commands over either one of a pair of duplicated communication paths again without incurring switching time delays.

In addition to equipment redundancy, a number of other system measures are employed in this one illustrative embodiment of our invention to enhance both system dependability and system maintainability. These measures may be divided into two major classes, each of which includes a number of subclasses. The two major classes are (1) hardware measures and (2) program measures.

Both of these classes include equipment checks which provide indications of trouble and, also, both of these classes include remedial steps which are calculated to keep a system running even in the presence of a detected trouble. The program measures also include actions which serve to not only isolate faults to a particular system or subsystem but also serve to accurately locate a fault within a subsystem. These more detailed program actions are directly reflected in the evaluation of the maintainability of our system and, as previously explained, are indirectly reflected in the dependability of our system as the rapid localization of trouble leads to rapid repair of a fault and thus makes duplicate subsystems available for service a high percentage of the time.

We have previously explained above herein the hardware checks hardware checks which are performed on the various subsystems of our system and have noted that program checks are employed also to detect troubles. The hardware checks will not be discussed at this time. However, further reference to the details of these checks will be made later herein as will a more detailed reference be made to the program checks which we employ. Both of these checks, i.e., hardware checks and program checks, lead to indications which are called "detected trouble." The action paths which are followed in the presence of hardware check and program check detected troubles are quite different. However, both of these paths merge at a point in the sequence at which a transfer is made to a nondeferrable fault recognition program.

If the detected trouble is in the operation of a Call Store 103 or a Program Store 102 the path to a sequence action called "retrial" is taken and if a successful call store or program store action accompanies a retrial action, the active combination of subsystems, i.e., call stores, program stores, central controls, and buses, is considered to be acceptable (pass) and the current sequence of program actions is continued. It should be noted, however, that even though a call store or program store retrial may be successful, the fact that a retrial was necessary is recorded and a large number of retrial actions within a limited period of time will lead to maintenance actions which are calculated to find the cause of repeated call store and program store reading errors or call store writing errors. If the call store or program store retrial action does not pass, a path is taken which leads to the maintenance action of setting an interrupt source flip-flop. This action is similarly taken when the detected trouble was other than a call store or program store trouble. There are a plurality of interrupt source flip-flops and these flip-flops are individual to the various sources of trouble.

The setting of an interrupt source flip-flop enables the Interrupt Sequencer 4901 which causes the current program sequence to be interrupted and to store in a reserved area in the Call Store 103 data which is found in a number of the registers of central control. Such data is preserved to permit in certain instances a subsequent return to the interrupted program where such return is both feasible and advisable, and in other cases to provide information which may be helpful in the course of the fault recognition program.

If the interrupt source flip-flop which is set indicates that the detected trouble is in one of the elements of the Central Processor 100, namely, the Central Control 101, the Program Store 102, or the Call Store 103, the Emergency Action 40 Millisecond Timer of the Real Time Check 5703 is enabled before transfer is made to the fault recognition program. When the interrupt source flip-flop which is set indicates a detected trouble in other than the Central Processor 100, a transfer is immediately made to the fault recognition program without enabling the emergency action timer.

If the detected trouble is indicated to be in either the Central Control 101 or the Call Store 103, a transfer is made to the fault recognition program located in the Program Store 102. However, if the detected trouble is in the Program Store 102, steps are taken to operate the Central Control 101 by means of a program which is found in the Call Store 103. That is, if a trouble is detected with respect to the operation of a Program Store 102, it does not appear reasonable to attempt to perform a fault recognition program based upon information derived from a Program Store 102; therefore, a relatively short fault recognition program is obtained from the Call Store 103. The call store program fault recognition sequence is initiated by enabling the Call Store Program Sequencer 5302.

When trouble is detected by means of program checks, a transfer is directly made to the fault recognition program which is specified by the detected trouble. It is not necessary to initiate an interrupt as was required when a hardware check detected trouble.

The fault recognition programs have the highest execution priority in our system as they are calculated to recover the system's call processing abilities. The fault recognition programs, however, are held to a minimum length to avoid disrupting call processing and are limited to steps which isolate the faulty subsystems and the necessary control actions which serve to remove the faulty subsystems from the active combination of subsystems. The first function of a nondeferrable fault recognition program is to determine whether the detected trouble represents a system error or a system fault. If the trouble cannot be reproduced by means of the fault recognition program, the detected trouble is considered to be an error and the system returns to call processing. However, before returning to call processing, a record is made which indicates that an error did occur since this information is required to determine whether or not a high error rate is occurring. As seen above, whenever an error occurs, it is necessary to transfer to a fault recognition program and this transfer reduces the call processing capacity of the central control. Therefore, a high error rate detracts from the efficience of our Control Processor 100.

If the fault recognition program is capable of reproducing the detected trouble, a fault is indicated and the fault recognition program proceeds to isolate the fault to a specific subsystem. It should be recognized that the fault may be found in either the active or the standby subsystem and that different program actions are required to recover system call processing.

If the fault occurs in a Central Control 101, a Call Store 103, or a Program Store 102, only a limited period of time (40 milliseconds) is allowed for the fault recognition program to isolate the fault to a specific subsystem. If the fault recognition program cannot isolate the fault within the prescribed period of time to a specific subsystem and it is known that the fault lies in the Central Control 101, Call Store 103, or Program Store 102, the fault recognition program records a request to subsequently initiate a deferred fault recognition program which will isolate the fault to a specific subsystem and then the nondeferrable fault recognition program rearranges the configurations of the central processor equipments which are related to the subsystem, i.e., Central Control 101, Call Store 103, or Program Store 102, which has an indicated fault.

If the nondeferrable fault recognition program isolates the fault to a specific subsystem it must be determined whether the subsystem which has failed is in the active or standby combination of equipments and appropriate action taken thereafter. If the active unit fails, the program serves to switch the standby unit into the active combination of equipments since this change is required to recover the system's call processing ability.

After a faulty subsystem has been switched to standby or after it has been determined that a standby subsystem is faulty, the fault recognition program operates trouble indicating flip-flops within the faulty subsystem or, in the case of a Network Controller 122, 131 or Signal Distributor 128, 136, 140, sets the faulty subsystem to a quarantine mode of operation.

Further, the nondeferrable fault recognition program marks a flag in the job supervisory register associated with the deferred fault recognition program which is required to pinpoint the trouble within the faulty subsystem.

After the call processing ability of the system is recovered by means of a program rearrangement of configurations of elements of the Central Processor 100 either after registering the request for a deferred fault recognition program or after isolating the fault to a particular subsystem, the fault recognition program resets the Emergency Action 40 Millisecond Timer of 5703. This was enabled when it was determined that a trouble had been detected which involved one of the elements of the Central Processor 100. If the call processing ability of the system is not recovered prior to time-out of the timer of 5703, specific emergency actions, which are described elsewhere herein, result in a B level program interrupt and ordered rearrangements of Central Control 101, Program Store 102, and their interconnecting buses.

When the Emergency Action 40MS Timer is reset before the end of its time-out period, the fault recognition program causes a transfer to a "Restart Program". The restart program, in accordance with prescribed rules, determines whether it is both feasible and advisable to return to the interrupted program. If return to the interrupted program is not advisable, the restart program will select one of several reference points within the H level program, the J level program, or the base level executive program to reinstitute call processing. If it is determined that it is possible to return to the interrupted program, the Go Back Sequencer 5300 is enabled to, on a wired basis, reinstitute call processing.

An example of a situation wherein it is feasible to return to the interrupted program is where a standby subsystem is found to be faulty; therefore, there has been no possibility of mutilation of data or either misdirection or misinterpretation of system commands. An example of an instance wherein it is not advisable to return to an interrupted program is where an active central control was found to be faulty and therefore there may be problems in accurately returning to the interrupted program. If the change from the fault recognition program to call processing is accomplished by way of the restart program rather than by way of the Go Back Sequencer 5300, the program serves to perform similar functions to those which the Sequencer 5300 performs on a wired basis; that is, the interrupt activity flip-flop is reset and the program then determines an appropriate reference point within one of the call processing levels H, J, or L to reinstitute call processing. The program places the code-address of the reference point in the Program Address Register 4801 and transfers to the program.

The recovery of call processing at the reference point does not require any prior history such as is required when an interrupted program sequence is reentered.

As previously discussed, base level work with the exception of work performed by interject is performed cyclically in accordance with the frequency list and there are no priorities associated with base level jobs. That is, each time the base level executive program is entered the job supervisory programs for all sublevels are performed and no one job supervisory program has priority over another. Within sublevel L.sub.a through L.sub.d the job supervisory programs serve all of the various types of sublevel jobs associated therewith. However, within sublevel L.sub.e which is devoted entirely to maintenance routines a priority scheme is employed. Maintenance actions are executed in their order of urgency and if urgent maintenance jobs remain undone, less urgent jobs are omitted. This is illustrated in FIG. 9 wherein the vertical line shows this priority arrangement. As seen at the top of FIG. 9, the maintenance, i.e., sublevel L.sub.e job supervisory program first determines whether or not there is a deferred fault recognition job to be performed. As previously described, a deferred fault recognition program is requested whenever a program rearrangement occurs without fully defining the faulty subsystem or pinpointing the fault to a subsystem. If there is a request for a deferred fault recognition program, the branch path is taken and such a program is executed. A deferred fault recognition program generally is rather lengthy and thus must be completed during several successive occurrences of sublevel L.sub.e processing. After thy action relating to the deferred fault recognition program has been completed, control is returned to the base level executive program. The deferred fault recognition program may include a special mode of operation termed the "simulated interrupt mode". In this mode of operation the program includes steps which simulate the conditions present during a maintenance interrupt.

If a deferred fault recognition request did not exist, the sublevel L.sub.e job supervisory program determines whether or not there are any diagnostic job requests present. Again, if such requests do exist, action is taken and control returned to the base level executive program. If no such jobs exist, the job supervisory program proceeds to determine whether or not there are requests for routine exercises of equipment. That is, from time to time maintenance personnel may enter requests for routine exercises of equipment by way of the teletypewriter. If such requests exist, action is taken and then control returned to the base level executive program. If no such requests exist, the job supervisory program determines whether or not there are any automatically scheduled routine jobs to be performed. That is, purely on a basis of time, certain routine tests are performed. Finally if all of the above jobs have been completed, the job supervisory program makes a time check and schedules routine jobs in accordance with the present time and then, after this has been completed, proceeds to so-called low order gap filling maintenance jobs.

It must be understood that at each successive execution of the sublevel L.sub.e job supervisory program the same priority is applied and it is possible that demand routine exercises, automatically scheduled routine jobs, etc., may not be served by many successive executions of the L.sub.e job supervisory program.

Claims

We claim:

1. In combination:

memory means containing a plurality of sequences of program order words and system data;

said sequences including timed interrupt program sequences;

said program order words including inhibit interrupt order words;

a central control comprising; means for obtaining information from said memory means, means for writing information into said memory means and means responsive to said information obtained from said memory means for executing said sequences of program order words;

clock means for generating signals defining machine cycles and times within said machine cycles and means responsive to said clock signals for generating timed interrupt signals;

interrupt means responsive to said timed interrupt signals for momentarily halting the execution of said program order words upon completion of the work functions of the order word being executed at the time said timed interrupt signal occurs;

means for initiating said timed interrupt program sequence; and

said central control further comprising means for delaying the response of said interrupt means to said timed interrupt signals when said order word being executed at the time of occurrence of said timed interrupt signal is said inhibit interrupt program order word.

2. In combination:

memory means containing sequences of program order words and data, said sequences including;

(a) a base level program sequence,

(b) timed interrupt program sequences, and

(c) maintenance interrupt program sequences,

a central control comprising;

means for reading information from said memory means and for writing data into said memory means, means for executing said program sequences, means for initiating the execution of said base level program sequences;

clock means defining machine cycles and times within said machine cycles;

interrupt timing means responsive to said clock signals for generating cyclically recurring timed interrupt signals;

timed interrupt means responsive to said timed interrupt signals for momentarily halting the execution of said base level program sequences and for initiating said timed interrupt program sequences;

a plurality of operational checking means for checking the execution of said base level program sequences and said timed interrupt program sequences and for generating a trouble signal upon detection of trouble in said execution; and

maintenance interrupt means responsive to said trouble signals for halting the execution of said timed interrupt program sequences and said base level program sequences and for initiating execution of said maintenance interrupt program sequences.

3. The combination in accordance with claim 2 wherein:

said maintenance interrupt program sequences comprise a plurality of program sequences discrete to said operational checking means;

said maintenance interrupt means comprises a plurality of maintenance interrupt sources discrete to associated ones of said maintenance interrupt program sequences and to associated ones of said operational checking means,

said operational checking means check the execution of said maintenance interrupt program sequences and generate trouble signals upon detection of trouble in execution thereof; and

certain of said maintenance interrupt sources being responsive to trouble signals of their associated operational checking means to halt the execution of certain of said maintenance interrupt program sequences and to initiate execution of said maintenance interrupt program sequences associated with said certain maintenance interrupt sources.

4. In combination:

a memory system containing sequences of program order words and system data;

a central control comprising means for reading information from said memory and for executing said sequences,

said system data includes an ordered list of classes of base level jobs to be performed;

said list defining a base level executive program and comprising a plurality of sublevel entries with identical sublevel entries for each time a class of job is to be performed in the execution of said base level executive program; and

said program sequences including sequences for executing said base level executive program.

5. The combination in accordance with claim 4 wherein:

said system data includes a plurality of job request registers uniquely associated with said classes of jobs;

said sequences of program order words include a plurality of sublevel job supervisory program sequences uniquely associated with said classes of jobs and a plurality of job program sequences;

said central control comprises means for entering job requests in said job request registers;

means responsive to said sublevel job supervisory program sequences for examining said job request registers to detect job requests and to generate job request signals; and

means responsive to said job request signals to initiate execution of a selected one of said job program sequences.

6. In combination:

a memory system containing sequences of program order words and system data;

said memory system including a plurality of job request registers, certain of said job request registers being interject registers a central control comprising means for reading information from said memory system and for executing said sequences of program order words;

said sequences of program order words including base level program sequences and timed interrupt program sequences;

said base level program sequences including interject program sequences;

means for reading information from said memory system and for writing data into said memory system;

means for executing said program sequences;

means for initiating the execution of said base level program sequences;

clock means defining machine cycles and times within said machine cycles;

interrupt timing means responsive to said clock signals for generating timed interrupt signals;

timed interrupt means responsive to said timed interrupt signals for momentarily halting the execution of said base level program sequences and for initiating said timed interrupt program sequences;

said timed interrupt program sequences including interject request recording program sequences;

said central control responsive to the execution of said interject request program sequences for entering interject requests in said interject request registers;

said central control responsive to the execution of said base level program sequences for examining said interject request registers to generate interject request signals upon detection of an interject request; and

said central control responsive to said interject request signals during the execution of said base level program sequences to initiate said interject program sequences.

7. In combination:

memory means containing sequences of program order words and system data, said memory means comprising a plurality of interrupt registers;

said sequences including a base level program sequence and interrupt program sequences, a central control comprising reading means for reading information from said memory means;

writing means for writing data into said memory means, a plurality of flip-flop registers,

means for executing said program sequences;

means for initiating the execution of said base level program sequence;

a plurality of interrupt sources for generating interrupt signals;

means responsive to said interrupt signals for interrupting the execution of said base level program sequences, for enabling said writing means to write into said interrupt registers the contents of a first plurality of said flip-flop registers, to reset a second plurality of said flip-flop registers and to selectively initiate the execution of said interrupt program sequences;

said interrupt program sequences including a go back to normal program order word, and said central control comprises means responsive to the execution of the said go back to normal order word for enabling said reading means to read from said data store the contents of said interrupt registers;

means for inserting in said first plurality of flip-flop registers the contents of said interrupt registers; and

means for initiating said base level program sequence to first execute the order word in the sequence following the order word which was being executed at the time said interrupt signal occurred.

8. The combination in accordance with claim 7 wherein said means for executing said program sequences comprises decoding means responsive to said program order words, and said means responsive to the execution of said go back to normal order word comprises a go back to normal sequencer which generates signals for momentarily inhibiting the operation of said decoding means and enabling said reading means.

9. In combination:

memory means containing sequences of program order words and system data;

said sequences including a base level program sequence and a plurality of interrupt program sequences;

said memory means comprises a plurality of interrupt registers discrete to said interrupt program sequences;

a central control comprising: reading means for reading information from said memory means;

writing means for writing data into said memory means;

means for executing said program sequences;

means for initiating the execution of said base level program sequences;

a plurality of flip-flop registers;

a plurality of interrupt sources for generating a plurality of discrete interrupt signals unique to said interrupt program sequences;

means for selectively enabling said interrupt sources; and

means responsive to said discrete interrupt signals for enabling said writing means to place the contents of certain of said flip-flop registers in the interrupt register discrete to the enabled interrupt source and to initiate the interrupt program sequence discrete to the enabled interrupt source.

10. In combination:

memory means containing sequences of program order words and system data;

said sequences including a base level program sequence and an interrupt program sequence;

said base level program sequences including interrupt sensitive program sequences;

a central control comprising means for reading information from said store and for writing data into said data store;

means for executing said program sequences;

means for initiating the execution of said base level program sequences;

an interrupt occurred flip-flop;

means for generating interrupt signals;

means responsive to said interrupt signals to set said interrupt occurred flip-flop to a first state, to momentarily halt the execution of said base level program sequences and to initiate said interrupt program sequences;

means responsive to the execution of said interrupt program sequences for halting the execution of said interrupt program sequences and for reinitiating the execution of said base level program sequences;

means responsive to the execution of said interrupt sensitive program sequences including means for examining the state of said interrupt occurred flip-flop; and

means responsive to the state of said interrupt occurred flip-flop for modifying the execution of said interrupt sensitive program sequences.

11. In combination:

memory means containing sequences of program order words and data;

said sequences including base level program sequences; interrupt program sequences and test interrupt program sequences;

said base level program sequences including maintenance program sequences;

a central control comprising means for reading information from said memory means and for writing data into said memory means;

means for executing said program sequences;

means for initiating the execution of said base level program sequences;

means for generating interrupt request signals;

a test interrupt flip-flop;

means responsive to the execution of said maintenance program sequences to set said test interrupt flip-flop to a first state; and

means responsive to said interrupt request signals and to an output signal of said test interrupt flip-flop to initiate the execution of said test interrupt program sequence and to reset said test interrupt flip-flop.

12. In combination:

a program store containing a plurality of sequences of program order words;

said sequences including base level program sequences and interrupt program sequences;

a data store containing system data;

a central control comprising means for reading information from said stores and for writing data into said data store;

means for executing said program sequences;

means for initiating the execution of said base level program sequences;

means for generating interrupt signals; and

means responsive to said interrupt signals for momentarily halting the execution of said base level program sequences upon completion of the work functions of the order word being executed at the time said interrupt signal occurred and for initiating the execution of said interrupt program sequences.

13. In combination:

memory means containing sequences of program order words and data;

said sequences including a base level program sequence and interrupt program sequences;

said program sequences including reference point program sequences;

a central control comprising means for reading information from said memory means and for writing data into said memory means;

means for executing said program sequences;

means for initiating the execution of said base level program sequence;

means for generating interrupt signals;

means responsive to said interrupt signals to momentarily halt the execution of said base level program sequences and to initiate said interrupt program sequences;

operational checking means for observing the execution of said interrupt program sequences and for generating trouble signals upon detection of trouble in execution thereof;

an interrupt trouble occurred register responsive to said trouble signals to set said register to a first state;

means responsive to the execution of said interrupt program sequences for halting the execution of said interrupt program sequences; and

means responsive to the halting of said interrupt program sequences and the state of said interrupt trouble occurred flip-flop to initiate the execution of said reference point program sequences.

14. In combination:

memory means containing information comprising sequences of program order words and system data;

said sequences including call processing and maintenance program sequences and a plurality of interrupt program sequences;

a central control;

said central control comprising means for obtaining said information from said memory means;

means for writing data into said memory means;

means for executing said sequences of program order words;

a plurality of interrupt sources uniquely associated with said interrupt program sequences;

said interrupt sources being assigned a relative interrupt priority level in an ordered priority arrangement;

a plurality of interrupt level activity flip-flops;

means for selectively enabling said level activity flip-flops;

means for selectively enabling said interrupt sources; and

interrupt sequencer means responsive to output signals of said interrupt sources and of said level activity flip-flops to initiate execution of the interrupt program sequence associated with the enabled interrupt source having the highest relative level of priority.

15. The combination in accordance with claim 14 wherein a plurality of said interrupt sources are assigned the same relative level of priority; wherein said interrupt program sequences comprise interrupt level program sequences and interrupt source program sequences; and wherein said interrupt sequencer initiates execution of the interrupt level program sequence associated with the enabled interrupt source having the highest relative priority to record in said memory means the contents of a portion of said central control and to examine the states of said plurality of interrupt sources associated with said interrupt level program sequence to generate an output signal defining an interrupt source program sequence associated with an enabled one of said plurality of interrupt sources; and further comprising means responsive to said output signal for initiating execution of the interrupt source program sequence associated with said enabled interrupt source.

16. In combination:

a central processor comprising a program store containing information comprising sequences of program order words and system data;

said sequences including call processing and maintenance program sequences and a plurality of interrupt program sequences;

a data store containing information comprising additional system data;

a central control;

said central control comprising means for obtaining said information from said stores;

means for writing data into said data store;

a go back to normal sequence circuit;

means for executing said sequences of program order words;

a plurality of interrupt sources uniquely associated with said interrupt program sequences;

said interrupt sources being assigned a relative interrupt priority level in an ordered priority arrangement;

a plurality of interrupt level activity flip-flops;

means for selectively enabling said level activity flip-flops;

means for selectively enabling said interrupt sources;

interrupt sequencer means responsive to output signals of said interrupt sources and of said level activity flip-flops to initiate the execution of the interrupt program sequence associated with the enabled interrupt source having the highest relative level of priority;

means responsive to the execution of said initiated interrupt program sequence to reset the interrupt source associated with said sequence being executed;

said initiated interrupt program sequence including a go back to normal order word; and

means responsive to said go back to normal order word for enabling said go back to normal sequence circuit to reset said level activity flip-flop associated with the initiated interrupt program sequence.

17. A central processor for a program controlled electrical control system comprising:

a program store containing sequences of program order words for controlling the operation of said control system;

a data store containing data relating to the operation of said system and ordered pairs of words defining maintenance program sequences;

a central control;

means in said central control for reading program orders from said program store;

means in said central control for generating code-addresses for reading said ordered pairs of words; and

means responsive to said ordered pairs of words for controlling said control system.

18. A program controlled data processing system comprising:

a central data processor comprising a program store containing sequences of program order words and data;

a data store for storing a plurality of words of data and pairs of words comprising maintenance program sequences;

a central control;

said central control comprising means responsive to said program order words for controlling said data processing and for reading information from said stores and for writing information into data store;

said central control further comprising operational checking means to detect incorrect responses of said central data processor; and

said central control responsive to output signals of said operational checking means to initiate execution of said data store maintenance program sequences.

19. In combination:

a program store containing information comprising sequences of program order words and system data;

a data store containing information comprising additional system data and ordered pairs of words defining maintenance program sequences;

a central control comprising means for obtaining said information from said stores;

means for writing data into said data store;

means for executing said sequences of program order words;

sequencer means for obtaining from said data store said ordered pairs of words;

operational checking means for generating a trouble signal upon detection of trouble in obtaining a particular ordered pair of words; and

said sequencer means responsive to said trouble signals for rereading said data store to reobtain said particular ordered pair of words.

20. The combination in accordance with claim 19 wherein said operational checking means is responsive to the rereading of said data store to check the obtaining of said data words and to generate a fault signal upon detection of trouble in obtaining information by said rereading.

21. In combination:

a program store containing sequences of program order words and data;

a data store;

a central control comprising means for reading information from each of said stores;

decoding means responsive to program order words read from said program store for controlling said central control;

checking means in said central control responsive to information read from said program store for checking the plausibility of said information;

said checking means effective to generate an error signal upon detection of an implausible response; and

means responsive to said error signals for momentarily interrupting the operation of said central control and for generating a program store command for rereading said program store at the address from which said implausible information was obtained.

22. The combination in accordance with claim 21 wherein:

said means responsive to said error signals comprises;

a program store reread sequence circuit; and

said program store reread sequence circuit effective to inhibit said decoding means and to control portions of said central control in effecting said rereading.

23. In combination:

a program store containing sequences of program order words and data, a data store for storing a plurality of words of data and a central control;

said central control comprising means responsive to said program order words for reading information from said stores and for writing information into said data store;

a plurality of operational checking means to detect incorrect responses of said central data processor and to generate a trouble signal upon detection of an incorrect response;

means discrete to each of said operational checking means for recording the occurrence of said trouble signals;

remedial means discretely enabled in response to said trouble signals for carrying out particular remedial actions, and a plurality of error counting registers discrete to each of said trouble signals; and

each of said remedial means including means for incrementing said error counting register by a count of 1 each time said remedial means is enabled.

24. In combination:

a program store containing sequences of program order words and data, a data store containing system data and a central control;

said central control comprising means for generating commands for reading information from said stores;

means for executing said program orders obtained from said program stores;

operational checking means for checking the validity of responses obtained from said program store and for generating trouble signals upon detection of an invalid response; and

remedial means responsive to said trouble signal to obtain information to replace said invalid response.

25. The combination in accordance with claim 24 wherein said operational checking means is responsive to said information obtained by said remedial means to check the validity of said data and to generate a fault signal upon detection of invalid data.

26. The combination in accordance with claim 25 wherein said central control comprises:

means for recording the code-address of the location in said program store from which said invalid response was obtained;

a flip-flop discrete to said fault signal for recording the occurrence of said fault signal; and

means responsive to said fault signal for initiating further remedial work functions.

27. In combination:

a program store containing sequences of program order words, certain of said order words being single cycle order words and others of said order words being multicycle order words;

a data store containing system data;

a central control comprising means for reading information from said stores and for writing information into said data store;

decoding means responsive to information read from said program store for generating output signals for controlling said central control;

said output signals including a plurality of unique sequencer enable signals;

clock means defining a central control machine cycle and a plurality of times within said cycle;

said central control responsive to output signals of said decoding means to execute said single cycle orders at the rate of one single cycle order per machine cycle and to execute said multicycle orders at a rate less than one order per machine cycle;

said central control further comprising multicycle sequencer means responsive to said sequencer enable signals for inhibiting output signals of said decoding means and for carrying out specified central control work functions defined by said unique sequencer enable signals;

a plurality of operational checking means for checking the responses of said central processor during the enablement of said multicycle sequencer means and for generating a trouble signal upon detection of an improper central processor response; and

means responsive to said trouble signals for momentarily inhibiting the action of said multicycle sequencer means and for carrying out remedial system work functions.

28. In combination:

a program store containing sequences of program order words;

a data store containing system data;

a central control;

said central control comprising means for obtaining information from said program store and from said data store and for writing information in said data store;

said central control comprising means for obtaining information from said stores and for executing said sequences of program order words;

said central control concurrently operative with respect to a plurality of order words of said sequences;

a plurality of operational checking means for checking the execution of each of said program order words and for generating a trouble signal discrete to said operational checking means upon detection of trouble in said execution;

a plurality of remedial means;

each of said remedial means associated with one of said operational check means;

said remedial means enabled by trouble signals of said associated operational check means;

output signals of certain of said recording means comprising inhibit signals to certain other remedial means not associated with said recording means to momentarily inhibit the operation of said nonassociated remedial means.

29. In combination:

a program store containing sequences of program order words;

a data store;

a central control comprising means for reading information from each of said stores;

decoding means responsive to program order words read from said program store for controlling said central control;

operational checking means responsive to information read from said data store for checking the plausibility of said information;

said checking means generating a trouble signal upon detection of implausible information; and

means responsive to said trouble signal for momentarily interrupting the operation of said central control and for generating a data store reread command for rereading said data store at the address from which said implausible information was obtained to obtain reread data.

30. he combination in accordance with claim 29 wherein said operational checking means is responsive to said reread data to check the validity of said data and to generate a fault signal upon detection of implausible data.

31. The combination in accordance with claim 30 wherein said central control comprises:

means for recording the code-address of the location in said data store from which said implausible information was obtained;

a flip-flop discrete to said fault signal for recording the occurrence of said fault signal; and

means responsive to said fault signal for initiating other remedial work functions.