Digital Counter Driven Pacer

Abstract

The cardiac pacer disclosed herein employs a digital counter driven by a relatively high frequency oscillator to time intervals which simulate various cardiac functions. When allowed to cycle repetitively, the counter provides a relatively slow, fixed rate mode of operation. However, the counter may be reset under certain conditions by ventricular signals to provide a demand mode of operation and by atrial signals under certain other conditions to provide a so-called synchronized mode of operation. Noise rejection circuitry is also disclosed.

Description

BACKGROUND OF THE INVENTION

This invention relates to cardiac pacers and more particularly to such a pacer employing digital circuitry.

In the normal heart, electrical signals are generated and appear in the atrium at a rate of approximately 60 to 120 times per minute, depending on such factors as body size and amount of physical exertion. Approximately 0.1 second after such a signal has appeared in the atrium, it is transferred to the ventricle of the heart, which reacts to the stimulation by contracting. This contraction forces blood from the ventricle into the arterial system and thence to the entire body. The delay between the appearance of an electrical signal in the atrium and its appearance in the ventricle is called the A-V delay. Following the contraction of the ventricle, there is an insensitive period lasting about 0.4 second, during which time the heart is unresponsive to electrical pulses. This time is referred to as the refractory delay period.

A common type of heart failure is irregularity in the generation of atrial potentials. In some cases, these potentials appear at only a low rate; in others, they cease entirely for extended periods though at other times the signals may be generated with perfect regularity. It is in persons suffering from this kind of cardiac disorder that a standby or so-called demand mode pacer is used. This device is designed to apply stimulating pulses to the ventricle, by means of an electrode implanted therein, only when the heart fails to generate pulses spontaneously. When natural pulses regularly appear, the pacer provides no stimulation; when they appear irregularly, the pacer adjusts its timing to integrate its artificial pulses with the natural ones. This type of pacer is often provided with circuitry which simulates the refractory delay period of the heart. The reason for including such delay circuitry is that a spontaneous electrical signal which appears a short time after delivery of an artificial pulse is ineffective to pump blood, either because the natural refractory period of the heart caused the heart to ignore the spontaneous pulse or because the ventricle has not had time following the previous beat to be refilled with blood. A simulated refractory period causes the pacer likewise to ignore these ineffective beats. The device's timing continues just as if the beats had never occurred.

Another form of heart disease is the so-called A-V block in which the patient's heart undergoes normal or near-normal atrial contraction but the atrial signal is not transferred to the ventricle. With such a patient, it is desirable to use a so-called synchronous pacer which detects atrial signals and supplies to the ventricle a stimulating pulse about 0.1 second later, a period which constitutes a simulated A-V delay. In the absence of detected atrial signals, the pacer supplies ventricular pulses at a fixed rate. The synchronous pacer, like the demand pacer, is often provided with refractory delay simulation.

A drawback of pacers presently in use is their relatively large size. While this does not affect the ease of installation in any but the rarest patients, it is easier to hermetically seal the pacer package if it is of smaller volume. Such sealing is desirable because it eliminates the possibility that body fluids will seep into the device and damage it. Such hermetic sealing employing metallic members can also be employed to shield the pacer from electromagnetic interference.

Another problem presented by currently-used pacers is their finite battery life. Recent improvements have extended battery life to the neighborhood of 2 years, but increasing this time still constitutes an important improvement by reducing the frequency of battery replacements which require surgery.

Among the several objects of the present invention may be noted the provision of a cardiac pacer which is highly reliable and stable; which provides very accurate timing; which is protected from dangerous operation caused by ambient electrical noise; which has very low power consumption and thus yields long battery life; which is relatively compact; which will operate in a demand mode providing either an inhibit demand or synchronous demand operation; which will operate in a straight synchronous mode; which can provide a fixed rate operation; and which is relatively inexpensive. Other objects and features will be in part apparent and in part pointed out hereinafter.

SUMMARY OF THE INVENTION

Briefly, a cardiac pacer according to the present invention times various events and delays by means of a digital counter which is driven by an oscillator operating at a frequency which is a relatively large multiple of a normal heartbeat rate. A cardiac stimulating pulse is generated at a predetermined point in the count. Thus, if the counter cycles repetitively, the heart is stimulated at a predetermined fixed rate. To provide demand mode operation, the counter is reset in response to spontaneous cardiac signals thereby to prevent stimulation when the heart is functioning normally. To provide synchronous mode operation, the counter is reset to a point preceding the stimulation count by an amount which simulates a normal A-V delay.

The use of digital count down circuitry permits both the various delays and the durations of the stimulating pulses to be accurately timed. Further, by counting down from a relatively high frequency, an oscillator having a relatively short duty cycle may be used so as to reduce battery drain. Further, the use of a relatively short oscillator period permits timing components, e.g. capacitors, of relatively small size to be used.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block logic diagram of a cardiac pacer of this invention;

FIG. 2 is a block logic diagram of another embodiment of the pacer incorporating noise detection circuitry; and

FIG. 3 is a block logic diagram of still another embodiment.

Corresponding reference characters indicate corresponding parts throughout the several views of the drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 1, the apparatus illustrated there is adapted for use as either a demand or synchronous mode cardiac pacer, separate output terminals, 6 and 9 respectively, being provided for the two modes. Depending on the mode of operation desired, an electrode which is implanted in a location suitable for stimulating ventricular contraction is connected to one or the other of these output terminals. A single input terminal, designated 10, is employed for both modes, the electrode connected to this input terminal being placed in contact with the ventrical for demand mode operation and in contact with the atrium for synchronous mode operation. In demand mode operation, the terminals 6 and 10 may in fact both be connected to the same lead.

Timing of the different events occurring in the operation of this apparatus is provided by a digital counter 3. The counter is driven by an oscillator 1 which establishes the time base. As illustrated, counter 3 comprises a nine stage binary divider and the oscillator 1 runs at a frequency which is relatively high with respect to the contemplated range of heartbeat rates or frequencies. Since the counter 3 requires only a very short triggering pulse, the duty cycle of oscillator 1 is preferably relatively short to reduce battery drain.

As is conventional, counter 3 provides a two-state output signal for each stage of binary division, these signals being designated C1--C9. The counter also provides signals which are the binary complements of these signals, these complementary signals being designated . In the embodiments illustrated herein, only the C1, C7, C8, C9 and signals are utilized and thus only these signals are designated on the drawings but, as will be apparent to those skilled in the digital circuitry arts, other combinations of output signals may be used if different event timings are desired. Positive logic is assumed.

As is also conventional, the counter 3 run cyclically, that is, the states of the binary output signals pass through a sequence which repeats after all the possible combinations have been utilized. With the nine stage binary counter illustrated, the number of possible states is 2.sup.9 or 512. Further, the counter may at will be reset to a predetermined starting point by the application of a reset signal to a reset terminal, designated R. The starting point of the counter is considered herein to be the zero count and the various possible states or counts are considered to be zero through 511. At zero count, the output signals C1--C9 are low and the output signals are positive or high.

The output signal from the counter 3 is applied to the clock input terminal, designated C, of a so-called D-Type flip-flop 16 and the C1 signal is applied to the reset terminal R of this flip-flop. D-type flip-flops are available commercially in integrated circuit form from several manufacturers and their operation is generally as follows. The device responds to a positive-going voltage transition on the clock input terminal, designated C, by making the logic level output on an output terminal, designated Q, identical to the logic level present at an input terminal designated D, at the time of the positive-going transition at the C terminal. Thereafter the Q output signal remains the same, ignoring changes in the D input signal, until another positive-going transition is applied at the clock input C. The device may also be reset by the application of a high or positive signal to a reset terminal designated R. The reset function overrides all others; as long as a high level is present at the R terminal, the output signal at Q is low regardless of changes at the D or C terminals. A signal which is the binary complement of the signal present at terminal Q is provided at a terminal designated .

Cardiac signals applied to the input terminal 10 are amplified and shaped by means of an amplifier 11 so as to be squared into waveforms suitable for use with digital circuitry, as is understood by those skilled in the art. The square signals thereby obtained are applied to the clock terminal C of a second D-type flip-flop 17. The C9 signal is applied to the D input of this flip-flop and the output signal from the oscillator 1 is applied to the reset terminal R. The Q output signal from flip-flop 17 is applied to the reset terminal R of the counter 3 while the output signal from this flip-flop is applied to the D input terminal of the first flip-flop 16.

The Q output signal from the flip-flop 16 is applied to the input terminal of an amplifier 21 which responds to a positive input signal by applying to the output terminal 6 a voltage level which is suitable for cardiac stimulation.

The portions of the apparatus thus far described are those employed in providing operation in the demand mode and that operation is substantially as follows. Assuming initially that no cardiac signals are applied to the input terminal 10 and that flip-flop 17 is in its reset condition so that the respective output signal is high, the counter 3 will run indefinitely in its cyclic mode. Thus, when the count changes from 511 to 0, the output signal will experience a positive-going transition and the positive output signal present at the D input terminal of flip-flop 16 will be transferred to its Q output terminal. On the next count, however, the flip-flop 16 will be reset by the C1 signal as the C1 signal goes positive on count 1. It can thus be seen that, with no detected cardiac signals, the pacer will generate a stimulating pulse having a duration of one oscillator cycle for every 512 oscillator cycles. Assuming that the oscillator 1 operates at 590 c.p.s., the apparatus will thus deliver 1.7 millisecond pulses at the rate of approximately 70 pulses per minute which is an appropriate timing for nonsynchronous or demand mode cardiac stimulation.

During the counting from zero to the intermediate count of 255, the C9 output signal is low and thus, even if cardiac signals are received, the flip-flop 17 will not change state. This insensitive period simulates the refractory delay of the heart and prevents any interaction between the output and input circuits of the pacer. From count 256 through count 511, however, the C9 signal is high and thus a cardiac signal received during this latter interval will cause the flip-flop 17 to change states and the resulting high signal applied to the terminal R of the counter 3 will cause the counter to be reset to its zero count. Simultaneously with the resetting of the counter 3, the Q signal from flip-flop 17 goes low so that, even though the resetting of the counter produces a positive-going transition in the C9 signal, no change of state is produced in the flip-flop 16 and thus no output signal is generated. On the next count after the resetting of counter 3, the flip-flop 17 is reset by the oscillator output signal. Received cardiac signals are typically of sufficient duration to span more than one cycle of the oscillator so that the flip-flop 17 will change state at least once even if the cardiac signal is initiated during a period when the oscillator output signal is high.

From the foregoing, it can be seen that, if the patient's heart is beating normally at a rate which is more than the free running rate of the pacer, i.e. about 70 beats per minute, and not more than twice that rate, i.e. about 140 beats per minute, the counter 3 will be reset to its zero count by each natural heartbeat before a count of 511 is reached. Thus, the patient's heart will not be stimulated at all if it is beating spontaneously within this 2 -to- 1 range of rates. However, if no spontaneous heartbeat is detected between count 256 and count 511, the pacer will then stimulate the patient's heart at the end of the full count period, that is, after a period which corresponds to the 70 pulse per second free running rate. In other words, the difference between the starting point count and the end of the counting sequence establishes a maximum interval between heartbeats. Accordingly, if the spontaneous heart signals disappear intermittently, the pacer will integrate its operation with the normal heartbeat.

The generation of a synchronous pacing signal is controlled by means including a third D-type flip-flop 18. The C8 and C9 signals are combined in a NOR gate 27 to provide a signal which is high from count 0 through count 127. The resultant signal is applied to the D input terminal of flip-flop 18. The C7 signal is applied to the clock input terminal C of this flip-flop and the C1 signal is applied to its reset terminal R. The output signal provided at the Q terminal of flip-flop 18 is amplified by an amplifier 33 to provide at output terminal 9 a signal level suitable for cardiac stimulation.

The C7 signal experiences a positive-going transition at counts 64, 192, 320 and 448 but only the transition at count 64 can produce a change in state of the flip-flop 18 since the D input is low at the other three transition points. Accordingly, it can be seen that flip-flop 18 will be put into its so-called set state each time the counter 3 reaches a count of 64. Further, the flip-flop 18 will be reset on the next count, i.e. count 65, by the C1 signal. Thus, each time the counter reaches a count of 64, a cardiac stimulating pulse having a duration of one oscillator cycle will be provided at the output terminal 9.

When the apparatus illustrated in FIG. 1 is to be utilized in the synchronous mode, the input terminal 10 is connected to an electrode which is implanted so as to detect atrial signals. The resetting of counter 3 is controlled in response to detected signals as described previously. Thus, the counter is reset to its zero count if an atrial signal is detected from count 256 through count 511. A stimulating pulse is then generated at output terminal 9 when count 64 is reached. The delay provided by the interval between the resetting and the 64 count is about 108 milliseconds which satisfactorily simulates the normal A-V delay. Thus the heart is stimulated with timing appropriate for synchronous pacer operation.

From the time that the counter 3 is reset until count 256 is reached, the input circuit is insensitive to detected cardiac signals just as it was in the demand mode of operation described previously. Thus, the interval from count 64 to count 256 provides a simulated refractory period during which the apparatus will not respond to input signals. Accordingly, interaction between the input and output circuits is prevented, as is the overly rapid stimulation of the heart due to premature detected signals.

If no atrial signals at all are detected, the counter 3 will run cyclically as described previously and stimulating pulses will be generated at a fixed rate, one pulse being generated each time the counter 3 passes the 64 count. Accordingly, if there is failure of the heart to generate atrial signals or if the input lead should break, the generation of stimulating pulses will not fail altogether but will lapse into the relatively slow free-running rate.

As noted previously, electrical noise present in certain environments can interfere with cardiac pacer operation by introducing false input signals which improperly modify the operation of the pacer. The embodiment illustrated in FIG. 2 includes circuitry for identifying interfering electrical noise and preventing it from causing a dangerous mode of operation. The embodiment of FIG. 2 is essentially the same as the apparatus of FIG. 1 except for the addition of those components which condition the effect of input signals. The amplifier 11 also drives a counter 35 which, as illustrated, comprises a two stage binary divider. Counter 35 provides, at an output terminal designated Q35, a signal which has a positive-going transition after four input signals have been counted. The signal from gate 27 is applied to a reset terminal R on counter 35 for resetting counter 35 to its zero count during counts 0 through 128 of counter 3.

The output signal from counter 35 is applied to the clock input terminal C of a fourth D-Type flip-flop 38. A Logic High Signal is applied to the D input terminal of flip-flop 38 and the Q output signal from flip-flop 16 is applied to the reset terminal R of flip-flop 38. The Q output signal from flip-flop 38 is combined with the signal from counter 3 in a NOR gate 44 and the resultant signal is applied to the D input terminal of the flip-flop 17 in place of the straight C9 signal which was employed in the embodiment of FIG. 1.

Assuming that the flip-flop 38 is in its reset condition and that the counter 3 has just reached a count of 128 so that the counter 35 has just been reset and the signal applied to the D input of flip-flop 38 is high, the operation of this noise detection circuitry is as follows. Detected input signals advance the counter 35. If more than four input signals are received before the counter 3 reaches a count of 256, the flip-flop 38 will be caused to change states, that is, to be put into its so-called set condition. In this set condition, the flip-flop 38 applies a high signal to the NOR gate 44. Thus, the NOR gate will provide a low signal to the D input of flip-flop 17 regardless of the state of the signal. Accordingly, detected input signals which are passed by the amplifier 11 to the clock input C of flip-flop 17 cannot cause that flip-flop to change states and thereby reset counter 3 as described previously. If the counter 3 is not reset, the apparatus then provides stimulating pulses at the relatively slow free running rate in the same manner as if no input signals were received. If fewer than four input signals are received between the count of 128 and the count of 256, the flip-flop 38 does not change states and the flip-flop 17 becomes responsive to input signals received after counter 3 reaches a count of 256 as described previously.

In summary, it can be seen that this noise detection circuitry operates by counting received signals for a predetermined period which precedes the normal sensitive period and by providing a fixed rate or free-running mode of operation if more than a predetermined number of input signals are detected during this period. In other words, the detection of input signals at a relatively high repetition rate is taken as an indication that interfering electrical noise is present and the pacer then ignores all detected signals for the remainder of the fixed rate cycle. While genuine cardiac signals may be ignored as a result of this mode of operation, the reversion to fixed rate operation is deemed preferable to the random rate of stimulation which might otherwise occur in the case of synchronous mode operation or the complete cessation of stimulation which might otherwise occur in the case of demand mode operation. This noise detection circuitry thus provides an advantageous protective feature in either mode of operation.

The standby demand mode operation provided by the circuits of FIGS. 1 and 2 is of the so-called inhibit type, that is, no output pulses are produced if normal heart signals are detected. The embodiment illustrated in FIG. 3, which is basically similar to the FIG. 1 embodiment, is arranged to provide so-called synchronous demand operation. A NAND gate 45 combines the output signal from flip-flop 16 with the output signal from the reset flip-flop 17. The NAND gate then drives the output amplifier 21.

The NAND gate 45 reinverts the inverted or complemented output signal from flip-flop 16 so that, when no input signal is received, this circuit operates as the FIG. 1 circuit to provide stimulation at a fixed rate. When a ventrical signal is detected, causing the counter 3 to be reset as before, an output pulse is also generated immediately due to the signal from flip-flop 17. However, since the ventrical is already starting to contract, the stimulus from the pacer is effectively disregarded. This type of operation avoids the possible conflicts of rhythm that may be present with a fixed-rate pacer, for example, when A-V mode conduction is restored. If desired, switching means can be incorporated to permit both inhibit demand and synchronous demand modes.

A form of synchronous demand operation can also be provided using the circuit of FIG. 1 without change by connecting the output terminal 9 to the input terminal 10 and to a ventrical lead. With this arrangement a pulse is generated a short interval after a normal ventricle signal is detected but this pulse is again ineffective since it occurs within the refractory period. If no input pulses are detected the apparatus lapses into a fixed rate mode of operation as in the other arrangements discussed.

It should be understood that certain variations on the preferred embodiments of these pacers are within the spirit of the invention. The binary dividers, for example, could be replaced by other binary logic devices such as ring counters, shift registers, or the like. Similarly, the NOR gates could be replaced by other gates. If desired, the stimulating pulse duration could be determined by a one-shot multivibrator. These changes could be made with only relatively minor alterations in the circuitry as well as changes in the logic.

An advantage of the use of digital circuitry for providing the various timing functions is that the various components, e.g., the counters, gates and flip-flops, can be constructed in integrated circuit form using presently available devices. Further, by custom designing the integrated circuitry using presently available fabrication techiques, the entire pacer can be constructed on a single semiconductor substrate thereby further reducing size, eliminating hand-wired circuit interconnections and facilitating hermetic sealing. Further, such integrated circuits have relatively low power consumptions.

In view of the above, it will be seen that the several objects of the invention are achieved and other advantageous results attained.

As various changes could be made in the above constructions without departing from the scope of the invention, it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

Claims

We claim:

1. Cardiac pacer apparatus comprising: an oscillator providing a pulsating signal at a preselected frequency, which preselected frequency is a relatively large multiple of a normal heart beat rate; a cyclically operating digital counter means for counting the pulsations of said pulsating signal; and means controlled by said counter for generating a cardiac stimulating potential when said counter reaches a predetermined count.

2. Apparatus as set forth in claim 1 wherein said means for generating said cardiac stimulating potential includes means for initiating the generation of said potential at the start of one cycle of said pulsating signal and for terminating the generation of said potential at the start of the next cycle of said pulsating signal.

3. Apparatus as set forth in claim 1 further comprising: means for detecting cardiac signals generated during a heartbeat; and means responsive to such detected cardiac signals for setting said counter to a starting point count which precedes said predetermined count by a number corresponding to a preselected maximum interval between successive heartbeats whereby a stimulating potential is generated only if said preselected maximum interval elapses between heartbeats.

4. Apparatus as set forth in claim 3 including means controlled by said counter for inhibiting resetting of said counter when the count held thereby is between said starting point count and a count which is intermediate said starting point count and said predetermined count, the difference between said starting point count and the intermediate count corresponding to a preselected refractory delay period.

5. Apparatus as set forth in claim 4 further comprising:

a second digital counter for counting signals detected by said detecting means;

means controlled by said second digital counter for inhibiting resetting of the first said counter between said intermediate count and said predetermined count if more than a predetermined number of detected signals are counted by said second counter during the interval between a count which is intermediate said starting point count and said intermediate count whereby rapidly repeated electrical noise signals reaching said detecting means are ineffective to prevent generation of a stimulating potential at said predetermined count.

6. Apparatus as set forth in claim 1 further comprising means for detecting atrial signals; and means responsive to such detected atrial signals for setting said counter to a starting point count, which precedes said predetermined count by a number corresponding to a preselected A-V delay whereby stimulating potentials are generated in synchronously timed relationship to said atrial signals.

7. Apparatus as set forth in claim 6 including means controlled by said counter for inhibiting resetting of said counter when the count held thereby is between said predetermined count and a subsequent count, the difference between said predetermined count and said subsequent count corresponding to a predetermined refractory delay period.

8. Apparatus as set forth in claim 7 further comprising:

a second digital counter for counting signals detected by said detecting means;

means controlled by said second digital counter for inhibiting resetting of the first said counter between said subsequent count and said starting point count if more than a predetermined number of detected signals are counted by said second counter during the interval between: a count which is intermediate said predetermined count and said subsequent count; and said subsequent count, whereby rapidly repeated electrical noise signals reaching said detecting means are ineffective to prevent generation of a stimulating potential at said predetermined count.

9. Cardiac pacer apparatus comprising:

an oscillator providing a pulsating signal at a preselected frequency, which preselected frequency is a relatively large multiple of a normal heart beat rate;

a cyclically operating digital counter means for counting the pulsations of said pulsating signal;

means for initiating the generation of a cardiac stimulating potential starting at a predetermined count and for terminating the generation of said potential at a subsequent count;

means for detecting cardiac signals generated during a heartbeat;

means for setting said counter to a starting point count which precedes said predetermined count by a number corresponding to a preselected maximum interval between successive heartbeats in response to cardiac signals which are detected after a count which is intermediate said starting point count and said predetermined count, the difference between said starting point count and the intermediate count corresponding to a preselected refractory delay period.

10. Apparatus as set forth in claim 9 further comprising:

a second digital counter for counting signals detected by said detecting means;

means controlled by said second digital counter for inhibiting resetting of the first said counter between said intermediate count and said predetermined count if more than a predetermined number of detected signals are counted by said second counter during the interval between: a count which is intermediate said starting point count and said intermediate count; and the first said intermediate count, whereby rapidly repeated electrical noise signals reaching said detecting means are ineffective to prevent generation of a stimulating potential at said predetermined count.

11. Cardiac pacer apparatus comprising:

an oscillator providing a pulsating signal at a preselected frequency, which preselected frequency is a relatively large multiple of a normal heartbeat rate;

a cyclically operating digital counter means for counting the pulsations of said pulsating signal;

means for initiating the generation of a cardiac stimulating potential starting at a predetermined count and for terminating the generation of said potential at a subsequent count;

means for detecting atrial signals;

means for setting said counter to a starting point count which precedes said predetermined count by a number corresponding to a preselected A-V delay in response to atrial signals which are detected after a subsequent count which is after said predetermined count by a number corresponding to a preselected refractory delay period.

12. Apparatus as set forth in claim 7 further comprising:

a second digital counter for counting signals detected by said detecting means;

means controlled by said second digital counter for inhibiting resetting of the first said counter between said subsequent count and said starting point count if more than a predetermined number of detected signals are counted by said second counter during the interval between: a count which is intermediate said predetermined count and said subsequent count; and said subsequent count, whereby rapidly repeated electrical noise signals reaching said detecting means are ineffective to prevent generation of a stimulating potential at said predetermined count.