U.S. patent number 3,835,260 [Application Number 05/342,323] was granted by the patent office on 1974-09-10 for communication switching system, with marker, register, and other subsystems coordinated by a stored program central processor.
This patent grant is currently assigned to GTE Automatic Electric Laboratories, Inc.. Invention is credited to Kenneth E. Prescher, Ronald E. Schauer, Frank B. Sikorski.
United States Patent |
3,835,260 |
Prescher , et al. |
September 10, 1974 |
COMMUNICATION SWITCHING SYSTEM, WITH MARKER, REGISTER, AND OTHER
SUBSYSTEMS COORDINATED BY A STORED PROGRAM CENTRAL PROCESSOR
Abstract
A stored program computer is used for functions such as digit
analysis and routing control where flexibility is important, while
a wired logic time division multiplex register-sender subsystem is
used to receive dialing and other call signals and to control
outpulsing which require relatively fixed functions of a repetitive
nature. A reed relay switching network is controlled by wired logic
markers which perform path selection functions as well as supplying
operating potentials for the network relays. The originating marker
also performs the function of scanning the lines for originating
calls, identifying the calling line and selecting a path through
the network to a register junctor. Direct data communication is
provided between the originating marker and the data processor
computer for sending an originating message identifying the calling
line and the register junctor. There is also a direct communication
path from the computer to the terminating markers to send them
messages identifying terminals to be connected to complete a call.
The data processor includes a separate drum memory system with its
own processing logic circuits for performing functions such as
translations and providing an extended memory for some programs for
the computer. The data processor computer communicates with the
register-sender subsystem by direct access to the register-sender
memory on a random basis, arranged so as not to interfere with the
cyclical access by the register-sender subsystem.
Inventors: |
Prescher; Kenneth E. (Lombard,
IL), Schauer; Ronald E. (Hanover Park, IL), Sikorski;
Frank B. (Des Plaines, IL) |
Assignee: |
GTE Automatic Electric
Laboratories, Inc. (Northlake, IL)
|
Family
ID: |
26828199 |
Appl.
No.: |
05/342,323 |
Filed: |
March 19, 1973 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
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130133 |
Apr 1, 1971 |
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Current U.S.
Class: |
379/237; 379/273;
379/290; 379/269; 379/279; 379/302 |
Current CPC
Class: |
H04Q
3/54583 (20130101); H04Q 2213/13057 (20130101); F02B
2075/027 (20130101) |
Current International
Class: |
H04Q
3/545 (20060101); F02B 75/02 (20060101); H04q
003/54 () |
Field of
Search: |
;179/18ES |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Brown; Thomas W.
Attorney, Agent or Firm: Franz; B. E.
Parent Case Text
This is a continuation-in-part of application Ser. No. 130,133
filed Apr. 1, 1971, now abandoned.
Claims
What is claimed is:
1. A communication switching system comprising:
a switching network having a plurality of terminals, a plurality of
line circuits individually connecting communication lines to
individual ones of said terminals, a plurality of register junctors
individually connected to other of said terminals;
originating marker means and terminating marker means for
controlling the switching network, each of the marker means
including apparatus to select a path and establish a connection
between two selected terminals, the originating marker means
further including means to detect originating call requests via the
line circuits and to select and identify one calling line circuit
at a time for service, to select an idle junctor for the call, and
to select and establish an originating connection between the
originating line circuit and the selected register junctor;
a register subsystem including a register memory which has junctor
memory areas permanently assigned to the register junctors, and
common logic means, time division multiplex means with sequential
cyclically recurring time slots for the register junctors to access
the junctor memory areas and the associated register junctors to
process information from the memory and the register junctor and to
store data into the junctor memory area;
a data processing unit which includes a central processor and a
central processor memory,
data communication means interconnecting the central processor with
the originating marker means and the terminating marker means,
the originating marker means including means effective after said
originating connection between a calling line circuit and a
register junctor has been selected to seize the data communication
means and transmit an originating data message identifying the
calling line circuit and register junctor terminals to the central
processor,
means in the central processor responsive to receipt of said
originating data message to assign a portion of the central
processor memory to the call as a call history table;
means in the data processing unit to find class of service
information relating to the calling line to be used in processing
the call,
data transfer means interconnecting the central processor and the
register subsystem,
means effective after the central processor has assigned said call
history table to a call to transmit information via the data
transfer means to a register subsystem for storage in the junctor
memory area for the register junctor which has been selected for
the call;
the register subsystem being effective to receive and store dialed
digits for the call, and to transmit information relating to the
dialed digits via said data transfer means to the central processor
for processing,
the central processor including means to process the call and
transmit a terminating data message via said data communication
means to the terminating marker means,
the terminating marker means being responsive to the receipt of the
terminating data message to select a path and establish a
connection in the switching network between the calling line
circuit and a selected terminating terminal;
and means responsive to both the register subsystem and the central
processor as well as the terminating marker means completing their
functions for a call to return both the junctor memory area and the
call history table to an idle state.
2. A communication switching system as claimed in claim 1, wherein
said central processor comprises a stored program computer
operating with said central processor memory.
3. A communication switching system as claimed in claim 2, wherein
said data processing unit includes an auxiliary processor having
its own memory including apparatus for associative searches,
arranged to operate with said central processor to receive data
therefrom, to use the associative search apparatus to find
correspondence between a part of the data and information in the
memory of the auxiliary processor, to extract related information
from the memory of the auxiliary processor and return it to the
central processor, while the central processor is independently
proceeding with the execution of other routines.
4. A communication switching system as claimed in claim 3, wherein
the memory of the auxiliary processor is used as an extended memory
for storing programs which upon request from the central processor
are transferred to the central processor memory for execution, the
transfer being effected without interference with the simultaneous
processing of other routines by the central processor.
5. A communication switching system as claimed in claim 4, wherein
said auxiliary processor is a drum memory system in which its
memory comprises magnetic drum means.
6. A communication switching system as claimed in claim 2, wherein
said data transfer means interconnecting the central processor and
the register subsystem comprises means for a direct access from the
central processor to the register memory on a random access basis,
with means to prevent interference with the sequential access by
the register subsystem to the junctor areas in the respective time
slots.
7. A communication switching system as claimed in claim 6, wherein
said common logic means of the register subsystem includes wired
logic with sequence control means.
8. A communication switching system as claimed in claim 1, wherein
said originating marker means and terminating marker means each
include wired logic apparatus with sequence control means, and
wherein said data communication means interconnecting the central
processor with the originating marker means and the terminating
marker means comprises serial data transmission apparatus.
9. A communication switching system as claimed in claim 8, wherein
said register subsystem includes sending means for outpulsing on
calls to other offices; wherein for all the dial pulse mode of
direct current signaling, there is an arrangement comprising
multiplex means to effectively connect the common logic means and
the register junctors during their respective time slots for
receiving and sending from or to relay repeating means in the
register junctors;
wherein for tone signaling comprising a combination of tones for
each digit, there are provided receivers and senders and a
switching matrix for selectively connecting them to the register
junctors, each receiver or sender being accessed on a time-division
multiplex basis from the common logic during the time slot
associated with the register junctor to which it is connected.
10. A communication switching system as claimed in claim 9, wherein
said central processor and said register subsystem are each
provided in duplicate and operated in synchronism to process the
same call information, with each central processor normally
communicating with a given one of the register subsystems, one of
the central processor-register subsystem combinations being on line
to supply output information ot other subsystems, and wherein the
system may be reconfigured with either central processor
communicating with either register subsystem, and any combination
of them being on line to supply output information.
11. A communication switching system as claimed in claim 10,
wherein said originating marker means is duplicated with both
operating simultaneously, interlocked so that any given call
request is served by only one originating marker; and wherein said
terminating marker means is duplicated and arranged to operate only
one at a time, with reconfiguration means permitting either
originating marker means or either terminating marker means to be
temporarily taken out of service.
12. A communication switching system as claimed in claim 11,
wherein said data processing unit includes an auxiliary system with
its own memory, the auxiliary system being duplicated, with both or
either central processor working with either auxiliary system.
13. A communication switching system as claimed in claim 12,
wherein the system includes a control section comprising one said
data processing unit and either one or two said register subsystems
depending upon the call processing traffic load of the system, and
wherein in a control section comprising two register subsystems
said data transfer means comprises an arrangement for the central
processor to selectively communicate with the register memories of
both register subsystems.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a processor controlled communication
switching system, and more particularly to a system using a stored
program computer processor and separate wired logic processors.
2. Description of the Prior Art
Today there are a number of applications for highly reliable
program-controlled data processing systems which have a real time
demand on the system services. One example is a modern
communication switching system for voice and/or data
communication.
Such a data processing system has operational requirements such as
an ability to cope with real time demands and an extremely high
degree of system dependability. The term "real time" as employed
herein, means that the processor must be capable of coping with all
requests without significant delay, and the term "dependability"
means that the system shall remain operative even though it has all
the frailties of a man-made device.
There are many known common control communication switching
systems, some of which use exclusively wired logic controlled
common systems, and others of which use primarily stored program
control for the common functions. Examples of a wired logic
controlled system are disclosed in U.S. Pat. No. 3,170,041 by K. K.
Spellnes, and U.S. Pat. No. 3,299,214 by K. E. Prescher et al.
While such systems perform many of the common control functions
well, it has become desirable in a modern system to have the
flexibility of a stored program control. However, systems
concentrating substantially all of the common functions in a single
stored program control data processor may be unable to cope with
the real time demands on such a system for high traffic density,
particularly in emergency situations in which the demand may be
several times the capability of the system. A communication
switching system using multi-processors to divide the tasks
involved in call processing is disclosed in U.S. Pat. No. 3,408,628
by R. L. Brass et al. While the multiprocessing approach increases
the capacity of a system such that the normal call processing
ability may be greatly increased, it is still possible in unusual
situations that the processing apparatus may become greatly
overloaded to the extent that the amount of output is actually
decreased because of the time spent in serving new requests. It
would be desirable to have a system arrangement such that the
number of call requests presented to the central data processing
system is limited so as not to exceed its capacity.
SUMMARY OF THE INVENTION
An object of the invention is to provide a switching system using
an optimum combination of wired logic and stored program control.
Another object is to provide a system in which the stored program
data processor does not have its call handling capacity actually
reduced due to overloading during periods of unusually high demand.
Still another object is to provide a system which has a high degree
of maintainability to provide the required dependability to insure
continuous service.
According to the invention a communication switching system
comprises wired logic markers arranged to independently find idle
paths and establish connections through the switching network, and
the markers further include means to detect originating call
requests from calling line circuits and for each call request to
establish an originating connection for the call to an idle
register junctor; a separate register subsystem including the
register junctors arranged to receive and store call digits for
each call; a data processing unit is provided for processing the
call data; data communication arrangement is provided
interconnecting the data processing unit with the markers, and a
data transfer arrangement is provided interconnecting the data
processing unit with the register subsystem; with the markers
having arrangements effective after the originating connection
between the calling line circuits and the register junctor has been
established to seize the data communication path and transmitting
and originating data message identifying the calling line circuit
and register junctor terminals to the central processor.
In the preferred form of the invention the data processor includes
a stored program control computer, while the markers and the
register subsystem use wired logic control. In the preferred
embodiment the register subsystem uses a time division multiplex
arrangement with cyclical access to its memory for serving the
register junctors. For data transfer between the data processor
computer and the register subsystem the computer has direct access
on a random access base to the register subsystem memory.
According to a further feature of the invention, the data
processing system includes a separate relatively slow speed
processing system for functions such as translations between
directory number and equipment number line designations, and also
for providing an extended memory for storing programs for the
computer. In the disclosed embodiment the memory for this system is
a magnetic drum system.
CROSS-REFERENCE TO RELATED APPLICATIONS
The register-sender subsystem for this system is generally similar
to that disclosed in U.S. Pat. No. 3,301,963 by D. K. K. Lee et al.
for a Register-Sender Arrangement for a Communication Switching
System Common Control Arrangement. The markers for the system are
generally similar to the arrangement disclosed in U.S. Pat. No.
3,293,368 by W. R. Wedmore for a Marker for a Communication
Switching Network.
The above patents relate to a prototype system which did not
include a stored program computer central processor.
The system covered by the present application, known as No. 1 EAX,
or simply EAX, has some of the subsystems thereof described in the
following U.S. patent applications, which are incorporated herein
and made a part hereof as though fully set forth. The system
disclosed herein uses integrated-circuit electronic logic
circuits.
The memory access, and the priority and interrupt circuits for the
register-sender subsystems are covered by U.S. Pat. application
Ser. No. 139,480, filed May 3, 1971 now U.S. Pat. No. 3,729,715,
issued May 3, 1973, by C. K. Buedel for a MEMORY ACCESS APPARATUS
PROVIDING CYCLIC SEQUENTIAL ACCESS BY A REGISTER SUBSYSTEM AND
RANDOM ACCESS BY A MAIN PROCESSOR IN A COMMUNICATION SWITCHING
SYSTEM, hereinafter referred to as the REGISTER-SENDER MEMORY
CONTROL patent application. The register-sender subsystem is
described in U.S. Pat. application Ser. No. 201,851 filed Nov. 24,
1971, now U.S. Pat. No. 3,737,873 issued Nov. 24, 1973, by S. E.
Puccini for DATA PROCESSOR WITH CYCLIC SEQUENTIAL ACCESS TO
MULTIPLEXED LOGIC AND MEMORY, hereinafter referred to as the
REGISTER-SENDER patent application. Maintenance hardware features
of the register-sender are described in four U.S. Pat. applications
having the same disclosure filed July 12, 1972, Ser. No. 270,909,
now U.S. Pat. No. 3,784,801, by J. P. Caputo and F. A. Weber for a
DATA HANDLING SYSTEM ERROR AND FAULT DETECTING AND DISCRIMINATING
MAINTENANCE ARRANGEMENT, Ser. No. 270,910, now U.S. Pat. No.
3,783,255 by C. K. Buedel and J. P. Caputo for a DATA HANDLING
SYSTEM MAINTENANCE ARRANGEMENT FOR PROCESSING SYSTEM TROUBLE
CONDITIONS, Ser. No. 270,912 by C. K. Buedel and J. P. Caputo for a
DATA HANDLING SYSTEM MAINTENANCE ARRANGEMENT FOR PROCESSING SYSTEM
FAULT CONDITIONS, and Ser. No. 270,916, now U.S. Pat. No.
3,783,256, by J. P. Caputo and G. O'Toole for a DATA HANDLING
SYSTEM MAINTENANCE ARRANGEMENT FOR CHECKING SIGNALS, these four
applications being referred to hereinafter as the REGISTER-SENDER
MAINTENANCE PATENT APPLICATIONS.
The marker for the system is disclosed in the U.S. Pat. No.
3,681,537, issued Aug. 1, 1972 by J. W. Eddy, H. G. Fitch, W. F.
Mui and A. M. Valente for a MARKER FOR COMMUNICATION SWITCHING
SYSTEM, and U.S. Pat. No. 3,678,208, issued July 18, 1972 by J. W.
Eddy for a MARKER PATH FINDING ARRANGEMENT INCLUDING IMMEDIATE
RING; and also in U.S. Pat. applications Ser. No. 281,586 filed
Aug. 17, 1972 by J. W. Eddy for an INTERLOCK ARRANGEMENT FOR A
COMMUNICATION SWITCHING SYSTEM, Ser. No. 311,606 filed Dec. 4, 1972
by J. W. Eddy and S. E. Puccini for a COMMUNICATION SYSTEM CONTROL
TRANSFER ARRANGEMENT, Ser. No. 303,157 filed Nov. 2, 1972 by J. W.
Eddy and S. E. Puccini for a COMMUNICATION SWITCHING SYSTEM
INTERLOCK ARRANGEMENT, hereinafter referred to as the MARKER
patents and applications.
The communication register and the marker transceivers are
described in U.S. Pat. application Ser. No. 320,412 filed Jan. 2,
1973 by J. J. Vrba and C. K. Buedel for a COMMUNICATION SWITCHING
SYSTEM TRANSCEIVER ARRANGEMENT FOR SERIAL TRANSMISSION, hereinafter
referred to as the COMMUNICATIONS REGISTER patent application.
DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a telephone switching exchange;
FIG. 2 is a block diagram of the system showing the duplication of
the subsystems of FIG. 1 and the reconfiguration control;
FIG. 3 is a block diagram showing how the computer central
processor interfaces with other units of the data processing unit
and of a register sender subsystem which together form the common
control of the switching system;
FIG. 3A is a block diagram in a computer central processor showing
a data bus and an address bus interconnecting a plurality of
registers;
FIG. 4 is a functional block diagram of the processor timing
control;
FIG. 5 is a functional block diagram showing the sources for data
bit .phi.;
FIGS. 6 and 7 are functional block diagrams showing the data bus
sources for all bit positions;
FIG. 8 is a functional block diagram showing the address bus
sources for bit .phi.;
FIG. 9 is a functional block diagram showing all of the address bus
sources;
FIG. 10 is a functional block diagram of the instruction
register;
FIG. 11 is a functional block diagram of the Y and S registers;
FIG. 12 is a functional block diagram of the arithmetic logic
unit;
FIG. 13 is a functional block diagram of the A and Q registers;
FIG. 14 is a functional block diagram of the program count and last
program count registers;
FIG. 15 is a block diagram of the index registers and a shift
register;
FIG. 16 is a timing diagram for the instruction ADM (add to
memory);
FIG. 17 is a block diagram of the computer line processor
interfaces with other subsystems;
FIG. 18 is a block diagram of the computer memory control and drum
systems;
FIGS. 19 and 19A comprise a drum access circuit block diagram;
FIG. 20 is a diagram of a drum segment, word organization;
FIGS. 21 and 22 are flowcharts for drum access circuit peripheral
adapter read and write transfer;
FIG. 23 is a drum control unit block diagram;
FIG. 24 is a graph of the down control unit timing;
FIGS. 25 and 25A comprise a diagram of the block transfer module of
the drum control unit block diagram;
FIGS. 26, 26A and 26B comprise a flowchart for read sequence and
write sequence in the drum memory system;
FIGS. 27 and 27A comprise a flowchart for termination sequence in
the drum memory system;
FIGS. 28 and 28A comprise a block diagram for associative search
control in the drum memory system;
FIGS. 29 and 29A comprise an MLS flowchart for the drum memory
system;
FIGS. 30 and 30A comprise an SLAS flowchart for the drum memory
system;
FIGS. 31, 31A, 31B, 32 and 32A comprise an MLS control actions
flowchart for the drum memory system;
FIGS. 33 and 33A are an MLS decision table for the drum memory
system;
FIG. 34 is a DCU sequence flowchart for the drum memory system;
FIG. 35 is a block diagram of the input/output system;
FIG. 36 is a diagram interface information between the
register-sender and the data processing unit;
FIG. 37 is a layout diagram of the register-sender memory;
FIG. 38 is a layout diagram of the storage area in memory for one
register;
FIG. 39 is a diagram of the call history table;
FIGS. 40-46 are layout diagrams of the call history table contents
during time frames .phi.-6 respectively;
FIG. 47 is a field program block diagram flowchart;
FIG. 48 is a typical layout of a portion of the main core
memory;
FIGS. 49-69 are memory diagrams and flowcharts for the executive
program;
FIG. 70 is a combined hardware and software simplified flowchart
for a local-to-local call;
FIGS. 71-103B are call processing software flowcharts; and
FIGS. 104-125A are executive software flowcharts.
GENERAL SYSTEM DESCRIPTION
Referring now to FIG. 1 of the drawings, there is shown a system
100 which incorporates the principles of the present invention and
which comprises a line group 110, a selector group 120, a data
processor unit 130, a maintenance and control center 140 for the
data processor unit, a trunk-register group 150, an originating
marker 160, a terminating marker 170, and a register sender 200.
The line group 110 includes reed-relay switching networks A, B, C
and R for providing local lines L000 to L999 with a means of
accessing the system 100 for originating calls and for providing a
means of terminating calls destined for local customers. The
trunk-register group 150 also includes reed-relay switching
networks A and B to provide access to the system 100 for incoming
trunks 152 from distant offices, and to route trunk calls through
the system to local customers or to outgoing trunks 120 to distant
offices. The selector group 120 forms an intermediate switch and
may be considered the call distribution center of the switching
system 100. The selector group 120 routes calls appearing on its
inlets to appropriate destinations, such as local lines or other
offices represented by outgoing trunks, by means of reed-relay
switching networks A, B and C. Thus, the line group 110, the
trunk-register group 150, and the selector group 120 form the
switching network for the system 100 and provide full-metallic
paths through the office for signaling and transmission.
As seen in FIG. 1, the originating marker 160 provides high-speed
control of the switching networks to connect the calls entering the
system 100 to the register sender 200. The terminating markers 160
control the switching networks of the selector group 120 for
establishing connections therethrough. If a call is to be
terminated on a customer's line within the office, the terminating
marker 170 sets up a connection through both the selector group 120
and the line group 110 to the customer's line.
The register sender 200 provides for receiving and storing of
incoming digits, and for outpulsing digits to distant offices, when
required. Incoming digits in the dial pulse mode, in the form of
touch calling multifrequency signals from local lines, or in the
form of multifrequency signals from incoming trunks are
accommodated by the register sender 200. A group of register
junctors RRJ provides an interface for the incoming digits which
are transferred to tone receivers 201 via a sender-receiver matrix
RSX. A ferrite-core memory RCM stores the digital information via a
memory access circuit RMA under the control of a common logic
control 202. Digits may be outpulsed by dial pulse generators or
multifrequency senders 203, which are selectively connected to the
register junctors RRJ via the sender-receiver matrix RSX. The
common logic control 202, the memory access RMA, and the core
memory RCM form the register apparatus of the present invention,
and provide a pool of registers for storing call processing
information received via the register junctors RRJ. The information
is stored in the core memory RCM on a time division multiplex
basis, and the memory RCM can be accessed by the data processor
unit 130 on a random access basis.
The data processor unit 130 provides stored-program computer
control for processing calls through the system 100. Instructions
provided by the unit 130 are utilized by the register sender 200
and other subsystems for processing and routing of the call. The
unit 130 includes a drum memory 131 for storing, among other
information, the equipment number information for translation
purposes. A pair of drum control units, such as the unit 132
cooperate with a main core memory 133 and control the drum 131. A
central processor 135 accesses the register sender 200 and
communicates with the main core memory 133 to provide computer
control for processing calls through the system 100. A
communication register 134 transfers information between the
central processor and the originating markers 160 and the
terminating markers 170. An input/output device buffer 136 and a
maintenance control unit 137 transfer information between the
maintenance and control center 140.
The maintenance and control center 140 provides a centralized
facility for interfacing between the attendant and the system
equipment. The center 140 provides displays and alarms to monitor
system operation, and includes input-output devices, such as a
teletypewriter 142, tape punch and tape reader unit 144, and a
maintenance console 145, which cooperates with the maintenance
control unit 137 of the data processor unit 130.
Line Group
The line group 110 is an equipment group which enables lines L000
to L999 to access the system 100. The line group 110 is also the
equipment group from which lines L000 to L999 are accessed. In
step-by-step electromechanical systems, each line has a dual
appearance, one at a linefinder for originating calls and the other
at a connector for receiving calls. In the system 100 of the
present invention, customer lines have only one appearance which is
at the line group for both originating and receiving calls.
The line group 110 may be considered to be a large switching
network which provides two-way switching to 1,000 lines. For larger
size offices, such as a 10,000 line exchange, additional line
groups and other equipment are provided. On an originating call,
the line group 110 provides concentration from 1,000 lines to 140
originating junctors. Each originating junctor provides a split
between calling and called parties while the call is being
established, thereby providing a separate path for signaling. On a
terminating call, the line group 110 provides expansion from 120
terminating junctors to 1000 lines being served. The terminating
junctors provide ringing control, battery feed, and line
supervision for calling and called lines. Crosspoint switching
networks, such as A network 111 and B network 112, are switching
matrices and form a full-metallic path for signaling and
transmission.
The line group 110 also includes line circuits LC1 to LC1,000,
which are individually associated with the lines L000 to L999. The
line circuits LC1 to LC1,000 each include line and cut-off reed
relays to provide a call-for-service on an originating call, to
mark the line busy on an originating or terminating call, and to
remove the attachments from the line on a terminating call.
The line matrices are arranged in four stages -- A, B, C and R. The
crosspoints used in the A, B, and C stages are two-winding three-
or four-contact reed relay crosspoints. The R stage crosspoints are
two-winding ten-contact crosspoints. The line matrices establish
connections to the originating junctors and the register junctors
RRJ of the register sender 200 from the lines L000 to L999
connected to their inlets for originating calls. The line matrices
also establish connections to terminating junctors 170 to the lines
L000 to L999 on terminating calls.
The A and B stages provide paths to the originating junctors and
provide concentration from 1000 line inlets to 140 originating
junctors. The R stage provides a temporary connection between the
originating junctor and the register junctor RRJ on originating
calls.
The A, B, and C stages provide paths from terminating junctors for
terminating calls. Both originating and terminating calls are
connected through the A and B stages, with separate outlets being
provided on the B stage to originating junctors and C stages for
handling each type of call. The C stage operates during terminating
calls only, and provides a matrix that distributes the traffic from
120 terminating junctors to all parts of the A and B stages. This
traffic is then expanded to a maximum of 1000 line inlets.
An originating junctor is used for every call originating from a
local line, and remains in the connection for the duration of the
call. The originating junctor extends the calling line's signaling
path to the register junctor RRJ in the register sender 200, and at
the same time provides a separate signaling path from the register
sender to the selector group 120 for outpulsing, when required. The
originating junctor isolates the calling line until cut-through is
effected, at which time the calling party is switched through to
the selector group inlet. The originating junctor also provides
line lock-out.
A terminating junctor is used for every terminating call and
remains in the connection for the duration of the call. Its
functions include ringing control, battery feed, and line
supervision for calling and called lines.
There is provided a connect and access circuit (not shown) which is
associated with the line matrices of the line group 110. The
purpose of this circuit is to provide a means for connecting a
marker to a matrix or a junctor to permit the marker to manipulate
them, to perform tests on them, and to receive information from
them.
Selector Group
The selector group 120 is an equipment group which provides
intermediate mixing and distribution of the traffic from various
trunks and junctors on its inlets to various trunks and junctors on
its outlets. The outlets of the selector group 120 are arranged so
that a path may be selected to one of a group of equipment on its
outlets. Line groups are connected to a plurality of outgoing
trunks 121 or other line groups through the selector group 120, and
a plurality of incoming trunks 152 are connected to line groups or
outgoing trunks through the selector group. An analogy may be made
between the functions of the selector group 120 of the system 100,
and those of selector switches of the electromechanical
step-by-step system.
The selector group 120 comprises a selector matrix, such as the A
stage 122, to provide the signaling and transmission paths, and
connect and access equipment (not shown) which controls the
selector group 120 in response to the terminating marker 170. The
crosspoints used to form the switching network in the selector
group 120 are two-winding four-contact reed relays.
The selector matrix comprises three switching stages -- A, B, and
C. The function of the three-stage selector matrix is to
interconnect the originating junctors, the incoming trunks, and
special local facilities, such as the insertion junctor 123, with
the terminating junctors, the outgoing trunks 121, intertoll, EAS,
toll terminating, and special local facilities on a "fan-out"
basis.
The connect and access circuit (not shown) associated with the
selector matrix of the group selector provides a means for
connecting the terminating marker 170 to a matrix to control the
matrix, to permit the marker to perform tests on it, and to receive
information from the matrix. Only the terminating marker 170 can
access the selector matrix.
Trunk-Register Group
The trunk-register group 150 provides access to the system 100 from
the group of incoming trunks 152, or special feature junctor
circuits (not shown).
The trunk-register group comprises a two-stage trunk-register
matrix to provide the signaling and transmission paths, and connect
and access circuitry (not shown) which controls the matrix of the
trunk-register group in response to the originating marker 160.
The trunk-register matrix provides a signaling path from the
distant party, via the associated trunk or junctor to the register
junctor RRJ, and a signaling path between the register junctor RRJ
and the selector group 120. Thus, the trunk-register matrix
provides the connection for the trunk or junctor to the register
junctor RRJ during sending and receiving of dial pulse or tone
signaling.
Originating Marker
The markers used in the system 100 are electronic units which
control the selection of idle paths and the establishment of
connections through the matrices. The originating marker 160
detects calls for service in the line and/or trunk-register group
150, and controls the selection of idle paths and the establishment
of connections through these groups. On line-originated calls, the
originating marker 160 detects calls for service in the line
matrix, controls path selection between the line and originating
junctors, and between originating junctors and register junctors.
On incoming trunk calls, the originating marker 160 detects calls
for service in the incoming trunks connected to the trunk-register
150 and controls path selection between the incoming trunks 152 and
register junctors RRJ.
Originating markers are provided in pairs, operating simultaneously
but not in synchronism. In case of marker fault, the redundant
marker can handle the entire traffic load. Ordinarily, the same
originating markers are used for setting up connections through
both line and trunk-register matrices. When the traffic warrants
it, originating markers are provided separately for the line matrix
and for the trunk-register matrix in an office. The marker pair
handling incoming trunk traffic in a selector section only can
serve up to 10 trunk-register groups.
The communication transceiver accepts data from the assigner, inlet
control, and outlet control circuits as to the identity of the
matrix accessed, inlet saved, and junctors to be used to service
the call. The communication transceiver forwards this data to the
data processor unit. For maintenance, the transceiver is used by
the data processor unit to gather status information from the
marker for analysis of fault conditions, and to instruct the marker
to change status, i.e., on-line to off-line. It is also used to
establish test calls for the purpose of error and fault separation.
Test call results determine reconfiguration and later enable
detailed diagnostics to be performed.
The originating marker can work in a reverse mode as well. That is,
the data processor sends a frame of data to the communications
transceiver, indicating inlet identity, and originating and
register junctors identity. This mode is employed when routining
the office equipment. In this case, the inlet control will access
only the inlet indicated. The outlet control section will be
restricted to a particular junctor if a junctor identity has been
included in the data frame. The communications transceiver then
returns a data frame response to the data processor unit as in a
normal call.
Terminating Marker
The terminating marker 170 controls the selection of idle paths and
the establishment of connections for terminating calls. The
terminating marker 170 controls the establishment of all calls
through the selector matrix of the selector group 120 and, in the
case of a call terminating on a local line, establishes connections
through the line matrix of the line group 110.
The marker connects an inlet of the selector group 120 to an idle
junctor or trunk circuit. If the call is to a local line, the
terminating marker selects the idle terminating junctor and
connects it to a line group inlet, as well as connecting it to a
selector group inlet. For this purpose, the appropriate idle
junctor is selected and a path through a line group 110 and the
selector group 120 is established.
A terminating marker is designed to serve up to 8 selector groups
and up to 10 line groups when serving an office section and up to
10 selector groups when serving a selector section. They are
provided in pairs and operate alternately. One of the markers of a
pair is selected for each termination, but the two markers are not
operated simultaneously. In case of a marker fault, the alternate
marker can handle the entire traffic load.
The communications transceiver is the primary link for signaling
and communicating with the data processor unit, both for call
processing and maintenance activity. Switching instructions are
received from the data processor unit as to a connection to be
established. This information (data) indicates the selector group
inlet to be serviced and the selector group outlets having the
correct junctor or trunk circuit group, and includes information to
be loaded into these junctors or trunk circuits. If the call is to
a line group, the data also indicates the line to which the call is
to be terminated. At the end of call processing, the communications
transceiver returns a data frame (block of information) to the data
processor unit containing the above information along with the
identification of the exact junctor or trunk chosen.
Register Sender
The register sender 200 is a time-shared common control unit with
the ability to register and process 192 calls simultaneously from
local lines or incoming trunks. The register sender 200 provides
the electronic time-shared register apparatus for receiving and
storing incoming digits, and pulse generating sender circuitry to
forward a call toward its destination. In this regard, the register
sender 200 generally includes a plurality of register junctors RRJ
which are space-divided electromechanical access circuits for
providing an interface between the switching matrices of the system
100 and the time-shared register apparatus, which includes the
electronic logic of a common logic control 202, a ferrite-core
memory RCM to store digits to be received and sent via the register
junctors RRJ, and supervisory information pertaining to the call
under the control of the common logic control 202 via a memory
access RMA. A sender-receiver matrix RSX selectively connects a
plurality of tone receivers 201 and senders 203 to the register
junctors RRJ for signaling modes other than the dial pulse mode
which is provided for by the register junctors RRJ.
The time-shared common logic control 202 of the register sender 200
is duplicated and runs identical operations in synchronism with one
another. Under normal conditions, both sets of time-shared
equipment are partially active, one set serving one-half of the
register junctors RRJ and the other set serving the remaining half
of the register junctors RRJ. In case of equipment faults, either
set of time-shared equipment can serve all of the register junctors
RRJ.
The space-divided equipment of the register sender 200 includes the
register junctors RRJ, the senders and receivers, and the
sender-receiver matrix RSX. The register junctors RRJ with their
associated multiplex equipment (not shown) provide an interface
between the space-divided matrix outlets connected to the register
junctors RRJ and the time-shared common logic control 202. The
sender-receiver matrix RSX provides a concentration of the traffic
from the register junctors RRJ to the tone senders and receivers
under the control of the common logic control 202. The senders 203
provide for sending in the multifrequency mode, and the receivers
provide for receiving in either the touch-calling multifrequency
mode from the local lines or the multifrequency mode from the
incoming trunks 152.
The register junctors RRJ are the entry and exit point of the
register sender 200 for information transferred between the
switching network and the register sender. The register junctors
enable the register sender to provide the following features: dial
pulse receiving and sending, coin and party testing, line busy, and
dial tone and reorder tone application. The incoming and outgoing
matrix paths are held by the register junctors RRJ during call
processing. The register junctors comprise electromechanical
components for compatibility with lines, trunks, and switching
network circuits, however they also include electronic interfacing
circuits which are similar to those in the markers for
compatability with the electronic common logic control 202. Signals
from lines, trunks, and network circuits are received by the
register junctors and forwarded to the common logic control for
processing.
The common logic control 202 contains the control logic for call
processing by the register sender 200. The purpose of the common
logic control 202 is to perform all functions associated with
receiving, sending, and timing of digits, and to control processing
of calls by generating commands for other circuits in the register
sender and for the switching network. Since the common logic
control 202 operates on a time-shared basis to store call
processing information in the memory RCM, the common logic control
202 has the ability to register and process 192 simultaneous calls.
The common logic control works closely with the core memory RCM
which together form the register apparatus of the present
invention, and which provides storage of information concerning the
calls in progress and information relating to the data processor
unit 130.
The core memory RCM is a conventional ferrite core memory, which
need not be disclosed in detail. The memory RCM automatically
restores the information in the same cores after a read operation,
and it likewise automatically clears the information from the cores
immediately prior to writing information into them. It is to be
understood that the memory RCM could also be any suitable type of
non-destructive read-out memory.
DATA PROCESSOR UNIT
The data processor unit 130 is the central coordinating unit and
communication hub for the system 100. The data processor unit 130
is in essence a general-purpose computer with special input-output
and maintenance features which enable it to process data. It uses
hardware interrupts with eight levels of priority, and several
sources per level. It has a two-microsecond main memory cycle.
The call processing operation includes control of: the originating
process communication (receipt of line identity, etc.), the
translation operation, route selection, and the terminating process
communication. The translation operation includes: class-of-service
look-up, inlet-to-directory number translations, matrix
outlet-to-matrix inlet translation, code translation, and certain
special feature translations. The maintenance operations include:
monitoring the system for trouble conditions, trouble access to
system units, routining, storage of information about certain calls
being established, trouble diagnosis, and printout. Traffic
operations include: monitoring equipment usage and overloads,
providing the proper response to relieve overload conditions, and
providing a means to measure the quality of service.
The data processor unit assembles information that is received from
markers and the register sender 200 into a series of call
processing instructions which are sent to the markers and register
sender to provide for processing of service demands throughout the
system 100. Storage is also provided for a directory number group
consisting of 25,000 blocks of numbers which can be associated with
up to a maximum of 16 different office codes. A library is
maintained of semi-permanent information concerning each line
inlet's classification, and of tables for use in translating
customer or machine pulse information into switching instructions.
There is also maintained a library of semi-permanent information
concerning the grading of the office and the connection of all
trunks and junctors, and a library of semi-permanent instructions
which are utilized for automated diagnosis and maintenance of all
portions of the system essential to call processing. Required
traffic monitoring functions for calls handled by the system 100
are performed by the unit 130.
The data processor unit is comprised of a computer complex 130 and
a drum memory system. The computer complex is comprised of the
central processor 135, ferrite-core main memory 133, computer
memory control (FIG. 2), and communication links including
communication register 130.
The computer complex 130 is a high-speed digital computer which is
designed for high availability and to allow the system to expand in
both features and additional equipment. This is accomplished
through the inherent flexibility of the stored program and the
orderly expansion of the computer complex 130 with use of modular
design. Through the use of its stored-program capability, the
computer complex 130 is used in call processing for making
high-speed translations. It is also used to control the
communications between all sub-systems.
Another important function of the computer complex 130 is in the
area of maintenance for the entire system. By utilizing its
stored-program capability, the computer complex recognizes error
conditions in other sub-systems, isolates the error to a particular
sub-system; removes it from service and assists in locating the
error to a minimum of replaceable plug-in modules. The computer
complex also provides for communication with other central office
equipment such as ticketers, routiners, and call metering
equipment.
The central processor 135 is the central control unit of the
computer complex 130 and is used to obtain program instructions
stored in the main memory 133, interpret each instruction, and
perform the necessary operations specified by the instruction. The
main memory 133 is a ferrite-core memory and stores the system
control program which is an executive program, and call processing
programs whose frequency of usage requires that they be locally
available.
The drum memory 131 provides mass storage for translation data,
diagnostic programs, tables, and other information. The drum
control unit provides control for transferring information between
the main core memory 133 and the drum memory 131, on a cycle
stealing basis, so that there is no interference with the central
processor in accessing the memory 133.
Either of two possible drum memory arrangements may be employed.
The entire drum may be accessed by one drum control unit. This
method may be used for low traffic on the drum. In the case of high
traffic on the drum, the drum is divided into two storage areas and
a separate drum control unit is provided for accessing each section
of the drum simultaneously.
The drum control unit has the ability to provide two different
search modes; the block transfer or extended memory mode, and the
associative search mode. The block transfer mode of operation is
used in transferring programs and tables between computer core
memory and the magnetic drum. (The programs and tables which are
drum resident are those which are not used frequently enough to
warrant the cost of core residence). The block transfer takes place
via the computer memory control (FIG. 2) without interferring with
the operation of the central processor, which continues its
operation. The location of each word on the drum is uniquely
defined by the segment number and an angular index value. The
angular index value, 1-11,000 defines a drum location relative to a
single fixed reference point (a single pulse on a clock track). A
counter, advanced one count per drum location, is used to develop
the index value. The pulses for advancing and resetting this
counter are derived from clock tracks written on the drum. The drum
index clock track consists of 11,000 consecutive pulses (one for
each location), and the drum reset pulse consists of one pulse per
revolution of the drum.
The associative search mode, used for translations in call
processing, requires an associative search of the information
stored on the drum to find the record to be transferred. This is a
"read only" mode, and the search may be either single-level or
multi-level. This mode likewise proceeds while the central
processor continues operation independently.
Maintenance and Control Center
The maintenance and control center 140 serves as a centralized
facility for interfacing between the operating personnel and the
switching system 100. The center 140 serves as the focal point for
monitoring system and sub-system operation, exercising manual
controls, initiating test call routines and test programs, and
providing print-out of maintenance information. Additionally, the
maintenance and control center 140 provides a visual indication of
all traffic conditions along with sufficient control for switch
management.
The maintenance and control center 140 also provides the interface
for use of optional remote test equipment to provide compatibility
with other testing in the exchange area. The remote test equipment
would be used to provide for testing of lines served by an office
located beyond the supervisory limits of the local test trunks in
the main office.
Multi-Section Offices
A switching unit may be divided into several sections of equipment.
These sections are: (a) office section(s), (b) selector section,
and (c) control section.
Office Section
"Office section" is a term applied to a given grouping of matrices
and markers in an office. The office section includes a number of
line groups, a number of selector groups, a single pair of
terminating markers, one or two pairs of originating markers, and
one or two trunk-register groups. An office section provides a
standardized arrangement of switching equipment for up to 10,000
lines and associated trunks and junctors. The office section may
have up to ten line groups. These line groups will provide up to
10,000 lines (10 .times. 1,000) or 12,500 directory numbers.
Although the office section serves up to 10,000 lines, there is no
association with directory numbers such as a single office code
with the office section. The lines are only associated with respect
to the traffic they generate.
Up to five trunk-register groups may be included in the office
section. These trunk-register groups will provide for up to 1,000
trunk circuits (5 .times. 200) and the special junctors which
require a register junctor. All incoming and two-way trunk circuits
and a few insertion junctors require connection to a trunk-register
group. Most insertion junctors and any intermediate junctors from a
"Selector Section" do not require connection to a trunk register
group.
The office section may have up to eight selector groups. These
groups will provide up to 2400 inlets (8 .times. 300). Since the
line groups will require 1400 or less inlets for originating
junctors (10 .times. 140 maximum), there will be 1000 inlets or
more for junctors and trunk circuits. These will include inlets for
insertion junctors, intermediate junctors, incoming trunk circuits,
and the incoming portion of two-way trunk circuits.
One or two pairs of originating markers may be included in an
office section. One pair of originating markers will handle ten
line groups as well as some trunk-register groups. The number of
trunk-register groups which can be served is a function of traffic.
If all trunk groups are stop-dial trunks, all of the trunk-register
groups may be served by the same marker pair that is serving the
ten line groups. If a large number of inter-digitally switched
trunks must be served, a second originating marker pair may be
required to serve those trunk-register groups which cannot be
served by the first originating marker pair.
A single pair of terminating markers is included in an office
section. The reason for this is that both the office section and
the selector section are built around a terminating marker
pair.
A system switching unit may contain one or two office sections,
equipped as required in accordance with the information presented
in the preceding paragraphs.
When the number of inlets provided by eight selector groups would
be too small, the office must be equipped with a selector section
(incoming portion) or the number of lines and/or trunks per office
section must be reduced. When the number of outlets provided by the
selector groups would be too small, the office must be equipped
with a selector section (outgoing portion) or the number of lines
and/or trunks per office section must be reduced. When the traffic
limits imposed would be exceeded, the number of lines and/or trunks
per office section must be reduced.
The choice of the ultimate number of selector groups within an
office section affords some degree of flexibility. The number
chosen must be made such as to plan for the ultimate sized office.
(This consideration is also true when determining the requirements
for selector group outlets.) If the office will ultimately require
that trunks be served by a selector section, the number of selector
groups may be kept less than the maximum, and new trunks served by
either the selector section or by a second office section so as to
avoid adding a selector group which later would not be
required.
Selector Section
A selector section is a term applied to a given grouping of markers
and matrices in a system. This section is a supplementary section
which provides for trunk switching. The selector section contains
the same equipment as an office section, except it does not have
any line groups and it may have up to ten selector groups. It may
also include up to fifteen trunk-register groups, equipped as
dictated by the number and type of trunks. The selector section may
include up to three originating marker pairs, and a terminating
marker pair.
In any system, the selector section may be referred to by its
function, such as incoming selector section, outgoing selector
section, or a combination of the two. An incoming selector section
extends incoming trunks to office sections and outgoing trunks, and
where required, to an ougoing selector section. An outgoing
selector section extends the outlets of office sections and
incoming trunks, and where required, the outlets of an incoming
selector section, to outgoing trunks. A selector section is
sometimes provided in two parts to function as both an incoming
selector section and an outgoing selector section.
Control Section
The control section is that part of the switching system used to
receive incoming signals from lines or trunks, to control the call
processing and translation, to control switching of the call by the
terminating markers, and send outgoing signals to the line or
trunk. The control section also provides for maintenance and
control of the system.
A control section always contains the following common control
equipment:
a. one register-sender with redundant RS common logic unit and
associated temporary memory for maintainability. Provides for
registering the called number, sending interoffice signaling, and
storage of supervisory information.
b. one data processor, with redundant circuitry, utilizes stored
program control for call processing control, translation,
maintenance, and traffic functions.
c. one maintenance and control center. Provides display and control
for the craftsman.
No switching system may have more than one control section. It may,
however, include two register-senders if traffic warrants it.
SYSTEM OPERATION
This part presents a simplified explanation of how three basic call
types are processed by the system. The following call types are
covered in the order listed: (1) call from a local party served by
one switching unit to another local party served by the same
switching unit, (2) call from a local party served by a switching
unit destined for a party served by a distant office, via an
outgoing trunk, and (3) call coming into the office via an incoming
trunk, and terminating at a local customer's line served by the
switching unit.
In the following presentations, reed relays are referred to as
correeds. All of the data processing operations which take place
are not included.
Local Line-to-Local Line Call
When a customer goes off-hook, the D.C. line loop is closed,
causing the line correed of his line circuit to be operated. This
action constitutes seizure of the equipment, and places a
call-for-service. One originating marker is assigned to the call. A
line identifier in the originating marker upon detecting a
call-for-service scans to select only one line if a plurality are
calling, and identifies the equipment number (matrix and terminal
identity), in the manner disclosed in U.S. Pat. No. 3,211,837 by L.
Bruglemans.
After the marker has identified the calling line number (line
matrix number, AB group number, A unit, and A unit inlet), and has
preselected an idle path identified in terms of the B unit, B unit
outlet, and R unit outlet; this information is loaded into the
marker communication register and sent to the data processor unit
via its communication transceiver.
While sending line number identity (LNI) and route data to the data
processor, the marker operates and tests the path from the calling
line to the register junctor. The closed loop from the calling
station operates the register junctor pulsing relay, contacts of
this relay are coupled to a multiplex pulsing highway.
Upon detecting the pulsing highway and a notification from the data
processor that an origination has been processed to the specified
register junctor, the central control circuits set up a hold ground
in the register junctor. The marker, after observing the register
junctor hold ground and that the network is holding, disconnects
from the matrix. The entire marker operation takes approximately 75
milliseconds.
The data processor unit, upon being informed of a call origination,
enters the originating phase. The originating phase is one of the
three major phases of the call processing function, and can best be
defined as all program functions that are performed from the time
the originating marker informs the data processor of an originating
call until the register-sender is initialized to receive the
incoming digital information.
As previously stated, the "data frame" (block of information) sent
by the marker includes the equipment identity of the originator,
originating junctor and register junctor, plus control and status
information. The control and status information is used by the data
processor control program in selecting the proper function to be
performed on the data frame.
The data processor analyzes the data frame sent to it, and from it
determines the register junctor identity. A register junctor
translation is required because there is no direct relationship
between the register junctor identity as found by the marker and
the actual register junctor identity. The register junctor number
specifies a unique cell of storage in the core memories of both the
register-sender and the data processor, and is used to identify the
call as it is processed by the remaining call processing
programs.
Once the register junctor identity is known, the data frame is
stored in the data processor's call history table (addressed by
register junctor number), and the register-sender is notified that
an origination has been processed to the specified register
junctor.
Following the register junctor translation, the data processor
performs a class-of-service translation. The class-of-service
translation is needed because different inlets on the line matrix
require different services by the system. Included in the
class-of-service is information concerning dial tone, party test,
coin test, type of ready-to-receive signaling required, type of
receiver (if any) required, billing and routing, customer special
features, and control information used by the digit analysis and
terminating phase of the call processing function. The control
information indicates total number of digits to be received before
requesting the first dialed pattern translation, pattern
recognition field of special prefix or access codes, etc.
The class-of-service translation is initiated by the same
marker-to-data processor data frame that initiated the register
junctor translation, and consists of retrieving from drum memory
the originating class-of-service data by an associative search,
keyed on the originator's LNI (line number identity). Part of the
class-of-service information is stored in the call history table
(in the data processor unit core memory), and part of it is
transferred to the register-sender core memory where it is used to
control the register junctor.
Before the transfer of data to the register-sender memory takes
place, the class-of-service information is first analyzed to see if
special action is required (e.g., non-dial lines or blocked
originations). The register junctor is informed of any special
services the call it is handling must have. This is accomplished by
the data processor loading the results of the class-of-service
translation into the register-sender memory words associated with
the register junctor.
The register junctor returns dial tone and the customer proceeds to
key (touch calling telephone sets) or dial the directory number of
the desired party. (Party test on ANI lines is performed at this
time).
The register junctor pulse repeating correed follows the incoming
pulses (dial pulse call assumed), and repeats them to the
register-sender central control circuit (via a lead multiplex). The
accumulated digits are stored in the register-sender core
memory.
In this example, a local line without special features is assumed.
The register-sender requests a translation after collecting the
first three digits. At this point, the data processor enters the
second major phase of the call processing function -- the digit
analysis phase.
The digit analysis phase includes all functions that are performed
on incoming digits in order to provide a route for the terminating
process phase of the call processing function. The major inputs for
this phase are the dialed digits received by the register-sender
and the originator's class-of-service which was retrieved and
stored in the call history table by the originating process phase.
The originating class-of-service and the routing plan that is in
effect is used to access the correct data tables and provide the
proper interpretation of the dialed digits and the proper route for
local terminating (this example) or outgoing calls.
Since a local-to-local call is being described (assumed), the data
processor will instruct the register-sender to accumulate a total
of seven digits and request a second translation. The
register-sender continues collecting and storing the incoming
digits until a total of seven digits have been stored. At this
point, the register-sender requests a second translation from the
data processor.
For this call, the second translation is the final translation, the
result of which will be the necessary instructions to switch the
call through to its destination. The data processor initiates a
request to the drum memory system for a look-up of the local
directory number table (terminating lists) to provide the line
equipment number of the called line and terminating
class-of-service of the called line (including ringing code and
special features). Grouping digits (selector outlet arrays) for the
terminating junctors are obtained from a core-memory table look-up
keyed on the terminating line matrix. The data processor also
requests the drum memory system to determine the selector matrix
inlet identity. This information is assembled in the dedicated call
history table in the data processor core memory. Control is
transferred to the terminating process phase. The digit analysis
phase is complete.
The terminating process phase is the third (and final) major phase
of the call processing function. Sufficient information is gathered
to instruct the terminating marker to establish a path from the
selector matrix inlet to either a terminating local line (this
example) or a trunk group. This information plus control
information (e.g. ringing code) is sent to the terminating
marker.
On receipt of a response from the terminating marker, indicating
its attempt to establish the connection was successful, the data
processor instructs the register-sender to cut through the
originating junctor and disconnect on local calls (or begin sending
on trunk calls). The disconnect of the register-sender completes
the data processor call processing function. The following
paragraphs describe the three-way interworking of the data
processor, terminating marker, and the register-sender as the data
frame is sent to the terminating marker, the call is forwarded to
the called party and terminated.
A check is made of the idle state of the data processor
communication register, and a terminating marker. If both are idle,
the data processor writes into register-sender core memory that
this register junctor is working with a terminating marker. All
routing information is then loaded into the communication register
and sent to the terminating marker in a serial communication.
The register-sender now monitors the ST lead (not shown) to the
network, awaiting a ground to be provided by the terminating
marker.
The terminating marker decodes the line matrix specified for line
termination, determines that the matrix is idle (no originating
marker processing it) and assigns itself to the matrix. The
terminating marker connects to the specified line and selector
matrices by operating dedicated access correeds in the respective
matrices. It then operates connect correeds accessing the selector
inlet, selector AB and BC links, line AB and BC links, and the line
equipment of the called line.
The marker checks the called line to see if it is idle. If it is
idle, the marker continues its operations. These operations include
the pulling and holding of a connection from the originating
junctor to the called line via the selector matrix, a terminating
junctor, and the line matrix. While controlling the path, the
marker makes a series of checks to monitor the proper operation of
the matrices, e.g., links are tested for busy, paths are pulled and
checked for foreign potentials, and the complete path from selector
inlet to line equipment is checked for continuity.
Upon receipt of the ground signal on the ST lead from the
terminating marker, the register-sender returns a ground on the ST
lead to hold the terminating path to the terminating junctor.
When the operation of the matrices has been verified by the marker,
it releases then informs the data processor of the identity of the
path and that the connection has been established. The data
processor recognizes from the terminating class that no further
extension of this call is required. It then addresses the
register-sender core memory with instructions to switch the
originating path through the originating junctor.
The register junctor signals the originating junctor to switch
through and disconnects from the path, releasing the R matrix. The
originating junctor remains held by the terminating junctor via the
selector matrix. The register-sender clears its associated memory
slot and releases itself from the call. The dedicated call history
table (for that register) in the data processor core memory is
returned to idle.
The calling party, now connected to the terminating junctor, loop
seizes the battery-feed (BFI) correed. The terminating junctor
splits the transmission path and connects ringing current to the
called line and ring-back tone to the calling line. When the called
party answers, a closed loop is detected by the ring-trip circuit
of the terminating junctor, which removes ringing and ring-back
tone from the line. The transmission path is completed and
transmission battery is provided to both calling and called
parties.
When the parties are through talking and hang up, the terminating
junctor releases the terminating line matrix and the selector
matrix. Release of the selector matrix releases the originating
junctor which releases the originating line matrix. The cut-off
correeds of both line circuits release, and the customer's line
circuits are idled for future calls.
Local Line-to-Outgoing Trunk Call
The processing of a call originated by a local customer, but
destined for a distant office, is handled the same as previously
described for a "local-to-local" call up to the point where a
three-digit translation has occurred. The digits are analyzed and
it is determined that the call destination is not a local line.
Operation from this point forward is described in subsequent
paragraphs.
For this example, the call is originating from a rotary dial line.
The customer is making a seven-digit EAS (extended area service)
call requiring tandem switching through the connecting office. The
connecting office is equipped for wink-start pulsing. The trunk to
the connecting office is an E and M trunk requiring D.C.
pulsing.
The data processor requests the drum memory system to access the
drum to obtain routing tables from which the following information
is obtained: (a) outgoing trunk group to the connecting office, (b)
selector switching digits for use by the terminating marker, (c)
codes for terminating marker selection or control of outgoing
circuits, (d) signaling and sending modes used on this trunk group,
and (e) alternate routing information.
The drum memory system also provides the originating
junctor-selector inlet translation. The routing information and the
class of the calling party allows the data processor to determine
all register-sender instructions necessary to forward this call
towards its destination.
The data processor writes the sending requirements into the
register-sender core memory fields. These include the following
information and instructions for this example: (a) early outpulsing
of all digits received, (EOP field is set), (b) when seven digits
are received, dialing is finished (TL field is set equal to 7), (c)
close terminating loop in the register junctor, and (d) working
with the terminating marker.
The network switching instruction is sent to the terminating marker
via the communication register. The marker then makes various
tests, selects a selector outlet, and completes a path thereto.
When the marker recognizes that the path has been connected
properly, it clears from the matrix and sends a message to the data
processor indicating successful call completion, and the identity
of the trunk that was used.
The data processor will place this information in the call history
table and write into register-sender core memory that outpulsing
may proceed when start signals have been received. When the distant
office is prepared to receive digits, it will return an off-hook
signal of approximately 150 milliseconds which the outgoing trunk
converts to a ground on the S lead. This causes the stop dial (SD)
relay in the register junctor to operate. At the end of the
150-millisecond period, the SD relay restores and outpulsing
begins.
The register-sender will outpulse the digits accumulated at this
point (early outpulsing) and will outpulse each additional digit as
it is received from the customer (no digits are deleted or prefixed
in this example). When seven digits have been accumulated and sent,
the register-sender will signal the originating junctor to switch
through.
The register junctor will release itself from the call, releasing
the R matrix. The register-sender memory is cleared, and the call
history table in the data processor is reset. The calling party now
controls the outgoing trunk. When the called party served by the
connecting office answers, they may begin to converse. The calling
line is now connected to the connecting office via the line matrix,
originating junctor, selector matrix, and outgoing trunk.
When the calling party disconnects, the outgoing trunk releases the
selector matrix, releasing the originating junctor and line matrix.
Release of the line cut-off correed idles the customer's line for
future calls.
The outgoing trunk remains busy for a short time to insure release
of the connecting office. It then returns to idle.
Incoming Trunk-to-Local Line Call
For purposes of explanation, it is assumed that a call has been
placed by a customer served by a distant office, and the call is a
locally-terminating EAS call. The signaling mode is dial pulse, and
the trunk is arranged for loop seizure. It is further assumed that
the local office has one central office code with less than 10,000
directory numbers, and the ABC digits of the called number have
been absorbed by preceding equipment.
In this example, the local office arrangement includes both an
office section and an incoming selector section. The incoming trunk
is located on the incoming selector section. The call is
terminating via the office section.
When the incoming trunk is seized from the distant end, the
trunk-register matrix inlet lead is marked with resistance battery,
denoting a call-for-service request.
An idle originating marker is assigned to this call. A scan of the
inlet leads identifies the trunk calling for service. One register
junctor is selected.
The calling trunk number identity (TNI) and the selected B outlet
information are loaded into the marker communication register and
sent to the data processor. The data processor enters the
originating phase of the call processing function and executes a
core translation of the data frame information which indicated the
section, matrix, B unit, and B unit outlet selected. This
translation yields the register junctor identity, which specifies
the unique cell of storage in the core memories of both the
register-sender and the data processor. Once the register junctor
identity is known, the data frame is stored in the data processor's
call history table (addressed by register junctor number).
The data processor also writes into the specified register-sender
core memory location that the register should begin timing the
arrival of pulsing over the line from the network.
While sending the TNI and path data to the data processor, the
originating marker operates the path from the incoming trunk to the
register junctor.
The incoming trunk loop, assisted by marker circuitry, seizes the A
correed in the register junctor. Operation of the register
junctor's A correed indicates a completed line loop to the
register-sender common logic. Upon detection of the completed line
loop, a hold is set in the register junctor. The marker, observing
that the register junctor is busy and the network is holding,
disconnects from the matrix.
Following the register junctor translation, the data processor
performs a class-of-service translation as previously described for
a local-to-local call. In the case of the incoming trunk call, the
drum search is keyed on the trunk number identity (TNI). For a call
now being processed, the class-of-service translation will indicate
the mode of start signaling, mode of receiving, quantity and
numerical value of previously absorbed digits, digit pattern to be
expected, and the total number of digits to receive before
requesting a final translation. These instructions are written into
the register-sender core memory of the proper register junctor.
When the register-sender has accumulated a total of four digits, it
requests the data processor to perform a translation. The data
processor performs a memory core table look-up to determine
grouping digits (selector outlet arrays) of intermediate junctors
which connect the incoming selector and office sections. Note: An
intermediate junctor is an interface device used between
sections.
A check is made for an idle communication register and an idle
terminating marker in the incoming selector section. When they are
idle, the data processor writes into register-sender core memory
that the register is working with the terminating marker.
Operation proceeds as previously described for a local-to-local
call. The terminating marker, upon completing a path, returns a
data transmission to the data processor indicating successful
completion and the selected selector outlet of the incoming
selector section. Control of the path is left to the register
junctor.
The data processor performs a drum look-up to obtain the local
selector section inlet identity of the intermediate junctor. If not
previously performed, the data processor also performs a drum
look-up of the terminating list to determine class-of-service and
switching digits of the called line. To obtain the grouping digits
of terminating junctors in the called matrix, the data processor
executes a core table look-up. All the switching information is
sent to a terminating marker in the office section.
The terminating marker processes the call as a normal local
termination. The intermediate junctor appears as a register junctor
to the terminating marker. When hold is returned to the selector by
the terminating junctor, the intermediate junctor switches the
supervisory lead through and the register junctor controls the
entire path.
Switch-through of the incoming trunk is accomplished by the
register-sender in the manner described for local calls, via
originating junctors. When the called party answers, ground is
returned from the terminating junctor to the incoming trunk via the
S lead. The incoming trunk then returns answer supervision to the
distant office.
DUPLICATED SYSTEM
FIG. 2 is a simplified block diagram showing in broad scope how
subsystems are duplicated and how the system may be reconfigured.
Reconfiguration is the removal of a malfunctioning subsystem. When
a malfunction is detected and isolated the system must be
reconfigured in order to continue normal call processing. Any
single subsystem of a pair can be removed from call processing
without seriously degrading service. Both subsystems of a pair must
not be removed from call processing; since this would result in the
system being out of service. The system can continue call
processing with only one subsystem of each pair functioning.
Normally computer A and computer B operate in synchronism, and at
particular intervals during each clock cycle which is related to
the access of a word of memory, certain points of the systems are
compared and the comparison is monitored by the third party
circuit. The third party circuit contains logic enabling it to
control the reconfiguration of the system, and to perform functions
such as controlling one of the computers to analyze the other.
The register sender subsystems A and B in like manner are operated
in synchronism and certain points of the systems compared during
each cycle. Normally register sender A communicates with computer A
and register sender B communicates with computer B. One of the
computer-register sender combinations supplies output signals to
other subsystems of the system. The system may be reconfigured so
that either computer-register sender combination supplies the
output signals, or for example computer A may communicate with
register sender B to supply output signals or computer B may
likewise work with register sender A.
The two computer subsystems A and B as a pair may work with either
of the drum memory systems, or if one computer is out of service
the other computer may work with either drum memory system. The
computer and the drum memory system each access the main core
memory via the computer memory control.
The originating markers A and B are arranged to process calls
simultaneously, with the limitation that they cannot both be
working with the same network matrix. They have an interlock
arrangement such that any given call request will be serviced by
only one of the originating markers. The terminating markers A and
B are arranged so that only one may be serving calls at a time, but
they are used alternately. There is also an interlock arrangement
to prevent originating and terminating markers from accessing the
matrices simultaneously. The communication registers A and B are
arranged so that one of them is on line, for example, the
communication register A, while the other is on standby. For
example, when communication register A is on line communication
register B is in standby. Both computers work with the
communication register which is on line.
In like manner the input-output buffers A and B have one on line
while the other is in standby, and both computers work with the one
which is on line.
COMPUTER CENTRAL PROCESSOR
The common control apparatus of the switching system is shown in
FIG. 3 in a block diagram which shows the duplication of units, and
how they interface with the computer central processor CCP. The
computer central processor is duplicated comprising units CCP-A and
CCP-B. A computer third party CTP provides for maintenance and
control functions, including coupling of the processors to a
computer programming console PRC. The register-sender subsystem in
a maximum configuration comprises two duplicated register-sender
units, namely register-sender unit RS1A and its duplicate RS1-B,
and unit RS2A and its duplicate RS2B.
The apparatus in FIG. 3 other than the register-sender subsystems
and the console PRC comprise the data processor unit DPU.
Each of the computer central processors has its own core memory and
computer memory control, for example core memory CMM-A and memory
control CMC-A for the computer central processor CCP-A, and the
duplicate units CMM-B and CMC-B for processor CCP-B. There is also
a drum memory system with up to six units in the maximum
configuration. The computer memory control has eight ports for each
of the duplicate units. The computer memory control CMC-A uses
ports 1, 3 and 5 principally for access to the drum memory systems
1, 3 and 5 and may also use ports 2, 4 and 6 for access to the drum
memory systems 2, 4 and 6; while the memory control unit CMC-B uses
ports 2, 4 and 6 for principal access to the drum memory systems 2,
4 and 6 and may also use ports 1, 3 and 5 for access to the drum
memory system 1, 3 and 5. Each of the memory controls uses port 7
for access to its own computer central processor, and may use port
8 for access to the other processor. The memory control unit
controls the transfer of data between the main core memory CMM and
one of the ports for transfer to a drum memory or the central
processor.
The computer line processors provide for processing of interrupts
from other units in the data processing unit, the register-sender
subsystem, and the markers. This unit is duplicated with computer
line processor CLP-A coupled to the computer central processor
CCP-A and the computer line processor CLP-B coupled to the computer
central processor CCP-B, with interconnections between the two
computer line processors.
The computer channel multiplex unit CCX-A connected to the computer
central processor CCP-A, and unit CCX-B to unit CCP-B provides for
input-output functions with various device buffers and the
communication registers. The communication register comprising
duplicated units CCR-A and CCR-B provides for communication with
the markers as shown in FIG. 1. The channel device buffer CDB-A and
its duplicate CDB-B provides for input-output to a local
maintenance teletype-writer, a high speed paper tape punch, and a
data set for remote teletypewriters; while its duplicate CDB-B
provides for input-output to a local office administration
teletypewriter and a high speed paper tape reader. The ticketing
device buffer TDB-A and its duplicate TDB-B (not shown in FIG. 2)
provide for coupling to a magnetic tape unit and scanner. The
maintenance device buffer MDB-A and its duplicate MDB-B provide for
input-output from a pushbutton control panel and displays, power
monitors and alarms, and maintenance routine logic.
The registers shown in FIG. 3A are used primarily for arithmetic
operations and address modification.
The A register, the main arithmetic accumulator, is a 24-bit
register used in data transfer between the central processor and
the register-sender, and between the central processor and the
channel multiplexer via the data bus, as well as for all arithmetic
operations. The A register can be shifted both logically and
arithmetically.
The arithmetical operations are performed by the arithmetic logic
unit ALU in conjunction with the A, Q, S and Y registers.
The Q register is a 24-bit register used in conjunction with the A
register for shift and rotate operations. It is also used as an
auxiliary arithmetic register for multiply and divide operations.
It is used to hold the multiplier and the lower order bits of the
product in a multiply process. For division, it is used for the low
order bits of the divident. It accumulates the quotient and finally
holds the resultant remainder.
The S register is a 24-bit register used during arithmetic
operations and during address modification when placing a main
memory address on the address bus.
The Y register is a 24-bit register used during arithmetic and
logical operations. It is one of the inputs to the arithmetic logic
unit ALU. It cannot be accessed by the program.
The instruction register IR is a 24-bit register that receives all
instructions (coded information for the operation to be performed,
address field, and the method of addressing) from the main memory
via the computer memory control and the data bus.
The three index registers X1, X2 and X3 are 15-bit registers used
for address modification, and as a counter.
The page register PR is a 6-bit register used to specify bits 15
and 16 of the address bus. It operates in conjunction with the
program counter to address a location within a memory page. The
page register is made up of three sections: the "instruction field"
(bits .phi. and 1), the "branch field" (bits 2 and 3), and the
"data field" (bits 4 and 5).
The last program count register LPC is a 15-bit register used to
store return linkage to the running program during processing. It
is continually updated by the program counter.
The last page reference register LPR is a 4-bit reigster used as an
extension of the last program count register. It is continually
updated by the page register. The last page reference register is
made up of two sections: the "last instruction field" (bits .phi.
and 1), and the "last data field" (bits 2 and 3). The "last data
field" is loaded from the "data field" of the page register. The
"last instruction field" is loaded from the "instruction field" of
the page register.
The central processor includes a program counter and a shift
counter.
The program counter PC is a 15-bit binary counter used to
sequentially count the address of instructions. The program counter
holds the address within a page of the next instruction to be
retrieved from core memory. It is used with the page register to
locate this address. This counter is incremented (increased by one)
for each instruction to establish program sequence.
The shift counter SC is a 6-bit counter used to control the number
of shifts during shifting operations.
SYMBOLISM FOR GATES, BISTABLE DEVICES AND EQUATIONS
The common logic circuits of the system are generally implemented
with integrated circuits, mostly in the form of NAND gates,
although some other forms are also used. The showing of the logic
in the drawings is simplified by using gate symbols for AND and OR
functions, the AND function being indicated by a line across the
gate parallel to the input base line, and the OR function being
indicated by a diagonal line across the gate. Inversion is
indicated by a small circle on either an input or an output lead.
The gates are shown as having any number of inputs and outputs, but
in actual implementation these would be limited by loading
requirements well known in the art. Latches are indicated in the
drawing by square functional blocks with inputs designated S and R
for set and reset respectively; the circuits being in practice
implemented generally by two NAND gates with the output of each
connected to an input of the other, which makes the circuit a
bistable storage device. The block symbol for the latch implies
inverters at the inputs so that it is set and reset with signals at
the "one" level. The logic also uses bistable devices in the form
of JK flip-flops implemented with integrated circuits, indicated in
the drawings by rectangles having the J and K inputs indicated by a
small semicircle, a clock input indicated by C, and set and reset
inputs indicated by S and R. Not all of the inputs for these
devices are shown in the drawings. The J and K inputs are each
actually AND gates having three external inputs, but the unused
inputs which are actually terminated in some manner are not shown
on the drawings. The S and R inputs are effective at the zero
level, the J and K inputs at the one level, and the C input on a
trailing edge.
While some discrete transistor circuits are used for interfacing
with relay circuits, most of the electronic circuits of the system
of FIG. 2 are implemented with integrated circuits of the Sylvania
SUHL TTL high level logic family or equivalents. The NAND gates
used to implement AND and OR functions include types SG 43, SG 63,
SG 132, and SG 143. The AND-OR functions are also implemented with
chips having AND gates feeding a NOR gate such as types SG 53 and
SG 113. JK flip-flops may be type SF 53.
Boolean expressions are used to designate signal leads in the
drawings, and in equations and miscellaneous references in the
specification. In the expressions for basic Boolean elements,
capital letters, numbers, spaces and hyphens are used. The
expressions for elements may also include parentheses enclosing two
numbers separated by a hyphen, indicating the first and last of a
group of bit positions of gates enabled by a control signal. For
example the expression IR(.phi. - 5) - DSO is a single Boolean
element. In combinations of elements, the period (.) is used for
the AND function, the plus sign (+) for the OR function, and the
apostrophe (') for negation. In a string of elements separated by
periods and plus signs without parentheses or brackets, the AND
operations are performed first and then the OR functions; for
example A + B.C + D is the same as A + (B.C) + D. Parentheses and
brackets are used in the usual manner indicating operations in
inner parentheses are performed first, then those in outer
parentheses or brackets, etc. On the drawings the minus sign (-) at
the beginning of an expression indicates negation of the entire
expression following it, and not merely the first element if there
is more than one. The period may be omitted before or after
parentheses which implies the AND function; but it cannot otherwise
be omitted between elements, since a space can occur within an
element.
In the equations, storage devices are indicated by using separate
equations for the various inputs. For simple NAND gate type latches
the set and reset inputs are indicated by (S) and (R). For JK
flip-flops the inputs are indicated by (J), (K), (C), (S)' and
(R)'. The apostrophe for the set and reset inputs indicates that
the zero level is effective, namely the negation of the expression
after the equal sign (=). The trailing edge of the entire
expression is effective for the clock input. The combination of the
three leads for J and K inputs is indicated by a single
equation.
Throughout the description and drawings, it is implied that all
circuits and signals relate to unit A of duplicated units, unless
specifically indicated by a suffix -A or -1 for unit A, or a suffix
-B or -2 for unit B.
TIMING FOR THE COMPUTER CENTRAL PROCESSOR
The timing generator CPT is shown in part in FIG. 4. There are
additional control circuits not shown which will be described by
Boolean equations.
The timing generator is designed to provide the timing increments
upon which the instruction set of the central processor is
structured. The basic timing intervals are the cycle which is two
microseconds long, the level which is 500 nanoseconds long, and the
pulse which is 100 nanoseconds long.
The timing is dependent upon a source providing a constant train of
pulses at a 10 megahertz rate with a duty cycle of approximately 50
percent. This is provided by clock circuits which are a part of the
third party circuit CTP. There is provided a main clock having its
output train of pulses on lead MOA and a standby clock having its
output train of pulses on a lead SOA. The third party circuit
includes logic for monitoring the outputs of the clocks and
insuring that one and only one of them is supplying output at all
times. The two output leads are connected to the timing generators
of both of the duplicate computer central processors CCP-A and
CCP-B. FIG. 4 is the timing generator CPT of the processor CCP-A.
Logic represented by exclusive OR gate 411 gates the train of
pulses from whichever of the leads MOA or SOA they are occurring
and supplies them to other logic circuits of the timing generator
as the basic clock control.
The timing generator includes three main storage devices that are
continually pulsed by the clock train from gate 411. These storage
devices are required to permit an orderly shutdown of the timing
generator, as well as an orderly processing during operation of the
timing generator. These storage devices comprise JK flip-flops
START CLK, CLK and SYNC. The clock inputs C of all three are
connected to the output of gate 411. The two outputs of flip-flop
START CLK feed respectively into the J and K inputs of flip-flop
CLK. The purpose of flip-flop CLK is to prime flip-flop SYNC, to
prime the basic timing pulse TCP and to prime the data bus and
address bus of the computer central processor. The function of the
flip-flop SYNC is to act as a primer for the basic timing pulse
TCP, and as such is controlled by feedback from the main memory
system by the register-sender memory system.
The basic timing pulses on lead TCP are normally supplied from one
of the AND gates 413 or 414, but may also be supplied via the lead
PULSE from the third party circuit. These three sources are gated
via OR gate 415 to the lead TCP. The train of clock pulses from
gate 411 is supplied as an input to both gates 413 and 414 as well
as the three flip-flops previously mentioned. If the two processors
are operating in a synchronization a signal on lead CYSYNC enables
gate 414, whereas if the processors are not operating in
synchronization the zero level signal on this lead via inverter 412
enables gate 413. If the processors are not in synchronization the
coincidence of signals from flip-flops CLK and SYNC along with the
signal from gate 412 enables gate 413 to gate the clock pulses via
gate 415 to lead TCP; whereas if the processors are operating in
synchronization it is required in addition that the duplicated
processor have its synchronization flip-flop set to supply a signal
on lead SYNC B, enabling gate 414 to supply the pulses via gate 415
to lead TCP.
The pulse counter shown as a single block 416 comprises five JK
flip-flops, not shown, whose outputs are respectively P1 through
P5. These five flip-flops are connected as a ring counter with the
one and zero outputs of each connected respectively to the J and K
inputs of the following flip-flop, the P5 outputs being connected
to the P1 inputs; and the clock inputs are supplied from lead TCP
for all five flip-flops. The counter is advanced on the trailing
edge of each clock pulse, thus the outputs appear for 100
nanoseconds on each of the output leads in turn.
The level counter comprises four JK flip-flops L1 through L4. The
clock inputs of these four flip-flops are supplied from lead P5, so
that the level counter may advance once each 500 nanoseconds on the
trailing edge of pulse P5. The output of a gate 450 is connected to
the J and K inputs of flip-flops L1 and L2, while the output of a
gate 460 is connected to the J and K inputs of flip-flops L3 and
L4. In addition flip-flop L1 has another J input from L4, and the
flip-flops L2, L3 and L4 have J inputs from leads SET L2, SET L3
and SET L4 respectively.
The cycle counter comprises JK flip-flops C1, C2 and C3. The lead
L4 is connected to the clock as well as the J and K inputs of all
three of these flip-flops so that the cycle counter may be advanced
once each two microseconds on the trailing edge of the pulse on
lead L4. In addition the flip-flops have J inputs connected
respectively to leads GOC1, GOC2 and GOC3, and a K input of
flip-flop C1 is connected to lead GOC2, a K input of flip-flop C2
is connected to an OR gate having inputs from leads GOC1 and GOC3,
and a K input of flip-flop C3 is connected to lead GOC1. The signal
on lead -CLR is used to set flip-flops P5, L4 and C3 and to reset
the other flip-flops.
There are a number of JK flip-flops not shown which are a part of
the timing generator, that are combinations of cycles, levels and
pulses. It is necessary to supply these signals from storage
devices, because if they were implemented with AND gates providing
AND and OR functions their outputs would not be stable during the
intended interval. Unless otherwise stated the clock inputs for
these flip-flops are from lead TCP. The first has J inputs from
leads L1, P2, and a lead -C2(MUL + DIV); and K inputs from leads L2
and P5; and provides an output L1(P3 + P4 + P5) + L2. The next
flip-flop has J inputs from leads -C2(MUL + DIV), P4 and L2, and K
inputs from leads P5 and the output of a gate providing the
function (L3 + L4); and has an output providing the function (L2.P5
+ L3). The next flip-flop has J inputs from leads L1, P4 and the
lead -C2(MUL + DIV), and K inputs from leads (L3 + L4) and P1; and
provides the output function (L1.P5 + L2 + L3.L1). The next
flip-flop has J inputs from leads (L3 + L4, P3) and -C2(MUL + DIV),
and J inputs from leads L4 and P5; providing an output L3(P4 + P5)
the next flip-flop has a clock input from lead P4 so that it
changes state on the trailing edge of pulse interval P4, a J input
from lead L1, and a K input from lead L4; providing the output
function (L2 + L3). The next flip-flop has a clock input from lead
P5, a J input from lead L2, providing the output function (L1 +
L2). The last flip-flop has a J input from lead P2 and a K input
from lead P5; providing the output function (P3 + P4 + P5).
The length of instructions for the time required to process an
instruction can vary with the type of instructions. Some
instructions require only one cycle to process while others require
two cycles. One instruction and traps require three cycles. Certain
instructions although only two cycles circulate within a cycle as
in shift instructions. Because of these differences controls are
provided that allow the timing generator to go from cycle 1 to
cycle 2 to cycle 3; or to set level 2, or to set level 3 or set
level 4. Since some instructions require the contents of memory and
cannot continue processing until the memory has retrieved the
contents, or some instructions write into memory, and cannot
continue until the write function is complete, a wait control is
implemented to reset the flip-flop SYNC which in turn suspends the
timing generator from proceeding until a feedback is received from
memory. The feedback signals from the main memory via memory
control include DAP7 and DLP7 designating respectively data
available and data loaded at port 7; while the feedback signals
from the register-sender subsystem are RSDAL and RSDLL for data
available and data loaded respectively. The timing generator
control logic is given by the following equations.
______________________________________ GOC1
=DAP7[IR23+PC-ASO(C2'+ZELO1')+XEC] +PREGOC1 GOC2
=C24INST.C1.L4.DAP7 +C1.L4.DAP7.C23INST.CCA'.SMP'.BSP'.
(PRA+CPD.TSTCPD)' +(BSP+STC).MMDLL +C1.(CCA+SMP) +C1.(DIV+TRAP)
+RSDAL.(PRA+CPD.TSTCPD) GOC3 =(DIV+ZELO1).C2.L4 RS DLL
=RSSEL'.CRS1.RS1DLL +RSSEL.CRS2.RS2DLL +RSSEL'.CRS1'.RS1DLL
+RSSEL.CRS2'.RS2DLL RS DAL =RSSEL'.CRS1.RS1DAL +RSSEL'.CRS1'.RS1DAL
+RSSEL.CRS2.RS2DAL +RSSEL.CRS2'.RS2DAL SET L2
=C2.L3.MUL.SC3.phi.'(MODE.Q.phi.'+MODE'.Q.phi.)+
C2.L3.DIV.SC31'+L1(C2'+Q.phi.+MUL') SET L3
=C1.L1.MUL.Q.phi.'+L2(C1'+(SMP'+A23')(ENDCT'+ (CCA+SFTA+SFTL)') SET
L4 =L3(C2'+SC3.phi.)(C2'+DIV1+SC31)+C1.L2
(SMP.A23+ENDCNT(CCA+SFTA+SFTL) START =TP POWER ON(RUN+INC+STEP+EXP
B)+TP INC+ TP STEP+TP RUN STP CLK =P3(INC+TP INC)+P3.PC-ASO.L4.((TP
POWER ON) (STEP+ADDRESS MATCH+EXPB)+HLT+TP STEP) WAIT STATE
=C1.(STX+STA+STQ).MMDLL' +L3' +C1.PAR.RSDLL'
+C2.MMDLL'(ADM+AOM+XAM+RPA+SOM)
______________________________________
BUS SOURCES
The data bus sources for the bit in position .phi. is shown in FIG.
5, while the sources for all bit positions are shown in FIG. 6. For
each bit position of each source there is a two input AND gate with
one input being the signal source for that bit position and the
other input being an enabling control signal. For example AND gate
501 has a signal source lead DB.phi. and an enabling control signal
lead LATCH DB. In each bit position the outputs of all these AND
gates are combined through OR gate circuitry to the single bit
position lead for the bus. FIG. 5 shows some of the sources
combined by OR gate 530 to lead DBA.phi. and other sources combined
through OR gate 531 to lead DBB.phi.. The outputs of these two OR
gates and the other AND gates are combined by circuits represented
by the symbol 540 to lead DB.phi.. Symbol 540 in actual practice of
course comprises a plurality of gates combined to provide the OR
function. To show signal sources received from other subsystems on
different frames via cables, cable receivers such as 521 are shown
in FIG. 5, with the subsystem designated by a mnemonic preceding a
bracket. For example the signal on lead DRP7-0 is received from the
computer memory control unit CMC. Signals received from the B units
of the two register sender subsystems are received via cable
receivers of unit CCP-B and supplied to both units CCP-A and CCP-B.
Similarly the signals received from the A units of the register
sender subsystems following the cable receivers of unit CCP-A are
supplied to both the A and B units of the computer central
processor CCP.
In FIG. 6 and in several of the other figures, rectangular blocks
designated AND are used to represent a set of AND gates having
signal sources from the respective bit positions and a common
enabling signal; and blocks designated OR are used to represent the
set of OR logic for the several bit positions combining signals
from the AND blocks. The arrangement of the gates within these
blocks is shown at the bottom of FIG. 11 with block 1150
representing an AND block and 1170 representing an OR block. In
some cases the bit positions are subdivided into groups with
different enabling signals; for example in the block 604 the
control signal A(.phi. - 5) - DSO enables bit positions .phi. - 5,
the control signal A(6 - 7) - DSO enables the gates for bit
positions 6 and 7, etc. The signal source leads for block 604 are
all from the A register; but in some cases the signal sources for
different bit positions will be from different registers or other
sources. For example in block 607 the control lead SC-DSO enables
bit positions .phi.-13 to gate the signals from bit position
.phi.-5 from the shift counter SC with ones into bit positions
6-13, while the signal on lead PC-DSO enables bit positions 12-21
to gate a 0 into bit position 14, the signals from the page
register PR in the bit positions 15-20, and a 0 into bit position
21. In bit positions 22 and 23 both the enable signal and the
source leads are 0's so that the output from these positions is
always 0. The signal ONES is derived from an electronic ground via
an inverter. For 0's electronic ground is used directly. The OR
gating corresponding to block 540 in FIG. 5 is represented in FIG.
6 by OR blocks 637, 638 and 639 feeding OR block 640 for
convenience. The OR function gating corresponding to gates 530 and
531 is shown in FIG. 7 by blocks 730 and 731 respectively. The
block 730 has only 15 bit positions for sources from the index
registers and program counter which likewise have only 15 bit
positions. The other signals for leads DBA15-DBA23 are derived from
OR gates having four inputs each from control pulse directive CPD
sources except that the last input of the gate for bit position
DBA23 is the signal C STROBE.
As shown by AND gate 501 which is a part of the AND logic 601, the
Data Bus leads DB-.phi. to DB-23 are connected back as input data
sources. These AND gates are enabled by the signal LATCH DB, so
that any ones appearing on the data bus are latched as long as the
signal LATCH DB is true. However, it is possible to enable another
source to gate additional 1's onto the data bus.
The sources for the address bus AB are shown in FIG. 8 with the
actual logic for bit .phi., and in FIG. 9 for fifteen bit positions
via the OR logic 940 plus two additional bit positions from the
page register. Latching of the address bus is provided via AND
logic 901 with bits AB.phi. to AB14 as sources enabled by the
signal LATCH AB. This latter signal is provided by a latch which is
shown along with its setting and resetting logic.
The program counter is used as a source when the enabling signal
GPC-ASO is true, and the S register is used as a source when the
enabling signal S-ASO is true.
For interrupts the AND logic 904 is enabled by signal IA-ASO. Four
of the five octal digits for the address source are provided by
hardwired inputs so that the address is 7371X, where the value of X
is determined by the three inputs 1A0, 1A1 and 1A2 which are
received from the computer line processor CLP. For traps the
address is provided by AND logic 905 enabled by a signal TA-ASO to
provide a wired address 737.phi.X, where the value of X depends on
signals TA0 and TA1 derived from the computer third party CPT.
The paging bits of the address are supplied via OR gates 906 and
907 for bit positions AB15 and AB16 respectively, with the logic
providing inputs from the page register as shown.
REGISTERS OF THE COMPUTER CENTRAL PROCESSOR
The registers shown in the block diagram of FIG. 1 are shown in
more detail in FIGS. 10-15.
The instruction register IR comprises 24 storage devices in the
form of latches. Each of the latches comprises an integrated
circuit chip comprising two four-input AND gates such as 1011 and
1012 feeding a NOR gate such as 1013. The output from gate 1013 via
an inverter 1014 supplies the output signal IR.phi., while the
output from gate 1013 is the negative signal -IR.phi.. Both the
true and inverted signals may be taken from each of the latches.
The instruction register is loaded from the data bus bits
DB.phi.-DB23. The load signal to the latches is supplied in
inverted form shown as an input to the latches for positions
IR.phi.-IR11 as -LOAD. The loading of these latches depends on a
time delay achieved in the inverters such as 1010. For example when
the signal LOAD becomes true (-LOAD false) then via inverter 1010
the upper input of AND gate 1012 is enabled and if the source
signal DB.phi. is also true then the output of the latch becomes
true. This output is fed back to the upper input of AND gate 1011.
When LOAD goes false (-LOAD true) then gate 1011 is enabled to
maintain the latch
TABLE A
__________________________________________________________________________
OP00 -- OP20 ADX OP40 ADD OP60 PRA 01 ADI 21 SBX 41 SUB 61 PAR 02
SBI 22 CAX 42 MUL 62 BSP 03 HWL 23 CSX 43 DIV 63 -- 04 HWS 24 IBP
44 AOM 64 LDQ 05 SEL 25 IBN 45 SOM 65 STQ 06 LSGA 26 STX 46 ADM 66
LPR 07 SSNT 27 -- 47 XEC 67 HLT 10 RTN 30 BPX 50 ANA 70 SMNT 11 BUN
31 BNX 51 ORA 71 SMNZ 12 SFTL 32 BZX 52 ERA 72 SANE 13 BZA 33 CCA
53 XAM 73 SANG 14 BNA 34 SFTA 54 LDA 74 LDC 15 BPA 35 BAO 55 STA 75
STC 16 BRR 36 RTR 56 CSA 76 SAMQ 17 CPD 37 MIS 57 RPA 77 SMNN
__________________________________________________________________________
set before the upper input of gate 1012 becomes false. The signal
on lead -CLR is normally true, and when it goes false it clears all
of the latches to zero. The LOAD IR logic is shown in simplified
form within block 1000. During normal operation the AND gate 1001
is enabled in response to the condition C1.L1.P3, which normally is
the necessary condition for loading all bit positions. The loading
of bit positions IR12, IR13 and IR14 may be inhibited at gate 1002
by the signal EXT OP PROTECT, the loading of bit positions
IR15-IR2.phi. may be inhibited at gate 1003 by the signal INOP, and
the loading of bit positions IR21 and IR22 may be inhibited at gate
1004 by the signal INX. All bit positions may alternatively be
loaded by the third party signal TP LOAD IR. FIG. 10 also shows the
OP code decoder 1020 for the instruction set, and a control pulse
directive decoder 1030. The control pulse directive decoder 1030 is
enabled by the signal on lead C STROBE which is true in response to
the condition CPD.L3. It decodes the value of the control pulse
directive from the six bit positions IR9-IR14 which provide the
output octal codes .phi..phi. to 77. These outputs are supplied to
the data bus as shown in FIG. 7, and also to the various subsystems
to which they apply.
The outputs of the OP Code decoder 1020 represent the decoding of
the six instruction register bits IR2.phi.-IR15 along with the
signal INHIBIT'. The six IR bits are expressed as two octal digits.
For example ADM = OP46 = IR20.IR19'.IR18'. IR17.IR16.IR15'.INHIBIT.
The full decoding is shown in Table A. Note that codes
OP.phi..phi., OP27 and OP63 are invalid codes which via an OR
function gating provide the signal IOP.
The Y register shown at the top of FIG. 11 comprises 24 latches
similar to those used in the instruction output from all of the odd
positions is in true form while that from even positions is an
inverted form. With this arrangement the carry is propogated
through all of the bit positions via only the single integrated
circuit chip for each position, thus minimizing the propogation
time.
When the signal ARITH is true the output is the sum of the contents
of the Y register and data bus. When the signal EXO is true the
output is the exclusive OR function of the Y register and data bus.
When the signal on lead AND is true the output is the AND function
of the Y register and data bus. To provide the OR function the
signals on leads AND and EXO are supplied simultaneously. To
provide the subtract function with 2's complement arithmetic the
signals on lead INVERT and the carry input on lead C.phi. are
provided. To simply invert a number in 2's complement form it is
supplied into the Y register, with the data bus all zeros, and the
signals INVERT and C.phi. are provided.
The A register and Q register are shown in FIG. 13. These registers
each comprise twenty-four JK flip-flops. These registers are loaded
by supplying a load signal to the clock inputs and supplying the
data to be loaded to the J inputs and inverted to the K inputs. The
clock input for the Q register is LOAD Q, while for the A register
the flip-flops are divided into four groups with separate load
signals to the clock inputs as shown. Both registers may be set to
all zeros by a signal on lead -CLR at zero level. Register A may be
loaded from the arithmetic logic unit bits AD.phi.-AD23 with an
enabling signal ADA, may be the sink for the data bus bits DB0-DB23
with the enabling signal A-DSK, may be loaded from its own output
shifted one bit position to the right and register. This register
is also loaded from the data bus bit positions DB.phi.-DB23 in
response to an LOAD Y signal. The S register shown at the bottom of
FIG. 11 also comprises twenty-four latches similar to those of the
IR register, except that the AND gates have only two inputs. This
register may be loaded from either the data bus or the arithmetic
logic unit in response to a signal LOAD S. It is loaded from the
data bus via AND logic 1150 when the signal on lead S-DSK is true
indicating that the S register is the data sink. It is loaded from
the arithmetic logic unit bits AD.phi.-AD23 via AND logic 1160 in
response to an enabling signal on lead ADS, which is true whenever
the signal on lead S-DSK is false. The bit positions 15-23 are
inhibited when the signal on lead XH is true to prevent loading
from bits AD15-AD23. The outputs from the AND logic 1150 and 1160
are passed through OR logic 1170 to the data inputs of the S
register. The arrangement of the gates within the blocks 1150, 1160
and 1170 is shown here, whereas in other figures only the blocks
are shown to represent the same form of logic.
The arithmetic logic unit ALU is shown in FIG. 12. This is a 24 bit
parallel adder. The circuit for bit positions AD1 and AD2 is shown
in detail. The data inputs to the register are from the Y register
and the data bus, and the output on leads AD.phi.-AD23 is the
result of the arithmetic operation. A feature of the adder is that
the carry output from each bit position is from an integrated
circuit chip which as shown for bit position AD1 comprises a
two-input AND gates 1201, 1202 and 1203 feeding an NOR gate 1204.
The chip actually contains four AND gates but one of them has its
inputs connected to ground. The arrangement is such that the carry
supplying the signal A23IN for the twenty-third bit with an
enabling signal STR, and may be loaded from itself shifted one bit
to the left and supplying the signal A.phi.IN for bit position zero
with an enabling signal STL. Similarly the Q register may act as a
data sink for the data bus with an enabling signal Q-DSK, may be
loaded from itself shifted one bit position right and a signal
Q23IN in the twenty-third bit position with an enabling signal STR,
and may be loaded from itself shifted one bit position left with a
signal Q.phi.IN in bit position zero with an enabling signal STL.
The flip-flop Q.phi. may also be set by a zero level signal on lead
-Q.phi.(S).
The program counter PC and last program count register LPC are
shown in FIG. 14. The program counter PC comprises fifteen JK
flip-flops connected as a binary counter, advancing one count each
time a trailing edge of a pulse appears on lead COUNT PC connected
to the clock inputs. The counter may also be loaded from the data
bus in response to a signal on lead LOAD PC, the loading being
effective via the asynchronous inputs S and R. The counter may also
be cleared by a zero level signal on lead -CLR to the second reset
input of each flip-flop. The first seven flip-flops and the last
one have been shown in order to illustrate the binary counting
logic at the J and K inputs. The logic is arranged in groups of
three flip-flops which with each having an AND gate supplying J and
K inputs of all three, for example gate 1423 supplies J and K
inputs of flip-flops PC3, PC4 and PC5 with the inputs of gate 1423
being from the preceding three flip-flops PC/, PC1 and PC2, and one
input from the AND gate of the preceding three flip-flops. The
second flip-flop of each group, for example flip-flop PC4 also has
J and K inputs from the preceding flip-flop, namely, PC3, while the
third flip-flop of each group such as PC5 has J and K inputs from
both of the other flip-flops, namely PC3 and PC4. The output of
gate 1423 is then supplied as an input to gate 1426 for the next
group of three, etc. For the first group of three instead of an AND
gate an inverter 1420 with input from ground is substituted.
The last program count register comprises fifteen latches of the
type each comprising two NAND gates. AND gates are provided to load
the output of the program counter PC into the last program count
register LPC in response to a signal on lead LOAD LPC.
The three index registers X1, X2 and X3 shown in FIG. 15 each
comprise fifteen latches similar to those used in the instruction
register and Y register. Each of these registers may be loaded in
response to each individual load command from the fifteen low order
bits of the data bus.
The shift counter SC shown at the bottom of FIG. 15 is a six-bit
counter with JK flip-flops generally similar to the program counter
PC. The count is advanced once upon each occurrence of a trailing
edge on lead COUNT SC. The counter may be loaded via AND logic from
the inverted six low order bits of the data bus in response to the
command LOAD SC. The output of the counter is decoded for certain
values as shown, SC = 0 for the state in which all the flip-flops
are set to zero, SC27, SC30 and SC31 for corresponding octal
values, and ENDCT for the octal value 77.
CONTROL LOGIC FOR THE COMPUTER CENTRAL PROCESSOR
The control unit logic block CPC in FIG. 1 represents the logic for
supplying the control signals for transferring data and address
information among the registers and buses. The definitions of the
various signals, and the Boolean equations follow.
__________________________________________________________________________
Definitions ACKN ACKNOWLEDGED RECEIPT OF DATA FROM I/O ADA = OUTPUT
OF ADDER TO RA ADD1 INDICATION THAT A CORRECTIVE ADDITION OF ONE
MUST TACKED ON TO THE QUOTIENT ADZ = OUTPUT OF ADDER EQUALS ALL
ZEROS. AND = LOGICAL AND A-DSO = REGISTER "A" AS A DATA SOURCE
A23IN = DATA INTO BIT 23 OF REG.A BCHI = A STORED BRANCH INDICATOR
BDIS PRCF BUTTON DISPLAY ENABLE C STROBE SIGNAL USED TO STROBE DATA
BUS DURING CPD CAR (S) = CARRY,OUT OF BIT 23 OF ADDER,STORED
CCX-DSO = CHANNEL MULTIPLEX AS A DATA SOURCE CLR = CLEARS TO AN
INITIAL STATE THE FOLLOWING: RA,RO,Y,IR,X1,X2,X3,PC.SC,TP TRAP,
START CLK,CLK,SYNC,MMREAD,MMWRITE LOCKOUT, CARRY,OVF,EVEN PARITY
TEST STORAGE,LATCH AB, TST CPD,WMPB,PCINH,RSSEL,TRAP DISABLE,
XH,LOAD LPC INHIBIT,BRH,INST,SW TO STDBY RT
CLK,QZ,MADD,ADDI,INX,INTIN,INOP,SREJECT, 6 C.phi. = CARRY INTO BIT
0 OF ADDER COUNT SC COUNT SHIFT COUNTER CRS1 SELECT REGISTER SENDER
1 UNIT A WHEN SET, AND RS 1 UNIT 1B WHEN RESET C13 INST = INDICATES
AN INSTRUCTION THAT ACCESS MEMORY DURING CYCLE 1 LEVEL 3 C23 INST =
INDICATES AN INSTRUCTION THAT ACCESS MEMORY DURING CYCLE 2 LEVEL 3
DEPE = DATA EVEN PARITY ERROR DIVZ INDICATES A DIVISION BY ZERO
DSTROBE DATA STOBE TO CCX DS-DSO = PRCF DATA SWITCH REGISTER AS A
DATA SOURCE ENWD = ENABLE WATCHDOG TIMER EXO = EXCLUSIVE"OR" IEPE =
INSTRUCTION EVEN PARITY ERROR INHIBIT = INHIBIT OF OP CODE INVERT =
INVERTS THE OUTPUT OF Y REG. 1'S COMPL. INOP INHIBITS LOADING OF
OPERATION FIELD IN IR INVOP ERROR INDICATING AN INVALID OP CODE INX
INDICATION OF A NON INDEXABLE INSTRUCTION IRL-DSO = INSTRUCTION REG
BITS(12-23) AS A DATA SOURCE IS SYNC SYNC PULSE SENT TO THE CLP
LATCH AB = LATCH ADDRESS BUS LBF LOAD BRANCH FIELD OF PAGE REGISTER
LDF LOAD DATA FIELD OF PAGE REGISTER LOAD AL LOAD RA BITS 12-23
LOAD AR LOAD RA BITS 0-11 LOAD LPC LOAD LAST PROGRAM COUNT REGISTER
LOAD SC = LOAD SHIFT COUNTER LPC-DSO = LAST PROGRAM COUNT AS DATA
SOURCE MADD INDICATES THAT AN ADDITION PROCESS DURING
MULTIPLICATION MODE INDICATES SUCCESSIONS OF '1'S"OR"0"S"IN MUL OFV
= OVERFLOW PBRM PROTECT BIT OF REFERENCED MEMORY PCINH INHIBITS
COUNTING OF PROGRAM COUNTER PC = PROGRAM COUNTER PC-DSO = PROGRAM
COUNTER AS A DATA SOURCE PEP7 = PORT 7 ERROR THAT INDICATES AN
ERROR HAS OCCURRED IN THE COMPUTER MEMORY CONTROL CIRCUIT RELATIVE
TO PORT 7 WHICH IS ASSIGNED TO THE CENTRAL PROCESSOR. THE ERROR IS
CAUSED WHEN THE CCP ADDRESSES A LOCATION OUTSIDE THE RANGE OF
MEMORY, OR WHEN THE CCP ATTEMPS TO WRITE INTO READ ONLY MEMORY QOIN
= DATA INTO BIT O OF RQ Q23IN = DATA INPUT TO REG.Q BIT 23 DURING A
SHIFT REI = RESET ERROR INDICATORS RS1B-DSO = REGISTER SENDER 1
UNIT B AS DATA SOURCE RS1A-DSO = REGISTER SENDER 1 UNIT A AS DATA
SOURCE RS2A-DSO = REGISTER SENDER 2 UNIT A AS DATA SOURCE RSSEL
SELECTS REGISTER SENDER 2 WHEN SET AND REGISTER SENDER 1 WHEN RESET
AS A SINK RST MEM REQ RESETS A MEMORY REQUEST FROM THIRD PARTY RWD
= RESET WATCHDOG TIMER SC(R) = RESET SHIFT COUNTER SC-DSO = SHIFT
COUNTER AS A DATA SOURCE SET L2 SET LEVEL 2 SG-DSO = SENSE GROUP AS
A DATA SOURCE SKIP ON SANG = A LESS THAN OR EQUAL TO EA. SANG SMP =
SHIFT AND MARK POSITION INSTRUCTION SREJECT = STORED REJECT
INDICATING A REJECTION OF AN ARITHMETIC PROCESS DURING DIV. START
START THE TIMING GENERATOR STP CLK STOP THE TIMING GENERATOR STR =
SHIFT RIGHT GATING SW TO STDBY RT = SWITCH TO STANDBY REAL TIME
CLOCK S(0-14)-DSO = REGISTER S BITS 0 THRU 14 AS A DATA SOURCE TID
TRANSFER INSTRUCTION FIELD TO DATA FIELD TOVF = TEMPORARY OVERFLOW
OF PARTIAL PRODUCTS DURING MULTIPLICATION. TP DSTROBE DATA STROBE
TO THIRD PARTY TST CPD A MAINTENANCE SIGNAL THAT ALLOWS A CHECK FOR
A LATENT FAULT ON THE INPUT TO THE CPD DECODE CIRCUIT WMPB STORED
SIGNAL TO WRITE MEMORY PROTECT BIT XHQ INDICATION THAT AN INDEX IS
BEING PROCESSED ZELO1 = TP TRAP + ERR TRAP
__________________________________________________________________________
##SPC1## ##SPC2## ##SPC3## ##SPC4## ##SPC5## ##SPC6## ##SPC7##
##SPC8## ##SPC9## ##SPC10## ##SPC11## ##SPC12##
ADM (ADD TO MEMORY) OPERATION
To illustrate latching of the buses, the operation for an ADM
instruction will be described. The timing chart is FIG. 16. An
octal representation is used in the following description for all
data and addresses in the registers and on the buses.
Assume initially that toward the end of the preceding instruction
PC-ASO and therefore GPC-ASO become true along with MM read. The
program counter PC (FIG. 14) contains some address, for example
(13257), which is gated onto the address bus AB (FIG. 9).
During the last cycle, which may be any one of C1, C2 or C3
depending on the instruction, the signal GO from gate 422 becomes
false. Therefore at P4, L4, input K of flip-flop SYNC becomes true.
The next clock pulse advances the pulse counter to P5 and also
resets SYNC. This blocks further pulses from lead TCP and thus
prevents the timing generator from advancing further.
In the meantime the memory control circuit causes the data word to
be read from the main memory and placed in a data register having
outputs on the cable leads DRP7-.phi. to 23. A signal DAP7 becomes
true indicating data available at port 7.
The signal GOC1 becomes true in response to the condition (DAP7.PC
- ASO.ZELO1'). The element ZELO1 relates to a trap condition and is
normally false. GOC1 via gate 422 along with CLK makes the J input
of SYNC true so that the next clock pulse sets it. When SYNC-B from
the duplicate processor is also true, gate 414 is enabled to supply
pulses to lead TCP. The next clock pulse then sets the timing to
C1.L1.P1. The signal PC-ASO becomes false as the timing is set to
L1.
To use the memory data register as a data source, the signal
MDR-DSO becomes true in response to the signal condition
[C1.L1.P5'(EXPB+XH)'CLK]. The data from leads DRP7-.phi. to 23 is
then gated onto the data bus (FIG. 6) during pulses P1-P4 of cycle
C1 level L1.
During the second pulse MM READ is reset in response to
DAP7.L1.P2.CLK.
During the third pulse the condition (C1.L1.P3) is used to LOAD IR,
LOAD Y and COUNT PC. In the equation for COUNT PC, EXPB and PCINH
will usually be false. (The signal PCINH may be true in certain
instances in which the program counter has already been advanced
with indirect addressing indexing, an interrupt or a trap and
should not be advanced again.)
The situation now is that the program counter has advanced to
(1326.phi.), and the contents of the word at address (13257) have
been placed via the data bus into registers IR and Y. Assume this
word to be (14621372). The (1) corresponding to bits 23, 22, 21
indicates indexing with register X1, the (46) is the OP code for
ADM and (21372) is the operand address.
INDEX is true in response to (IR21.IR19'). During the fifth pulse
MDR-DSO becomes false, and index register X1 becomes the data bus,
source by X1 - DSO = (X1.C1.L1.P5.INDEX), where X1 = (IR22'.IR21).
The signal ADS is normally true during cycle C1 unless RTR is
true.
As shown in FIG. 11, the input for register S is normally from the
adder of FIG. 12, via AND logic 1160 enabled by signal ADS which is
normally true except when S-DSK is true. The signal LOAD S is true
with (ADX IN1.C1.L2.P5) where ADX INI is true with INDEX true. LOAD
S causes register S to be loaded with the output of the adder,
which is the sum of the operand address instruction which has been
loaded into register Y and the contents of register X1 which
appears on the data bus. Assuming for example a value
(.phi..phi..phi.12) from the index register, the address in
register S is now (21404).
On the first pulse of the thid leve., MMREAD latch is set on
(C1.L3.MRI.PRA'); where MRI is true with bit IR20 true, this bit
being true for the ADM code OP46. The signal S-ASO is also true
with (CLK.MMDLL'.C1.L3.MRI). The main memory is now accessed via
memory control CMC to read the data from the word at address
(21404). In the meantime the processor continues other
operations.
During level L4 the signal A-DSO becomes true with C1.L4.ADM.
During pulse P3 the signal LOAD Y is true with (ADM.C1.L4.P3), and
LATCH AB is also set on the same condition. Therefore data from
register A via the data bus is placed in register Y, and the
address from register S is latched on the address bus. Assume data
from A into Y is (.phi..phi..phi..phi..phi.132).
It is now necessary to wait for the data to be available from the
main memory, indicated by the signal DAP7. ADM is a C24 instruction
so GOC2 becomes true on the condition C1.L4.C24INST.DAP7. This
initiates the cycle C2.
The signal MDR-DSO becomes true on C2.L1.P5'(C2,MDR-DSO
Inhibit)'CLK, which gates the data from the memory onto the data
bus. Assume data is (23512562).
The latch MMREAD is reset on (DAP7.L1.C2.CLK).
The signal LATCH DB becomes true on (ADM.C2[L1(P3 + P4 + P5) + L2])
so that the data from memory is latched on the data bus during the
last three pulses of level L1 and all of level L2.
During pulse P4 of level L2, LOAD S becomes true on ADM.C2.L2.P4.
therefore the sum from the adder is placed in register S. This sum
is (.phi..phi..phi..phi..phi.132) + (23512562) = (23512724).
During level L3 the signal S-DSO is true on (C2.L3.ADM); and
MMWRITE is true on (C2.L3.ADM.MMDLL'.LATCH AB). This signal along
with LATCH AB remains true during all of level L3. Therefore a
command is given to memory control to write the data from register
S at the address of the data word which is latched on the address
bus.
The timing stops at C2.L3.P5 while awaiting a signal from the
memory control that the data is loaded in memory. This is
accomplished by the signal WAIT STATE on the condition
(C2.MMDLL'.ADM).
The latch MMDLL is set in response to the signal DLP7 from memory
control indicating data loaded at port 7. LATCH AB is reset in
response to MMDLL. With MMDLL true, WAIT STATE becomes false and
makes GO from gate 422 true. Flip-flop SYNC sets on the next clock
pulse, and along with SYNC-B enables gate 414 to provide clock
pulses on lead TCP and advance the timing to level L4. MMWRITE
becomes false and the latch MMDLL is reset (DLP7 becomes false to
remove the set signal). The signal S-DSO becomes false when the
level goes to L4.
The last level of the cycle is used to initiate reading the next
instruction, whose address is in the program counter, now at 13260.
MMREAD sets and PC-ASO becomes true on (C2.L4.C24INST), and GPC-ASO
then becomes true. The timing stops at C2.L4.P5 while waiting for
the data available signal DAP7.
OTHER INSTRUCTIONS WITH BUS LATCHING
As seen in the equations for LATCH AB(S) and LATCH DB, the
instructions AOM for add one to memory and SOM for subtract one
from memory, use latching of both the address bus and the data bus;
the instructions XAM for exchange contents of register A and
memory, and RPA for replace address, use address bus latching; and
the instructions SANG for skip an instruction if contents of
register A is not greater than memory contents at the effective
address, SANE for skip if contents of register A not equal to
memory contents, and PRA for place contents of register-sender
memory into register A, use data bus latching.
The operation for instructions AOM and SOM is very similar to ADM.
Both omit A-DSO during C1.L4 so that the data bus has all zeros
when register Y is loaded during C1.L4.P3. For AOM the carry into
bit .phi. signal C.phi. is true on (C2.AOM), while for SOM a
negative one is effectively added by INVERT = C2.SOM.
The instructions XAM and RPA use latching of the address bus to
keep the address available while using the S register for other
purposes.
The instructions SANG and SANE use latching of the data bus to
retain information read from memory to do arithmetic operations
(subtract contents of register A from the data read from memory)
during cycle C2, levels L1 and L2.
COMPUTER USER MANUAL
SECTION 1.0 Computer Central Processor
1.1 Introduction to Computer Organization
An understanding of the Computer Central Processor will aid the
user to manipulate, maintain and to analyze the system.
1.1.1 Word Formats
The memory data word is represented in octal format as follows:
##SPC13##
e.g., a number represented as octal 24176653 has a corresponding
binary representation of:
010100001111110110101011
The instruction word format for the central processor is:
##SPC14##
Bits .phi. - 14 contain the address for memory reference
instruction or micro-instructions for non-memory reference
operations.
Bits 15 - 20 contain the code representing the operation to be
performed.
Bits 21 & 22 are coded to represent any of three index
registers to be used in address modification.
______________________________________ Bits Specify
______________________________________ 22 21 0 0 No Index 0 1 Index
1 1 0 Index 2 1 1 Index 3
______________________________________
Bit 23 is the indirect address bit.
(Bits 15 - 23 are referred to as the instruction field.)
The single precixion fixed point data word format (24 bits) is
represented as an 8 octal digit number with the highest order bit
denoting a positive or negative quantity: ##SPC15##
The word format for a double precision data word (48 bits) is
represented by two separate single precision words with the highest
order bit in the word of most significance denoting a positive or
negative quantity. ##SPC16##
Fixed point numbers are stored in memory in two's (radix)
complement form. Thus, magnitudes of negative numbers are not
directly available but must be recomplemented. The Clear A and
Subtract instruction has been provided to facilitate this
operation.
1.1.2 Main Memory (CMM)
The Main memory is a high speed random access store capable of a
complete read or write cycle time 1 microsecond and a
read-modify-write cycle time of 1.6 microseconds. (Slower memories
may be substituted with the only penalty being a derating in
processing speeds and Drum Transfer rates). Main Memory is
expandable in 4096, 8192, 16384 or 32768 word modules to a maximum
of 131,072 words or four modules, whichever occurs first.
Each memory module contains its own address register, data
register, and read-write control circuitry. A set of margin
switches is provided with each memory module that can be manually
changed to improve fault localization resolution and run preventive
maintenance routines. An amber lamp is provided on the memory
module front panel to indicate that any one or more of these
switches is off-normal.
Each word in Main Memory contains 26 bits: 24 bits are used for
storing data, 1 bit is used for storing the parity of the complete
word, and 1 bit is used for storing the "protect" status of the
word.
A 17 bit address bus allows any word in main memory to be directly
addressable. Each word can be read out of or "written" into, or
both. However a memory protect system is utilized to protect
specified locations in core from being altered. A hard wired
section of memory of 512 or 1024 words, within the first 1024
locations, cannot be written unless the memory protect system is
inactivated. The memory protect system can only be inactivated by
depressing the memory protect inhibit switch, on the Maintenance
control center panel. With the memory protect system active, other
locations in memory are protected by the setting of a read only
memory storage element in the CMC and that particular word having
bit 25 set. This read only memory storage element is programmed
controlled by a CPD instruction.
A parity check feature is provided for all memory transfer
operations (both reading and writing). The parity generation and
checking is provided in the CMC and extends over the complete
memory word, including the memory protect bit, for additional
security.
1.1.3 Addressing Alternates
For most instructions, which reference memory from the operand, the
following addressing modes are available.
Paging
the core memory of the Central Processor is organized into pages.
The maximum number of pages is four, with the maximum number of
location or addresses assigned to a page being 32,768. This totals
a maximum of 131,072 words of memory.
Addressing a page is via the hardware page register. Bits 15 and 16
(the 16th and 17th bits of the address bus) are taken from the
instruction field or the data field of the Page Register whenever a
memory reference occurs. The Page Register can be altered via
programmed instructions (refer to section 1.3.3 Paging).
Direct addressing
the operand or address field of an instruction specifies an address
within a page on a memory reference instruction. A maximum of
32,768 words of core within any one of four pages is directly
addressable.
Indexing
the contents of any one of the three 15 bit index registers is
added to the contents of the instruction address field to form a
new operand address. Indexing does not carry over into a new page,
rather a wrap around effect will occur. Indexing does not affect
the page register.
Indirect addressing
the address field of an instruction, after modification by indexing
if required, specifies a memory location which will contain a new
address for the operand. The indirect addressing is multilevel with
indexing allowed at each level.
The indexing operations always precede indirect referencing
operations. Indirect references proceed until the indirect address
bit is false. Instructions which are used to specify index
operations are themselves not indexable.
1.1.4 ARITHMETIC
Parallel, binary, fixed point arithmetic is provided in the No. 1
EAX computer. Single precision numbers are stored in memory as 23
bit integers (i.e., binary point at extreme right) with the highest
order (leftmost) 24th Bit considered as a sign.
Negative numbers are held in memory in two's complement form and
are operated on in the arithmetic unit in a two's complement number
system.
Provisions for double length products and dividend are made by
using two registers in the multiply and divide operations. The two
registers may be shifted logically or arithmetically and may be
logically rotated (circular shift).
1.1.5 INPUT/OUTPUT
The EAX processor input/output system is made up of two distinct
sections; the Computer Channel Multiplex and Channel Buffers.
The Channel Multiplex (CCX) provides a unique communication path
between the Central Processor and the Channel Buffer. The CCX can
accommodate a maximum of 16 Channel Buffers.
Standard Channel Buffers provided with a EAX Office Switching Unit
are: (1) Computer Channel Device Buffer. This buffer provides an
interface to the peripheral adapters which provide control features
for the operation of the Teletype Model 35ASR, Teletype Model
35KSR, Paper Tape Punch and Paper Tape Reader. (2) Computer
Communications Register. This shift register provides the serial
communication link between the Central Processor and the
Originating or Terminating Markers. (3) Maintenance Device Buffer.
This buffer provides a store and forward interface between the
Central Processor and the Maintenance and Control Center. (4)
Automatic Toll Ticketer. A channel buffer provides the interface
between the central Processor and the Automatic Toll Ticketer.
1.1.6 PRIORITY INTERRUPT
Since the operation of the No. 1 EAX system is dictated by events
occurring external to the Central Processor, provision is made to
alert the CP to these external occurrences; this provision is
called the Priority Interrupt system.
The interrupt system is a true multi-level system, 8 levels of
interrupt are available, and the program of highest active priority
is always being processed.
The eight general categories of interrupts and their priorities are
listed below.
1. Manual Requests and Power Failures
2. Major Alarm Errors
3. Real Time Clock
4. Communication Register and Drum Control Unit Ready
Interrupts
5. Register-Sender Requests for Translation
6. Minor Alarm Errors
7. Input/Output and Originating Marker Interrupts
8. Clock Errors and Register-Sender Minor Errors.
Additional program control is provided by separate instructions
which either DISABLE the interrupt system or ENABLE the interrupt
system.
1.1.7 TRAPS
Failures that could disrupt the No. 1 EAX system require immediate
attention. The priority interrupt system has a time lag of at least
one cycle time before recognition for service can be processed,
also a program disable feature can delay recognition for any length
of time. Because of these features, a trap system is used to
accommodate failure recognition. There are two trap levels, and
both have a higher priority than the interrupt system but only at
the time of failure. Once the trap has been recognized, and the BSP
instruction at the trap address has been processed, an interrupt
can occur. The recognition of the interrupt can be delayed,
however, by processing a disable interrupt (DSI) instruction.
Trap level 1 has a higher priority than trap level 2. Trap level 1
is called the third party trap. It is triggered whenever the
duplicated central processors, while running in sync, do not agree
with each other. Recognition of this trap is immediate. However,
the instruction in process is allowed to be completed before a
force is made to the trap location. (Refer to section 1.6 for
further detail).
Trap level 2 is called the computer error trap. It is triggered
when an error, internal to a central processor or its associated
computer memory control, occurs. Recognition of this trap is
immediate, and the instruction in process is aborted. (Refer to
section 1.6 for further detail).
1.1.8 COMPUTER REGISTERS
In addition to the registers shown in FIG. 3A, the computer
operates in conjunction with Memory Registers. Each memory module
contains its own data, or information register and its own address
register. Data registers are 26 bits (one parity and one protect
bit). Address registers may be 12 to 14 bits for module sizes of
4096 to 16,384 respectively. These registers are time multiplexed
as required between the central processor and a direct access I/O
device (optional). The memory registers are not accessible for
program control. 1.1.8.8 Register "PR" is a 6 bit register used to
specify bits 15 and 16 of the address bus. The 6 bits are assigned
to a data field (2 bits); a branch field (2 bits); and an
instruction field (2 bits). Program access to this register is via
the instruction set.
SECTION 1.2 Central Processor Instruction Set
1.2.1 Introduction
This section contains the description of the Central Processor
Circuit instructions. The descriptions are separated into
functional groupings.
All instruction execution times are expressed in terms of memory
cycles unless otherwise noted. The timing indicated includes
instruction access time and address modification time. Where
indirect addressing is specified, one additional memory cycle is
required.
Indexing and indirect addressing apply to every instruction unless
otherwise noted.
A timing cycle is equal to 2 .mu.sec plus time for memory reference
in some instructions. Refer to section 8.12.
The term "effective address," EA, is used to describe the final
operand field of the instruction after all indirect references and
modification. For memory reference instructions, the effective
address denotes the location of the memory cell containing the
actual operand. For non-memory reference instructions, the
effective address is used literally as the operand.
(EA) = Contents of Main Memory at the Effective Address within a
memory page.
(A) = Contents of Register A.
Ea = effective Address -- Indicates Direct or Literal Operation
Using Modified Address Field.
: = Colon Defined as Notation "if: then."
(nn) = Octal representation of Op code.
1.2.2 Arithmetic Group
Add (40) add Memory to A (A).sub.0.sub.-23 + (EA).sub.0.sub.-23
.fwdarw.(A).sub.0.sub.-23
the contents of the memory location at the effective address are
added to the contents of Register A. The sum replaces the contents
of the A register. If an overflow occurs, the overflow indication
will be set. A carry out of bit position 23 will be recorded by
setting the carry indicator.
Register affected: A
Timing: 2 cycles
Sub (41) subract Memory From A (A).sub.0.sub.-23
-(EA).sub.0.sub.-23 .fwdarw.(A).sub.0.sub.-23
the contents of the memory location at the effective address are
subtracted from the contents of Register A. The difference replaces
the contents of the A register. If an overflow occurs, the overflow
indicator will be set. A carry out of bit position 23 will be
recorded by setting the carry indicator.
Register affected: A
Timing: 2 cycles
Mul (42) multiply Memory by Register Q (EA).sub.0.sub.-23 .times.
(Q).sub.0.sub.-23 .fwdarw.(AQ).sub.0.sub.-47
register A is reset, the contents of the memory location at the
effective address are multiplied by the contents of register Q. The
product will replace the contents of the double precision registers
A-Q, bits 0-47.
Register affected: A and Q
Timing: 7.5 cycles min., 10.5 cycles max. ##SPC17##
The contents of the double precision registers A and Q are divided
by the contents of memory at the effective address. The quotient
will replace the contents of Register A. The remainder will replace
the contents of register Q and will be signed as dividend. If a
division overflow occurs, the overflow indicator will be set.
Division by zero will result in a computer error TRAP (LEVEL
2).
Registers affected: A and Q
Timing: 15 cycles
Adi (.phi.1) add Immediate (A).sub.0.sub.-23 + EA.sub.0.sub.-14
.fwdarw.(A).sub.0.sub.-23
the effective address is added directly to the contents of register
A. If indirect addressing is specified, only bits .phi. thru 14 at
the indirect address are added to register A. A carry out of bit
position 14 will propagate. If an overflow occurs, the overflow
indicator will be set. A carry out of bit position 23 will be
recorded by setting the carry indicator.
Register affected: A
Timing: 1 cycle; 2 cycles if Indexed
Sbi (.phi.2) subract Immediate (A).sub.0.sub.-23 - EA.sub.0.sub.-14
.fwdarw.(A).sub.0.sub.-23
the effective address is subtracted directly from the contents of
register A. If indirect addressing is specified, bits .phi. thru 14
at the indirect address take part in the subtraction process.
Borrows from bit positions of higher order than 14 will propagate.
If an overflow occurs, the overflow indicator will be set. A carry
out of bit position 23 will be recorded by setting the carry
indicator.
Register affected: A
Timing: 1 cycle; 2 cycles if Indexed
Aom (44) add One to Memory (EA).sub.0.sub.-23 +
1.fwdarw.(EA).sub.0.sub.-23
the contents of the memory at the effective address are incremented
and stored back in memory at the same address. Overflow and carry
indicators are not affected.
Register affected: None
Timing: 2 cycles
Som (45) subtract One from Memory (EA).sub.0.sub.-23 -
1.fwdarw.(EA).sub.0.sub.-23
the contents of the memory at the effective address are
decremented, and stored back in memory at the same address.
Overflow and carry indicators are not affected.
Register affected: None
Timing: 2 cycles
Adm (46) add A Register to Memory (A).sub.0.sub.-23 +
(EA).sub.0.sub.-23 .fwdarw.(EA).sub.0.sub.-23
the contents of the A register are added to the contents of the
memory at the effective address. The result is stored back in
memory at the same address. Overflow and carry indicators are not
affected.
Registers Affected: None
Timing: 2 cycles
1.2.3 Indexing Operations
(Multilevel Indirect Addressing is allowed but the loading of the
index bits of the tag field is suppressed)
Adx (2.phi.) add to Index (XR).sub.0.sub.-14 + EA.sub.0.sub.-14
.fwdarw.(XR).sub.0.sub.-14
(not Indexable). Add the effective address directly to the
specified index register. If no index register is specified, ADX
will be treated as a no-op. Overflow not affected.
Register affected: XR.sub.n
Timing: 1 cycle
Sbx (21) subtract from Index (XR).sub.0.sub.-14 - EA.sub.0.sub.-14
.fwdarw.(XR).sub.0.sub.-14
(not Indexable). Subtract the effective address directly from the
index register specified in the tag field of the instruction. If no
index register is specified, SBX will be treated as a no-op.
Overflow is not affected.
Registers affected: XR.sub.n
Timing: 1 cycle
Cax (22) clear and Add Index EA.sub.0.sub.-14
.fwdarw.(XR).sub.0.sub.-14
(not Indexable). Load the effective address bits 0 thru 14,
directly into the specified index register. If no index register is
specified, the CAX will be treated as a no-op.
Register affected: XR.sub.n
Timing: 1 cycle
Csx (23) clear and Subtract Index 2.sup.15 - EA.sub.0.sub.-14
.fwdarw.(XR).sub.0.sub.-14
(not Indexable). The effective address is loaded in two's
complement form into the specified index register. If indirect
addressing is specified, the effective address portion of the
memory word at the indirect address is loaded in two's complement
form to the specified index register. If no index register is
specified, the CSX will be treated as a no-op.
Register affected: XR.sub.n
Timing: 1 cycle
STX (26) Store Index (XR).sub.0.sub.-14 .fwdarw.(EA).sub.0.sub.-14
0 .fwdarw.(EA).sub.15.sub.-23
(Not Indexable). Store the contents of the specified index register
in the memory location at the effective address.
Register affected: None
Timing: 1 cycle
IBP (24) Increment Branch Positive (XR).sub.0.sub.-14
+1.fwdarw.(XR).sub.0.sub.-14 (XR).sub.14 =0:EA.sub.0.sub.-14
.fwdarw.(PC).sub.0.sub.- 14
(Not Indexable). The contents of the specified index register are
incremented. If bit 14 of that index register is zero, a branch to
the effective address will be executed.
Register affected: XR.sub.n :PC if Branch Occurs
Timing: 1 cycle
IBN (25) Increment Branch Negative (XR).sub.0.sub.-14
+1.fwdarw.(XR).sub.0.sub.-14 (XR).sub.14 =1:EA.sub.0.sub.-14
.fwdarw.(PC).sub.0.sub.- 14
(Not Indexable). The contents of the specified index register are
incremented. If bit 14 of that index register is not zero, a branch
to the effective address will be executed.
Register affected: XR.sub.n ; PC if Branch Occurs
Timing: 1 cycle
Bpx (3.phi.) branch Positive Index (XR).sub.14 = 0:EA.sub.0.sub.-14
.fwdarw.(PC).sub.0.sub.-14
(Not Indexable). A branch to the effective address will be executed
if bit 14 of the specified index register is zero.
Register affected: PC if Branch Occurs
Timing: 1 cycle
Bnx (31) branch Negative Index (XR).sub.14 = 1:EA.sub.0.sub.-14
.fwdarw.(PC).sub.0.sub.-14
(not Indexable). A branch to the effective address will be executed
if bit 14 of the specified index register is not zero. If no index
register is specified, or if the test fails, the BNX will be
treated as a no-op.
Register affected: PC if Branch Occurs
Timing: 1 cycle
Bzx (32) branch Zero Index (XR).sub.0.sub.-14 = O:EA.sub.0.sub.-14
.fwdarw.(PC).sub.0.sub.-14
(not Indexable). A branch to the effective address will be executed
if the contents of the specified index register are equal to
zero.
Register affected: PC if Branch Occurs
Timing: 1 cycle
1.2.4 Load and Store Group
Csa (56) clear and Subtract A 2.sup.24 - (EA).sub.0.sub.-23
.fwdarw.(A).sub.0.sub.-23
the contents of the memory at the effective address are loaded in
two's complement form into the A register. Overflow and carry
indicator are not reset.
Register affected: A
Timing: 2 cycles
RPA (57) Replace Address (EA).sub.15.sub.-23 .fwdarw.
(EA).sub.15.sub.-23 (A).sub.0.sub.-14 .fwdarw.
(EA).sub.0.sub.-14
The address portion of register A (bits 0 thru 14) replaces the
address portion of the memory word at the effective address. Bits
15 thru 23 of the memory word at the effective address are not
affected.
Register affected: None
Timing: 2 cycles
Lda (54) load A (EA).sub.0.sub.-23 .fwdarw.(A).sub.0.sub.-23
the contents of memory at the effective address are loaded into the
A register. The overflow and carry indicators are not reset.
Register affected: A
Timing: 2 cycles
Sta (55) store A (A).sub.0.sub.-23 .fwdarw.(EA).sub.0.sub.-23
the contents of register A are stored in memory at the effective
address.
Register affected: None
Timing: 1 cycle
Ldq (64) load Q (EA).sub.0.sub.-23 .fwdarw.(Q).sub.0.sub.-23
interrupt ignored during instruction. The contents of the memory at
the effective address are loaded into the Q register.
Register affected: Q
Timing: 2 cycles
Stq (65) store Q (Q).sub.0.sub.-23 .fwdarw.(EA).sub.0.sub.-23
the contents of the Q register are stored in memory at the
effective address.
Register affected: None
Timing: 1 cycle
Pra (60) place RS Memory into "A" Register
(Register Sender (EA)).sub.0.sub.-23 .fwdarw.(A).sub.0.sub.-23
The contents of the register Sender Memory at the effective address
are loaded into the A register of the CP. The overflow and carry
indicators are not reset.
Register affected: A
Timing: 2 cycles
Par(61) place "A" Register into RS Memory
(A).sub.0.sub.-23 .fwdarw.(Register Sender (EA)).sub.0.sub.-23
The contents of register A are stored in the Register Sender Memory
at the effective address.
Register affected: None
Timing: 1 cycle
Lpr (66) load Page Register
Interrupts Ignored During Instruction
This Op-Code with its extended field allows the loading of the data
field and branch field of the page register. This instruction is
indexable. A zero extended OP code will be treated as a no-op.
Lpd (661) load Data Field EA.sub.3,4 .fwdarw.(PR).sub.4,5
(not Indexable)
The effective address bits 3 and 4 are loaded directly and
respectively into bits 4 and 5 of the Page Register.
(DATA FIELD).
Register affected: Page Register
Timing: 1 cycle
Lpb (662) load Branch Field EA.sub.0,1 .fwdarw.(PR).sub.2,3
(not Indexable)
The effective address bits 0 and 1 are loaded directly and
respectively into bits 2 and 3 of the Page Register.
(BRANCH FIELD).
Register affected: Page Register
Timing: 1 cycle
Lpdb (663) load Data and Branch Fields
(Not Indexable) EA.sub.3,4 & 0,1 .fwdarw.(PR).sub.4,5 &
2,3
the effective address bits 3,4,0 and 1 are loaded directly and
respectively into the Page Register bits 4,5 (DATA FIELD) and 0,1
(BRANCH FIELD).
Register affected: Page Register
Timing: 1 cycle
Tid (664) transfer Instruction Field to Data Field
(Not Indexable) (PR).sub.0,1 .fwdarw.(PR).sub.4,5
this instruction will allow data storage reference within the
memory page of the running program.
Register Affected: Page Register
Timing: 1 cycle
Ldc (74) load Output Channel (EA).sub.0.sub.-23
.fwdarw.(OC).sub.0.sub.-23
the contents of the memory at the effective address are loaded on
the output channel. A separate sampling level is extended to
external devices to indicate when data is stable.
Register affected: None
Timing: 2 cycles
Stc (75) store Input Channel (IC).sub.0.sub.-23
.fwdarw.(EA).sub.0.sub.-23
the contents of the input channel are stored in memory at the
effective address. A separate sampling level is extended to the
external devices to acknowledge storage.
Register affected: None
Timing: 2 cycles
1.2.5 Miscellaneous Control Group (37) (Non-Indexable) DSI Disable
Interrupt (SET INIT) (3700001)
Interrupts are accepted into the WAIT STATE. Interrupts will not be
scanned and therefore not acknowledged by the Central Processor,
while in this state.
Register affected: None
Timing: 1 cycle
ENI Enable Interrupt (RESET INIT) (3700002)
All interrupts are acepted into a WAIT STATE and interrupt break
will be acknowledged during the next sequential instruction
providing it allows interrupt recognition. Thus this instruction
resets the DSI storage and will allow the interrupt system access
at the end of next processed instruction if that instruction allows
it.
Registers affected: None
Timing: 1 cycle
Ecr enable CPD Routine (Refer to Section 8.5 Maintenance)
(3700004)
This instruction sets a storage element, the output of which will
allow loading of the data bus into the "A" register of the Central
Processor during level 3 of a CPD instruction. The format of the
"A" register after loading is as follows: ##SPC18##
Bit 15 = cpd00 + cpd11 + cpd22 + cpd33
bit 16 = cpd01 + cpd12 + cpd23 + cpd34
bit 17 = cpd02 + cpd13 + cpd24 + cpd35
bit 18 = cpd03 + cpd14 + cpd25 + cpd36
bit 19 = cpd04 + cpd15 + cpd26 + cpd37
bit 20 = cpd05 + cpd16 + cpd27 + cpd30
bit 21 = cpd06 + cpd17 + cpd20 + cpd31
bit 22 = cpd07 + cpd10 + cpd21 + cpd32
register affected: RA
Timing: 1 cycle
Dcr disable CPD Routine
(3700010)
This instruction resets the storage element set by ECR. Register
affected: None
Timing: 1 cycle
Rei reset Error Indicators
(3700020)
All internal Central Processing Unit stored error indicators will
be cleared. These include: Memory Even Parity Error, Invalid OP
Error, Division by Zero Error, Error Trap and
Cmc errors.
Register affected: None
Timing: 1 cycle
Mps memory Protect Set
(3700040)
The WMPB indicator is set. This becomes bit 25 of the data bus.
Register affected: None
Timing: 1 cycle
Mpr memory Protect Reset
(3700100)
The WMPB indicator is reset.
Register affected: None
Timing: 1 cycle
Bps set Bad Parity
(3700200)
This instruction generates bad parity to main memory in the
following manner.
Whenever this storage element is set by the above execution, the
succeeding memory reference instructions will generate bad parity.
The Store Register A (STA) instruction or Place A in
Register-Sender (PAR) instruction or character copy out (CCO)
instruction or load channel (LDC) will generate bad data parity to
either Main memory (STA) or Register-Sender memory (PAR) or to the
channel multiplexor (CCO or LDC). Any other memory reference
instruction will generate bad address parity. PRA will generate bad
address parity to the Register-Sender memory while all the others
(Operation Code = 26 or 40 through 77 except 55 (STA) and 61 (PAR)
will generate bad address parity to the Main Memory. Indirect
addressing will also cause bad address parity.
Registers affected: None
Timing: 1 cycle
Bpr reset Bad Parity
(3700400)
Resets the Bad Parity Storage element.
Registers affected: None
Timing 1 cycle
Ssrtc switch to standby real time clock
(3701000)
this instruction sets a storage element, the output of which
switches the MAIN REAL TIME CLOCK output off thus allowing the
STANDBY REAL TIME CLOCK to run. A simulated MAIN REAL TIME CLOCK
ERROR is created causing a level 8 interrupt.
Register affected: None
Timing: 1 cycle
Smrtc switch to main real time clock
(3702000)
this instruction resets the above storage element. The MAIN REAL
TIME CLOCK takes over and the error indication caused by the
previous action (SSRTC) is removed.
Register affected: None
Timing: 1 cycle
Enwd enable Watch Dog Timer
(3704000)
This instruction enables the Watch Dog Timer so that it can reset.
(See 8.6)
Register affected: None
Timing: 1 cycle
Riw reset Interrupt Waits
(3720000)
This instruction resets the Wait States of the eight Interrupt
Levels.
Register affected None
Timing: 1 cycle
Note: simultaneous selection of separate operators is allowed,
e.g., 3700021 will effect the DSI and the REI operation. Ambiguous
selections attempting to specify two states of a single operator
(e.g. 3700014) result in unpredictable operation.
Rwd reset Watch Dog Timer
(3710000)
This instruction resets the Watch Dog Timer.
(See 8.6)
Register Affected: None
Timing 1 cycle
Sync resync Watch Dog Timer
(3740000)
This instruction resynchronizes the Watch Dog Timer. (See 8.6 for
operation).
Register affected: None
Timing: 1 cycle
1.2.6 Branch and Skip Group
Rtn (10) branch Unconditional EA.sub.0.sub.-14
.fwdarw.(PC).sub.0.sub.-14
the next instruction in program sequence is at the effective
address in the page specified by the instruction field of the Page
Register.
INDIRECT ADDRESSING of this instruction will load the Page Register
from the contents of the effective address as follows. When
returning the data contents of the locations specified by the
operand bits 0-14 will be loaded into the IR register in the normal
manner and then loaded into the program counter; bits 15 thru 18
will be loaded into the branch and data fields of the Page
Register. Thus return linkage to a different page other than the
one where the RTN resides is possible. (refer to section 1.3.3
Paging).
Register affected: PC; PR if indirect
Timing: 1 cycle; 2 cycles if indirect
Bun (11) branch Unconditional EA.sub.0.sub.-14
.fwdarw.(PC).sub.0.sub.-14
the next instruction in program sequence is at the effective
address in the page specified by the instruction field of the Page
Register.
Register affected: PC
Timing: 1 cycle
Bao (35) branch A Register Overflow OVF = 1:EA.sub.0.sub.-14
.fwdarw.(PC)
(not Indexable)
If the A register overflow indicator is set, the next instruction
is taken from the location specified by the effective address. The
overflow indicator is reset.
Register affected: PC if Branch Occurs
Timing: 1 cycle
BZA (13) Branch if A Register Zero (A).sub.0.sub.-23 =
0:EA.sub.0.sub.-14 .fwdarw.(PC)
the next instruction is taken from the location specified by the
effective address if the A register contents are zero.
Register affected: PC if Branch Occurs
Timing: 1 cycle; 2 if Indexed
Bna (14) branch if A Register Negative A.sub.23 =
1:EA.sub.0.sub.-14 .fwdarw. (PC)
the next instruction is taken from the location specified by the
effective address if the contents of register A are negative.
Register affected: PC if Branch Occurs
Timing: 1 cycle; 2 if Indexed
Bpa (15) branch if A Register Positive A.sub.23 =
O:EA.sub.0.sub.-14 .fwdarw.(PC)
the next instruction is taken from the location specified by the
effective address if the contents of register A are positive.
Register affected: PC if Branch Occurs
Timing: 1 cycle; 2 if Indexed
Bsp (62) branch and Store Program Linkage
OVF.fwdarw.(EA).sub.20, CARRY.fwdarw.(EA).sub.19,
(LPR).sub.0.sub.-3 .fwdarw.(EA).sub.15.sub.-18, (LPC).sub.0.sub.-14
.fwdarw.(EA) .sub.0.sub.-14
The current contents of the program counter and the page register
as stored in the last program count register and the last page
reference register and the overflow indicator and the carry
indicator, replaces the contents of the memory word at the
effective address. The next instruction is taken from the effective
address plus one. This instruction will delay an interrupt by one
instruction.
This instruction facilitates real time sub-routine linkages. The
interrupt dealy feature provides a safeguard against inadvertent
sub-routine re-entry; the interrupt system may be disabled by the
first instruction in the sub-routine.
Register affected: PC
Timing: 2 cycles
Brr (16) branch Return Reset EA.sub.0.sub.-14 .fwdarw.PC:
0.fwdarw.INT. ACTIVE
if indirect
(EA).sub.20 V OVF .fwdarw.OVF, (EA).sub.19 V CARRY
.fwdarw.CARRY
(EA).sub.15.sub.-18 .fwdarw.(PR).sub.2.sub.-5 (EA).sub.0.sub.-14
.fwdarw.(IR).sub.0.sub.-14
the next instruction is executed at the effective address. The
highest active interrupt is reset.
Register affected: PC
Timing: 1 cycle; 2 if Indexed
This instruction is used to exit from an interrupt subroutine and
should be an indirect reference to the subroutine link location to
properly restore the interrupted program. SMNT (7.phi.) Skip Memory
Not True, i.e., if A and Memory Do not Compare Ones.
(A).sub.0.sub.-23.sup.. (EA).sub.0.sub.-23 .noteq.0: (PC) + 1
.fwdarw.(PC)
Contents of the memory at the effective address are compared with
register A. If they do not match in positions that contain a one in
register A, skip one instruction.
Register affected: PC if Skip
Timing: 2 cycles
Smnz (71) skip if A and Memory Do Not compare Zeros
(A).sub.0.sub.-23.sup.. (EA).sub.0.sub.-23 .noteq.0: (PC) + 1
.fwdarw.(PC)
Contents of the memory at the effective address are compared with
register A. If the memory operand does not contain zeros in bit
positions corresponding to "ones" in register A, skip one
instruction.
Register affected: PC if Skip
Timing: 2 cycles
Smnn(77) skip if Memory Not Negative
(EA).sub.23 = 0: PC + 1 .fwdarw.(PC)
If Bit 23 of the memory location at the effective address is a
zero, skip one instruction.
Register affected: PC if Skip
Timing: 2 cycles
Ssnt (.phi.7) skip if Sense Group Not True
(SG.sub.n) .sup.. EA.sub.0.sub.-7 .noteq. 0: (PC) + 1
.fwdarw.(PC)
A portion of the effective address (bits 9 thru 7) form a mask.
This mask is compared to 8 sense line inputs in any of 128 possible
groups as specifed by bits 8 thru 14 of the effective address. If
the selected sense line group and the mask do not compare one's,
skip one instruction.
Register affected: PC if Skip
Timing: 1 cycle; 2 cycles if Indexed
The word format of the SSNT is as follows: ##SPC19##
The SSNT instruction can be used to test the condition of a maximum
of 1024 individual input lines.
The sense group numbering, by nature of the position in the
computer instruction follows the sequence (000, 010, 020, . . .
760, 770, 004, 014, 024, . . . 764, 774).
See Section 1.5.3 for explanation of sense lines. See Section 8.3
for sense line assignments.
Sane (72) skip if A Register Not Equal to Memory
(EA).sub.0.sub.-23 - (A).sub.0.sub.-23 .noteq. 0:(PC) + 1
.fwdarw.(PC)
The contents of the memory at the effective address are compared
with the A register. If the A register is not algebraically equal
to the contents of the memory location at the effective operand
address, skip one instruction.
Register affected: PC if Skip
Timing: 2 cycles
Lsga (.phi.6) load Sense Group into "A" Register
0 .fwdarw.(A).sub.8.sub.-23
Selected SG .fwdarw.(A).sub.0.sub.-7
The upper seven bits of the effective address defines the desired
sense group. The assignment of sense group numbers for the
seventy-one (71) standard sense groups given in the SSNT
instruction also applies to this instruction. The contents of the
selected sense group is placed in the lower eight bit position of
the A register.
Register affected: A
Timing: 1 cycle
Samg (76) skip if Register A and Memory Do Not Compare
Equal as Masked by Register Q ##SPC20##
Register A and the contents of memory at the effective address are
compared in positions extracted by the mask bits of Register Q. If
they do not compare identically, skip one instruction.
Example:
Register A 6 7 4 0 6 1 5 3 (EA) 1 2 7 3 6 0 1 2 Register Q 0 0 0 0
7 0 0 0 (A).sub.0.sub.-23 .sym. (EA).sub.0.sub.-23 7 5 3 3 0 1 4 1
##SPC21##
Registers affected: PC if Skip
Timing: 2 cycles
Half Word Skips (.phi.4) Indexing will not affect extended Op
code
This is an extended operation provided for half word immediate (or
literal) tests of the A Register. The effective address field bits
12, 13 and 14 are used to specify the following skip tests: The
execution time is 1 cycle.
Slnt (.phi.4.phi.) skip Left Not True (A).sub.12.sub.-23.sup..
EA.sub.0.sub.-11 .noteq.0:(PC) + 1 .fwdarw.(PC)
skip one instruction if bits 12-23 of register A do not compare
one's as masked by bits 0-11 of the effective address.
Srnt (.phi.41) skip Right Not True (A).sub.0.sub.-11.sup..
EA.sub.0.sub.-11 .noteq.0: (PC) + 1 (PC)
skip one instruction if bits 0-11 of register A do not compare
one's as masked by bits 0-11 of the effective address.
Slnz (.phi.44) skip Left Not Zeros (A).sub.12.sub.-23.sup..
EA.sub.0.sub.-11 .noteq.0: (PC) + 1 (PC)
skip one instruction if bits 12-23 of Register A do not contain
zeros as masked by bits 0-11 of the effective address.
Srnz (.phi.45) skip Right Not Zeros (A).sub.0.sub.-11.sup..
EA.sub.0.sub.-11 .noteq.0: (PC) + 1 (PC)
skip one instruction if bits 0-11 of register A do not contain
zeros as masked by bits 0-11 of the effective address.
Slne (.phi.42) skip Left Not Equal (A).sub.12.sub.-23 -
EA.sub.0.sub.-11 .noteq.0: (PC) + 1 (PC)
skip one instruction if bits 0-11 of the effective address and bits
12-23 of register A are not equal.
Srne (.phi.43) skip Right Not Equal (A).sub.0.sub.-11 -
EA.sub.0.sub.-11 .noteq.0: (PC) + 1 (PC)
skip one instruction if bits 0-11 of the effective address and bits
0-11 of register A are not equal.
1.2.7 Shift Group
The execution time for all shift instructions is N + 3/4 cycles; N
is specified in the effective address of the instruction.
The notation convention utilized in the following descriptions are
iteration formulas. Termination occurs after N iterations unless
otherwise specified.
Sal (34.phi.) shift Register A Left Arithmetic
(A).sub.i .fwdarw.(A).sub.i + 1
0.fwdarw.(A).sub.0
(a).sub.22 .sym. (a).sub.23 :1 .fwdarw.ovf
(not Indexable) the A register is shifted left N bit positions.
Zeros are placed in the N least significant bits of Register A
(open end shift). An overflow occurs if the register is shifted
when bit 23 does not equal bit 22. N shifts will be completed
regardless of overflow.
Registers affected: A
Sar (341) shift Register A Right Arithmetic
(A).sub.i .sub..sym. 1 .fwdarw.(A).sub.i
(A).sub.23 .fwdarw.(A).sub.22
(a).sub.23 .fwdarw.(a).sub.23
(not Indexable) the A Register is shifted right N positions. Bit 23
is not changed and is shifted to bit 22 for each specifed
shift.
Registers affected: A
Lsl (342) long Shift Left Arithmetic
(A).sub.i 43 (A).sub.i .sub.+ .sub.1 ; (Q).sub.23 .fwdarw.(A).sub.0
; (Q).sub.i .fwdarw.(Q).sub.i .sub.+ .sub.1 ; 0.fwdarw.(Q).sub.0 ;
(A).sub.22 .sym. (A).sub.23 :1 .fwdarw. OV
(Not Indexable) the double precision register A-Q is shifted left N
bit position. Zeros are entered into the least significant N bits
of A-Q. An overflow will occur if the double register is shifted
when A.sub.23 does not equal A.sub.22. Bit 23 of Register Q is
shifted. N shifts will be completed regardless of overflow.
Registers affected: A-Q
Lsr (343) long Shift Right Arithmetic
(A).sub.i.sub.+1 .fwdarw.(A).sub.i ; (A).sub.0 .fwdarw.(Q).sub.23 ;
(Q).sub.i.sub.+1 .fwdarw.(Q).sub.i ; (A).sub.23 .fwdarw.(A).sub.22
; (A).sub.23 .fwdarw.(A).sub.23
Not Indexable. The double precision register A-Q is shifted right N
bit position. Bit A.sub.23 is not changed, however, its value is
copied into Bit A.sub.22. Bit Q.sub.23 is shifted. Bits shifted
beyond Q.sub.0 are lost.
Registers affected: A-Q
Smp (344) shift and Mark Position
(A).sub.23 =1 Termination 0.fwdarw.(Q).sub.0 ; (Q).sub.i
.fwdarw.(Q).sub.i.sub.+1 ; (Q).sub.23 .fwdarw.(A).sub. 0 ;
(A).sub.i.fwdarw.(A).sub.i.sub.+1
(Not Indexable) A.sub.23 is tested to see if it equals one. If
A.sub.23 .noteq.1, A-Q registers are shifted left until A.sub.23 32
1 or the number of shifts equal the maximum field length has been
tested, the number of shifts is placed in the index register
specified by the TAG field.
Registers affected: A, Q, X
Llr (120) long Left Rotate
(A).sub.i .fwdarw.(A).sub.i.sub.+1 ; (Q).sub.23 .fwdarw.(A).sub.0
;
(q).sub.i .fwdarw.(Q).sub.i.sub.+1 ; (A).sub.23
.fwdarw.(Q).sub.0
the double precision register A-Q is shifted right N bit positions.
Bit Q.sub.0 is shifted to bit A.sub.23 ; and bit A.sub.0 is shifted
to bit Q.sub.23.
Registers affected: A-Q
Lrr (121) long Right Rotate
(A).sub.i.sub.+1 .fwdarw.(A).sub.i ; (A).sub.0 .fwdarw.(Q).sub.23
;
(q).sub.i.sub.+1 .fwdarw.(Q).sub.i ; (Q).sub.0
.fwdarw.(A).sub.23
the double precision register A-Q is shifted right N bit positions.
Bit Q.sub.0 is shifted to bit A.sub.23 ; and bit A.sub.0 is shifted
to bit Q.sub.23.
Registers affected: A-Q
Lla (122) left Shift A Logical
(A).sub.i .fwdarw.(A).sub.i.sub.+1 ; 0.fwdarw.(A).sub.0
the contents of register A are shifted left N bit positions. Zeros
are entered in the least significant N Bits of register A. Bits
shifted out of position A.sub.23 are lost. No overflow is
recorded.
Register affected: A
Llq (124) left Shift Q Logical
(Q).sub.i .fwdarw.(Q).sub.i.sub.+1 ; 0.fwdarw.(Q).sub.0
the contents of register Q are shifted left N bit positions. Zeros
are entered in the N least significant bits. Bits shifted out of
Q.sub.23 are lost. No overflow is recorded.
Register affected: Q
Lra (123) right Shift A Logical
(A).sub.i.sub.+1 .fwdarw.(A).sub.i ; 0.fwdarw.(A).sub.23
the contents of register A are shifted right N bit positions. Zeros
are entered in the N most significant bits of register A. Bits
shifted out of position A.sub.0 are lost.
Register affected: A
Lrq (125) right Shift Q Logical
(Q).sub.i.sub.+1 .fwdarw.(Q).sub.i ; 0.fwdarw.(Q).sub.23
the contents of register Q are shifted right N bit positions. Zeros
are entered into the N most significant bits of Register Q. Bits
shifted out of Q.sub.0 are lost.
Register affected: Q
1.2.8 logical Operator Group
Ana (5.phi.) and a with Memory (A).sub.0.sub.-23 .sup..
(EA).sub.0.sub.-23 .fwdarw.(A).sub.0.sub.-23
the contents of memory at the effective address and Register A are
compared bit by bit. Register A will contain a one where
corresponding bits in both register A and the memory word are
one's. The result remains in A.
Register affected: A
Timing: 2 cycles
Ora (51) or (Merge) Memory with A
(a).sub.0.sub.-23 v (ea).sub.0.sub.-23
.fwdarw.(a).sub.0.sub.-23
the contents of the memory at the effective address and Register A
are compared bit by bit. Register A will contain a one in bit
positions corresponding to those in which either Register A or the
memory word contain a one. The result remains in A.
Register affected: A
Timing: 2 cycles
Era (52) exclusive-Or Memory with A
(a).sub.0.sub.-23 .sym. (ea).sub.0.sub.-23
.fwdarw.(a).sub.0.sub.-23
the contents of the memory location at the effective address and
Register A are compared bit by bit. Register A will contain a one
where either register A or the memory word, but not both, contain a
one in corresponding bit positions. The result remains in A.
Registers affected: A
Timing: 2 cycles
Half Word Logicals (HWL)
This is an extended operation provided for half word immediate
logical operation on Register A. Three bits (12, 13 and 14) of the
effective address field are used to specify the following logical
operations.
Timing: 1 cycle, 2 if Indexed.
Anl (.phi.3.phi.) and Left (A).sub.i.sub.+12 .sup.. EA.sub.i
.fwdarw.(A).sub.i.sub.+12 ; 11 .gtoreq. i .gtoreq. 0
The effective address bits 0-11 are compared bit by bit with
register A bits 12-23. Register A bits 12-23 will contain a one
where corresponding bits in both register A and the effective
address contain a one.
Register affected: A
anr (.phi.31) and Right (A).sub.i.sup.. EA.sub.i .fwdarw.(A).sub.i
; 11 .gtoreq. i .gtoreq. 0
The effective address bits 0-11 are compared bit by bit with
register A bits 0-11. Register A bits 0-11 will contain a one where
corresponding bits in both Register A and the effective address
contain a one.
Register affected: A
orl (.phi.32) or Left (A).sub.i.sub.+12 V EA.sub.i
.fwdarw.(A).sub.i.sub.+12 ; 11 .gtoreq. i .gtoreq. 0
The effective address bits 0-11 are compared bit by bit with
Register A bit 12-23. Register A will contain a one where
corresponding bits in either effective address bits 0-11 or
register A bits 12-23 contain a one.
Register affected: A
Orr (.phi.33) or Right (A) V EA.sub.i .fwdarw.(A).sub.i 11 .gtoreq.
i .gtoreq. 0
The effective address bits 0-11 are compared bit by bit with
Register A bit 0-11. Register A will contain a one where
corresponding bits in either the effective address bits 0-11 or
Register A bits 0-11 contain a one.
Register affected: A
Erl (.phi.36) exclusive Or Left
(A).sub.i.sub.+12 .sym. EA.fwdarw.(A).sub.i.sub.+12 ; 11 .gtoreq. i
.gtoreq. 0
The effective address bits 0-11 are compared bit by bit with
register A bits 12-23. Reigster A will contain a one where
corresponding bits in either the effective address bits 0-11 or
Register A bits 12-23, but not both, contain a one.
Register affected: A
Err (037) exclusive Or Right
(A).sub.i .sym. EA.sub.i .fwdarw.(A).sub.i ; 11 .gtoreq. i .gtoreq.
0
The effective address bits 0-11 are compared bit by bit with
Register A bits 0-11. Register A will contain a one where
corresponding bits in either the effective address bits O-11 or
Register A bits 0-11 but not both, contain a one.
Register affected: A
Adl (034) add Immediate Left
Ea.sub.0.sub.-11 + (a).sub.12.sub.-23
.fwdarw.(a).sub.12.sub.-23
the effective address bits 0-11 are added to register A bits 12-23.
Register A bits 0-11 are not affected. Overflow and carry
indicators are not affected.
Register affected: A
Adr (035) add Immediate Right
Ea.sub.0.sub.-11 + (a).sub.0.sub.-11 .fwdarw.(a).sub.0.sub.-11
the effective address bits 0-11 are added to register A bits 0-11.
Register A bits 12-23 are not affected. Overflow and carry
indicators are not affected.
Register affected: A
1.2.9 program Control Group
Hlt (67) halt EA.sub.0.sub.-14 .fwdarw.PC
processing this instruction will cause the central processor to
stop. If the processor is on-line, a timer, after a delay of 1
microsecond, will cause the processor to run. If not on-line, then
a signal from the computer programming console or the computer
third party, will be required before the processor can start.
Register affected: None
Timing: 1 cycle
Xec (47) execute
The instruction at the effective address will be executed. The next
instruction will be taken from the location specified by the
program counter. Thus, a branch or a skip could change the program
counter. The instruction at the effective address may be indexable
or indirectly addressable.
Register affected: Refer to appropriate instruction being
executed.
Timing: 1 cycle plus Execution Time of Instruction
1.2.10 Input/Output Group
Sel (05) select Input Output Operation
The effective address is interpreted to select an input/ output
Channel Controller, Peripheral Adapter device and function at the
device for subsequent data transfer operations. Bit 14 of the
effective address is used to arm the Channel Ready Interrupt. A
Channel Controller disconnect function will disarm the interrupt.
The Priority Interrupt System will be disabled for one instruction
execution time. This instruction is also used in selecting third
party functions.
Register affected: None
Timing: 1 cycle
Cpd (17) control Pulse Directive
The effective address of this instruction is interpreted by
external functions as follows: ##SPC22##
Register affected: None
timing: 1 cycle
See Section 8.5 for CPD explanation.
Cca character Copy I/O Register A (33)
This is an extended operation provided for versatile input and
output word assembly and disassembly under program control. Three
bits (12, 13, and 14) of the effective address are interpreted as
an operation code extension field to determine register format
control. The N field is used in a manner similar to the shift
instructions to determine the number of binary positions for
rotation. This instruction is not indexable.
Cco character Copy Output
(33.phi..phi..phi..phi.6)
Rotate Register A left six binary digit positions
(N = 6) and copy bits 0-5 to the output channel.
(331 .phi..phi.1.phi.)
Rotate Register A left eight binary digit positions
(N - 10.sub.8 ) and copy bits 0-7 to the output channel.
(332 .phi..phi.14)
Rotate Register A left twelve binary digit positions
(N = 14.sub.8) and copy 0-11 to the output channel.
(333.phi..phi..phi..phi.)
Copy Register A bits 0-23 to the output channel.
Cci character Copy Input
(334 .phi..phi..phi.6)
Rotate Register A left 6 binary digit positions (N = 6)
and copy bits 0-5 of the input channel into bits 0-5
of Register A.
(335.phi..phi.1.phi.)
rotate Register A left 8 binary digit positions
(N = 10.sub.8) and copy bits 0-7 of the input channel into
bits 0-7 of Register A.
(336.phi..phi.14)
rotate register A left twelve binary digit positions
(N = 14.sub.8) and copy bits 0-11 of the input channel into
bits 0-11 of Register A.
(337 .phi..phi..phi..phi.)
copy bits 0-23 of the input channel into bits 0-23
of Register A.
Register affected: A
Timing: N + 7/4 cycles
1.2.11 Transfer and Exchange Group
Xam (53) exchange Register A and Memory
(EA).sub.0.sub.-23 .fwdarw.(A).sub.0.sub.-23
the contents of memory at the effective address are exchanged with
the contents of Register A.
Register affected: A
Timing: 3 cycles
Rtr (36x) register to Register
This is a non-indexable extended operation provided for operations
between registers. Three bits (12, 13, and 14) of the effective
address field are interpreted as an operation code extension (OPE)
field. The instruction word format for this instruction is as
follows: Single cycle. ##SPC23##
Crr copy Register to Register
Ope 000 (so) .fwdarw.(sk)
copy selected source register into sink register Source register in
uneffected. Multiple sources selection results in logical "OR"
copies. Multiple sink selection results in simultaneous copy to all
selected registers.
Ccr copy then Clear Register
Ope 001 (so).fwdarw.(sk); 0.fwdarw.(so)
copy selected source register to sink register. Source register is
cleared to zeros except PC which remains unaffected. Multiple
source selection results in a logical "OR" copies and cleared.
Multiple sink selection is allowed.
Exr exchange Registers
Ope 010 (so) (sk); (sk) (so)
exchange selected source register with selected sink register.
Multiple selection of source or sink will result in logical "OR" of
source or sink registers participating in the exchange For exchange
involving a small register and a large register, non-corresponding
bits are zeroed or lost as the case may be.
______________________________________ Bit 0 Reg A is the Sink 1
Reg Q is the Sink 2 Reg X1 is the Sink 3 Reg X2 is the Sink 4 Reg
X3 is the Sink 5 Reg Diag is the Source 6 Reg A is the Source 7 Reg
Q is the Source 8 Reg X1 is the Source 9 Reg X2 is the Source 10
Reg X3 is the Source 11 Reg PC and PR is the Source
______________________________________
See section 8.2 for register to register operation map.
Section 1.3 address Modification
Address modification in the No. 1 EAX computer is accomplished by:
Indexing, Indirect Addressing, Paging.
Indexing and Indirect addressing operate directly with the operand
portion of the instruction.
Indirect addressing in specific instructions operates also on the
Page Register.
Paging operates only on the Page Register.
Indexing and indirect addressing are operators to an instruction
while paging in an instruction itself. Indexing and indirect
addressing can be used by themselves or in combination. If both are
specified, indexing is done first and then indirect addressing. The
instructions upon which the address modification is performed is
retained in memory in its unaltered form.
1.3.1 Address Modification Using Index Registers
Three hardware index registers are provided in the basic standard
mainframe for address modification. Any of the three registers
(X.sub.1, X.sub.2, X.sub.3) can be specified by the programmer by
encoding the appropriate bits in the tag field of the instruction.
The instruction is then executed as if its address field contained
the specified address of the instructions plus the contents of the
index register (additive indexing).
EXAMPLE
Instruction = ADD 47631,2 (Note: 2 specifies index register No.
2)
Contents of X.sub.2 = 00135
Address of Data = 47766
Address modification is accomplished by using binary radix
complement (2's complement) arithmetic modulo 2.sup.15. The
algorithm may be stated as follows:
EA = (Y + X.sub.n) modulo 2.sup.15 EA = Effective Address Y =
Specified Instruction Address X.sub.n = Specified Index
Register
A powerful set of instructions is provided for index register
modification. These instructions operate on the index registers
using 2's complement arithmetic modulo 2.sup.14. Thus, the index
registers may be incremented or decremented and tested for terminal
condition by examination of the highest order bit. The incrementing
and decrementing operations may be explained as follows:
1. Index register in "positive" range -- Index register may be
incremented or decremented and terminal test is for a "one" in the
15th bit position (negative index).
2. Index Register in the "negative" number range. -- Index register
may be incremented or decremented in this range and the terminal
test is for a "zero" in the 15th bit position (positive index).
This method of indexing allows the programmer complete flexibility
in his choice of address manipulation.
Literal Add (ADX) and Subtract (SBX) operations on the specified
index registers, coupled with individual conditional Branch
instructions provide yet another degree of programming freedom.
Programming flexibility is further enhanced by the provision of
literal clear and subtract index (CSX) and the clear and add index
(CAX) instructions. By the use of these instructions, an index
register is easily initialized. The literal index operator
instructions are unique in the use of the indirect reference bit.
These instructions are normally used to load the index register
directly from the operand field of the instruction, however, if the
indirect addressing bit is set, the index register is loaded from
memory at an effective address specified by the address field of
the instruction.
Register transfer instructions (RTR) provide the capability of
transferring the index registers to any other operating register
and conversely, from the operating registers to the index
registers.
1.3.2 Indirect Addressing
The concept of providing alternatives for addressing is extended by
the use of indirect addressing. In very much the same manner as the
index registers are specified by 2 bits in the tag field, indirect
addressing also is specified by a separate bit in the tag field;
thus allowing an instruction to have index modification and
indirect addressing by a single tag field specification.
If an instruction operation calls for an operand to be retrieved
from memory, and if that same instruction has its indirect
addressing tag bit set, the address field of the instruction after
modification by the indexing operations refers to the memory
location at which the address of the operand will be found.
Further, if that location also has the indirect tag bit set, the
contents of that location after modification by indexing, is
interpreted as the address at which the address of the operand will
be found. Thus, the indirect addressing and indexing process is
iterative. Instruction execution time is increased by one cycle for
each level of indirect addressing. The following example will
further illustrate the concept of indirect addressing (*will be
used to indicate the indirect address tag field bit):
LOCATION CONTENTS REMARKS ______________________________________
00345 *ANA 43217 Instruction to be executed. 43217 * 0037416
Location of next indirect address. 37416 00037500 Location of
operand address. 37500 77777777 Operand location.
______________________________________
1.3. Paging
In order to increase the memory addressing capabilities of the
Central Processor beyond the 32K of directly-addressable core
memory that is possible with its 15 bit address field, a paging
technique is employed. A page consists of no more than 32K of core
memory. No more than 4 pages are to be implemented under present
design. This limits the size of core memory to 131K. To implement
paging, a page register, a last page reference, and paging
instructions are described as follows.
1.3.3.1 The Page Register will be a six-bit storage register:
The Page Register is sectioned into three fields:
a. The DATA FIELD is bits 4 and 5,
b. The BRANCH FIELD is bits 2 and 3.
c. The INSTRUCTION FIELD is bits 0 and 1.
The format for the Page Register is as follows: ##SPC24##
1.3.3.2 Last Page Reference
The Last Page Reference is a four-bit storage register, sectioned
into two two-bit fields, called the LAST DATA FIELD, and the LAST
INSTRUCTION FIELD.
The format for the Last Page Reference is as follows: ##SPC25##
The LAST DATA FIELD is loaded during every Cycle One, Level Two,
except when a trap occurs. The LAST DATA FIELD is loaded from the
DATA FIELD of the Page Register.
The LAST INSTRUCTION FIELD is loaded during every Cycle One, Level
Two (except when a trap occurs), from the INSTRUCTION FIELD of the
Page Register.
1.3.3.3 The Paging instructions are as follows:
LOAD PAGE REGISTER GROUP (66)
(Not indexable)
This is an extended operation, provided for the loading of the Page
Register.
The effective address field, bits 12 and 13, is used to specify
which field of the Page Register is to be loaded. Bit 14 of the
effective address is used to specify a transfer of INSTRUCTION
FIELD information bits into the DATA FIELD.
Bits 0, 1, 3, and 4 of the operand will specify the page number to
be loaded into the selected field, except during a transfer of the
INSTRUCTION FIELD into the DATA FIELD. In this latter case bits 0,
1, 3 and 4 are ignored.
Simultaneous selection of the extended OP codes is allowed. E.g.
06630011 will load both the BRANCH FIELD and the DATA FIELD of the
Page Register with page 01.
This is a single-cycle instruction.
Interrupts will be ignored during this instruction.
(Refer to Section 1.5.2.2)
Lpd (661): load data field ea.sub.3,4 .fwdarw.(pr).sub.4,5
(not Indexable)
The effective address, bits 3 and 4, is loaded directly and
respectively into bits 4 and 5 of the Page Register (DATA
FIELD).
Register affected: Page Register
Timing: 1 cycle
Lpb (662): load branch field ea.sub.0,1 .fwdarw.(pr).sub.2,3
(not Indexable)
The effective address, bits 0 and 1, is loaded directly and
respectively into bits 2 and 3 of the Page Register (BRANCH
FIELD).
Register affected: Page Register
Timing: 1 cycle
Lpdb (663): load data and branch field ea.sub.3,4 & 0,1
.fwdarw.(pr).sub.4,5 & 2,3
(not Indexable)
The effective address, bits 3, 4, 0 and 1 is loaded directly and
respectively into bits 4, 5 (DATA FIELD) and 2, 3 (BRANCH FIELD) of
the Page Register.
Register affected: Page Register
Timing: 1 cycle
Tid (664): transfer instruction field to data field
(not indexable) (PR).sub.0,1 .fwdarw.(PR).sub.4,5
this instruction will allow referencing data storage within the
instruction storage references of the running program.
Register affected: Page Register
Timing: 1 cycle
Rtn (10)..return ea.sub.0.sub.-14 .fwdarw.(pc)
(indexable)
This instruction is an unconditional branch, the same as BUN with
the following exception:
When RTN is processed indirect, bits 15 thru 18 of the indirect
location will be loaded into the BRANCH FIELD and the DATA FIELD of
the Page Register, bits 2 through 5 respectively.
Brr (16) branch return reset
when this instruction is processed indirect it will load bits 15
thru 18 of the indirect location into the branch field and the data
field, bits 2 thru 5 respectively, of the Page Register. (Refer to
instruction set section 1.2 for further information on this
instruction).
Bsp (62) branch and store program linkage
bsp will store the LAST DATA FIELD and the LAST INSTRUCTION FIELD
of the Last Page Reference Register into bits 18 and 17 and bits 16
and 15 of the location referenced by the operand. Bits 0 through 14
therefore, contain the Last Program Count Register (LPC); bits 15
and 16 contain the LAST INSTRUCTION FIELD: and bits 17 and 18
contain the LAST DATA FIELD. Bits 19 and 20 will contain the carry
and overflow indicators.
When processed indirect, BSP will inhibit loading of address bits
15 and 16 onto the Address Bus, thus forcing the memory reference
to page 00. The data word read from the indirect location is stored
in the processor's logic and appears at the output of the Adder.
Adder bits 15 and 16 are loaded into the BRANCH FIELD of the Page
Register. The BRANCH FIELD becomes the address source and specifies
the page where the Last Page Reference Register and Last Program
Count Register is to be stored.
The Exact location within that page is specified by the "S"
register. After storage of the information, the Adder output, bits
17 and 18, are loaded into the DATA FIELD of the Page Register, and
the BRANCH FIELD is transferred to the INSTRUCTION FIELD of the
Page Register.
Rtr.. register-to-register transfer
the Page Register will become a source whenever the Program Counter
becomes a source. Thus when used in this way with Register A or
Register Q, the address plus the six bits of the Page Register can
be transferred to these programmable registers so that the Page
Register can be interrogated for maintenance purposes. PRO-5 to
(A+Q) 15-20.
1.3.3.4
the Address bus of the Central Processor contains the 15 bits of
the "S" register or the program counter, depending whether a data
reference or an instruction reference is in process, and two bits
from the output of the Page Register. These two bits, (15 and 16)
are the controlled "OR"(ed) output of the DATA FIELD, BRANCH FIELD
and INSTRUCTION FIELD of the Page Register.
1.3.3.5
Definition of DATA AND INSTRUCTION storage
1.3.3.5.1
DATA storage is defined as those locations of memory where
references are made for the purpose of:
1.3.3.5.1.1
Loading information into programmable registers Instructions that
do this are: ADD (40), SUB (41), MUL (42), DIV (43), CSA (56), LDA
(54), LDQ (64), ANA (50), ORA (51), ERA (52), XAM (53), PRA
(60).
1.3.3.5.1.2
modifying locations: Instructions that do this are: AOM (44), SOM
(45), ADM (46), STX (26), RPA (57), STA (55), STQ (65), STC
(75).
1.3.3.5.1.3
executing an instruction out of sequence with the running program.
Such an instruction is XEC (47).
1.3.3.5.1.4
comparing such storage. Instructions that do this are SMNT (70),
SMNZ (71), SANE (72), SANG (73), SAMQ (76), SMNN (77).
1.3.3.5.1.5
distributing data to the input-output path. Instructions that do
this are LDC (74) and PAR (61).
1.3.3.5.1.6
modifying the address or operand of any instruction, except BUN
(11), BSP (62), HLT (67) and RTN (10), BRR (16).
1.3.3.5.2
instruction storage is defined as those locations of memory where
references are made for the purpose of:
1.3.3.5.2.1
Obtaining the next instruction to be processed, except XEC (47)
1.3.3.5.2.2
modifying the address of a BUN (11), HLT (67), RTN (10), BRR (16)
instruction.
1.3.3.5.2.3
Storing the Last Page Register and LPC (Last Program Count)
Register, and then branching to the following location, where the
storage took place. The instruction that does this is a BSP (62).
In this case the BRANCH FIELD will be the page source.
1.3.3.6
Address Modification
1.3.3.6.1
Indexing is accomplished over the 15-bit operand field of the
instruction. Indexing will not be extended to the Page Register.
Thus, if indexing modifies the operand beyond the 15-bit capacity,
a "wrap-around" effect will occur within the page referenced.
1.3.3.6.2
Indirect modification of the operand of an instruction will be via
the DATA FIELD of the Page Register, except in the BRR, BUN, HLT,
and RTN instructions. These instructions will use the Instruction
Field as memory references. An additional exception will be the BSP
instruction. BSP indirect will inhibit the output of the Page
Register, forcing the indirect reference to page .phi..phi.. The
location referenced will point to the page and location where the
Last Page Reference Register and LPC are to be stored. During the
BSP instruction the Page Reference Register LAST DATA FIELD and
LAST INSTRUCTION FIELD are stored at the location specified, and
the Page Register is loaded with the data and branch information
that was stored in the indirect reference.
1.3.3.7
Features of Page Register and Last Page Reference Register
Operation
1.3.3.7.1
Whenever any branch instruction is executed, the BRANCH FIELD of
the Page Register will transfer its contents into the INSTRUCTION
FIELD.
1.3.3.7.2
during data storage references, the DATA FIELD of the Page Register
will be gated onto the Address Bus of the CCP.
1.3.3.7.3
during instruction storage references, the INSTRUCTION FIELD of the
Page Register will be gated onto the Address Bus of the CCP, except
during the BSP instruction. For this instruction the BRANCH FIELD
is used as the page source.
1.3.3.7.4
During each Cycle One, Level Two, Pulse Three, the LAST DATA FIELD
and the LAST INSTRUCTION FIELD of the Last Page Reference Register
will be loaded from the DATA FIELD and INSTRUCTION of the Page
Register, except when a trap occurs. 1.3.3.8 Example of Page
Register Operation
Page 00 ______________________________________ LOCATION MACHINE
LANGUAGE ASSEMBLER LANGUAGE ______________________________________
00100 00000104 A NDS 00000000+E 00101 00102 00103 00104 00100106 E
NDS 00105 06610010 LPD 01 00106 05400112 LDA K 00107 41000104 RTN*E
(=RTN G) 00110 00111 00000005 NDS 05 00112 05400111 L NDS 05400111
______________________________________
Contents of Page 01 ______________________________________ LOCATION
MACHINE LANGUAGE ASSEMBLER LANGUAGE
______________________________________ 00100 06200102 A BSP C 00101
01100105 B BUN F 00102 00100101 C NDS 00103 04700112 D XEC L 00104
41000102 E RTN*C (=RTN B) 00105 46200100 F BSP*A (=BSP E) 00106
41100112 G BUN*K (-BUN J) 00107 00110 00111 06700111 J HLT $ 00112
00000111 K NDS 0111 ______________________________________
Initial Conditions for the Example
The initial condition of the Page Register is DATA FIELD = 00,
BRANCH FIELD = 01, INSTRUCTION FIELD = 01, and the Program Counter
of the CCP = 00100.
This initial condition allows the processing of the instruction
located in page 01, address 00100. The BSP to location C references
instruction storage. The BRANCH FIELD of the Page Register
indicates the page in which location C resides. The BSP instruction
will store contents of the DATA FIELD and the INSTRUCTION FIELD of
the Page Register into location C (Bits 18 thru 15). Condition of
the Page Register after this instruction is: ##SPC26##
Since the INSTRUCTION FIELD of the Page Register is set to 01, and
the Program Counter of the CCP now equals 00103, the next
instruction to be processed will be XEC. XEC references data
storage and since the DATA FIELD of the Page Register is set to 00,
the data in location L (00112) in page 00, will be processed as an
instruction, and will in this case, load Register A of the CCP from
location 00111 in page 00. This is because the LDA instruction
references data storage and the DATA Field still is set to 00.
Condition of the Page Register after this instruction is:
##SPC27##
The INSTRUCTION FIELD is at 01 and the Program Counter of the CCP
is at 00104, therefore the next instruction to be processed resides
in page 01 location 00102. RTN*C references instruction storage.
Location C (00102) is in page 01 as indicated by the INSTRUCTION
FIELD of the Page Register, and contains the return location
(00101) and the stored DATA FIELD and INSTRUCTION FIELD. The stored
values for DATA FIELD and INSTRUCTION FIELD are loaded respectively
into the DATA FIELD and the BRANCH FIELD of the Page Register. The
BRANCH FIELD's contents are then transferred into the INSTRUCTION
FIELD, so that the return can be complete. Condition of the Page
Register after this instruction is: ##SPC28##
The Progam Counter of the CCP now reads 00101, and the INSTRUCTION
FIELD of the Page Register reads 01. The next instruction is read
from page 01, location 00101. The BUN F is processed as an
instruction storage. No changes are made to the Page Register and
the next instruction is read from Page 01, location F (00105).
The instruction BSP*A inhibits the output of the Page Register, so
that location A (00100) in page 00 will be referenced. The BSP
instruction will temporarily store not only bits 9 through 14 of
the referenced location, but also, bits 15 through 18. These bits
will contain information for the BRANCH FIELD and the DATA FIELD of
the Page Register respectively. Before loading the information into
the Page Register, however, the DATA FIELD and the INSTRUCTION
FIELD contents of the Page Register will be stored. After storage,
the Page Register will be loaded, and then the BRANCH FIELD will
transfer its contents to the INSTRUCTION FIELD. Processing of the
instruction has now changed the Page Register so that the
INSTRUCTION FIELD is now 00 or pointed to page 00. The next
instruction therefore will be read out of Page 00, location 00105.
These changes in the Page Register occur during the BSP*
instruction: ##SPC29##
The next instruction to be processed is in Page 00, location 00105.
An LPD (Load Data Field) instruction is inserted at this point,
because the next instruction to be processed references data
storage in page 01. (LDA K requires data from page 01 location K
(00112). The LPD 01 will load the Page Register's DATA FIELD = 01.
There will be no change in the other fields. The next instruction
processed, then, would be the LDA K. Since LDA K references data
storage and the DATA FIELD is equal to 01, Register A will be
loaded with 00000111. Since the next instruction to be processed,
RTN*E, does not use the DATA FIELD for memory references, and since
the RTN*E will pick up new DATA FIELD information, it is not
necessary to use a LPD to alter the DATA FIELD of the Page
Register.
RTN*E references instruction storage. Location E (00104) is in page
00 as indicated by the INSTRUCTION FIELD of the Page Register. This
storage contains the return location (00106) and the stored DATA
FIELD and INSTRUCTION FIELD. The stored DATA FIELD and INSTRUCTION
FIELD are loaded into the DATA FIELD and BRANCH FIELD of the Page
Register. The BRANCH FIELD contents are then transferred into the
INSTRUCTION FIELD, so that the return can be complete.
Conditions of the Page Register during this instruction are:
##SPC30##
The INSTRUCTION FIELD points to page 01 and the Program Counter of
the CCP reads 00106. The BUN*K references instruction storage and
goes to location K, (00112) in page 01 for the address where the
next instruction resides. The Page Register is not changed at this
time. Condition of the Page Register after this instruction is:
##SPC31##
Page 01 and location 00111 hold the instruction HLT $. This is an
instruction storage reference. The address of the next instruction
is in Page 01, location 00111. No change to the Page Register.
1.4 ARITHMETIC
The Computer performs binary, fixed point, arithmetic computations
on basic single precision (24 bits) data words. For certain
arithmetic operations, (e.g. MUL. DIV. SHIFT) register Q is
provided for some degree of extended precision. The extended
register Q facilitates double precision operations but it is
emphasized that the basic accumulation of an arithmetic process is
single precision only. Extensive shifting and exchange operations
on registers A and Q are provided to simplify programmed multiple
precision subroutines. Extended precision is provided for multiply
operations in that the product of two single precision numbers can
result in a double precision product which in turn appears in
registers A and Q as if they were a single register. Division on
the other hand, is basically an inverse of multiplication and
register A-Q is now used for a double precision divident; the
resultant remainder appears in register Q and the quotient in
register A.
Negative numbers are represented in 2's complement form. The
arithmetic shifting operations are consistent with this notation
##SPC32##
An overflow indicator is provided for the following:
a. a Sum or a difference (resulting from ADD, ADI, SUB or SBI
operations) that cannot be contained within the A register.
b. A Division operation which would result in a quotient exceeding
the capacity of the A register (Division by zero is a special case
resulting in a trap level 2)
c. The results of arithmetic left shift operations (SAL, LSL,)
which would exceed the number range of the original data words (for
example a negative number that is shifted into a positive number
range).
A CAR storage element is set whenever a carry out of bit 23 of the
adder is true during an ADD, SUB ADI or SBI instruction. The
storage element is reset when a carry is not true out of bit 23 of
the adder during an ADD, SUB, ADI or SBI instruction.
The CAR storage element is also set during a BRR instruction
indirect, if the indirect location contained bit 19 true.
Section 1.5 priority Interrupt and Sense Line System
1.5.1 Introduction
The Computer Central Processor is equipped, with a real time,
priority Interrupt and Sense Line System, to handle external
requests and abnormal conditions.
All external signals that require immediate service are assigned to
one of the eight levels of interrupt priority. Each of these
signals are also assigned to a unique Sense Line as are other
external signals not requiring immediate attention. Some internal
indicators of the Central Processor are also assigned to Sense
Lines.
1.5.2 Interrupt System
1.5.2.1 Description
There are eight levels of Interrupt. Priority is hard wired and the
highest level is assigned to Interrupt One, the next highest level
of priority is assigned to Interrupt No. two and so on down to the
lowest level which is assigned to Interrupt No. eight.
The Interrupt System is scanned each instruction cycle to see if a
signal, with a higher priority than the program running, requires
servicing. If such a signal exists the Central Processor is forced
to execute an instruction from the dedicated location of the
interrupt involved. If linkage to the interrupt program is to be
saved a BSP instruction should reside in the dedicated location.
After processing the signal, the use of a BRR instruction indirect
will take you back into the program where the interrupt occurred,
and into the next sequence of instructions. The BRR will have also
reset the highest Active Interrupt.
1.5.2.2 Interrupt Control: Enable and Disable
There are two control instructions which allow the programmer to
exercise some influence over the interrupt system. The enable
Interrupt (ENI) is provided to allow interrupts to break into the
running program. The disable interrupt (DSI) is provided, so that
the running program will not be bothered with an Interrupt
Break.
Certain instructions will ignore interrupt requests during their
process time. This will enable at least one more instruction to be
processed before being forced to an interrupt address. These
instructions are the, BSP (Branch and Store Last Program Count),
thus protecting the loss of its re-entry capability. ENI (enable
Interrupts), thus allowing programming to enable the interrupts,
and to process at least one more instruction without interrupt. LDQ
(Load Register Q), thus allowing the program time to process a
sense line instruction (SSNT or LSGA) for the purpose of
interrogating the sense line indication of the 25th bit of the
memory location referenced by the LDQ. An interrupt between the
processing of these two instructions can lose the indication. LPR
(Load Page Register), thus allowing the Last Page Register to
reflect the updated Page Register and maintain correct linkage. SEL
(Select an I/O Channel or Third Party), thus allowing a subsequent
data transfer.
1.5.2.3 Priority Interrupt Assignments to levels and their unique
Sense Lines (See Section 8.4).
1.5.2.4 Priority Interrupt Operation
Any given priority interrupt level may be in one of three states:
Inactive, Wait, Active.
The inactive state is completely neutral; no interrupts are
awaiting service and none are being serviced.
The wait state stores the fact that an external signal requires
servicing. The wait state will persist until all higher level
interrupts which are waiting or are active, have been processed.
When all higher level interrupts have been serviced the wait
condition will be transferred to the active state.
The active state indicates that the Central Processor has
recognized that level of interrupt, has caused an automatic
transfer to the levels dedicated location and is being processed.
Interruptions by higher level interrupts, or traps will not change
this state, but will defer the completion of the processing
associated with it. The active state is reset by the execution of a
BRR instruction when no other interrupt of higher priority is
active.
Disabling the Interrupt system does not affect the state of any
level. New signals will be allowed into wait states, Active
interrupts could be reset with BRR instructions. During a Disable
period no interrupt breaks will be formed.
The active state of each level can be interrogated via the Sense
Line group 52 the individual assignments are as follows:
64001 INTERRUPT 1 ACTIVE
64002 interrupt 2 active
64004 interrupt 3 active
64010 interrupt 4 active
64020 interrupt 5 active
64040 interrupt 6 active
64100 interrupt 7 active
64200 interrupt 8 active
1.5.3 sense Line System
1.5.3.1 Description
Certain conditions within the Central Processor and within the
subsystems external to the Central Processor must be available for
immediate decision making. The Sense Line system is the
concentration point of these signals and its output is controlled
by the Two Sense Line Instructions SSNT (Skip Sense Line not true)
and LSGA (Load Sense Group into Register A).
These two instructions present the following format: ##SPC33##
The tag field is for indirect addressing or indexing as explained
in section 1.3. Both SSNT and LSGA, instrucions can be indexed and
are capable of indirect addressing.
The op code field specifies the instruction.
The octal numeral representation for LSGA is 06.
The octal numeral representation for SSNT is 07.
The group specifies one of a possible 128 sense groups. Each group
contains 8 Sense Lines. All groups are not implemented. Some groups
are specified for maintenance use, others are for furture
expansion.
The group field, (numeral representation,) by nature of it's bit
position in the instruction follows the sequence (000, 010, 020, .
. . , 760, 770, 004, 014, 024, . . . , 764, 774). Each group is
assigned a decimal numeral. The decimal numeral is not directly
translatable to the octal representation of it's associated group,
however a translation is obtainable by the following algorithm.
1. Convert the decimal to three octal digits.
2. Rotate answer left one octal digit.
3. Multiply the right most digit by 4.
Examples
decimal 52 converts to octal 064
rotate left one equals 640
multiply right most digit by 4 equals 640
decimal 71 converts to octal 107
rotate left one equals 071
multiply right most digit by 4 equals 074
The Sense Line Field is useful only with the SSNT instruction.
During the SSNT instruction the 8 bits of the field are used as a
mask, to indicate which of the sense lines, are to be tested. The
LSGA instruction ignores the Sense Line Field.
1.5.3.2 Operation
When the condition of a sense line is required, a SSNT or a LSGA
instruction must be used. The SSNT instruction, via its group
field, selects a group of 8 sense lines and signals the sense line
system to invert their output. The mask of the SSNT instruction is
then "and" (ed) with the eight sense lines, and the results
checked.
If the results are all zeros, then the Sense lines that were true
corresponded with bits of the mask that were true. No action will
take place and the program will proceed to the next
instruction.
If the result is not zero then the masked and true bits of the
sense lines did not match and the program counter will be
incremented by one. This will result in the program skipping the
next sequential instruction.
The LSGA instruction like the SSNT instruction selects a group of
eight sense lines, however, it does not want the 8 lines inverted.
Instead it loads the eight lines, as is, into the "A" register of
the Central Processor. The eight lines can then be processed in
whatever manner the program chooses.
1.5.3.3 Sense Line Assignments
As stated previously Sense lines are assigned to groups, and that
certain groups are specified for maintenance. The reason for the
maintenance assignment is for routining Sense Group Cards (See
section 1.5.4).
The assignments of all implemented signals are as follows:
Maintenance Groups
______________________________________ NUMERIC REPRESENTATION
DECIMAL OCTAL ______________________________________ 0 000 8 100 16
200 24 300 32 400 40 500 48 600 56 700 64 004 72 104 80 204 88 304
96 404 104 504 112 604 120 704
______________________________________
1.5.4 maintenance
1.5.4.1 Tools (Hardware and Software)
For efficiency in routining, 16 CPD instructions were implemented
for the Computer Line Processor system.
The CPD instruction for the CLP has the following format.
##SPC34##
The tag field defines address modification (Indexing and indirect
addressing are allowed).
The Directive field and a description is as follows. (Octal
representation).
000 -- LOCKOUT ALL EXTERNAL SIGNALS
Inhibits all external signals from entering system.
001 -- RESET LOCKOUT
002 -- set test signals true
this simulates a true condition on all external signals that
normally enter the system. It does not simulate the signals from
the CCP.
003 -- set test signals false
this simulates a false condition on all external signals that
normally enter the system. It does not simulate the signals from
the CCP.
004 -- reset: control signal errors, pseudo clp cpd signals, gate
group signals and gate card signals.
control Signals Errors are:
Cpd clp err 1 sense line 04420
cpd clp err 2 sense line 04440
sync err 1 sense line 04404
sync err 2 sense line 04410
cls cont err 1 sense line 04500
cls cont err 2 sense line 04600
005 -- cls clear:
this signal clears all Sync Hold Storage Elements.
006 -- INHIBIT IS SYNC 1
This CPD will not allow a sync pulse into unit 1 of the CLP. The
affect will be a CLS CONT ERR 1 and 2 (sense lines 04500 &
04600).
007 -- INHIBIT IS SYNC 2
This CPD will not allow a sync pulse into unit 2 of the CLP. The
affect will be a CLS CONT ERR 2 and 1. (sense lines 04600 &
04500).
010 -- PSEUDO IS SYNC 1 (from CCPA)
This CPD will extend the normally 100 nanosecond IS Sync Pulse into
a 500 nanosecond pulse. This will simulate a stuck true condition.
The affect will be a SYNC ERR 2 (SENSE LINE 04410) and an inhibit
of the IS SYNC 1 signal.
011 -- PSEUDO IS SYNC 2 (from CCPB)
This CPD will extend the normally 100 nanosecond IS SYNC Pulse into
a 500 nanosecond pulse. This will simulate a stuck true condition.
The affect will be SYNC 2 signal.
012 -- PSEUDO p1 1
This CPD will expand the normal 100 nanosecond P1, from CCPA, to
500 nanoseconds. This will result in a simulated stuck true
condition for P1. The affect will be to set SYNC ERR 2 (sense line
04410). The possibility also exists that one or both of the CLS
CONT ERR flops will set (sense lines 04500 and 04600).
014 -- SET PSEUDO CLP CPD 1
This storage element will provide a signal that will create a CPD
CLP ERR 2 on the next non CPD instruction. It simulates a stuck
true condition. The affect will inhibit the CLP CPD 1 signal.
015 -- SET PSEUDO CLP CPD 2
This storage element will provide a signal that will create a CPD
CLP ERR 1 on the next non CPD instruction. It simulates a stuck
true condition. The affect will inhibit the CLP CPD 2 signal.
016 -- GATE GROUPS
This CPD will set a storage element that will gate the decode of
the 7 groups assigned to each card and card 9 onto the sense line
bus for use by the CCP during an SSNT or LSGA instruction. The
groups are to be selected during the selection of card 16 and card
9 is selected with group 1. This storage element is reset with
004.
017 -- GATE CARDS
This CPD will set a storage element that will gate the decode of
the first 8 cards onto the sense line bus for use by the CCP during
an SSNT or LSGA instruction. The cards are to be selected along
with group 1. This storage element is reset with 004.
1.5.4.2 Operation
1.5.4.2.1 Routining of the Sense Line System requires either both
CCP(s) on line or both CCP(s) off line. So that routining will not
be interrupted the Interrupt System must be disabled, and all
external signals locked out via CCP, 01, 0. A CPD, 01, 02 will
place a true signal on all sense lines in all groups except the
following Groups 1, 2, 52, 60, 67, 68, 69, 70 and 71. A true signal
will be placed on lines 1 thru 6 of group 60, and on lines 1, 2 and
5 and 6 of group 67; by selecting each group via an LSGA or SSNT
instruction it can be verified whether the intended result exist.
After exercising as stated above the simulated signal can be set to
a false condition (CPD, 01, 03) and again the results can be
verified as above. Those Sense lines not included in the above test
are to be routined individually.
1.5.4.2.2 Routining of the Interrupt System.
With the Interrupt System Disabled, the MIS Instruction RIW (reset
interrupt waits) is executed along with 8 BRR (branch return reset)
instructions to initialize the interrupt system. The external
signals are locked out (CPD, 01, 00) and simulated to a true
condition (CPD 01, 02). The MIS instruction ENI (enable interrupts)
is executed. Only the Highest Priority level should request
servicing. Upon acknowledging the request and with the issue of a
BRR instruction the Highest level will be reset and the next
highest will request service and this will continue until all
interrupts have been serviced in succession. Any deviation
indicates a fault, and this fault can be isolated and
localized.
1.5.4.2.3 Routining of the Control Circuitry
The CLP receives its control signals from the duplicated CCP(S).
The signals are "OR"(ed) together only when the two CCP(S) are
on-line. When this condition does not exist then only the on line
CCP(S) signals are used. A failure in three of these control
signals at point where they are common to both halves of the CLP
system could bring the system down therefore hardware to detect
such an error is implemented. Hardware controlled by software (CPD
instructions) has also been implemented to exercise the error
detection circuitry. When such an error occurs (control signal
fault) the error detection hardware will lock out the signal from
bringing down the system and will set a storage element. A latent
fault could also exist in the control signal IS sync within a CLP
Power Module that would lock out all external signals to that half
of the system. Hardware will detect such a fault and the hardware
is exercised via a CPD instruction.
Test one would inhibit a sync pulse in one half of the system and
then the other half. (CPD 01, 06 and CPD 01, 07) an error should
occur in each instance (CLS CONT ERR 1 and CLS CONT ERR 2).
Test two would simulate the IS sync pulse stuck true first from one
CCP and then the other (CPD 010 and CPD 011) in each case the
storage elements SYNC ERR 1 and SYNC ERR 2 will be set.
Test three would set storage elements in both halves of the CLP.
(CPD 01, 014; CPD 01, 015). These storage elements would simulate
the CLP CPD signal stuck true and would be programmed such that
first one would be set and tested and then the other. In each case
subsequent instruction executions which were other than CPD would
set the error storage elements. CPD CLP ERR1 and then CPD CLP ERR
2.
Test four would gate the group decode circuitry outputs on to the
Sense Line Bus for monitoring. (CPD, 01, 016). This is necessary to
catch a latent fault on the input to the decode circuitry. The use
of an LSGA or SSNT instruction can then determine if the correct
group is being selected and that only one group is being selected.
Group 1 does not exist on a card. SL 1 = group 2; SL2 = group 3;
SL3 = Group 4; SL4 = group 5; SL5 = group 6; SL6 = group 7; SL7 =
group 8; SL8 = CARD 9.
Test five would gate the Card decode circuitry outputs on to the
Sense line bus for monitoring. (CPD 01, 017) As in the case of the
group decode, this method is used to catch a latent fault. The LSGA
and SSNT instructions can determine if the correct card is being
selected and that only one card is selected. SL1 = Card 1; SL2 =
Card 2; CL3 = Card 3; SL4 = Card 4; SL5 = Card 5; SL6 = Card 6; SL7
= Card 7; SL8 = Card 8.
Card 9 was placed in group SENSE LINE 8. All faults in the system
can be isolated with the tools provided.
The block diagram of FIG. 17 shows the interfacing of the computer
line processor CLP with other subsystems for processing of sense
line and interrupt signals, for a duplicated system. The computer
line processor comprises duplicate units CLP-A and CLP-B. The
principal inputs are data sense lines in cables designated DSL. The
data sense lines from drum control units DCU-1, DCU-3 and DCU-5 are
routed via computer memory control CMC-A to line processor CLP-A;
while the data sense lines from drum control units DCU-2, DCU-4 and
DCU-6 are routed via computer memory control CMC-B to line
processor CLP-B. The data sense lines from the channel multiplex
units CCX-A and CCX-B are routed to their respective line processor
units CLP-B and CLP-B. The register-senders RS1-A and RS-1B have
data sense lines to line processor CLP-A, while RS-1B and RS-2B
data sense lines go to CLP-B. There are up to four pairs of
originating markers OM-A1 to OM-A4 and OM-B1 to OM-B4. The
terminating markers have a pair TM-A1 and TM-B1 for office section
1, a pair TM-A2 and TM-B2 for office section 2, and a pair TM-AS
and TM-BS for a selector section. The data sense lines from the
markers are cabled through the communication registers CCR-A and
CCR-B as shown to the respective line processors CLP-A and CLP-B.
There are also data sense lines from the computer central
processors CCP-A and CCP-B to the respective line processors CLP-A
and CLP-B. Control signal lines from the central processors CCP-A
and CCP-B are supplied to the line processors CLP-A and CLP-B.
There are also data sense lines from the maintenance routine logic
MRL to both line processors CLP-A and CLP-B. The eight merged sense
line leads SL.phi.-7 and address signals are supplied from the line
processors CLP-A and CLP-B to the computer central processors CCP-A
and CCP-B. Since the computer line processor receives many external
signals, and many of these signals are required by the maintenance
and control circuit, the specified signals are cabled directly to
the maintenance display and control circuit MDC.
Section 1.6 Trap System of the Computer Central Processor
1.6.1 Introduction
The trap system for the Computer Central Processor was devised to
handle those events that directly affect the internal operation of
the Processor, and to facilitate recovery from programming errors
There are two trap levels.
Trap level one third party trap
trap level two computer internal errors
1.6.2 traps: Description, Operation
1.6.2.1 Trap Level One (Third Party Trap)
1.6.2.1.1 Description:
Should a mismatch occur between the duplicated Central Processors,
while they are in sync, a Third Trap signal will be initiated by
the Third Party Circuitry.
This event is given the highest priority of any event associated
with the Central Processor and is assigned to trap level one.
1.6.2.1.2 Operation:
When a Third Party Trap signal is initiated the Central Processor
will allow the instruction in process to finish and then process
the trap. The Central Processor's timing generator will proceed to
cycle three where the trap address will be formed, and used, as an
address source. Thus the next instruction read from memory will be
located in the address specified. The address of where this trap
occurred plus one has been stored in the Last Program count
register and last page register. To Store this information a BSP
(Branch and Store Last Program Count) instruction must reside in
the trap address. No other trap can break in to a program while the
Third Party Trap is true. However Interrupts can occur from the
Interrupt system, unless a DSI (Disable Interrupt) Instruction is
implemented as the first instruction in the trap program.
1.6.2.2 Trap Level Two (Computer Internal Error Trap)
1.6.2.2.1 Description:
Should one of the following events occur in one or both of the
duplicated Central Processors, that Processor will initiate an
error trap signal.
1.6.2.2.1.1 Instruction Even Parity Error is true when even parity
is detected while reading a new instruction from memory.
1.6.2.2.1.2 Data Even Parity Error is true when even parity is
detected during the transfer of data from main memory, the
Register-Sender or the Channel Multiplexor.
1.6.2.2.1.3 Division by zero is true when during a division
instruction the divisor is detected as being all zeros.
1.6.2.2.1.4 Invalid Operation Code is true when the decode of the
Instruction operation field detects one of the following invalid
Codes. 00; 27; 63.
1.6.2.2.1.5 Memory Reference Time Out is true when one of the
memory reference signals remain true for more than 140
microseconds. Memory reference signals are Main Memory read, Main
Memory Write; Register-Sender, Read or Register-Sender Write.
Reason for failure is signal failure or lack of a feedback from the
Main Memory or Register-Sender.
1.6.2.2.1.6 Port 7 error is true when the Central Processor
attempts to access memory out of range, or when it attempts to
write into "Read Only" memory.
1.6.2.2.2 Operation
When an error trap signal is initiated the Central Processor will
abort the instruction in process, from the point of recognition. If
a read or write signal to memory is true the abort will be delayed
until the signals are removed.
The Central Processors timing generator will proceed to cycle three
where the error trap address will be formed and used as the address
source.
Note the error trap signal will be ignored if a Third Party trap
signal is present.
The address of where this trap occurred plus one has been stored in
the Last Program Count register and last page register. To store
this information a BSP (Branch and Store Last Program Count)
instruction must reside in the trap address.
Interrupts can occur from the interrupt system, unless a DSI
(Disable Interrupt) instruction is implemented as the first
instruction in the trap program.
The errors that caused the error trap signal as well as the error
trap signal itself can be reset by a REI instruction or a master
clear. An indication of which error caused the trap resides in the
Sense Line system under groups 1 and 2. Refer to section 8.3 for
Sense Line Assignments. Should an error signal that would usually
initiate an error trap occur, while in the error trap program, the
sense line associated with that signal will be the only indication
of it being active. Unless, therefore, that signal is scanned after
it becomes true, it is possible to lose it when an REI instruction
is executed.
Section 1.7 memory protect system
1.7.1 introduction
the Program Protect System of the computer provides hardware
protection for Computer Main Memory (CMM). The Program Protect
System is activated by releasing the INHIBIT MEMORY PROTECT switch
on the Maintenance Display and Control Panel (MDCF). All memory
protection is disabled when the Inhibit Memory Protect pushbutton
is operated.
Hardware in the Computer Memory Controller (CMC) allows four types
of protection for the main memory. The four are: Switch-Protected
Read Only Memory, Software- Protected Read Only Memory,
Initialization Table Protection and Block Transfer Area
(Non-Resident Area) Protection.
1.7.2 Switch-Protected Read Only Memory
This block of words in core may only be written into when the
INHIBIT MEMORY PROTECT pushbutton on the MCC is operated (Inhibit
position). Protection is in effect both for the Drum Control Units
(DCU's) and the computer Central Processor (CCP), regardless of
their status.
Bit 25 of each word in this block may be written into when the
INHIBIT MEMORY PROTECT pushbutton on the MDCF is operated and the
PCROM flip-flop is reset (CPD 012, 066). Bit 25 will be written
true if the MIS instruction MPS (03700040) has set the Write Memory
Protect Bit (WMPB) storage element. Bit 25 will be written False if
the MIS instruction MPR (03700100) has reset the WMPB storage
element.
Switch-Protected Read Only Memory is strappable to 512 or 1024
words and may start at location 0 or 512 but does not extend beyond
location 1023.
1.7.3 Software-Protected Read Only Memory
Program protection of individual words is available via the 26th
bit (Bit 25) of the word as written in core. This protection is in
effect for the Central Processor only. Drum Control Units may
overwrite Software-Protected Read Only Memory.
The Computer Maintenance Panel (PNL) or the Computer Programming
Console (PRC) write through the Central Processor and therefore
protection is in effect for these units. Software Protection, Bit
25 written True in core, may be applied to any location in core.
Protection however is redundant in Switch-Protected Read Only
Memory. A Software Read Only Memory Error will be generated when
trying to write into a software-protected location in
Switch-Protected Read Only Memory.
When the Program-Controlled Read Only Memory (PCROM) Active FF is
set and the INHIBIT MEMORY PROTECT pushbutton has not been operated
(Memory Protect System "ACTIVE" state) the Central Processor, PNL
or PRC can write into all core locations except Switch Protected
Read Only Memory. Bit 25 will be written into Core as a One if the
WMPB flip-flop is set or as a Zero if WMPB flip-flop is reset. If
the PCROM Active flip-flop is reset and INHIBIT MEMORY PROTECT
pushbutton has been operated (Memory Protect System `INHIBITED`
state) the CCP, PNL or PRC can write into any core location.
When the INHIBIT MEMORY PROTECT pushbutton has been operated
(Memory Protect System "Inhibited" state) the CCP can write into
any core location. However if the PCROM Active flip-flop is set and
the Central Processor writes into core, Bit 25 in core will always
be written as Zero regardless of the state of WMPB and correct
parity will be provided by CMC.
The PCROM Active flip-flop is a S/R latch located in the Computer
Memory Controller. The state of this latch is controlled by CPD
instructions and can be interrogated via sense line. The PCROM
Active latch is reset ("inactive state") by CLEAR.
1.7.4 initialization Table Protection
A 64-word block of main memory is dedicated to each DCU as its
initialization table. When a DCU is being initialized (Init lead to
CMC True) it may access only its own initialization table.
Otherwise a DRUM TABLE ERROR occurs and write operation is
aborted.
A DCU may write into another DCU's initialization table only when
it is "privileged," i.e., its PT lead to the CMC is true.
In summary, a DCU may access only its own initialization table when
it is in the initialization sequence and a DCU may not write
outside of its own initialization table or the Block Transfer Area
unless it is privileged or the INHIBIT MEMORY PROTECT pushbutton is
operated. All DCU initialization tables are contiguous within a
512-word block of main memory. The starting location of the first
DCU (DCU1) Initialization Table is strapped to the last word (word
511) of the 512-word initialization tables block minus (n + 1)
.times. 64, where n = 2,4,6 is the TOTAL number of DCU's attached
to the CMC. In this way the DCU Initialization Tables occupy the
highest-numbered addresses in the 512-word block leaving the last
64 words at the end of the block for other usage (trap and
interrupt addresses). The 512-word block may be strapped in
increments of 512 words to any location in core. However the trap
and Interrupt addresses generated by CCP are not relocatable.
1.7.5 Block Transfer Area Check
With initialization Table Protection this check may be considered
to be `Bound Checking` on DCU access to main memory. A DCU may not
write outside of its own initialization table or the Block Transfer
Area ("non-resident" Area) unless it is privileged. If a DCU
attempts to write outside these areas a DRUM TABLE ERROR will be
generated and write operation will be aborted. A DCU which is
privileged may write in any core location except Switch Protected
ROM. When the INHIBIT MEMORY PROTECT button is operated any DCU may
write in any location in core.
Section 2.0 main Memory and Drum Control
2.1 Main Memory
2.1.1 Introduction
The CMC (Computer Memory Control) can best be thought of as a
bi-directional multiplex - distributor such that any of the units
at the ports can transfer data to any memory bank in main memory
and data from any memory bank can be transferred to any port on a
one-transfer-at-a-time basis. FIG. 18 shows the maximum
configuration of Drum Control Units, Central Processors and CMC's
in a No. 1 EAX office. Smaller offices may have only 2 or 4 DCU's
(Drum Control Units). DCU's are supplied in redundant pairs.
2.1.3 Operational Description
The CMC operates on a request acknowledge basis. If no requests are
presented by the Drum Control Units or the Central Processor the
CMC and the core memories are idle. The Central Processor is
pre-selected as the Address Bus Source at the end of each memory
request and remains pre-selected if no requests are presented to
the CMC. This enables accelerated access to main memory by the CCP.
If a DCU request is presented to CMC a 350 ns timer is started to
allow selection of the port making the request and to allow the
address to propagate to the bank selection circuitry and to the
memory banks. At the end of the 350 ns delay if all main memories
have finished their previous requests a Start Read command is
issued to the main memory bank specified by the address bits
supplied by the requesting port.
The memory bank will return a Memory Busy signal and after the word
at the address specified has been read it will return a Data
Available signal and the data read at the address. On a read
request, a data available signal and the data, will be returned to
the port within 1.0 microseconds after the request was received. On
a read request, the CMC will send a Restore Control signal to the
memory and the word read from memory will be written back in. On a
write request at the end of the data available signal the CMC will
send to the memory bank the data to be written into the
location.
After the data is written into the data register of the memory it
will return a Data Loaded signal to the CMC and the CMC will return
a Data Loaded signal to a port having a write request. After the
data word has been written into memory and another memory cycle can
be initiated the Memory Busy signal will go false. The memory will
also return an END of Cycle signal which is used for timing in the
CMC.
The CMC has seven ports of which up to six DCU's and the CP will be
connected. Simultaneous memory requests are resolved by a
predetermined priority assignment to each port. Port 1 has the
highest priority, port 2 has the next highest and so on to port 7.
The Central Processor is assigned to port 7 due to the inability of
the DCU's to wait for any extended period. Service of one memory
request is always completed before another is started. The next
request to be serviced is always the one of highest priority in the
queue.
The port selection to determine which request will be answered can
be made while the previous request is being completed.
Failure of a port to remove a read request or write request after
it is answered will result in a Port Request Time-Out Error. Any
error which occurs while a port is accessing the memory will cause
the port to be locked out except for the CP, which is never
lockout. Also a read request or write request must be removed
before the next memory request from that port can be
recognized.
The time required for the Data Available signal to be sent to a
port after a read request is received varies from 0.8 microseconds
to (1.0 + 1.8N) microseconds where N is the number of the port in
the queue. The Data Loaded signal is sent to port N1.4 to (1.6 +
1.8N) microseconds after the write request is received.
A word is read from the magnetic drum of the Drum Memory system
once every 1.5 to 1.63 microseconds and since the words on the drum
have an interlace of five this means that the maximum time the DCU
can wait for a Data Loaded signal after a write request goes out is
7.5 microseconds. If four DCU's present read requests or write
requests to the CMC at a time when the CMC is answering a memory
request from the CP, then one of the DCU's may not have its request
answered in the time necessary and its CORE ACCESS TROUBLE sense
line to Computer Line Processor will go true. The DCU will remove
its write or read request and if it does not receive a malfunction
indication from the CMC a DCU TIME OUT interrupt will be generated
8 drum revolutions (approximately 136 milliseconds) after a request
was first sent to the DCU.
When the CMC's are running in sync the port selections of the two
CMC's must agree before a port can be selected. When a memory
request appears a 350 ns delay, Delay 1, will be started to allow
port selection to take place. At the end of Delay 1 a comparison
will be made to see if the port selections agree. If another memory
request was being answered when the memory request appeared, Delay
1 will not start until 150 ns after the fall of the Data Available
signal from the first request.
If two ports presented read requests at the same time it would be
possible for the two CMC's to select different ports. When at the
end of Delay 1, the port selections did not agree, a second delay,
Delay 2, of 150 nanoseconds would be started and at the end of it a
retry at port selection can be made. After the third retry a port
will be selected regardless of whether the port selections compare.
If three retries have been made and the port selections do not
agree an error interrupt will be generated and the PORT SELECT
RETRY ERROR sense line will go to the one state. Any write
operations will be aborted to a read operation and the Abort write
sense line will become true. Each retry adds a maximum of 614 ns to
the time required for port selection so that if three retries are
made, the third DCU will receive a Data Loaded signal within 7042
ns which is within the 7500 ns maximum required to guarantee that
the DCU does not encounter port blockage.
2.1.3 Status Indicators and Interrupts
Besides the data return leads the following outputs from the CMC
are connected directly to the CP to indicate the status of the CP's
read requests and write requests.
______________________________________ LEAD DESCRIPTION REMARKS AND
TIMING ______________________________________ DATA AVAILABLE
Indicates that data is being read from main memory. Becomes true
0.8 to (1.0 +1,8N) .mu.s after read request becomes true and
remains true for as long as read request is true. DATA LOADED
Indicates that data has been written into main memory. Becomes true
1.4 to (1.6+1.8N) .about.s after write request becomes true and
remains true for as long as write request is true. PROGRAM ERROR
Indicates that the CP caused an Address Out of Range, attempted
Read Only Memory Write or Protected Location Write malfunction
during main memory access. Becomes true 0.3 to (2.2+1.8N) .mu.s
after read request or write request becomes true. Reset by REI or
CLR. Causes a CP level 2 trap. COMPARE ERROR Indicates that a
mismatch was detected between the two CMC's. Causes a Computer
Third Party trap. ______________________________________
The only interrupts assigned to the CMC's are CMC 1 Error and CMC 2
Error in interrupt level 2 with octal sense line numbers 73002 and
73020 respectively. The following sense lines are assigned to the
CMC's:
COMPUTER MEMORY CONTROL: GROUP 53
______________________________________ OCTAL SENSE LINE NO. SENSE
LINE NAME SENSE LINE DESCRIPTION
______________________________________ 65001 PAICEST 1 Port Address
In Compare Error Stored. The Addresses supplied by the port are
different in the two CMC's. 65002 PDICEST 1 Port Data In Compare
Error Stored. The Data words supplied by the port are different in
the two CMC's 65004 PAIPEST 1 Port Address in Parity Error Stored
The address supplied by the Port has even parity. 65010 PDIPEST 1
Port Data In Parity Error Stored The data word supplied by the port
has even parity. 65020 PINVCIEST 1 Port Invalid Control In Error
Stored The port has made an invalid request for service. 65040
RTRYEST 1 Retry Error Stored The CMC's have made 3 port select
retries and the port selections still do not match. 65100 PTOEST 1
Port Time Out Error Stored The port has not removed its read or
write request after it was answered. 65200 CMC PROT SYSTEM ACT 1
The memory protection system has not been disabled by the switch on
the control panel. COMPUTER MEMORY CONTROL: GROUP 54
______________________________________ 66001 SYNCTOST 1 Sync Time
Out Stored The two CMC's have fallen more than 800 nanoseconds out
of synchronization. 66002 MARCEST 1 Memory Address Return Compared
Error Stored The addresses returned from the memories associated
with the two CMC's do not compare. 66004 MDRRCEST 1 Memory Data
Return Read Compare Error Stored The words read from the two
memories do not compare. 66010 MDRWCEST 1 Memory Data Return Write
Compare Error Stored The data words returned from the memories on
the write portion of the cycle do not compare. 66020 MARPEST 1
Memory Address Return Parity Error Stored The address returned by
the memory has even parity. 66040 MDRWPEST 1 Memory Data Return
Write Parity Error Stored The data returned from memory on the
write portion of the cycle has even parity. 66100 MINVCREST 1
Memory Invalid Control Return Error Stored The control signals
returned from memory are invalid. 66200 BSRCEST 1 Bank Select
Register Compare Error Stored The bank selections of the two CMC's
do not agree. COMPUTER MEMORY CONTROL: GROUP 55
______________________________________ 67001 BSMR[0]1 Bank Select
Malf Reg. These leads indicate the bank which was selected when the
first error occurred. 67002 BSMR[1] 1 67004 ABORT WRITE 1 A core
write transfer has been aborted to a READ/MODIFY/WRITE or core read
operation. 67010 PCIMR[RR] 1 Port Control in Malf Reg. These leads
contain the state of the Port Control In leads when the first error
occurred. 67020 PCIMR[WR] 1 67040 PCIMR[RMPB] 1 67100 PCIMR[PT] 1
67200 PCIMR[INIT] COMPUTER MEMORY CONTROL: GROUP 57
______________________________________ 71001 AOREST 1 Address Out
of Range Error Stored The address exceeds the range of memory used.
71002 ROMEST 1 Read Only Memory Error Stored The port has tried to
write into read only memory. 71004 CROSS WRITE ACTIVE FF SET Cross
Write configuration has been achieved. 71010 DTEST 1 Drum Table
Error Stored A DCU has tried to read or write outside of its
initialization table while in the initialization sequence or write
outside of its initialization table and outside of the block
transfer area while it was not privileged. 71020 PSMR[0] 1 Port
Select Malf Reg. These leads carry the binary-encoded number of the
port selected when the first error occurred. 71040 PSMR[1] 1 71100
PSMR[2] 1 71200 PSMR[3] 1 COMPUTER MEMORY CONTROL: GROUP 58
______________________________________ 72001 PMALFR[1] 1 Port
Malfunction Register 72002 PMALFR[2] 1 An error has occurred while
72004 PMALFR[3] 1 this port was selected. 72010 PMALFR[4] 1 72020
PMALFR[5] 1 72040 PMALFR[6] 1 72100 CCP PMALFR 1 72200 PMALFR[8]
COMPUTER MEMORY CONTROL: GROUP 59
______________________________________ 73001 PC ROMEST 1 Program
Controlled Read Only Memory Error Stored. The CCP has tried to
write into program controlled read only memory. 73002 CMC ERR ST 1
The CMC has detected one of the errors listed here. 73004 MDRRPEST
1 Memory Data Return Read Parity Error Stored. The data word read
from memory has even parity. 73010 PC ROMACT 1 Program Controlled
Read Only Memory Active Read only memory protection is in effect
for the program controlled read only memory selection. 73020 PC
ROMEST 2 Same as 73001 73040 CMC ERR ST 2 Same as 73002 73100
MDRRPEST 2 Same as 73004 73200 PC ROM ACT 2 Same as 73010 COMPUTER
MEMORY CONTROL: GROUP 61 ______________________________________
75001 PAICEST 2 75002 PDICEST 2 Similar to Group 53 75004 PAIPEST 2
75010 PDIPEST 2 75020 PINVCIEST 2 75040 RTRYEST 2 75100 PTOEST 2
75200 CMC PROT SYST ACT 2 COMPUTER MEMORY CONTROL: GROUP 62
______________________________________ 76001 SYNCTOST 76002 MARCEST
2 Similar to Group 54 76004 MDRRCEST 2 76010 MDRWCEST 2 76020
MARPEST 2 76040 MDRWPEST 2 76100 MINVCREST 2 76200 BSRCEST 2
COMPUTER MEMORY CONTROL: GROUP 63
______________________________________ 77001 BSMR[0] 2 77002
BSMR[1] 2 Similar to Group 55 77004 ABORT WRITE 2 77010 PCIMR [RR]
77020 PCIMR[WR] 2 77040 PCIMR[RMPB] 2 77100 PCIMR[PT] 2 77200
PCIMR[INIT] 2 COMPUTER MEMORY CONTROL: GROUP 65
______________________________________ 01401 AOREST 2 01402 ROMEST
2 Similar to Group 57 01404 CROSS WRITE ACTIVE 2 01410 DTEST 2
01420 PSMR[0] 2 01440 PSMR[1] 2 01500 PSMR[2] 2 01600 PSMR[3] 2
COMPUTER MEMORY CONTROL: GROUP 66
______________________________________ 02401 PMALFR [1] 2 02402
PMALFR [2] 2 Similar to Group 58 02404 PMALFR [3] 2 02410 PMALFR
[4] 2 02420 PMALFR [5] 2 20440 PMALFR [6] 2 02500 CCP PMALFR 2
02600 PMALFR [8] 2 ______________________________________
2.1.4 data and Instruction Formats
Besides the data bus and address bus the following inputs are
provided to the CMC from the CP.
______________________________________ Input Description
______________________________________ READ REQUEST Becomes true to
read main memory. WRITE REQUEST Becomes true to write into main
memory. SYSTEM MEMORY MP STAT is alway true unless the Disable
PROTEST STATUS Memory Protect Switch on the Maintenance Control
Panel is operated. RESET ERROR INDICATORS REI becomes true during
the execution of an REI instruction. MASTER CLEAR CLR is always
false unless the computer test panel is plugged in and the MASTER
CLEAR Push button is depressed or the THIRD PARTY CLEAR signal
becomes true to clear a CCP. CONTROL PULSE DIRECTIVE Control Pulse
Directive is a signal for CMC to interpret data bus bits 0 to 8.
CCP ON LINE The CP is on-line.
______________________________________
Control pulse directives from the CP are used to set or reset
Maintenance registers in the CMC. Which register receives a pulse
is determined by data bus bits 0 to 8 and the register is set if
bit 0 is a one and reset if it is a zero. The registers which are
set or reset by a control pulse directive and the various
combinations of bits 0-8 on the data bus are given in the following
list.
CMC Control Pulse Directive
__________________________________________________________________________
Data Bus Octal No. Action Description of Register
__________________________________________________________________________
000 MCLTR{MB}-RST Memory Control Logic 001 MCLTR{MB}-SET Test
Register {Memory Busy} MCLTR simulates a memory request from a port
and the control signals returned from the memory to test CMC
control logic. 002 MCLTR{DA} RST MCLTR {Data Available} 003 do. SET
004 MCLTR{DL} RST MCLTR {Data Loaded} 005 do. SET 006 MCLTR{EOC}RST
MCLTR {End of Cycle } 007 do. SET 010 MCLTR {MREQ}RST MCLTR {Memory
Request} 011 do. SET 012 MMDBSOCR{1}RST Maintenance Memory 013 do.
SET Data Bus Source 014 MMDBSOCR{2}RST Control Register 015 do. SET
By setting MMDBSOCR{1} 016 MMDBSOCR{3}RST {2} {3} the test points
017 do. SET previously listed will be connected to the data bus if
the CP is off-line 020 PENTR{1} RST Port Enable Test Register 021 "
SET {1 - 6} 022 PENTR{2} RST PENTR enables the CMC 023 " SET to
answer a memory 024 PENTR{3 } RST request from an off-line port 025
do. SET if the CP is off-line 026 PENTR{4} RST 027 do. SET 030
PENTR{5} RST 031 do. SET 032 PENTR{6} RST 033 do. SET 034 POLR{1}
RST Port On Line Register {1 - 6} 035 do. SET POLR controls the
on-line 036 POLR{2} RST status of the six DCU's 037 do. SET
attached to ports 1 to 6. 040 POLR{3} RST The POLR's of a DCU must
be 041 do. SET reset in both CMC's before 042 POLR{4} RST an
off-line indication is 043 do. SET given to that DCU. POLR is 044
POLR{5} RST also reset by the MASTER 045 do. SET CLEAR button on
the computer 046 POLR{6} RST test panel. 047 do. SET 050 INPUT TEST
Input Test Register {1-6} REG {1} RST 051 INPUT TEST REG {1} SET
052 INPUT TEST used to test the signal paths REG {2} RST from the
DCU's to the CMC's 053 INPUT TEST When an input test register REG
{2} SET is set all the inputs to the 054 INPUT TEST CMC's from that
DCU should REG {3} RST be true. 055 INPUT TEST REG {3} SET 056
INPUT TEST REG {4} RST 057 INPUT TEST REG {4} SET 060 INPUT TEST
REG {5} RST 061 INPUT TEST REG {5} SET 062 INPUT TEST REG {6} RST
063 INPUT TEST REG {6} SET 064 MCLTR{LCH-MDB}RST Memory Control 065
do. SET Logic Test Register {Latch Memory Data Bus} If the CP is
off-line setting MCLTR{LCH-MDB} latches the data bus so that a one
applied to the data bus remains on the data bus after the input is
removed. 066 PC ROM ACT-RST Program Controlled 067 PC ROM ACT-SET
Read Only Memory Active. Setting this register enables the program
controlled read only memory protection. 076 CROSS WRITE-RST 077
CROSS WRITE-SET Cross write enables an on-line CCP to write into
its own memory and the duplex memory which must be off
__________________________________________________________________________
line.
2.1.5 Configuration
The configuration of ports enables to access main memory is
software controlled. Two registers are provided in the CMC for
control of the ports. One bit in each register is assigned to each
port. For a DCU to access an `On Line` main memory (i.e CCP ON LINE
signal from CCP to CMC true) its associated bit in the Port On Line
Register (POLR 1-6) must be true. For the port to access an Off
Line main memory (the CCP ON LINE signal from CCP to CMC false) its
associated bit in the Port Enable Test Register (PENTR 1-6) must be
true. Bits of the POLR and PENTR are individually set by CPD
instructions. Bits of the POLR and PENTR are individually reset by
CPD instructions and both registers are reset to all zeros by
CLEAR. The status of the POLR and PENTR are available for
interrogation on Maintenance Memory Data Bus Source word 3. See
Section 2.1.4.
The status of Port 7 and Port 8 is under control of the Cross Write
feature, refer to section 2.1.6.
2.1.6 Maintenance Features
2.1.6.1 Error Detection
A list of errors detected by the CMC and their description appears
under CMC sense lines. Certain of these errors cause the CMC to
take immediate action.
All errors will cause the following actions. The port which was
accessing main memory will be blocked from any further access until
REI or CLEAR is received from the CCP. The CCP (PORT 7) is only
blocked if it does not remove its memory request after the request
is answered. Other errors do not block Port 7.
The Port Selected Malfunction Register (PSMR) is set indicating via
sense line which port was accessing memory when the error occurred.
The Bank Selected Malfunction Register (BSMR) set indicating via
sense line which bank of main memory was selected when the error
occurred. The Error Stored Flop and Disable Error Load Flop (ESF
and DERLF) are set. DERLF will prevent any subsequent errors from
changing the value of PSMR or BSMR and will prevent any subsequent
errors from changing the error indicators to the CLP. DERLF will
cause subsequent errors to be ignored by the CLP until the first
error is reset by REI or CLEAR from CCP.
If DERLF (disable error load flop) is set, a THIRD PARTY TRAP can
be caused by Synchronism Time Out (SYNCTOF) only, and an ERROR TRAP
can be generated.
In addition to the above any error will cause its associated sense
line to become true if DERLF was not previously set and to remain
true until REI or CLEAR is issued to CMC by CCP.
The following errors will cause an Error Trap if they occur while
the CCP is accessing main memory:
Read Only Memory Error (Switch protected)
Address Out of Range Error
Program Controlled Read Only Memory Error (25th bit protected
words).
The following errors will cause a Third Party Party Trap when both
CCP's are On Line only:
Bank Selection Comparison Error
Memory Address Returned Comparison Error
Memory Data Returned Read Comparison Error
Memory Data Returned Write Comparison Error
Port Address In Comparison Error
Port Data In Comparison Error
Retry Error (Port selection does not compare after three
retries)
Synchronism Time Out Error
A Third Party Trap is not generated by a miscomparison during Cross
Write. The associated sense line to CLP does become true.
To protect the integrity of information in memory the following
errors will generate a Restore Control Signal to Main Memory and
thus abort a write operation. If these errors occur during a write
operation a sense line to CLP, Abort Write, will become true:
Read Only Memory Error (Switch Protected)
Port Invalid Control In Error
Bank Select Comparison Error
Port Address In Compare Error
Port Address in Parity Error
Address Out of Range Error
Retry Error
Drum Table Error
Software Protected Read Only Memory Error.
2.1.6.2 Program Controlled Read Only Memory
A set-reset latch in CMC is provided to activate 25th bit read only
memory protection. (See section 1.7.3, Software Protected Read Only
Memory for the operational description of this latch.)
2.6.3 Maintenance Data Bus Source
The status of internal points in the CMC may be interrogated by
returning these points to the CCP on the Data Bus. When a CCP is
OFF LINE it is connected as a sink to the CMC Data Bus. (This is
also true during Cross Write).
By execution of the associated CPD instruction in the ON LINE CCP
the following three words describing the status of control points
may be placed on the Data Bus of the off line CMC and thus onto the
Data Bus of the off line CCP.
Mmdbsocr{1}
__________________________________________________________________________
data Bus Bits Test Point Description
__________________________________________________________________________
0-17 MAB (0-17) MEMORY ADDRESS BUS (0-17) The address bus of the
CMC may be the address in from port or the address returned for the
last Memory Bank accessed. 18-23 POLR (1-6) PORT ON LINE REGISTER
(1-6) The on-line status of the DCU's. 24 DATA BUS (0-25) causes
MMDBSOCR{1} to be EVEN PARITY sent to CCP with odd parity 25 EG
Logic 0 MMDBSOCR {2} 0 EG Logic 0 1 ROMF READ ONLY MEMORY FLIP-FLOP
The last Address in accessed Switch Protected Read Only Memory 2
DIIITF DRUM IN ITS INITIALIZATION TABLE FLIP-FLOP The last request
was from a DCU for a word in its initialization table. 3 DOBTAF
DRUM OUTSIDE BLOCK TRANSFER AREA FLIP-FLOP The last request was
from a DCU which accessed a location outside of the Non-Resident
area. 4 PCIR{RMPB} PORT CONTROL IN REGISTER {RETAIN MEMORY PROTECT
BIT} The last request was from CCP and Software Read Only Memory
Pro- tection was in effect. 5 PCIMR{RMPB} PORT CONTROL IN
MALFUNCTION REGISTER {RETAIN MEMORY PROTECT BIT} Same as above when
an error occurred. 6 MARGIN SW OFF NOR MARGIN SWITCH OFF NORMAL One
of the Power Supply Level switches on one of the Main Memories is
oper- ated to the `high` or `low` position. 7 MDRREPF MEMORY DATA
RETURNED READ EVEN PARITY FLIP FLOP Even parity on the word
returned from Main Memory during a ready cycle. 8 MDIEPF MEMORY
DATA IN EVEN PARITY FLIP FLOP Even Parity on the word supplied by
the port during a write cycle. 9 MDRWEPF MEMORY DATA RETURN WRITE
EVEN PARITY FLIP FLOP Even parity on the word returned from Main
Memory during a write cycle (will also become ture if MDRREPF is
true) 10 DERLF DISABLE ERROR LOAD FLIP FLOP No further errors will
be stored until REI or CLEAR is issued by CCP. 11 RTRY3F RETRY 3
FLIP FLOP 3 attempts have been made at port selection and port
selection does not compare. 12 MDF{25}F MEMORY DATA BIT {25} STORED
The status of bit 25 in the last core location accessed. 13 -PH0
PHASE 0 (inverted) A CMC internal timing pulse occurring while CMC
is idle. 14 -PH1 PHASE 1 (inverted) A CMC internal timing pulse
occurring where a memory request is received and before a Start
Read is issued to Main Memory. 15 PH2 PHASE 2 A CMC internal timing
pulse occurring while Start Read to Main Memory is true. 16 PH3
PHASE 3 A CMC internal timing pulse occurring after Start Read to
Main Memory is issued and before Data Available is returned. 17 PH4
PHASE 4 A CMC internal timing pulse occurring while Data Available
returned from Main Memory is true. 18 -PH5 PHASE 5 (inverted) A CMC
internal timing pulse occurring during a 150 ns monopulser which is
triggered at the falling edge of the Data Available signal returned
from Main Memory. 19 -PH6 PHASE 6 (inverted) A CMC internal timing
pulse occurring from the end of Phase 5 until the Data Loaded
signal is returned from Main Memory 20 PH7 PHASE 7 A CMC internal
timing pulse occurring while the Data Loaded signal is returned
from Main Memory. 21 -PH8 PHASE 8 (inverted) A CMC internal timing
pulse occurring from the fall of the Data Loaded signal until the
End of Cycle signal returned from main memory. 22 -PH3 & PH4
PHASE 3 or PHASE 4 (inverted) 23 -PH5 & PH6 PHASE 5 or PHASE 6
(inverted) 24 Data Bus (0-25) Causes MMDBSOCR (2) Even Parity to be
returned to CCP with odd parity 25 EG LOGIC 0 MMDBSOCR {3} 0
PCIR{RR} PORT CONTROL IN REGISTER {READ REQUEST} The last memory
request presented by a port was a read request. 1 PCIR{WR} PORT
CONTROL IN REGISTER {WRITE REQUEST} The last memory request
presented by a port was a write request. 2 PCIR{PT} PORT CONTROL IN
REGISTER {PRIVILEGED TRANSFER} a. The last request was from a DCU
which was allowed to access a location outside of its initiali-
cation table and outside of the block transfer area, because the
Privileged Transfer lead from that DCU was true at the time of the
request. b. The last request was from the CCP and Program
Controlled read only memory protection was disabled. 3 PCIR{INIT}
PORT CONTROL IN REGISTER {IN INITIALIZATION TABLE} The DCU INIT
lead from the last DCU to make a memory request was true indicating
that the DCU was attempting to access its initiali- zation table. 4
START READ The START READ command to Main (11,12) Memory Bank one
from CMC (inverted) 5 START READ The START READ command to Main
(21,22) Memory Bank two from CMC (inverted) 6 START READ The START
READ command to Main (31, 32) Memory Bank three from CMC (inverted)
7 START READ The START READ command to Main (41,42) Memory Bank
four from CMC (inverted) 8-13 PENTR (1-6) PORT ENABLE TEST REGISTER
(1-6) The associated port is enabled to access CMC when the CCP is
off line. 14 ACKR{1}+ACKR{2} ACKNOWLEDGE REGISTER 1 or 2 or 3. +
ACKR{3} A Data Available signal has been returned to a port and
that port's memory request remains true. 15 ACKR{4}+ ACKR{5}
ACKNOWLEDGE REGISTER 4 or 5 + ACKR{6} or 6. 16 ACKR{7}+ ACKR{8}
ACKNOWLEDGE REGISTER 7 or 8 + ACKR{9} 9 17 MAR EPF MEMORY ADDRESS
RETURNED EVEN PARITY FLIP FLOP The address stored in the address
return buffer register has even parity. 18 AORF ADDRESS OUT OF
RANGE FLIP FLOP The address supplied with the memory request was
for a location outside of the available core. 19 PAIEPF PORT
ADDRESS IN EVEN PARITY FLIP FLOP The address supplied with a memory
request had even parity 20 PAICF PORT ADDRESS IN COMPARISON FLIP
FLOP The address supplied by a port to both CMC's while running in
synchro- nism did not compare. 21 MEM ADD RTRN MEMORY ADDRESS
RETURN COMPARE FLOP COMPARISON FLIP FLOP The address stored in the
address return buffer registers of Main Memory attached to CMC-A
and that attached to CMC-B did not compare. 22 PAI{17} PORT ADDRESS
IN BIT 17 FLIP FLOP Indicates the parity bit of the address
supplied with the last memory request. 23 RESTORE RESTORE CONTROL
signal instructing CONTROL Main Memory to change from a R/M/W to a
R/M/W cycle. 24 DATA-BUS {0-25} CAUSES MMDBSOCR{3}to be sent to
EVEN PARITY CCP with odd parity. 25 EG LOGIC 0
__________________________________________________________________________
2.1.6.4 memory Control Logic Test Register
An OFF LINE CMC may be stepped through a simulated memory cycle by
executing CPD instructions in the ON LINE CCP. In this manner the
ON LINE CCP may simulate:
1. A Memory Request via the MCLTR{MREQ} set CPD
2. memory Busy signal from Main Memory via the MCLTR{MB} set
CPD
3. data Available signal, MCLTR{DA}
4. data Loaded signal, MCLTR{DL}
5. end of Cycle signal, MCLTR{EOC}
If the proper sequence of set and reset CPD's are executed the CMC
will simulate a complete memory cycle. Note that the CMC under test
must be OFF LINE and the other CCP which executes the test must be
ON LINE.
2.1.6.5 input Test Register
A bit set `true` in the Input TEST REGISTER, INPTR{1-6} will cause
the inputs from the associated DCU to CMC to become true. This does
not include the eight DCU sense lines which are passed through
CMC.
INPTR{1-6} are set and reset in CMC by CPD instructions executed in
the CCP associated with that CMC. All bits of INPTR are reset by
CLEAR.
2.1.6.6 cross Write
A maintenance feature is incorporated into the CMC's which enables
an on line CCP to refresh an off line core main memory directly
from the on line copy of main memory. Once the CMC's are in the
Cross Write Active configuration one CCP may independently refresh
all locations in main memory by merely repeating a two instruction
loop; LOAD A, STORE A. Note that all memory protection features
remain in effect in the on-line CMC during a cross write operation.
During cross write Program Controlled Read Only Memory protection
is disabled in the off-line CMC. Thus the on line CCP will write
over 25th bit protected words in the off line memory. (ref. sect.
1.7).
Cross Write may only be employed by an on-line CCP and the memory
being refeshed must have its associated CCP off line. If both CCP's
become either on line or the configuration is reversed by the Third
Party, Cross Write Configuration is immediately lost and must be
entirely reinitiated. If both CCP's become off-line Cross Write
remains Active.
During Cross Write, the DCU's may be active when Cross Write is
initiated and during cross write. Since the DCU's can access the on
line, main memory it is necessary to also allow them access to the
off-line memory. This insures that the off-line memory is updated
by any DCU to main memory transfer which occurs during a cross
write.
The duplex CMC's are configured to Cross Write Active state by
means of master-slave storage elements. The master is loaded at the
time the on-line CCP issues the SET CROSS WRITE CPD.
The slave is not set until both CMC's become idle. Note that
setting CROSS WRITE ACTIVE requires a re-synchronization of the
CMC's. If 3 DCU's request access to the on line main memory at the
time CCP tries to set Cross Write a worst case maximum of 7.0
.mu.sec. could elapse between the SET CROSS WRITE CPD and the
achievement of Cross Write Active configuration. A sense line is
provided indicating CROSS WRITE ACTIVE.
Once Cross Write Active configuration is achieved the on line CCP
is enabled by the Cross Write Active Flop to access the off line
CMC through Port 8 (Port 8 is connected to Port 7 of the duplex CMC
unit via backplane wiring). In the off line CMC Port 7 is blocked
to insure that the off line CCP can not interfere with actions of
the on line CCP. CPD instructions from the off line CCP are allowed
access to the off line CMC during Cross Write. To insure that both
CMC's will be available for transfers during Cross Write Active the
CMC's are run in synchronism. Because they are in sync the
following comparisons are made:
i. Port Address in
ii. Port Data in
iii. Memory Address returned
iv. Synchronism Time Out
v. Bank selection Comparison
vi. Port Selection Retry Error
The memory data returned is not compared as it is not expected to
compare during Cross Write. The above mismatches are available on
sense lines for interrogation. The CMC MISMATCH signal however is
DISABLED during cross write as this signal is used to generate a
THIRD PARTY trap.
Data and control signals are returned to the CCP from the on-line
main memory (via CMC) only during CROSS WRITE. DATA LOADED is
returned to the on-line CCP by the on-line CMC only after DL is
returned to the CMC by BOTH memories. Control signals are returned
to the DCU's from both CMC's but DATA is returned to the DCU's only
from the on-line CMC.
All error detection circuitry in both CMC's with the exception of
Memory DATA (READ and WRITE) RETURNED COMPARISON ERROR remains
active during CROSS WRITE.
Two means of exit (other than system master CLEAR) from cross write
are available:
1. Execution of RESET CROSS WRITE CPD. In this case the same
sequence of events occurs as does when entering cross write. The
CROSS WRITE ACTIVE (SLAVE) latch is not reset until both CMC's are
idle. When Cross Write Active flop becomes reset the DCU's will not
have access to the off line CMC unless their associated PENTR's are
set.
2. Bring the off-line CCP back on line. This causes immediate
resetting of Cross Write Active Flop. The DCU's will now be enabled
to both CMC's by the CCP ON LINE signal if their associated POLR's
are set.
In summary the steps required to enter CROSS WRITE ACTIVE
configuration are:
1. One CCP must be on-line, one CCP must be off-line.
2. The Port On Line Register (POLR 1-6) of the off-line CMC must be
equal to the POLR of the on-line CMC.
3. Issue SET CROSS WRITE CPD to the on-line CMC by execution of the
associated CPD instruction in the on-line CCP.
4. Sense for CROSS WRITE ACTIVE sense line true.
5. When CROSS WRITE ACTIVE sense line is true begin reading the
on-line core main memory and writing both memories with the STA,
STQ, etc. instruction executed in the on-line CCP only.
To exit from Cross Write
1. System Clear in the off-line CCP. Subsequent DCU transfers will
not effect the off-line CMM.
2. Issue Reset Cross Write CPD and sense for Cross Write Active
sense line false. DCU transfers will now be lost unless the Port
Enable Test Register (PENTR 1-6) in the off-line CMC is equal to
the POLR of the on-line CMC.
3. Bring the off-line CCP back on-line. No DCU transfers will be
lost as long as the POLR in the off-line CMC has been left set.
Section 2.2 drum memory
2.2.1 introduction
drum memory is used as storage area for the programs and data that
do not require "immediate" access by the central processor. Drum
Memory information is readout of and written into main memory under
control of a Drum Control Unit (DCU) via the Computer Memory
Control (CMC) circuit. Each DCU is assigned a specific port, in the
CMC. These ports are numbered 1 through 6 and are assigned a
priority. Port 1 having a higher priority than port 2 and so on
down to port 6 with the lowest priority of DCU's. The central
Processor has port 7 assigned to it and attains the least priority.
Each DCU can control an entire drum of 18 segments or one half a
drum (9 segments). Thus a maximum of 6 drums could be handled. Each
drum segment contains 10,999 words of 27 bits each.
The writing into and reading out of drum must be accomplished when
the Drum is ready. Failure to do so will create an error. A word
can be read out of, or written into memory every 1.6 microseconds.
If more than one Drum, or a Drum and the CCP wished to access
memory, transactions in the Drum area would be lost, or the CCP
would not get a change to access memory. In order to avoid this the
drums are handled at an interlace rate of 5. This means that
successive Drum locations to be read or written into are actually
spaced every five locations. Thus when a drum reads from memory, it
will not be ready to read again until 8 microseconds later. Thus
one Drum will not hog memory. With this interlace, three Drums and
a CCP can be running simultaneously without loosing drum and yet
allowing the processor to access memory at least once for every
three separate Drum transactions. If a fourth Drum is accessed, the
CCP may get locked out for a longer length of time or conceivably
until one of the drums stops processing. As a Fifth Drum is added
the possibility of locking out the CCP becomes more prevalent. The
loss of transactions on a drum are also possible. Simultaneous use
of a sixth drum exaggerates the problem.
2.2.2 OPERATIONAL DESCRIPTION (HARDWARE)
2.2.2.1 modes of processing
there are three basic modes of processing the Drum Memory System
(DMS). Initialization, search and transfer, and termination.
2.2.2.1.1 INITIALIZATION
Initialization involves loading the various registers in the DMS
from the initialization table located in main core memory.
2.2.2.1.1.1 The even numbered locations (0-16) of the
initialization table are loaded by the Central Processor's running
program. All information necessary for a Drum Control Unit (DCU) to
fulfill an assigned task is present in these nine locations.
2.2.2.1.1.2 The odd numbered locations are used by the DCU, to
write into them, the data contained in the proceeding even numbered
locations, so that a check can be made, that the information in
those locations are correct.
2.2.2.1.1.3 Location 18 thru 24 will contain other data that will
be explained further on in the article.
2.2.2.1.1.4 Initialization is accomplished by the issuance of a CPD
instruction from the CCP to a selected DCU.
2.2.2.1.2 search and transfer
two methods of search are available. Single Level Counter Start
(SLCS) or associative search. The SLCS mode of operation is used in
transferring program and tables between core memory and drum. Large
blocks of data may be transferred, the limit being defined by the
Limit Register (LR). Blocks of 2048 words are reserved in core as
SLCS (block transfer) areas.
A search is made in the DAC for address coincidence. The address in
the Drum Address Register (DAR) of the DAC is compared with the
binary or BCD counter. When match is found, the words are
transferred on interlace until the number of words defined by the
contents of the LR are read (from core or drum). Associative
Search
The associative search module of the DCU is a read drum write core
data transfer sequence, where the data is located by searching for
data coincidence between the drum data and the specified search
register (SR). There is an associated mask register (MR) that
specifies which of the SR bits are to be involved in the
associative coincidence. There are two associative search
sequences, single and multilevel. Associative Search (MLS) can
perform one to three levels of search and read.
2.2.2.1.3 Termination
After the required number of words have been transferred, the
termination cycle is entered. This cycle dumps the contents of the
Core Address Register (CAR) of the DCU into the initialization
table of core. This information aids the program in accessing
retrieved data. Following this, the DCU interrupts the CCP with a
DCU Ready Interrupt indicating the process is complete.
2.2.2.2 HARDWARD DESCRIPTION
The following section will present the Drum, the Drum Access
Circuits (DAC) and the Drum Control Unit (DCU) from a hardware
point of view.
2.2.2.2.1 Drum Characteristics
The magnetic drum used in the EAX system is a Bryant Computer
Products Model 10512. It operates at 3600 rpm and has a hard plated
nickel-cobalt surface. The drum comes equipped with 504 data
recording heads and 6 clock track recording heads.
2.2.2.2.1.1 Storage Characteristics
The drum is divided into 18 segments. Each segment contains 27
active recording heads and one spare recording head. There are
10,999 locations around the peripheral of the drum, thus, each
segment is capable of recording 10,999, 27 bit parallel words. The
total storage per drum is then 18 .times. 10,999 or 197,982
words.
Depending upon the system application, the drum can be arranged in
one of two configurations. One configuration treats the drum as a
single storage area of 18 segments. The other divides the drum into
two independent storage areas of nine segments each. The two areas
can be accessed simultaneously without electrical interaction. Each
drum unit, whether nine or 18 segments, will have 3 sets of clock
tracks. Each set consists of two tracks; one has a single bit
recorded at drum location .phi. and the other is a continuous
closed track with a bit recorded at every drum location.
There is one master set and two auxiliary sets for each drum unit.
The auxiliary tracks provide redundant clock sources for the Drum
Memory System. One set will be active and the other will be on
standby. The master tracks provide backup for re-recording
auxiliary tracks.
The drum is equipped with Bryant AH-020 recording heads. A modified
return-to-bias recording method is used at a recording frequency of
660 KHz (350 bits per inch). The write current pulse width is 400
nsec. and the pulse amplitude is 80 ma. For reading, a playback
voltage of 60 mv is obtained across a 1K ohm read amplifier
input.
2.2.2.2.1.2 Power Distribution and Control
The distribution and control of power to the Drum Memory System
refers to the circuits and equipment necessary to run the drum
motor and apply the D-C voltages to the Drum Memory System
circuit.
2.2.2.2.1.2.1 Drum Motor Power
The drum motor operates on 117 volts, 60 Hz A-C. The motor starts
on commercial power and after a preset time delay, a DC-AC inverter
is switched in to provide motor power. If the inverter output
fails, the motor will be switched back to commercial power with no
other discontinuities in the system. The failure will cause an
alarm signal to be sent to the Maintenance Control Center (MCC) and
a lamp to come on at the A-C power control panel to the DMS.
The starting current requirements of the motor are about three
times the run current requirements, e.g., the measured start and
run currents for the Bryant drum are 15 and 5 amps respectively. A
special circuit, the Drum Motor Start Circuit, is used to provide a
high starting current and yet permit the use of a smaller, more
economical and more reliable inverter. Basically, the circuit holds
start capacitors in the motor power circuit until the motor has
been on for a few minutes, at which time it switches the capacitors
out. A short time after the capacitors have been switched out, the
power source will be switched from the commercial line to the DC-AC
inverter.
A thermal overload switch which is preadjusted by the manufacturer
for maximum allowable internal temperature of the drum, is supplied
with the drum. When a thermal overload occurs, power is removed
from the drum, an alarm signal is sent to the MCC and a lamp at the
A-C power control panel of the DMS provides a local indication of
the thermal overload condition.
2.2.2.2.1.2.2 D-C Power Sequencing
Three D-C supply voltage levels are used in the Drum Access
Circuits (DAC). These are the -5V off-bias voltage, the +5V logic
voltage, and the +24V write/read voltage. In order to protect the
information on the drum, the sequence of power application and
removal must be defined. The Power Sequencing Circuit provides this
function automatically when -50V is applied to the circuit by
depressing the D-C power sequencing switch on the D-C control panel
of the DMS. The sequence of application is -5V and +5V together and
then +24V. In removing power, the opposite sequence must be used,
i.e., +24V is removed first, then +5V and -5V. The DCU has a
separate supply which is not sequenced with the DAC supplies.
2.2.2.2.1.2.3 Power Supply Monitor
The output of each power supply in the DMS is connected to an inlet
of a voltage monitor. There is one voltage monitor per DMS frame.
Whenver the output voltage of a power supply drifts beyond a
predetermined allowable tolerance, the voltage monitor board
indicates which supply is in trouble, and an alarm signal will be
sent to the MCC indicating that the DMS subsystem has power supply
trouble.
2.2.2.2.1.3 DMS Power Panel
The power panel is mounted on the DMS frame and is equipped as
follows.
1. A-C Power
1. Lighted POWER-ON Switch
2. Lighted POWER-OFF Switch
3. Inverter Failure lamp
4. Thermal overload lamp
5. Lamp check pushbutton
2. DC Power
1. D-C power sequencing lighted switch
2. +24 volt lighted switch
3. Lamp check pushbutton
2.2.2.2.2 Drum Access Circuits (DAC)
FIGS. 19 and 19A illustrate the three major sections of the DAC.
They are the Recording Circuits, the Clock Circuits and the
Peripheral Adapter (PA). The recording circuits are those circuits
including their drivers, monitors and protect circuits which
communicate directly with the magnetic drum. The clock circuits
provide clock pulses for referencing drum locations and for timing
logical functions in the DAC and DCU. The PA contains the storage
and control circuits necessary for interfacing the DCU and the
recording circuits.
2.2.2.2.2.1 Recording Circuits
The functional blocks of the recording circuits are shown in FIG.
19A. These include the Write/Read Circuits; the Head Select
Circuit; the Write/Read Control Circuit; the Head Select Monitor
Circuit; and the Memory Protect Circuit.
2.2.2.2.2.1.1 Write/Read and Select Circuits
Write/Read Circuits and Head Select Circuits FIG. 20 illustrates
the organization of recording heads and their write circuits -- the
Head Select Circuit and the Write/Read Amplifiers. The Head Select
Circuit selects the heads in the horizontal direction defined as a
segment. Each segment contains 27 heads (number of bits per word).
Corresponding heads (same bit number) are connected together as
shown and are driven by one write amplifier. For a write operation,
one segment is selected and all write amplifiers are energized.
Data will be recorded only at the drum location related to the
selected segment. Each write amplifier has a corresponding read
amplifier to sense the information recorded on a particular bit and
segment. The input to the read amp is the playback voltage
developed across the recording head.
1. Head Select
The Head Select Circuit receives its inputs from a circuit in the
PA that decodes the segment portion of the drum address. Only one
segment decode input will be true at a time. The Head Select
Circuit will place +24V on the center tap of all heads of the
selected segment; all other center taps will be grounded. Write
current for the 27 heads, approximately 2.5 amperes, is applied to
the heads in this manner.
2. Write Amplifiers
The write amplifiers switch current directly to the heads
previously selected by the Head Select Circuit. Control comes from
the DAC Write/Read Control Circuit which receives write commands
from a PA control circuit. Each amplifier has two outputs; they are
connected to opposite endtaps of the same head via shielded twisted
pair leads.
3. Read Amplifiers
The read amps read the playback voltage across the recording heads
and output a logic 1 for a recorded logic 1 and a logic 0 for a
recorded logic 0. The physical connection between the read amp
inputs and the recording heads is via the same shielded twisted
pair that connects the write amp to the head. The shield is
grounded at both ends. The read amps have a differential input
stage. This, along with the twisted pair, provides a high degree of
balance. The differential input has a relatively high common mode
rejection which is necessary because of the noisy environment that
may exist around the cable between head and read amp input. The
output of the read amplifier is a 800 nsec pulse from a standard
NAND gate.
2.2.2.2.2.1.2 Write/Read Control Circuit
The Write/Read Control Circuit develops the pulses and levels
necessary to control and drive the 27 Write/Read Circuits. Since
the timing of the write pulses to the amplifiers is critical, the
circuit contains precision timing and checking circuits. To write
informatiion on the drum, an enable signal (WRITE LEVEL) and write
pulses (WRITE PULSE) are sent from the PA to the Write/Read Control
Circuit. Timing is not critical at the WRITE PULSE input level
since the critical delay and shaper circuits are on the Write/Read
Control Circuit itself. To read information from the drum, the PA
sends an enable signal. Data to be recorded on the drum is sent
from the DCU to the Drum Buffer Register in the PA and then to the
write amplifiers. Data read from the drum is sent from the read
amplifiers to the Drum Buffer Register and to the DCU. Two error
detectors, the Access Circuit Err and Write Control Err, check the
integrity of control signals to the write/read circuits.
2.2.2.2.2.1.3 Head Select Monitor Circuit
The Head Select Monitor Circuit detects a selection of none or more
than one segment. There are two one-out-of-18 circuits on each
monitor card. One monitors the decoded segment select information
at the input to the Head Select Circuit; the other monitors the
output of the Head Select Circuit. The error signals sent to the PA
are Head Select Input Fault and Head Select Output Fault
respectively. Either one will cause a DCU interrupt.
2.2.2.2.2.1.4 Memory Protect Circuit
The DAC contains a Memory Protect Circuit which acts to protect
drum recording information in the event of a power supply or drum
speed failure. This circuit also acts to protect drum and reset the
DMS when power is turned on or off. (See DMS-PDR document). A power
supply failure is indicated by a lamp on the power supply monitor
panel as well as bits 22 and 19, word 20 and bit 19, word 22 (refer
to sections 4.1 and 4.2 on error status indicator words) of ITE if
the Error Termination Sequence is at all possible. A drum speed
error will set bits 19, 22 and 13 of word 20 and bit 19, word 22 of
ITE.
The Memory Protect Circuit is independent of the +5 logic power
supply. It utilizes an on-the-card DC-DC converter powered by
redundant +24V power supplies. A failure on this card causes a DCU
error interrupt indicated by bits 19 and 23 word 20, and bit 19
word 22 of the ITE.
Problems within the drum may cause the thermal overload contacts to
open and release A-C power to the drum motor. This condition will
cause the drum speed detection circuits to set and trigger an error
termination sequence setting the same bits as mentioned for a Drum
speed failure.
2.2.2.2.2.2 Clock Circuits
The Clock Circuits will provide the Drum Reset Pulses (DRP) and the
Drum Index Pulses (DIP) for referencing the angular index of the
drum. A clock track, called Master Reset Pulse (MRP), will be
recorded with one bit. This bit develops the DRP which marks the
start location on the drum perimeter.
A second clock track, called Drum Index Pulse, will be recorded
with 10,999 bits. This will be a continuous closed track and each
bit will reference a word location on drum.
For reliability reasons, it was decided there would be three sets
of clock tracks, one set called master (MRP and DIP) and two sets
called auxiliary tracks (1 and 2). The master tracks will provide
backup for re-recording auxiliary tracks. The two sets of auxiliary
tracks provide backup for each other. If an auxiliary track which
is on-line failed, the Clock Circuit would automatically switch the
respective standby track on line and indicate a clock track error.
The responsibility of the Clock Circuits is to record clock tracks,
transfer tracks, and indicate clock track errors. These functions
are shown on the DAC Block Diagram; FIG. 19 and 19A.
2.2.2.2.2.2.1 recording Clock Tracks
The Clock Track Control (CTC) is a panel which contains all the
controls for writing clock tracks. Each clock track has its own
write/read amplifier. The mode of recording tracks is
return-to-bias (RB).
The manual procedure for writing a clock track is as follows:
1. Select the track to recorded
2. Enable the write amplifier
3. Depress the erase button. This will bias the associated clock
track.
4. Depress the write button. This will start the Clock Track Writer
(CTW) recording sequence.
When recording Master MRP, the CTW will generate one pulse which
will record one bit on the associated MRP track. When recording
Master DIP, the CTW in conjunction with the Binary Counter (BC)
will generate a train of 10,999 pulses which will record the
associated DIP track. The frequency of these pulses will have to be
adjusted to obtain a closed track. It may take several attempts to
record a perfect DIP track. The CTW will have the capability of
recording 10,500 to 11,500 bit tracks. The BC is a standard 15 bit
counter programmable from 0 to 16,383.
When recording the auxiliary tracks, the CTW will record the
associated master track data (read amp. output) on to the selected
auxiliary clock track. There will be a delay adjustment to minimize
the skew between auxiliary DIP tracks. After all clock tracks have
been recorded the Clock Track Control Panel may be removed.
However, it is necessary to strap the Write Inhibit lead of the
Write/Read amplifier to ground before removing the CTC. This
strapping is accomplised on the CTW card where jacks are
provided.
2.2.2.2.2.2.2 Transfer and Error Check
The Transfer Circuit will switch on-line the alternate axuiliary
track either automatically (due to a clock pulse error), or
manually from the CTC, or on command from the PA. The MRP on-line
develops the Drum Reset Pulse (DRP) which will be in coincidence
with one DIP. DRP and DIP are the clock timing pulses for the Drum
Memory System.
There are five error checks for Clock Circuit Faults. Error
detectors will set latches which will retain the error indication
for diagnostics.
1. Master Track Error Detector -- this detects coincidence between
MRP and DIP bit 10,998.
2. DIP Track Skew Detector -- This detects the skew between the
auxiliary DIP tracks.
3. Drum Speed Detector -- This detects the speed of the drum by
timing the DIP pulses.
4. DRP Error Detector -- This detects the absence of DRP
pulses.
5. DIP Error Detector -- This detects the absence of DIP
pulses.
2.2.2.2.2.3 DAC Peripheral Adapter (PA)
The PA contains the circuitry necessary for locating drum
addresses; drum interlacing; temporary storage of drum data; timing
of drum write/read control signals; and detection of hardware and
software errors.
2.2.2.2.2.3.1 Locating Drum Addresses
The PA locates drum addresses by finding coincidence between the
contents of an address register and the count of a counter which is
advanced one count for every Drum Index Pulse (DIP). The following
information is required to find a drum address: (1) the segment
number, (2) whether the drum location is specified in binary or
BCD, and (3) the address of the word relative to DRP (location 0).
This information is loaded into the Drum Address Register (DAR) at
the beginning of a transfer. The segment number (bits 16-20) is
decoded and sent to the Head Select Circuit, which in turn,
energizes the appropriate segment. DAR bits 0-15 contain the drum
address (relative to DRP). DAR bit 22 specifies which counter will
be compared with the address bits. Two counters, one binary and one
modified BCD, continuously count DIP pulses. Each count up to the
equivalent of decimal 10,998 and then are reset to zero by DRP.
Thus, each count in the counters is related to a specific drum
location or drum location references in this manner is called a
drum index value.
The search for coincidence starts upon command from the DCU (START
COUNTER SEARCH).
2.2.2.2.2.3.2 drum Interlacing
A maximum of 6 DCU's will be interfaced with two CMC's working in
sync. Words can be read from each drum at a 1.6 microsec. rate and
the core memory cycle time is 1 to 2 microsec. Thus, since several
DCU's might request access to core simultaneously, it is not
possible to transfer successive words from drum to core. A drum
interlace, whereby one word every five locations is read (written)
from drum and written (read) into core, is used. The interlace rate
of five was selected so six DCU's and the CCP would access core
with the probability of a request going unanswered minimized. The
interlace rate is not variable, but could be increased to 6, 7 or 8
if required.
Interlacing is controlled by a 3 stage counter on the PAD sequence
Control Circuit. The counter starts when coincidence is found in
either the PA (counter coin) or in the DCU (assoc. coin) and
outputs one pulse (MI-DCP2) for every 5 drum locations. MI-DCP2
will effectively skip ahead one location for every complete drum
revolution. For example if drum locations 0, 5, 15 etc. were read
on the first drum revolution, locations 1, 6, 16, etc. would be
read on the second revolution.
2.2.2.2.2.3.3 Temporary Data Storage
One register, the Drum Buffer Register (DBR) is used as temporary
storage for both writing and reading operations. The register
contains 26 bits including a parity bit and a memory protect bit.
Another bit, The Block Mark Bit, is treated as the 27th bit of the
DBR. This bit is located on the PAD Data Control circuit. Parity is
checked across all bits except Block Mark for both read and write
operations.
The use of DRB in transferring data is described in detail in
section 2.2.2.2.2.3.5.
2.2.2.2.2.3.4 Timing and Write/Read Control
The PAD Sequence Control Circuit and the PAD Data Control Circuit
are the PA circuits that provide timing and write/read control.
The DIP clock track is the source for all DAC write/read timing
signals. For some applications, DIP is used directly; for others
timing pulses are generated by pulse circuits on the PAD Data
Control Circuit. These pulses are sent to the other DAC circuits
for write/read control and to the DCU (refer to section 2.3.1.4 and
FIG. 24, for additional DMS timing details). Write/read control
signals are developed on the PAD Sequence Control Circuits. For
both writing and reading, an enable signal and pulse are developed.
These are WRITE LEVEL and WRITE PULSE for writing, and PA READ
ENABLE and STROBE DBR for reading. The write/read control interface
with the DCU is described in detail in section 2.2.2.2.2.3.5.
2.2.2.2.2.3.5. Operational Explanation of the PA
The operational explanation of the PA will be divided into read and
write categories.
2.2.2.2.2.3.5.1 Read Transfer (drum to core).
Refer to the flow chart of FIG. 21. A data transfer is started when
the Drum Address Register (DAR) is loaded during the initialization
cycle of the DCU. Bits 16 thru 20 of the DAR contains the segment
address of the first word to the transfer. If the specified segment
is valid (within range of implemented segments), the number of the
specified segment is decoded and sent to the Head Select Circuits.
The Head Select Circuit then notifies the PA that one and only one
segment has been selected and the PA sends the ONE SEGMENT SELECTED
(ISS) signal to the DCU. When the DCU acknowledges the ISS signal,
it initiates an enable signal (in this case READ ENABLE) and either
a CONTINUOUS READ or a START COUNTER SEARCH signal.
Assume that the DCU sent a CONTINUOUS READ signal. If there have
been no DAC errors up to this point, the PAD sequence Control
Circuit sends the PA READ ENABLE signal to the recording circuits.
Data is transferred from the Drum to the Drum Buffer Register under
control of the PA. After each word is loaded into the DBR, its
parity is checked. If parity is correct, the DCU, by sending a
DIPLAY DBR signal transfers the data from the DBR to the PA Output
Bus and thus to the DCU. In this manner, the DMS presents a
continuous stream of data, and the contents of a register in the
Associative Search Module of the DCU. When coincidence is found,
the contents of the specified counter is stored in the address bits
of the DAR and the PAD Sequence Control Circuit switches the PA to
interlaced control. The count stored in the DAR will be the address
of the coincidence word +8.
If, instead of a CONTINUOUS READ signal the DCU had sent a START
COUNTER SEARCH signal (refer to the CR decision box on the flow
chart), the address search would have been performed in the Address
Coincidence circuit of the PA. Bit 22 of the DAR specifies which
counter (binary or BCD) will be compared with the address bits of
the DAR. When coincidence is found, the PAD Sequence Control
Circuit sends the PA READ ENABLE signal to the recording circuits
and switches the PA to interlaced control. With the PA in the
interlaced control mode, every fifth drum word (for interlace of 5)
will be loaded into the DBR, checked for correct parity and sent to
the DCU. Control of the data transfer will handled in the same
manner as for a continuous read operation.
The transfer continues until the READ ENABLE signal from the DCU is
removed. During the transfer, the count of the specified counter is
transferred to the address bits of the DAR once for every 5 DIP
pulses. At the end of transfer, the DAR will contain the address of
the last word transferred +8.
2.2.2.2.2.3.5.1 Write Transfer (Core to Drum)
The DCU Associative Search Mode is not used for drum write
operations. Therefore, PA operation for write transfers is less
complex than that of read transfers. Refer to the flow chart of
FIG. 22. The sequence of operation through initial loading of the
DAR, segment decode, segment select and ONE SEGMENT SELECTED signal
is identical to that of the read operation. If no errors have been
detected, the DCU sends the START COUNTER SEARCH signal. The
specified counter (binary or BCD) will be compared with the address
bits of the DAR to locate the angular index value for the beginning
of the transfer. When the angular index value is found the Z
COUNTER signal is sent to the DCU and to the PAD Sequence Control
Circuit. The DCU controls transfer of data to the DBR and the PAD
Sequence Control Circuit sends the WRITE LEVEL and WRITE PULSE to
the recording circuits. WRITE PULSES cause data to be written on
the drum at the specified interlace rate. The transfer will
continue until the WRITE ENABLE (from DCU) signal is removed,
terminating the transfer. The count of the specified counter is
stored in the address bits of the DAR. The stored count will be the
address of the last word written +8.
2.2.2.2.2.3.6 Error Detection
Whenever an error occurs in any circuit of the DAC, the following
actions are taken in the PA.
1. if a data transfer is in progress, it will be halted; the
contents of the DBR and the 10 higher order bits of the DAR will be
held intact for diagnostic purposes.
2. The contents of the binary or BCD counter, at the time of the
trouble indication, is stored in the address field of the DAR. For
most PA errors, this stored count is meaningless. However, for
parity errors, it can be used to identify the bad word. Since
binary numbers should be simpler to handle in diagnostic routines,
parity errors will cause the binary count to be stored.
3. The error indication will be stored in a flip-flop or latch type
of storage element, the output of which can be displayed on the PA
Output Bus for diagnostics.
4. The DCU will be notified of the detected error. All DAC error
indications will be OR'ed together and a single error signal, DAC
ERROR, will be sent to the DCU.
Diagnostic routines, which simulate error conditions in the DAC,
will be written so that DAC error detection circuitry is exercised
periodically.
2.2.2.2.3 Drum Control Unit (DCU)
The DCU provides the control and data path for the transfer of
information between the CMC and DAC. The DCU contains buses (I/O
and internal), registers, error detectors, and control circuitry as
depicted in the DCU Block Diagram, FIG. 23.
2.2.2.2.3.1 block Diagram Description
FIG. 23 illustrates the organization of the DCU, and aids in
understanding the following sections.
2.2.2.2.3.1.1 Bus Structure
1. Data Bus A (Input)
Data to the DCU (25 bits and 1 parity) from the CMC or DAC is
received via bus A. Parity at bus A is checked by the Bus A parity
circuit.
2. Data Bus C (Output)
Data from the DCU (25 bits and 1 parity) to the CMC or DAC is sent
via bus C. Parity is checked (Bus C parity) and corrected if
necessary before data is sent to the CMC or DAC, i.e. bad parity
will never be written in core or on drum.
3. Address Bus D
Addressing core (15 bits and 1 parity) is accomplished directly
over bus D from the DCU. Correct parity is generated at bus D (Bus
D parity circuit).
2.2.2.2.3.1.2 Registers
Each register in the DMS except the IAR contains parity and memory
protect information in bits 24 and 25 respectively. The following
is a description of the registers in the DCU. More detailed
description of each DMS register is found in Appendix I of this
section.
1. Instruction Register/Limit Register (IR/LR).
The IR portion (10 bits) will contain the directive to be executed
by the DMS. The IR portion (14 bits) will contain the number of
words to be transferred in the case of single level counter search
or the number of words to be skipped (indexed) in the case of
single level associative search.
2. Initialization Address Register (IAR)
The IAR is a 15 bit address register used to address core during
certain DCU sequences. The low order 5 bits are preset and
incremented during these sequences. The high order 10 bits are
strapped internally whose value is determined by bound checks to be
made in core.
3. Core Address Register (CAR)
This 26 bit register is used to address core during any of the data
transfer modes. Bits 15 thru 20 are not programmable.
4. Core Buffer Register (CBR)
The 26 bit CBR is used as a temporary store of data being
transferred.
5. Search Registers (SR1-SR3)
The Search Registers (26 bits) contain information that specifies
the drum address or data coincidence to be encountered before
entering the respective levels of associative search.
6. Mask Registers (MR1-MR3)
The Mask Registers (26 bits) contain information that specify which
bits of their respective SR are to be involved.
2.2.2.2.3.1.3 Associative Search Match Circuit
This circuit decodes coincidence between bus A information from
drum and the search register screened by the mask register.
2.2.2.2.3.1.4 Common Control
The Common Control contains the DMS timing, coincidence circuit,
pulse distributor, and the directive decode circuit.
The DMS timing is illustrated in FIG. 24. DCP2 and DCP1 are
generated in the PA of the DAC from the drum clock tracks (DIP).
FRI-DCP2 (also generated in the PA) is a free running DCP2 whose
period is 1 drum interlace time of 7.5 microsec. DCU TIMING CP
(TCP) is generated from DCP2 by a pulse shaper on the Bus D
Multiplex circuit of the DCU. The coincidence circuit recognizes
the specified coincidence (counter or information) and enables the
pulse distributor at the approximate time. The pulse distributor
(PD) is a three stage counter which is synchronized with the
interlace counter of the DAC and clocked by DCP2 pulses. The PD is
strapped at the connector for an interlace rate of five. The
strapping can be changed if a higher interlace rate of six, seven
or eight is required. The DCU timing is dependent on the control
pulses of the pulse distributor.
There are five control pulses, P1 through P5. The P1 pulses of the
PD are synchronized with each MI-DCP2 of the DAC. The starting of
the PD counter is different for the various DCU sequences.
During the write sequence, the PD counter will be set to P1 and
started by Z counter (counter coincidence). For any read-drum
write-core counter search sequence, the PD counter will be set to
P1 and started by MI-DCP2.
When searching for associative coincidence, the PD will be set to
P3 and started on match strobed by DCP2.
Regardless of what the PD counter is set to or which signal started
the PD, the control pulses will not be enabled until the counter
has been started and the count reaches P3 time.
The directive decode circuit will decode the instruction register
bits 20-23 and determine the operation to be performed that is,
read sequence (SLCS), write sequence (SLCS), single or multi level
associative search DAC maintenance, or invalid operation.
2.2.2.2.3.1.5 Block Transfer
The Block Transfer module controls SLCS read drum, SLCS write drum,
initialization, termination, error termination, spills, and the
error detection associated with these functions. All of the CMC
interface control, as well as the sense line circuitry is under the
control of the SLCS module.
2.2.2.2.3.1.6 Associative Search Control
This module controls the multi level and the single level
associative search sequences and provides enabling control to the
SLCS module which interfaces with the CMC and DAC.
2.2.2.2.3.2 initialization
FIG. 25 is a detailed picture of the Block Transfer Module of the
DCU block diagram. The Register/bus structure and some control are
retained on FIG. 25 (from FIG. 23) for clarity.
Before data transfers between core and drum (or DAC maintenance)
can be made, the DCU must be initialized.
Initialization is the process initiated by a CPD, by which
information is read from fixed locations in core (Initialization
Table) into the registers of the DMS. This information contains
directives and associated data necessary for execution of the DMS
request. A copy of the Initialization Table is shown in the left
column in DMS Appendix III. These locations are addressed by the
IAR via bus D and the information is controlled by the
initialization control and register control multiplex (see FIG.
25).
2.2.2.2.3.3 single Level Counter Start (SLCS)
The following operation description will refer to the SLCS flow
chart, FIG. 25 and FIG. 23.
2.2.2.2.3.3.1 drum Write (SLCS-write)
For the SLCS drum write IR directive (see DMS Appendix II for IR
format); the IR/LR, DAR, and CAR are loaded in the DMS during
initialization. When complete, the DCU mode control circuit (FIG.
25) sets the write sequence circuits. The Write Sequence bit of the
Error/Status register (bit 2, word 22) is set. For detailed
sequential circuit conditions see the flow chart on FIG. 26. The
notes along side of the functions on the flow chart indicate the
timing of the hardware functions.
A core read request is issued (FIG. 25). The CMC responds with a
"Data Available" pulse indicating that the word at the core
location defined by the CAR is available on bus A. The word is then
loaded into the CBR. The CAR is advanced (1) to address the next
core location, and the LR is stepped (decremented because LR
contains 2's complement) to indicate a word was transferred to the
DCU. The command to "Start Counter Search" is given to the DMS. The
address search continues on interlace 1 until match between the
address field of the DAR and the particular angular index counter
in the PA is found. If there are no errors the DBR is loaded from
the CBR and the word is written on drum where address match was
found. The above functions of "Core Read Request," "Data
Available," load CBR, load DBR, step CAR and LR, and check for
errors are continued on interlace 5 until the LR contains all
zeros. At this point the Write Sequence status bit is reset and the
Termination Sequence is triggered. The Termination Sequence
circuits control the necessary functions for storing the present
contents of the CAR (core address of last word read) into core
memory, and setting the DCU Ready interrupt (see FIG. 25).
A CPD spill after this directive reveals
1. the original contents of the IR/LR
2. final Drum address
3. final core address
4. last word transferred in CBR
5. last word transferred in DBR
2.2.2.2.3.3.2 drum Write-Block Mark
If the DCU was placed in the Block Mark Mode (set bit 18 in IR),
the last word written on drum will set its block mark bit, i.e. bit
26 of the last word will record a 1.
2.2.2.2.3.3.3 Drum Read (SLCS-read)
For the read drum (write core) drective (see Appendix II for IR
format; the same DMS registers are loaded as for Drum Write. In
other words initialization is similar, but when complete, the DCU
mode control circuit sets the read sequence circuits. The Read
Sequence bit of the Error/Status register (bit 3, word 22) is set.
For detailed sequential circuit functions see Read Sequence on flow
chart FIG. 26. The notes along the flow chart functions indicate
which DCU timing pulses cause the action. After the read sequence
circuits set up the buses required to receive data from drum, the
command to the PA to "start counter search" between the address
field of the DAR and the particular angular index counter in the PA
is found.
The data at the coincidence address is sent to the DCU via bus A
and held in the CBR and placed on the output bus (bus C). A "write
request" is issued to core. After the word is stored in core at the
location defined by the CAR, the CMC responds with a "Data Loaded"
pulse. The CAR is advanced (1) to address the next core location,
and the IR is stepped (decremented) to indicate a word was
transferred to the CMC.
The DAC continually places words from drum into the DBR at an
interlace 5 rate. The DCU loads the DBR word into the CBR, issues a
"write request" to core and steps the CAR and LR after the "Data
Loaded" response from core. Parity is checked at the DBR, on bus A
as the data enters the DCU, and at bus C just before the "write
request" is issued to the CMC. This process continues until the LR
contains all zeroes in which case a block mark bit is checked (if
block mark mode), the Read Sequence status bit is reset and the
Termination Sequence begins. The DCU Ready interrupt (see FIG. 25)
indicates the completion of the Termination Sequence.
2.2.2.2.3.3.4 Drum Read -- Block Mark
If the DCU was placed in the Block Mark mode (IR Bit 26-1). The
last word to be transferred is defined by the state of the LR = all
zeroes.
If these two conditions
1. LR = 0 2. DBR bit 26 = 1
do not occur simultaneously an error interrupt occurs. A CPD spill
following a read sequence reveals
1. the original contents of the IR/LR
2. final drum address
3. final core address
4. last word transferred in CBR
2.2.2.2.3.4 associative Search
The associative search function of the DCU is basically a read drum
write core operation where the data to be transferred is located by
associatively searching the drum. There are two associative search
sequences multilevel and single level associative search.
The multilevel associative search (MLS) provides for three levels
of search and transfer, however, a fourth level of search can be
obtained by having a counter search prior to the first associative
search. The normal three levels of search can be either a search
for counter or associative coincidence. Indirect addressing on drum
is possible because of the overwrite feature of the MLS. This
feature is the capability of drum data to specify the location of
coincidence for the next level of search. From the time the MLS has
entered the first level until termination, the DCU is controlled by
the drum data.
The single level associative search (SLAS) provides for only one
level of associative searching which may or may not be preceded by
a counter search. The number of words to be skipped after
associative coincidence is specified by the limit register and the
number of words to be transferred is specified by the instruction
register. Therefore, the number of words transferred is under the
control of the initialization table (refer to DMS Appendix III) in
core.
When the first associative coincidence is preceded by a counter
search, the Block Mark (BM) bit will be checked. If the BM bit
comes true while searching for this first associative coincidence,
the level end flag will be set and cause an interrupt.
2.2.2.2.3.4.1 MLS Description
The operation or control of the MLS sequence is for the most part
data driven. During the Initialization sequence all the control
registers are loaded with data pertinent to MLS transfer. That is,
the Instruction Register (IR) has the MLS directive and specifies
the type of coincidence (counter of associative) to be encountered
for each level of search. If all levels of search are not to be
used, the unused levels must be specified counter coincidence. The
Drum Address Register (DAR) contains the drum address if a counter
search and the specified drum segment to be searched. The Core
Address Register (CAR) contains the location in core where the
first data word is to be written. All the Search Registers (SR) are
loaded with information that specifies the drum address or data
coincidence to be encountered before entering their respective
levels of MLS. The Mask Register (MR) contains information that
specifies which bits of their respective SR will be involved.
Upon completing the Initialization sequence, the DCU will enter the
MLS sequence as specified by the directive in the Instruction
Register. Other than the Search Register specifying the drum
address or information coincidence at which the DCU should enter
the next level of associative search, the control bits (21, 33 and
23) of the data read from drum will direct the DCU through the MLS
sequence word by word until directed to enter the termination
sequence.
There are nine possible control actions the DCU can follow as each
word is read from drum during the MLS sequence. The action taken is
determined by the control bits of the previous (CBR) and present
(DBR) word read from drum, the present level of associative search,
the present state of the DCU (read or search), and if the present
word is a coincidence word (address or information coincidence).
Refer to the MLS decision table for more detail information of the
MLS control actions, FIG. 33 and MLS flow diagram FIG. 29.
2.2.2.2.3.4.1.1 mls operation
After completing the Initialization Sequence the MLS sequence is
set. This will display the Drum Buffer Register (DBR) on the DAC
data bus, enable the drum data on bus A, display the Core Buffer
Register (CBR) on bus C, and display the appropriate SR and MR on
the match bus and bus B, (refer to DCU Block Transfer and
Associative Search Control diagrams FIGS. 25 and 28). The Read
Enable latch and EN CAR CBR CTL latch will be set for the MLS
sequence. The Read Enable lead will condition the DAC to respond to
DCU control. The EN CAR CBR CTL lead will ready the Block Transfer
Read Sequence circuitry necessary to transfer the DBR data via CBR
into core.
If the MLS Transfer is a counter start, the Start Counter Search
will be set and the DAC will look for coincidence between the
specified counter and the DAR. When coincidence is found the DAC
will go active; this will send Z counter to the DCU, start the DAC
interlace counter, and load the word associated with counter
coincidence in the DBR. There will be an MI-DCP2 Pulse at the
interlace rate which will start the Pulse Distributor in sync with
the interlace counter of the DAC. The DCU will start searching the
data at the interlace rate and associative match will be tested
every P3 of the Pulse Distributor.
If the MLS Transfer is not a counter start, the Start Search
circuit will send a Continuous Read to the DAC. The DAC will start
reading drum and loading the DBR every DCP1, and every DCP2
associative match will be tested. When associative coincidence is
found, the Pulse Distributor will be started at P3 time and Z
associative will synchronously start the DAC interlace counter. The
DMS will now transfer data at the normal interlace rate.
At this point, the operation of the MLS sequence is controlled by
the MLS decision table FIG. 33. The MLS Sequence Decode circuit
will decode the control action to be taken for each word
transferred. This action will be decoded and loaded in the action
register every P3 time. The Action Encode Multiplex initiates the
appropriate control at the proper P time, refer to the control
action flow charts of FIGS. 31 and 32.
The following is a description of the nine actions which control
the MLS transfer until entering the termination sequence.
These actions are decoded by the MLS Sequence Decode circuit and
executed by the Action Encode Multiplex. The following is a list of
the associative search control actions:
1. Enter Next Level (ENL)
2. read Present Word (RPW)
3. drum Modify Search Word (DMSW)
4. drum Modify Mask Word (DMMW)
5. reset Read Latch (RRL)
6. previous Word Interrupt (PVWI)
7. present Word Interrupt (PSWI)
8. level End Interrupt (LEI)
9. invalid Action Interrupt (IAI)
ENTER NEXT LEVEL, every new level is started by an ENL action at P3
time. This Decoded action will set the ENL latch refer to the ENL
flow chart (FIG. 31). At P4 time the Read latch will be set. This
will send a Core Write Request, via DCU Block Transfer Control, to
write each succeeding word from drum into core. The Level Register
will be advanced to n + 1 (P4 trailing edge). The DAR, which will
contain the address +8 of the word now in the DBR, will be
displayed on bus A. Then at P5 time the DAR address will be loaded
into SR (n), and at P1 time the DBR will be redisplayed on bus A.
P2 will load the DBR into the CBR and set the Write Request latch.
The modified search or mask register flag bits (23 and 22) will be
enabled, so at P4 + 1 time the flag bits will be loaded in the MR
along with the Core address of the coincidence word being written
into Core. Bit 23 set indicates this level search register had been
overwritten by the drum prior to ENL however, the drum can only
overwrite level two and three search and mask registers. Bit 22 set
indicates this level mask register has been overwritten prior to
ENL control action. At P3 + 1 time a new action latch will be set
and at P4 + 1 the MR will be loaded, as previously described and at
P5 + 1 the ENL will be reset.
READ PRESENT WORD, there is no decode for the RPW action. If the
read latch was set by the previous word control action and there is
no present action decoded, the next P2 will set a write request and
the present word will be written into core. DRUM MODIFY SEARCH
WORD. This action is the search word overwrite feature of the DCU.
At P3 time the decoded action sets the DMSW action latch. At P4
time the next level search register is reset and the Read Latch is
set. At P5 the modifying drum word is loaded into the next level SR
with the proper control bit corrections. That is, if the next level
search is a counter search the control bits of the drum word will
not be altered (000), if (n) is level 1 and searching associatively
the control bits will be changed to 100, and if (n) is level 2 and
searching associatively the control bits will be altered to 110. At
this time the DMSW flag bit will be set to be used for the next ENL
action. P2 time a core write request will be set to write the
modifying drum word into core. The control bits of this word will
not be altered (000).
DRUM MODIFY MASK WORD. This action is similar to the DMSW with the
exception of modifying the Mask Register and the control bits load
into the MR will always be altered to 110.
RESET READ LATCH. This action will stop the transfer of data from
drum to core and continue searching if the next level is
associative coincidence. If the next level is to be entered via
counter coincidence, this action must load the new drum address
into the DAR and start the counter search on interlace one.
At P3 the RRL action is set. At P4 the Read latch is reset to stop
transferring to core; also the Read Control Bits latch is reset,
this is to avoid decoding any control action until detecting a
coincidence word. If entering the next level is via associative
coincidence, detecting Z assoc (coincidence) will set the ENL
latch. This will complete the RRL action. If a counter search, P4
will reset Read Enable thus deactivating the DAC. After receiving
Data Loaded from core and stepping CAR, Parity C AS will be set.
This will permit checking bus C parity while loading the new DAR
address during P2. At P5+1 time, the pulse distributor will be
reset for interlace one searching. When the DAC has selected the
new segment a Start Counter Search will be sent and the next level
will be entered on Z counter.
PREVIOUS WORD INTERRUPT. This action will reset the Read latch,
Read Enable, EN CAR CBR CTL, and Read Control Bits latch at P4
time. Resetting Read Enable will capture in the DAR the drum
address +13 of the last word written into core. Resetting EN CAR
CBR CTL will capture in the CBR the last word written in core.
Then, P2 will activate the SET END SEQ AS lead and the DCU will
enter the normal termination sequence.
PRESENT WORD INTERRUPT. This action will reset Read Enable on P4
which will capture in the DAR the drum address +8 of the last word
to be written. This will also capture in the DBR the last word to
be written in core. At P2 time the Read Control Bits latch will be
reset and a write request will be issued to write this last word in
core. During P4+1 the Read latch will be reset to halt issuing any
further write requests also EN CAR CBR CTL will be reset which will
capture in the CAR the core address of the last word in core and
hold in the CBR the last word written in core. At P2+1 the DCU will
enter the normal termination sequence.
LEVEL END INTERRUPT. This action is identical to PSWI control
action mentioned above with the exceptions, at P4 time the Read
latch is set and a level end flag is set in the Error/Status Word
18 bit 14. The Read Latch is set to write the present word (the DBR
word) into core.
INVALID ACTION INTERRUPT. This control action will not reset the
Read latch, but will inhibit initiating any further write request.
The Read latch is an indicator bit in the Error/Status word 18 bit
20 which will indicate the status of transfer when the interrupt
occurred. The DAR will capture the drum address +8 of the word held
in the DBR. If interrupt occurred while writing core, the CBR will
contain the word being written and the CAR will contain the address
of the same word. If the DCU was searching at the time of
interrupt, the CBR would not contain intuitively meaningful
information, however the CAR will contain the location at which the
next word would have been put into core. At P2 time the DCU will
enter the Error Termination sequence.
2.2.2.2.3.4.2 SLAS Description.
The SLAS is a single level transfer in which the data is located
via information coincidence and the size of transfer is specified
by the initialization table in core.
During the Initialization Sequence, the control registers are
loaded with information necessary to perform a Single Level
Associative Search (SLAS). The Instruction Register (IR) will
contain the SLAS directive with or without a counter start (CS) and
the WCT field which will specify the number of words to be
transferred. The Limit Register will contain the complement of the
number of words to be skipped (indexed) before transferring data.
The first level Search and Mask registers will be loaded with the
search information. The Core Address Register (CAR) will specify
the address in core to start loading data. The Drum Address
Register (DAR) will specify the segment to search and, if a counter
start, specify the drum address to start associative searching,
refer the SLAS flow diagram FIG. 30.
2.2.2.2.3.4.2.1 slas operation
After the Initialization Sequence is completed, the SLAS sequence
will be set. This will display the DBR on the DAC data bus, enable
the drum data on bus A, display the CBR on bus C, and display the
level one SR and MR on the match bus B, (refer to DCU Block
Transfer and Associative Search Control diagrams FIGS. 25 and 28).
This will also set the Read Enable and EN CAR CBR CTL latches.
If the SLAS is not a counter start (CS) sequence, the DCU will
associatively search the data from drum, on interlace one. If a CS
sequence, the DAC will search for the drum address specified by the
DAR. Upon counter coincidence, the DCU will begin searching
associatively on interlace five.
Upon obtaining information coincidence, the ENL control action
(refer to FIG. 31) will be set. This will cause the coincidence
word to be written into core and will step (increment) the limit
register. Each word read from drum will now increment the LR. When
the LR equals zero, the Read Latch will be set and all successive
words will be written into core. This will continue until the LR
equals the WCT field of the instruction register. LR, WCT
coincidence will reset Read Enable, Read Latch, and the EN CAR CBR
CTL latch, thus capturing the last word in core in the DBR and CBR.
The DAR will capture the drum address +8 and the CAR will capture
the core address of the last word in core. The SLAS sequence will
then relinquish control to the normal termination sequence.
There is a Block Mark (BM) check for the SLAS sequence without CS.
If bit 26 (BM bit) of bus A is true for the associative coincidence
word or any succeeding word prior to the last word transferred, the
SLAS BM error will be set. This will relinquish control to the
Error Termination sequence and will cause an error interrupt.
2.2.2.2.3.5 Termination Sequence (TS)
The Termination Sequence is an automatic sequence of the DCU which
occurs at the completion of a DCU process. The contents of the CAR
are dumped into location 24 (bits 0 thru 14) of the Initialization
Table (FIG. A of Appendix III).
After the dump, a DCU interrupt is set. If the DMS process was
completed with no errors, the DCU Ready interrupt follows the
Termination Sequence.
FIG. 25 shows the input control to the Termination Sequence as
outputs from the End Sequence. The End Sequence is a transient
state providing the hardware link between drum-core transfers and
Termination.
It should be noted that a Termination Sequence which follows an
Error Termination Sequence will also dump the low order bits of the
IAR.
2.2.2.2.3.6 error Termination Sequence (ETS)
When an error is detected the three error/status indicator words
(E/S words) will be dumped into locations 18, 20, and 22 of the
table giving details of the error and status of the DMS at the time
of the error. The 5 low order bits of the LAR are captured into
bits 15-19 of the CAR at the time of the error and are dumped into
core by the normal termination sequence. A DCU Error Interrupt
follows, and the DCU ERR/STATUS IN CORE sense line is set
indicating a successful transfer of the error status indicator
words in core.
(See FIG. 25). The status of the captured IAR bits in the CAR may
be important for diagnostics depending upon when the error
occurred. For example, the TS which follows an ETS from an error
that occurred during initialization would reveal the last location
of the table that was loaded into the DMS. An error during the
execution of one of the data transfer directives causing the IAR to
be captured would reveal the last entry read during
initialization.
During a CPD Spill (see section 2.2.3.1.3), the captured IAR bits
should display the state of the IAR just as the Error Termination
Sequence is entered or 18 (10010), providing another check.
A hardware description of the TS and ETS is contained in the flow
chart (FIG. 27). The notes along the flow chart functions indicate
which DCU timing pulses cause the action in the boxes.
2.2.2.2.3.7 Forced Errors
The DCU has the hardware capability of checking some of its error
detecting circuits. Certain bits of the E/S words will be set (1)
if the particular detectors are working properly. This forced error
routining of the DCU is possible thru the CPD Maintenance command
which is discussed fully in section 2.2.3.1.4.
2.2.2.2.3.8 Spill
Under the control of CPD (CPD Spill) the DCU can dump all registers
(including E/S words) of the DMS into the initialization table --
see the spill format shown in the right hand column of DMS,
Appendix III.
2.2.3 interface
the following section will present the DMS from an interface point
of view. The CPD control (interface with CCP) will be discussed in
detail. Since sense lines reveal the states of the DCU, these
states and a thorough analysis of the DCU sense and interrupt lines
will be considered. The memory protect system and finally the core
access characteristics of the DCU will be deliberated. Refer to
FIG. 34 for access-response characteristics of the DCU.
2.2.3.1 cpd directives (Control Pulse Directives)
The CPD lines interface with the CCP thru the CMC. There are four
CPD commands. Two data and one CPD line sent to the DMS. The CPD
clears or begins processing in the DMS.
2.2.3.1.1 cpd clear (DLO = 0, DL1 = 0)
This CPD completely clears the DMS. All registers except for the
IAR, all error latches, all control and sequence circuits are
reset. If the machine has successfully cleared, the DCU IDLE sense
line will be set. No interrupt will occur. When the CPD pulse is
removed, the machine will be cleared and the IDLE sense line may be
checked.
Under normal conditions (no error) the CPD Clear should be issued
when either the DCU READY or DCU ERROR sense line is set. The
directive may, however, be issued while the DCU is active. In this
event, the job will be aborted after the completion of the present
core request. An Error Termination Sequence will follow and bit 21
word 22 in the ITE will be set. Termination will set the DCU ERROR
interrupt. A CPD Clear may now be issued to clear the DMS. If the
double CPD is used to abort DCU processing and the interrupt is not
desired, the following sequence of instructions must be used:
1. Set Input Test Register -- Cause Port Malfunction
2. Reset Input Test Register -- Restore Port
3. Reset Port on Line Register -- Since the REI below will initiate
DCU requests (ETS), the CMC must ignore the requests.
4. REI -- Removes Port Malfunction
5. LLR 48 -- Wait 24 microsec. for DCU Core Access Trouble to be
set. Inhibits DCU Interrupt.
6. DMS CPD Clear -- Reset DMS
7. set Port on Line Register -- Restore POLR.
2.2.3.1.2 cpd initialize (DLO = 1, DL1 = 0)
This CPD command begins initialization which is the process of
loading the various registers in the DMS from an area in core
called the Initialization Table (ITE, DMS, Appendix III). Each word
is alternately copied back in core for parity checks. The even
locations (left hand side of DMS, Appendix III) are read into the
DMS registers and the odd locations are filled with a copy of the
registers by writing back into core from the corresponding register
of the DMS. The process follows an alternate read core-write core
pattern.
Referring to FIGS. 23 and 25, the data is received over bus A,
loaded in a register and placed on bus C (via bus B is required)
and sent back to core. For the DAR, the cross transfer of bus A to
bus B to bus C (see FIG. 25) is used to go from core to drum or
from drum to core. In this manner, the integrity of the data, the
DMS registers, and the DMS buses is checked by parity checking
schemes in the DMS and CMC. If a parity error is detected in the
DMS, the word is still copied back into core, but an attempt is
made to correct the parity via (bit 24) at the output bus as it is
written back in core. This way the core will always see correct
parity, but a comparison between adjacent entries of the
Initialization Table can be made in core to locate the erroneous
bit if required.
During initialization, the complement of the core data is loaded
into the LR; however, the actual uncomplemented value is copied
back into core. The complement is loaded into the LR because this
register will be decremented by the input clock pulses. The number
of words read into the DMS registers (initialized) from the
Initialization Table (ITE) and the time involved depends upon the
directive in the IR as illustrated in the table below with
reference to the ITE figure (DMS, Appendix III).
__________________________________________________________________________
Locations Locations Execution Register read from Written in
Directive Time Loaded ITE (DMS ITE (DMS in LR (DMS micro- in DMS
Appendix III) Appendix III) Appendix II) seconds
__________________________________________________________________________
A IR/LR 0 1 DAC Maint 15 B A+DAR+CAR 0,2,4 1,3,5 Block Trans 45
Write or Read C B+SR1+MR1 B+6+8 B+7+9 SLAS 90 D C+SR2+MR2 C+10+12
C+11+13 MLS 135 +SR3+MR3 +14+16 +15+17
__________________________________________________________________________
During this sequence the Initialization Sequence status bit of the
error/status register of the DCU (Bit 0, word 22 in ITE) is set
until the last register is loaded.
2.2.3.1.3 CPD Spill (DL0 = 0, DL1 = 1)
When this CPD is issued all DCU and DAC registers are dumped into
the odd locations of the initialization table, and the three error
status indicator words are dumped into locations 18, 20 and 22. The
CPD Spill command utilizes the Initialization Sequence with dummy
reads, Error Termination Sequence, and the Termination Sequence.
The CPD Spill format is shown in the right hand column of DMS
Appendix III.
Location 23 should contain all zeros if there are no faults,
indicating the quiescent state of busses B and C. When the CAR is
dumped in location 24, bits 15-19 will contain the low order bits
of the IAR. If the spill is successful, these bits should display
18 or
Location 24 1 0 0 1 0 CAR in ITE 25 20 19 18 17 16 15 14 0
indicating the state of this register just as the Error Termination
portion of the spill is entered. These bits have a different
meaning when the CAR is dumped in location during the termination
sequence of an error interrupt on DCU interrupts.
The meaning of the data dumped in the other locations is shown in
the right hand column of DMS Appendix III. The CPD Spill takes 25
drum interlace periods or about 188 microsec.
2.2.3.1.4 CPD Maintenance (DL0=1, DL=1)
This CPD command can be used to check certain error detecting
circuits of the DCU. When issued, the DMS will proceed as though a
normal Initialize CPD was issued. After initialization, the
instruction in the IR will be executed followed by normal
termination.
The difference, however, is the DCU will be forced to detect
certain errors. The error detectors will be set at the proper time
during the CPD Maintenance Sequence but an Error Termination
Sequence will not begin when the error occurs as would begin when
an error occurs during any normal data transfer processing. This
means that the indiciator bits of the particular error detecting
circuits being checked will not be automatically dumped into core
as they normally are following an error. A CPD spill request is
necessary to dump into core the words containing the error/status
indicator bits (words 18, 20, and 22 of the Initialization Table).
If the error detecting circuits are working, ones should be present
for certain indicator bits depending upon which directive was in
the IR when CPD Maintenance was issued. If at least one of the
error detecting circuits has detected the simulated error, the
spill will be followed by a DCU Error interrupt.
1. CPD Maintenance -- Write Drum directive in IR. When CPD
Maintenance is issued with a drum write directive in the IR, six
indicator bits and one sense line should be set. The set indicator
bits should be:
1. DAC ERROR -- bit 19 word 22 in ITE
2. dac parity -- bit 5 word 20 in ITE
3. bus a parity -- bit 22 word 22 in ITE
4. bus c parity -- bit 23 word 22 in ITE
5. pd skew -- bit 22 word 18 in ITE
6. read time out error -- bit 12 word 22 in ITE
The CORE ACCESS TRBL sense line will also be set because of the
READ TIME OUT ERROR.
2. cpd maintenance-Read Drum Directive in IR. With a read drum
directive in the IR, the same error bits except for 1 and 2 above
should be set.
3. CPD Maintenance -- Other directive in IR. The CORE ACCESS TRBL
sense line and READ TIME OUT ERROR (bit 12 word 22 in ITE) may be
set by issuing a CPD Maintenance with a directive other than Read
Drum or Write Drum in the IR.
The parity errors are detected by a technique of inhibiting three
bits (21, 22 and 23) at the input bus (bus A). i.e., a word with
correct parity from drum (core) may be used because the bad parity
simulation takes place at the Data Bus A Multiplex circuit (FIG.
25). This approach eliminated the need to write bad parity in core
or on drum since the bus A control for bits 21, 22 and 23 are
handled separately because of Associative Search Requirements. It
must be remembered; however; that bits 21, 22, and 23 of the known
word as it exists in core or on drum must contain odd parity.
Inhibiting them therefore causes even (bad parity in the DCU).
The execution time of CPD Maintenance is determined by the
directive in the IR.
2.2.3.2 sense Lines and Interrupts
The DMS contains 10 sense lines to interface with the CCP (thru the
CMC). Two of these sense lines are interrupts. The DMS sense lines
provide indications of the present state of the machine. They are
used; 1) as an aid in diagnostics when the E/S words are not
available and 2) to indicate present states of the DMS which could
be necessary information to the CCP before and/or after certain
action is taken involving the DMS.
2.2.3.2.1 dcu interrupts
The two sense lines that interrupt the CCP are DCU READY AND DCU
ERROR. The DCU Termination Sequence is followed by a DCU READY
Interrupt if processing was successful (errorless). The DCU ERROR
Interrupt is set indicating that an error or a CPD violation has
been detected. A special case of the DCU ERROR interrupt is DCU
TIME OUT detection.
The interrupts may be inhibited by the DCU ON LINE interface
control from the CMC. In other words, the DMS may be accessed for
normal processing but the interrupts will not be set.
2.2.3.2.2 DCU STATES
Table 1 below contains a summary of the basic states of the DMS.
State (1) is the only state from which a data transfer directive
may be issued. Tables 2 and 3 show other DMS States and are
discussed in the sections on memory protect and core access
problems.
TABLE 1 -- DCU STATES
__________________________________________________________________________
DCU State Sense Lines Description DCU DCU DCU RDY ERR IDLE
__________________________________________________________________________
(1) 0 0 1 DMS is IDLE and READY for any CPD (2) 0 0 0 MS is ACTIVE
or QUIESCENT (see TABLE 2) (3) 1 0 0 DMS has completed task.
Waiting See (B) of FIG. 34. (4) 0 1 0 An error was detected.
Waiting See (B) of FIG.
__________________________________________________________________________
34.
TABLE 2 -- DCU STATES FROM CORE ACCESS PROBLEM
__________________________________________________________________________
PORT MAL- PORT MAL- CORE DCU FUNCTION FUNCTION ACCESS DCU INTERRUPT
DCU CMC TIME (ONE CMC) (OTHER CMC) TRBL STATE SET BY TRBL TRBL OUT
__________________________________________________________________________
1 1 0 QUIESCENT CMC 1 0 0 1 0 0 QUIESCENT CMC 0 1 0 0 1 0 QUIESCENT
CMC 0 1 0 0 0 1 QUIESCENT DCU 1 0 1 then INTERRUPT 1 0 1 QUIESCENT
CMC 0 1 0 0 1 1 QUIESCENT CMC 0 1 0 1 1 1 QUIESCENT CMD 1 0 0
DCU-CMC SENSE LINE MP BIT AREAS IN CORE CONTROL Privileged Working
Memory Prot Block Init Elsewhere Transfer With Table Bit 25 Trans 0
0 0 Yes Yes No 0 0 1 DCU ERROR 0 1 0 No Yes No 0 1 1 DCU ERROR 1 0
0 Yes Yes Yes 1 0 1 Yes Yes Yes 1* 1* 0 No Yes No) Impossible 1* 1*
1 No Yes No)
__________________________________________________________________________
*NOTE -- last two entries are normally impossible
2.2.3.3 Memory Protect Scheme
Bit 25 of all the registers in the DMS is the memory protect bit
defining protected or unprotected locations in core (bit set or not
set respectively). Bit 1 of the IR sets the DCU in the privileged
transfer mode.
In writing drum the memory protect bit 25 will be recorded as it
comes from core. In reading the drum, when the privileged transfer
bit (bit 19 = 0 in IR) is not set, an error will be detected when
the drum word being read has a memory protect bit set. An Error
Termination Sequence and a DCU ERROR interrupt will follow. The
word will not be written into core. When the DCU is not privileged,
only words with bit 25-0 may be written into core. In reading drum
when the DCU is privileged, words will be written into core
regardless of the status of the memory protect bit 25. Memory
protection is extended further by the "WORKING WITH TABLE" sense
line. This line is set when the DCU is reading or writing into the
initialization table. The two areas in core reserved for data
transfers from the DMS are the Initialization Table Area (32 or 64
words) and the Block Transfer Area 2000 words). Table 3 in section
3.2.2 shows the locations in core that may be written for the
various combinations of the "Privileged Transfer" control line,
"WORKING WITH TABLE" sense line and Memory Protect bit 25. The "NO"
entries in Table 3 imply that if an attempt is made to write in
these core areas under these conditions, the error will be detected
by the CMC.
The drum address of the last word transferred when a memory protect
error occurs may be calculated. The word containing the memory
protect violation will not be written into core.
Drum address of last word transferred =
dar.sub.initial + 5(lr.sub.initial - lr.sub.final - 2)
where
Dar.sub.initial = location 2 of ITE
Lr.sub.initial = location 0 of ITE (bits 0-14)
Lr.sub.final = location 1 of ITE (bits 0-14) after CPD Spill
2.2.3.4 Core Interface
The DMS is placed on line by the DCU ON LINE control signal from
the CMC. This signal enables the DCU READY and DCU ERROR interrupt
gates. To test the interface cables and cards all outputs to the
CMC may be set to a logic 1 by the TEST CMC INPUTS control from the
CMC. Core Address (15 bits and 1 parity) is provided over DCU bus D
(FIG. 25). 26 data bits are received from core via bus A and sent
to core via bus C.
To read core, the DCU sets a CORE READ REQUEST. Within one
interlace period the CMC will select the identifying DCU port and
fetch the word at the location defined by the address on bus D of
the DCU. When the data is available to the DCU, the CMC sends a
DATA AVAILABLE PULSE.
To write core, the DCU sets a CORE WRITE REQUEST. Within one
interlace period the CMC will write the data present on DCU bus C
at the core location defined by the address on DCU bus D. When
complete, the CMC responds with a DATA LOADED PULSE.
2.2.3.5 maintenance
2.2.3.5.1 DCU Error Status Indicators (E/S words).
The following section describes each bit of the three E/S words.
The description indicates when each bit is set and reset, drum
location and other register status when applicable.
2.2.3.5.1.1 DCU E/S Indicator Word 22
The following is a description of the error/status indicator bits
of the DCU indicator word 22.
Bit 0 -- Initialization Sequence (Init. Seq. Ind). Bit 0 is set in
the DCU only when the DCU is in its initialization sequence, Bit 0
set in the initialization table indicates an error was detected
during the initialization sequence.
Bit 1 -- Error Initialization Sequence (Err Init Seq Status). Bit 1
is set in the DCU when it has been issued a CPD initialize command
while in an error interrupt state (DCU ERROR interrupt set). Bit 1
is reset when the ets begins. It must always be reset in the
ITE.
Bit 2 -- Write Sequence (Write Seq Ind). Bit 2 is set in the DCU is
reading from core and writing on drum. Bit 2 set in the
initialization table indicates an error was detected during the
Write Sequence for these conditions the LR contains the number of
words -2 remaining to be written on drum.
Bit 3 -- Read Sequence (Read Seq Ind). Bit 3 is set in the DCU when
it is reading from drum and writing into core. If set in the
initialization table, an error was detected during the Read
Sequence. The LR contains the number of words -1 remaining to be
written into core.
Bit 4 -- Single Level Associative Search (SLAS Ind). Bit 4 is set
in the DCU when it is in the SLAS sequence. If an error occurs
during this sequence bit 4 will be set in the initialization table
in core.
Bit 5 -- Multi Level Associative Search (MLS Ind) Bit 5 is set in
the DCU when it is in the MLS sequence. If an error occurs during
this sequence, bit 5 will be set in the initialization table in
core.
Bit 6 -- Termination Sequence (Term Seq Ind). Bit 6 is set in the
DCU during the Termination Sequence. This bit must always be reset
in the ITE.
Bit 7 -- Error Termination Sequence (ETS Ind) This bit is set in
the DCU, when the machine is dumping the three E/S words into
locations 18, 20 and 22 of the initialization table. The bit should
be set in the core table.
Bit 8 -- CPD Spill (CPD Spill Ind) The CPD Spill bit is set when
CPD requests a dump of all registers and E/S words of the DMS into
core. This bit is provided to inform the operator that a CPD spill
was requested.
Bit 9 -- CPD Maintenance (CPD Maint Ind). Bit 9 is set in the DCU
when the CPD Maintenance Directive is issued. This bit remains set
until the next CPD clear is issued. In other words this bit will be
set (written) in core by a CPD spill following CPD Maintenance.
Bit 10 -- Maintenance Sequence (Maint Seq Ind). Bit 10 is set in
the DCU when it begins executing the DAC Maintenance directive
specified in the IR.
Bit 11 -- Write Block Mark. (Write BM Ind). This bit is set in the
DCU during the Write Sequence when the last word is written on
drum. This bit must always be reset in the ITE.
Bit 12 -- Read Time Out Error (RTOE Err). This bit indicates that
response to a CORE READ REQUEST was not received in the proper
time.
Bit 13 -- Begin Error Termination Sequence (BETS Ind). This bit is
set in the DCU whenever an error is detected. The bit is set in the
initialization table if the E/S word dump was preceded by a
detected error, as opposed to a CPD spill request and no existing
errors.
Bit 14 -- ( - ) En A/D to Core. When bit 14 is reset in the DCU,
bus A, C, and D are enabled for a drum read. This bit should always
be set in the E/S words of the initialization table.
Bit 15 -- ( - ) En A/D to Drum. When this bit is reset in the DCU,
bus A, C, and D are enabled for a drum write. See bit 14.
Bit 16 -- DCU Time Out (DCU Time Out Ind). Bit 16 indicates that a
23 drum revolution time period (approx. 385 ms) has elapsed between
a CPD command and a DCU interrupt. The Selected Counter in the PA
is captured and loaded into the DAR when the time out occurs.
Bit 17 -- Memory Protect Error (MP Err Ind). Bit 17 is set in the
initialization table when an unprivileged DCU attempts to transfer
(read a protected word from drum to core). The word causing the
error is frozen in the DBR and does not get written into core. The
number of words transferred =
LR.sub.I - LR.sub.f - 1
The drum address of the word containing the error may be found
by
DA + 5 (LR.sub.I - LR.sub.f - 1)
where
Da = initial drum address
Lr.sub.i = initial contents of LR
Lr.sub.f = final contents of LR
The CAR contains the core address or core +1 of the last word
written in core.
Bit 18 -- Block Mark Error -- SLCS (BM Err SLCS Ind) Bit 18 is set
in the initialization table when the conditions below do not occur
simultaneously during a read drum sequence:
1. LR = 0
2. block Mark Bit = 1
The word in the CBR when the error is detected is frozen and
written into core. The drum address of this word may be found:
DA + 5 (LR.sub.I - LR.sub.f - 2)
The number of words transferred =
LR.sub.I - LR.sub.f - 1
(See bit 17 for definition of terms)
The CAR contains the core address or core address +1 of the last
word written in core.
Bit 19 -- DAC Error (DAC Error (DAC Err Ind) The Drum Access
Circuit Error Indicator is set in the initialization table when an
error is detected in the PA or drum access circuits. (See E/S word
20)
Bit 20 -- Initialization Error (Init Err Ind). Bit 20 is set of the
DCU is initialized with a data transfer directive in the IR and the
DCU is in the READY or ERROR interrupt state.
Bit 21 -- CPD Error (CPD Err Ind) CPD Error is set in the
initialization table when the DCU receives a CPD during a DCU
active mode (processing). Where the LR is used the number of words
transferred may be found by:
LR.sub.I - LR.sub.f - 1
Bit 22 -- Bus A Parity (Bus A Par Err Ind). Bit 22 is set when even
parity is detected at Bus A (input bus). During a SLCS drum read,
bus A parity error will freeze the word in the DBR and its drum
address + 12 will be loaded into the DAR. The word will be parity
corrected at bus C and written into core. The CAR contains the core
address or core address + 1 of the word written into core. The
number of words transferred may be found by:
LR.sub.I - LR.sub.f - 1
When writing drum, bus A parity checks the word from core. An error
will freeze the word in the CBR and the word will not be written on
drum. The CAR contains the address + 1 of the error detected word.
The number of words transferred to drum may be found by:
LR.sub.I - LR.sub.f - 2
Bit 23 -- Bus C Parity (Bus C Par Err Ind). Bit 23 is set when even
parity is detected at Bus C (output bus). During a SLCS drum read,
bus C parity error will freeze the word in the DBR and its drum
address + 12 will be loaded into the DAR. The word is parity
corrected at bus C and written into core. The CAR contains the core
address or the core address + 1 of the word written into core. The
number of words transferred may be found by:
LR.sub.I - LR.sub.f - 1
When writing drum, bus C parity error freezes the word in the CBR,
and the word will not be written on drum. The CAR contains the core
address + 1 of the error detected word. The number of words
transferred to drum may be found by:
LR.sub.I - LR.sub.f - 2
2.2.3.5.1.2 DCU E/S Indicator Word 18
The following is a description of the error/status indicator bits
of the DCU indicator word 18.
Bit 0 -- The Previous Word Interrupt bit (PVWI STAT) is set during
the PVWI action for the MLS sequence. If an error occurs at this
time bit 0 will be set in the initialization table (ITE).
Bit 1 -- The Present Word Interrupt bit (PSWI STAT) is set for one
interlace cycle (P.sub.3 to P.sub.3 + 1) during the PSWI action of
the MLS sequence. If an error occurs at this time bit 1 will be set
in the initialization table (ITE).
Bit 2 -- The Level End Interrupt Bit (LEI STAT) is for one
interlace cycle (P.sub.3 to P.sub.3 + 1) during the LEI action of
the MLS sequence. If an error occurs at this time bit 2 will be set
in the initialization table (ITE).
Bit 3 -- The Invalid Action Interrupt bit (LAI STAT) is set during
the IAI action of the MLS sequence. This action is an error
condition, and the DCU will enter the Error Termination Sequence
(ETS) and bit 3 will be set in the ITE.
Bit 4 -- The Enter Next Level bit (ENL STAT) is set for one
interlace cycle (P.sub.3 to P.sub.3 + 1) during the ENL action of
the MLS sequence. If an error occurs at this time bit 4 will be set
in the ITE.
Bit 5 -- The drum Modify Mark Register bit (DMMR STAT) is set
during the DMMW action of the MLS sequence. If an error occurs at
this time bit 5 will be set in the ITE.
Bit 6 -- The Drum Modify Search Register Bit (DMSR STAT) is set
during the DMSW action of the MLS sequence. If an error occurs at
this time bit 5 will be set in the ITE.
Bit 7 -- The Reset Read Latch bit (RRL STAT) is set for one
interlace cycle (P.sub.3 to P.sub.3 + 1) of the RRL action of the
MLS sequence. If an error occurs at this time bit 7 will be set in
the ITE.
Bit 8 -- Level 2 or level 3 bit (L.sub.2 + L.sub.3), this bit is
set when the DCU is in level 2 or level 3 of the MLS Sequence. If
an error occurs while in either level bit 8 will be set in the ITE.
If a CPD spill is initiated after an MLS sequence and this bit
becomes set in the ITE, the MLS sequence terminated in level 2 or
level 3. To determine which level, it is necessary to refer also to
bit 9 of E/S word 18.
Bit 9 -- Level 1 or Level 3 bit (L.sub.1 + L.sub.3), this bit
functions the same as the preceding bit 8 except, bit 9 indicates
the MLS sequence terminated in level 1 or 3.
Bit 10 -- The drum Modify Mask Word bit (DMMW BIT) is set if the
drum has overwritten the mask register, and will remain set until
the DCU enters the next level of MLS sequence. If an error occurred
during this time bit 11 will be set in the ITE.
Bit 11 -- The drum Modify Mask Word bit (DMMW BIT) is set if the
drum has overwritten the mask register, and will remain set until
the DCU enters the next level of MLS sequence. If an error occurred
during this time bit 11 will be set in the ITE.
Bit 12 -- The Drum Modify Search Word bit (DMSW BIT) is set if the
drum has overwritten the search register, and will remain set until
the DCU enters the next level of MLS sequence. If an error occurred
during this time bit 12 will be set in the ITE.
Bit 13 -- The Read Control Bits bit (READ CTL BITS) is set when the
MLS sequence is scanning the CBR and DBR control bits (21-23). The
scanning of control bits starts with coincidence to enter a level
and continues until a reset read latch or interrupt action is
entered. This bit 13 must always be 0 in the ITE.
Bit 14 -- The Level End Interrupt Flag bit (LEIF) is set when level
1 or 2 coincidence cannot be found for a MLS sequence. This bit
will also be set if, for a SLAS or MLS sequence with a counter
start, a block mark is detected after counter coincidence (Z
counter) and prior to associative coincidence (Z assoc.).
Bit 15 -- The Pulse Distributor Bit 1 (PAD BIT 1) is set for the
counts of P.sub.2 and P.sub.4 but must always be 0 in the ITE.
Bit 16 -- The Pulse Distributor Bit 2 (INTERL STRAP 6) is set for
the counts of P.sub.3 and P.sub.4, but must always be 0 in the
ITE.
Bit 17 -- The Pulse Distributor Bit 3 (PD BIT 3) is set for the
count of P.sub.5, but must always be 0 in the ITE.
Bit 18 -- The Associative Search Sequence bit (ASSEQ) is set when
the DCU is in a SLAS or MLS sequence, but bit 18 must always be 0
in the ITE.
Bit 19 -- The Distributor Enable bit (DIST EN) is set when the
Pulse Distributor is enabled, but bit 19 must always be 0 in the
ITE.
Bit 20 -- The Invalid Action Interrupt Error bit (IAI ERROR) is set
if there is an invalid combination of control bits, read latch
status, coincidence status, and MLS sequence level. This invalid
combination will cause an error interrupt and bit 20 in the ITE
will be set.
Bit 21 -- The Block Mark Error bit (BM ERROR BIT) is set if the DCU
is performing a SLAS counter start sequence and a block mark is
detected after associative coincidence and before the last word of
the transfer. This error will cause an error interrupt and bit 21
in the ITE will be set.
Bit 22 -- The Pulse Distributor Skew bit (PD SKEW) is set when the
pulse distributor and the DAC interlace counter are not in
synchronization. This will cause an error interrupt and bit 22 in
the ITE will be set.
Bit 23 -- The Invalid Operation Code bit (INVALID OP) is true when
the OP Code field of the instruction register is invalid. This will
cause an error interrupt and bit 23 in the ITE will be set.
2.2.3.5.2 DAC Error/Status Indicators
A 24 bit word for storing a record of the operational status of the
DAC circuitry has been assigned to the DAC. This word will be
stored at address 20 of the Initialization Table as a result of a
DCU error termination sequence or a CPD spill. These 24 bits
indicate the status of 19 error detectors and 5 status monitoring
points in the DAC. A bit set to 1 denotes the true condition in all
cases. Bits 0 through 8 are assigned to Peripheral Adapter; bits 9
through 15 are assigned to the Clock Circuits; bit 16 indicates
Block Mark status for the word currently in the DBR; and bits 17
through 23 are assigned to the Recording Circuits. A description of
each indicator bit follows.
2.2.3.5.2.1 DAC Error Detector and Status Indicator
Descriptions
Bit 0 -- Mode Error - Indicates a discrepancy between the RWI bit
of the Drum Address Register (DAR) and the directive in the
instruction register, the error latch will be set on the trailing
edge of the first DCP1 after READ ENABLE or WRITE ENABLE (from DCU
becomes true).
Bit 1 -- Invalid Segment Error -- Indicates that an attempt has
been made to select a segment that is not assigned to that
particular DCU. The error latch will be set when ROUTE TO DAR is
sent from the DCU to the PA. DAC ERROR will not be enabled until
READ ENABLE or WRITE ENABLE becomes true.
Bit 2 -- Protected Segment Error -- Indicates that an attempt has
been made to write in a read only segment. The error latch will be
set when WRITE ENABLE becomes true. This error indication can be
inhibited by operating a manual switch which is mounted on the
Segment Decode card.
Bit 3 -- Binary Counter Error -- Detects a binary counter failure
or the absence of counter clock or reset pulses. The error latch
will be set on the first Drum Reset Pulse (DRP) after the error
occurs. DAC ERROR will not be enabled until READ ENABLE or WRITE
ENABLE becomes true.
Bit 4 -- BCD Counter Error -- Detects a BCD counter failure or the
absence of counter clock or reset pulses. The error latch will be
set on the first Drum Reset Pulse (DRP) after the error occurs. DAC
ERROR will not be enabled until READ ENABLE or WRITE ENABLE becomes
true.
Bit 5 -- DAC Parity Error -- Detects a parity error in the data in
the Drum Buffer Register (DBR). The error latch will be set appr.
450 ns after the word is loaded into the DBR. The count sent to the
Drum Address Register (DAR) when the error occurs will be the data
words address + 8 for a write operation.
Bit 6 -- Route Error -- The error occurs if
1. a Route to DAR is sent while the PA is active
2. a Route to DBR is sent while the PA is inactive.
The error latch will be set on one of these two signals depending
upon the fault location:
Bit 7 -- PA Active -- PA Active is a storage element which is set
when the PA is transferring data to or from the Drum. It is set by
either counter coincidence (Z COUNTER) or associative search
coincidence (Z ASSOC) and is reset at the end of a transfer when
the DCU drops READ ENABLE or WRITE ENABLE.
Bit 8 -- Enable Binary Capture - This storage element indicates
which counter is transferred to the address bits of the DAR. If
set, the binary count is sent to the DAR at the appropriate times;
if reset, the BCD count will be sent to the DAR. It is set by ROUTE
TO DAR .sup.. DAR22 or a DAC Parity Error. It is reset by ROUTE TO
DAR .sup.. DAR22.
Bit 9 -- Auxiliary MRP 1 Error - Detects an absence of DRP pulses.
The error latch which is set during a master MRP, enables DMS Clock
Track Error which causes an immediate DCU Error Interrupt.
Bit 10 -- Auxiliary MRP 2 Error -- same as Aux. MRP 1 Error.
Bit 11 -- Auxiliary DIP 1 Error -- Detects the absence of Drum
Index Pulses (DIP). The error can occur randomly. The latch will be
set immediately, enabling DMS Clock Track Error.
Bit 12 -- Auxiliary DIP 2 Error -- Same as Aux. DIP 1 Error.
Bit 13 -- Drum Speed Error -- Detects when the drum speed drops
below an operable level. The latch will set immediately, enabling
DMS Clock Track Error.
Bit 14 -- Master Track Error -- Detects the absence of master MRP.
The detector circuitry checks for the presence of an MRP for each
auxiliary DRP. This detector will also be set by the absence of a
DIP. This Error does not cause DMS Clock Track Error.
Bit 15 -- DIP Skew Error -- Detects skew between the auxiliary DIP
tracks. The error can occur randomly and does not cause a DMS Clock
Track Error.
Bit 16 -- BM 26 DCU/WR -- This indicator denotes the status of the
Block Mark bit of the word currently in the DBR. A 1 specifies that
the BM bit is set. The indicator is set or reset each time a word
is loaded into the DBR.
Bit 17 -- Head Select Input Error -- This detector is set by a 1 -
out - of - 18 circuit which monitors the segment select input to
the Memory Protect Circuit and is set if none or more than one
segment has been selected. The error latch will be set appr. 15
microsec after ROUTE TO DAR and before READ ENABLE or WRITE ENABLE
becomes true.
Bit 18 -- Head Select Output Error -- Same as Head Select Input
Error except the monitor point is at the output of the Memory
Protect Circuit.
Bit 19 -- Access Circuit Error - The error is detected on the DAC
Write/Read Control Circuit and is gated in the PA so that DAC ERROR
is not enabled until READ ENABLE becomes true.
Bit 20 -- Write Control Error -- Checks the integrity of write
control signals to the write/read circuits. The error signal is
gated in the PA.
Bit 21 -- MPC Write Inhibit -- This detector does not cause DAC
ERROR directly. The signal sent to the DAC ERROR gate is MPC ERROR
which cannot become true until either READ ENABLE or WRITE ENABLE
becomes true.
Bit 22 -- Power Supply or Drum Speed Error -- Gated in the PA so
DAC ERROR does not become true until READ ENABLE or WRITE ENABLE
becomes true.
Bit 23 -- + 5V Redund Error -- Monitors the redundant power supply
of the Memory Protect Circuit. The error signal is gated in the
PA.
2.2.3.5.2.2 dac forced Error Checks
Simulated faults are forced into the DAC via an instruction
register directive called DAC Maintenance. Ten simulated faults and
a clock transfer feature are initiated by the same directive. The
simulated faults provide a means of checking DAC error detectors
that cannot be checked by forcing software errors. The clock
transfer causes the alternate auxiliary clock track to be switched
on-line and does not cause an error.
The first entry in the Initialization Table provides all the
control and data information required for DAC maintenance. The
format is shown below. ##SPC35##
Bits 0 through 15, except for the clock transfer bit (10), are
error simulator bits. They are divided into three groups, the
peripheral adapter, the clock circuits and the recording circuits.
A logic 1 in bit 16, 17 or 18 will cause the circuitry to enable
the appropriate group of simulator bits. It is possible to enable
more than one group simultaneously or more than one error simulator
within a group simultaneously. When writing programs, care will
have to be taken to insure that only those bits associated with the
fault to be simulated are set to logic 1. All others should be at
logic 0. Bits 20 through 23 form the instruction word directive
which sets up the DCU circuitry for a DAC maintenance
operation.
The DAC maintenance directive is initiated by DCU Initialization
CPD. After the first entry in the Initialization Table has been
written into the Instruction Register of the DCU, bits 20 through
23 are decoded.
After recognizing the decoded directive as DAC maintenance, the DCU
sends Instruction Register bits 0 through 18 and an enabling pulse
(ROUTE ERR SIM) to the Error Simulator Circuit of the DAC. If bit
16, 17 or 18 is at logic 1 and one of the error simulator bits is
also at logic 1, the Error Simulator Circuit will force a simulated
fault in the appropriate circuit. For example, if bits 16 and 0 are
at logic 1, the INHIBIT DRP error simulator signal will inhibit the
resetting of the address counters after the maximum count (10,998)
has been reached. This will cause the counter error detectors to be
set. An error detector being set will cause DAC Error to be sent to
the DCU, resulting in a DCU error interrupt. The DCU will go
through its error termination sequence. Word 20 of the
Initialization Table, the DAC error indicators, will be checked to
see if the appropriate indicators were set. If so, it can be
assumed that the detectors functioned properly.
The signal that forces the simulated fault will remain at a
constant level until reset by the CPD CLEAR. If more than one error
detector is to be checked in sequence, the DCU will be
reinitialized for each individual test.
Error simulator signals, instruction register bits that must be set
for each, and the word 20 indicator bits that will be set as a
result of the simulated fault are listed on the next page.
DAC MAINTENANCE ERROR SIMULATOR
__________________________________________________________________________
LISTING FAULT SIMULATOR INSTRUCTION ERROR DETECTORS SET LEAD NAME
REGISTER BITS AS RESULT OF SET TO LOGIC 1 SIMULATED FAULT COMMENTS
__________________________________________________________________________
INHIBIT DRB 16, 0 DAC ERR 3 -- BIN CTR ERR INHIBITS RESET OF PA DAC
ERR 4 -- BCD CTR ERR ADDRESS COUNTERS. HOLD CTR RST 16, 1 DAC ERR 3
-- BIN CTR ERR HOLDS PA ADDRESS DAC ERR 4 -- BCD CTR ERR COUNTERS
IN A RESET STATE. ADVANCE COUNT 16, 2 DAC ERR 3 -- BIN CTR ERR
FORCES ADDRESS COUNTERS DAC ERR 4 -- BCD CTR ERR TO REACH MAX.
COUNT EARLY. DECODE INHIBIT 16, 3 DAC ERR 3 -- BIN CTR ERR
SIMULATES THE EFFECT OF DAC ERR 4 -- BCD CTR ERR MISSING COUNTER
CLOCK PULSES. MRP ERR SIM 17, 6 DAC ERR 14 -- MASTER TRK ERR ERROR
WILL BE FORCED ON WHICHEVER (DAC ERR 9 -- AUX MRP 1 ERR + TRACK IS
ON-LINE THE FORCED ERROR DAC ERR 10 -- AUX MRP 2 ERR) WILL CAUSE A
CLOCK TRANSFER. DIP ERR SIM 17, 7 DAC ERR 14 -- MASTER TRK ERR
ERROR WILL BE FORCED ON WHICHEVER (DAC ERR 11 -- AUX DIP 1 ERR +
TRACK IS ON-LINE. THE FORCED ERROR DAC ERR 12 -- AUX DIP 2 ERR)
WILL CAUSE A CLOCK TRANSFER. SPEED/SKEW SIM 17, 8 DAC ERR 13 --
DRUM SPEED ERR DAC ERR 15 -- DIP SKEW ERR DAC ERR 22 -- PS DRUM SPD
ERR TRANSFER CLOCK 17, 10 none 500 NSEC. TRANSFER CLOCK PULSE. FAIL
TEST INPUT 18, 11 DAC ERR 17 -- HS INPUT ERR FORCES ERROR IN 1 OUT
OF 18 DETECTOR MONITORING SEGMENT SELECT CKT OUTPUTS. FAIL TEST OUT
18, 12 DAC ERR 18 -- HS OUTPUT ERR FORCES ERROR IN 1 OUT OF 18
DETECTOR DAC ERR 19 -- ACCESS CKT ERR MONITORING HEAD SELECT CKT
OUTPUTS. MPC FAIL SIM 18, 13 DAC ERR 22 -- PS DRUM SPD ERR DAC ERR
19 -- ACCESS CKT ERR
__________________________________________________________________________
2.2.3.5.3 dcu time Out
The DCU Time Out sense line causes the DCU ERROR interrupt and
indicates that DMS processing cannot continue because of a hardware
or software error not covered by the detection circuits. In other
words, the DMS is stuck somewhere, and the E/S words may indicate
where. There are some cases, however, where E/S words are not
available for analysis (such as core access or ETS difficulties) in
which case the sense lines must be used. Certain core access
troubles cause DCU TIME OUT indications -- see section 4.4 for
complete coverage of core access problems and related sense line
status.
After the DCU TIME OUT is detected (DCU ERROR interrupt set) a
period of eight interlace periods (approx. 60 .mu.s on interlace 5)
must elapse before error/status indicators may be used. In other
words a software wait may be used by checking the DCU ERROR/STATUS
IN CORE sense line. When set the E/S words are available in core
for diagnostics.
2.2.3.5.4 Core Access Problems
Unique problems may arise which cause core access difficulties. The
CORE ACCESS TRBL sense line is a monitor of the core request time
out circuits. Certain core access trouble conditions could cause
the CMC to set its CMC PORT MALFUNCTION in both CMC's. When this
occurs, and the CORE ACCESS TRBL line is set or not set, the DCU
will enter a state of quiescence (not idle, not ready, and not
active). The DCU will sit in this state (without sending an
interrupt) until another CPD is issued. The interrupt is sent by
the CMC. In all cases (except for a certain prot malfunction) it
may be concluded that the DMS contains the fault. The DMS may be
accessed via CPD for diagnostics. Localization can be accomplished
by running routines based on possible DMS error conditions.
If the PORT MALFUNCTION sense line of one CMC is set and the CORE
ACCESS TRBL line of the DCU is set or not set, the DCU again enters
the quiescent state, but the fault is in the CMC. The interrupt in
this case is set by the CMC.
In the final case where the DCU has trouble accessing core (CORE
ACCESS TRBL Set) and the PORT MALFUNCTION line is not set, the DCU
will enter its quiescent state until a DCU ERROR interrupt is set
by the DCU time out circuits (about .5 sec.).
These decisions are shown in the lower right of the flow chart in
FIG. 34 beginning at D. Table 2 in section 2.2.3.2.2 shows at a
glance the states of the DCU in the event of core access
difficulties. This approach is used to insure that interface errors
of this nature will not cause more than one interrupt to the
CCP.
DMS APPENDIX I
FORMAT OF DMS REGISTERS
1. initialization Address Register -- IAR (15 bits)
This register consists of a 5 bit binary counter and a strapping
field for the high order 10 bits. It is used to form the address
for accessing the Initiation table entry (ITE) in main core memory
during the initiation cycle or during the storage of all DMS
registers into the ITE (caused by a spill CPD). When an Initialize
CPD is issued, the low order 5 bits will be set to 0. This requires
the ITE to begin at a location divisible by 32.
2. Core Address Register -- CAR (26 bits)
The low order 15 bits of this counter and storage register are used
to access main core memory during all active processes other than
the processes for which the Initialization Address Register is
used. This address, loaded during initialization, is used to
specify the starting core address where the data transfer between
core and the drum will take place. Bits 15-20 are not programmable.
The tag field (bits 21, 22, 23) are not used by the DCU and may be
used to aid programs. When the DCU executes the error termination
sequence, bits 15 through 19 will contain the low order 5 bits of
the LAR.
3. limit Register (14 bits)
This is a 14 bit binary counter and storage register. For single
level counter start, the number of words to be transferred is
loaded into this register during the initialization cycle. The
limit register is also used for indexing in the SLAS mode refer to
DMS Appendix II.
4. instruction Register (12 bits)
This is a 12 bit storage register used to hold the DCU directive (4
bits) and the directive extension (6 bits); refer to DMS Appendix
II.
5. core Buffer Register -- CBR (26 bits)
This is a 26 bit storage register used to buffer words which are
written or read into core memory.
6,7,8. Information Search Register - ISR1, 2, 3 (26 bits)
These storage registers (one for each level of search) specify the
drum address or data coincidence to be encountered to enter their
respective levels of associative search. These registers are
normally loaded during the initialization sequence however, the
second and third can be modified with information on drum when
specified by the control bits. When coincidence is found these
registers will be loaded with the drum address +8 of the level
1,2,3 coincidence word respectively.
9,10,11. Information Mask Register -- IMR (26 bits)
These storage registers (one for each level of search) are provided
to facilitate a masked associative search. These registers are
loaded at initialization time similar to the Information Search
registers. When each level of coincidence is found IMR1, 2, 3
respectively, will be loaded with the Core address register which
contains the location of the coincidence word in core. The high
order bit (23) of IMR 2 and 3 will be set if the corresponding
search register was overwritten with a word from drum. Bit 22 will
be set if the mask word was overwritten after initialization.
12. Drum Buffer Register -- DBR (27 bits)
This is a 27 bit register used to buffer words read from (written
onto) Drum.
13. Drum Address Register -- DAR (26 bits)
This 26 bit register has the following format:
______________________________________ RWI CS Space Segment ADD
______________________________________ 23 22 20 16 15 0
______________________________________
Address field -- this field is used to specify a location on the
drum. The value of this field will vary from 0 to 10,998 (Binary or
BCD).
Segment -- This field is used to specify a segment for a read
(write) operation. Its value can vary from 0 to 18 depending on the
number of DCU's assigned to a drum.
Counter select (CS) bit (bit 22)
This bit is used to select the counter BCD or Binary, to be used in
accessing the drum via the angular index value. It also specifies
which counter should be retrieved in the associative search
mode.
Cs = 1 use modified BCD
Cs = 0 use Binary
Read/Write instruction (RWI) bit -- (bit 23) this bit must be set
if the DCU is to write on drum.
Rwi = 1 write
Rwi = 0 read
14. Angular Index Counters
A standard binary and modified BCD counter is required for each DAC
peripheral Adapter. The range of this counter is from 0 to 10,998.
This counter will be reset by the drum reset pulse. This is not a
standard BCD counter because of the requirements that the high
order 4 bit stage count from 1 to 9 to 0 rather than 0 to 9. Also 0
in base 10 is represented by the bit pattern 1010. This counter is
also reset by the drum reset pulse. The relationship between the
values of each counter is illustrated in DMS Appendix III.
DAC ANGULAR INDEX COUNTERS ______________________________________
INTERLACE DECIMAL ADDRESS BINARY COUNTER BCD COUNTER
______________________________________ 0 5 00000000000000
0001101010101010 1 1 1 0001 2 2 10 0010 3 3 11 0011 4 4 100 0100 5
5 101 0101 6 1 110 0110 7 2 111 0111 8 3 1000 1000 9 4 1001 1001 10
5 1010 00011010 100 5 00000001100100 000110101010 1000 5
00001111101000 0010101010101010 9000 5 10001100101000
1010101010101010 10000 5 10011100010000 1011101010101010 10998 3
10101011110110 1011101010101000 0 4 00000000000000 0001101010101010
1 5 00000000000001 0001101010100001
______________________________________
DMS APPENDIX II
DMS INSTRUCTION REGISTER AND CPD DIRECTIVES ##SPC36##
OP = Bits 23 thru 20 = 7 = (0111).sub.2 PT = In WRITE DRUM
Sequence, the PT is meaningless. BM = Bit 18 -- if bit 18 is true a
block mark will be written on the drum along with the last word
transferred. LIMIT = Bits 0 thru 13 the limit portion of the
directives specifies the number of words to be read from core and
written on the drum. Bits = 14 thru 17 are not decoded or used
during this operation. Cycles = I + S + N (T) + ES + TERM/CORE
CYCLE TIME I = 45.4 .mu.sec = Initialize A = 0 to 16666 .mu.sec =
SEARCH N = number of words written/read T = 7.56 .mu.sec = TRANSFER
TIME PER WORD ES = 0 to 7.56 .mu.sec = END SEQUENCE TERM = 7.56
.mu.sec = TERMINATION
DRUM READ SINGLE LEVEL COUNTER START ##SPC37##
OP = Bits 23 thru 20 = 6 (0110).sub.2 PT = Bit 19 -- if bit 19 is
true the controller will assume a privileged transfer status for
the entire transfer. BM = Bit 18 -- if bit 18 is true the
controller will make a check for a block mark when the last word is
read from drum. If the bit is false this check will be bypassed. It
will check if BM comes true before LR = 0, or if LR = 0 and BM not
true. LIMIT = Bits 0 thru 13 the limit portion of the directive
specifies the number of words to be read from drum and transferred
to core. Bits 14 thru 17 are not decoded or used during this
operation Note: If PT is not set, the words may be transferred only
to an unprotected area in core. Any attempt to write a word from
drum to core when bit 25 of that word is a "1", will cause an error
and being error sequence. Refer to Drum Write for calculating core
cycle per task.
DRUM READ ROUTINE (SLCS) ##SPC38##
OP = Bits 23 thru 20 = 16.sub.8 = (1110).sub.2 BM = Bit 18 -- if
bit 18 is true the controller will make a check for a block mark
when the last word is read from drum. It will check if BM comes
true before LR = 0. If the bit is false this check will be
bypassed. LIMIT = Bits 0 thru 13 the limit portion of the directive
specifies the number of words to be read from drum and checked for
proper parity. Bits = 14 thru 17 are not decoded or used during
this operation. Note: Refer to Drum Write for calculating core
cycles per task.
SINGLE LEVEL ASSOCIATIVE SEARCH ##SPC39##
OP = Bits 23 thru 20 = 5 = (0101).sub.2 PT = Bit 19 -- if bit 19 is
true the controller will assume a privileged transfer status for
the entire transfer. INDEX = Bits 0 thru 13 the index portion of
the directive specifies the number of words to SKIP after
information coincidence until a transfer to core memory will begin.
LIMIT = Bits 14 thru 18 the limit portion of the directive
specifies the total number of words to be read from drum and
written into core. NOTE* Associative searching is performed in
interlace 1, every word is examined. After information coincidence
indexing and transfer will take place at the DCU interface rate.
CYCLES = I + S + T (N + 1) + ES + TERM/CORE CYCLE TIME I = 75.6
.mu.sec S = 0 to 16666 .mu.sec T = 7.56 .mu.sec N + 1 = Number of
words read + coincidence word ES = 0 to 7.56 .mu.sec TERM = 7.56
.mu.sec
SINGLE LEVEL ASSOCIATIVE SEARCH ROUTINE ##SPC40##
OP = Bits 23 thru 20 = (15).sub.8 = (1101).sub.2 INDEX = Bits 0
thru 13 the index portion of the directive specifies the number of
words to skip after information coincidence before the read latch
is set. LIMIT = Bits 14 thru 18 the limit portion of the directive
specifies the number of words to be read from drum with the read
latch set. NOTE: Refer to Single Level Associative Search for
calculating core cycles per task.
SINGLE LEVEL ASSOCIATIVE SEARCH COUNTER START ##SPC41##
OP = Bits 23 thru 20 = 4 = (0100).sub.2
Bit 23 = Routine all operations will be performed with the
exception of writing into core memory. NOTE* After counter
coincidence associative search will be performed at the DCU
interlace rate. CYCLES = I + S + 5 (S) + T (N + 1) + ES + TERM I =
75.6 .mu.sec. = INITIALIZE S = 0 to 16666 .mu.sec -- SEARCH N + 1 =
Number of words read + associative coincidence word. T = 7.56
.mu.sec = TRANSFER TIME PER WORD ES = 0 to 7.56 .mu.sec = END
SEQUENCE TERM = 7.56 .mu.sec = TERMINATION
MULTI-LEVEL ASSOCIATIVE SEARCH AND ROUTINE ##SPC42##
OP = Bits 23 thru 20 = 3 = (0011).sub.2 PT = Bit 19 -- if bit 19 is
true the controller will assume a protected status for the entire
transfer. A = Bit 14 -- if bit 14 is true the first level of search
will be a counter coincidence. If false it will be associative with
MR1 and SR1. B = Bit 15 -- if bit 15 is true the second level of
search will be a counter search. If false the search will be
associative with MR2 and SR2. C = Bit 16 --if bit 16 is true the
third level of search will be a counter search. If false the search
will be associative with MR3 and SR3. CS = Counter Start. If OP
code OP = 2 - (0010).sub.2 is true the first level of associative
search will begin after counter coincidence. Bits = 0-13 are not
used and not decoded. Bit 23 = Routine: All operations will be
performed with the exception of writing into core memory. NOTE*
Once the first coincidence is found all succeeding associative
searches and transfers take place at the DCU interlace rate. All
counter searches will be on interlace 1. CYCLES = LEV1 + LEV2 +
LEV3 + ES + TERM LEV 1 = I + S + N (T) if level 1 is a counter
start add the term 5(S) for searching an interlace five LEV 2&3
= if searching for associative coincidence = LD + W + S + N (T) ES
= - to 7.56 .mu.sec = END SEQUENCE TERM = 7.56 .mu.sec =
TERMINATION I = 136.2 .mu.sec = INITIALIZE S = 0 to 16666 .mu.sec
-- SEARCH N = number of words read T = 7.56 .mu.sec = TRANSFER TIME
PER WORD LD = 7.56 .mu.sec = LOAD DAR W = 0 to 15.0 .mu.sec = WAIT
FOR SEGMENT SELECTION
DCU DIRECTIVES AND FORMATS
The binary codes for the directives are summarized below. A more
elaborate description is found within.
INSTRUCTION REGISTER BITS 23 22 21 20 DIRECTIVE DESCRIPTION
______________________________________ 0 0 0 0 INVALID OP CODE 0 0
0 1 INVALID OP CODE 0 0 1 0 MULTI LEVEL ASSOCIATIVE SEARCH- COUNTER
START 0 0 1 1 MULTI LEVEL ASSOCIATIVE SEARCH 0 1 0 0 SINGLE LEVEL
ASSOCIATIVE SEARCH-COUNTER START 0 1 0 1 SINGLE LEVEL ASSOCIATIVE
SEARCH 0 1 1 0 READ DRUM -- BLOCK TRANSFER 0 1 1 1 WRITE DRUM --
BLOCK TRANSFER 1 0 0 0 INVALID OP CODE 1 0 0 1 DAC MAINTENANCE 1 0
1 0 MULTI LEVEL ASSOCIATIVE SEARCH- COUNTER START -- ROUTINE 1 0 1
1 MULTI LEVEL ASSOCIATIVE SEARCH -- ROUTINE 1 1 0 0 SINGLE LEVEL
ASSOCIATIVE SEARCH- COUNTER START --ROUTINE 1 1 0 1 SINGLE LEVEL
ASSOCIATIVE SEARCH-- ROUTINE 1 1 1 0 READ DRUM ROUTINE 1 1 1 1
INVALID OP CODE ______________________________________
DAC MAINTENANCE CONTROL ##SPC43##
Op = bits 23 thru 20 = 11 = (1001).sub.11
This code will routine the error checking circuits of the DAC. For
example, to check the PA circuits, bit 16 is set and any or all of
bits 0-4 are set to check the circuits which correspond to each
bit.
CPD CONTROL
The control between the CPU and DCU is as follows:
1. CPD Clear (DLO=0, DL1=0) 2. CPD Initialize (DL0=1, DL1=0) 3. CPD
Spill* (DL0=0, DL1=1) 4. CPD Maintenance** (DL0=1, DL1=1)
The DCU must receive a CPD Clear before any data transfer may be
executed via initialization.
At the completion of a data transfer or the completion of an Error
Termination Sequence, the DCU will interrupt the DCU with a READY
or ERROR interrupt respectively.
With the READY or ERROR interrupt set, the DCU may be called to
execute a CPD Spill, a DMS Maintenance Sequence, or a CPD
Maintenance The DCU will reset the interrupt upon execution of the
command, and then set the previous interrupt. Any attempt to
initialize for a data transfer (Block Transfer or Associative
Search) will begin an Error Termination sequence and cause an ERROR
interrupt. The DCU may be initialized for Maintenance, however.
This flow of DCU sequences is made clear by the attached flow
chart, FIG. 34. The chart shows the normal sequential flow of the
DCU for data transfers and errors. It also makes clear the
consequences of a programming violation.
*CPD Spill. The CPD spill directive dumps all the registers of the
DCU and CMS, and the error/status bits of the DMS.
The DAC error checking circuits may be routined by the DAC
Maintenance word via initialization.
**The DCU error checking circuits and the parity circuits may be
routined by the CPD Maintenance. This command causes the
instruction in the IR to be routined.
APPENDIX III
INITIALIZATION TABLE FORMAT
The initialization format is a map of the initialization area in
core. Each DCU has its own assigned initialization area in core.
The even numbered location 0-16 contain all the pertinent
information necessary to specify a drum task, refer to the
following table. After the DCU has completed initialization the odd
numbered location 1-17 will contain the image of their preceding
even location. This is to verify that the information was
accurately loaded into the DMS registers. If the drum task was
completed successfully, location 24 will contain the last CAR
address. If an error occurred, the error termination sequence will
load the DAC and DCU error/status words in locations 18, 20 and
22.
After a CPD spill directive the odd numbered loications 1-23 and
locations 18, 20, 22 and 24 will be updated with CPD spill format,
refer to the following table. ##SPC44## ##SPC45##
3.0 CHANNEL MULTIPLEXOR
3.1 introduction
3.1.1 operational Description
The Computer Channel Multiplex (CCX) provides communication paths
for I/O buses of the two CCP(S) up to sixteen controllers. Its
functions are:
A. route output data and control data from either CCP to any one of
sixteen controllers.
B. route input data from any one of the controllers to both CCP I/O
buses so that both CCP's may operate synchronously.
C. check and verify that output and control data is received by the
controllers and that controller parity checks are satisfied.
D. route I/O device controller interrupts and sense line data to
the Interrupt and Sense Line Circuits.
E. decode and store I/O controller selected.
F. check that only one Controller is selected at a time.
G. interpret Channel Multiplex CPD instructions such that
maintenance and reconfiguration may be performed on the CCX.
Except for the interface between the CCX and Controllers, the CCX
may be considered to have two identical halves. Each half is
associated with a CCP. The CCX operates on ACTIVE/STANDBY basis,
only half can be active at a time. Either half may be made active
only when its associated CCP is on line. Thus for synchronous
CCP(s) operations, either half, but not both, may be active. For
simplex CCP operations only the half associated with the on line
CCP can be active.
The interface between the CCX and the Controllers are powered by
two separate power modules: the odd numbered Controllers by one and
the even numbered Controllers by the other, such that a failure in
either power supply will not cause loss of all Controllers. (Note
that duplicated Controllers are assigned odd and even
identities).
3.1.2 Data and Instruction Format
There are three categories of instructions related to the CCX
operations:
1. SEL Directives
2. Data Transfer Instructions (LDC, CCD, STL, CCI)
3. ccx cpd instructions.
3.1.3.1 SEL Directives: (Refer to section 1.2 page 1.2-28)
These are I/O Command Words for assigning a Controller to the CCX
and/or a Device to the Controller. They are also used for sending
control codes to the Controller/Device assigned. Once a Controller
is assigned to the CCX, it will remain so until another Controller
is assigned to the CCX by a subsequent SEL instruction, a
Disconnect SEL instruction for that particular Controller, or a
CPDCX7 is executed.
The format of the I/O Command Word (which is the effective address
of the SEL instruction) is as follows: ##SPC46##
I -- arm I/O Ready Interrupt
C -- channel Controller Identity -- There can be a maximum of 16
controllers. The lower order bit of the C field (bit number 9) will
be used to specify the odd or even controller.
X -- x field -- The X field is used in conjunction with the Y &
Z fields to form a directive for the controller or peripheral
adapter. A value of zero for the X field specifies that the Y &
Z fields should be interpreted as controller directives. Non zero
values of the X field are used to specify a particular peripheral
adapter on a controller or as a directive extension. The X field is
only used for directive extension, when the Y & Z field
directives are exhausted or for maintenance.
Y -- y field -- The Y field is used as a directive modifier to the
Z field directive for both controller and peripheral adapter
directives.
Z --z field -- The Z field is used as a general directive field for
controllers and specific directive field for peripheral
adapters.
The Controller Codes are as follows:
C Field CONTROLLER NAME CONTROLLER NO.
______________________________________ 00 Channel Device Buffer A 1
01 Channel Device Buffer B 2 02 Ticketing Device Buffer A 3 03
Ticketing Device Buffer B 4 04 Maintenance Device Buffer 5 05
Channel Device Buffer 6 06 Communication Register A 7 07
Communication Register B 8
______________________________________
3.1.2.3 data Transfer Instructions: (Refer to section 1.2)
There are a total of nine CPD instructions related to the CCX:
Cpdcxo -- put CCXA On-line (017 00001)
Cpdcx1 -- put CCXB On-line (017 00002)
Cpdcx2 -- put CCXA Off-line (017 00004)
Cpdcx3 -- put CCXB Off-line (017 00010)
Cpdcx4 -- make CCXA Active and CCXB Standby (017 00020)
Cpdcx5 -- make CCXB Active and CCXA Standby (017 00040)
Cpdcx6 -- reset CCX Errors (017 00100)
Cpdcx7 -- initiate Select Storage Check Routine (017 00200)
Cpdcx8 -- end Select Storage Check Routine (017 00400)
CPDCX0 through CPDCX3 are for removing a faulty half of the CCX off
line for repair or putting a repaired half back to service.
CPDCX4 and CPDCX5 are for selecting which half of the CCX should be
active.
CPDCX6 is for resetting all CCX error conditions.
CPDCX7 and CPDCX8 are for routining the error checking circuitry in
the CCX. CPDCX7 informs the CCX that the following data
transmission should be gated to the Select Storage in the CCX. This
instruction will also disconnect any Controller from the CCX.
DPCDX8 terminates data output to be gated to the Select
Storage.
3.1.3 Status Indicators and Interrupt Stimuli
3.1.3.1 Select Error Check
This is a one out of sixteen check. It monitors the output of the
Channel Select Storage, which contains the Selected Channel
Controller Identity. Thus on a Select Instruction, if none or more
than one, controller is selected, this Select Error Check will flag
an error, (Sense Lines 74100 and/or 74200). This error will abort
the affect of the SEL instruction and the channel buffers will not
be initialized. In addition to the above, sense lines 07100 and/or
07200 will also be true.
The Channel Select Storage output is displayed on sense lines. (See
Section 3.1.4 for Group and Line Number). The error can be reset by
the execution of a RESET CCX ERROR (CPDCX6) instruction.
3.1.3.2 Time Out Error
This is used to check proper instruction and output data transfer
from the CCP through the CCX to the selected controller.
Specifically, upon receiving a select instruction or a data output
instruction, the selected controller will check the parity of the
information received. A Verify Strobe will be sent back to the CCX
signifying all is well. Failure to receive this Verify Strobe by
CCP timing period C1L2P2 of the next instruction will cause the CCX
to indicate an error (Sense Lines 07100 and/or 07200). The identity
of the selected controller that failed to return the Verify Strobe
is stored in the CXX and is available through the sense line. (See
Section 3.1.4 for Group & Line Number). All errors are reset by
CPDCX6 instruction.
______________________________________ 3.1.4 SENSE LINES Channel
Time Out (Group 47) ______________________________________ 57001
SCTOERR 1 Channel 1 Time Out Error 57002 SCTOERR 3 Channel 3 Time
Out Error 57004 SCTOERR 5 Channel 5 Time Out Error 57010 SCTOERR 7
Channel 7 Time Out Error 57020 SCTOERR 9 Channel 9 Time Out Error
57040 SCTOERR 11 Channel 11 Time Out Error 57100 SCTOERR 13 Channel
13 Time Out Error 57200 SCTOERR 15 Channel 15 Time Out Error
Channel Time Out (Group 49) ______________________________________
61001 SCTOERR 2 Channel 2 Time Out Error 61002 SCTOERR 4 Channel 4
Time Out Error 61004 SCTOERR 6 Channel 6 Time Out Error 61010
SCTOERR 8 Channel 8 Time Out Error 61020 SCTOERR 10 Channel 10 Time
Out Error 61040 SCTOERR 12 Channel 12 Time Out Error 61100 SCTOERR
14 Channel 14 Time Out Error Channel Selected (Group 50)
______________________________________ 62001 SCSELCT 1 1 Selected
62003 SCSELCT 3 3 Selected 62004 SCSELCT 5 5 Selected 62010 SCSELCT
7 7 Selected 62020 SCSELCT 9 9 Selected 62040 SCSELCT 11 11
Selected 62100 SCSELCT 13 13 Selected 62200 SCSELCT 15 15 Selected
Channel Selected (Group 51) ______________________________________
63001 SCSELCT 2 2 Selected 63002 SCSELCT 4 4 Selected 63004 SCSELCT
6 6 Selected 63010 SCSELCT 8 8 Selected 63020 SCSELCT 10 10
Selected 63040 SCSELCT 12 12 Selected 63100 SCSELCT 14 14 Selected
63200 SCSELCT 16 16 Selected
______________________________________
3.2 CHANNEL DEVICE BUFFER (CDB)
3.2.1 introduction
Maintenance and Support I/O Equipment is assigned to the CDB(s),
and consist of the Teletypewriters, Paper Tape Reader, Paper Tape
Punch, Line Printer and Card Reader. This equipment will have a
configuration as shown in Intro FIG. 7, in the EAX Engineering
Model. As seen in the figure, Controllers 1 & 2 are used as
duplicated Channel Device Buffers, that handle the teletypewriters,
a single Paper Tape Reader, and a Paper Tape Punch. The Line
Printer and Card Reader are assigned to a single controller (6).
The Maintenace TTY is equipped with Printing and Keyboard Entry
facilities only. Backup for the readers and punch is provided by
the Office Administration Teletypewriter which contains a low speed
reader and punch.
The primary purpose of the Channel Device Buffers (CDB) is to
function as a store and forward center for data and control between
the Central Processor and the external devices. The CP communicates
with the CDB and it subsequently communicates with the external
device through a Peripheral Adapter. A unique Peripheral Adapter is
provided for each I/O device. Its function is to provide an
interface between the CDB and the device. Each CDB can control a
maximum of four Peripheral Adapters.
With the configuration shown in FIG. 35 simultaneous operation of
the Channel Buffers can be accomplished. Example, the CP can
initiate a typeout on the Maintenance Typewriter and read tape from
the High Speed Reader.
3.2.2 Operational Description
3.2.2.1 Channel Device Buffer
The CDB stores and forwards information between the Central
Processor and the External devices. Thus all I/O "wait" operations
are between the CDB and its associated devices. The Central
Processor sends a command word via the Channel Multiplexer which
assigns the CDB to the I/O Channel and a device to the CDB. The
Channel Device Buffer then proceeds to perform the operation
specified by the command word.
3.2.2.2 Input/Output Command Word is the effective address of a SEL
instruction and is interpreted as follows: ##SPC47##
I = arm I/O Ready Interrupt (Refer to Section 3.2.2.5)
C = channel Buffer (function is performed by CCX, it defines which
Channel Buffer is being selected).
X = x field (defines which Peripheral Adapter has been
selected)
Y = y field (directive extension of the Z field)
Z = z field (directive to be performed)
3.2.2.3 Channel Device Buffer Directives
The C Field of the I/O Command Word is 00 when addressing the
Maintenance Teletypewriter or High Speed Punch. It is 01 when
addressing the Office Administration Teletypewriter or High Speed
Reader. The directives are stored and routed to the appropriate
Peripheral Adapter.
When the Channel Device Buffer is addressed, X Field -- 0.sub.8,
the Y and Z Fields are interpreted by the CDB as follows:
X Y Z DIRECTIVE ______________________________________ 0 0 0 Load
CDB Status --Places the CDB Status Lines into the CDB buffer. The
CP can now load the status into the CP by executing a STC or CCI
instruction. This directive does not destroy the previous status of
the X, Y and Z Fields. 0 0 1 Display Buffer -- Places the contents
of the CDB buffer register onto the I/O bus. This directive does
not destroy the previous selection stored in the X, Y and Z Fields.
This directive stays true until it is cleared by a CLEAR directive.
0 0 2 Not Used 0 0 3 Check 1 of 8 Circuits -- (Maintenance
Directive) Gates register bits 0-15 into the two 1 out of 8
circuits. During the following data output, a routining field is
loaded in the Buffer Register and a 1 out of 8 check is made on the
two circuits. If an error is detected the appropriate error
flip-flop is set. 0 0 4 Reset Errors -- All errors in the CDB and
its associated Peripheral Adapters are reset. 0 0 5 Off Line --
Places the CDB off-line 0 0 6 On Line -- Places the CDB on-line.
This is the only directive that will be recognized by the CDB when
it is off-line. 0 0 7 Clear and Disconnect -- Clears the CDB and
its associated Peripheral Adapters. In addition it disconnects
itself from the I/O bus. 0 1 7 Clear -- Clears the CDB and its
associated peripheral adapters. 0 2 7 Disconnect -- Disconnects the
CDB from the I/O bus. Contents of CDB and PA's are not cleared.
______________________________________
3.2.2.4 Status Lines
When the directive, Load CDB Status (000), is executed the
following status lines will be loaded into CDB buffer register. The
CP can then load them into the CP by executing a STC or CCI
instruction.
______________________________________ Buffer Bit STATUS LINE
______________________________________ 0 Loading Error -- If the CP
or the I/O Device attempts to transfer new data to the buffer
register before the old data has been removed, this error indicator
will be set. The old data in the buffer will not be changed. This
results in an Error Interrupt. 2 X Field One out of N Error None or
more than one Peripheral Adapter has recognized the last SEL
instruction or data transfer. 1 Z Field One out of N Error --
Either no directive or more than one has been decoded during the
last SEL instruction. 1 Z Field One out of N Error -- Either no
directive or more than one has been decoded during the last SEL
instruction. 3 Interrupt Armed -- Channel Device Buffer is armed
for Ready Interrupt. 7 Active -- The CDB Active flip-flop is set. 5
Device Error -- One of the 4 Peripheral Adapters has detected an
error. The PA Status Lines must be examined to determine what
caused the Device Error. This results in an Error Interrupt. 6
Parity Error -- If a parity error (even parity) exists on the data
transfer (SEL, LDC, or CCO), the Parity Error is set. If a parity
error exists, neither the directive or data will be forwarded to
the Peripheral Adapters. This results in a Channel Time Out Error
from the Channel Multiplexer. 4 GO Flip-Flop -- Indicates the
condition of the GO flip-flop. This indicator determines whether or
not directives and data are forwarded to the peripheral adapters. 8
Z Field=0 9 Z Field=1 10 Z Field=2 11 Z Field=3 12 Z Field=4 13 Z
Field=5 14 Z Field=6 15 Z Field=7 16 X Field=0 17 Z Field Ackn 1 --
The Acknowledge flip-flop in Peripheral Adapter No. 1. 18 X Field
Ackn 2 -- The Acknowledge flip-flop in Peripheral Adapter No. 2. 19
X Field Ackn 3 -- The Acknowledge flip-flop in Peripheral Adapter
No. 3. 20 X Field Ackn 4 -- The Acknowledge flip-flop in Peripheral
Adapter No. 4. 21 Y Field Bit 0 22 Y Field Bit 1 23 Y Field Bit 2
______________________________________
3.2.2.5 Channel Ready Signalling
The Channel Device Buffer Ready signal is the means used by the
Peripheral Adapters to indicate that they have completed the task
assigned to it by the CCP. It is specifically used to indicate that
the CDB buffer register is loaded or the peripheral adapter no
longer needs the data in the buffer register. This signal is
automatically reset during a Store, Load or Select (except CDB 1
out of n check) Channel operations.
The CDB Ready indicator is connected to the CCP via the Sense Line
inputs, Group 41 Line 0 for CDB-A and Group 42 Line 0 for
CDB-B.
The CDB Ready indicator may be armed for interrupt via bit 14 of
the effective operand of the SEL instruction. Once armed, the Ready
signals from the CDB's will create an interrupt, Level 7. When
armed for interrupt, only the CLEAR directives, 007 or 017, will
disarm the Ready interrupt.
3.2.2.6 CDB Error Signalling
The CDB Error indicator can be set by the CDB or by any selected
malfunction at any Peripheral Adapters. Errors which cause the
indicator are:
Loading Errors
X Field 1 out of N Error
Z Field 1 out of N Error
PA Device Error
Any one of the above errors will result in a Level 6 interrupt. The
error can be sensed via Sense Line inputs, Group 43 Line 0 for
CDB-A and Group 44 Line 0 for CDB-B.
Errors originating at the peripheral devices, PA Device Error, are
combined and transmitted to CDB by the respective Peripheral
Adapters. Appropriate status calls are executed to locate the
offending device. The offending CDB error; Loading Error, X Field 1
out of N Error or 2 Field 1 out of N Error; is determined by
executing the CDB directive, Load CDB Status (0,0,0) and testing
the appropriate bits.
If a Parity Error is detected in the CDB on a transmission from the
CCP (LDC, CCO or SEL) the Parity Error indicator is set. This does
not result in a CDB Error however, it will result in a Channel Time
Out Error. The Channel Time Out Error can be sensed via Group 47
Line 0 for CDB-A and Group 48 Line 0 for CDB-B. To determine if the
fault was a Parity Error the Status Lines of the CDB (Line 6) must
be examined.
All error signals; Loading Error, X Field 1 out of N Error, Z Field
1 out of N Error, PA Device Error and all errors originating at the
peripheral devices are reset either by a Reset Error directive
(004) or the Clear directive (007 or 017).
3.2.2 Teletypewriter Operation
3.2.3.1 Introduction
The System contains two teletypewriters, Maintenance (LMT) and
Office Administration (LOAT). The LMT is a Teletype Model 35 KSR
(Keyboard and Printer C Field = 00) while the LOAT is a Teletype
Model 35 ASR (Keyboard, Printer, Punch and Reader C Field = 01).
These devices operate at a maximum speed of 10 characters per
second. They accept and transmit ASCII code with even parity.
To operate the TTY with the CCP, the LINE LOCAL switch must be
turned to the ON LINE position. If the switch is in the LOC
position, the TTY will neither accept or transmit data to and from
the CP.
All data sent to and received from the TTY has the eighth channel
as an even parity bit. Only in the case where the mode Switch is in
the TTS or TTR positions can binary information be sent or
received.
3.2.3.2 Modes of Operation for Model 35 ASR
The Mode of Operation may be set up by operating the rotary mode
switch to the left of keyboard. The modes available are:
K Keyboard KT Keyboard Tape T Tape TTS Tape-Tape Send TTR Tape-Tape
Receive
3.2.3.2.1 K -- (Keyboard) Operation
The keyboard and typing unit are connected to the computer.
Transmission is provided from the keyboard to the CP and is
printed. The reader is disabled and the punch is placed in the
local circuit.
3.2.3.2.2 KT (Keyboard Tape) Operation
The keyboard, typing unit, reader and punch are connected to the
computer. When the reader is transmitting to the computer, the
information is copied by the typing unit and a duplicate tape is
punched. The keyboard should not be operated when the reader is
sending. When the keyboard is sending to the computer, the
information is copied by the typing unit and tape is punched. In
this case the reader should not be operated. LOC (local) operation
is the same except the unit is not connected to the computer.
3.2.3.2.3 T (Tape) Operation
The reader and typing unit are connected to the computer. The
typing unit copies what is being transmitted from the reader or
from the computer. The keyboard and punch are on the local circuit.
Tape can be prepared on the punch from the keyboard without
interfering with transmission to the computer. LOC operation will
be the same except the reader and typing unit are connected to the
local circuit.
3.2.3.2.4 TTS (Tape-Tape Send) Operation
The reader transmits data other than ASCII coded data to the
computer. The typing unit is blinded to outgoing and incoming
information. The keyboard and punch are connected to the local
circuit and can be used to prepare tape. This mode provides no
functional use in the LOC operation.
3.2.3.2.5 TTR (Tape-Tape Receive) Operation
The punch is connected to computer and can receive from it data
other than ASCII coded. The reader is disabled, the typing unit is
blinded and the keyboard is in the local circuit. This mode
provides no functional use in the LOC operation.
3.2.3.3 Modes of Operation For Model 35 KSR
The Teletype Model 35 KSR does not have any of the above (3.2.3.2)
modes of operation. To operate the KSR with the CP the LINE LOCAL
switch must be turned to the ON LINE position. This connects the
TTY to the computer. When the switch is in the LOCAL position, the
TTY is blinded from the computer however, the keyboard is connected
to the typing unit for local use.
3.2.3.4 TTY Interrupt Pushbutton
On each Teletype machine there is a Request for Input pushbutton.
This pushbutton is used to notify the computer program that the CP
should accept data from the keyboard. This pushbutton should be
kept depressed until the Ready to Receive Message lamp is lit. Once
the keyboard is enabled, the TTY peripheral adapter will accept all
information sent to it via the keyboard.
3.2.3.5 Teletype Directives
The effective address portion of the SEL instruction indicates the
Peripheral Adapter, X Field = 1 for both typewriters, and the
directive, Z Field.
______________________________________ X Y Z Field TTY Directive
______________________________________ 1 0 0 Present TTY Status --
Places the status lines from TTY Peripheral Adapter into the CDB
buffer. The CCP can now load them into the CCP executing a STC or
CCI instruction. 1 0 1 TTY Receive -- Alerts the Peripheral Adapter
that the next data transmission, LDC or CCO, is to be sent to the
Teletypewriter. 1 0 2 TTY Send -- Alerts the Peripheral Adapter to
send the next data transmission, LDC or CCO, to the TTY and then
monitor the incoming line and receives any characters sent via the
TTY keyboard or reader. ______________________________________
3.2.3.6 Status Lines
When the directive, Load TTY Status (100) is executed, the
following status lines will be loaded into the CDB buffer register.
The CCP can then load them into the CCP by executing a STC or CCI
instruction
Buffer Bit Status Line ______________________________________ 0
Shift Register Bit 2 1 do. Bit 3 2 do. Bit 4 3 do. Bit 5 4 do. Bit
6 5 do. Bit 7 6 do. Bit 8 7 do. Bit 9 8 do. Bit 10 9 do. Bit 11 10
do. Bit 0 11 do. Bit 1 12 Counter Decode = 0 13 do. =1 14 do. = 9
15 do. = 10 16 do. = 11 17 Record Start Pulse 18 Clock Enable 19
Counter Bit 3 20 Start Clock 21 Break Key 22 False Start 23 Paper
Alarm ______________________________________
Bits 21, 22 and 23 are error indicators; all the other status lines
are used for maintenance purposes.
3.2.3.7 Operation
The AC power to the Teletypewriter is turned on by placing the
Line/Local switch into the Line position. This switch should be
kept in this position as long as the TTY is on-line. The following
explanation assumes the Mode Switch is in the K position.
3.2.3.7.1 Print One Character
To print one character on the TTY a SEL instruction (X = 1, Y = 0,
Z = 1) must be executed. This directive alerts the TTY Peripheral
Adapter that the next computer data transfer to its associated
channel buffer (bits 0-7) will be printed on the Teletypewriter.
Once the TTY Adapter has been alerted, it need not be reinitialized
for each succeeding data transfer. When the character has been
printed, the Channel Device Buffer is notified and a Ready signal
(section 3.2.2.5) is sent to the computer. In order to keep the TTY
operating at its maximum speed of 10 characters per second, the
computer program must execute the next data transfer within 9
ms.
3.2.3.7.2 Punch One Character
To punch one character on tape the following sequence must be
followed:
Sel -- tty receive (101)
Ldc or CCO-DATA = TAPE ON -- 00000022
Wait for Ready
Ldc or CCO -- DATA = Data to be punched
The remaining characters to be punched can be outputted without
reselecting the TTY punch. When punching in the K position, the
information will also be printed on the TTY. To punch and not print
the mode switch must be in the TTR position. To turn the punch off,
the following sequence must be followed: SEL TTY RECEIVE (101)
Ldc or CCO -- DATA = TAPE OFF = 00000024
3.2.3.7.3 keyboard Entry
To enter information into the computer from the TTY keyboard, the
following procedure should be followed. The operator should notify
the computer program via the Request for Service pushbutton on the
TTY panel that he wishes to input from the keyboard. The program
will then execute the next sequence of instructions.
Sel tty send (102)
ldc or CCO -- DATA = LAMP ON 0000005
This data transfer lights the Ready to Receive Message lamp thus
notifying the operator that the keyboard information will now be
forwarded to the computer. This transfer of information is ASCII
coded with the 8th channel being the even parity bit. Whenever the
keyboard is used, a printed copy of the information is made on the
TTY.
When the keyboard operation is complete, the computer program must
reset the selection and extinguish the Ready to Receive Message
lamp by executing the following sequence of instructions:
Sel tty receive (101)
ldc or CCO -- DATA = LAMP OFF = 0000006
3.2.3.7.4 read Tape
The TTY paper tape reader has only one mode of operation that is
read slew. Reading tape in the slew mode allows the tape to run
until a stop character is recognized on tape. To initiate the
reading of tape, the following programming sequence must be
used.
Sel tty send (102)
ldc or CCO -- READER ON -- 00000021
The perper reader on the TTY will then read tape until the stop
character on the tape is recognized by TTY. This character is TTY
CODE DC1 (00000223). Following the tape off character, the TTY will
read a maximum of two additional characters. Thus if successive
records are on tape, a minimum of two delete characters should
separate them. These delete characters as long as the TTY SEND
directives is present.
3.2.3.8 Teletype Error Signalling
The TTY Peripheral Adapater recognizes three types of errors which
result in a PA1 Device Error. This device error ultimately results
in a CDB Error which notifies the computer of the error (see
Section 3.2.2.6).
3.2.3.8.1 Paper Error
When the TTY detects either of the two signals, out of print paper
or print paper jammed, the PA Device Error Signal is sent to the
CDB. This error does not detect an outage or jamming of the paper
tape. This error will stay set until paper error is corrected. Its
status can be determined via status line No. 23.
3.2.3.8.2 Break Key
This error is detected whenever the Break Key is depressed or when
an open line exists between the adapter and the teletype machine.
In the case of the break key, the error can be reset by either the
CLEAR or RESET ERROR directives. In the case of an open line, the
error will be reset by the above directives but will reappear after
a TTY SEND directive sequence is executed. The status of this error
can be sampled via status line No. 21.
3.2.3.8.3 False Start
When the adapter receives a short start pulse, this error will be
set. This results in a CDB Device Error. This error along with the
CDB Device Error will remain set until a CLEAR or RESET ERROR
directive is issued. This error can be sampled via status line No.
22.
3.2.4 PAPER TAPE READER
The High Speed Paper Tape Reader used in the EAX System is a
photoelectric reader capable of reading at rates up to 400
characters per second. Reading is in the 8 bit binary mode in which
all eight channels of the tape enter the computer as data bits. At
all times blank tape (leader) and rub outs (deletions) are read
into the computer. Prior to reading tape the AC power to the reader
must be manually turned on via a switch on the front of the reader
panel.
3.2.4.1 High Speed Paper Tape Reader Directives
The Controller Field (C Field) of the I/O Command Word is 01 when
addressing the High Speed Reader. The X, Y and Z Fields are stored
and decoded by the Channel Device Buffer (CDB) and routed to Paper
Tape Adapter number 2 (X field = 2). When Channel Device Buffer 01
is addressed, the X, Y and Z Fields are interpreted by the Paper
Tape Adapter for High Speed Reader as follows: X Y Z DIRECTIVE
______________________________________ 2 0 0 Load Paper Tape
Adapter Status -- Places the Paper Tape Status Lines into the CDB
Buffer. The CCP by executing a STC or CCI instruction. 2 0 4 Read
Slew -- Reads Tape continuously at a rate of 400 characters per
second. Stops when any other directive is selected on CDB 01 except
CDB directives 0 and 1. When stopping, there is a record gap
between records. 2 0 5 Read Step -- Reads one character from tape
and automatically resets the selection.
______________________________________
3.2.4.2 Status Lines
When the directive, Load Paper Tape Status (200) is executed the
following status line is loaded into the CDB buffer register. The
CCP can then load it into the CCP by executing a STC or CCI
instruction.
______________________________________ BUFFER BIT STATUS LINE 3
Reader On -- Indicates that the manual switch on the reader panel
is the LOAD or RUN position.
______________________________________
3.2.4.3 Operation
The Power switch located on the reader panel must be turned on
manually. This is a three position switch and its operation is as
follows:
Off -- This position indicates that the power is turned off in the
unit.
Load -- Indicates that the power is turned on however, the computer
cannot access the reader. This position should be used when loading
a new tape.
Run -- This position indicates the power is turned on and the unit
is capable of reading tape.
3.2.4.3.1 Read Slew
A paper tape read slew operation is initiated by a SEL instruction
(X = 2, Y = 0, Z = 4). Execution of this instruction causes the
tape to start moving. When the first character is read, it is
loaded into the CDB buffer register and the Ready indicator is set.
If the Ready Interrupt is armed, an interrupt is sent to the
computer. The tape will continue to advance until the directive is
removed (either by executing another SEL or by executing the Clear
directive).
The computer program has approximately 2 ms to remove the data from
the CDB buffer. If it is not removed the next character from tape
will be lost and a Loading Error signal will be generated by the
CDB.
When the reader is stopped (either by executing a different SEL or
by executing the Clear directive), the next character on tape is a
record gap. (One character will not be read.)
3.2.4.3.2 Read Step
A paper tape read step operation is initiated by a SEL instruction
(X = 2, Y = 0, Z = 5). Execution of this instruction causes the
reader to advance one character and stop. The character is loaded
into the CDB buffer and the signaling to computer is the same as
explained in Section 3.2.4.3.1.
3.2.5 HIGH SPEED PAPER TAPE PUNCH
The paper tape punch is capable of punching at rates up to 120
characters per second in either binary or parity check modes. The C
Field of the I/O Command Word is 00 when addressing the high speed
punch.
3.2.5.1 High Speed Paper Tape Punch Directives
When the C Field equals 00, the X, Y and Z Fields are stored and
decoded by the Channel Device Buffer and routed to Paper Tape
Adapter number 2 (X Field = 2). When CDB 00 is addressed, the X, Y
and Z fields are interpreted by the Paper Tape Adapter for the High
Speed Punch as follows.
______________________________________ X Y Z Directives
______________________________________ 2 0 0 Load Paper Tape
Adapter Status -- Places the Paper Tape Status Lines into the CDB
Buffer the CCP can now load the status into the CCP by executing a
STC or CCI instruction. 2 0 1 Turn Punch On -- this directive
applies the AC power to the punch. The Computer program should
allow 1 second for the motor to obtain its running speed. 2 0 6
Punch Binary -- Punches eight data bits from the computer into
tape. 2 0 7 Punch with Parity Check -- Punches seven data bits and
one parity bit from the computer into tape and checks them for even
______________________________________ parity.
3.2.5.2 Punch Status Lines
When the directive, Load Paper Tape Status (200) is executed the
following status lines are loaded into the CDB buffer register. The
CCP can then load it into the CCP by executing a STC or CCI
instruction.
______________________________________ Buffer Bit Status Line
______________________________________ 0 Parity Error -- An odd
number of holes was punched into the tape during a Punch with
Parity Check operation. 1 Low Tape -- The low tape signal will give
an indication when there is 50 feet .+-.20 feet of tape reamaining
on the supply reel. This will result in a PA2 Device Error thus a
CDB 00 Error. 2 Punch On -- Indicates that the AC power to the
punch has been applied. 4 DTL Stored -- This signal indicates that
the Data Transfer Level Stored Flip-Flop is set. (Used for
Maintenance). 5 End of Tape -- When there is less than inches of
tape remaining ahead of the punch head, this indicator will be
______________________________________ given.
3.2.5.3 Operation
The AC power must be turned on by executing a SEL instruction (X =
2, Y = 0, Z = 1). After waiting approximately 1 second for the
motor to obtain its rated speed, a delete character (all holes
punched) should be put on tape. Once the punch has been selected,
bits 0 through 7 of the I/O bus will be put on tape whenever a LDC
or CCO instruction is executed.
The AC power to the punch must be turned off via a Clear
directive.
3.2.5.3.1 Punch Binary
A paper tape punch binary operation is initiated by the execution
of a SEL instruction (X = 2, Y = 0, Z = 6). This directive alerts
the paper tape Peripheral Adapter that the next computer data
transfer (bits 0-7) will be punched into tape. Once the Peripheral
Adapter has been alerted, it need not be reinitialized for each
succeeding data transfer. When the character has been punched, the
Channel Device Buffer is notified and a Ready signal (see section
3.2.2.5) is sent to the computer. In order to keep the punch
operating at its maximum speed of 120 characters per second, the
computer program must execute the next data transfer within
approximately 8.33 ms.
3.2.5.3.2 Punch with Parity Check
To punch with a Parity Check a SEL instruction (X = 2, Y = 0, Z =
7) must be executed. The operation of this directive is identical
with that of section 3.2.5.3.1 with the following additions.
When punching with parity check, the eights bits transferred from
the CCP are checked for even parity after they are punched, an
error indicator, Parity Error, will cause a CDB error, Device
Error. When this error occurs, the tape is not advanced in the
punch. This error can then be rectified by deleting (punch all
holes) the character and repunching it. The error can be reset by
either the execution of a Clear directive a Reset Error
directive.
3.2.5.4 High Speed Punch Error Signalling
The high speed punch has three Device Errors (parity, low tape, end
of tape).
3.2.5.4.1 Parity Error
When punching with parity check (X = 2, Y = 0, Z = 7) and an odd
number of holes are punched into the tape, the Parity Error will be
set. This results in a CDB Device Error. This error will stay set,
along with Device Errors in the CDB, until a Clear or Reset Error
directive is executed.
3.2.5.4.2 Low Tape
When there is 50 feet .+-. 20 feet of tape remaining on the supply
reel, a low tape error signal will be generated that results in a
CDB Device Error. This error signal will only interrupt when the AC
power is turned on to the punch. However, it will always be
available as a status line (bit 1). It can only be reset by placing
a new role of tape on the supply reel.
3.2.5.4.3 End of Tape
An end of tape signal will be given when there is less than 2
inches of tape remaining ahead of the punch head. This error
results in a CDB Device Error whenever the AC power is turned on to
the punch. It will always be available as a Status line (bit 5). It
can only be reset by rethreading the tape through the punch
head.
Section 3.3 communication registers
3.3.1 introduction
the Communication Registers provide the media by which the Central
Processors can communicate with the Originating and Terminating
markers. For normal Call processing, the Originating marker
transmits the equipment identity of junctors selected by the OM to
the Central Processor. This is one way communication. The
communication between the Central Processor and the Terminating
Marker is two way in that the CCP sends the routing information to
the TM and the TM responds with the results of the termination
attempt.
Each originating and Terminating Marker is equipped with a single
Communication Register (MCR) for communicating with the Data
Processor. The Data Processor is equipped with a pair of CRs
operated in an active -- standby configuration. The single CR in
each marker and the active CR in the DP will be used to transfer
call processing, metering, routining, and maintenance information
between these subsystems.
The maximum system configuration, two office sections and a
selector section, utilize a maximum of 14 markers. The constraints
on the maximum number of Markers in an office section or selector
section are as follows:
Each Office Section 2 OM Pairs (2 Sections) 1 TM Pair Selector
Section 3 OM Pairs 1 TM Pair
The constraint on the number of TM pairs for a maximum size system
is three, one pair for each section. The constraint on the number
of OM pairs for a maximum size system is four pairs. This amounts
to a maximum of eight individual Originating Markers and 6
individual Terminating Markers. Each Originating Marker and its
duplicate can process different calls simultaneously as long as the
calls are in different line or trunk register group matrices. The
Termination Marker cannot be operated simultaneously because of a
common data bus between a pair of TMs and the trunk and junctor
they control. Therefore, each TM of a pair will be operating on an
alternating basis. Based on the above the maximum number of markers
that can be in operation at any one time is 11 (8 OMs and 3
TMs).
The on-line - standby status (configuration) of the two CRs in the
Data Processor is under program control. Either CR can be put into
either status by means of Select Directives (see section 3.3.2). An
on-line CR in the CP scans all the markers in the office for calls
for service for transmission to the DP. It is up to the program to
determine which DR is on-line when a transmission to one of the
markers is required.
3.3.2 COMMUNICATION REGISTER OPERATIONAL/DESCRIPTION
3.3.2.1 description of CR Data Register Formal
The format of each of the four data registers in the CR controller
is as follows: ##SPC48##
Data -- This 24 bit field is used to hold the data for a
transmission.
P -- parity bit -- This bit contains the parity of the data field
and the CB field. The parity for the 26 bit word is odd.
Mp -- memory Protect bit - This bit is used to provide an even
number of bits for the register. This bit is set = 0 by the CR
controller on sending and set = 0 at the MCR when it is
sending.
The order of the registers to provide a 106 bit shift register is
as follows: ##SPC49##
3.3.2.2 Communication Register Control Directives
1. Select Command Format --
The DPU will use a Select (SEL) instruction with its associated I/O
Command Word (effective address of SEL instruction) for directing
the functions of the Communication Register (CR). The CR will use
the standard controller I/O Command Word format as described below:
##SPC50##
I -- arm I/O Ready Interrupt
C -- channel Controller Identity -- This field is used to specify
one of 16 controllers to be addressed.
Communication Register A = 06, Communication Register = 07
X -- - x field -- This field will not be used for the CR controller
and should always be set equal to zero.
Y -- y field -- The Y field is used as a directive modifier to the
Z field.
Z -- z field -- The Z field is used as a general directive.
2. Description of Directives
The Y & Z field directive codes for the CR controller are
defined below:
Z = 0 display Status - Causes the status group specified by Y to be
gated to the I/O bus. If this directive is followed by a STC or CCI
instruction, the status word will be stored in memory or the A
register.
Y = 0 standard Status Word & Arm Scanner Loading
Y = 1 error Status Word 1
Y = 2 error Status Word 2
Y = 3 - 7 spare
This directive also causes the CR to "lock" in its present status.
If sending or receiving it will continue to do so. If scanning, the
CR will stop scanning and will not recognize any call for service
while the status is selected. The status will be "unlocked" by a
Disconnect or Clear Controller directive (Z = 7, Y = 0 or 2) or a
Send Directive (Z = 2, Y = 0, 1, 2, or 3).
Z = 1 display Buffer - Causes the buffer specified by the Y field
to be gated to the I/O bus. This directive also causes the buffer
specified by the Y field to be primed for loading. Therefore if
this directive is followed by a STC or CCI instruction, the
contents of the specified controller buffer will be stored in
memory or the A register. If this directive is followed by a LDC or
CCO instruction, the buffer in the controller will be loaded from
memory or the A register.
Y = 0 data Register 0
Y = 1 data Register 1
Y = 2 data Register 2
Y = 3 data Register 3
Y = 4 - 7 spare
Z = 2 interrupt Control -- Based on the value of the Y field the CR
can be directed to either interrupt or go into the "Idle and
Scanning State" after a successful send operation. The CR will
always interrupt if the send operation is unsuccessful.
Y = 0 -- interrupt after Sending -- The CR will maintain this state
until an Inhibit Interrupt direction (Z = 2, Y = 1) is
received.
Y = 1 -- inhibit Interrupts (after sending), -- The CR will
maintain this state until an Interrupt after Sending directive (Z =
2, Y = 0) is received.
Z = 3 send Control -- Causes the CR to send the message stored in
the shift register over the link whose address is stored in the
Address Register in one of four modes, send two or four words
normally or send two or four words in a special mode where the
message is returned as sent. Each Send directive will reset the CR
interrupt if set.
Y = 0 -- send 2 -- causes two words to be sent in the normal
mode.
Y = 1 -- send 4 -- causes four words to be sent in the normal
mode.
Y = 2 -- send 2 prime -- causes two words to be sent in the special
mode that causes the message to be returned as sent.
Y = 3 -- send 4 prime -- causes four words to be sent in the
special mode that causes the message to be returned as sent.
Z = 4 reset I/O Errors -- Causes the CR Controller to reset all
errors and the controller error interrupt.
Z = 5 take Controller Off-Line or Enable Automatic Reset on Time
Out Error on Receiving.
Y = 0 -- take Controller Off-Line -- Causes the Controller to be
taken off line and inhibits the controller from any further access
of the DP, namely, error and ready interrupts and gating to the I/O
bus.
Y = 1 -- enable Automatic Reset on Time Out state where it will
automatically reset itself and return to the idle and scanning
state without causing an error interrupt if a time out error occurs
while receiving. The controller will retain this state until a Z6 -
Y3 directive is issued.
Z = 6 -- put Controller On-Line or Inhibit Automatic Reset on Time
Out Errors in Receive Mode - Causes the Controller to be put in an
on-line (active or standby) condition or in a state where time out
errors during receiving will cause an error interrupt. The action
to be taken is based on the Y value.
Y = 0 -- operative Active -- Causes the CR to scan all data links
for calls for service. The CR will maintain this state until an
Operate Standby (Z = 6, Y = 1) or a Take Controller Off-Line
directive is received.
Y = 1 -- operate Standby -- Causes the CR to scan only the data
link call for service from the other CR. While in this state, the
CR can be directed to send a message over any idle data link. The
CR will maintain this state until an Operate Active (Z = 6, Y = 0)
or Take Controller Off-Line directive is received.
Y = 2 -- inhibit Automatic Reset on Time Out Errors while receiving
-- causes CCR to be put in state where it will cause an error
interrupt if a time out error occurs while in the receiving mode.
In this state the CCR will not reset itself. It will remain in this
state until a Z5-Y1 directive is issued.
Z = 7 controller Disconnect and Clear Based on the Y field, this
directive either clears or disconnect the controller or does
both.
Y = 0 -- disconnect and Clear the Controller - Resets and clears
all stored directives, errors, and interrupts at the CR controller.
The CR controller is also disconnected from the I/O bus. If the CR
controller is in the On-line, Active state, this directive puts the
controller in the "Idle and Scanning State".
Y = 1 -- clear Controller - Resets and clears all stored
directives, errors, and interrupts at the CR controller. The CR
remains in a Selected state.
Y = 2 -- disconnect Controller - Disconnect the CR controller from
the I/O bus. Except for resetting the Selected Status State, and
disconnection from the I/O bus, this directive has no other affect
on the controller.
Y = 3 -- master Reset -- Reset shift register and serial
transmission control, initialize scanner, and perform functions
associated with "Clear Controller" (Z = 7, Y = 1).
3.3.2.3 status and Address Word Format and Description
The format and definition of each bit or field in the two status
words and the address word are given below.
______________________________________ 1) Controller Status Word
Bit Position Mnemonic Description
______________________________________ 0-4 ASO Address Scanner
output -- indicates data link being scanned, 0 to 31. 5 IAS A 1
indicates that the state of the CR is Idle and Scanning. 6 SEN A 1
indicates that the CR is sending a message. 7 REC A 1 indicates
that the CR is receiving a message. 8 SES A 1 indicates that the CR
has sent a message successfully. 9 RES A 1 indicates that the CR
has received a message successfully. 10 ERS A 1 indicates that the
CR has sent a message with an error being detected. 11 ERR A 1
indicates that the CR has received a message with an error being
detected. 12 SST A 1 indicates that the CR is in the Operating Full
Scan state. A 0 indicates that the CR is in the Operate Standby
state. 13 INS A 1 indicates that the CR will interrupt the DP after
each message is sent successfully. A 0 indicates that the CR will
not interrupt the DP after each message is sent successfully. 14
MGT A 1 indicates that the data link being scanned requires a four
word message. A 0 indicates that the data link being scanned
requires a two word message. 15 CRI A 1 indicates the CR interrupt
flip-flop is set. 16 DB0 A 1 indicates that the 25th data bit of
word 0 is a 1. 17 DB1 A 1 indicates that the 25th data bit of word
1 is a 1. 18 DB2 A 1 indicates that the 25th data bit of word 2 is
a 1. 19 DB3 A 1 indicates that the 25th data bit of word 3 is a 1.
20-23 Spare = 0 2) Error Status Word 0 RPO A 1 indicates that word
0 was received with bad parity. (By either the CR or the MCR). 1
RP1 A 1 indicates that word 1 was received with bad parity. 2 RP2 A
1 indicates that word 2 was received with bad parity. 3 RP3 A 1
indicates that word 3 was received with bad parity. 4 ES0 A 1
indicates that bad shifting was detected in word 0's shift
register. 5 ES1 A 1 indicates that bad shifting was detected in
word 1's shift register. 6 ES2 A 1 indicates that bad shifting was
detected in word 2's shift register. 7 ES3 A 1 indicates that bad
shifting was detected in word 3's shift register. 8 SP0 A 1
indicates that the CR detected bad parity while sending word 0. 9
SP1 A 1 indicates that the CR detected bad parity while sending
word 1. 10 SP2 A 1 indicates that the CR detected bad parity while
sending word 2. 11 SP3 A 1 indicates that the CR detected bad
parity while sending word 3. 12 PER A 1 indicates that a message
was received by either the CR or an MCR with bad parity. 13 SER A 1
indicates that a message was received by either the CR or an MCR
and bad shifting was detected. 14 PES A 1 indicates that the CR
detected bad parity while sending a message. 15 DLE A 1 indicates
improper responses over data link. 16 PB1 Indicates the status of
the 1st prefix bit register. 17 PE2 Indicates the status of the 2nd
prefix bit register. 18 LSC This bit indicates the current status
of the "data" lead of the data link. 19 LSC This bit indicates the
current status of the "clock" lead of the data link. 20-22 DLS
These three coded bits indicate the status of three remaining
status leads of the data line. DLS is coded as follows: DLS = 0
Idle 1 Spare 2 Good Message Received 3 Acknowledge 4 Bad Message
Received 5 Call for service prime 6 Call for service 7 Spare 23 LOS
A 1 indicates the link for the unit whose address is stored in the
address register in the lockout condition. 3) The Address Word
(from the DP to the CR) 0-4 ASI Input to the Address Scanner --
Indicates data link to be scanned, O-31. 5 PF1 A 0 causes a 1 to be
the first bit of the prefix bit. A 1 causes a 0 to be the first of
prefix bits. 6 PF2 A 0 causes a 0 to be the second bit of the
prefix bits. A 1 causes a 1 to be the second prefix bit. 7-23 Spare
= 0 ______________________________________
3.3.2.4 Scanning, DP Selection of the CR, and CR interrupts. The CR
can be put in one of three major states listed below by means of
the Select instructions described in section 3.3.2.2.
Off-Line -- State in which the CR is not in a condition to be put
in service due to a fault or other maintenance reasons.
On-Line, Standby -- State in which the CR is ready to be put into
service. In this state, the CR is scanning only the call for
service request from the duplicate (active CR).
On-Line, Active -- State in which the CR is scanning the call for
service leads from the Markers or is in the process of being used
for a transmission (to or from the Marker).
When the CR is in this last state, it can be seized by the Markers
for a transmission to the DP. Since the on-line active CR can also
be seized by the DP for a transmission to the Markers, a scanning
interlock is required. This interlock is achieved by stopping the
scanner in the CR and inhibiting all Marker call for service
requests from being recognized whenever the CR receives a select
(SEL) instruction with a Display Status directive, from the DP. The
CR will maintain this state until a Disconnect, Disconnect and
Clear, or one of the four Send directives is received. Since the CR
can be in the process of causing an interrupt (receive or send
complete), the interrupt should be disabled when the CR is selected
to determine its idle/busy status. If the CR is found idle, the
interrupts can be enabled and the loading process can be initiated.
If the CR is found busy the CR should be "unlocked" via a
Disconnect directive prior to enabling the interrupts. The use of
the above procedure for obtaining an idle CR for sending a frame to
an Originating or Terminating Marker is described below.
1. Sending a Frame to the Originating Marker
The communication between the OM and the DP is normally a one way
transmission from the OM to the DP. Communication from the DP to
the OM is only needed for equipment routining (junctors, lines,
etc.), marker routining and diagnostics, and marker directives (on
line/off line, etc.). To communicate with a particular OM, the DP
must select the CR when the CR is idle and the OM is either idle or
in trouble. If the marker is in trouble and the CR is idle when
selected, the CR loading process can be started. If the marker is
in trouble and the CR is busy when selected, the next CR interrupt
(send or receive complete) can be used to initiate the CR loading
process for sending. If however, the marker is idle or busy (non
trouble condition), the CPD directive STANDBY (Refer to section
8.5-10) can be processed. This directive will place a selected
marker in the standby condition when it enters the idle state. In
the standby condition the OM will not assign a CFS from a matrix,
and will set the standby interrupt/sense line true to alert the
Central Processor.
2. Sending a Communication Frame to the Terminating Marker.
The Terminating Marker differs from the Originating Marker in the
way it receives a task to perform. The TM only performs tasks
conveyed to it by the DP via the CR i.e. it never goes out of idle
on its own. Also since the TM returns the results of the
termination attempt (just prior to going idle) to the DP via the
CR, the DP always has an indication of when the TM goes idle.
Therefore the DP can use the interrupt from the CR to service the
Terminating Marker queue(s). However if the TM and CR are both idle
the frame for the TM can be loaded into the CR without waiting for
the CR interrupt.
The above procedure can be used for all types of communication
frames i.e. call processing, maintenance, routining, etc.
3.3.2.5 Receiving Sequence
The CR in the DPU is put into the receiving mode whenever the
scanner stops on a call for service signal from one of the markers.
The steps in the sequence after a request has been observed are as
follows:
1. The CR returns an "acknowledge" signal to the marker.
2. When the MCR in the marker observes the "acknowledge" signal, it
starts sending the information using serial transmission.
3. As each 26 bit word is shifted out of the MCR, a parity bit is
generated and added to the frame of information to make up the 26th
bit.
4. As each 26 bit word is shifted into the CR in the DPU, the word
is checked for correct parity.
5. After two or four words (frames from OM and TM respectively) are
received and the parity is correct for each word, the CR interrupts
the DPU for unloading. The CR also returns a "Good Message
Received" signal to the MCR.
6. after the DPU acknowledges the interrupt, the call processing
status word and two or four data words are stored in core memory
via Select and Store Channel Commands.
7. When the data is stored in memory, the DPU can either disconnect
the CR and put it into the "idle and scanning" state or reset the
CR and go into the loading sequence for sending a frame to one of
the markers.
8. If in sequence 6, the call processing status word indicated
trouble, the error status word would be retrieved via Select and
Store Channel Commands. The CR will automatically return a "bad
message receive" signal to the MCR. The MCR upon observing the
signal, will make a second "call for service" to the CR.
9. the DPU must put the CR in an idle and scanning state (via
Select command) to enable the scanner to observe the second call
for service signal from the Marker. By loading the address word
with the correct address (Add-1) prior to disconnecting the CR, the
DPU can force the CR to observe the second call for service signal
from the original marker before scanning any other MCR
requests.
10. If the second transmission is error free, the original problem
will be considered an error and the operation will proceed to
sequence (6).
11. If the second transmission also has error(s), the CR will again
send a "bad message received" signal to the MCR. This time,
however, the MCR will not make another call for service to the
CR.
3.3.2.6 sending Sequence
The sending sequence can be entered from the receive sequence or by
selecting the CR and finding it in the idle and scanning state. If
the CR is not in the idle and scanning state when selected, the DPU
must wait for the next interrupt (receive or send complete) before
entering the sending sequence. Once entered, the sending sequence
is as follows.
1. The address word and two or four data words (depending on
whether the frame is for the OM or TM respectively) are loading
into the registers of the CR via Select and Load Channel
commands.
2. Following a Select Command (Send), the CR will make a "call for
service" to the MCR specified by the address word.
3. The MCR will return an "Acknowledge" signal and the CR will
begin the serial transmission. As each 26 bit word, is shifted out
of the shift register, the parity for the word is checked against
the parity generated by the DPU. Any errors detected during the
transmission will be stored and the transmission will be allowed to
continue until completion. Following the transmission, the DPU will
be interrupt if an error is stored.
4. As the information is received in the MCR, each 26 bit word is
checked for correct parity. If parity is correct for all words
received, and no other errors have occurred, the MCR will return a
"Good Message Received" signal to the CR. If errors are detected in
the MCR, it will return a "Bad Message Received" signal to the CR.
For the second case see sequence 7.
5. the Following a "Good Message Received" signal from the MCR the
CR will either go into the "Idle and Scanning" state or interrupt
the DPU. The DPU can control the action taken by the CR with a
Select Command (Interrupt After Sending directive).
6. If the CR is set to interrupt after successful sending, the DPU
can either disconnect the CR or reenter the sending sequence.
7. If errors are detected in sequence 3 or 4, the DPU can initiate
a retrial. This consists of resetting the CR with a Select Command
before going to sequence 1.
8. If the retrial is successful, the original problem is considered
an error. If the retrial is not successful the Communication
Register fault isolation program will be called.
3.3.2.7 Holding Time of the CR
The holding time for the Communication Register includes the
loading or unloading time in the DP, the send transmission time,
and the overhaul time in the marker. The holding time will differ
based on whether the transmission is involved with an Originating
or Terminating Marker. Since the communication frame for the OM is
one half the size of the frame for the TM, the holding time for the
CR involving the OM is one-half that involving the T. The holding
time for these cases is given below:
A) Transmission with OM 1) DP load or unload commands 50 .mu.s 2)
Transmission Time: 208 .mu.s 52 bits at 250 KC 3) Marker &
Signaling 20 .mu.s Overhead B) Transmission with TM 1) DP load or
unload 70 .mu.s Commands 2) Transmission Time 416 .mu.s 104 bits at
250 KC 3) Marker & Signaling 20 .mu.s Overhead Total 506
.mu.s
The loading or unloading time stated for the DP assumes no
interrupts during the loading or unloading sequence. Also for
loading the CR, it is assumed that the three or five words to be
loaded into the CR are preformatted and are stored in a three or
five word table prior to selecting the CR.
3.3.2.8 communication Register Maintenance
A. cr error Detection -- There are two error interrupts which are
directly associated with the CR. The first is the error interrupt
from the Channel Multiplex circuit. This interrupt will indicate a
parity error on loading the CR or any other failure which would
cause the CR not to return an acknowledge to the Channel Multiplex.
The second type of error is that received from the CR controller.
The different types of errors which are included in CR controller
error are listed in section 3.3.2 under Controller and Error Status
Words. A summary of these errors is given below:
1. Parity error indication for each word for both sending and
receiving.
2. Shifting error indication for each word.
3. Data link-error.
4. Parity Error indication from the source or sink of the
transmission.
B. cr routining -- There are two dynamic routines provided for CR
fault isolation and localization. The first routine consists of
sending a frame to a marker and instructing the MCR in the marker
to return the message as received. This can be accomplished in one
of two ways.
1. Issue a Send 2 Prime or Send 4 Prime directive rather than the
normal Send 2 or Send 4 directive.
2. Set the instruction field (INT or INO) of word 0 of either the
terminating or originating frame to zero.
Method 1 involves only the CR in the DP and the MCR in the Marker
whereas the second method involves the instruction decoding and
sending sequence control of the marker.
The second type of CR routine consists of sending a two or four
word frame from the on-line active CR in the DP to the duplicate
on-line standby CR. The two CRs in the DP can be put into the above
state with Select directives. The routine is set up by loading the
address scanner in the on-line CR with the address of the standby
CR. Based on whether the routine is for checking a two or four word
transmission, one of two procedures will be followed:
1. Two Word Transmission Routine
a. Two Words are loaded into data register 0 & 1.
b. A Send 2 Prime directive is given.
2. Four Word Transmission Routine
a. Four Words are loaded into the 4 data registers.
b. A Send 4 directive is given.
3.3.3 MARKER OPERATION
3.3.3.1 data Interface with Originating Marker
A. description of Originating Marker Communication Frames.
The frame of information which is transmitted via the CR between
the Data Processor and the Originating Marker consist of two data
words (48 data bits) two parity bits, and two other error detection
bits. Included in the two data words are the following groups of
data.
Line Group Originations
1. Control Data and Marker Identity
2. Line Number Identity
3. Matrix Identity of Originating Junctor (OJ)
4. matrix Identity of Register Junctor (RJ)
Trunk Group Originating
1. Control Data and Marker Identity
2. Trunk Number Identity
3. Matrix Identity of RJ
As described in section 3.3.2 the interface with the OM for call
processing and metering consists of a single two word transmission
from the OM to the DP. There is no response to the OM other than
the "message received OK" signal returned by the hardware. The only
case where the DP transmits a message to the OM (Via the CR) is for
maintenance or routining. Given below are the format and
description of the Originating Marker Communication Frame.
1. Data Word 0 -- Data word zero is the control and Marker identity
word for the total frame of information. The format of this word is
similar to the format of data word 0 for the Terminating Marker
communication frame. ##SPC51##
Sbs -- subsection
1. Bit Position -- 2-3
2. Valid Range -- 0-3
3. Description -- This field specifies the type of marker and if
there is more than one marker in a section, the subsection. This
field, along with SEC & MID specifies a unique marker.
4. Value
Sbs = 0 terminating Subsection
Sbs = 1,2,3 originating Subsection 1, 2, 3 respectively
Mid -- marker Identity
1. Bit Position -- 4
2. Valid Range -- 0-1
3. Description -- This bit indicates which marker of a given pair
specified by SEC & SBS) is involved in the origination.
4. Value
Mid = 0 marker A
Mid = 1 marker B
Mtn - maintenance Call
1. Bit Position -- 5
2. Valid Range -- 0-1
3. Description -- This bit indicates whether the frame should be
interpreted as call processing or maintenance information.
4. Value
Mtn = 0 -- call Processing or test call
Mtn = 1 -- maintenance request or command
Tcl - test Call
1. Bit Position -- 6
2. Valid Range -- 0-1
3. Description -- This bit is used to indicate a test call on the
return frame from the OM.
4. value
Tcl = 0 standard Call
Tcl = 1 test Call
Ino - instruction (Originating Marker)
1. Bit Position -- 7-11
2. Valid Range -- 0-31
3. Description -- When MTN = 0, this field is used by the DP to
specify the type of action to be taken in the processing of test
origination.
4. Value -- When MTN = 1, this field is used for maintenance
instruction (See Section VI). The values below one for the normal
case with MTN = 0.
Ino = 0 mcr test -- no call processing is performed, but the MCR
will immediately return the data frame exactly as received.
Ino = 1 no pull -- this is a special call in which an inlet CFS is
simulated and the selected or requested matrix path is not pulled,
but a multiple path check is made. The test call is stopped at this
point and a special call status is returned indicating the test
call was successful. The TCL byte must always be set for this
call.
Ino = 2 pull -- this special call simulates an inlet CFS and
completes the test call to the selected or requested matrix outlet.
On response will be returned at end of call was successfully
completed. The TCL byte must always be set for this call.
Ino = 3 wire chief origination -- the path is completed from a
specific matrix inlet even if the line is busy.
Ino = 4-31 spare
Bun - b unit
1. Bit Position -- 16-19
2. Valid Range -- 0-10
3. Description -- This field specifies which of 10 matrix B units
for a given AB group was involved in the origination.
4. Value -- BUN = 0 Used for test calls only. As blank BUN field
indicates that no specific B unit is required for the test
call.
BUN - 1 - 10 Regular B units
Cso - call Status (originating)
1. Bit Position -- 20-23
2. Valid Range -- 1-15
3. Description -- This field is used to indicate the outcome of an
originating marker attempt to process on origination.
4. Value
Ocs = 1 normal LN1 or TN 1 message
Ocs = 2 all AB Link busy
Ocs = 3 all RJ's busy
Ocs = 4 path busy
Sec - office Section
1. Bit Position -- 0-1
2. Valid Range -- 1-3
3. Description -- This field of the LNI or TNI specifies which
office section was involved in the origination. LNIs can only be
associated with office sections 1 and 2 while TNIs can be
associated with all three sections.
4. Value
Sec = 1 office Section No. 1
Sec = 2 office Section No. 2
2. Data Word 1 - Data Word 1 contains the line or trunk number
identification (LNI or TNI) and matrix information for identifying
the selected Originating Junctor (Line originations only) and
Register Junctor. The LNI or TNI includes all the fields from bit
position 6 to 23 of Data Word 1.
MTX ABG AUN AUI RUO BUO 23 22 21 18 17 15 14 11 10 6 5 3 2 0
Buo -- b unit Outlet
1. Bit Position -- 0-2
2. Valid Range -- 0-4
3. Description -- This field specifies the outlet at the B unit
that was selected for the origination.
4. Value -- BUO = 0 Used only for test calls. BUO = 0 indicates
that no B unit outlet is being specified.
BUO = 1 - 4 Regular B Unit outlets
Ruo - line Matrix R Unit Outlet
1. Bit Position -- 3-5
2. Valid Range -- 0-6
3. Description -- For line originations, this field specifies which
outlet on the Line Matrix R unit was selected. The R unit is not
specified in the frame directly because it is identical to the B
Unit Outlet (BUO). For trunk originations this field is blank.
4. Value -- RUO = 0 For test calls, it indicates that no R unit
outlet is specified. For a RUO = 1-5 Regular Line Matrix R unit
Outlets
Aui - a unit Inlet
1. Bit Position -- 6-10
2. Valid Range -- 1-20
3. Description -- The AUI field of the LNI or TNI specifies which
of the 20 inlets of the A unit was identified in the
origination.
4. Value
Aui = 0 invalid AUI = 1-20 Regular A Unit inlet
Aun - a unit
2. Bit Position -- 11-14
2. Valid Range -- 1-10
3. Description -- This field of the LNI or TNI specifies which of
the 10 A Units of the Line Matrix was identified during the
origination.
4. Value -- AUN = 1-10 Regular A Units
Abg - ab group
1. Bit Bosition -- 15-17
2. Valid Range -- 1-6
3. Description -- This field of the LNI or TNI specifies which of
the 200 line AB group was identified during the origination. This
field also indicates if the origination is associated with a line
or trunk B register matrix.
4. Value -- ABG -- 1-5 Regular Line AB groups (LNI)
6 indicates a Trunk Register Matrix Identity (TNI)
7 invalid
Mtx - matrix (Line Group or Trunk Register)
1. Bit Position -- 18-21
2. Valid Range -- 1-11
3. Description -- This field of the LNI or TNI specifies which of
the 10 Line Group Matrices or 5 Trunk Register Matrices was
identified in the origination.
4. Value MTX = 1-10 Regular Line Group Matrices For Trunk Register
Matrices the range is 1-5. MTX = 6 is the trunk test matrix.
B) Description of the Control for Setting the Fields of the
Originating Marker Communication Frame
The control for setting the fields described above will vary based
on whether the frame corresponds to a normal call or a test call.
Table IV-A illustrates the 12 possible call processing and test
call frames and indicates the control for each field. (Table
IV-A).
The entry in the table have the following meaning:
M -- indicates the field is set by the OM.
D -- indicates the field is set by the DP.
M' -- indicates the field is set by the OM based on what was sent
by the DP. The OM resets these fields and loads them from the
internal hardware (scanners). Comparison of what was sent to the OM
against what was received is one of the fault detection methods for
the interface.
U -- indicates the field is returned to the DP unaltered.
Dc -- indicates the value of the field is a don't care because it
will be overwritten by the OM. However for consistency, this field
should either be set to zero or to the value that the OM will set
it to.
Specific Values -- Some of the entries in the table have specific
values. This is to indicate the required value of the field for the
particular frame. Those entries where the value is not specified
can take on any reasonable value.
1. Call Processing Frames. The first two frames No. 1 and No. 2 are
the normal call processing frame received from an OM for a line and
trunk origination respectively. Since the OM sets all fields on
these two frames, these two frames are quite simple.
2. Test Call Frames. Frames 3 to 12 illustrate the setting control
(Data Processor Originating Marker) for selecting certain lines and
junctors during a test call. These frames are as follows:
Frame No.
3 -- Frame sent to OM to request the OM to cause an origination
from the line specified (LNI) using any OJ or RJ.
4 -- frame returned from OM (to DP) as a result of frame No. 3.
5 -- Frame sent to OM to request the OM to cause an origination
from an inlet on the Trunk Register Matrix as specified by the TN1
using any RJ.
6 -- frame returned from OM as a result of frame No. 5.
7 -- Frame sent to OM to cause an origination from the line
specified (LN1) using the OJ specified and any RJ in specified R
unit.
8 -- Frame returned from OM as a result of frame No. 7.
9 -- Frame sent to OM to cause an origination from the line
specified (LN1) using the specified OJ and RJ.
10 -- frame returned from OM as a result of frame No. 9.
11 -- Frame sent to the OM to cause an origination from the inlet
of the Trunk Register Matrix specified by TNI using the RJ
specified.
12 -- Frame returned from OM as a result of frame No. 11.
3. Metering Frames. When blockage occurs in the Originating Marker,
it will transmit a frame with the same information content and
format as frames No. 1 or 2 based on whether the blockage occurred
during a line or trunk origination respectively. The frame will
always contain the correct LNI or TNI however if blockage occurs
the matrix identities for the junctors will be whatever the marker
scanner indicates when the blockage was detected.
4. Maintenance Frames. These frames are described in section
3.3.3.3.
TABLE IV A
__________________________________________________________________________
ORIGINATING MARKER COMMUNICATION FRAMES FRAME* CSO BUN INO TCL MTN
MIO SBS SEC MTX ABG AUN AUI RUD BUO
__________________________________________________________________________
1 M M M=0 M=0 M=0 M M M M 1-11 M 1-5 M M M M 2 M M M=0 M=0 M=0 M M
M M 1-5 M 6 M M M M 3 D=0 D=0 D D=1 D=0 DC DC DC D D 1-5 D D D=0
D=0 4 M M U U U M M M M' M' M' M' M M 5 D=0 D=0 D D=1 D=0 DC DC DC
D D=6 D D D=0 D=0 6 M M U U U M M M M' M'=6 M' M' M M 7 D=0 D D D=1
D=0 DC DC DC D D 1-5 D D D=0 D 8 M M' U U U M M M M M' 1-5 M' M' M
M' 9 D=0 D D D=1 D=0 DC DC DC D D 1-5 D D D D 10 M M' U U U M M M
M' M' 1-5 M M' M' M' 11 D=0 D D D=1 D=0 DC DC DC D 1-5 D=6 D D D=0
D 12 M M' U U U M M M M' 1-5 M'=6 M' M' M' M'
__________________________________________________________________________
3.3.3.2 data interface with terminating marker
a. description of Terminating Marker Communication Frames
The frame of information which is transmitted via the CR between
the data Processor and the Terminating Marker consists of 4 data
words (96 bit), 4 parity bits, and 4 error detection bits. The four
data words contain the following groups of data
Word 0 -- Control data and Marker identity
Word 1 -- Selector Group Inlet Identity and Trunk control.
Word 2 -- Selector Group Outlet information.
Word 3 -- Terminating line identity.
The normal call processing interface with the TM consist of a 4
word (104 bit) transmission followed by a 4 word response from the
TM indicating the result of the termination attempt. The format of
the four data words is given below:
1. Data Word 0 -- Data word zero is the control and marker identity
word for the total frame of information. The format of this word is
similar to the format of data word 0 for the Originating Marker.
##SPC52##
Sbs - subsection
1. Bit Position -- 2-3
2. Valid Range -- 0-3
3. Description -- This field specifies the type of marker and if
there is more than one marker in a section, the subsection. This
field, along with SEC & MID specifies a unique marker.
4) Value
Sbs = 0 terminating Subsection
Sbs = 1, 2, 3 originating Subsection 1, 2, 3 respectively
Mid - marker Identity
1. Bit Position -- 4
2. Valid Range -- 0-1
3. Description -- This bit indicates which marker of a given pair
(specified by SEC & SBS) is involved in the origination.
4. Value
Mid = 0 marker A
Mid = 1 marker B
Mtn - maintenance Call
1. Bit Position -- 5
2. Valid Range -- 0-1
3. Description -- This bit indicates whether the frame should be
interpreted as call processing or maintenance information.
4. Value
Mtn = 0 -- call Processing or test call
Mtn = 1 -- maintenance request or command
Tcl - test Call
1. Bit Position -- 6
2. Valid Range -- 0-1
3. Description -- This bit is used to indicate a test call on the
return frame from the OM.
4. value
Tcl = 0 standard Call
Tcl = 1 test Call
Int - instruction Terminating
1. Bit Position -- 7-11
2. Valid Range -- 0-31
3. Description -- When MTN = 0 this field is used to specify the
type of termination required. This mode is used for normal call
processing, routining, and test calls. When MTN - 1 the INT field
will be used for maintenance instructions (see Section
3.3.3.3.)
4. Value -- When MTN = 0, the INT field will have the following
interpretation.
Int = 0 -- mcr test -- no call processing is performed, but the MCR
will immediately return the data frame exactly as received.
1. Normal Call, No Test -- Normal call process with no continuity
test to the RJ.
2. normal Call with Test -- Normal call processing with a
continuity test to the RJ. This test is specified by the DPU when
the call is being processed through the final selector matrix and
the call is not terminating to a local line matrix.
3. No Pull -- This is a special call in which the inlet potential
is not checked and the path is not pulled, but a multiple path
check is made. This call is used only as a test call and the TCL
bit must always be set.
4. Busy Override -- The path is completed even if the line is busy.
The BO instruction is only used to complete to lines and always
uses an X-TJ. The BO instruction should never be used in
conjunction with a specified matrix path. A continuity test to the
RJ is made.
5. Wire Chief -- The path is completed even if the line tests busy
and a line circuit test is performed. In addition the call is
completed even with the detection of either foreign potential or
power cross. If either of these conditions is detected, the TCS
byte will indicate one of the line circuit fault codes.
6. Line Routine - This special call performs a line circuit test
but does not override line busy or override any other check or
test. ITN = 7 - 31 Spare
Cst - call Status Terminating
1. Bit Position -- 20-23
2. Valid Range -- 0-15
3. Description -- This field is used by the TM to inform the DP on
the outcome of the Termination attempt. Table V-A illustrates the
possible CST replies for each Terminating instruction (INT).
4. value -- CST = 0 Marker malfunction -- call not complete
1. Completed call -- line or outlet idle -- no line circuit
fault.
2. Call not completed -- line busy.
3. All LX AB links busy
4. All TJ-LX paths busy or all outlets busy.
5. Special feature busy.
6. Path Busy
7. Call completed -- line or outlet busy - no line circuit
fault.
8. Call completed -- line idle, -- line circuit fault.
9. Call completed -- line busy -- line circuit fault.
10. Marker Trouble -- call completed -- line idle -- no line
circuit fault
11. Marker trouble -- call completed -- line busy -- no line
circuit fault
12. Marker Trouble -- call completed -- line idle -- line circuit
fault
13. Marker Trouble -- call completed -- line busy -- line circuit
fault
14-15. Spare
In some codes where "no line circuit fault" is indicated, a line
circuit test was not made. A line circuit test is only made when a
Wire Chief or Line Routine instruction is received.
Sec - section
1. Bit Position -- 0-1
2. Valid Range -- 1-3
3. Description -- This field is used in the return frame from the
TM to indicate the section in which the transmission was sent.
4. Value
Sec = 1 office Section No. 1 SEC = 2 Office Section No. 2 SEC = 3
Selector section
B. Data Word 1 - Data word 1 contains the 16 bit Selector Group
inlet identity and the Trunk and junctor control field.
##SPC53##
Tkc - trunk control
1. bit Position -- 0-5
2. Valid Range -- 2.sup.6
3. Description -- The bit TKC field is a control field for
controlling the Terminating Junctor or Trunk. The 6 bit field is
transferred to the trunk or junctor via a 6 bit bus.
4. Value -- The value of the TKC field for specifying ringing
frequency for TJs is as follows:
Tck = 16 frequency 1 to the R lead
Tck = 17 frequency 1 to the T lead
Tck = 18 frequency 2 to the R lead
Tck = 19 frequency 2 to the T lead
Tck = 20-25 spare ringing codes
Sau - selector Matrix A Unit
4. Value
Sau = 1 selector A Unit No. 1
Sau = 5 selector A Unit No. 10
Sab - selector Matrix AB Group
1. Bit Position -- 15-17
2. Valid Range -- 1-6
3. Description -- The SAB field defines one of the 6 AB group of
the Selector Matrix in the total Selector Group inlet identity.
4. Value
Sab = 1 selector AB Group No. 1
Sab = 6 selector Ab Group No. 6
Smx - selector Matrix
1. Bit Position -- 18-21
2. Valid Range -- 1-11
3. Description -- The SMX field defines one of the 10 Selector
Matrices in a Selector Group in the total Selector Group inlet
identity.
4. Value
Smx = 1 selector Matrix No. 1
Smx = 10 selector Matrix No. 10
Smx = 11 selector Test Matrix
C. Data Word 2 -- Data Word 2 contains the fields for specifying a
group of outlets of the Selector Group Matrices. It also contains
the fields for retrieving the identity of the trunk or junctor
selected by the Terminating Marker. ##SPC54##
Sut -- selector Units
1. Bit Position -- 0-3
2. Valid Range -- 0-10
3. Description -- On communication frames from the TM to the DP,
this field and the STN field specified which outlet in the group
was selected. On frames to the TM this field, in conjunction with
the STN field, can instruct the TM to select any idle unit (SUT =
0) of a particular outlet specified by SUT & STN (both not
equal to zero)
4. Value -- SUT = 0 In the transmission to the TM, this indicates
that a scan is to be made.
1 In the transmission to the TM, this indicates that the path is
specified and that Units No. 1 is to be used.
10 This indicates that the path is specified and that Units No. 10
is to be used.
In the return transmission to the DPU, the Units No. used in the
call (1-10) is sent.
Stn -- selector Tens
1. Bit Position -- 4-7
2. Valid Range -- 0-8
3. Description -- See SUT
4. value -- STN = 0 In the transmission to the TM, this indicates
that a scan is to be made.
1 In the transmission to the TM, this indicates that the path is
specified and that Tens No. 1 is to be used.
8 In the transmission to the TM, this indicates that the path is
specified and that Tens No. 8 is to be used.
In the return transmission to the DPU, the Tens No. used in the
call (1-8) is sent.
Sqs - sequential Scan
1. Bit Position -- 8
2. Valid Range -- 0, 1
3. Description -- This field specifies the type of scan the TM
should use in selecting in idle unit.
4. Value
-- SQS - 0 Random Scan
Sws = 1 sequential Scan
Pls -- plus
1. Bit Position -- 9-11
2. Valid Range -- 0-7
3. Description -- The PLS field is used to specify the size of the
outlet group to be scanned. The PLS field specific how many arrays
(10 outlets) should be scanned in addition to the array specified
by the ARR field.
4. Value -- PLS = 0 Only the array indicated by ARR is to be
scanned.
1 One Array (array ARR + 1) is addition to that specified by ARR is
to be scanned.
6 Six Arrays in addition to that specified by ARR are to be
scanned.
6 Six Arrays in addition to that specified by ARR are to be
scanned.
7 Scan all Arrays on Horizontal specified.
Arr - array
1. Bit Position -- 12-15
2. Valid Range -- 1-8
3. Description -- The ARR Field is used to specify one of 8 outlet
groups. An array consists of 10 outlets on the same horizontal.
##SPC55##
Ccg -- c card Group
1. Bit Position -- 16
2. Valid Range -- 0,1
3. Description -- The CCG field is used to indicate which group of
C cards should be involved in the scan. Each C card group consists
of 800 outlets maximum.
4. Value
Ccg - 0 c card Group A
(hor = 1, 10)
ccg - 1 c card group B
(hor = 1, 10 is interpreted as horizontal 11 to 20).
Hor -- horizontal
1. Bit Position -- 17-20
2. Valid Range -- 1-10
3. Description -- In conjunction with the CCG field, the HOR field
specifies one of the 20 horizontal upon which the scan or selector
should take place.
4. Value -- For CCG = 0, HOR has the following interpretation:
Hor = 1 horizontal No. 1
Hor = 10 horizontal No. 10
For CCG = 1, HOR has the following interpretation:
Hor = 1 horizontal No. 11
Hor = 10 horizontal No. 20
D. Data Word 3 -- Data word 3 contains the information required to
specify a line equipment for a local termination. This word also
contains information for termination to PBXs on the line matrix.
For trunk terminations, data word 3 is blank.
______________________________________ L LMX LAB LAU LAI P X 23 22
21 18 17 15 14 11 10 6 5 4 0
______________________________________
Lpx -- line Matrix PBX
1. bit Position -- 5
2. Valid Range -- 0-1
3. Description -- The LPX field is used to indicate a PBX line
matrix termination. When LPX is a one, the interpretation of the
remaining fields will differ from that of a normal line Termination
(LPX = 0).
4. value
Lpx = 0 normal Line Termination (not PBX)
Lpx = 1 line Matrix PBX termination
Lai - line A Inlet
1. Bit Position -- 6-10
2. Valid Range -- 1-20
3. Description -- The LAI field, which is analogous to the AUI on
originating, is used to specify the particular inlet in the A unit
for terminating a local call.
4. Value -- The interpretation of LAI for LPX = 0 is as
follows:
Lai = 1 line inlet No. 1
Lai = 20 line Inlet No. 20
When LPX = 1, the LAI field should be set = 0 by the DP. For this
case, the TM will insert the particular inlet selected into the LAI
field for the terminating response.
Lau - line Matrix A Unit
1. Bit Position -- 11-14
2. Valid Range -- 0-10
3. Description -- This field, which is analogous to SUN an
originations, is used to specify one of 10 A units for terminating
a local call. For a PBX call (LPX = 1), the LAU field is used to
specify the scan group and the particular set of PBX inlets. For
LPX = 0, LAU has the following interpretation
LAU - 0 Indicates that no Line A Unit is being used. ##SPC56##
4. Value -- For LPX = 1, LAU has the following interpretation:
Lau = 0xxx indicates inlets 1 and 6 of every A unit.
Lau = 1xxx indicates inlets 11 and 16 of every A unit ##SPC57##
If the LPX bit is a 1, the LAU field is broken into two pieces of
data.
The most significant bit indicates whether inlets 1 and 6 or inlets
11 and 16 are to be used. The 3 least significant bits indicate the
scan group.
Lab -- line AB Group
1. Bit Positions -- 15-17
2. Valid Range -- 0-6
3. Description -- This field, which is analogous to the ABG on
originating, specifies which of five AB groups are involved in the
local termination.
4. Value -- The interpretation of the LAB group is independent of
the LPX field.
Lab = 0 indicates that no line matrix is being used. ##SPC58##
Lmx -- line Matrix
1. Bit Position -- 18-21
2. Valid Range -- 0-11
3. Description -- This field, which is analogous to MTX on
originating, is used to specify 1 of 10 line matrices for a local
termination.
4. Value -- The interpretation of LMX is independent of the LPX
field.
Lmx - 0 indicates that no line matrix is being used ##SPC59##
B. Description of the Control for Setting the Fields of the
Terminating Marker Communication Frame
The control for setting the fields described in section 3.3.2.8
will vary based on whether the frame correspond to a line, trunk,
or PBX termination and whether the termination is a normal call or
a test call. Table V-A illustrates the 10 call processing and test
call frames and indicates the setting control for each field. The
entries in the table have the same meaning as for Table IV A
(Section 3.3.3.1). The 10 frames are as follows:
Frame No.
1 -- Frame sent to TM for a line termination.
2 -- Frame returned from TM as a result of frame No. 1.
3 -- Frame to TM for a line termination specifying a particular
Terminating Junctor.
4 -- Frame returned from TM as a result of frame No. 3.
5 -- Frame sent to TM for a trunk termination on the Selector Group
Matrix.
6 -- Frame returned from TM as a result of frame No. 5.
7 -- Frame sent to TM for a trunk termination specifying a
particular trunk (particular Selector Group outlet).
8 -- Frame returned from TM as a result of frame No. 7.
9 -- Frame sent to TM for a PBX line termination.
10 -- Frame returned from TM as a result of frame No. 9.
When blockage or trouble occurs on a termination attempt the TM
will convey this condition via the status field (CST) on the return
frame.
The maintenance frames (MTN = 1) are described in section
3.3.3.3.
TABLE V-A
__________________________________________________________________________
TERMINATING MARKER COMMUNICATION FRAMES CST INT TCL MTN MID SBS SEC
SGI* TKC SGO* STN SUT TLN* LPX
__________________________________________________________________________
1 DC D D=0 D=0 DC DC DC D D D D=0 D=0 D D=0 2 M U U U M M M U U U M
M U U 3 DC D D=1 D=0 DC DC DC D D D D D D D=0 4 M U U U M M M U U U
M' M' U U 5 DC D D=0 D=0 DC DC DC D D D D=0 D=0 D=0 D=0 6 M U U U M
M M U U U M M U U 7 DC D D=1 D=0 DC DC DC D D D D D D=0 D=0 8 M U U
U M M M U U U M' M' U U 9 DC D D=0 D=0 DC DC DC D D D D=0 D=0
D.sup.t D=1 10 M U U U M M M U U U M M U.sup.t U M
__________________________________________________________________________
*SGI -- Selector Group Inlet Includes SMX, SAB, SAU, +SAI *SGO --
Selector Group Outlet Includes HOR, CCG, ARR, PLS, +SQS *TLN --
Terminating LNI includes LMX, LAB, LAU, LAI t -- The LAI Field
Should be Set = 0 by DP + -- The Marker will Write LAI but return
the Remainder of TLN unaltered
3.3.3.3 Marker Maintenance Frames
A. Retrieval of Marker Diagnostic Data
The transfer of all diagnostic information including error
indication, Marker sequence state in which the error occurred, and
marker status data (states of logic elements) to the DP will be via
the Communication Register. The CR is presently planned to be used
also for all maintenance directives such as on line/off line
control, resetting error interrupts, etc. Word of either the
Originating or Terminating frame will be used for both requesting
the marker to return diagnostic data and for maintenance commands.
Word one of either the Originating or Terminating frame will be
used to transfer 24 bits of diagnostic information. The format of
these two words are as follows: ##SPC60##
Tcl, & sec -- these fields have the same meaning as described
in section 3.3.2 and 3.3.3.1. TCL should be set = 0 for the
maintenance retrieval.
Mtn -- this field indicates the frame should be interpreted as a
maintenance retrieval or command. It should be set = 1 for the
maintenance mode.
In(x) -- the Instruction field, INO and INT for originating and
terminating respectively, is used to specify which group of 24
status or indication points are to be returned to the DP.
Dg(x) -- the Data Group field, DGO and DGT for originating and
terminating respectively, is used to specify which group of 24
status or indication points are to be returned to the DP.
Md(x) -- the Maintenance Data, MDO and MDT field for originating
and terminating respectively, contains the 24 bits of status or
indication points in the Marker. MD(X) should be set = 0 by the DP
on the transmission to the Marker.
The additional two words of the frame on terminating communication
frames will not be used for the maintenance transmissions and
should be set = 0 by the DP.
The Marker (originating or terminating) will always attempt to
return a communication frame to either a maintenance data retrieval
command or a maintenance command. The only time this would not be
possible would be the occurrence of trouble in the MCR sending
operation.
3.3.3.4 CPD DIRECTIVES:
Both Originating and Terminating Markers can be controlled via CPD
directives (refer to section 8.5-10) in the following manner.
Cpd n*, 001: RESET ENABLE:
This directive resets all error indicators in the markers and sets
it to an idle state.
Cpd n*, 002: RESET INTERRUPTS
This directive resets only the malfunction alarm interrupts. It
does not change the state or condition of the marker.
Cpd n*, 004: SEND SR DATA
This directive is used to unload the shift register in the MCR and
transmit its contents to the CCP via the CR for analysis.
Cpd n*, 010: STANDBY
This directive will place the associated Originating Marker in a
standby condition when that marker enters the idle state. The
standby condition will inhibit the OM from assigning a CFS from a
matrix and will set the standby interrupt/sense line true in order
to alert the CCP of its condition.
Cpd z*, 020: report blockage:
after receiving this directive the OM will report (via the CR) to
the CCP, the conditions of, all AB lines busy, All RJ(s) busy and
path busy, whenever they are encountered. (With this directive true
the initial (or same) CFS could cause redundant reports to be
transmitted.)
Cpd z*, 040: do not report blockage
this directive cancels the preceding directive.
Cpd n*, 100: DO NOT PERFORM LINE TEST
This directive resets a latch in the markers that would test the
conditions of the marker line.
Cpd n*, 200: PERFORM LINE TEST:
This directive sets the latch as described in CPD n, 100.
Cpd n*, 400: RESET SEND SR DATA
This directive cancels the directive CPD n, 004.
Section 4.0 register sender
4.1 introduction
a brief description is given here of the major hardware elements of
the Register-Sender and their relationship to the Data Processing
Unit (DPU.) A fully-equipped Control Section has one DPU and two
Register-Senders.
Each Register-Sender (RS) has two identical Common Logic Units
(CLU-A and CLU-B) and each CLU has an associated RS Core Memory
(abbreviated as RCM-A or RCM-B). Each Register-Sender also has its
own multiplex equipment and space-divided hardware.
Space-divided hardware is electromechanical in nature and provides
interfaces with the system's network equipment. The multiplex
equipment provides the interface between the space-divided
electro-mechanical hardware and the time-shared electronic hardware
of the CLU's.
A minimally-equipped EAX Control Section includes at least one RS
(in addition to the Always-required DPU). Within the RS, both CLU's
must be equipped but space-divided hardware and its associated
multiplex equipment will be equipped to the extent called for by
individual office requirements. The two CLU's within an RS normally
operate in synchronism, simultaneously servicing each call. They
are provided as a pair for reliability so that a single fault in
the hardware will not put an RS out of service. The two
Register-Senders in a fully-equipped EAX control Section operate
independent of each other, never servicing the same call.
4.2 Interface
FIG. 36 shows the major elements involved in the interface between
the RS and the DPU. The groupings involve signals from RS Core
Memory (RCM) to the DPU, from the DPU to RCM (including parity
signals not associated with RCM), RS/DPU configuration sense lines,
RS multiplex configuration sense lines, and RS interrupt-associated
Sense lines.
4.2.1 Signals from RCM to DPU
A group of 24 data bits, (Data Bits 0-23) and a parity bit (Data
Bit 24) are sent to the DPU from the RCM. The DPU detects parity
over all 25 leads as a check on the transmissions. This 25 lead
grouping is used for the PRA instruction execution by the CCP.
4.2.2 signals from the DPU to RCM
A group of 24 data bits, is sent to the RS from the DPU. The RS
generates parity on Data Bits 0-23 and stores this parity bit in
the RCM. The 24 lead grouping is controlled by execution of the PAR
instruction.
A group of 13 address bits is sent from the DPU to the RS. This 13
lead grouping is used for both the PAR and PRA instruction
executions.
4.2.3 RS/DPU Configuration Sense Lines
Three sense lines from the RS give a partial status indication to
the DPU of the configuration between the RS and DPU. The three
lines are: (a) CCP-A Selected: indicates that this Register-Sender
Common Logic Unit (CLU) is accepting read/write commands and data
from CCP-A. (b) CCP-B Selected: indicates that this CLU is
accepting read/write commands and data from CCP-B. (c) Run Simplex:
indicates that this CLU will not attempt to sync read/write
commands with its CLU mate before execution of such commands. This
operation feature will typically be used when the other CLU has
been configured off line with respect to its space-divided
equipment.
These sense lines are assigned to groups 20-23 as shown in section
8.3 of this document.
4.2.4 RS Multiplex Configuration Sense Lines
Four sense lines from the RS indicate to the DPU the status of the
configuration between the CLU's and their associated multiplex
equipment. The multiplex circuits and CLU's have two sets of
signals between them. One set, the scan leads, carry signals from
the multiplex to the CLU's. The other set, the distribution set,
carries signals from the CLU's to the multiplex.
Normally both CLU's scan multiplexed signals from all space-divided
equipment but each CLU distributes signals (via the multiplex) only
to the half of the space-divided equipment to which it is
configured for distribution. CLU-A normally distributes signals to
RJM Groups 0, 2, 4 and 6, and RSM Files 1, 3, 5, and 7. CLU-B
normally distributes signals to RJM Groups 1, 3, 5, and 7 and RSM
Files 2, 4, 6, and 8. The CLU-Multiplex configuration is controlled
by means of Direct Control Pulses; see section 8.5. In the case of
a Register Timing Generator (RTG) "Y" or "Z." Generator failure,
the CLU-Multiplex scan configuration is automatically changed, via
hardware, to a simplex mode in which the CLU's scan configuration
is the same as the normal distribution configuration.
The four sense lines are:
a. Normal RJM Scan (RJM being the multiplex circuitry dealing with
Register Junctors).
b. Normal RSM Scan (RSM being multiplex circuitry dealing with
senders and receivers).
c. Normal RJM Distribution
d. Normal RSM Distribution
All four of these sense line types are assigned to each of groups
25, and 26 as shown in section 8.3 of this document.
4.2.5 RS Interrupt Associated Sense Lines
Three sense lines from the RS cause the DPU to be interrupted. The
three are associated with maintenance; the RS Fault Interrupt Sense
Line, the RS Error Count Interrupt, and the RS System Trouble
Interrupt Sense Line. They are associated with interrupt levels 2
and 8.
These sense lines are assigned to groups 18 and 19 as shown in
section 8.3.
The interrupt level assignments are given in section 8.4. 4.3
General RS Core Memory Accessing & Layout
FIG. 37 shows a sketch of the layout of the RCM. It is conceptually
divided into five sections: normal call processing Register Junctor
Memory slots which are associated with Register Junctor units,
maintenance Register Junctor memory slots which are not associated
with any physical Register Junctor units, miscellaneous RCM data
words, the fault snapshot area, and a section of unassigned
words.
4.3.1 Normal & Maintenance RJ Memory Slots
The first two sections of the RCM lie within the 10 millisecond
operating scan of the RS. These areas are divided into 202
sixteen-word blocks. The layout of the first 201 blocks are defined
in the REGISTER-SENDER patent application to which the reader is
referred for full definition of the 16-word call processing blocks.
The 202 word block controls the RS Direct Control Pulse and Latch
hardware of the RS Maintenance Control Unit (RMU) which is
described in section 4.4.5.
The first 192 blocks have a one-for-one fixed assignment to 192
space-divided Register Junctor circuits which may be equipped in a
Register-Sender. Even though only part of the 192 Register Junctors
may be equipped in a Register-Sender, all 202 RJ memory blocks are
always dedicated and are scanned during each 10-millisecond scan
cycle. Normally the Register-Sender executes the RJ memory block
scan in one of two modes described below, starting with the memory
block dedicated to the first Register Junctor circuit.
The RJ time slot is known as a Z time. There are 202 Z times, all
of them occurring sequentially during the 10-msec cycle. Each Z
time is normally divided into 9 intervals to allow successive
appearances of 9 of 11 possible Y times, which are numbered Y1 to
Y11. Each Y time represents operation by the Register-Sender on a
pair of memory words within an R memory block.
A Y time is divided into five X times numbered X1 to X5. During X1
and X2 the RS successively reads two 26-bit words from the RCM into
a 52-bit buffer. The combined contents of this buffer are referred
to as a row. During X3 the call processing circuitry of the RS
common logic acts on the contents of this buffer and on information
from space-divided equipment associated with the call being
serviced by the common logic during this Z time.
During X3 the RCM itself can be used for three purposes depending
on the Y time. During Y1-X3 the RS always writes the RJ Scan
Position Word (see section 4.3.2). During Y2-X3, if the associated
RJ requires DPU data, the RS writes the Translation Interrupt Word
(see section 4.3.2). If during Y2-X3 the associated RJ does not
require DPU data, X3 may be used by the DPU for reading or writing
at any location in RCM except at a location in the RJ Memory block
(Z slot) which the RS is presently servicing (see writeup on the RJ
Scan Position Word in section 4.3.2). During the X3 times of Y3
through Y11 the DPU is allowed access with only one restriction:
the DPU may not access any word in the Z slot presently activated
by the RS common logic.
The difference between the two normal scans is that: in one rows 5
& 6 are scanned and in the other rows 7 & 8. The selection
is made by call processing hardware.
Maintenance hardware overrides the above given conditions at
certain times. The maintenance sequences are covered in section
4.4.
4.3.2 Miscellaneous RCM Data Words
In the 203rd memory block, four words have been assigned as
miscellaneous RCM data words. The RJ Scan Position Word contains
the address of the RJ memory block currently being addressed by the
RS. It is changed each time the Z time changes. This data is used
by call processing software to prevent interference which would
arise by both the RS and call processing software simultaneously
altering the data within an RJ slot. If software finds the RS is
serving or is about to serve the slot that it wants to access,
software will delay its access until the RS is finished with that
RRJ slot.
The Translation Word is written at the request of RS call
processing circuitry. It contains the identity of an RJ which
requires a translation. This data is used by call processing
software to determine which RJ slot requests a Translation.
The System Trouble Interrupt Word is written under the control of
RS maintenance hardware. It contains the RJI and the identity of
the row and RJ memory slot during which a System Trouble Interrupt
was set. This data is used by maintenance software to identify the
cause of the interrupt. The Error Count Interrupt Word contains the
same data and performs the same function as the System Trouble
Interrupt Word except it is used when the Error Count Interrupt is
set by RS maintenance hardware.
4.3.3 Fault Snapshot Area
Block number 203 is allotted for a Fault Snapshot of 16 words. The
layout of the block is given in Section 8.2 of the MSSS. This block
is loaded by RS maintenance hardware at the time of the detection
of a fault or when requested by the DPU (see section 4.4.3). This
data is used by maintenance software to determine the cause of the
RS Fault Interrupt which is set by RS maintenance hardware after
the fault snapshot is stored.
4.3.4 Unused RCM
The portion of RCM which is not used by the RS may be addressed by
the DPU. One instance where this is done is when maintenance
software attempts to localize faults associated with the RCM. This
software must access certain words of RCM within this area in order
to accomplish its tasks. DPU access of words in this area is
executed in the same manner as for words in any other area.
4.4 RS Maintenance Functions
From a DPU point of view, there are two important features of RS
maintenance. First, RS maintenance hardware can change the status
of RS sense lines, RS interrupts, and RCM contents upon the
detection of a fault. Second, certain functions of RS maintenance
hardware are directly controlled by outputs of the DPU both by the
altering of RCM and by the use of CPD's.
RS maintenance hardware is composed of three main elements all
under the general heading of the RS Maintenance Circuit (RMN). The
first element is the RS Maintenance Control Unit (RMU) which
controls overall maintenance functions within a CLU. There are two
RMU circuits (A and B) within the RMN, one unit associated with
each common logic unit of an RS. The second element, RS Maintenance
Data Selector and Parity Generator (RSP), gates data to be compared
into comparison gates or maintenance signals to be stored into
memory under the control of the RMU. It also generates parity on
the data stored into RCM and the address signals sent to RCM. The
RSP is duplicated in the same manner as the RMU, one RSP associated
with each common logic unit.
The third element is the RS Maintenance Comparitor (RCP) which
compares the signals gated to it from each RSP. This element is not
duplicated within a Register-Sender.
Within each 16-word memory block associated with Register Junctor
circuits there are certain bits dedicated for maintenance.
The FB Bit (Freeze Bit) is located in word 1B position K1. When
set, it instructs the RMU to prevent alteration by the CLU of any
word of that RJ memory block. The DCY Field (Data Collection Y Time
Field) contains four bits and is located in word 4B positions L1 to
L4. The contents of DCY are used by the RMU during Data Collection
(see section 4.4.3). The DCX Field (Data Collection X Time Field)
contains two bits and is located in word 4B positions K2 & K3.
The contents of DCX also are used by RMU during data collection.
The SB Bit (System Trouble Service Bit) is located in word 4B
position K1. When set it indicates to the RMU that the System
Trouble Interrupt generated by this RJ Memory block has been
serviced by the DPU.
4.4.1 generation of an Error Count Interrupt or Fault Interrupt
The primary hardware fault detection method used by the RS in
comparisons between certain signals of the synchronously running
CLU's. When a non-comparison occurs or when a secondary detector
(parity circuit for example) indicates a failure the RS initiates a
recycle of the operations that have just been performed. If the
recycle is successful, the Error Count Word (see section 4.3.2) is
written and the Error Count Interrupt is set.
If the recycle is unsuccessful the RMU sets the FB bit to 1 in the
appropriate memory word of this RJ memory block, a fault snapshot
is taken under the control of the RMU (see section 4.3.3), and the
Fault Interrupt is set.
The RMU will ignore all further fault detections in this and other
RJ slots until the Fault Interrupt is reset by a CPD.
4.4.2 generation of a System Trouble Interrupt
Synchronously-operating RCC (RS Central Control) hardware in the
CLU continuously monitors several conditions during the processing
of a call. The reader is referred to the REGISTER-SENDER
MAINTENANCE patent applications for a discussion of the conditions
which result in the setting of the System Trouble Bit (TRB) in
RJ-associated memory. The CLU's will detect a system trouble during
Y1 to Y4 and will each set an associated common logic flip-flop.
During Y5 each RMU senses this flip-flop set and examines the
system trouble interrupt status flip-flop and the system trouble
Service Bit (SB) flip-flop in the RMU. If neither of these latter
flip-flops is set the RMU will store the System Trouble word with
the proper information from this RJ memory slot (see section 4.3.2)
and set the System Trouble Interrupt. If either the interrupt or SB
is set, indicating that this or another system trouble is being
serviced or that this system trouble has already been serviced, no
action is taken. During Y9, the Freeze Bit (FB) in RJ memory is set
as well as the TRB bit whether or not the interrupt was set in Y5.
The Freeze Bit prevents alteration of the contents of the Z slot
until reset.
If an RJ slot is entered and the FB and TRB memory bits are set but
the SB bit is not set, the RMU knows that the System Trouble for
that slot has not yet been serviced. An attempt to serve it will be
made in Y5 in the same manner as the initial attempt. The RMU will
continue to attempt to service the Trouble until successful.
After servicing the System Trouble the processing of the RJ can be
allowed to continue in the presence of the trouble by resetting the
FB bit and leaving the SB bit set. This capability allows for the
clearing down of the call.
4.4.3 Data Collection
The RMU has the capability for the taking of a data collection
snapshot under software control. This function is controlled by the
DCX and DCY fields (see section 4.4). Two adjacent RRJ slots are
required in order to collect data. The first contains the
instructions DCX and DCY giving the XY times of the next RRJ slot
at which time the data is to be collected, and the second RRJ slot
contains the data which is to drive the hardware to be exercised
for the diagnosis of faults that might exist in it.
The general sequence is as follows:
a. Freeze the RJ slot from which data is to be collected, the 2nd
RJ slot.
b. Load the frozen RJ slot with the data to be acted on by the
CLU.
c. The DCX and DCY fields in the first RJ slot must now be loaded.
The CDY field indicates the Y time during which the data is to be
collected in the following RJ slot, DCY = 0 to 10 for Y slots 1 to
11 and the DCX field determines the X time, DCX = 1 to 3 for X3 to
X5.
d. If it is desired that the snapshot be taken with the 2nd RJ slot
unfrozen the FB bit in that RJ is reset at this point. If the FB
bit is to be reset both c. and this item must be carried out before
the normal RS scan begins to service the RJ slot prior to the RJ
slot in which the data collection snapshot is to be taken.
The data collection snapshot will be available in RJ memory block
number 203 (see section 4.3.3). As is the case with a fault
snapshot, the FB bit is automatically written whenever a data
collection snapshot is taken. If it is desired to return the RJ to
normal call processing after a fault or data collection snapshot
has been taken, the FB bit will have to be reset.
4.4.4 Control Pulse Directives
The CPD's defined for the RS are given in section 8.5. The numbers
given are the octal numbers associated with the CPD's.
Octal no. directive description
005: rpi-a select CCP-A
Clu-a will take read/write commands from CCP-A and the data to be
written into RCM-A will be that data sent by CCP-A
006: rpi-b select CCP-A
The same as 005 except for CLU-B and RCM-B
007: rpi-a&b select CCP-A
The same as 005 exept for both CLU's and RCM's.
011: RPI-A Select CCP-B
Clu-a will take read/write commands from CCP-B and the data to be
written into RCM-A will be that data sent by CCP-B
012: rpi-b select CCP-B
The same as 011 except for CLU-B and RCM-B
013: rpi-a&b select CCP-B
The same as 011 except for both CLU's and RCM's
015: RCM Clear -- CLU-A
This initializes hardware in RCM-A.
016: rcm clear -- CLU-B
This initializes hardware in RCM-B.
017: rcm clear -- CLU-A&B
This initializes hardware in both RCM-A&B
021: rpi-a select No CCP
Clu-a will not accept read/write commands from either CCP.
022: rpi-b select No CCP
Clu-b will not accept read/write commands from either CCP.
023: rpi-a&b select No CCP
Both CLU's will not accept read/write commands from either CCP.
025: rtg trouble Reset CLU-A
Resets RTG (RS Timing Generator) trouble and error detecting logic
in CLU-A
026: rtg trouble Reset CLU-B
Resets RTG trouble and error detecting logic in CLU-B
027: rtg trouble Reset CLU-A&B
Resets RTG trouble and error detecting logic in both CLU's.
031: RTG Reset CLU-A
Resets all RTG timing functions in CLU-A to an initial state.
032: RTG Reset CLU-B
Same as 031 except for CLU-B
033: rtg reset CLU-A&B
Same as 031 except for both CLU's
101: RMU-A Control Pulse Enable
Enables the generation of pulses in CLU-A (see section 4.4.5)
102: RMU-B Control Pulse Enable
Enables the generation of pulses in CLU-B (see section 4.4.5)
103: Both RMU's Control Pulse Enable
Enables the generation of pulses in both CLU's (see section
4.4.5)
201: RMU-A Control Latch Enable
Enables the setting or resetting of latches in CLU-A (see section
4.4.5)
202: RMU-B Control Latch Enable
Enables the setting of resetting or latches in CLU-B (see section
4.4.5)
203: Both RMU's Control Latch Enable
Enables the setting or resetting of latches in both CLU's (see
section 4.4.5)
401: RPI-A SELECT NO CCP
Same as 021 but must be used when CCP-A is off line instead of
021
402: RPI-B SELECT No CCP
Same as 022 but must be used when CCP-B is off line instead of
022
414: Reset Request for Translation Interrupt
Resets the flip-flop associated with the request for translation
interrupt sense line in both CLU's
421: RPI-A SELECT NO CCP
Same as 021. May be used instead of 021 whether one or both CCP's
are on line.
422: RPI-B SELECT NO CCP
Same as 022. May be used instead of 022 whether one or both CCP's
are on line.
423: RPI-A & B SELECT NO CCP
Same as 023. Must be used instead of 023 when one CCP is
off-line.
424: Reset RS Fault Interrupt
Resets the flip-flop associated with the RS fault interrupt sense
line in both CLU's.
430: Reset System Trouble Interrupt
Resets the flip-flop associated with the RS system trouble
interrupt sense line in both CLU's.
454: Run In Sync
Instructs the CLU's to sync commands from both CCP's before
ackowledging either.
464: Run Simplex
Instructs the CLU's not to attempt to sync commands from both CCP's
before ackowledging each one.
470: Reset Error Count
Resets the flip-flop associated with the RS error count interrupt
sense line in both CLU's.
4.4.5 Direct Control Pulses and Latches
Pulses controlling certain RS conditions can be generated and
certain latches within the RS set or reset under software control.
The following is a list of the direct control pulse assignments by
bit:
A1: enable RJM Group O
If this is executed in CLU-A, Group 0 of the RJM is configured to
CLU-A, or conversely for CLU-B. The RJM Common Group enable pulse
(FI) must also be specified.
A2: enable RJM Group 1
As A1 Except for RJM Group 1
A3: enable RJM Group 2
As A1 except for RJM Group 2
A4: enable RJM Group 3
As A1 except for RJM Group 3
B1: enable RJM Group 4
As A1 except for RJM Group 4
B2: enable RJM Group 5
As A1 except for RJM Group 5
B3: enable RJM Group 6
As A1 except for RJM Group 6
B4: enable RJM Group 7
As A1 except for RJM Group 7
C1: enable RSM File 1
If this is executed in CLU-A, file 1 of the RSM is configured to
CLU-A, or conversely for CLU-B. The RSM Common Group Enable pulse
(F2) must also be specified
C2: enable RSM File 2
As C1 except for file 2
C3: enable RSM File 3
As C1 except for file 3
C4: enable RSM File 4
As C1 except for file 4
D1: enable RSM File 5
As C1 except for file 5
D2: enable RSM File 6
As C1 except for file 6
D3: enable RSM File 7
As C1 except for file 7
D4: enable RSM File 8
As C1 except for file 8
E1: reset BY Flip-Flop in RCB
Resets the BY (S/R a-signment function BUSY) Flip-Flop which
normally is set when the RCC is in process of connecting a sender
or receiver to a Register Junctor
E2: unassigned
E3: ccp inhibit retrial
When this latch is set, the RMU initiates a Fault Interrupt on the
initial detection of a malfunction rather than initiate a retrial.
This latch is automatically reset from the RMU after the next
snapshot is taken.
E4: set DMC latch in RMU
This pulse is used to set the Disable Matrix Connection (DMC) latch
in the RMU. The DMC latch when set prevents the CLU within which it
is set from initiating a S/R matric connection.
F1: rjm common Group Enable
This pulse enables the eight RJM reconfiguration pulses.
F2: rsm common Group Enable
This pulse enables the eight RMS reconfiguration pulses.
F3: cross RTG Reset
This pulse is used to resync the Y, Z, 100 MS, and 1 SEC counters
in the RTG. This pulse resets the 100 MS and the 1 SEC counter in
the CLU in which it is executed. If the Cross RTG Enable latch is
set in the other CLU, all four counters will also be reset in that
CLU at time Y1 in RRJ slot O, therefore resyncing the two
RTG's.
F4: reset DMC latch in RMU
This pulse is used to reset the Disable Matrix Connection (DMC)
latch in the RMU. See E4.
The following is a list of direct control latch assignments by
bit:
G 1 to G 4: Unassigned
H1: monitor High State 1
Used for clock routining.
H2: monitor Low State 1
See H1
H3: monitor High State 2
See H1
H4: monitor Low State 2
See H1
I1 to I3 Unassigned
I4 cross RTG RST Enable
This latch enables the cross write reset function from the other
CLU to reset the Y, Z, 100 MS, and 1 SEC counters in the RTG in
order to sync the TWO CLU's. This enable is required in order to
avoid a fault in one CLU affecting the other CLU. This latch must
be set prior to executing the Cross RTG RESET DIR. CON. pulse, in
the other CLU.
J1: select Even RJM Groups
For the CLU within which this latch is set, scanned signals from
the even-numbered RJM Groups (0,2,4,&6) are gated into the RCC
logic.
J2: select Odd RJM Groups
As J1 except for Odd-numbered RJM Groups (1, 3, 5 & 7)
J3: select Even RSM Files
For the CLU within which this latch is set, scanned signals from
the even numbered RSM files (2,4,6, & 8) are gated into the RCC
logic.
J4: select Odd RSM Files
As J3 except for odd-numbered files (1, 3, 5 & 7)
K1: busy Out RRJ Group (0, 4)
Setting this latch in CLU-A forces RRJ Group 0 to appear busy to
the Markers; setting it in CLU-B, RRJ Group 4 appears busy.
K2: busy Out RRJ Group (1,5)
As K1 except relates to RRJ Groups 1 and 5.
K3: unassigned
K4: busy out RRJ Group (2, 6)
As K1 except relates to RRJ Groups 2 and 6.
L1: busy Out RRJ Group (3, 7)
As K1 except relates to RRJ Groups 3 and 7.
L2: routine W Generator
This latch is used to routine error and fault detection circuitry
of the W generator in the RTG.
L3: routine X Generator.
As L2 except for X generator.
L4: unassigned
The 202nd RRJ slot is treated in a special way by the RMU in order
to control these pulse and latch signals. The ninth & tenth
words, 5A and 5B, of this slot are directly associated with the
pulse and latch assignments given above, the letter number
designation for each assignment referring to the bit position in
the fifth memory row.
Any combination of pulses can be generated in the following
way:
1. The bit positions corresponding to the pulses to be generated
are set to 1 and all other pulse associated bits are set to 0.
2. The desired CPD, 101, 102, 103, is generated when the RS is in a
slot other than the 202nd.
During the RS's next scan of the fifth row of the 202nd RRJ slot,
the RMU will generate pulses corresponding to the 1 found in
memory.
Any combination of latches may be set or reset in the following
way:
1. All bit positions corresponding to the latches are put into the
1 state if the desired final state of the latch is to be set or
into the 0 state if the desired final state is to be reset. All
bits must be appropriately set.
2. The desired CPD, 201, 202, or 203, is generated when the RS is
in a slot other than the 202nd.
During the RS's next scan of the fifth row of the 202nd RRJ slot,
the RMU will set or reset the latches as given by the state of the
associated bits.
From an RS hardware point of view, contradictory commands should
not be given simultaneously; for example, executing the A1 bit
command in both CLU's.
Section 5.0 computer third party
the computer third party will be described in a separate patent
application.
Section 6.0 computer programing console
6.1 introduction
The Computer Programing Console (PRC) is a modified version of the
PNL (Computer Maintenance Panel) and is designed for use in the
field for the initial debug of a Central Processor and for the
localization of Faults or errors that cannot be handled through
diagnostic routines. Except for the DDT features, the PRC is
designed primarily to be used on the OFF LINE CCP. The PRC is
cabled to both central processors but being a simplex unit, it
monitors only one CCP, hence, the CCP to be monitored and/or
controlled is dictated by the settings of the Directional Switches.
All signals leaving the PRC are primed when the PRC is enabled and
the Directional Switch is pointing to an OFF LINE Central
Processor. If the Directional Switch is pointing to an ON LINE CCP,
these signals are automatically locked out of, and cannot enter,
the ON LINE CCP.
The Data Bus and Address Bus is displayed and the bus source is
controlled via panel switches. Internal indicators of the Central
Processor being monitored are displayed whenever the Programing
Console is powered up. Entry into and display of, the memory can be
executed via panel switches. Loading of the Program Counter and
Page Register can be executed via panel switches. Instructions may
be processed in increments of Levels (500 n.s.) or "Stepped" thru
complete instructions.
The Timing Generator may be pulsed in 100 n.s. increments. A match
address stop feature can be implemented via the thumb-wheel
switches. A LEVEL ONE INTERRUPT on addressmatch can also be
generated via the Dynamics Debug Tool (DDT) circuitry and the
thumbwheel switches.
6.2 Panel and Operational Description
6.2.1 Panel Display Lamps and Indicators:
All lamps used in the PRC are pre-heated via a resistor to ground
to reduce the switched inrush current and prolong the lamp's life.
When lit, the lamps indicate the "true" condition.
6.2.1.1 Data Bus Lamps
There are 26 Data Bus Lamps, each one mirroring the 24 bits of the
Data Bus, plus the Parity Bit and the Memory Protect Bit associated
with the Data Bus. The Lamps are arranged in 8 columns of 3 bits
each, weighted 4,2,1 from top to bottom. A ninth column consists of
2 bits representing the Parity Bit and the Memory Protect bit.
6.2.1.2 Address Bus Lamps
There are 18 Address Bus Lamps. Each are mirroring the 17 bits of
the Address Bus plus a parity bit associated with the Address Bus.
There are 5 columns of 3 bits each, weighted 4,2,1 from top to
bottom. A sixth row contains 2 bits weighted 2,1 from top to bottom
and a seventh row contains the parity bit.
6.2.1.3 COMPUTER ERROR: Indicates one of the following errors has
occurred.
6.2.1.3.1 Instruction Even Parity Error
6.2.1.3.2 Data Even Parity Error
6.2.1.3.3 Division by Zero
6.2.1.3.4 Invalid Operation Code
6.2.1.3.5 Memory Reference Time Out
6.2.1.3.6 Port 7 Error
6.2.1.4 CCPA ON LINE: Indicates on line status of CCPA.
6.2.1.5 ccpa clk: indicates condition of the Interval Timing
Generator of Central Processor "A".
6.2.1.6 ccpb on line: indicates on line status of CCPB.
6.2.1.7 ccpb clk: indicates condition of the Internal Timing
Generator of Central Processor "B".
6.2.1.8 ctp on line: indicates on line status of the Computer Third
Party.
6.2.1.9 HALT: Indicates when true, that a Halt Instruction has just
been processed.
6.2.1.10 INT. DISABLE: Indicates that no Interrupts will be
recognized during this interval.
6.2.1.11 PULSE 1: This indicator, when lit, defines the progress of
the timing generator through PULSE 1.
6.2.1.12 pulse 2: this indicator, when lit, defines the progress of
the timing generator through PULSE 2.
6.2.1.13 pulse 3: this indicator, when lit, defines the progress of
the timing generator thru PULSE 3.
6.2.1.14 pulse 4: this indicator, when lit, defines the progress of
the timing generator thru PULSE 4.
6.2.1.15 pulse 5: this indicator, when lit, defines the progress of
the timing generator thru PULSE 5.
6.2.1.16 level 1: this indicator, when lit, defines the progress of
the timing generator thru LEVEL 1.
6.2.1.17 level 2: this indicator, when lit, defines the progress of
the timing generator thru LEVEL 2.
6.2.1.18 level 3: this indicator, when lit, defines progress of the
timing generator thru LEVEL 3.
6.2.1.19 level 4: this indicator, when lit, defines progress of the
timing generator thru LEVEL 4.
6.2.1.20 cycle 1: this indicator, when lit, defines the progress of
the timing generator thru CYCLE 1.
6.2.1.21 cycle 2: this indicator, when lit, defines progress of the
timing generator thru CYCLE 2.
6.2.1.22 cycle 3: this indicator, when lit, defines progress of the
timing generators thru CYCLE 3.
6.2.1.23 latch db: this indicator, when lit, indicates that the
data bus is primed to latch up. Each bit of the Data Bus that is
true will remain true during this interval. Therefore care must be
taken during a pulse or increment operation. Should the DATA SOURCE
SWITCH be activated while the lamp is lit, an "OR" ing effect will
take place and additional bits other than the instruction intended
will be set and latched up.
6.2.1.24 LATCH AB: This indicator when lit, indicates that the
address Bus is primed to latch up. Each bit of the Address Bus that
is true will remain true during this interval. Therefore care must
be taken. Should the ADDRESS SOURCE SWITCH be activated while the
lamp is lit, an "OR"ing effect will take place and additional bits
other than the instruction intended will be set and latched up.
6.2.1.25 WMPB: This indicator when lit indicates that the storage
element WMPB is set. (Refer to Section 1.2 MPS)
6.2.1.26 page register lamps: there are 6 Page Register Lamps
arranged in a single row. Each lamp represents a bit in the Page
Register.
6.2.2 Display Source Swtiches: The following switches are alternate
action push buttons. They are backlighted when depressed.
6.2.2.1 BUS: When depressed, these switches will prime a signal to
the Central Processor to allow whatever has been logically selected
by the CCP hardware, on to the Data Bus and/or the Address Bus.
6.2.2.2 DR: When depressed, this switch will prime a signal to the
Central Processor to allow the Data Register of the selected memory
on to the Data Bus.
6.2.2.3 IR: When depressed, this switch will prime a signal to the
Central Processor to allow the Instruction Register of the Central
Processor on to the Data Bus.
6.2.2.4 "A": When depressed, this switch will prime a signal to the
Central Processor to allow the "A" Register of the Central
Processor on to the Data Bus.
6.2.2.5 "Q": When depressed, this switch will prime a signal to the
Central Processor to allow the "Q" Register of the the Central
Processor on to the Data Bus.
6.2.2.6 "X1": When depressed, this switch will prime a signal to
the Central Processor to allow the "XL" (Index Register 1) of the
Central Processor on to the Data Bus.
6.2.2.7 "X2": When depressed, this switch will prime a signal to
the Central Processor to allow "X2" (Index Register 2) of the
Central Processor on to the Data Bus.
6.2.2.8 "X3": When depressed, this switch will prime a signal to
the Central Processor to allow the "X3" (Index Register 3) on to
the Data Bus.
6.2.2.9 "DS": When depressed, this switch will prime a signal to
the Central Processor to allow "DS" (Data Switch Register) of the
Computer Programing Console on to the Data Bus.
6.2.2.10 "SG" When depressed, this switch will prime a signal to
the Central Processor to allow the "SG" (Sense Group Selected) of
the Central Processor on to the Data Bus. The group to be displayed
must be entered into the Data Switch Register bits 9 through 14.
(Should the IR register's OP Code contain a SSNT instruction (07),
the sense lines of the group selected will be inverted).
6.2.2.11 "S": When depressed, this switch will prime a signal to
the Central Processor to allow the "S" (Sum Register) of the
Central Processor on to the Data Bus.
6.2.2.12 "CCX": When depressed, this switch will prime a signal to
the Central Processor to allow the "CCX" Computer Channel Matrix of
the Central Processor on to the Data Bus.
6.2.2.13 "DIAG": When depressed, this switch will prime a signal to
the Central Processor to allow the "DIAG" (Diagnostic Register) of
the Third Party on to the Data Bus.
6.2.2.14 "SC": When depressed, this switch will prime a signal to
the Central Processor to allow the "SC" (Shift Counter -- 6 bits)
of the Central Processor on to the Data Bus.
6.2.2.15 "PC": When depressed, this switch will prime a signal to
the Central Processor to allow the "PC" (Program Counter) and the
instruction field of the Page Register, of the Central Processor on
to the Address Bus.
6.2.3 Panel Control
6.2.3.1 The following switches are alternate action push buttons
and are backlighted when depressed.
6.2.3.1.1 "LAMPTEST": When depressed, this switch will activate all
display lamps on the panel.
6.2.3.1.2 "ENABLE" When depressed, this switch will prime all
outgoing signals of the Computer Programing Console. When not
depressed, all signals leaving the Computer Programing Console are
inhibited.
6.2.3.1.3 "MATCH A" When depressed, this switch will enable the
address matching circuitry of the PRC. When an address on the
Address Bus coincides with the address dialed into Address Switch A
during an instruction fetch, a stop clock is effected.
6.2.3.1.4 "MATCH B" Function is identical to item 6.2.3.1.3 but
uses Address Switch B.
6.2.3.1.5 "match c" function is identical to item 6.2.3.1.3 but
uses Address Switch C.
6.2.3.1.6 "breakpoint a" when depressed this switch will prime the
matching circuitry of the PRC. If the DDT circuitry in the PRC is
enabled via CPD instructions and a match occurs between the Address
Bus and the address dialed into Address Switch A during an
instruction fetch, an interrupt Level One is generated.
6.2.3.1.7 "BREAKPOINT B" Function is identical to item 6.2.3.1.6
but uses address switch B.
6.2.3.1.8 "breakpoint c" function is identical to item 6.2.3.1.6
but uses Address Switch C.
6.2.3.1.9 "s-match" when depressed, this switch will prime the
matching circuitry of the PRC. If the DDT circuitry of the PRC is
enabled via CPD instructions and a match occurs between the "S"
Register and the address dialed into "Address Switch C" when the S
Register contained the final effective address, an Interrupt Level
One is generated.
6.2.4 Instruction and Memory Manipulation Control. The following
named switches are momentary action and are not backlighted.
6.2.4.1 PULSE: This switch will guide the timing generator thru its
paces one pulse at a time.
6.2.4.2 INCREMENT: This switch will guide an instruction thru its
paces one level at a time. 1 level = 5 pulses.
6.2.4.3 STEP: This switch will guide a program thru its paces one
instruction at a time. It also acts as a STOP pushbutton when the
CCP is in the RUN MODE.
6.2.4.4 run: this switch will allow a normal flow of instructions
at the maximum rate.
6.2.4.5 MASTER CLEAR: This switch will prime a signal to the
Central Processor that will clear all necessary storage elements
and logic.
6.2.4.6 EXECUTE: This switch will execute from the Panel any
instruction that has been dialed up on the Data Switch Register
Buttons (DSR).
6.2.4.7 display: this switch will display memory locations as
selected by the program counter. The program counter will be
incremented once for each display so that a consecutive number of
locations can be viewed without selecting a new address.
6.2.5.8 ENTER: This switch will enter data dialed up into the DSR
into the memory location specified by the program counter and will
increment the program counter by one for each entry. Thus,
successive locations of memory can be entered without selecting a
new address.
6.2.5.9. LOAD PC: This switch will enter the 15 least significant
bits of the DSR into the Program Counter, and will load bits 15
thru 18 into the Page Register.
6.2.5.10 DATA CLEAR: This switch resets the DSR to all zeros.
6.2.5.11 DATA SWITCH REGISTER (DSR) SWITCHES: These eight switches
will generate a 3 bit BCD code which is fed into the DSR.
Depressing any of the eight buttons (0 thru 7) will enter that
number into the last significant digit of the DSR after shifting
all digits to the next highest significant digit.
6.2.6 "DIRECTIONAL SWITCHES": Two lever key switches are used to
dictate the CCP to be monitored and/or controlled. It is possible
to output to and receive from either CCP, or output to both and
receive from one CCP.
6.2.7 address Switches: The following are thumbwheel switches. Each
wheel within a module is registered 0-7 and will generate a BCD
code for the digit selected.
6.2.7.1 "ADDRESS SWITCH A" This thumbwheel module contains six
wheels and is used for MATCH A and BREAKPOINT A functions.
6.2.7.2 "ADDRESS SWITCH B" Same as item 6.2.7.1 but used for MATCH
B and BREAKPOINT B functions.
6.2.7.3 "ADDRESS SWITCH C" Same as item 6.2.7.1 but used for MATCH
C and BREAKPOINT C and S-MATCH functions.
7.0 COMPUTER LINE SYNCHRONIZER
7.1 introduction
The transferring of information between the Central Processor and
the systems with which it communicates, is done either directly (as
with the Register Senders) or via control interfaces (such as the
communication register via the channel multiplexor or the drum
system via the Computer Memory Control). When these systems require
services, such as transferring data, they alert the central
processor to their need via the Interrupt and/or Sense Line System.
Although the Central Processors are in sync with each other and the
other duplicated systems may be in sync with themselves, there is
no synchronization between the systems. Because of this, the
Computer Line Synchronizer circuit was implemented in order to sync
up all request signals that are external to the Central
Processor.
7.2 Operational Description
7.2.1 Normal
Each external signal that is to be sensed by the Central Processor
is assigned to a sync hold circuit. These signals are considered
"hot" and under the direct control of the system which stimulates
them. The Central Processor has no direct control over them and
they are subject to change at any time. Since they are a single
source signal, and the signal, once received by the CLS must be
distributed over two separate paths to the duplicated Sense Lines
and/or Interrupts, the possibility exists that one Sense line
system may "see" a signal at a "point in time," while the other
system has not yet received the signal. If during that "Point in
time," the Central Processor Monitors the sense line system a
mismatch may occur, placing the CCP(s) out of sync. The purpose of
the sync hold circuit therefore, is to freeze, or temporarily store
the "Hot" signal for a period of time. This period of time allows
for propagation to the duplicated Sense Lines, thus a mismatch will
not occur due to a changing signal. This storage takes place every
500 nano seconds.
The Sync Hold circuit distributes the stored signals to the
duplicated Interrupt and Sense Line system.
7.2.2 Control
As stated previously, the CLS is a simplex unit, but must be
controlled, by a duplexed CCP. If both CCP(s) are on line (running
in sync) the control signals are "or(ed)" together in both halves
of the simplex CLS. If only one CCP is on line, only the signals
from that CCP will be used to control both halves of the CLS. If
both CCP(s) are off line then the "A" half of the CLS is controlled
by CCPA and the "B" half is controlled by CCPB.
7.2.3 error Detection
The signal IS SYNC from each CCP is commoned to both halves of the
CLS. Where this signal is faulted true, the hardware of one of the
CLS units would recognize the fact, set a storage element SYNC ERR
and lockout the faulted signals from both halves of the CLS. The
storage element SYNC ERR1 is assigned to sense line 04404 and when
true indicates that the IS SYNC or P1 signal from CCPB is faulted
true. The storage element SYNC ERR 2 is assigned to sense line
04410 and when true indicates that the IS SYNC or P1 signal from
CCPA is faulted true.
The signal Pulse 1 (P1) is used to detect the IS SYNC fault. If it
should fault true the same events will occur as in the case of IS
SYNC fault. Also, as a side effect, which is not predictable
another storage element CLS CONT ERR may be set. The sense lines
associated with this condition are 04500 and 04600.
The CPD CPL STROBE to the CLP is checked for a stuck-at-one
condition. Should it occur a storage element is set called CPD CLR
ERR 1 and/or 2. The sense lines associated with these storage
elements are 04420 and 04440 respectively. The offending signal
will also be locked out of both halves of the CLS.
The fourth detection occurs where an IS SYNC signal does not
function within a unit of the CLS. The signal may be faulted true
or false.
In either case the ability to monitor the external systems
associated with that unit of the CLS has been lost. Should this
case occur the storage elements CLS CONT ERR 1 and 2 will be set.
The sense lines associated with these storage elements are 04500
and 04600.
These faults having been processed by the detection hardware are
now considered latent and will be recognized by the CCP(s) via
Interrupt level 8. They are considered latent because the system is
not down without them. 7.2.3 Hardware maintenance is via CPD
instructions that are decoded in each half of the CLS simplex
circuit. The maintenance possible covers not only the CLS but the
Interrupt and Sense Line system as well add is explained in section
1.5.4.
Section 8.6 watchdog timer operation
in every computing system there exists the possibility of the
system entering a closed loop and not exiting. This may be due to a
hardware or software fault. In the No. 1 EAX system this problem is
overcome through the use of a watchdog timer. The watchdog or
interval timer employed in the EAX Central Processor contains two
separate time intervals.
The two timing intervals have the following relation: Operation
The normal operation of the watchdog timer consists of the
following sequence of steps. The timer is running only when its
associated CCP is on-line.
1. The watchdog must be enabled, via the MIS instruction, Enable
Watchdog (ENWD) 3704000), and then disabled via the MIS INSTRUCTION
reset watchdog (RWD) (3710000), after the minimum time of T1 (1.4
seconds). To insure that time T1 has been completed, the sense
lines WDT2 from CCPA and CCPB must be tested (07404 and 07410).
When both are true, the CCP's watchdog timer are in time interval
T2.
When the CCP's are not in sync (one or both off line), the WDT2
sense line from the off-line CCP will appear true.
This was implemented so that the method of checking for a WDT2
signal need not vary because of configuration. The off-line CCP's
WDT2 signal will not reflect the actual condition that exists in
the watchdog.
Errors
If the above sequence is violated, a watchdog time out is
initiated. The conditions which cause a violation are:
1. Interval T2 times out.
2. An attempt to enable or reset during T1.
3. resetting the timer before it has been enabled.
4. Enabling the timer after it has been previously enabled and
before it has been reset.
Resynchronizing Duplex Watch Dog Timers
When the CCP's are to be returned to duplex operation the following
procedure must be followed.
The on-line CCP must either clear the off-line computer
(accomplished via the Diagnostic access, (see section 5.0), or it
must initiate the off-line machine to execute the Resync Watch Dog
instruction (SYNC) (3740000). After this has been accomplished, the
on-line CCP must execute the same (SYNC) instruction immediately
prior to resynchronizing both CCP's with the Resync CPD instruction
(SYNC CPD) (01732122).
______________________________________ SECTION 8.3 Sense Line
Assignments An asterisk(*) indicates undefined sense lines Computer
Internal Indicators (Group 1) 81001 BTR SHC Branch Trace Indication
(a branch has occurred) 01002 BKP SHC Break Point Indication (an
address, as dialed up on the break point switch, has been
referenced during an instruction access) 01004 S MATCH SHC Register
S Match Indication (An address as dialed up on the S break print
switch has been referenced during a data access) 01010 PEP 7 Port 7
Error or CP, CMC port error 01020 IEPE Instruction Parity Error
01040 DEPE Data Parity Error 01100 RS25 Register-Sender Bit 25
01200 WMPB Write Memory Protect Bit Computer Internal Indicators
(Group 2) 02001 T1 Storage Element for 2MS Timer T1 in 3rd. Party
02002 DDT ON LINE MODE DDT Panel Sw. Mode 02004 INVOP Invalid
Operation Code 02010 DIVZ Division by Zero 02020 MRTO Main Memory
Request Time Out 02040 RSTO Register-sender Request Time Out 02100
WDTO Watch Dog Timer Out 02200 CAR Carry Out of Adder Bit 23 Stored
Maintenance Control Console (Group 3) 03001 SRECON Configuration
Panel Interrupt 03002 SMAJ PALM Major Power Alarm 03004 SMIN PALM
Minor Power Alarm 03010 STTY1 Maintenance Teletypewriter Input
Request Interrupt 03020 STTY2 Office Administration Teletypewriter
Input Request Interrupt 03040 WK AREA INT Request for a Programed
Work Area Audit 03100 MDB CONF Maintenance Device Buffer
Configuration 03200 MDCF CONF Maintenance Display and Control Frame
Power Failure Terminating Markers 1 and 2 (Group 4) 04001 SSTTMON
On Line 04002 SSTTMOL1 Off Line 04004 SSTTMSLI1 Initiate Send or MR
LATCH 04010 SSTTMCA1 Clock Alarm 04020 SSTTMON2 On Line 04040
SSTTMOL2 Off Line 04100 SSTTMSLI2 INITIATE SEND or MR LATCH 04200
SSTTMCA2 Clock Alarm Terminating Marker 3 and 4 (Group 5) 05001
SSTTMON3 On Line 05002 SSTTMOL3 Off Line 05004 SSTTMSLI3 INITIATE
SEND or MR LATCH 05010 SSTTMCA3 Clock Alarm 05020 SSTTMON4 On line
05040 SSTTMOL4 Off Line 05100 SSTTMSLI4 INITIATE SEND or MR LATCH
05200 SSTTMCA4 Clock Alarm Terminating Marker 5 and 6 (Group 6)
06001 SSTTMON5 On Line 06002 SSTTMOL5 Off Line 06004 SSTTMSLI5
INITIATE SEND or MR LATCH 06010 SSTTMCA5 Clock Alarm 06020 SSTTMON6
On Line 06040 SSTTMOL6 Off Line 06100 SSTTMSLI6 INITIATE SEND or MR
LATCH 06200 SSTTMCA6 Clock Alarm Terminating Marker Malfunction
Alarms and CCX ERROR Group 7 07001 SSTTMAL1 07002 SSTTMAL2 07004
SSTTMAL3 07010 SSTTMAL4 07020 SSTTMAL5 07040 SSTTMAL6 07100 CCX
ERR1 07200 CCX ERR2 Originating Marker 1 and 2 (Group 9) 11001
SSTOMON1 On Line 11002 SSTOMOL1 Off Line 11004 SSTOMSLI1 INITIATE
SEND or MR LATCH 11010 SSTOMCA1 Clock Alarm 11020 SSTOMON2 On Line
11040 SSTOMOL2 Off Line 11100 SSTOMSLI2 INITIATE SEND or MR LATCH
11200 SSTOMCA2 Clock Alarm Originating Marker 3 and 4 (Group 10)
12001 SSTOMON3 On Line 12002 SSTOMOL3 Off Line 12010 SSTOMSLI3
INITIATE SEND or MR LATCH 12004 SSTOMCA3 Clock Alarm 12020 SSTOMON4
On Line 12040 SSTOMOL4 Off Line 12100 SSTOMSLI4 INITIATE SEND or MR
LATCH 12200 SSTOMCA4 Clock Alarm Originating Marker 5 and 6 (Group
11) 13001 SSTOMON5 On Line 13002 SSTOMOL5 Off Line 13004 SSTOMSLI5
INITIATE SEND or LATCH 13010 SSTOMCA5 Clock Alarm 13020 SSTOMON6 On
Line 13040 SSTOMOL6 Off Line 13100 SSTOMSLI6 INITIATE SEND or MR
LATCH 13200 SSTOMCA6 Clock Alarm Originating Marker 7 and 8 (Group
12) 14001 SSTOMON7 On Line 14002 SSTOMOL7 Off Line 14004 SSTOMSLI7
INITIATE SEND or MR LATCH 14010 SSTOMCA7 Clock Alarm 14020 SSTOMON8
On Line 14040 SSTOMOL8 Off Line 14100 SSTOMSLI8 INITIATE SEND or MR
LATCH 14200 SSTOMCA8 Clock Alarm Originating Marker Malfunction
Alarms (Group 13) 15001 SSTOMAL1 15002 SSTOMAL2 15004 SSTOMAL3
15010 SSTOMAL4 15020 SSTOMAL5 15040 SSTOMAL6 15100 SSTOMAL7 15200
SSTOMAL8 Originating Marker Stand By (Group 14) 16001 SSTOMSB1
16002 SSTOMSB2 16004 SSTOMSB3 16010 SSTOMSB4 16020 SSTOMSB5 16040
SSTOMSB6 16100 SSTOMSB7 16200 SSTOMSB8 Originating Marker Idle/Busy
(Group 15) 17001 SSTOMIB1 17002 SSTOMIB2 17004 SSTOMIB3 17010
SSTOMIB4 17020 SSTOMIB5 17040 SSTOMIB6 17100 SSTOMIB7 17200
SSTOMIB8 Terminating Marker Idle/Busy (Group 17) 21001 SSTTMIB1
21002 SSTTMIB2 21004 SSTTMIB3 21010 SSTTMIB4 21020 SSTTMIB5 21040
SSTTMIB6 21100 * 21200 * Register Sender: Fault and RFT (Group 18)
22001 SRS FAULT Register-Sender Fault 1A 22002 STS FAULT 2
Register-Sender Fault 1B 22004 SRS FAULT 3 Register-Sender Fault 2A
22010 SRS FAULT 4 Register-Sender Fault 2B 22020 SRS RFT 1
Register-Sender RFT 1A Request for Translation 22040 SRS FRT 2
Register-Sender RFT 1B 22100 SRS FRT 3 Register-Sender RFT 2A 22200
SRS RFT 4 Register-Sender RFT 2B Register Sender System Trouble and
Error Count (Group 19) 23001 SRS SYTTRB1 Register-Sender 1A System
Trouble 23002 SRS SYTTRB2 Register-Sender 1B System Trouble 23004
SRS SYTTRB3 Register-Sender 2A System Trouble 23010 SRS SYTTRB4
Register-Sender 2B System Trouble 23020 SRS ERRCNT1 Register-Sender
1A Error Count 23040 SRS ERRCNT2 Register-Sender 1B Error Count
23100 SRS ERRCNT3 Register-Sender 2A Error Count 23200 SRS ERRCNT4
Register-Sender 2B Error Count Register Sender 1A (Group 20) 24001
SCCPA SELECTED1 CONFIGURED TO CCP-A 24002 SCCPB SELECTED1
CONFIGURED TO CCP-B 24004 RUN SIMPLEX SELECTED1 NOT SYNCING CLP
SIGNALS WITH RS 1B 24020 SRS SL41 * 24010 SRS SL31* * 24040 SRS
SL51 24100 SRS SL61 * 24200 SRS SL71 Register Sender 1B (Group 21)
25001 SCCPA SELECTED2 25002 SCCPB SELECTED2 SIMILAR TO GROUP 20
25004 RUN SIMPLEX SELECTED 2 25010 SRS SL32 * 25020 SRS SL42 *
25040 SRS SL52 * 25100 SRS SL62 * 25200 SRS SL72 * Register Sender
2A (Group 22) 26001 SCCPA SELECTED 3 26002 SCCBP SELECTED 3 SIMILAR
TO GROUP 20 26004 SRUN SIMPLEX SELECTED3 26010 SRS SL33 * 26020 SRS
SL43 * 26040 SRS SL53 * 26100 SRS SL63 * 26200 SRS SL73 * Register
Sender 2B (Group 23) 27001 SCCPA SELECTED 4 27002 SCCPB SELECTED 4
SIMILAR TO GROUP 20 27004 SRUN SIMPLEX SELECTED4 27010 SRS SL34 *
27020 SRS SL44 * 27040 SRS SL54 * 27100 SRS SL64 * 27200 SRS SL74 *
Register-Sender 1A & 2A (Group 25) 31001 RJM NORM SCAN CONFIG 1
31002 RSM NORM SCAN CONFIG 1 31004 RJM NORM DIST CONFIG 1 REFER TO
SECTION 4.0 FOR EXPLANATION 31010 RSM NORM DIST CONFIG 1 31020 RJM
NORM SCAN CONFIG 3 31040 RSM NORM SCAN CONFIG 3 31100 RJM NORM DIST
CONFIG 3 31200 RSM NORM DIST CONFIG 3 Register-Sender 1B & 2B
(Group 26) 32001 RJM NORM SCAN CONFIG 2 32002 RSM NORM SCAN CONFIG
2 32004 RJM NORM DIST CONFIG 2 32010 RSM NORM DIST CONFIG 2 REFER
TO SECTION 4.0 FOR EXPLANATION 32020 RJM NORM SCAN CONFIG 4 32040
RSM NORM SCAN CONFIG 4 32100 RJM NORM DIST CONFIG 4 32200 RSM NORM
DIST CONFIG 4 Register-Sender 1B & 2B (Group 27) 33001 * 33002
* 33004 * 33010 * 33020 * 33040 * 33100 * 33200 * Register-Sender
1B & 2B (Group 28) 34001 BAD PARITY SET 34002 CLP POWER DOWN
34004 * 34010 * 34020 * 34040 * 34100 * 34200 *
CCR & DCU ERR INT. (Group 29) 35001 SCR ERR1 COMMUNICATION
REGISTER A ERROR INTERRUPT 35002 SCRA ERR2 COMMUNICATION REGISTER B
ERROR INTERRUPT 35004 SDCUERROR1 DCU ERROR INT 1 35010 SDCUERROR2
DCU ERROR INT 2 35020 SDCUERROR3 DCU ERROR INT 3 35040 SDCUERROR4
DCU ERROR INT 4 35100 SDCUERROR5 DCU ERROR INT 5 35200 SDCUERROR6
DCU ERROR INT 6 DCU 1 Sense Lines (Group 30) 36001 SDCU IDLE1 All
DCU and DMS registers are reset and both the DCU and DMS are
otherwise ready to accept an initialize command from the CCP. 36002
SDCU ON LINE1 The DCU is on-line. Set and reset by CPD. 36004 SDCU
CORE ACC1 The DCU had trouble accessing the CMC. 36010 SDMS RDY1
The Drum power sequencing is complete and Drum speed is within
operating range. 36020 SDMS CLK TRACK ERROR 1 The Drum clock track
circuits have detected an error. This is one of the error
conditions that causes ERROR to become true. 36040 SDCU INIT1 DCU
is using the Initialization Table in Core. 36100 SDCU TIME OUT1
Begins on Spill or Initialize CPD. Time out in 23 drum revolutions
if no READY or ERROR interrupt occurs and if no MALFUNCTION is
received from the CMC. 36200 SCDU ERR-STATUS Error termination
sequence WAS IN CORE1 completed. DCU 2 Sense Lines (Group 31) 37001
SDCU IDLE2 37002 SDCU ON LINE2 37004 SDCU CORE ACC2 Similar to
Group 30 37010 SDMS RDY2 37020 SDMS CLK TRACK ERROR 2 37040 SDCU
INIT2 37100 SDCU TIME OUT 2 37200 SDCU SL72 DCU 3 Sense Lines
(Group 33) 41001 SDCU IDLE3 41002 SDCU ON LINE3 41004 SDCU CORE
ACC3 41010 SDMS RDY3 Similar to Group 30 41020 SDMS CLK TRACK ERROR
3 41040 SDCU INIT3 41100 SDCU TIME OUT3 41200 SDCU ERR-STATUS IN
CORE3 DCU 4 Sense Lines (Group 34) 42001 SDCU IDLE4 42002 SDCU ON
LINE4 42004 SDCU CORE ACC4 42010 SDMS RDY4 Similar to Group 30
42020 SDMS CLK TRACK ERROR 4 42040 SDCU INIT4 42100 SDCU TIME OUT4
42200 SDCU ERR STATUS IN CORE 4 DCU 5 Sense Lines (Group 35) 43001
SDCU IDLES 43002 SDCU ON LINE 5 43004 SDCU CORE ACC5 43010 SDMS
RDY5 Similar to Group 30 43020 SDMS CLK TRACK ERROR 5 43040 SDCU
INIT5 43100 SDCU TIME OUT5 43200 SDCU ERR STATUS IN CORE 5 DCU 6
Lines (Group 36) 44001 SDCU IDLE6 44002 SDCU ON LINE6 44004 SDCU
CORE ACC6 44010 SDMS RDY6 Similar to Group 30 44020 SDMS CLK TRACK
ERROR 6 44040 SDCU INIT6 44100 SDCU TIME OUT 6 44200 SDCU ERR
STATUS IN CORE 6 CCR and DCU RDY (Group 37) 45001 SCR RDY SL 1 CCRA
RDY 45002 SCR RDY SL 2 CCRB RDY 45004 SDCU RDY 1 DCU1 RDY 45010
SDCU RDY 2 DCU 2 RDY 45020 SDCU RDY 3 DCU 3 RDY 45040 SDCU RDY 4
DCU 4 RDY 45100 SDCU RDY 5 DCU 5 RDY 45200 SDCU RDY 6 DCU 6 RDY CCR
1 Sense Lines (Group 38) 46001 SCCR SL01 CCR Initialized 46002 SCCR
SL11 SEL STRB 2 LATCH 46004 SCCR SL Parity OK LATCH 46010 SCCR SL31
Error Sense 46020 SCCR SL41 CCR Connected 46040 SCCR SL51 On Line
Active 46100 SCCR SL61 On Line Standby 46200 SCCR SL71 * CCR 2
Sense Lines (Group 39) 47001 SCCR SL02 47002 SCCR SL12 47004 SCCR
SL22 47010 SCCR SL32 Similar to Group 38 47020 SCCR SL42 47040 SCCR
SL52 47100 SCCR SL62 47200 SCCR SL72 Channel Ready (Group 41) 51001
SC RDY SL01 Channel 1 Ready 51002 SC RDY SL13 Channel 3 Ready 51004
SC RDY SL25 Channel 5 Ready 51010 * 51020 SC RDY SL49 Channel 9
Ready 51040 SC RDY SL511 Channel 11 Ready 51100 SC RDY SL613
Channel 13 Ready 51200 SC RDY SL715 Channel 15 Ready Channel Ready
(Group 42) 52001 SC RDY SL02 Channel 2 Ready 52002 SC RDY SL14
Channel 4 Ready 52004 SC RDY SL26 Channel 6 Ready 52010 * 52020 SC
RDY SL410 Channel 10 Ready 52040 SC RDY SL512 Channel 12 Ready
52100 SC RDY SL614 Channel 14 Ready 52200 SC RDY SL716 Channel 16
Ready Channel Error (Group 43) 53001 SC ERR1 Channel 1 Error 53002
SC ERR3 Channel 3 Error 53004 SC ERR5 Channel 5 Error 53010 * 53020
SC ERR9 Channel 9 Error 53040 SC ERR11 Channel 11 Error 53100 SC
ERR13 Channel 13 Error 53200 SC ERR15 Channel 15 Error Channel
Error (Group 44) 54001 SC ERR2 Channel 2 Error 54002 SC ERR4
Channel 4 Error 54004 SC ERR6 Channel 6 Error 54010 * 54020 SC
ERR10 Channel 10 Error 54040 SC ERR12 Channel 12 Error 54100 SC
ERR14 Channel 14 Error 54200 SC ERR16 Channel 16 Error Channel
ON/OFF LINE (Group 45) 5501 SC ON LINE1 Channel 1 ON LINE 55002 SC
ON LINE3 Channel 3 ON LINE 55004 SC ON LINE5 Channel 5 ON LINE
55010 SC ON LINE7 Channel 7 ON LINE 55020 SC ON LINE9 Channel 9 ON
LINE 55040 SC ON LINE11 Channel 11 ON LINE 55100 SC ON LINE13
Channel 13 ON LINE 55200 SC ON LINE15 Channel 15 ON LINE Channel
ON/OFF LINE (Group 46) 56001 SC ON LINE2 Channel 2 ON LINE 56002 SC
ON LINE4 Channel 4 ON LINE 56004 SC ON LINE6 Channel 6 ON LINE
56010 SC ON LINE8 Channel 8 ON LINE 56020 SC ON LINE10 Channel 10
ON LINE 56040 SC ON LINE12 Channel 12 ON LINE 56100 SC ON LINE14
Channel 14 ON LINE 56200 SC ON LINE16 Channel 16 ON LINE Channel
Time Out (Group 47) 57001 STOERR 1 Channel 1 Time Out Error 57002
SCTOERR 3 Channel 3 Time Out Error 57004 SCTOERR 5 Channel 5 Time
Out Error 57010 SCTOERR 7 Channel 7 Time Out Error 57020 SCTOERR 9
Channel 9 Time Out Error 57040 SCTOERR 11 Channel 11 Time Out Error
57100 SCTOERR 13 Channel 13 Time Out Error 57200 SCTOERR 15 Channel
15 Time Out Error Channel Time Out (Group 49) 61001 SCTOERR 2
Channel 2 Time Out Error 61002 SCTOERR 4 Channel 4 Time Out Error
61004 SCTOERR 6 Channel 6 Time Out Error 61010 SCTOERR 8 Channel 8
Time Out Error 61020 SCTOERR 10 Channel 10 Time Out Error 61040
SCTOERR 12 Channel 12 Time Out Error 61100 SCTOERR 14 Channel 14
Time Out Error 61200 SCTOERR 16 Channel 16 Time Out Error Channel
Selected (Group 50) 62001 SCSELCT 1 1 Selected 62002 SCSELCT 3 3
Selected 62004 SCSELCT 5 5 Selected 62010 SCSELCT 7 7 Selected
62020 SCSELCT 9 9 Selected 62040 SCSELCT 11 11 Selected 62100
SCSELCT 13 13 Selected 62200 SCSELCT 15 15 Selected Channel
Selected (Group 51) 63001 SCSELCT 2 2 Selected 63002 SCSELCT 4 4
Selected 63004 SCSELCT 6 6 Selected 63010 SCSELCT 8 8 Selected
63020 SCSELCT 10 10 Selected 63040 SCSELCT 12 12 Selected 63100
SCSELCT 14 14 Selected 63200 SCSELCT 16 16 Selected Interrupt 1
Thru 8 (Group 52) 64001 ACTIVE 1 Interrupt 1 Active 64002 ACTIVE 2
Interrupt 2 Active 64004 ACTIVE 3 Interrupt 3 Active 64010 ACTIVE 4
Interrupt 4 Active 64020 ACTIVE 5 Interrupt 5 Active 64040 ACTIVE 6
Interrupt 6 Active 64100 ACTIVE 7 Interrupt 7 Active 64200 ACTIVE 8
Interrupt 8 Active Computer Memory Control (Group 53) 65001 PAICEST
1 Port Address In Compare Error Stored. The addresses supplied to
the memories are different in the two CMC's 65002 PDICEST 1 Port
Data In Compare Error Stored The data words supplied to the
memories are different in the two CMC's. -65004 PAIPEST 1 Port
Address In Parity Error Stored The address supplied by the Port has
even parity. 65010 PDIPEST 1 Port Data In Parity Error Stored The
data word supplied by the port has even parity. 65020 PINVCIEST 1
Port Invalid Control In Error Stored The port has made an invalid
requst for service. 65040 RTRYEST 1 Retry Error ST The CMC's have
made 3 port select retries and the port selections still do not
match. 65100 PTOEST 1 Port Time Out Error Stored The port has not
removed its read or write request after it was answered 65200 CMS
PROT SYSTEM ACT 1 The memory protection system has not been
disabled by the switch on the control panel. Computer Memory
Control (Group 54) 66001 SYNCTOST 1 Sync Time Out Stored The two
CMC's have fallen more than 800 nanoseconds out of synchronization.
66002 MARCEST 1 Memory Address Return Compare Error Stored The
addresses returned from the memories associated with the two CMC's
do not compare 66004 MDRRCEST 1 Memory Data Return Read Compare
Error Stored The words read from the two memories do not compare.
66010 MDRWCEST 1 Memory Data Return Write Compare Error Stored The
data words returned from the memories on the write portion of the
cycle do not compare. 66020 MARPEST 1 Memory Address Return Parity
Error Stored The address returned by the memory has even parity.
66040 MDRWPEST 1 Memory Data Return Write Parity Error Stored The
data returned from memory on the write portion
of the cycle has even parity. 66100 MINVCREST L Memory Invalid
Control Return Error Stored The control signals returned from
memory are invalid. 66200 BSRCEST 1 Bank Select Register Compare
Error Stored The bank selections of the two CMC's do not agree.
Computer Memory Control (Group 55) 67001 BSMR[1] 1 Bank Select Malf
Reg. These leads indicate the bank which was selected when the
first error occurred. 67002 BSMR[2] 1 67004 ABORT WRITE 1 67010
PCIMR[RR] 1 Port Control in Malf Reg These leads contain the state
of the Port Control In leads when the first error occurred. 67020
PCIMR[RW] 1 67040 PCIMR[RMPB] 1 67100 PCIMR[PT] 1 67200 PCIMR[INIT]
1 Computer Memory Control (Group 57) 71001 AOREST 1 Address Out of
Range Error Stored The address exceeds the range of memory used.
71002 ROMEST 1 Read Only Memory Error Stored The port has tried to
write into read only memory. 71004 CROSS WRITE ACTIVE 1 71010 DTEST
1 Drum Table Error Stored A DCU has tried to read or write outside
of its initialization table while in the initialization sequence or
write outside of its initialization table and outside of the block
transfer area while it was not privileged. 71020 PSMR[0] 1 Port
Select Malf Reg These leads carry the binary -- encoded number of
the port selected when the first error occurred. 71040 PSMR[1] 1
71100 PSMR[2] 1 71200 PSMR[3] 1 Computer Memory Control (Group 58)
72001 PMALFR[1] 1 72002 PMALFR[2] 1 Port Malfunction Register 72004
PMALFR[3] 1 An error has occurred while this port was selected.
72010 PMALFR[4] 1 72020 PMALFR[5] 1 72040 PMALFR[6] 1 72100
PMALFR[7] 1 72200 PMALFR[8] 1 Computer Memory Control (Group 59)
73001 PC ROMEST 1 Program Controlled Read Only Memory Error Stored.
73002 CMC ERR ST1 The CMC has detected one of the errors listed
here. 73004 MDRRPEST 1 Memory Data Return Read Parity Error Stored
The data word read from memory has even parity. 73010 PC ROM ACT 1
Program Controlled Read Only Memory Active. 73020 PC ROMEST 2 Same
as 73001 73040 CMC ERR ST 2 Same as 73002 73100 MDRRPEST 2 Same as
73004 73200 PC ROM ACT 2 Same as 73010 CCX, MCC & CCP MISC.
(Group 60) 74001 CCX A P FAIL CCX "A" Power Failure 74002 MCC P A
FAIL MRLF "A" Power Failure 74004 CCX ACTIVE 1 74010 CCX ACTIVE 2
74020 CCX ON LINE 1 74040 CCX ON LINE 2 74100 CCX SEL ERR 1 74200
CCX SEL ERR 2 Computer Memory Control (Group 61) 75001 PAICEST 2
75002 PDICEST 2 Similar to Group 53 75004 PAIPEST 2 75010 PDIPEST 2
75020 PINVCIEST 2 75040 RTRYEST 2 75100 PTOEST 2 75200 CMC PROT
SYST ACT 2 Computer Memory Control (Group 62) 76001 SYNCTOST 76002
MARCEST 2 Similar to Group 54 76004 MDRRCEST 2 76010 MDRCEST 2
76020 MARPEST 2 76040 MDRWPEST 2 76100 MINVCREST 2 76200 BSRCEST 2
Computer Memory Control (Group 63) 77001 BSMR[0] 2 77002 BSMR[1] 2
Similar to Group 55 77004 ABORT WRITE 2 77010 PCIMR[RR] 77020
PCIMR[WR] 2 77040 PCIMR[RMPB] 2 77100 PCIMR[PT] 2 77200 PCIMR[INIT]
2 Computer Memory Control (Group 65) 01401 AOREST 2 01402 ROMEST 2
Similar to Group 57 01404 CROSS WRITE ACTIVE 2 01410 DTEST 2 01420
PSMR[1] 2 01440 PSMR[2] 2 01500 PSMR[3] 2 01600 PSMR[4] 2 Computer
Memory Control (Group 66) 02401 PMALFR [1] 2 02402 PMALFR [2] 2
02404 PMALFR [3] 2 Similar to Group 58 02410 PMALFR [4] 2 02420
PMALFR [5] 2 02440 PMALFR [6] 2 02500 PMALFR [7] 2 02600 PMALFR [8]
2 Int. Level 8 Misc. (Group 67) 03401 SMAIN CLK ALARM MAIN CLOCK
ALARM 03402 SSTDBY CLK ALARM STANDBY CLOCK ALARM 03404 SMAIN RT CLK
ALARM MAIN REAL TIME CLOCK ALARM 03410 SSTDBY RT CLK ALARM STANDBY
REAL TIME CLOCK ALARM 03420 STEST TRUNK TEST TRUNK 03440 SMRS INT
AUTOMATIC ROUTINER INT 03500 SCLP TRBL 1 AN ERROR HAS OCCURRED IN
03600 SCLP TRBL 2 THE CONTROL OF THE CLP CLP Status Group (Group
68) 04401 RT CLK 1 (MAIN) REAL TIME CLOCK THIS SIGNAL WILL 04402 RT
CLK 2 (STANDBY) OCCUR EVERY 16.6 MIL SEC 04404 SYNC ERR 1 common
sync control 04410 SYNC ERR 2 SIGNAL FAULTED 04420 CPD CLP ERR 1
COMMON CPD CONTROL 04440 CPD CLP ERR 2 SIGNAL FAULTED 04500 CLS
CONT ERR 1 CONTROL SIGNAL UNIQUE TO UNIT 1 OR 2 FAULTED 04600 CLS
CONT ERR 2 Third Party Status (Group 69) 05401 TRAP SENSE A TRAP
SIGNAL TO CCPA 05402 CCPA ON LINE CONFIGURATION STATUS 05404 CPGA
GOOD FLOP ISOLATION CKT RESULT 05410 CPT ON LINE CONFIGURATION
STATUS 05420 TRAP SENSE B TRAP SIGNAL TO CCPB 05440 CCPB ON LINE
CONFIGURATION STATUS 05500 CPGB GOOD FLOP ISOLATION CKT RESULT
05600 DCU/DMS 1A DRUM CONFIGURATION Miscellaneous (Group 70) --
(CAUTION: If this group is selected while system is in sync, a TP
TRAP will occur) 06401 TP OFFTOF BOTH CCP(S) OFF LINE AN EXCESSIVE
TIME 06402 DIAG ACCESS READY D ALERT, THAT DIAGNOSTIC ACCESS
CIRCUIT HAS COMPLETED ITS CHORES (THE CLOCK IN A CCP HAS STOPPED)
06404 THIS IS CCPA 06410 THIS IS CCPB 06420 *CPD DECODE ENG (1,1)
06440 *CPD DECODE ENG (2,2) 06500 * 06600 * Miscellaneous (Group
71) 07401 PROT BIT OF Bit 25 of the Location of REF MEM the Address
Referenced. 07402 INT IN Interrupt of Associated CCP in Inhibited
07404 WDT 2-A WATCH DOG TIMER: TIME T2 FROM CCPA 07410 WDT 2-B
WATCH DOG TIMER: TIME T2 FROM CCPA 07420 SCRS1-1 RSIA IS DATA
SOURCE FOR CCPA 07440 SCRS1-2 RSIA IS DATA SOURCE FOR CCPB 07500
SCRS2-1 RS2A IS DATA SOURCE FOR CCPA 07600 SCRS2-2 RS2A IS DATA
SOURCE FOR CCPB SECTION 8.4 Interrupt Level 1 (Sense Group 3 and
69) Sense Line Octal Description 03001 Configuration Panel
Interrupt 03002 Major Power Alarm 03004 Minor Power Alarm 03010
Teletypewriter 1 Input Request Interrupt 03020 Teletypewriter 2
Input Request Interrupt 03040 Repair Verify Request Int. -05402
CCPA ON LINE 05440 CCPB ON LINE 05410 CTP ON LINE The condition of
05402, 05440 and 05410 have to be compared to stored conditions to
determine if a change occurred. A change of configuration
stimulates Interrupt level 1. Interrupt Level 2 (Sense Groups 7;
13; 18; 29; 59) Sense Line Octal Description 15001 15002 15004
15010 Originating Markers 15020 1 thru 8 15040 Malfunction Alarm
15100 15200 73002 CMC 1 Error 73020 CMC 2 Error 07001 07002 07004
Terminating Marker 07010 1 thru 6 07020 Malfunction Alarm 07040
22001 Register-Sender 1A Fault 22002 Register-Sender 1B Fault 22004
Register-Sender 2A Fault 22010 Register-Sender 2B Fault 53002
Ticketing Device Buffers 54002 Channels 3 and 4 reset. 35004 35010
35020 Drum Control Units 35040 1 thru 6 35100 error 35200 35001
Communication Register 35002 1 and 2 Error Interrupt Level 3 (Group
68) 04401 (main) Real Time Clock 04402 (standby) This signal will
occur every 16.6 mil. sec. 51002 Ticketing Device Buffer RDY Int.
52002 channels 3 and 4 Interrupt Level 4 (Sense Group 37) Mnemonic
Description 45001 Communication Registers 1 & 2 45002 Ready
Interrupt Interrupt Level 5 (Sense Group 18) 45004 45010 Drum
Control Units 45020 1 thru 6 45040 Ready Interrupts 45100 45200
Interrupt Level 6 (Sense Groups 43; 44) 53001 54001 Channel Device
54004 Buffers 1, 2 and 6 53020 and 9 thru 16 54020 error 53040
54040 53100 54100 53200 54200 Interrupt Level 7 (Sense Group 14;
41; 42) 16001 Originating Markers 16002 1 thru 8 16004 standby
Interrupt 16010 16020 16040 16100 16200
51001 Channel Device Buffers 52001 1, 2, 5, 6, and 9 thru 16 51004
Ready Interrupt 52004 51020 52020 51040 52040 51100 52100 51200
52200 03440 Automatic Routiner Int. Interrupt Level 8 (Sense Group
19; 67) 23001 Register-Senders 1A, 1B, 2A, 2B 23002 respectively
23004 System Trouble 23010 23020 Register-Senders 1A, 1B, 2A, 2B
23040 respectively 23100 Error Count 23200 03401 MAIN CLOCK ALARM
03402 STANDBY CLOCK ALARM 03404 MAIN REAL TIME CLOCK ALARM 13410
STANDBY REAL TIME CLOCK ALARM 03420 TEST TRUNK 03500 CLP ERR INT 1
03600 CLP ERR INT 2 ______________________________________
Section 8.5
control pulse directive, assignments and functions
assignments have been made to 38 Control Pulse Directive requests.
Functions have been defined on all CPD assignments.
______________________________________ CPD Instruction Code Format
______________________________________ 23 21 20 15 14 9 8 0 TAG
INSTRUCTION SUBSYSTEM DIRECTIVE FIELD CODE CODE
______________________________________ The TAG FIELD defines
address modification (Indexing and indirect INSTRUCTION CODE
defines CPD (17)
Subsystem code defines 1 of 64 possible subsystems. DIRECTIVE is
used to define the function to be performed.
The 38 CPD, their octal representation in the SUBSYSTEM CODE
portion of the format, and the functions of their directives are as
follows.
______________________________________ DIRECTIVES SUBSYSTEM CODE
OCTAL DESCRIPTION ______________________________________ 000 CPD CX
(Channel Multiplex) 001 Put CCXA On-Line 002 Put CCXB ON-line 004
Put CCXA Off-line 010 Put CCXB Off-line 020 Make CCXA Active and
CCXB Standby 040 Make CCXB Active and CCXA Standby 100 Reset CCX
Error 200 Initiate Select Storage Check Routine 400 End Select
Storage Check Routine 001 CPD CLP 000 Lockout All External
(Computer Line Signals Processor) 001 Reset Lockout 002 Set Test
Signals True 003 Set Test Signals False 004 Reset: CPD CLP ERR1;
CPD CLP ERR 2; SYNC ERR1; SYNC ERR 2; CLS CONT ERR 1; CLS CONT ERR
2; PSEUDO CLP CPD 1; PSEUDO CCP CPD 2; GATE Groups and Gate Cards.
005 CLS CLEAR (Clears all External Signal Synchronizers) 006
INHIBIT IS SYNC 1 This CPD will not allow a sync pulse into unit 1
of the CLP. The affect will be a CLS CONT ERR 1 & 2 (SENSE LINE
04500 & 04600) 007 INHIBIT IS SYNC 2 This CPD will not allow a
sync pulse into unit 2 of the CLP. The affect will be a CLS CONT
ERR 2 & 1 (SENSE LINE 04600 & 04500) 010 PSEUDO IS SYNC 1
This CPD will extend the normally 100 nanosecond IS Sync Pulse into
a 500 nanosecond pulse. This will simulate a stuck true condition.
The affect will be a SYNC ERR 2 (SENSE LINE 04410) and an inhibit
of the IS SYNC 1 signal. 011 PSEUDO IS SYNC 2 This CPD will extend
the normally 100 nanosecond IS Sync Pulse into a 500 nanosecond
pulse. This will simulate a stuck true condition. The affect will
be a SYNC ERR 1 (SENSE LINE 04404) and an inhibit of the IS SYNC 2
signal. 012 PSEUDO P5 1 This CPD will expand the normal 100
nanosecond P51 to 500 nanoseconds. This will result in a simulated
stuck true condition for P51. The affect will be to set to SYNC ERR
2. (SENSE LINE 04410). The possibility also exist that one or both
of the CLS CONT ERR flops will be set (sense lines 04500 &
04600). 013 PSEUDO P5 2 This CPD will expand the normal 100
nanosecond P52 to 500 nanoseconds. This will result in a simulated
stuck true condition for P52. The affect will be to set the SYNC
ERR 1 (sense line 04404). The possibility also exist that one or
both of the CLS CONT ERR flops will be set. (Sense line 04500 &
04600). 014 SET PSEUDO CLP CPD 1 This storage element will provide
a signal that will create a CPD CLP ERR 2 on the next non CPD
instruction. It simulates a stuck true condition. The affect will
inhibit the CLP CPD L SIGNAL. 015 SET PSEUDO CLP CPD 2 This storage
element will provide a signal that will create a CPD CLP ERR 1 on
the next non CPD instruction. It simulates a stuck true condition.
The affect will inhibit the CLP CPD 2 signal. 016 GATE GROUPS This
CPD will set a storage element that will gate the decod of the 7
groups assigned to each card and card 9 on to the sense line bus
for use by the CCP during an SSNT or LSGA instruction. The groups
are to be selected during the selection of card 16 and card 9 is
selected with group 1. This storage element is reset with 004. 017
GATE Cards The CPD will set a storage element that will gate the
decode of the first 8 cards onto the sense line bus for use by the
CCP during an SSNT or LSGA instruction. The cards are to be
selected along with group 1. This storage element is reset with
004. 020 Enable Branch trace 021 Disable Branch trace 024 Reset
Branch trace flop 022 Prime break point 023 Disable break point 025
Reset break point flop 026 Prime S-match 027 Disable S-match 030
Reset S-match flop 037 Lockout RT CLK sense lines 002 CPD RS1
Register-Sender 1 005 RPI-A Select CCP-A CLU-A will take read/write
commands from CCP-A and the data to be written into RCM-A will be
that data sent by CCP-A. 006 RPI-B Select CCP-A The same as 005
except for CLU-B and RCM-B 007 RPI-A&B Select CCP-A The same as
005 except for both CLU's and RCM's. 011 RPI-A Select CCP-B CLU-A
will take read/write commands from CCP-B and the data to be written
into RCM-A will be that data sent by CCP-B. 012 RPI-B Select CCP-B
The same as 011 except for CLU-B and RCM-B 013 RPI-A&B Select
CCP-B The same as 011 except for both CLU's and RCM's. 015 RCM
Clear -CLU-A This initializes hardware in RCM-A. 016 RCM Clear
-CLU-B This initializes hardware in RCM-B. 017 RCM Clear
-CLU-A&B This initializes hardware in both RCM-A&B. 021
RPI-A Select No CCP CLU-A will not accept read/write commands from
either CCP. 022 RPI-B Select No CCP CLU-B will not accept
read/write commands from either CCP. 023 RPI-A&B Select No CCP
Both CLU's will not accept read/write commands from either CCP. 025
RTG Trouble Reset CLU-A Resets RTG (RS Timing Generator) trouble
and error detecting logic in CLU-A 026 RTG Trouble Reset CLU-B
Resets RTG trouble and error detecting logic in CLU-B. 027 RTG
Trouble Reset CLU-A&B Resets RTG trouble and error detecting
logic in both CLU's. 031 RTG Reset CLU-A Resets all RTG timing
functions in CLU-A to an initial state. 032 RTG Reset CLU-B Same as
031 except for CLU-B. 033 RTG Reset CLU-A&B Same as 031 except
for both CLU's. 101 RMU-A Control Pulse Enable Enables the
generation of pulses in CLU-A. 102 RMU-B Control Pulse Enable
Enables the generation of pulses in CLU-B. 103 Both RMU's Control
Pulse Enable Enables the generation of pulses in both CLU's. 201
RMU-A Control Latch Enable Enables the setting or resetting of
latches in CLU-A. 202 RMU-B Control Latch Enable Enables the
setting or resetting of latches in CLU-B. 203 Both RMU's Control
Latch Enable Enables the setting or resetting of latches in both
CLU's. 414 Reset Request for Translation Interrupt Resets the
flip-flop associated with the request for translation interrupt
sense line in both CLU's. 424 Reset RS Fault Interrupt Resets the
flip-flop associated with the RS fault interrupt sense line in both
CLU's. 430 Reset System Trouble Interrupt Resets the flip-flop
associated with the RS system trouble interrupt sense line in both
CLU's. 454 Run In Sync Instructs the CLU's to sync commands from
both CCP's before acknowledging either. 464 Run Simplex Instructs
the CLU's not to attempt to sync commands from both CCP's before
acknowledging each one. 470 Reset Error Count Resets the flip-flop
associated with the RS error count interrupt sense line in both
CLU's. 003 CPD RS2 Register-Sender 2 Same as CPD RSI 004 CPD DCU1
000 Reset DCU and DMS Drum Control Unit 1 001 Initialize DCU 002
Spill Directive 003 Initialize Maintenance 005 CPD DCU2 Same as CPD
DCU 1 Drum Control Unit 2 006 CPD DCU3 Same as CPD DCU 1 Drum
Control Unit 3 007 CPD DCU4 Same as CPD DCU 1 Drum Control Unit 4
010 CPD DCU5 Same as CPD DCU 1 Drum Control Unit 5 011 CPD DCU 6
Same as CPD DCU 1 Drum Control Unit 6 012 CPD CMC 000 MCLTR MB -RST
Computer Memory Control Memory Control Logic 001 MCLTR MB -SET Test
Register Memory Busy MCLTR simulates a memory request from a port
and the control signals returned from the memory to test CMC
control logic. 002 MCLTR {DA}RST MCLTR {Data Available} 003 MCLTR
{DA} SET 004 MCLTR {DL} RST {Data loaded} 005 MCLTR {DL} SET {Data
Loaded} RST 006 MCLTR {EOC} MCLTR {End of Cycle} 007 MCLTR
{EOC}-SET 010 MCLTR {MREQ}RST MCLRT {Memory Request} 011 MCLTR
{MREQ}RST 012 MMDBSOCR{1}-RST Maintenance Memory 013
MMDBSOCR{1}-SET Data Bus Source 014 MMDBSOCR{2}RST Control Register
015 MMDBSOCR{2}SET By setting MMDBSOCR{1} 016 MMDBSOCR{3}RST {2}
{3} the test points 017 MMDBSOCR{3}SET previously listed will be
connected to the data bus if the CP is off-line 020 PENTR{1}-RST
Port Enable Test Register 021 PENTR{1} SET {1-6} 022 PENTR{1}-RST
PENTR enables the CMC to answer a memory request from an off-line
port if the CP is off-line. 023 PENTR{1} SET 024 PENTR{3}-RST 025
do. SET 026 PENTR{4} RST 027 do. SET 030 PENTR{5} RST 031 do. SET
032 PENTR{6}-RST 033 do. SET 034 POLR{1}-RST Port On Line Register
{1-6} 035 POLR{1}SET POLR controls the on-line status of the six
DCU's
attached to ports 1 to 6. The POLR's of a DCU must be reset in both
CMC's before an off-line indication is given to that DCU. POLR is
also reset by the MASTER CLEAR button on the computer test panel.
036 POLR{2}-RST 037 do. SET 040 POLR{3}-RST 041 do. SET 042 POLR{4}
RST 043 do. SET 044 POLR{5} RST 045 do. SET 046 POLR{6}-RST 047 do.
SET 050 INPUT TEST REG{1}-RST Input Test Register {1-6} 051 INPUT
TEST REG{1}-SET 052 INPUT TEST Used to test the REG{2}-RST signal
paths from 053 INPUT TEST the DCU's to the CMC's REG{2}-SET When an
input test 054 INPUT TEST register is set all REG{3}-RST the inputs
to the CMC's from that DCU Should be true. 055 INPUT TEST
REG{3}-SET 056 INPUT TEST REG{4}-RST 057 INPUT TEST REG{4}-SET 060
INPUT TEST REG{5}-RST 061 INPUT TEST REG{5}-SET 062 INPUT TEST
REG{6}-RST 063 INPUT TEST REG{6}-SET 064 MCLTR{LCH.sup.. . MDB}-RST
Memory Control 065 MCLTR{LCH.sup.. . MDB}-SET Logic Test Register
Latch Memory Data Bus If the CP is off-line setting MCLTR{LCH MDB}
latches the data bus so that a one applied to the data bus remains
on the data bus after the input is removed. 066 PC ROM ACT-RST
Program Controlled 067 PC ROM ACT-SET Read Only Memory Active
Setting this register enables the program controlled read only
memory protection. 076 CROSS WRITE-RST 077 CROSS WRITE-SET Cross
write enables an on-lineCCP to write into its own memory and the
duplex memory which must be off line. 013 CPD CP SETS OR RESETS CRS
1 AND/OR CRS 2 TO DETERMINE WHICH REGISTER-SENDER WILL BECOME A
DATA SOURCE CRS1 = REGISTER-SENDER 1A CRS1' = REGISTER-SENDER 1B
CRS2 = REGISTER-SENDER 2A CRS2' - REGISTER-SENDER 2B 001 Set CRS1
in CPA 002 Reset CRS1 in CPA 004 Set CRS1 in CPB 010 Reset CRS1 in
CPB 020 Set CRS2 in CPA 040 Reset CRS2 in CPA 100 Set CRS2 in CPB
200 Reset CRS2 in CPB 014 CPD OM1 001 Reset Enable (Originating
Marker 1 002 Reset Interrupts 004 Send SR Data 010 Standby 020
Report Blockage 040 Do not Report Blockage 100 Do not Perform Line
Test 200 Perform Line Test 400 Reset Send SR data 015 CPD OM 2 Same
as CPD OM1 (Originating Marker 2) 016 CPD OM 3 Same as CPD OM1
(Originating Marker 3) 017 CPD OM 4 Same as CPD OM1 (Originating
Marker 4) 020 CPD OM 5 Same as CPD OM1 (Originating Marker 5) 021
CPD OM 6 Same as CPD OM1 (Originating Marker 6) 022 CPD OM 7 Same
as CPD OM1 (Originating Marker 7) 023 CPD OM 8 Same as CPD OM1
(Originating Marker 8) 024 CPD TM 1 001 Reset Enable (Terminating
Marker 1) 002 Reset Interrupt 004 Send SR Data 100 Do not Perform
Line Test 200 Perform Line Test 400 Reset, Send SR Data 025 CPD TM
2 Same as CPD TM 1 (Terminating Marker 2) 026 CPD TM 3 Same as CPD
TM 1 (Terminating Marker 3) 027 CPD TM 4 Same as CPD TM 1
(Terminating Marker 4) 030 CPD TM 5 Same as CPD TM 1 (Terminating
Marker 5) 031 CPD TM 6 Same as CPD TM 1 (Terminating Marker 6) 032
CPD CTP (Third Party 000 SET TEST FLOP 1 (CPDTSTF1) This signal is
used by the control circuit in conjunction with CPDTSTF2; CPDTSTF3
and CPDTSTF4 plus CPDTST 1 thru 9, to form up the MTST signals used
in routining the detection circuit. (see Sec. 5.6.1.4) 001 RESET
CPDTSTF1 002 SET TEST FLOP 2 (CPDTSTF2) Refer to Directive 000 for
comments. 003 RESET TEST FLOP 2 (CPDTSTF2) Refer to Directive 000
for comments. 004 SET TEST FLOP 3 (CPDTSTF3) Refer to Directive 000
for comments. 005 RESET TEST FLOP 3 (CPDTSTF3) Refer to Directive
000 for comments. 006 SET TEST FLOP 4 (CPDTSTF4) Refer to Directive
000 for comments. 007 RESET TEST FLOP 4 (CPDTSTF4) Refer to
directive 000 for comments. 010 SET TEST FLOP 5 This signal is used
to simulate both CCP (s) on line for use in Detection Circuit
Maintenance 011 RESET TEST FLOP 5 Refer to Directive 010 for
comments. 012 SET TEST FLOP 6 This signal is used to simulate the
signal P3 and P4 stuck at 1 in CCPB for use in detection circuit
maintenance. 013 RESET TEST FLOP 6 Refer to Directive 012 for
comments. 014 SET TEST FLOP 7 This signal is used to simulate the
signal P3 and P4 stuck at 1 in CCPA for use in detection circuit
maintenance. 031 RESET TEST FLOP 13 Refer to Directive 030 for
comments. 032 SET TEST FLOP 14 This signal simulates all zeros on
both sets of inputs to the matchers of the detection circuit. 033
RESET TEST FLOP 14 Refer to directive 032 for comments. 034 SET
TEST FLOP 15 Not assigned 035 RESET TEST FLOP 15 Refer to directive
034 for comments. 036 SET TEST FLOP 16 Not assigned 037 RESET TEST
FLOP 16 Refer to directive 036 for comments. 040 CPDTST 1 This
signal is a 500 nano second pulse. When CPDTSTF 1 (only) is set the
CPD CTP signal from CCPA will be inhibited. MTST3A. When CPDTSTF 2
(only) is set the CPD CTP signal from CCPB will be inhibited
(MTST3B). This is a partial inhibit, but is in effect at the time
that the detection circuit is monitoring for a match. This results
in an expected mismatch and is used in routining that particular
matcher. 042 CPDTST 2 This signal is a 500 nano second pulse. When
CPDTSTF1 (only) is set, the CCPA on line Signal will be inhibited
(MTST4A). When CPDTSTF 2 (only) is set, the CCPB on line signal
will be inhibited (MTST4B). This is a partial inhibit, but is in
effect at the time the detection circuit is monitoring for a match.
This results in an expected mismatch and is used in routining that
particular detection matcher. 015 RESET TEST FLOP 7 Refer to
directive 014 for comments. 016 SET TEST FLOP 8 This signal allows
the loading, of the result, of the matcher gates, in the Isolation
Circuit, into the Routine Match Flops for use in maintenance of the
Isolation Circuit. 017 RESET TEST FLOP 8 Refer to directive 016 for
comments. 020 SET TEST FLOP 9 This signal inhibits all data bus
signals from CCPA to the isolation and detection circuit, for
maintenance. 021 RESET TEST FLOP 9 Refer to directive 020 for
comments. 022 SET TEST FLOP 10 This signal inhibits all data bus
signals from CCPB to the isolation and detection circuit, for
maintenance. 023 RESET TEST FLOP 10 Refer to directive 022 for
comments. 024 SET TEST FLOP 11 This signal inhibits the place BOTH
CCP(S) ON LINE signal in the synchronizer circuit of the control
circuit during Maintenance routining. 025 RESET TEST FLOP 11 Refer
to directive 024 for comments. 026 SET TEST FLOP 12 This signal
simulates both CCP(S) on line for the stuck at X (Sax) circuit
only. 027 RESET TEST FLOP 12 Refer to Directive 026 for comments.
030 SET TEST FLOP 13 This signal simulates all ones on both sets of
inputs to the matchers of the detection circuit. 044 CPDTST 3 This
signal is a 500 nano second pulse. When CPDTSTF1 (only) is set, the
CCPA MPSTAT signal will be inhibited (TST5A). When CPDTSTF 2 (only)
is set the CCPB MPSTAT signal will be inhibited (MTST5B). This is a
partial inhibit, but is in effect at the time the detection circuit
is monitoring for a match. This results in an expected mismatch and
is used in routining that particular detection matcher. 046 CPDTST
4 This signal is not assigned. 050 CPDTST 5 This signal is a 500
nano second pulse. When CPDTSTF 1 (only) is set the CCPA MMREAD
signal is inhibited (MTST7A). When CPDTSTF 2 (only) is set the CCPB
MMREAD signal is inhibited (MTST7B). This is a partial inhibit, but
is in effect at the time the detection circuit is monitoring for a
match. This results in an expected mismatch, and is used in
routining that particular detection matcher. 052 CPDTST 6 This
signal is a 500 nano second pulse When CPDTSTF 1 (only) is set, the
CCPA MM Write will be simulated to the detection matcher (MTST8A).
When CPDTSTF 2 (only) is set the CCPB MM WRITE will be simulated to
the detection matcher (MTST8B). This is a partial simulation, but
is in effect at the time the detection circuit is monitoring for a
match. This results in an expected mismatch, and is used in
routining that particular detection matcher. 054 CPDTST 7
This signal is not assigned. 056 CPDTST 8 This is a 500 nano second
pulse. When CPDTSTF 1 (only) is set, the CCXA ENABLE signal to the
detection circuit will be inhibited (MTST10A). When CPDTSTF2 (only)
is set, the CCXB ENABLE signal to the detection circuit will be
inhibited (MTST10B). This is a partial inhibit, but is in effect at
the time the detection circuit is monitoring for a match. This
results in an expected mismatch, and is used in routining that
particular detection matcher. 060 CPDTST 9 This is a 500 nano
second pulse. When CPDTSTF 1 (only) is set, the CCPA signal C1 L2
P2 is simulated (MTST11A). When CPDTSTF2 (only) is set the CCPB
signal C1 L2 P2 is simulated (MTST11B). This simulation appears
during level 3 and creates an expected mismatch, and is used in
routining that particular matcher. 062 CPDTST 10 This signal is
used to inhibit P3 + P4 from CCPB, creating the effect stuck at
zero. It is used in maintenance of the detection circuit. 064
CPDTST 11 This signal is used to inhibit P3 + P4 from CCPA creating
the effect stuck at zero. It is used in maintenance of the
detection circuit. 066 CPDTST 12 This signal is used to increment
counter C1 in the isolation circuit for maintenance. 070 CPDTST 13
This signal is used to preset counter C1 (ROM address register) of
the isolation circuit, to an address that contains all ones for
maintenance. 072 CPDTST 14 This signal is used to preset counter C1
(ROM address register) of the isolation circuit, to an address that
contains all zero's, for maintenance. 074 CPDTST 15 This signal is
used to reset storage element T1 in the isolation circuit. 076
CPDTST 16 This signal is used by the clear and start circuit to
reset the "CLEAR" and the "CP OFF" flops that are set during the
routining of the clear and start circuits associated with CCPB.
0100 CPDTST 17 This signal is used by the clear and start circuit
to reset the "CLEAR" and the "CP OFF" flops that are set during the
routining of the clear and start circuitry associated with CCPA.
0102 CCPDTST 18 This signal is used to set the routine flop in the
clear and start circuit associated with CCPB. 0104 CPDTST 19 This
signal is used to set the routine flop in the clear and start
circuit associated with CCPA. 0106 CPDTST 20 This signal is used to
reset the routine flop described in 0102. 0110 CPDTST 21 This
signal is used to reset the routine flop described in 0104. 0112
CPDTST 22 This signal is used to create a clear and start signal in
the circuitry associated with CCPB, when the routine flop in that
circuitry is set. Because of intended design, the clear and start
circuitry associated with CCPA will also be activated. If the
intent of this clear and start is to, only, routine the circuitry
and to ignore its effect on the overall configuration, then the
routine flop for the clear and start circuits associated with CCPA
must also be set. (CPD032, 0102). 0114 CPDTST 23 This signal is
used to create a clear and start in the circuitry associated with
CCPA, the routine flop in that circuitry is set. Due to intended
design, the clear and start associated with CCPB will also be
activated. If the intent of this clear and start is to, only,
routine the circuitry, and to ignore the normal effect on the
overall system, then the routine flop of the clear and start
circuits associated with CCPB must also be set. (CPD032, 0104) 0116
CPDTST 24 This signal is used to create a clear and start under
program control in the circuitry associated with CCPB. This signal
is inhibited if a third party trap does not exist or if CCPF is off
Line. Once initiated the clear and start circuitry associated with
CCPA will also be initiated without restriction. 0120 CPDTST 25
This signal is used to create a clear and start under program
control in the circuitry associated with CCPA. This signal is
inhibited if a third party trap does not exist, or if CCPA is off
line. Once initiated the clear and start circuitry associated with
CCPB will also be initiated with out restriction. 0122 CPDTST 26
(SYNC CPD) This signal is used to initiate synchronous operation of
the duplicated CCP(S) and the computer third party. The signal sets
the synchronizer flop in the central circuit, when both clocks of
the duplicated CCP(S) have stopped, a PLACE BOTH CCP(S) ON LINE
SIGNAL is sent to the configuration circuit. Placing of both CCP(S)
on line resets the sync flop. 0124 CPDTST 27 (CPD OFF F) This
signal resets the (TP OFF TO F) storage element in the isolation
circuit that stores the fact that both CCP(S) were off line an
excessive length of time. 0126 CPDTST 28 This signal is not
assigned. - 0130 CPDTST 29 This signal is not assigned. 0132 CPDTST
30 This signal is not assigned. 0134 CPDTST 31 This signal is not
assigned. 0136 CPDTST 33 This signal is not assigned. 0140 CPDTST
33 This signal is not assigned. 0142 CPDTST 34 This signal is not
assigned. 0144 CPDTST 35 This signal is not assigned. 0146 CPDTST
36 This signal is not assigned. 0150 CPDTST 37 This signal is not
assigned. 0152 CPDTST 38 This signal is not assigned. 0154 CPDTST
39 This signal is not assigned. 0156 CPDTST 40 This signal is not
assigned. 0160 CPDTST 41 This signal is not assigned. 0162 CPDTST
42 This signal is not assigned. 0164 CPDTST 43 This signal is not
assigned. 0166 CPDTST 44 This signal is not assigned. 0170 CPDTST
45 This signal is not assigned. 0172 CPDTST 46 This signal is not
assigned. 0174 CPDTST 47 This signal is not assigned. 0176 CPDTST
48 This signal is not assigned. 033 CPD CTP CLR RESETS ALL CTP
CIRCUITS (Third Party) (only if by ON LINE CCP) -034 CPD TRAP 001
SET TP TRAP DISABLE (Third Party) Disables trap signal from
entering CCP(s) 002 RESET TP TRAP DISABLE 004 RESET TRAP SIGNALS TO
CCP(s) 035 CPD CP OFF TAKES CCPA OFF LINE 036 CPD CP OFF TAKES CCPB
OFF LINE 037 CPD CTP ON-OFF 000 PLACE CTP ON-LINE 001 TAKE CTP
OFF-LINE ______________________________________
CALL HISTORY TABLE
The system has the capability of processing as many as 384 calls at
one time. Any call that originates into the system must have a
signaling path from the originating inlet to the common control
(the register sender (RS) and the central processor unit (CPU)).
The register junctor is the component which provides this signaling
path between the network and the common control equipment. Since
the maximum number of register junctors in the system is 384, the
maximum number of calls that the software can process is 384.
The software is structured in such a manner that it identifies the
calls which it is processing by the register junctor identities
which are being used to supply the signaling path for the call.
Since the software must be able to process several calls at one
time, it cannot work on one call continuously from the time of
origination to the time it is connected through the network. Thus,
the software performs several small tasks on a call when it is not
doing other work in the system (i.e., ticketing, processing other
calls, maintenance).
This implies that the software must have an area to save
information about the call when it is performing other work. Since
the software must be capable of processing 384 calls at one time,
there exist 384 areas in core to save intermediate data for each
call. The area in core which is used to save intermediate data for
calls that are being processed is the call history table.
The call history table contains 384 entries. Each entry consists of
a twelve word buffer to store intermediate data about the call
which is associated with a particular register junctor. Each entry
in the call history table is associated with one of the 384
register junctors in the system. Thus, an entry in the call history
table is accessed by using the register junctor identity associated
with the call being processed. A register junctor identity is
defined as follows:
Register Junctor Identity = Register Sender Section in which the
register junctor is part of (0,1) + Register Junctor Identity
relative to the Register Sender Section that is part of (0-191)
Examples of information that is saved in the call history table
are:
1. Originating class of service data
2. Digit translation data
3. Data which is internally generated by the software that is to be
used for later processing of the call.
4. Data which will be sent to the ticketing software so that the
call can be billed properly.
Another important item of information which is stored in the call
history table is a pointer to the work area which is being used to
perform a task for the call. Thus, it is easy to retrieve the work
area associated with a call by knowing the register junctor
identity associated with the call. It is worth mentioning that a
work area is not always linked to the call history table. A work
area is linked to the call history table when the software is
performing a task to process the call (i.e., there is no work area
linked to the call history table during the reception of
digits).
A diagram of the call history table is shown in FIG. 39. It
comprises 4608 words (384 entries .times. 12 entries/word). FIGS.
40-46 are diagrams of one entry of 12 words, which show what
information is in a call history table entry during various stages
of processing a call, identified as time frames .phi.-6. Note that
there are groups of data (overlays) identified as CHA, CHC, CHE,
CHG, CHH, CHL, CHM, CHQ, CHT, and CJA. Individual items in each
group are identified by the three letters of the group followed by
three additional letters. In some cases sets of items within the
same word also have a common identity comprising the same group
identity followed by three other letters, not shown in FIGS. 40-46.
The entire word is also identified by the three group letters
followed by W and a pair of digits .phi..phi.-11 for the word; for
example the first word of group CHA is identified as
CHAW.phi..phi., and is located in word three of the entry. Note
that the items of a group may appear in an entry during one or more
of the time frames of FIGS. 40-46, and that the same location in an
entry is used for different items during the progress of a call
through the time frames. The information for the various items of
the groups is defined below. The tables at right are references for
definitions and values.
Group CHA comprises six words .phi.-5 located in the entry in rods
3-8. This group is used to schedule program module C.phi.1
(class-of-service initialization) and by the F32 (CCR handler)
module. Table CHA is also used by program module C.phi.1 in the
process of obtaining a work area. The fifth and sixth words contain
status information which is used for scheduling purposes.
______________________________________ Word CHAW.phi..phi. in entry
word 3 Item Bits Description Table LKC .phi.-14 Linkage control
FWALKC TYP 15-20 Work area type indicator FWATYP BK.phi. 21-23
Constant value .phi. Word CHAW.phi.1 in entry word 4 NPG .phi.14
Next program identity FWANPG ELN 15-17 Entry line number FWAELN PRI
18-20 Priority PWAPRI BK1 21-23 Constant value .phi. Word
CHAW.phi.2 in entry word 5 TPF .phi.14 Identity of program in
control of work area FWATPF ADI 23 Audit indicator used by the work
area audit routine (WARAUD) which determines is the call history
table can be found in a queue or not. BK2 15-22 Constant value
.phi. Word CHAW.phi.3 in entry word 5 FEP .phi.-14 Forced exit
program identity FWAFEP ERP .phi.-14 Error program identity FWAERP
FEL 15-17 Entry line number in forced exit program FWAFEL FPR 18-20
Priority of forced exit program FWAFPR HPB 23 Hitching post
indicator indicates whether or not the call history table slot is
being used as a hitching post for a work area. BK3 22-23 Constant
value .phi. Word CHAW.phi.4 in entry word 6 RJI .phi.-14
Register-junctor identity FWARJI RJN 4-11 Register-junctor number
FWARJN SEC 12 Register-sender section EIO 15-20 Error indicators
from the I/O programs of the FWAEIOive BK4 21-23 Constant value
.phi. Word CHAW.phi.5 in entry word 7 WAA .phi.-14 Work area
address indicates the address of the work area that is being used
for the call. CCM 15-20 call condition modified indicates the call
abandoned, a time out, or an interrupt has occurred. Field CCM
contains the fields TIO, CAB and XTO. TRI 15-18 Translation
interrupt FWBTRI CAB 19 Call abandon FWBCAB XTO 20 Time-out FWBXTO
BK5 21-23 Constant value .phi.
______________________________________
Group CHC is used to store the originating marker data frames,
which are the equipment information for originating calls. This
information from the originating marker is used by call processing
in the identification and processing of the call. CHC is accessed
by the call history address assigned by the executive. It consists
of two 24 bit words with a bias of 10 so that they appear in words
10 and 11.
______________________________________ Word CHCW.phi..phi. in entry
word 10 SEC .phi.-1 Office section CTNSEC SBS 2-3 Subsection
indicates orig. marker pair CTNSBS SSB .phi.-3 Section and
subsection SEC + SBS MID 4 Marker identity FWCMID MTN 5 Test call
FWCTCL INO 7-11 Instructions originating FWDINO-A,B BUN 16-19 B
unit FWDBUN-A CSO 20-23 Call status originating FWDSCO-A Word
CHCW.phi.1 in entry word 11 BUN .phi.-2 B unit outlet FWDBUO-A RUO
.phi.-5 R unit outlet FWDRUO-A AUI 6-10 A unit inlet FWDAUI-A AUN
11-14 A unit FWDAUN-A ABG 15-17 AB group FWDABG-A MTX 18-21 Matrix
FWDMTX ABX 15-21 Consists of ABG and MTX LMI 6-21 Line matrix
inlet, defines the matrix and unique inlet of the matrix for a line
or trunk. Consists of MTX, ABG, AUN and AUI. RBO .phi.-5 R unit, B
unit combination. Consists of RUO and BUO.
______________________________________
CHE contains data used by the non-local pre-translator to access
drum table CPD via a 1, 2 or 3 digit translation. CPD in turn
contains data used to instruct the register sender to collect more
digit or to standardized a non-standard digit pattern. The table
consists of three words, with a bias of 0 so that they fall in
words .phi.-2 shown in FIG. 42.
______________________________________ Word CHEW.phi..phi. in entry
word .phi. XD6 .phi.-3 Sixth called number digit -- obtained from
FWBXD6 XD5 4-7 Fifth called number digit -- obtained from FWBXD5
XD4 8-11 Fourth called number digit -- obtained from FWBXD4 XD3
12-15 Third called number digit -- obtained from FWBXD3 XD2 16-19
Second called number digit -- obtained from FWBXD2 XD1 20-23 First
called number digit -- obtained from FWBXD1 X13 12-23 Consists of
XD1, XD2 and XD3 -- Part of the search key used to access table
CPD. See CHESID. X23 12-19 Consists of XD2 and XD3 CD1 .phi.-23
Consists of XD1-XD6. Word CHEW.phi.1 in entry word 1 FTP .phi.-1
Fast time out digit position TIP 2-3 Translation interrupt digit
position Specifies the digit position CHEXD1, XD2 or XD3 in the
search key the FWBIDC value is to be placed when a TRI = 1
interrupt has occurred and CHESID = 1. UID .phi.-3 Use incoming
digit counter. Specifies the digit position CHEXD1, XD2 or XD3 in
the search key the FWBIDC value is table placed if CHESIO-1. SID 20
Search on incoming digit counter. Indicates whether or not to place
the FWBIDC value in the digit portion of the search key. Part of
the search key used for the table CPD. Word CHEW.phi.2 in entry
word 2 AUI .phi.-4 A unit inlet AUN 5-8 A unit ABG 9-11 AB group
MTX 12-15 Matrix SEC 16-17 Section LNI .phi.-17 Consists of AUI,
AUN, ABG, MTX, SEC. ______________________________________
Group CHG is used to store code translation data from work area CXD
which defines the routing information necessary to terminate a
call. The table consists of four words with a bias of .phi. so that
they fall in words .phi.-3 as shown in FIG. 43
______________________________________ Word CHGW.phi..phi. in entry
word .phi. RTN .phi.-11 Route number CTTRTN TTN 12-15 Traffic type
number CTTTTT TSR 16 Tandem selective routing CTTTSR LSR 17 Local
selective routing CTTLSR RPV 18-19 Route plan value CTTRPV CDR 20
Coin deposit required CTTCDR DNT 21 Directory number translation
CTTDNT Word CHGW.phi.1 in entry word 1 NJR .phi.-3 Next job to run
CTTNJR CID 4-8 Code identification CTTCID AOS 9 Allowed on six
CTTAOS EOP 10 Early outpulsing CTTEOP ECP 11 Elacs code protection
CTTECP STR 12-14 Separate toll routing CTTSTR ZNC 17-19 Zone of
charge CTTZNC ZTS 20-22 Tandem screening zone CTTZTS Word
CHGW.phi.2 in entry word 2 OSV .phi.-3 Outpulsing start value
CTTOSV FTO 4-7 Fast time out CTTFTO XTL 8-11 Totals CTTXTL Word
CHGW.phi.3 in entry word 3 PJR .phi.-3 Previous job run by digit
analysis OJR 4-7 Old job run. Used for ambiguous code processing.
TAT 8 Translation action taken.
______________________________________
Group CHH is used to store routing information which may be used to
retrace a call. CHH consists of one entry type format (format A)
and a general format (format B). Table CHH consists of six words
falling in words .phi., 2, 4, 5, 6 and 7, shown in FIGS. 44, 45 and
46.
______________________________________ Word CHHW.phi..phi. in entry
word .phi. RTN .phi.-11 Route number being processed if a route -
number or alternate route number translation was the last
translation performed. (CHHDNX = .phi.) Word CHHW.phi.1 in entry
word 2 SU1 .phi.-3 Selector units of the first loop through the
selector matrix FWCSUT-A SN1 4-7 Selector tens of the first loop
FWCSTN-A ST1 .phi.-7 Comprises SUI and SNI. Word CHHW.phi.2 in
entry word 4 SU3 16-19 Selector units of the third loop FWCSUT-A
SN3 20-23 Selector tens of the third loop FWCSTN-A ST3 16-23
Comprises SU3 and SN3. Word CHHW.phi.3 in entry word 5 SU2 .phi.-3
Selector units of the second loop FWCSUT-A SN2 4-7 Selector tens of
the second loop FWCSTN-A ST2 .phi.-7 Comprises SU2 and SN2. Word
CHHW.phi.4 in entry word 6 SAI .phi.-2 Selector matrix A inlet
FWCSAI-A SAU 3-6 Selector matrix A unit FWCSAU-A SAB 7-9 Selector
matrix AB group FWCSAB-A SMX 10-13 Selector matrix SGI .phi.-13
Comprises SAI, SAU, SAB, SMX. Word CHHW.phi.5 in entry word 7 ARN
.phi.-11 Alternate route number if route number being processed
cannot be terminated and CHHARI = 1. CRNARN LXT 13 Line matrix
termination if = .phi.. or selector matrix if = 1. ART 14 Alternate
route translation was last translation performed. REP 15 Previous
route early outpulsing ARI 16 Alternate route exists, in CHHARN RTL
17 Retrial DAT 18 Delayed alternate route translation
______________________________________
Group CHL is for ticketing information, including the normalized
called number, the calling director number, and the ticketing scan
point. See FIG. 45.
______________________________________ Word CHLW.phi..phi. in entry
word .phi. TCT 14-18 Terminating call type FNA 19 Foreign numbering
area CL2 20-23 Calling directory number 7th digit NO7 20-23 Calling
directory number 7th digit Word CHLW.phi.1 in entry word 1 CL1 0-23
Calling directory number first six digits NO6-NO1. Also CL4 for
6th-3rd digits, and for 2nd and 1st digits. Word CHLW.phi.2 in
entry word 2 CD2 8-23 Called number 7th-10th digits comprising
XD10-XD7. Word CHLW.phi.3 in entry word 3 CD1 0-23 Called digits
XD6-XD1 Word CHLW.phi.4 in entry word 6 TSG 15-22 Ticketing
scanpoint comprising TSY and TSX. Word CHLW.phi.5 in entry word 7
TSB 19-23 Ticketing scanpoint -- 3rd field.
______________________________________
Group CHM is used by maintenance to store data which is to be used
by call processing modules C32. This data indicates to C32 whether
or not to take a sender/receiver and/or register junctor off line.
The table consists of one word with a bias of 4 so that it falls in
word four.
______________________________________ Word CHMW.phi..phi. in entry
word 4 SRS 22 Maintenance -- take sender/receiver off line RJS 23
Maintenance -- take register junctor off
______________________________________ line
Table CHQ is used to store the program generated indicators which
are generated by call processing programs during the processing of
a call for use later on in the processing of the call. The table
consists of four words with a bias of 8 so that they fall in words
8-11.
______________________________________ Word CHQW.phi..phi. in entry
word 8 TMF 21-23 Time frame field. The value of which provides the
means to identify the relative progression of the call through the
call processing program and thus indicates how the data and the
call table shall be interpreted. The value TMF = .phi. for time
frame .phi. of FIG. 40, during which program modules F32 and
C.phi.1 are run. The value TMD = 1, FIG. 41, has programs F51,
C.phi.2, C.phi.3, C.phi.6, C.phi.7 and C.phi.9. The value TMF = 2,
FIG. 42, is the time during which program modules F51, C.phi.4, and
C.phi.5 are run. The programs that are run during time frame TMF =
3, FIG. 43, are C.phi.7, C.phi.8, C10, C12, C13 and C15A. The
programs that are run during time frame TMF = 4, FIG. 44, are C14,
C15B, C16, C17, C19, C20, C21 and C24. The programs that are run
during time frame TMF = 4, FIG. 45, are C24, C26, and retrial
programs. Program C26 sets TMF = 6 before instructing the register
sender to clear its memory. Time frame 6 is the register junctor
idle time frame and is succeeded by time frame .phi. when the
register junctor beings to process a new call. Word CHQW.phi.1 in
entry word 9 TIE .phi.-3 Translation instruction expected, contains
the value of the translation instruction which is expected from the
register sender during a TRI interrupt. The definitions of the
various values of TRI are given in the REGISTER/SENDER patent
application TOV 4-7 Index into table FTT for program to run in case
of fast interdigital time out. LWA 8-11 Leave word area. An index
for accessing entries in table FTE for program to be run for an
expected register-sender interrupt. IPS 12 Inhibit program
scheduling WAL 13 Work area linked. Indicates that a work area is
associated with the register junctor and is to be used when
scheduling a program as a result of an RS interrupt. TST 14
Maintenance is using the RJ. ROL 15 Off line RJ. RJB 16 Busy RJ ADR
17 Indicates no more digits expected. RSA 18 Sender/receiver
assigned to call. TRS 19 Unused CRJ 20 Maintenance is attempting to
clear the RJ. DNP 21 Used by C32 to clear if no job is scheduled.
ABC 22 Abort the call. EOP 23 Early outpulsing. Word CHQW.phi.2 in
entry word 10 DNR 5 Directory number retrieved. SBM 6 Switch bit
for maintenance used in C19. TPI 8-9 Type of print out RCC 10
Revertive call VPD 11-12 Value of prefix digit dialed RTO 13-14
Recorded time out LPI 15 Loop pulled in selector PGI 5-15 Comprises
DNR, SBM, TPI, RCC, VPD, RTO and LPI TNo. 20 Traffic service
observation for ticketing TSS 21 Traffic sampling -- ticketing MRR
22 Message rate service CHA 23 The call is chargeable TKR 20-23
Comprises TSO, TSS, MRR and CHA Word CHQW.phi.3 in entry word 11
PDL 3-5 Number of called digits previously deleted -- used to
restore deleted digits for alternate routing OJT 22 Originating
junctor translation NCB 23 New call bit, used by CCR handler only
gradual transition is in effect to indicate use of a specific copy
of drum memory. ______________________________________
Group CHT is a table which contains general information about a
call and its status while it is being processed. It consists of
twelve words.
Group CJA is used to store the originating class-of-service data
for a line or trunk which has originated. This information is
obtained from a drum table CLN or drum table CTN, depending on
whether the origination is a line or a trunk, and is placed in CJA.
Group CJA is accessed via the address assigned by the executive.
The table consists of two entry formats. Format type A is for trunk
originations and format type B is for line originations. There is
also a general format, format type C. The table consists of four
words, with a bias of three so that it falls in words 3, 4, 5 and
6.
______________________________________ Word CJAW.phi..phi. in entry
word 3 AUN 0-3 A unit identified during origination CLNAUN ABG 4-6
AB group identified during origination CLNABG MTX 7-10 Matrix
identified during origination CLNMTX SEC 11-12 Section identified
during origination SBS 13-14 Subsection identified during
origination CTMSBS Word CJAW.phi.1 in entry word 4 TGI .phi.-7
Trunk group incoming OSN 8-10 Originating service number ACO 11
Annoyance call originating TCN 12-13 Terminating control DS1 14
Disconnect status 1 DS2 15 Disconnect status 2 PDG 17-21 Published
directory number billing group DN1 18-22 Directory number 1
location Word CJAW.phi.2 in entry word 5 RCI .phi.-4 Receiving
control index SCA 6 Special code allowed ZCL 7-9 Zone associated
with class of service. FWS 10 Foreign WATS state MRS 11 Message
rate service MRT 12-17 Modified routing type IDC 18-21 Incoming
digit count INT 18-22 Intest circuit identity DN2 18-22 Directory
number 2 location Word CJAW.phi.3 in entry word 6 SAI .phi.-2
Selector A inlet SAU 3-6 Selector A unit SAB 7-9 Selector AB group
SMX 10-13 Selector Matrix SGI .phi.-3 Comprises SAI, SAU, SAB and
SMX TXS 14-15 Trunk matrix section ETN 16-18 Equipment type and
number MTP 19-21 Manual Test panel PTS 22 Pretranslator
standardization required ______________________________________
FIELD PROGRAM DESCRIPTION
General
this section describes the "Field Program," the name given to the
collection of programs that make up the software system. The
purposes of this section are to:
1. Identify the generic programs that make up the software
system.
2. Describe the functions each program performs in the system.
Field program
the "Field Program" is divided into five major divisions. They
are:
a. Executive program.
b. Application programs.
c. Maintenance programs.
d. Data Base.
e. Debugging Technique program.
The executive program provides centralized supervision over the
operation of the data processor unit hardware, and control of the
execution of the maintenance and application program software. The
application programs are responsible for providing the operational
characteristics of the system; e.g., call processing, ticketing,
metering, etc.
The maintenance programs provide system and subsystem level
maintenance functions; reconfiguration, scheduling of subsystem
diagnostic programs, special handling of interrupts that occur
during diagnostic operations, etc. The data base contains all of
the table data that is stored in the system by means of the data
processor unit's ferrite core and magnetic drum memories. The
debugging techniques program is used to locate troubles within the
software programs.
Refer to FIG. 47 for a block diagram of the field program
flowchart.
Executive program
the executive program is responsible for the scheduling of
application and maintenance programs. The executive program's major
objective is to provide an orderly and efficient means of utilizing
system hardware for these programs. The executive program provides
the following major system functions:
a. Scheduling of central processor time on a priority basis.
b. Distributing interrupts to the appropriate interrupt
processors.
c. Providing for the detection and handling of level two traps.
d. Scheduling and handling input/output device operations.
e. Providing the ability to time programs and events.
Central Processor Control
Both central processor time and the used non-resident areas in core
main memory are scheduled by the executive program. The allocation
of central processor unit time is accomplished by eight level
priority scheduling for the system software.
The eight levels are referred to as levels zero through seven.
Priority level zero is the highest level and level seven is the
lowest. The executive will attempt to service all central processor
time requests for programs waiting in priority zero before handling
priority one requests. Similarly, priority one requests will be
handled before those on priority level two, etc. Any one of the
eight priority levels may be used to request execution of core and
drum resident programs. Since only one program can be running at
any instant, the eight levels provide the executive with the
program priorities needed to properly schedule their processing.
For example, "catastrophic situation processing" programs are given
the highest level priority (level 0), and "routining maintenance"
programs are given the lowest priority (levels 5, 6, and 7). Call
processing, ticketing, and metering programs are scheduled on
levels 3 and 4.
The data processor unit scheduler module is part of the executive
program. Its function, as previously mentioned, is to schedule
other program modules on a priority basis. If the program selected
to run is core resident, it is merely started. If the selected
program is drum resident, it must first be brought into core memory
before execution can start. There is only one area available in
core for the execution of drum resident programs. This area is
called the "non-resident area" (NRA). The NRA consists of 2048
locations of core storage.
Interrupt and Trap Control
Processing interrupts received by the computer complex is a
function accomplished by the executive program through the use of
its interrupt processor modules. These modules analyze the cause of
an interrupt and initiate the appropriate software action.
There are eight hardware priority interrupt levels associated with
the computer central processor. These eight interrupt levels are of
a higher priority than the executive's eight software priority
levels. This means that the lowest hardware priority interrupt
level is higher than the highest software priority level.
In addition to the interrupt system there are two levels of
hardware traps, the traps are of a higher priority than the
interrupt levels. These hardware priority trap levels provide for a
"third party trap"(Level one), and a "central processor errors
trap" (Level two). The executive only "controls" trap level two.
The activation of any traps immediately suspends the running of the
current program. If this occurs, the trap program modules are
initiated and run before resuming execution of the suspended
program.
I/o device Control
The executive program also has control of the following
input/output devices:
a. High speed paper tape punch and reader.
b. Teletypewriters.
c. Marker communications registers.
d. Magnetic drums.
e. Magnetic tape units.
f. Maintenance and control center.
The executive schedules the input/output devices so that they may
be used with maximum efficiency. It performs all actions required
to operate the various input/output devices, thereby releasing the
application programs, etc., from the necessity of having to perform
these functions.
The executive interprets input messages from the teletypewriters
and schedules the correct program module, as determined by the
message control routine. The output data is made available in
specific formats with headers as required.
Timing Control
The executive maintains a real time clock which keeps track of
seconds, minutes, hours, days of the month, and months of the year.
The clock is normally read by an applications program when it
requires the date and time of day. Also provided, is an interval
timer which provides timing functions required by some application
programs.
The application program timing requests are timed by the interval
timer module in multiples of 16.67ms. For example, if a program is
run every minute, it will be called when a total of 3620 time
intervals have elapsed. (3620 .times. 16.67 ms. = approximately 60
sec.)
Call processing program
the call processing program controls hardware and analyzes data to
enable the system to perform its primary function which is to
process calls. The modules of the call processing program analyze
the data received from the markers and the register-sender
subsystems.
Origination and Digit Reception
Data is transferred between the markers, data processor unit, and
the register-sender subsystems. These subsystems are directed to
perform their functions of interfacing with the network and
completing the call via the call processing program. The primary
call processing modules that process an origination and prepare the
register-sender to receive digits are referred to as follows:
a. Class of service initialization.
b. Class of service analysis.
c. Non-dial line store.
The class of service initialization module performs the task of
obtaining a work area (spaces reserved in core memory) from the
executive program. Also, parameters are collected so that a class
of service drum translation for the originating line or trunk may
be made.
The originating class of service analysis module obtains the class
of service drum translation information, analyzes it, and writes it
into the register-sender core memory. The information received from
the drum translation is analyzed and the program determines if a
DTMF or MF receiver must be connected in order to receive digits.
Additional class of service information is obtained from core
tables and is then written into register-sender core memory by the
executive program as directed by the call processing class of
service analysis module.
The non-dial line store module formats the non-dial line digits
retrieved from drum storage so that they may be written into the
register-sender memory. This module updates register-sender memory
with the formatted digits and instructs the register-sender to
examine its memory for these digits.
Digit Analysis
The call processing program modules primarily responsible for
analyzing data supplied by the customer for determining the call's
destination are the following:
a. Pattern recognition handler.
b. Local and non-local pretranslators.
c. Digit translation initialization.
d. Digit translation analyzer.
The pattern recognition handler module is used when the
register-sender has recognized certain dialed digit patterns.
Specifically, the module initiates the routing of the call to an
operator when a single zero has been dialed in an office not
arranged for 0+ dialing. It also decreases the digits totals field
of the register-sender core memory, upon recognition of 1+ dialing
in an office so arranged.
The non-local pretranslator is scheduled by the call processing
program when the origination is from a foreign office. The
pretranslator is designed to add and/or delete digits as required.
For example, if the call is from a direct control office to a local
termination in this office, up to three (office code) digits may
have to be added.
The translation portion of call processing begins with a local
pretranslation of the incoming digits. The local pretranslator
first determines if a 1 or a 0 prefix digit has been dialed. If so,
the digit is deleted from register-sender core memory. Indicators
(bits set in core) are then set to indicate that a prefix digit was
dialed and what its value was (one or zero). If the register-sender
has not accumulated three digits (excluding the 1+ or 0+ prefix
digits), the digits total field in register-sender memory is
updated to a value of three. This indicates to the register-sender
that three digits are to be collected before a translation can be
performed.
Digit translation initialization takes place and first initiates a
three, then a four, five or six digit translation if required. The
type of translation initiated will depend on the call destination
which is usually apparent with the first three digits received.
The digit translation analyzer is responsible for deleting certain
three digit prefix codes such as those associated with ticketing
codes, reverting call access codes, and home numbering plan area
codes and determining whether translations other than the normal
three digit translation are required.
Routing
The routing function is controlled by a route translation
initialization module which initiates the correct drum translation
so that all of the information needed for the termination of a call
is available.
A directory number translation is usually initiated if the call
terminates locally, and a route number translation is usually
performed if the termination is to a foreign office. A selective
routing translation will be made in cases indicated by the
originating route type attached to the originators class of service
and by the prefix digits dialed.
Termination
The terminating cycle of call processing involves five major
modules to accomplish the task; they are referred to as
follows:
a. Route number and directory number translation analyzer.
b. Selector matrix routing.
c. Sender-receiver assigner.
d. Sending patterns and format control.
e. Termination cycle.
The route and directory number translation analyzer provides a
preliminary analysis of data taken from drum after a route number
or directory number translation. This module makes the following
route checks:
a. Route for a permanent signal trunk.
b. Route for reorder tone or line busy tone application.
c. Route for intercept.
d. Alternate route indicators to access the alternate route control
module.
The selector matrix routine module provides a means to determine
the routing from a selector group inlet to a selector group outlet
based on the type or types of equipment required to complete the
call.
The sender-receiver assigner maintains a check on the busy-idle
status of senders and receivers. It also maintains a check of the
on-line/off-line status of senders and receivers. The
sender-receiver assigner provides a map which shows the assignment
of all senders and receivers to register junctors.
The sending pattern and format control module prepares the called
number, calling number, and prefix digit storage cells to meet the
sending pattern requirements of the receiving office. The
register-sender memory is prepared by loading in register-sender
memory the sending data contained in the route number expansion
table. This module also gives the sending control information from
the route number expansion table to register-sender.
The termination cycle acquires terminating information for the
register-sender and the terminating marker. The terminating marker
uses this information to connect a terminating path through the
network. The register-sender uses this information for timing the
termination process.
The termination cycle module determines most of the terminating
requirements for the terminating marker and the register-sender.
More specifically it accomplishes the following:
a. Readies the routing and control information to be used by the
terminating marker and the data processor unit's communication
register.
b. Acquires the calling directory number and determines if sending
is required.
c. Schedules the succeeding call processing modules, if
required.
Alternate Routing
The alternate route control module is called for whenever an
alternate route termination is being processed. The primary purpose
of the module is the determination of whether the conditions set up
by the preceeding termination attempt require any modification.
To meet the requirements of an office, several types of alternate
routing are provided. The types provided are as follows:
a. Route number alternate routing for lines or trunks.
b. Alternate routing for PBX lines.
c. Trunk group alternate routing for trunk groups with an
availability greater than 80 (maximum scanning capability per
group) and sequential selection of groups.
d. Alternate routing for oversize trunk groups providing a balance
by random selection of one of two trunk groups for even traffic
distribution.
Ticketing program
the primary purpose of the ticketing program is the collection,
formating, and recording of toll data for future processing. The
ticketing program consists of 16 modules to perform the necessary
ticketing functions. The software operates in conjunction with the
automatic toll ticketing subsystem hardware to provide ticketing
data for Local Automatic Message Accounting (LAMA) operation.
The ticketing subsystem tickets subscriber dialed automatic number
identification traffic. It tickets direct distance dialed (DDD)
toll traffic as "timed" calls while ticketing message rate service
(MRS) local traffic as "pegged" calls (calls recorded for answer
only, not timed). Only calls originating within the local office
are ticketed.
Ddd call
The brief description that follows illustrates the way in which the
ticketing software handles a DDD call.
When a DDD call is originated, the call processing program
determines the identity of the trunk that was seized. At this
point, the call processing program stores the identity of the
seized trunk for this call, and transfers control to the ticketing
seizure module.
The seizure module checks the activity bit table to assure that the
associated trunk activity bit is 0. This (activity bit 0) will
inhibit the scanner from looking at the trunk supervisory contacts
during outpulsing. Control is then returned to the call processing
program.
If the last call of this trunk was incomplete, the activity bit
will still be a 1 when checked by the seizure module. In this case,
the seizure module would reset the activity bit to 0 and schedule
the recording of the "incomplete call" information on magnetic tape
(if traffic observation is being conducted).
Assuming a normal call, after cut-through (register-sender
outpulsing completed) has occurred, the call processing program
passes the equipment number of the trunk, the called number, and
the calling number to the ticketing call completion module. The
call completion module formats this information, and schedules its
writing in a table on the drum. The call completion routine then
sets an indicator causing the scan interrupt routine to begin
interrogating this trunk for an answer condition. At this point the
call completion module returns control to the call processing
program.
The scan interrupt handler interrogates the trunk for an answer
condition until an answer condition is found. When answer is first
detected, the scan interrupt routine begins timing a 2.4 second
charge delay interval. If the answer state remains true for the 2.4
second interval, the time of answer is recorded and is scheduled to
be written into the drum cell associated with this trunk.
The scan interrupt handler continues to interrogate the trunk,
looking for a disconnect condition. If a false disconnect is
detected (called party on-hook, calling party off-hook), the
disconnect time is stored in a table on drum and the associated
trunk bit is set in the disconnect recorded table. The scanner will
continue monitoring the trunk for as long as the calling party
remains off-hook. If, while the calling party is still off-hook,
the called party again goes off-hook, the trunk bit in the
disconnect recorded table will be reset (0). This nullifies the
disconnect time previously recorded. The scanner always continues
its supervision until both parties have gone on-hook, indicating a
true disconnect. When a true disconnect occurs, a request is
generated to move the call data associated with the trunk from the
drum cell to a work area in the computer core main memory. The scan
interrupt handler also requests the scheduling of the output format
module, after the call record has been read off of the drum.
The output format module is responsible for arranging call data
into a useable format for magnetic tape output. On completion of
its assigned task, it indicates that the call record buffer format
module should be scheduled.
The call record buffer format module is responsible for moving the
formatted call record into a buffer work area, determining where
the call data should be stored, and when the buffer becomes full,
indicating to the magnetic tape 1/0 scheduler that the buffer
contents should be outputted on magnetic tape.
Mrs call
An MRS (message rate service) call is handled in a fashion similar
to that of the DDD call, except that those operations necessary to
time the call and detect disconnect conditions are not used. The
MRS calls are recorded when the scanner detects a true answer
condition. The record contains the calling number and the answer
time.
Miscellaneous Functions
In addition to its normal recording tasks, the ticketing program
also provides instructions for checking certain hardware
malfunctions. The ticketing program provides for detecting trunks
with scan contacts that remained in an open or closed state for
more than a 24 hour period. It also provides for detection of any
trunk on which a call was in progress for more than one hour. Such
malfunctions are identified by TTY output messages.
Metering program
the metering program provides a means to measure traffic density
through the office. Also measured is the application of reorder
tone when such application is due to a system malfunction. The
various metering modules are driven by the call processing and
executive programs.
The metering program provides the following types of metering:
a. Overflow metering.
b. Call routing metering.
c. Call event metering.
d. Grade of service metering.
e. Reorder tone application metering.
Overflow Metering
Overflow metering measures the number of times a line busy
condition exists from a selected group of local directory numbers.
The count is taken each time a call termination attempt is made to
one of these numbers.
Call Routing Metering
This function provides a count of the number of times specified
traffic originations have been connected to specific traffic
terminations. Lines and/or trunks may be counted.
Call Event Metering
The purpose of this metering is to count the number of times a
given set of conditions occurs in the processing of a call through
the system. The call event metering is driven by various call
processing modules. Some of the events counted are:
a. Blocked call in the line matrix.
b. Call blocked by all register junctors busy.
c. Successful connection to register junctors.
d. Blocked calls in the selector group matrix.
Grade of Service Metering
Grade of service metering or, dial office administration, counts
the ability of the system to switch calls through the network. A
count is made of calls blocked in the switching matrices caused by
all AB links busy. The grade of service metering module interfaces
with the call processing program to acquire information necessary
to perform this metering function.
Reorder Tone Application Metering
This metering function counts the number of times reorder tone is
applied when caused by a system malfunction. The reorder tone
metering function is driven by the call processing software so that
various fault conditions resulting in reorder tone application
initiate the count.
Input-Output Devices
The normal output of the metering program is via the high speed
paper tape punch. The adminstrative teletypewriter may be used to
output metering messages in response to an appropriate input
request. The metering modules that require input parameters receive
them via the high speed paper tape reader.
Maintenance program
the overall maintenance program consists of two major sections,
having the capability of performing maintenance operations on the
system and/or subsystem level. The maintenance program is composed
of program modules and tables which are stored both in core and on
drum.
This extensive maintenance software system is necessary to insure
that the No. 1 EAX system meets its design goal of a maximum
downtime of 1.5 hours in a 30 year period. The maintenance software
needed to accomplish this goal makes up approximately 65 percent of
the total software package.
That group of modules concerned with the overall control and
service of system level maintenance functions is called common
maintenance. Common maintenance programs have functions useful to
most subsystem diagnostic programs but are not peculiar to any
specific one. They provide centralized control to minimize
interference among subsystem diagnostic functions.
The subsystem diagnostic program modules allow the hardware system
to operate in the presence of faults and errors. They provide the
following functions:
a. Malfunction detection.
b. Fault isolation (of a faulty unit).
c. Malfunction recovery and restart (after disturbances due to
diagnostic testing or repairs).
d. Fault localization (to a location within a few circuit
boards).
e. Repair verification (checking a "repaired" unit before placing
it in service).
f. Routining (testing the capability of a subsystem or unit to
perform certain tasks).
Common Maintenance
The major functions of the common maintenance are as follows:
a. Scheduling of subsystem diagnostics.
b. Reconfiguration of the system or subsystem.
c. Audits.
d. Power monitor scan of power failure detectors.
e. Central control of error counters.
f. Display lamp control.
g. Special analysis of TTY input messages.
The common maintenance programs have the capability of interfacing
with each other and to the diagnostic subsystem programs. These
common maintenance programs also interface with the executive
program and the maintenance personnel in the office.
The common maintenance programs interface with each other and the
subsystem maintenance programs via the normal interfaces of the
executive, and the diagnostic control program (DIACON). When
maintenance programs call DIACON (a common maintenance module) it
will schedule these programs via the executive. DIACON uses a
special indicator attached to the front of each of the executive's
queues that permits control to be transferred from the executive to
DIACON. This enables DIACON to gain control without the requirement
of first having a work area. After DIACON receives control, it
acquires a work area and schedules the requested program by using
the executive's scheduler module.
The interface with the maintenance personnel is accomplished via
requests from the MMC controls, TTY input messages, etc. This
interface causes various common maintenance programs to be
scheduled and effectively gives the maintenance man control of the
system.
Part of the common maintenance software is a configuration control
program (CONFIG) that exercises control over system status and
configuration. This program performs the following major
functions:
a. It receives requests for configuration changes. The requests
come via TTY input, MCC pushbutton demands, diagnostic software,
and power monitor scan software.
b. It determines if a configuration change can be made without
affecting system availability.
c. It maintains a record of current system status in the system
status table.
d. It performs all legal configuration changes that are requested,
or calls the appropriate program to effect the change.
e. It provides for the appropriate TTY output which contains the
configuration change information.
The maintenance interrupt and access program (MANIAC) and its
associated tables provide centralized control over special
processing of interrupts. This requirement is necessary because,
during diagnostic functions, inadvertent or deliberate interrupts
may occur. These interrupts must not be allowed to affect normal
processing, therefore, the MANIAC program is used to provide the
maintenance feature of allowing these interrupts to have special
handling.
The system clear and start program (SYSCLR) provides centralized
control for initializing or re-initializing the
system/subsystem(s). The SYSCLR program is used initially (at
cutover) to place the system into operation. It is also used to
re-initialize the system on demand, and to recover the system (or
subsystems) from malfunctions for which there are no other means of
recovery and then return the system to normal processing.
The "audit" programs perform checks on significant software areas.
The following are the areas checked:
a. The specially protected areas of read only core memory.
b. The linking of work areas to queues, call history tables, and
hitching posts. (Hitching posts are one entry queues reserved for a
particular system function.) All lost work areas will be returned
to the appropriate size spare work area queue.
c. The MF sender and MF receiver assignment tables to compare the
on-line/off-line, busy/idle software status to the actual hardware
status.
d. the MANIAC tables to insure that they are being correctly used
by the programs accessing them.
e. The system status table to insure that all data within the table
is correct and that no illegal entries have been made.
f. The call history tables to verify that the software indication
of each register junctor's off-line and busy status is consistent
with its actual hardware status.
The audit programs also perform the following two timing
checks:
a. The non-resident area audit of core memory to insure that a
program does not maintain continuous control of the NRA. This
software "time-out" feature allows a program to only occupy the NRA
for a certain predetermined time. If this time is exceeded and
certain other conditions are met, the system clear and start
program will be called.
b. The input/output handler time-out audit to provide a software
time-out check for each 1/0 device. This time-out check is required
so that an 1/0 device does not hold up normal processing. If a
device does not respond within a predetermined time, the
appropriate 1/0 handler abort program is notified.
The power monitor scan program (PMSCAN) is used to reconfigure the
system around any power failure that may occur. PMSCAN monitors the
output lines from the office power alarm circuits via the power
monitor adapter to ensure that all power conditions are reported to
the system. If a power fault is detected in a particular unit, that
unit is placed off-line by the configuration control program
(CONFIG). CONFIG will update the system status table so that it
will represent the current status of all units in the system.
The error count program (ERRCNT) provides centralized control over
incrementing, reading out, or resetting of certain software
counters. These "error" counters are used for reasons other than
error counting. ERRCNT provides the requesting program with the
ability of having their respective counters reset, read and printed
out via TTY, or incremented and printed out via TTY upon
overflow.
The lamplighter program (LMPLTR) provides software control over the
lighting and extinguishing of the lamps associated with the
maintenance display adapter of the maintenance display adapter of
the maintenance control center (MCC). LMPLTR maintains the status
of these lamps in a table in core memory. When a lamp is to be
turned on or off, LMPLTR calls the MCC 1/0 handler program to
perform this function. When a certain predetermined number of work
area overload lamps are lit, the work area audit program (WARAUD)
is scheduled via DIACON. WARAUD may call the system clear and start
program under certain work area overload conditions.
The configuration pushbutton handler program (CNFPBH) provides the
maintenance personnel with the capability of requesting
reconfiguration of any of the subsystems from the maintenance and
control center. Activating the applicable MCC pushbuttons will
accomplish the reconfiguration via CONFIG. The CONFIG program will
insure that both units of a pair are not taken out of service.
Subsystem Maintenance
The subsystem diagnostic programs that handle the faults and errors
that occur in the system, and which permit the system to function
in spite of these malfunctions are as follows:
a. Processor configuration group (PCG) diagnostic program.
b. Register-sender diagnostic program.
c. Markers and network diagnostic program.
d. Drum memory system diagnostic program.
e. 1/0 peripheral apparatus diagnostic programs.
f. Space divided equipment routining program.
In addition to the primary subsystem maintenance programs
(malfunction detection, fault isolation, etc.) there are the
routining and auditing programs. The malfunction detection, fault
isolation, and fault recovery programs are handled quickly because
call processing is inhibited during their execution. All the other
subsystem maintenance programs are deferrable and are normally run
intermixed with the call processing programs.
The malfunction detection programs respond to hardware detectors
and provide for separation of faults and or errors, routining of
seldomly used circuits, routining of malfunction detectors, and
routining of space divided equipment. The fault isolation programs
are used to determine which one of a pair of redundant units is
faulty and to separate (isolate) the faulty unit from the rest of
the system.
The malfunction recovery and restart program will return the
hardware/software to normal operation after disturbances due to
diagnostic testing or repairs. Fault localization programs are used
to narrow down the location of the fault to a few circuit boards
and provide a trouble report printout on the maintenance
teletypewriter. The repair verification programs utilize combined
diagnostic processes and are executed before returning a "repaired"
unit to service.
A processor configuration group (PCG), consists of one each of the
following computer complex units: central processor (CCP), memory
control (CMC), core memory (CMM), and the priority interrupt and
sense line circuits of the line processor (CLP). The PCG diagnostic
program operates in response to hardware detected malfunctions.
These malfunctions are primarily detected by the specially designed
hardware of the computer third party circuit (CTP) which is used to
insure the matching integrity of the duplexed PCG's.
When a PCG mismatch occurs, an isolation program will determine
whether the malfunction was due to a fault or a transient error.
The PCG mismatch caused what is known as a third party trap (level
one). Both CCP's will be taken off-line, and therefore out of sync,
when a level one trap occurs. The isolation program used to
determine the fault (if a transient error was not the cause) will
run both CCP's independent of one another through a set of the same
diagnostic detection programs. These programs exercise all logic
elements that could have caused the mismatch. The programs will
return periodically with intermediate results to the CTP. A faulty
unit is determined if an incorrect result occurs or if a diagnostic
program fails to return for a check in either CCP.
The register-sender's isolation modules wll also be initiated by a
hardware detected malfunction. The synchronized common logic units
of the register-sender are compared by special hardware matching
circuits to determine the faulty unit. Isolation is accomplished by
analysis of data collected at the time of the non-comparison, by a
RCC logic simulator (stored in the drum memory system) used as a
third party element, or by exercising RS functions under software
control. The fault localization software will find the general
location of the fault and will then initiate a TTY trouble report
output to inform the maintenance man at the MCC. The
register-sender diagnostic program also includes special software
used for monitoring troubles in space divided apparatus outside of
the RS common control equipment (e.g., MF senders and receivers,
RJ's, etc.). This special software contains system trouble monitors
and busy/idle and configuration status indicators for the space
divided apparatus.
The marker and network malfunctions are detected primarily by
hardware contained within the markers. Hardware circuits take the
affected marker out of service and an interrupt is generated which
will cause the executive program to schedule the appropriate
diagnostic program. The localization diagnostics are used to
analyze faults in the markers.
The drum memory system diagnostic program operates in response to
hardware detected malfunctions and software generated requests. It
provides basis malfunction detection of parity checks, special drum
timing checks, and special program segment marks. Isolation is
performed via task retrys on the duplexed units. The fault
localizing software finds the general location of the fault and
will provide a TTY trouble report output. The DMS maintenance
program also provides for data transfers and comparison checks
between drums. Repair verification and routining software is also
included in this program.
The I/O peripheral apparatus diagnostic programs are initiated by
various hardware detected malfunctions. The I/O maintenance program
includes diagnostics on the computer channel multiplexor and its
associated controllers (TDB, MDB, CDB AND CCR). Special diagnostic
software is provided for the unique features of the peripherals.
This software is used with the automatic peripherals (ticketing
scanner unit and magnetic tape unit) and the manual interactive
peripherals (teletypewriter, paper tape reader and punch, and the
maintenance and control center displays and pushbuttons).
The space divider equipment routining provides test connections to
space divided equipment (lines, outgoing trunks, junctors, senders,
and receivers) to allow for manual testing. It also provides for
automatic routining of this space divided equipment. Another
feature of the space divided routining program is to provide for a
metallic path for testing via an incoming remote test trunk.
Routining requests from remote locations are provided for via a
special incoming line.
The manual testing of space divided equipment is accomplished by a
testman via controls on the MCC.
The automatic routining of space divided equipment is primarily
performed by the maintenance routining logic (MRL) hardware of the
MCC and its associated software. During and/or after testing, the
MRL sends data (such as test status and test results) to the CCP.
The diagnostics performed on the space divided equipment can be
initiated by detection of an error, a request via the TTY to
perform a specified routine, or the routine may be periodically
scheduled by the timed routine scheduler module (L18).
Testing from a remote location (via additional testing equipment)
can provide the following features in addition to manual and
automatic routining:
a. Initiate single shot and repetitive automatic tests.
b. Initiate requests for system status or configuration
reports.
c. Receive teletypewriter printouts of maintenance test data,
system status, etc.
d. Perform manual tests on customer lines.
Data base
the data base contains all of the stored table data used by the
system such as specific office data, translation data, etc. The
data is stored in data processing unit core memory and on the drum
memory.
The data base contains all of the stored table data used by the
system such as specific office data, translationdata, etc. The data
is stored in data processing unit core memory and on the drum
memory.
Office data is stored in tables and may be core or drum resident.
The tables consist of a field or fields of data which are retrieved
together and are contained in a single physical table. The
following represents the types of data contained within the data
base:
a. A series of data tables which contain variable data peculiar to
each office (directory numbers, code translations, routing
instructions, etc.).
b. Engineerable data concerning hardware configurations (i.e. line
and selector matrix grading).
The following represents the type of variable data needed for an
office. This type of information is normally supplied by the
operating telephone company.
a. Line number identity.
b. Incoming trunk group identity.
c. Terminating classification.
d. Originating routing types.
e. Foreign numbering plan area.
f. Directory numbers.
g. Ringing mode (Frequency and line side).
h. Type of station apparatus (dial or DTMF).
i. Blocking of supervision on answer.
Organization
The data that appears on the drum and in core is arranged in a
logical pattern. A drum layout typical arrangement has the drum
divided into 18 segments. The core image (a duplication of the
information in certain areas of core for reliability reasons) is
found in the first 31/2 segments. The remaining 31/2 segments
contains programs. Variable data, such as information pertaining to
ticketing, is contained in segment 8. Segments 10 to 18 contain the
translation data. A portion of segment 7 and segment 9 are spare
areas.
FIG. 48 illustrates a typical organization of core memory. The
patch areas shown are used in debugging operations. The constant
data, is data that remains unchanged during the life of the
program. The parameter data provides input to various programs so
they may be properly run. The variable data consists of data that
is held temporarily during processing; this information is held in
a work area. The drum control unit initialization area contains
tables of data that are used to enable transfer of other data
between the drum and the core memory and between the core memory
and the drum.
System update program.
the purpose of the system update program is to allow the permanent
data associated with the system to be modified, when required, and
to provide a means to add new information to the stored data.
Whenever a hardware change is made to an office, usually the data
base will require an update; also, the addition of new customer's
lines to the office and any changes in service require an update.
These changes are accomplished by means of the system update
program. The office administration program permits the following
changes:
a. Adding new information to the system.
b. Modifying information already in the system.
c. Deleting information in the system.
To make any required modifications or changes to the system, the
system update program is activated by an input via the:
a. High speed paper tape reader (HSPTR)
b. Low speed paper tape reader (LSPTR)
c. Office administrative teletypewriter (LOAT)
The system update program consists of 10 modules to accomplish its
required task, that is, keeping all stored office information
current.
In updating the office, various checks are required on the data
supplied, such as limit checks on numeric data and reasonability
checks on alphabetic data. Also checked is the quantity of data
received to see that it is sufficient to program a successful
update.
When the data is loaded into the system (via tape or
teletypewriter) for the update, the program initializes this data,
or converts it in form, so that it may be interpreted by the
program. The data is then checked and analyzed, as mentioned
previously, for errors and quantity of information provided.
If new information is being loaded, the program checks to see that
the required number of storage locations are available for the
data. If it is desired to remove information already in storage, a
program module will zero all information existing in the location
specified by the update request.
The program is capable of changing information in storage as
indicated by the update request. The data is transferred to one
drum for both core and drum resident data. A drum-to-drum transfer
is then made to equalize the data between drums, and also to
equalize the core data.
A punched paper tape of the new data is supplied by a module for
office back up purposes. The tape may also be used to remove the
update entered, via an input device.
Debugging techniques program
the debugging techniques program provides a means to locate
troubles within the software programs. The program is not run
automatically, but must be activated by office personnel.
The program has the ability to provide selective dumps of
information existing in core, drum, register-sender or sense lines.
The information is outputted on the administrative teletypewriter
and analyzed to see that the information present is as it should
be. Any program, at any point in the program, may be selected for
dumping.
The program is enabled by an input set instruction, which specifies
what is to be dumped and under what conditions it is to be
provided. At specified points in the field program called
breakpoints, which are variable and defined by the input
instructions, the debugging techniques subprogram checks for the
previously mentioned conditions and produces an information dump
when the conditions are satisfied. Two types of breakpoints are
available, hardware or software.
A computer programming console (PRCF) provides thumbwheel type
switches for setting the address of the breakpoints. The hardware
will now give control to the debugging techniques subprogram via an
interrupt when the instruction at the address specified by the
thumbwheel switches is executed. Software breakpoints are inserted
into the program by the debugging techniques subprogram; this
subprogram gains control when the instruction at the specified
address is to be executed. The input set instruction is inputted
via the teletypewriter.
EXECUTIVE PROGRAM DESCRIPTION
General
this section describes the Executive Program, the program used to
provide centralized supervision and control over the operation of
the Data Processor Unit (DPU) hardware and over the execution of
maintenance and application programs. The Executive Program is a
part of the Field Program and is a major portion of the system
software.
The purposes of this section are:
1. To identify the generic programs and tables that make up the
Executive Program.
2. To describe the major functions of the "executive" and the
individual functions of the associated program modules and
tables.
Organization
the Executive Program (executive) provides a proper operating
environment for execution of the ticketing, metering, and call
processing application programs and for the maintenance programs.
To accomplish this, the executive schedules the use of the central
processor and its associated memory, and utilizes a priority
interrupt system for efficient hardware operation.
The executive is used as a means of linking application programs.
The executive contains program modules that are used to communicate
with input/output (I/O) devices such as the teletypewriters, paper
tape devices, magnetic drums, etc. These program modules schedule
the operation of the devices and perform various I/O functions upon
request from the application programs. The I/O devices associated
with the system are shown in FIG. 35.
Most real time systems have a scheduling routine which looks at the
groups of programs waiting in line (in queues) to be run, and
decides, according to a priority system, which program will be
processed next. This scheduling routine obtains control whenever
the program currently running relinquishes its control of the
computer. In this system, the program module which performs this
function is called the DPU Scheduler (E/1).
A "queue scan" routine is entered whenever an application program
ends and the decision of which program to run next has to be made.
By interrogating the queues, the queue scan routine determines the
application program having the highest software priority, and
passes control to this program. The scanning of queues is another
function of the DPU Checuler (E.phi.1).
The Executive Program consists of a group of modules which exercise
software control over the Data Processor Unit and its associated
I/O equipment, and also over execution of the application and
maintenance programs. To provide this capability, the executive
schedules DPU time, the use of various areas of core memory (work
areas), and the processing of interrupt signals from the I/0
devices. These interrupt signals control the introduction of new
tasks into the system via the I/0 devices.
The Executives Program modules access various tables in core memory
and drum memory. Some of these tables (FIT, FII, FMA, etc.) are
considered part of the executive, while others such as the Call
History Table (CHT) and the Program Locator Table (PLT) are
accessed by several other programs, and are not considered part of
the executive.
Queuing
As part of a basic understanding of the Executive Program
scheduling process, a knowledge of queue structure is necessary.
The queue structure consists of two parts: the entries in the queue
and the queue root. The queue entries are work areas which are
assigned to specific programs. Each queue has a unique queue root
associated with it. This queue root consists of a six word table
located in computer core memory.
A standard queue root format is shown in FIG. 49. An explanation of
the information contained in each queue root word follows:
a. Word .phi. (Bits 0-14) contains the address of the first word of
the first entry in the queue. If there are no entries in the queue
at this time, these bits will be set to zeroes.
b. Word 1 (Bits 0-14) contains the address of the first word of the
last entry in the queue. If there are no entries in the queue,
these bits indicate the address of the first word of the next queue
root.
c. Word 2 (Bits 0-23) contains the number of entries currently
remaining in the queue.
d. Word 3 (Bits 0-23) contains the total number of entries that
have even been linked to the queue.
e. Word 4 (Bits 0-23) contains the total number of times that
entries were linked to the queue after it was emptied.
f. Word 5 (Bits 0-23) contains the maximum number of entries that
the current queue length attained.
For this discussion of the operation of the executive, the first
three entries are the most important. Words .phi. and 1 are used to
link the queue root to the first and last entries in the queue.
Word 2 represents the number of work area linked to the queue.
Words 3 through 5 contain statistics used to determine how well the
queue is performing.
FIG. 50 shows how work areas can be linked to each other in a
queue. The method of linking uses the least significant fifteen
bits of the first word of each entry. The first word of the queue
root points to the address of the first entry in the queue, and the
first word of the first entry points to the address of the second
entry, the second entry points to the third, etc. The last entry,
since it has no work area to point to, will contain all zeroes in
its first word.
Work Areas
Work areas are sections of computer core memory used for
intermediate storage of data during the processing of application
programs. These work areas are divided into six sizes, which are 8,
16, 26, 38, 64, and 100 words in length. The quantity provided of
each size is determined by the size of the system. Work areas are
said to be residing in their "spare queues" when they are not
assigned to any particular program.
Before the executive can schedule an application program module to
be run, the program must request and obtain a work area. When the
work area is assigned to the program, it will remain so until the
required task is completed. When it is no longer needed, the work
area is released. This action effectively places the work area back
into its appropriate spare queue.
When requesting a work area, the caller (requesting program) must
specify the proper size. The Executive Program then assigns a work
area of the proper size (if available) to the requesting
program.
The queue size data is placed in the Work Area Type indicator field
of word .phi. (FIG. 4). Bits 0-14 of this same word contain the
core address of the next program on that priority level to be
processed.
Word 1 indicates the next program to schedule and its priority.
Word 2 contains the identity of the program presently using the
work area. Word 3 contains the identity and priority of the program
to be run in case the program presently using the work area
encounters trouble. Word 4 is used to indicate a particular RS pair
and RJ identity. Bits 15-20 of word 4 are error indicators related
to the various I/0 programs. Word 5 contains the address of the
Call History Table entry associated with the RJ specified in word
4.
See FIG. 51, which shows the following fields in the first six
words of a work area:
Lkc -- linkage control used to link the work areas to queues
Typ -- work area type (size) indicator indicating the proper work
area queue to which the spare work area is to be returned
Npg -- identifies the next program module to be scheduled
Eln -- indicates the entry line number of the program specified in
bits 0-14
Pri -- indicates the absolute priority in which to run the task
identified in bits 0-14
Tpf -- identifies the program presently using the work area
Tel -- indicates the entry line number of the program specified in
the TPF field
Fep -- identifies the program to be scheduled for forced exits
(Error Program)
Fel -- indicates the entry line number of the Error Program
Fpr -- indicates the absolute priority in which to run the Error
Program
Rji -- indicates the particular RJ associated with a call (when the
work area is used for call processing)
Cht -- indicates the address of the entry in the Call History Table
associated with a particular RJ
Software Priority Structure
The allocation of central processor (CP) time to various
application programs is accomplished by eight software priority
levels. These levels are 0 through 7, with level 0 the highest and
level 7 the lowest. The executive attempts to service all CP time
requests in priority level 0 before servicing those on level 1.
Similarly, priority level 1 requests are handled before those on
level 2, etc.
Any one of the eight levels of priority may be assigned to a
program. Since only one program can be running at any instant, the
eight priority levels provide the executive with the ability to
schedule the processing of the most important programs first. For
example, isolation programs for major system malfunctions are given
the highest priority (level 0), and the routining maintenance
programs are given the lowest priorities (levels 5 6, and 7).
Certain guidelines have been formulated to generalize the
assignment of programs to specific priority levels. These priority
allocations are as follows:
a. Level 0 -- castastrophic situation processing.
b. Levels 1 and 2 -- general maintenance programs.
c. Levels 3 and 4 -- call processing, ticketing, and metering
programs. The Watch Dog Timer Manipulator Module (L4.phi.) is
scheduled on Level 4.
d. Levels 5, 6, and 7 -- routining and miscellaneous programs.
Priority Interrupt Levels
There are eight hardware priority interrupt levels associated with
the central processor. These eight interrupt levels are of a higher
priority than the eight software priority levels. Therefore, the
lowest hardware interrupt level is higher than the highest software
priority level.
The executive has the ability to identify any interrupt causes and
transfer control to modules which service these causes. The eight
hardware interrupt levels and their primary causes are listed
below:
a. Level 1 -- manual input requests from the attention key of the
teletypewriters, power failure indications from the voltage
monitors and power alarms, status and configuration control panel
inputs, CCP/CTP configuration changes, and DDT matches.
b. Level 2 -- drum control unit, computer memory control, computer
communication register, and ticketing device buffer (TDB) errors;
register-sender faults; and originating marker and terminating
marker malfunction alarm indicators.
c. Level 3 -- timed interrupts from the main and standby real time
clocks every 16.67 milliseconds, and ready interrupts from the
TDB's.
d. Level 4 -- ready interrupts from the computer communication
registers.
e. Level 5 -- ready interrupts from the drum control units.
f. Level 6 -- 1/0 error interrupts from the computer device buffers
(CDB's).
h. Level 8 -- register-sender error count and system trouble
interrupts, general alarm errors (main clock, standby clock, etc.),
and computer line processor errors.
The executive controls the cause identification and the processing
of multiple simultaneous interrupts that occur, regardless of the
interrupt levels involved. The executive provides for returning
control to the interrupted program after all interrupt processing
is complete.
When an interrupt occurs, the executive Register Stacking Module
(F13) saves the contents of the computer central processors index
registers (X1, X2, and X3), the contents of the A and Q registers,
and that of the four pseudo registers (in core memory). When
interrupt processing is completed, the F13 module restores the
contents of the registers and returns control to the interrupted
program at the calling location plus one.
Traps
In addition to the eight level interrupt system, there are two
levels of hardware priority traps. These trap levels have a higher
priority than any of the interrupt levels.
The level 1 or third party trap occurs when there is a mismatch
between the duplexed central processors or the memory control units
during synchronous operation. When a third party trap occurs, the
instruction in process is completed, and the active CCP is forced
to a dedicated location (address) in main memory. A third party
trap program located at this address is used to determine the cause
of the trap. The Executive Program does not become involved with
third party traps.
Level 2 trap identification and processing is controlled by the
Executive Program. Such traps are caused by internal errors that
occur in one central processor during simplex operation, or
simultaneously in both central processors during synchronous
operation. A level 2 trap signal will be generated by one or both
CCP's by any of the following:
a. Data even parity error -- occurs when even parity (rather than
odd) is detected from computer core main memory, the
register-sender, or the channel multiplexor.
b. Instruction even parity error -- occurs when even parity is
detected while reading a new instruction from memory.
c. Division by zero -- occurs during a division instruction when
the divisior is detected as being all zeros.
d. Invalid operation code -- occurs when the decode of the
instruction operation field detects one of the following invalid
codes: 00, 27, or 63.
e. Memory reference time-out -- occurs when one of the memory
reference signals (main or register-sender memories) remains true
for more than 140 microseconds.
f. Port seven error -- occurs when the central processor attempts
to access memory out of range, or when it attempts to write into
"read only memory."
Note: if, during synchronous operation, an error occurs causing a
level 2 trap signal to be generated by only one CCP, the Computer
Third Party Circuit (CTP) will generate a third party trap and the
level 2 trap signal will be ignored.
Level 2 trap causes (a) and (i b) result in a retry of the
instruction. Causes (c), (d),(e), and (f), or failure of an (a) and
(b) retry, result in a transfer to the System Clear and Start
Program.
Program Linkage
The program modules of the executive, and also those modules
associated with other programs, contain one or more entry lines.
These lines serve as entry points into a program module. They are
selected for the various functions they provide. Each module may
have a maximum of eight entry lines. Linkage between application
programs is via these entry lines and by the use of branch
instructions (BUN, BSP, etc.).
The linking mechanism involves two vector tables, The Program
Locator Table (PLT), and the Entry Line Locator Table (ELT). PLT is
used as a pointer to an address in the ELT associated with the
first entry of a specified core resident program.
PLT is also used to locate entry lines for drum resident programs.
In such cases, the ELT is actually part of the program rather than
a separate table in the core memory. The ELT is located at the
beginning of each program read from drum and is referenced by the
executive at this location.
When a program is coded, it is not necessary to know whether the
program is core or drum resident because linkage from one program
to another can be established by using a macro. A macro is a group
of instructions which takes the identity of the requested program
and its entry line address, and transfers directly to the requested
program providing both the requesting and requested programs are
core resident. If either program is not core resident the macro
schedules the linkage through the DPU Scheduler Module.
Functional description
this part briefly describes the five major functions of the
executive and the major program modules associated with these
functions. Some program modules are common to more than one major
function such as those that "link" and "unlink" the work areas from
the spare queues. Refer to Table EX1 as a reference to the titles
of the major executive modules.
The primary objective of the Executive Program is to provide an
orderly and efficient means of utilizing system hardware for
processing application and maintenance programs. To accomplish
this, the executive provides control over the following system
functions:
a. Scheduling of central processor time on a priority basis.
b. Distribution of interrupt requests to the appropriate interrupt
processors.
c. Detection and handling of level 2 traps.
TABLE EX1 ______________________________________ MAJOR EXECUTIVE
MODULES GROUPED ACCORDING TO FUNCTION MODULE FUNCTION NUMBER MODULE
NAME ______________________________________ E.phi.1 DPU SCHEDULER
CENTRAL E.phi.6 QUEUE INTERROGATION PROCESSOR F.phi.2 LINK TO QUEUE
CONTROL F.phi.3 UNLINK FROM QUEUE F.phi.4 WORK AREA ASSIGNMENT
F.phi.5 WORK AREA RETURN E1.phi. TRAP 2 CAUSE ANALYSIS F13 REGISTER
STACKING INTERRUPT F34 OM STANDBY INTERRUPT PROCESSOR AND TRAP
E21-28 INTERRUPT CAUSE AND ANALYSIS CONTROL F51 RS INTERRUPT
PROCESSOR F52 MARKER MALFUNCTION INTERRUPT HANDLER F58 TTY USE
REQUEST INTERRUPT PROCESSOR E2.phi. HOT SENSE LINE FINDER F32B CCR
READY INTERRUPT HANDLER E.phi.2 INTERVAL TIMER REQUEST ACCEPTOR
E.phi.3 INTERVAL TIMER HANDLER TIMING E.phi.4 INTERVAL TIMER
INTERRUPT PROCESSOR CONTROL E.phi.5 REAL TIME CLOCK E.phi.8 REAL
TIME CLOCK INITIATE AND UPDATE E.phi.9 MINUTES TIMER F.phi.1 RS
TIMING INTERLOCK DRUM F35 MANIPULATOR INPUT/OUTPUT F29 DRUM
SCHEDULER DEVICE F30 DRUM HANDLER CONTROL F40 DRUM HANDLER
SUBROUTINE F41 DRUM HANDLER SUBROUTINE E07 BLOCK LOAD/STORE
COMPUTER COMMUNICATION REGISTER F31 CCR SCHEDULER F32A CCR HANDLER
F36 CCR SUBROUTINE 1 F38 CCR SUBROUTINE 2 F14 CHT ADDRESS
CALCULATOR F33 RJ TRANSLATOR F37 CCR ERROR ISOLATION AND RECOVERY
F39 CCR LOAD/UNLOAD TTY/PAPER TAPE AND TICKETING EQUIPMENT F.phi.6
INPUT MESSAGE ANALYSIS F.phi.7 OUTPUT FORMAT F.phi.8 RS ACCESS
F1.phi. PRINTOUT INHIBIT F22 PAPER TAPE IDENTIFICATION F25 I/O
INTERRUPT DISTRIBUTOR F26 I/O SCHEDULER F27 I/O HANDLER F28 TAPE
CONTROL F23 HOURLY PRINTOUT F15 INTERNAL TO ASCII F16 PARITY
CALCULATOR F17 CHARACTER PACKING AND DELETION F18 CHARACTER
UNPACKING F19 ASCII TO INTERNAL F2.phi. NUMERICA CONVERSION F21
COMMON NUMERIC CONVERSION F72 TICKETER SCANNER I/O HANDLER F73
MAGNETIC TAPE SCHEDULER F74 MAGNETIC TAPE HANDLER F.phi.9 MATRIX
GROUP IDENTIFICATION F11 INDIVIDUAL MATRIX IDENTIFICATION F6.phi.
CHT AUDIT F61 SENDER/RECEIVER AUDIT F7.phi. PRIVILEDGED INSTRUCTION
WRITER ______________________________________
d. Timing of system programs and events.
e. Scheduling and handling of input/output device operations.
Central Processor Control
To fulfill its function of controlling the central processor, the
executive schedules the execution of programs within the confines
of an eight level software system. It also provides the ability for
application programs to schedule other programs.
If a program scheduled to be run is core resident, it is simply
started. If the program selected is drum resident, it must be
brought into core memory before it can be run. The area of core
memory available for the execution of drum resident programs is
called the Non-Resident Area (NRA). Because there is only one such
area available, a second drum resident program cannot be processed
until the one currently being executed is completed, and control of
the NRA has been relinquished.
The scheduling philosphy is:
a. Give the most important job in the system to the computer.
b. Once a task is begun, allow it to be completed, (excluding
processing interrupt and trap causes).
c. Once the NRA is loaded, place the drum program residing in it
into the first position in the highest priority queue (.phi.).
The scheduling duties of the executive are primarily handled by the
DPU Scheduler Module (E.phi.1) (see FIGS. 52a-52e). There are five
major functional sections or entry lines associated with the DPU
Scheduler. These entry lines and their applications are as
follows:
a. ACCEPT -- Schedules program modules that require control to be
passed back to the requesting program.
b. RELEAS -- This section is used by programs that have completed
their processing and want to return control to the central
processor so that it can perform other scheduled duties.
c. RESKED -- This section is used if a group of modules are
scheduled consecutively using the same work area at the same
priority. RESKED is also used when a work area overload occurs and
it is necessary to reschedule a work area request.
d. RELOAD -- This section is used by two-part programs, where both
parts are drum resident. It permits the program to be run without
being broken. The first part of a two part NRA program is read off
the drum, placed into NRA, and executed. When this part has been
processed (at priority .phi.), the second half of the program is
scheduled at the same priority, and control of the NRA is retained.
This eliminates the possibility of interleaving the parts of
several non-resident programs of the same priority.
e. TIME -- This section is entered any time a program relinquishes
control of the central processor. TIME scans the eight software
queues and gives control to a program according to the highest
priority. In addition, this entry line is used to schedule drum
resident programs to be read into the NRA. TIME calls the Data
Manipulator Module (F35) to perform a drum to NRA transfer.
Supplementary program modules are used in conjunction with the DPU
Scheduler. These modules perform functions such as linking and
unlinking the programs contained in the priority queues. Other
modules assign work areas from the spare queues and return them to
spare status when they are no longer needed. See FIG. 53.
A work area (WA) is assigned to a requesting program by the Work
Area Assignment Module (F.phi.4). The work area address is then
passed to the DPU Scheduler to be placed into a queue at a specific
numeric priority. If the desired size work area is not available in
the spare WA queue, a maintenance program lights a WORK AREA
OVERFLOW lamp on the maintenance and control console as an
indication of a work area overload. The WA assignment program then
looks for the next larger size WA. If again, none is available,
another overflow lamp lights and this procedure continues until an
available WA is found. If there are none available, control is
passed to the RESKED entry line of E.phi.1, or back to the calling
program. This choice is a programming consideration and is
determined by the calling program.
If a program is to relinquish control of the central processor, it
must pass control to the RELEAS section of the DPU Scheduler.
RELEAS then returns the work area to the appropriate spare work
area queue using the Work Area Return and the Link to Queue
supplementary program modules (F.phi.5 and F.phi.2,
respectively).
If a work area has to be removed from other than the front or the
back of a queue, the Queue Interrogation Module (E.phi.6) is used.
This module (FIG. 54) can locate and/or remove any entry from a
specified queue. Since this module functions as a closed
subroutine, it always returns control to the calling program.
Interrupt Control
Each of the eight hardware interrupt levels is associated with
certain interrupt processors, such as the RS Interrupt Processor
(F51), are part of the executive, while others, such as the
maintenance interrupt processors, are not.
The Interrupt Cause and Analysis Program (ICAP) modules, E21
through E28, act as an interface between the interrupts and the
interrupt processors. The processors schedule the appropriate
program to handle the cause of the interrupt.
The ICAP modules receive and process the eight levels of
interrupts; module E21 receives level 1 interrupts, E22 receives
level 2 interrupts, and so on to E28. FIG. 55 shows a level 1
interrupt (Maintenance Teletypewriter Input Request) being
processed by E21. The E21 module stores the address of the
interrupted program. The Register Stacking Module (F13) saves the
contents of the central processor registers. Its function is to
prevent loss of the data contains within the A and Q registers, the
index registers (X1, X2, and X3), and the four pseudo
registers.
The E21 module obtains the sense group image of the sense lines
that cause a level 1 interrupt. It uses closed subroutine E2.phi.
(Hot Sense Line Finder) to determine the identity of the "hot"
sense line in the group. This sense line identifies the hardware
system causing the interrupt (in this case, the maintenance
TTY).
ICAP module E21 then calls the Maintenance Interrupt Access Program
(MANIAC) to see if the interrupt was caused by a maintenance
routining program. If this is the case, MANIAC instructs ICAP to
ignore the interrupt since it was not valid, and control is
returned to the interrupted program.
Assuming that the interrupt is valid, E21 passes control to the TTY
Use Request Interrupt Processor (F58). F58 determines the identity
of the TTY making the request, schedules the Input Message Analysis
Program (F.phi.6) to initiate the I/O operation (via the ACCEPT
entry line of E.phi.1), and then passes control back to ICAP. The
Register Stacking Module restores the registers to their original
state and returns to the interrupted program. Before exiting to the
requesting program, ICAP resets the interrupt (sense line) that was
just processed.
A variety of interrupt processors and handlers are used by ICAP to
process the different types of hardware interrupts. In addition,
there are various supplimentary modules used to accomplish
interrupt processing. These modules are called as closed
subroutines and must return control to the calling interrupt
processor or handler after performing their required tasks. The
processor then returns control to ICAP which passes control to the
interrupted program at the point of interruption.
The subroutines used by the interrupt processors must be core
resident, as the time required to read them from the drum (8 ms.
average) would be too long. In addition, the non-resident area of
core may be busy at the time of the interrupt, thus preventing the
program from being brought in from drum.
The F32x/3 entry line of the CCR Ready Interrupt Handler Module
(F32B) is used when a ready interrupt is generated by the Computer
Communication Register (CCR) after two words are received from an
Originating Marker (OM). A CCR ready interrupt (level 4) causes the
ICAP module E24 to call F32x/3. FIG. 56 shows a diagram of F32B and
its major subroutines.
The CCR Ready Interrupt Handler:
a. determines if the interrupt came from the A or B unit (CCR A or
CCR B),
b. determines the work area associated with the interrupt
request,
c. determines if the interrupt request was sent successfully,
d. schedules maintenance routines (if necessary) via ACCEPT,
e. determines if the message was received successfully, and
f. determines if the request is for an originating or terminating
marker.
The RRJ Translation Module (F33) is used by F32x.phi.3 during line
or trunk call originations to determine the register junctor
handling the call. F33x.phi.1 is entered to perform the translation
of the data frame sent by the OM to the CCR when a line or trunk
call origination occurs. This module translates the line matrix R
outlet identity (LRO) for line call originations, or trunk register
matrix B outlet identity (TBO) for trunk call originations into the
corresponding register junctor identity (RJI).
The Call History Table Address Calculator Module (F14) is called by
F32x.phi.3 (if the translation by F33 was successful) to calculate
the CHT address from the RRJ identity. F32x.phi.3 calls F.phi.1x01
to access the RRJ slot and will then use ACCEPT to schedule call
processing module C.phi.1x.phi.1 (the first call processing module
to be run).
To complete the interrupt handling procedure and to disconnect the
CCR from the marker, F32B calls the CCR Handler (F32A). The F32A
module returns to F32B when completed and control is then returned
to ICAP (E24). ICAP restores the registers and returns control to
the interrupted program.
Trap Control
The Executive Program handles only level 2 traps, as shown in FIG.
57. The Trap Two Cause Analysis Module (E1.phi.) is the computer's
internal error processing program. A level 2 trap is caused by any
one of the errors listed under the heading Traps, paragraph on
level 2. Recognition of this trap is immediate and the instruction
in process is aborted.
The Trap Two Cause Analysis Module (E1.phi.) passes control for
nearly all trap two causes to the System Clear and Start (L16)
maintenance program. For instruction even parity errors (IEPE) and
data even parity errors (DEPE), E1.phi. will call the Parity
Recovery Program (S3.phi.), a maintenance program) to determine if
the trap was caused by a transient error. If so, the system will
return to normal processing. If the parity error was definitely
caused by a fault, the System Clear and Start Program will be
called to reinitialize the system. This program is run when any
unrecoverable system errors occur.
When System Clear and Start is called, it clears out all sybsystems
and places them in an idle state, and clears out all interrupts
stored by the central processors. To return the system to normal
processing again, the L16 module reinitializes core main memory
(CMM), enables the interrupt system, and restores the subsystems to
an operational condition.
Timing Control
The information contained in paragraphs below describes the timing
control functions of the executive modules. These modules allow the
application and maintenance programs to time certain functions,
schedule other programs at various time intervals, and be executed
themselves at specified time intervals.
Timing control provides the capability of timing various events
that are requested to be run at specific times. An example of this
is the scheduling of the Non-Resident Area Audit Program (L39),
which is run every minute to verify that a program is not
improperly occupying the non-resident area of core main memory. The
timing control modules provide interval timing and the initiation
of requested actions when the intervals elapse.
The Interval Timer Request Acceptor Module (E02) accepts timing
requests by placing them into a general timer queue. Of the time
interval requests in the general timer queue, the first interval in
the queue is the one being timed at that particular moment. There
is a 40 year software clock in the main memory that provides
current time. This clock is initiated at cutover and provides
current time which is used as a basis for placing interval timer
requests into the general timer queue.
Timing control maintains a software clock called the real time
clock. The real time clock (RTC) is used by application and
maintenance programs to provide the time of day in hours, minutes,
and seconds. It also provides the year, month, day of the month,
and day of the week. The Real Time Clock Program Module (E/5)
maintains the five counters that comprise the RTC, which is in a
binary coded decimal (BCD) format. E05 updates the RTC and resets
its counters at the appropriate times (FIG. 58).
A level 3 interrupt is received by ICAP module E23 every 16.67 ms.
which causes E23 to call the Interval Timer Interrupt Processor
Module (E/4). See FIG. 59. This action provides a standard time
interval that is used to produce other intervals required by
various timing programs. These intervals are all multiples of 16.67
ms. The following are some of the programs initiated by E/4:
a. The Diagnostic Control (DIACON) Maintenance Program Timer Module
(L22X.phi.7) every 16.67 ms.
b. The Real Time Clock Program (E.phi.5) every second (60 - 16.67
ms. intervals).
c. The Minutes Timer Program (E/9) every minute (3620 - 16.67 ms.
intervals).
d. The Non-Resident Area Audit Program (L39) every minute (3620 -
16.67 ms. intervals).
e. The I/O Time-Out Audit Program (L52) every 167 ms. (10 - 16.67
ms. (10 - 16.67 ms. intervals).
f. The Interval Timer Handler Program (E.phi.3) which is called by
E.phi.4 at the expiration of a requested time interval (a variable
number of 16.67 ms. intervals).
g. The Ticketing Hardware Validation Program (W.phi.1) every 2.4
seconds (144 - 16.67 ms. intervals).
In FIG. 59, which shows the primary timing modules, the Interval
Timer Interrupt Processor (E.phi.4) is shown as the heart of the
timing functions. After the required number of 16.67 ms. intervals
have elapsed, E.phi.4 calls the appropriate program. When E.phi.4
has completed its functions, it returns control to E23.
E.phi.4 calls the Real Time Clock Program after every one second
interval has elapsed in order to update the system real time clock.
This update is performed to provide the application programs with
an accurate indication of the time.
As shown in FIG. 58, the Real Time Clock Module calls the Timed
Routine Scheduler (TRS) maintenance program (L18) every hour. One
of the modules that the TRS controls is the Hourly Printout Routine
(F23). This module permits the time of day and the date to be
outputted on both the maintenance and office administration
teletypewriters.
The Interval Timer Request Acceptor (E.phi.2) is used to place
timing requests from application programs into the general timer
queue. If a program is to be run at a specified time, it calls
E.phi.2. This module places the shortest interval requests at the
front of the timer queue so that they may be processed first (FIG.
60). If a request is to be placed on the front or rear of the
queue, the Link to Queue Module (F.phi.2) is used. For any timing
requests that are to be placed somewhere between the first and last
entries, E.phi.2 will not require F.phi.2.
If entry line E.phi.2X.phi.1 is entered, the exit will be back to
the caller. If entry line E.phi.2X.phi.3 was used, the exit will be
to the executive's TIME routine. E.phi.1X.phi.4 will then scan the
CPU queues for the next task.
The interval Timer Handler's E.phi.3X.phi.1 entry line is entered
from E.phi.4 at the expiration of the general interval timer (FIG.
61). The general interval timer is a counter that can be set to any
requested time. For example, if a program is to be run in two
minutes, the request is placed on the timer queue and when the two
minute interval has expired, E.phi.4 will call E.phi.3X.phi.1 to
handle the request. E.phi.3X.phi.1 will use F.phi.3X.phi.1 to
remove the entry from the timer queue. This entry indicates to set
a specified flag in memory, to transfer control direct to a
specified entry line, or to schedule a program by using the ACCEPT
entry line of E.phi.1. After the requested action has been taken,
F.phi.5X.phi.1 is called to return the work area to the spare
queue. E.phi.3X.phi.1 will then calculate the next interval to be
timed. It will also set the timer to idle if no intervals are to be
timed.
The E.phi.3X.phi.2 entry line is called from a program that wants
to remove a request for a time interval before that interval has
expired. E.phi.3X.phi.2 uses routine E.phi.6X.phi.3 to locate the
entry to be removed from the timer queue. E.phi.6X.phi.5 is used to
perform the entry removal before timer expiration. The Queue
Interrogation Module (E.phi.6) is shown in FIG. 54.
Both E.phi.3X.phi.1 and E.phi.3X.phi.2 are called as closed
subroutines. E.phi.4 receives control again after routine
E.phi.3X.phi.1 has completed, and control is returned to the caller
of routine E.phi.3X.phi.2 after the requested entry has been
removed from the timer queue. The work area used for a timing
request regardless of whether action was taken or the interval was
aborted, will be returned to the spare queues by F.phi.5X.phi.1
(FIG. 53).
A timing function used to provide an interlock when accessing
register-sender memory is accomplished by modules F.phi.8 and
F.phi.1 (see FIGS. 62 and 63). F.phi.8 (the Register-Sender Access
Module) and F.phi.1 (the Register-Sender Timing Interlock Module)
are used to provide access to RS memory so that accidental
alteration of the memory data cannot occur.
The F.phi.8 module is called by the call processing programs via
entry line F.phi.8X.phi.1 to permit writing into RS memory. It uses
F.phi.1X.phi.1 to provide an interlock between the DPU and the RS
memory. Any data in a register junctor (RRJ) memory slot is
protected against alteration by the DPU as a function of the
F.phi.1X.phi.1 entry line.
When an RRJ slot is to be accessed by the CPU, F.phi.1X.phi.1
determines the amount of time remaining before the RS will scan the
slot. From the input parameters received from the calling program,
it knows the number of time slots required to modify the data
within a particular RRJ (approximately 50 microseconds per slot).
If enough time remains before the RS scan reaches the RRJ, control
will be returned to F.phi.8 to permit the DPU to access the slot.
The interrupts to the computer central processor (CCP) are disabled
upon return to F.phi.8 to insure that F.phi.8 has the full time
interval for its update.
If insufficient time is available to update, control is retained by
F.phi.1 until the scan has passed the slot. At this time, the
F.phi.1 Time Interlock Module will try again. Retries will continue
until an interlock is obtained (600 tries are maximum).
The F.phi.8 .phi.2 entry line (FIG. 62 is used by maintenance
programs for read and write requests. There are three functions
performed by this routine. The first is to write from the work area
into the RS memory, the second is to write from RS memory into the
work area, and the third is a read/modify/write RS memory
operation. This entry line also used F.phi.1 to prevent
interference with the RS scan of the RRJ's. The exits of F.phi.8
are either back to the caller or to the Call Condition Analysis
Program (C29).
As shown in FIG. 63, the exit points for F.phi.1X.phi.1 are either
back to the caller for normal operations, or to the caller's error
return in the case of an RS fault or RRJ trouble. The exit point
for all programs calling F.phi.1X.phi.2 is back to the caller.
The watch dog timer (WDT) prevents software looping. If a program
has control of the central processor for over 882 ms., the watch
dog timer times out and a system clear and start is initiated by
the Computer Third Party Circuit (CTP).
The TIME entry line of the DPU Scheduler (E.phi.1X.phi.4) permits
scanning of the eight queues (0-7) associated with the central
processor unit (CPU queues). If there are no entries in the queues,
a watch dog time-out will occur (unless the WDT is reset). A
time-out is not desirable at this time since there is no software
looping involved. To prevent the time-out, E.phi.1X.phi.4 schedules
a maintenance module called the Watch Dog Timer Manipulator
(L4.phi.). The main function of this module is to reset the
WDT.
If TIME scans the eight CPU queues and finds no work areas attached
to any of the levels, it obtains a work area to schedule
L4.phi.X.phi.1 (see FIG. 64). The work area is obtained by
F.phi.4X.phi.1 and F.phi.3X.phi.1. The ACCEPT entry line
(E.phi.1X.phi.1) places the work area containing the necessary
parameters required by L4.phi. on the front of the priority 4
queue.
ACCEPT returns control to TIME which will then rescan the queues.
The work area for L4.phi. is removed from the queue by
F.phi.3X.phi.1, and L4.phi.X.phi.1 is then initiated. When
processing of L4.phi. is complete, control will pass to RELEAS
(E.phi.1X.phi.3). RELEAS returns the work area used by L4.phi. to
the proper spare queue and passes control to TIME to rescan the
eight CPU queues. If there are still no tasks in the queues.
L4.phi.X.phi.1 is rescheduled and the manipulation of the watch dog
timer is repeated.
Input/Output Device Control
The executive has control over the operation of the following I/O
devices:
a. High speed paper tape punch and reader.
b. Teletypewriters (maintenance and office adminstrative).
c. Low speed paper tape punch and reader.
d. Marker communication registers (located within the originating
and terminating markers).
e. Magnetic drums.
f. Ticketing magnetic tape unit.
g. Ticketing scanner unit.
The executive schedules the use of the I/O devices so that they may
be utilized with maximum efficiency. The executive performs all
actions required to operate the various I/O devices. This releases
the application and maintenance programs from having to perform
these functions.
If a request is made for an I/O operation, the operation is
initiated immediately if the requested device is idle and a path to
it is free. If the device or the path are not idle, the I/O
requests are placed in the appropriate queue. The major queues used
by the I/O programs are shown in Table EX2.
When a device becomes idle, its associated queue (or queues) is
scanned in a present pattern. All tasks of the highest priority
(first queue scanned), associated with the specified device, are
processed before the next lower priority queue is scanned. Table
EX2 defines the queues associated with each device, the order in
which the queues are scanned, and the maximum length each queue may
attain. Maximum queue length is equal to the number of work areas
large enough to accomodate an I/O request for a specified
device.
A normal request is one that does not require special attention or
a particularly rapid response (most call processing I/O requests
are normal requests). The high priority requests must be executed
in a relatively short period of time as normal processing may
depend upon these requests (e.g., maintenance requests used to
isolate and diagnose malfunctions in the I/O devices).
The drum memory I/O operations are accomplished in much the same
manner as operations for other I/O devices. The drum memory
contains data needed by the system, and the programs used to access
this data are the I/O schedulers, I/O handlers, and their
associated subroutines.
The programs that access the drum are shown in FIG. 65 as users of
the Data Manipulator Module (F35X.phi.1). This module is used by
resident and non-resident programs and provides centralized control
of all drum accesses. F35X.phi.1 obtains the required parameters
needed for drum access and functions as a drum directory by
locating the proper drum, drum segment, and start address required
by the requesting program. The work area specified in index
register one is used to process the request.
When a drum access request is received, F35X.phi.1 goes to its
control tables in the core memory to obtain the parameter data
needed to accomplish the access. This is unusual because most
modules have the parameter data passed to them. The collected
parameters are passed to the Drum Scheduler Module (F29) for
scheduling the drum access operation.
The Drum Scheduler (F29X.phi.1) then schedules a drum read or write
operation from the parameters it has received. It places the
requester's work area into a queue associated with the desired drum
control unit (DCU) pair. The work area is placed on the queue by
the Link to Queue Routine (F/2X.phi.1) according to its assigned
priority. Since there can be a maximum configuration of six DCU's,
a maximum of three queues are used (one for each DCU pair). Each of
these queues has three priority levels, as shown in Table EX2.
The F29 module exits to TIME when it cannot branch to the Drum
Handler. At this time, an exit can also be made back to the
requester; however, this action must have been previously specified
in the requester's work area. If a software error occurs during
F29X.phi.1 (e.g., the request number of the drum is invalid or the
work area is too small for the I/O request), F29 will use ACCEPT
(E.phi.1X.phi.1) to schedule an error return to the requester.
The Drum Handler MODULE (F3.phi.) performs the drum access. The
Drum Scheduler calls F3.phi.X.phi.1 when it determines that the
drum and DCU are not busy and that the request from F35 is valid.
The Drum Handler uses the Drum Handler Subroutine Module (F4.phi.)
to interrogate the request's work area data in order to obtain the
required indications. F3.phi. and the subroutines it calls are used
to:
a. Remove the tasks from the appropriate queue.
b. Check request validity.
c. Initiate the DCU initialization.
d. Notify the requester if the request cannot be handled.
e. Disconnect the DCU after a request has been serviced.
Note: drum maintenance programs may also enter entry line
F3.phi.X.phi.1.
The exit to TIME from F3.phi.X.phi.1 occurs when the DCU's are
busy. TIME will then scan the queues for another task that the
central processor can perform until the drum access
TABLE EX.2
__________________________________________________________________________
Queue Structure of I/O Devices CONTROLLER I/O ORDER OF MAXIMUM (CBD
OR DCU) DEVICE ASSOCIATED QUEUES QUEUE SCAN QUEUE LENGTH
__________________________________________________________________________
Channel Maintenance Input (Keyboard) 1 1 Device TTY High Priority
Output 2 N Buffer .phi. Normal Output 3 N HSPT Punch Output 4 N
Input Keyboard or LSPT 1 2 Channel Office (Reader) Device
Administrative High Priority Output Buffer TTY (Printer) 2 N 1
Normal Output (Printer or LSPT Punch) 3 N HSPT Reader Input 4 N
High Priority (For Maintenance) 1 N (One Queue/DCU Pair) Drum
Magnetic Block Transfer Control Drums (Program Read) Units (One
Queue/DCU Pair) 2 N ,Normal (One Queue/DCU Pair) 3 N Computer
Marker Communication Communication Communication Register (CCR
Maintenance) 1 N Registers Registers High Priority Marker (One
Queue for all Markers 2 N Terminating Marker Normal (One Queue/TM
Pair) 3 N Ticketing Magnetic Maintenance 1 N Device Tape Unit A
Normal 2 N Buffer A Ticketing Magnetic Maintenance 1 N Device Tape
Unit B Normal 2 N Buffer B
__________________________________________________________________________
is retried. The Drum Handler normally returns to F29X.phi.1 which
will check a bit in the requester's work area to determine whether
to pass control back to the calling program, or to exit to TIME.
The TIME exit is the most common.
The ACCEPT entry line of E.phi.1 is entered from I3.phi.X.phi.1 to
schedule the following routines:
a. The requester's error return if a request cannot be
serviced.
b. The next requested task when a DCU task has been successfully
completed.
c. DCU maintenance when a DCU error occurs.
Ticketing write requests get special treatment by being attached to
the front of the second drum queue by F.phi.2X.phi.2. The Drum
Handler also uses F.phi.2X.phi.2 to link the non-resident programs
that have not completed processing to the front of a zero priority
CPU queue, thereby permitting these programs to be run first, and
freeing the non-resident area of core as quickly as possible.
The F.phi.3X.phi.1 subroutine is used to remove the indicated
requests from the appropriate queue. DROP (F.phi.5X.phi.1) is used
by F3.phi. to release a work area when a task is completed after an
I/O operation.
The CCR/Marker I/O operations are accomplished by the CCR Scheduler
(F31) and the CCR Handler (F32A) programs and their associated
subroutines (FIG. 66). Various call processing and maintenance
programs are the users of these modules.
The CCR Scheduler's F31X.phi.1 entry line accepts all requests for
data transfers between the markers and the DPU via the CCR.
F31X.phi.1 provides its users (calling programs) with the means of
instructing the CCR to perform an input or output operation.
Entry line F31X.phi.1 takes the parameters in the requester's work
area, determines if they are valid, and if they are, places the
request into a CCR queue. The three types of queues used by the CCR
Scheduler are listed in Table EX2. The work area size is also
checked to see if it is large enough to accommodate the request. If
the parameters are not valid or if the work area is not proper, the
appropriate error routine is scheduled by F38. The CCR Scheduler
exits to F32X.phi.1 when F31 finds that the appropriate marker
(pair) and the CCR are in the idle state.
If an error occurs during the running of F31X.phi.1 (e.g., the work
area obtained was not large enough for the task, a marker was
checked in preparation for a data transfer and was found to be
unequipped, etc.) F38X.phi.3 will schedule an error program. The
LINK entry line (F.phi.2X.phi.1) is used to place entries on the
back of the CCR I/O queue.
Entry line F31X.phi.2 is used to schedule CCR status dumps. A
status dump includes such information as the scanner address,
status of the CCR (idle scanning, sending, or receiving), if the
message was sent or received successfully between the CCR and the
marker, etc. The status is stored in the user's work area by
F36X.phi.6. Control will be returned to the caller of F31X.phi.2 if
requested. If no return was specified, F38X.phi.1 will act as an
interface between F31X.phi.2 and E.phi.1X.phi.1 to schedule the
next program. An exit from
The CCR Handler (F32A) uses two entry lines F32X.phi.1 and
F32X.phi.5. F32X.phi.1 is used to perform operations necessary to
prepare the markers and CCR for operation. It will initiate data
transfers between the CPU and the CCR, and between the CCR and the
markers. Entry line F32X.phi.5 is entered from the CCR Error
Isolation and Recovery Module (F37) to retransmit the data
transmission after an error has occurred.
The tasks placed in the CCR I/O queue by F31 are removed (via
F.phi.3X.phi.1) so that they may be handled by F32A. F32X.phi.1
prepares the CCR and the appropriate marker pair for operation, and
controls the data frame transmission by the CCR. The data frames
consist of two 26-bit words for the originating markers (OM) or
four 26-bit words for the terminating markers (TM). Data frame
transmission to the OM is only performed for maintenance
purposes.
If the requested marker is not available, F32X.phi.1 notifies the
calling program. This is known as the requester's error return.
Other subroutines used with F32X.phi.1 are F.phi.2X.phi.3 (LINK),
which is used to add an unfinished non-resident task to the front
of a CPU priority queue; F.phi.3X.phi.1 (UNLINK), which is used to
remove entries from the CCR queues; and F.phi.1X.phi.1 (RS TIME),
which is used for TM requests in order to perform an interlock with
the register-sender.
The CCR Subroutines 1 Module (F36) handles common tasks required by
the CCR I/O programs. F36 may be used to set up maintenance
requests, unload the CCR data and status words, reconfigure the
CCR, etc.
The CCR Subroutines 2 Module (F38) is also used for common CCR
tasks. This module contains routines that provide an interface
between the CCR Handler and the DPU Scheduler for scheduling of the
next program to be run or of an error program. In addition, F38 can
place a CCR maintenance-out-of-service (MOS) and schedule an
isolation program, abort a task, etc.
The TTY and paper tape I/O devices are scheduled and controlled by
the I/O Scheduler (F26) and the I/O Handler (F27) modules,
respectively, and their associated subroutines (FIG. 20). The I/O
Scheduler accepts requests for and schedules the use of the
following I/O devices:
a. Local maintenance teletypewriter (LMT)
b. Local office administrative teletypewriter (LOAT)
c. Low-speed paper tape reader (LSPTR)
d. Low-speed paper tape punch (LSPTP)
e. High-speed paper tape reader (HSPTR)
f. High-speed paper tape punch (HSPTP)
Entry line F26X.phi.1 is used to transfer I/O data via one of the
peripheral devices listed above. F26X.phi.1 checks the parameters
located in the requesters work area. The work area parameters
include the work area size, name and priority of the requester's
program, the next program to schedule in case of errors, etc. If
errors are encountered, ACCEPT (E.phi.1X.phi.1) is called to
schedule an error routine and will either pass control to
E.phi.1X.phi.4 to permit scanning the queues for a new task, or
will return to the calling program.
From the work area parameters, the I/O Scheduler determines the I/O
device to be used and then checks to see if the device and its
associated controller is available. (The controllers used with the
TTY's and the paper tape devices are the channel device buffers --
CDB's). F26X.phi.1 will check a table located in the core memory to
determine if the requested device and its associated controller are
available. If a device is not available, the I/O Scheduler can
assign the request to an alternate device. If a request cannot be
serviced because of hardware unavailability, the caller is notified
via an error return.
The I/O Scheduler places each I/O device request into its
appropriate queue by using the Link to Queue Module
(F.phi.2X.phi.1). The I/O Scheduler exits to the I/O Handler (F27)
when the I/O device is idle, the path to it is free via the channel
device buffer, and the request is determined to be valid.
The I/O Handler Program (F27) performs all operations necessary to
prepare each device for operation and affects the data transfer
between the CPU and and selected device. Data manipulations, code
conversions, parity checking requirements, etc., are provided by
the various subroutines used by F27.
Upon entry, F27X.phi.1 unlinks the work area from the I/O queue via
F.phi.3X.phi.1 and then stores the work area address into a table
in the core memory. It also checks the availability of the
peripheral adapter (PA) and channel device buffer (CDB), determines
if the I/O request is an input or an output, and determines which
device is to be used (LMT, HSPTR, etc.). The Interval Timer Request
Acceptor (E.phi.2X.phi.1) is called when a TTY input request is
initiated. This routine allows 120 seconds maximum to input the
message.
The CCS Recovery Module (S31) is used by F27X.phi.1 to check for
any channel multiplex errors and to reset a CCX error counter.
Another subroutine shown in FIG. 67 which is used by F27 is the
Stop Time (E/3X.phi.2). This entry line is used when the I/O
Handler wants to remove a task from a timer queue before the
requested interval has expired. The entries are located and removed
from the queue by the Queue Interrogation Module (E/6).
The Input Message Analysis Module (F/6) is primarily used to
prepare the I/O system to receive a TTY input message, F/6 is
accessed once for each TTY input, and at least once for each paper
tape that is read. All TTY inputs are in ASCII code. ASCII code is
converted to the computer's internal code and vice-versa by the F19
and F15 modules, respectively.
A TTY message consists of the ACTION CODE (the first four
characters containing the identity of the program designated to
receive the input data), and the inputted data. Each character in
ASCII code will be converted to six binary bits by F19. The message
length cannot exceed 72 characters, and the time required to input
cannot exceed two minutes. Violations of either limit will cause
the input message to be aborted and an error output message to be
printed on the TTY.
The Paper Tape Control Module (F28) enables the paper tape to be
read by the computer via a paper tape reader. It receives control
when a maintenance man at a TTY types in the required ACTION CODE,
or when an application program wants to read tape. The maintenance
man placing the paper tape on the reader and typing in the proper
ACTION CODE initiates the reading of the paper tape data into the
system.
The data read into the DPU is placed into a 100 word work area.
Input from either of the paper tape readers is limited to 70 words
per request.
The inputted tape may be completely in ASCII code or it may only
contain an ASCII code leader followed by binary data (core
image).
Note: the first example is known as "ASCII paper tape" and the
second is called "binary paper tape."
An application program or a maintenance program wishing to initiate
a paper tape message output calls F26X.phi.1. The I/O Scheduler
places the output request on the HSPTP queue (Table EX2). When the
hardware necessary to service the request is available, the I/O
Handler turns-on the device motor, allows the motor to reach
operating speed, and initiates the paper tape output. Each paper
tape punch output (high or low speed) is limited to 512 characters.
Character packing, code conversion, parity checking, and other
miscellaneous functions are performed by subroutine modules used by
F27.
The magnetic tape transport (MTT) operations are scheduled by the
Magnetic Tape Scheduler Module (F73). The magnetic tape transports
(the MTT is duplexed) are controlled and operated by the Magnetic
Tape Handler Module (F74). See FIG. 68 for a magnetic tape software
diagram.
The F73 scheduler module places the MTT access requests into an MTT
queue according to priority via the Link to Queue Module, (F.phi.2)
and the ACCEPT (E.phi.1X.phi.1) entry line of the DPU Scheduler.
When F74 is entered at F74X.phi.1, these requests are removed from
the queue and are processed by the Ticketing Magnetic Tape Unit
(TMU). The MTT, its associated peripheral adapter, and the
necessary read/write electronics comprise the TMU. This is a dual
channel configuration used for ticketing purposes.
The Ticketing Output Format Module (T.phi.4) calls the Magnetic
Tape Scheduler via F73X.phi.1 when the core resident Call Record
Buffer Table is filled (when it contains a maximum of 15 call
records). The Magnetic Tape Scheduler accepts the magnetic tape
output request and schedules a call record data block which is
formatted and transferred to tape by the Magnetic Tape Handler. If
errors are encountered, ACCEPT is called to schedule an error
routine and control is either passed to TIME or returned to the
requester of F73.
Entry line F73X.phi.2 is called by the Magnetic Tape Label Routine
(F75) in order to write a header label on tape. F73X.phi.3 is used
to place a particular channel (A or B) of the ticketing subsystem
on-line o off-line.
The F74X.phi.1 entry line of the Magnetic Tape Handler is the
normal entry from the Magnetic Tape Scheduler. This program removes
the requests from the MTT queue and initiates the tape output.
The F74A.phi.1 subroutine is used by F74 to output four data words
on magnetic tape. F74T.phi.1 is a subroutine used by F74 as a 32
millisecond timer. DIACON and CONFIG are used by the Magnetic Tape
Handler to schedule maintenance programs and to reconfigure the
ticketing system hardware, respectively. DIACON schedules ticketing
device buffer (TDB) localization routines and CONFIG is used to
place the appropriate TDB maintenance-out-of-service (MOS).
The Ticketing Scanner Unit (ITSU) Handler Program (F72) permits the
ticketing operations to be accomplished (FIG. 69). The Ticketing
Scan Interrupt Module (T.phi.3), at 600 ms. intervals, calls F72 to
enable the TSU to successfully interrogate all incoming trunks and
OJ's. The busy/idle condition of local lines and trunks as well as
the duration holding time of the trunk circuits is passed by F72 to
the calling programs for analysis.
The requests for ticketing scanner unit operation from the TSU
Handler's calling programs do not have to be scheduled by a
scheduler program because of the high speed of TSU operations which
permits a TSU to be effectively accessed on a continuous basis. F72
functions as an I/O program for ticketing and maintenance programs,
enabling them to store information within the ticketing device
buffer (TDB) and to interrogate and control the TSU.
Entry line F72X.phi.1 is always entered as a closed subroutine. In
the event of a TSU fault condition, F72 schedules a fault
localization routine (via DIACON) to attempt to rectify the
condition. CONFIG is used to reconfigure a TDB/TSU channel to its
alternate TDB/TSU channel.
The TSU Handler uses module L26 to count TSU errors in a given
length of time. Thus, the error rate can be used to indicate a
faulty TSU.
Simplified operation of the executive during a local-to-local
call
the simplified block diagram shown in FIG. 70 illustrates a
local-to-local call including the executive and call processing
program modules that are involved. Some of the basic modules that
are required for this operation, such as the LINK or UNLINK from
queue modules, are not shown.
The following definitions apply to FIG. 70:
Cfsv -- call For Service Voltage
Cht -- call History Table
Cos -- class of Service
Ccr -- computer Communication Register
Icap -- interrupt Cause Analysis Program
Om -- originating Marker
Dpu -- data Processor Unit
Rj -- register Junctor
Rs -- register-Sender
Rft -- request For Translation
Tm -- terminating Marker
When the originating marker (OM) senses a call for service voltage
(CFSV) caused by the customer going off-hook, the OM sends a two
word data frame to the computer communication register (CCR). This
data frame contains the originating junctor identity, the
customer's equipment identity, and the line matrix outlet identity.
An interrupt is sent to the data processor unit (DPU) by the CCR
which causes ICAP to pass control to the CCR Ready Interrupt
Handler (F32). F32 analyzes and processes the data and then
requests F33 to perform a register junctor (RJ) translation.
The F33 module translates the R-matrix outlet identity into a
register junctor identity. The data frame is then stored in the
call history table (CHT) in main memory (addressed by the register
junctor time slot). The register-sender memory is updated to record
the call origination in order for the register-sender (RS) to take
over control of the originating path and allow the originating
marker to drop control.
After the register junctor translation has been performed, F32
schedules a class-of-service (COS) translation to be performed by
call processing module C/1. This translation consists of retrieving
from drum, via Data Manipulator Module F35, the unique
characteristics of the customer, which are recorded with his line
equipment number identity. F35 schedules C/2 via the DPU Scheduler.
C/2 then analyzes the COS information (e.g., billing information,
type of receiver required, total number of digits required before
requesting a translation, etc.). Part of the COS data is placed in
the Call History Table in main memory and part is stored in
register-sender memory. The data placed in register-sender memory
is used to control the receipt and analysis of the dialed digits
and to supervise the network via the register junctor.
The register-sender returns dial tone to the calling line and
prepares to receive digits. The RS collects the first three digits
and then program control is passed from the Call Processing Program
to the Executive Program by a request-for-translation (RFT) from
the RS. The RFT signal causes control to be transferred to F51, the
Register-Sender Interrupt Processor. When F51 is completed, control
is passed back to the Call Processing Program (module C.phi.6) for
the three digit translation analysis. This is done to determine the
type of call being analyzed, and is accomplished by accessing the
three digit translation table on the drum.
As a result of the three digit analysis, call processing module
C.phi.8 is scheduled and seven digits are accumulated in
register-sender memory before another translation is requested.
After collecting seven digits, the register-sender again generates
a request-for-translation (RFT). The Register-Sender Interrupt
Processor Module (F51) initiates a read-out from register-sender
memory, stores the read-out in computer main memory, and then
schedules Call Processing Program C.phi.6 to perform the seven
digit translation.
Since this is a final translation, the Call Processing Program
requests a directory number translation. This initiates a request
to the F35 module for a drum look-up of the local directory number
table which provides the line equipment number of the called line,
the proper ringing code, and any special called line features.
The Call Processing Program analyzes the data retrieved from the
drum and obtains the originating line matrix identity, which
defines the selector matrix inlet. The data needed to instruct the
terminating marker to establish a path from the selector matrix
inlet to the called local line, together with other control data,
is loaded into four 26-bit words to be sent serially by the
computer communication register to an idle terminating marker. This
data transfer is scheduled by the CCR Scheduler (F31) and processed
by the CCR Handler (F32A).
The terminating marker sets up the terminating condition and upon
successful completion, communicates this result to the CCR. The CCR
sends a ready interrupt to the central processor which is processed
by E24 and the CCR Ready Interrupt Handler (F32B). The RS, upon
instruction that the termination operation was successful, performs
its terminating phase functions. Call processing module C26 returns
the call history address to idle, and a cut-through and register
junctor disconnect is initiated. Program control is then returned
to the Executive Program for scheduling of the next task in the
system via TIME (E.phi.1X.phi.4).
CALL PROCESSING PROGRAM MODULES
C.phi.1 -- fig. 71
1. name -- class Of Service (COS) Initialization module.
2. PURPOSE -- The COS Initialization module C.phi.1 initiates the
appropriate COS drum translation for the originating line or
trunk.
3. FUNCTIONS -- Module C.phi.1 performs the following
functions:
a. Requests WASPAR module (F04) to obtain a Work Area (WA). If a WA
is not available, F.phi.4 will reschedule module C.phi.1. This
process continues until a WA is obtained.
b. Zeroes out Register Sender (RS) memory image words in the WA;
included are words FWBX1A, FWBX2A, FWBX4A, FWBX5A, FWBX6A, and
FWBX6B.
c. Initializes the zero items CHQTKR, CHQOJT, AND CHQPG1 of the
Call History Table (CHT).
d. Stores the following information in the WA:
Fwacht = cht address.
Fwarj1 = register Juctor (RJ) identity plus RS section number.
e. Stores the following information in the CHT:
Chawaa = wa address.
Chqwal = 1, indicates that a WA is linked to the CHT.
f. Checks a maintenance indicator to see if a call should be placed
on a timer queue for 100 milliseconds. Entry point C.phi.1X.phi.2
is scheduled if maintenance does not clear down the RJ.
b. Requests MANIP module (F35) to perform a COS drum translation
for the originating line (CLN) or trunk (CTN) and, if successful,
schedules the Originating COS Analysis module (C.phi.2). I
unsuccessful, schedules the Local Call Processing Maintenance
Program (LCPMP) module (C31).
4. inputs
4.1 software
4.1.1 core Tables
Cha -- scheduling Information.
Chc -- originating Marker Data Frame Received.
4.1.2 Drum Tables
None.
4.1.3 Registers
None
4.2 HARDWARE
None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables
None.
5.1.3 Registers
None.
5.2 HARDWARE
None.
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points C.phi.1X.phi.1
Scheduled by the Communications Control Register (CCR) Handler
module (F32) upon recognition of an Originating Marker (OM)
origination. Module C.phi.1 also reschedules itself when no WA is
available. C.phi.1X.phi.2 Scheduled as a special entry line and is
not part of normal C.phi.1 processing. C.phi.1X.phi.2 is scheduled
from within C.phi.1 itself as part of the solution to the constant
call for service problem, e.g. a line which appears as a constant
origination to the OM, and the OM is unable to pull a path due to a
malfunction. 6.2 EXIT POINTS Exit Reasons for Exit Points
E.phi.2X.phi.3 Interval Timer Request Program: Used to cause
requests for timing of specified time intervals to be added to the
Executive's timer queue. F35X.phi.1 Data Manipulator (MANIP)
Program: Used by resident and non-resident programs to access drum
memory. After MANIP is entered the user loses control of his WA. To
regain control, the user must request another WA. 7. SUBROUTINES
USED Entry Functional Names Points F.phi.4X.phi.1 WASPAR -- Work
Area Assignment.
8. NARRATIVE
8.1 discussion
when a subscriber originates a call, i.e., goes off-hook, it is
necessary to perform a drum translation in order to retrieve the
subscriber's Originating COS data. Module C.phi.1 begins the
originating process of determining if the originator is a local
subscriber or an incoming trunk circuit. After the identification
of the origination, module C.phi.1 initiates the appropriate COS
translation.
8.2 TECHNIQUE
Upon entry, module C.phi.1 has the call-associated call history
table CHT. To be consistent with the call processing entry
philosophy module C.phi.1 uses the CHT as a WA until a WA is
obtained. To accomplish this task, a CHT offset address is created
to index the CHT by its address, relative to the first WA address.
This procedure allows overlays, normally associated with the WA, to
be used in modifying the CHT.
The CHT offset address may be symbolically represented as
'.vertline.a - b .vertline. + c' where:
a = The original start location of the table of WA's.
b = The start location of the table of CHT's.
c = The relative depth of the RJ into the CHT.
*notes to fig. 71
1. scheduled by ccr handler (f32) upon recognition of an
origination. cht offset addr in xr1 cht offset addr=diff. between
cht addr and first wa addr.
2. obtain 26 word call processing work area.
3. manip (f35) initiates retrieval of cos drum info and places it
in cja and schedules c.phi.2x.phi.1. for error, f35 will schedule
c31x.phi.1.
4. place call on timer queue and schedule c.phi.1x.phi.2 after 100
msec. ccr handler indicates that call should be put on timer queue
when it expects om maintenance to clear down the call (remove from
queue and idle the rj). if maintenance does not clear down call the
c.phi.1x.phi.2 is entered and call processing continues
normally.
c.phi.2 -- figs. 72-72c
1. name
originating Class of Service Module.
2. PURPOSE
The Originating Class of Service (COS) module (C.phi.2) retrieves
and analyzes each originator's common COS information. As a
function of this analysis, module C.phi.2 routes the data to the
appropriate Call Processing module. Module C.phi.2 also obtains
Multifrequency (MF) or Touch Call Multifrequency (TCMF) receivers
for any call requiring receivers.
3. FUNCTIONS
Module C.phi.2 performs the following functions:
a. Zeroes out the CHQPDL data from the previous call.
b. Sets the Time Frame (CHQTMF) to 1.
c. Calls the Event Metering program module (M.phi.5) to update
successful Register Junctor (RJ) count.
d. Calls the Call Condition Analysis program module (C29) to check
if a call abandon, timeout, or translation request interrupt has
occurred. If an interrupt has occurred, module C29 will process the
call according to the trouble condition. If no interrupt occurred,
module C29 will return to module C.phi.2.
e. Obtains common COS data (ZTO, PRF, ZOC, and XTL) from core table
CCE. This data is placed in the work area FWB) in order to be
written into Register Sender (RS) Memory.
f. Sets up the Call History Table (CHT) to run the Pretranslator
Initialization program module (C.phi.4), on an expected interrupt
of 11 (TIE = 11), for the Trunk Test Access Circuit/Communications
Line (TTA/CL).
g. Sets up the CHT to run Local Pretranslator program module
(C.phi.7) on an expected interrupt of 1 (TIE = 1), for local
originations (CCELOR = 1).
h. Sets up the CHT to run module C.phi.4 on an expected interrupt
of 1 (TIE = 1), for non-local originations (CCELOR = 0).
i. Obtains the receiving control data (DST, XCB, PTT, PTR, SDS, and
MDR) from core table CRC. This data is placed in the work area
(FWB) in order to be written into RS Memory.
j. Requests the MANIP program module (F35) to perform a Non-Dial
Line Digit Translation on non-dial switched direct lines (CCEOCT =
5). Schedules the Non-Dial Line Store program module (C.phi.3) when
the Non-Dial line Digit Translation is successful. Schedules the
Local Call Process Maintenance Program (module C31) when the
translation is unsuccessful.
k. Sets the first digit in RS Memory (XD1) to 0 (10) for operator
assistance non-dial common battery lines (CCEOCT = 4).
l. Sets the Instruction Field (IN) equal to 2 and Complete
Translation Request (CTR) equal to 1 for a translation complete
indication.
m. Attempts to obtain a receiver, when required, by using the
Sender/Receiver Assigner program module (C27). If the first attempt
of obtaining a receiver fails, module C.phi.2 initiates
Sender/Receiver (S/R) timing in the RS. Module C27 is used to
search for an idle, assigned, and on-line receiver until either one
is found or until the timer runs out (the RS goes into system
trouble).
n. Sets the totals instruction (XTL) equal to 0, and the expected
interrupt instruction to 3 (TIE = 3) when an MP receiver is
obtained (AOG = 2). No interrupt will occur until all the required
digits are received.
o. Has the RS Access program module (F.phi.8) write the required
data into RS Memory and releases the work area, with or without an
attached receiver.
4. INPUTS
4.1 software
4.1.1 core Tables
Cce -- core Class of Service Expansion.
Dep -- engineered Office Parameters.
Cja -- original Class Data.
Crc -- call Processing Receiver Control.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
4.1.2 Drum Tables
None.
4.1.3 Registers
None.
4.2 HARDWARE
None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chq -- program Generated Indicators.
Cwa -- sender Receiver Assigner Interface.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables
None.
5.1.3 Registers
None.
5.2 HARDWARE
None.
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points C.phi.2X.phi.1 The
normal entry is scheduled by the COS Initialization program, module
C.phi.1, following the initial COS translation. Additional
translation requirements are determined from the COS data. S/R
requirements are processed through module C27. C.phi.2X.phi.2 This
entry point is scheduled by module C27 when an idle assigned
receiver is obtained during S/R timing. The RS is instructed to
connect the receiver; then control is released until the required
number of digits are received. 6.2 EXIT POINTS Exit Reasons for
Exit Points C31X.phi.3 Local Call Process Maintenance Program
(LCPMP): This exit point is called when module C.phi.2 encounters
an error. A trouble index must be passed in X2 for use in
outputting the appropriate Teletypewriter (TTY) message. For module
C.phi.2, the subscriber is given lockout via C26X.phi.4, thus
returning control to the calling program. F.phi.8X.phi.1 RS Access
Program: This exit point is used for writing in RS Memory. It also
has the capability to write and to read-modify-write. F35X.phi.1
Data Manipulator (MMANIP) Program: This exit point is used by
resident and non-resident programs to access drum memory. After
MANIP is entered, the user loses control of his WA. To regain
control, the user must request another WA. 7. SUBROUTINES USED
Entry Functional Names Points C27X.phi.1 Sender/Receiver Assigner.
C29X.phi.1 Call Condition Analysis. F.phi.8X.phi.1 Register-Sender
Access. - M.phi.5X.phi.1 Call Event Metering: Successful RJ
Connections. M.phi.9X.phi.1 Call Event Metering: Sender/Receiver
Connection.
8. NARRATIVE
8.1 discussion
the COS data is common to a large group of subscribers and it is
stored in core tables CCE and CRC. Module C.phi.2 retrieves and
analyzes the common COS data for each origination to determine the
type of call (local, non-local, etc.). Then module C.phi.2 routes
this data to the appropriate Call Processing module for further
processing.
Module C.phi.2 is also responsible for obtaining the required MF or
TCMF receivers. This is accomplished by utilizing module C27.
8.2 technique
two unique techniques are employed by module C.phi.2. The first
technique employed by module C.phi.2 is in retrieving the required
common COS data. Module C.phi.2 utilizes index values obtained from
the initial COS translation (tables CLN or CTN) to access tables
CCE and CRC. The data obtained is written into RS Memory and is
utilized to further process the call.
The second technique employs the use of module C27 to obtain an
idle, assigned, and on-line receiver. A receiver must be connected
in the call path of MF and TCMF originations in order to receive
the input information. This must be accomplished prior to any
further call processing. Module C.phi.2 utilizes module C27 in
making a single attempt to obtain a receiver. If the attempt fails,
a S/R timing mechanism in RS Memory is initialized. Module C.phi.2
then returns to module C27 where it continuously attempts to obtain
a receiver. This procedure continues until either a receiver is
obtained or a timeout occurs. Utilizing this technique each
origination is given the maximum opportunity in obtaining the
required receiver.
Notes to figs. 72-72c.
1. f.phi.8 will transfer to release (e.phi.1) to release wa. if
trouble, in rs, f.phi.8 will schedule c31x.phi.2. in updating 1a,
2a, 4a, 6a, 6b, f.phi.8 will protect fd, edp, trb, tas, rsf, trj,
trc, p2, to, cab, trj, of rs and place their imaof in fwb.
2. manip will place non-dial line xtrans in cxa and schedule
c.phi.3x.phi.1. for error, f35 will schedule c31x.phi.1.
c.phi.3 -- fig. 73
1. name
non-Dial Line Store module.
2. PURPOSE
The Non-Dial Store program (module C.phi.3) formats the Non-Dial
Digits, which were retrieved from drum translation table CND, to
enable the writing of the digits into Register-Sender (RS) Memory.
A software All-Ditis Received indicator (ADR) is set and RS Memory
is updated via a request to the RS Access program, (module
F.phi.8). The originating Class Of Service (COS) data formatted by
the originating COS Analysis program (module C.phi.2) is written
into RS Memory concurrently.
3. FUNCTIONS
Module C.phi.3 performs the following functions:
a. Formats the non-dial digits in order to write them into RS
Memory.
b. Indicates in the Call History Table (CHT) that all required
digits have been received (CHQADR = 1).
c. Prepares information to be written into RS memory Indicating the
digit count.
d. Directs the RS Access program to write into RS Memory the data
formatted in module C.phi.3' and the COS data formatted in module
C.phi.2.
4. inputs
4.1 software
4.1.1 core Tables
Cja -- originator's Class of Service Data.
Cxa -- drum Table CND Data.
Fwa -- executive Interface Work Area.
4.1.2 Drum Tables
None.
4.1.3 Registers
None.
4.2 HARDWARE
None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables
None.
5.1.3 Registers
None.
5.2 HARDWARE
None.
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points C.phi.3X.phi.1
Scheduled by module C.phi.2 after drum table CND translation is
successfully completed. C.phi.3X.phi.1 properly formats the
non-dial digits in the RS and sets up the RS and the CHT for
continuation of normal call processing. 6.2 EXIT POINTS Exit
Reasons for Exit Points F.phi.8X.phi.1 RS Access Program: This exit
point is used for writing in RS Memory. It also has the capability
to write and to read-modify-write. 7. SUBROUTINES USED Entry
Functional Names Points None.
8. NARRATIVE
8.1 discussion
one of the many possible features a subscriber may request is to
have his telephone used as a "hot-line"; i.e., all the calls
terminate to a predetermined destination without inputting any
digits. An example of this type of service is the hotel reservation
phones available at airports. Here, the subscriber can pick up a
telephone handset and immediately be connected to a particular
hotel's reservation desk. This feature can be implemented in one of
two ways. Either the subscriber is directly wired to the
destination (this would be impractical over long distances) or, as
in EAX, the digits required for termination are internally
generated by the switching system. The call processing software
determines if an originating subscriber has the non-dial
switched-digit (hot line) feature. If so, the required unique
dialed digits are retrieved from drum table CND. Module C.phi.3 is
utilized in inputting these unique dialed digits into the RS
Memory. Call Processing will now terminate the call normally.
8.2 TECHNIQUE
Not applicable.
*NOTES TO FIG. 73
1. fwbx2a, fwbx4a also contains cos xtrans done by c.phi.2. f.phi.8
will transfer to releas (e.phi.1) to release wa. if trouble in rs,
f.phi.8 will schedule c31x.phi.2 in updating 1a, 2a, 4a, 6a, 6b.
f.phi.8 will protect fd, eop, trb, tas, rsf, trj, trc, p2, to, cab,
tri of rs and place their image in fwb.
c.phi.4 -- fig. 74
1. name
pretranslator Initialization Module.
2. PURPOSE
The Pretranslator Initialization program (module C.phi.4) is
scheduled for all non-local originations. For Multifrequency (MF)
calls, the Key Pulse (KP) and Start (ST) digits are removed from
the Register-Sender (RS) Memory, and the receiver busy indicator is
reset. Module C.phi.4 determines if the Non-Local Pretranslator
program (module C.phi.5) or the Digit Analysis program (module
C.phi.6) is required as the next step in call processing.
3. FUNCTIONS
Module C.phi.4 performs the following functions:
a. Resets the receiver busy indicator by calling the
Sender/Receiver Assigner subroutine (C27X.phi.1) when the call is
2/6 MF and the Conditional Matrix Disconnect (CMD) bit is set in RS
Memory.
b. Deletes the ST and KP digits, when the call is 2/6 MF using the
RS Write program (module F08). Also sets All Digits Received (ADR)
in the Call History Table (CHT).
c. Uses the Pretranslator Standardization Required (PTS) field from
the originating Class of Service (COS) translation to determine if
the Non-Local Pretranslator program is required. If non-local
pretranslation is required, control is transferred to module
C05.
d. Determines if sufficient digits were received, when module C05
is not required, in order to continue with digit analysis. If
sufficient digits have been received, control is transferred to
module C06. If insufficient digits have been received, the RS
totals field (XTL) is set to 3 via module F08. Module C06 is
scheduled after the reception of three digits.
e. Freezes the Register Junctor (RJ) and schedules module V99 when
the originator is either a Trunk Test Access circuit (TTA) or a
Communications Line (CL).
4. inputs
4.1 software
4.1.1 core Tables
Cce -- core Class of Service Expansion.
Cja -- originating Class of Service Data.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register-Sender Memory Image.
4.1.2 Drum Tables
None.
4.1.3 Registers
None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chg -- code Translation Information.
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register-Sender Memory Image.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
Control
6.1 entry points entry Reasons for Entry Points C04X01 The
Originating COS Analysis Program (module C02) determines if the
originator is non-local, then it schedules module C04 to receive
control on a Translation Interrupt (TRI) from the RS. Normally
TRI=1; however, for Multifrequency reception TRI=3. 6.2 EXIT POINTS
Exit Reasons for Exit Points C05X01 Non-Local Pretranslation
program: C05X01 is branched to from module C04 for non-local
originators whose digits are in non-standard form. C06X01 Digit
Translation Initialization program: C06X01 is exited to or
scheduled when additional digit translations are required. C06X01
schedules drum table CTT or CGT translations and/or program modules
as required. E01X06 Data Processing Unit (DPU) Scheduler (RESKED)
program: Exit line E01X06 is used to cause the DPU Scheduler to add
a run request to a queue. E01X06 can be used by any application
program not executed in the interrupt mode. C31X03 Local Call
Process Maintenance Program (LCPMP): This exit point is called when
C04 encounters an error. A trouble index must be passed in X2 for
use in outputting the appropriate Teletypewriter (TTY) message. For
module C04 the subscriber is given lockout via C26X04. F08X01 RS
Access Program: This exit point is used for writing in RS Memory.
It also has the capability to write and to read-modity-write. 7.
SUBROUTINES USED Entry Functional Names Points C27X01
Sender/Receiver Assigner. F08X01 RS Access Program. V75X04
Maintenance Control Center. (MCC) Maintenance String. 8.
NARRATIVE
8.1 discussion
the non-local traffic coming into EAX may utilize Dial Pulse or 2/6
MF signalling. The digit trains of this non-local traffic may
optionally require digit standardization via the non-local
pretranslator. The above characteristics are determined by the
incoming trunk circuit and the sending office.
When MF signalling is required, the KP and ST digits are received
but not used in routing the call. The KP and ST digits indicate the
beginning and the end of the digit train, respectively and have no
other function when received in a Class 5 Office. The KP and ST
digits are deleted from the digit train prior to digit analysis.
Module CO4 is responsible for deleting the KP and ST digits and
determining if digit standardization is required for the incoming
digit train.
8.2 TECHNIQUE -- Not applicable.
C.phi.5
1. name -- non-Local Pretranslator Module.
2. PURPOSE
The Non-Local Pretranslator program (module C05) is utilized for
non-local originations only, and therefore must be able to uniquely
identify an incoming trunk digit train to determine if
standardization procedures are required. When standardization is
required, module C05 deletes and/or adds the necessary digits prior
to passing control to the Digit Translation Initialization program
(module C06) for the initiation of the appropriate three-digit
translation.
3. FUNCTIONS
Module C05 performs the following functions:
a. Performs a one-, two-, or three-digit translation, depending
upon the value of the totals field (XTL). (XTL can equal 1, 2, or
3. ) The translation is performed utilizing the called digits as
input.
b. When the one-, two-, or three-digit translation indicates a
final translation (FPX = 1), module C05 can attempt to delete
and/or add the required digits.
1. When the Register Sender (RS) has insufficient digits to delete,
module C05 waits until the RS obtains sufficient digits; then
begins its process again.
2. After digits are deleted and/or added (added digits are obtained
in the translation process), module C05 updates the RS Memory with
the standardized digits.
3. The translation also indicates if the Modified Routing Type
(MRT) of the originator is to be changed.
4. The Time Frame (TMF) is set to 2 and the call History Table
(CHT) is initialized (CHGNJR = CHGPJR = 3 where NJR is the Next Job
to Run and PJR is Previous Job Run) to enable module C06 to perform
a three-digit translation.
5. If at least three digits are obtained, control is passed to
module C06.
6. for all other conditions, the RS waits for additional digits,
then schedules module C06.
c. When the one-, two-, or three-digit translation does not
indicate a final translation (FPX = 0), module C05 performs
additional translations.
1. When the Incoming Digit Counter (IDC) is not utilized as part of
a search key, and there are sufficient digits, module C05 initiates
either a two- or three-digit translation, then reschedules module
C05.
2. if IDC is not utilized as part of the search key, and there are
insufficient digits, module C05 instructs the RS to obtain the
required number of digits, and reschedules module C05 (where
function (1 above will be performed).
3. When IDC is utilized as part of the search key, and there are
sufficient digits for the additional translation, module C05 places
IDC in the first, second, or third digit position (search key);
initiates a one-, two- or three-digit translation; and reschedules
module C05.
4. if IDC is utilized as part of the search key, and there are
insufficient digits, module C05 instructs the RS to obtain the
required number of digits, and reschedules module C05 (where
function (3) above will be performed).
4. INPUTS
4.1 software
4.1.1 core Tables
Cce -- core Class of Service Expansion.
Che -- pretranslator Access Store Data.
Cja -- originating Class of Service Data.
Cxb -- pretranslator Drum Table CPD.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Che -- pretranslator Access Store Data.
Chg -- code Translation Information
Cja -- originating Clas of Service Data.
Fwa -- executive Interface Work Area.
Fwb --call Processing Register Sender Memory Image.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points C05X01 C05X01 is
branched to from the Non-Local Pretranslator Initialization program
(module C04) for non-local originators whose digits are in
non-standard form. C05X01 may also be scheduled when C05X02 is
processing a final pretranslation and finds that more digits must
be collected. C05X02 C05X02 is always scheduled upon the successful
completion of a Pretranslator Data (CPD) translation Since entry
lines C05X01, C05X02 and C05X03 can initiate a CPD translation,
they all can schedule C05X02. C05X03 C05X03 is scheduled by C05X02
after sufficient digits are received and either a Translation
Interrupt (TRI=1) or a Fast Timeout (FTO) has occurred. C05X03
initiates a CPD translation and C05X02 is scheduled upon completion
of the translation. -6.2 EXIT POINTS Exit Reasons for Exit Points
C05X01 Digit Translation Initialization Program: C06X01 is called
when additional digit translations are required. C06X01 schedules
drum table (CTT or CGT) translations and/or program modules as
required. F08X01 RS Access Program: This exit point is used for
writing in RS Memory. It also has the capability to write and to
read-modify-write. F35X10 Data Manipulator (MANIP) Program: Used by
resident and non-resident programs to access drum memory. V73X01
Maintenance Control Center (MCC): - Maintenance String Program:
V73X01 is used by module C05 in order to perform the digit analysis
function for the Incoming Remote Test Trunk (IRTT)/Line Test Access
(LTA) originations, when a nine-digit Line Number Identity (LNI)
was dialed instead of a directory number. 7. SUBROUTINES USED Entry
Cunctional Names Points F08X01 RS Access.
8. NARRATIVE
8.1 discussion
common control systems, as well as progressive control systems,
must be able to interface with EAX. Common control switching
systems have the capability of using 2/6 Multifrequency (MF)
sending, and normally are engineered to properly format the digit
train. This formatting eliminates the need for digit
standardization. Progressive control systems absorb several dialed
digits in determining the interoffice routing thus causing EAX to
receive an incomplete set of digits. The EAX then standardizes the
incomplete digit train by restoring any absorbed digits.
An example of a subscriber in a progressive controlled Step-by-Step
(SXS) office placing a call to a subscriber in an EAX office. When
863-1234 is dialed and 863 is the home office code of the EAX, the
SXS office absorbs the 863 digits and routes the last four digits
to the EAX office. The EAX, therefore, must restore the 863 digits
before processing the call. Standardizing the incoming digit
trains, by the adding and/or deleting digits, is performed by
module C05. Once digit standardization is performed, digit analysis
begins processing the call.
8.2 TECHNIQUE
Module C05 employs a technique uniquely identifying the incoming
trunk digit train enabling the appropriate digits to be added
and/or deleted.
Associated with every incoming trunk is a unique Trunk Group
Incoming (TGI) value. The TNI value is obtained from the
originating Class of Service (COS) data in drum table CTN and it
allows module C05 to individually standardize incoming trunk digit
trains. A simplified example, illustrating the necessity of the TGI
value, is shown in FIG. 2. Two home office codes (452 and 932) are
associated with the EAX office. Two SXS offices are directly
trunked into the EAX office. When a subscriber in SXS office 1
dials 452-5678, the SXS office absorbs the first two digits;
therefore EAX only receives 25678. This digit train arrives on TGI
equal to 22, and the EAX office restores the digits (4,5) absorbed
by the SXS office. If a subscriber in SXS office 2 dials
932-532-5678, the EAX office again receives 25678; however, this
time on TGI equals 31. This illustrates that the TGI value is
necessary in determining which prefix digits (45 or 93) are
associated with the digit train.
Digit standardization patterns are unique to a particular office;
i.e., an engineerable item on a per office basis. All data
necessary for the pretranslator process is therefore contained in
the engineerable Pretranslator Data table (CPD). Module C05
performs digit standardization by searching drum table CPD, and
analyzing the retrieved data.
There are five items which constitute a CPD translation request
search key. These items are listed below:
ITEM DESCRIPTION TGI Trunk Group Incoming: Uniquely identifies the
incoming trunk group. SID Search on Incoming Digit Count
Indication: SID=1 indicates that one of the incoming digit values
(XD1 through XD3) is the total number of digits received (not
counting the Key Pulse (KP) and Start (ST) digits) from the
incoming call SID=0 indicates that XD1 through XD3 only contain
digit values. XD1 Digit value of the first digit received: can
represent IDC value if SID=1. XD2 Digit value of the second digit
received: Can represent IDC value if SID=1. XD3 Digit value of the
third digit received: Can represent the IDC value if SID=1.
Utilizing the TGI value, the items allow the incoming trunk to be
uniquely specified. Utilizing combinations of SID, XD1, XD2, and
XD3, the incoming trunk digits train is uniquely identified.
Two or more CPD translations may be required prior to performing
digit standardization. When obtaining data contained in table CPD,
one of two formats is utilized. The CPD translation requirement is
utilized as the basis of format selection. The data formats are
described as follows:
Format A (FPX =0) ITEM DESCRIPTION -FPX Final Pretranslator
Indicator: FPX = 0 indicated that standardization of an incoming
digit train is not yet possible, and at least one more
pretranslation is required. FPX =1 (See Format B). XTL Totals
Field: Indicates total number of digits to be collected before
initiating the next pretranslation. FTO Fast Timeout Field:
specifies number of digits to be received before fast timing is
initiated. Fast timing will then begin on the arrival of the next
digit. TIP Translation Interrupt Digit Position: Specifies XD1,
XD2, or XD3 digit position into which the IDC value from RS Memory
is placed. This is accomplished when a response to the XTL request
is received from the RS. FTP Fast Timeout Digit Position: Same as
TIP, except response to a FTO request. Format B (FPX =1) ITEM
Description FPX Final Pretranslator Indicator: FPX =1 indicates
that standardization of an incoming digit train is possible. The
remainder of Format B contains standardization data. DDF Delete
Digit Field: Specifies number of digits to delete from the incoming
digit train. DPF PDF Prefix Digit Dield: Specifies number of digits
(RD1 through RD6) prefixing the incoming digit train. RD1-RD6
Replacement Digit Values: Each field specifies the value of the
digits prefixing the incoming digit train. ORT Originating Routing
Type: ORT = 0 indicates that ORT obtained from table CTN must be
used in processing the call in process. If ORT is not equal to 0,
this value should replace the ORT
An example of digit standardization is: An incoming trunk, from a
SXS office (TGI = 27), can send three distinct digit patterns (a,
b, and c) to the EAX office. Module C05 uniquely identifies each of
the digit patterns, then prefixes the necessary digits. If the
first digit is a 4, pattern a is immediately identified. Patterns b
and c, however, can only be differentiated by examining the total
number of digits received (either 4 or 5). Table CPD is engineered
to immediately standardize the digit train when a 4 is recognized
as the first digit. If, however, a 5 is the first digit, another
translation is required after all the digits are received.
The technique employed in engineering table CPD is flexible, thus
allowing EAX to interface with any existing or presently conceived
type of adjoining switching systems. C.phi.6 -- FIG. 75-76A
1. name -- digit Translation Initialization module.
2. PURPOSE
The Digit Translation Initialization module (C.phi.6) utilizes the
Next Job to Run (NJR) field in determining which additional jobs
are required (drum translations and/or program modules) for
continued call analysis. Module C.phi.6 Idles Touch Call
Multifrequency (TCMF) receivers by utilizing the Conditional Matrix
Disconnect (CMD) field. Module C.phi.6 also attempts to resolve
ambiguous Number Plan Area (NPA) codes. When the attempt is
unsuccessful, the subscriber is given reorder tone via the Final
Processor program (module C26).
3. functions -- Module C.phi.6 performs the following
functions:
a. Idles the assigned TCMF receiver, via the Sender/Receiver (SR)
Assigner program (module C27), when CMD = 1 and module C.phi.6 is
not entered as the result of a fast timeout (FWBXTO). The
Register-Sender (RS) Memory is updated and control is returned to
module C.phi.6 for further analysis.
b. Determines which additional translations and/or program modules
are required by utilizing the NJR field, NJR field descriptions are
as follows:
NJR Job Description 0 No More Translations Required: Module C.phi.6
transfers control to the Digit Translation Analyzer program (module
C08) to wait for reception of all the digits. Allowed on Six (AOS)
Check: Performs a three-digit translation (drum table CTT) using
the fourth, fifth, and sixth dialed digits (XD4, XD5, and XD6) to
determine if these digits are allowed with an NPA code. Schedules
C08X01 after a successful MANIP access. 2 Office code in the Home
Number Plan Area (HNPA) which is also an Extended Local Area
Calling Service (ELACS) Office code of a Foreign Number Plan Area
(FNPA): Performs a three-digit translation (table CGT) using the
first, second, and third dialed digits (XD1, XD2, and XD3) to
determine the routing information pertaining to the HNPA. Schedules
C08X01 after a successful MANIP access. 3 Three Digit Translation:
Accesses table CTT using XD1, XD2, and XD3. Schedules C08X01 after
a successful MANIP access. Every call processed by call processing
will perform this translation at least once. 4 Four Digit
Translation: Accesses table CGT using XD1, XD2, XD3, and XD4.
Schedules C08X01 after a successful MANIP access. This type of
translation would be required when the first three digits are a
split office code and therefore a fourth digit is required for
routing information. 5 Five Digit Translation: Accesses table CGT
using XD1, XD2, XD3, XD4, and XD5. Schedules C08X01 after a
successful MANIP access. This type of translation would be required
when the first three digits can be an Indial Private Automatic
Branch Exchange (PABX) of 100 or less numbers. Five digits are
necessary to route this type of call. 6 Six Digit Translation:
Accesses table CGT using XD1 through XD6. Schedules C08X01 after a
successful MANIP access. This type of translation would be required
when a direct trunk exists from EAX to an office in a Foreign NPA.
EAX requires a total of six digits to determine if a direct trunk
is to be used. 7 Ambiguous NPA Code: Module C06 attempts to
determine whether the code dialed is an office code or a FNPA code.
When a FNPA code is dialed EAX determines if the number is a
directory number call, an information call, or a special code. 8
Initiate a Route Number Translation: Module C06 transfers control
to C10X02 and a Route Number Translation if performed. 9 Collect
More Digits: Module C06 transfers control to C08X02 when a code is
dialed which requires Early Outpulsing (EOP) after a certain number
of digits. The software must wait for the reception of these digits
before outpulsing occurs.
4. INPUTS
4.1 software
4.1.1 core Tables
Chg -- code Translation Information.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register/Sender Memory Image.
4.1.2 Drum Tables - None.
4.1.3 Registers - None.
4.2 HARDWARE - None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chg -- code Translation Information.
Dhl -- ticketing Interface Data.
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
5.1.2 Drum Tables - None.
5.1.3 Registers - None.
5.2 HARDWARE - None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C06X01 C06X01 is
scheduled when additional digit translations are required. C06X01
also schedules drum table translations (CTT or CGT) and/or program
modules as required. If an ambiguous code is dialed (NJR=7) C06X01
attempts to resolve whether the dialed code is an office or an NPA
code. 6.2 EXIT POINTS Exit Points Reasons for Exit C08X02 Digit
Translation Analyzer program C08X02 is scheduled by module C06 when
the Previous Job Run (PJR) does not entail additional drum
translations (PJR=0, 8, or 9). C10X02 Route Translations
Initialization program: C10X02 is entered only to initiate route
number translation. It initiates the drum translation (CRN) then
schedules the Route Number and Directory Number Translation program
(module C15). program (module C15). C26X02 Final Processor program:
C26X02 terminates the call by returning reorder tone from the
Register Junctor (RJ). C31X03 Local Call Process Maintenance
Program (LCPMP): This exit point is called when module C06
encounters an error. A trouble index must be passed in X2 for use
in outputting the appropriate Teletypewriter (TTY) message. For
module C06 the subscriber is given lockout via C26X04. F35X01 Data
Manipulator (MANIP) program: Used by resident and non-resident
programs to access drum memory. 7. SUBROUTINES USED Entry Points
Functional Names C27X01 Sender-Receiver Assigner. F05X01
Register-Sender Write.
8. NARRATIVE
8.1 discussion
module C06 is the overall controller of the digit analysis process.
Mudule C06 performs two major functions: (1) it determines the next
job to perform via the NJR field, (2) it resolves certain dialed
code ambiguities. Module C06 also accomplishes the software idling
of dropped TCMF receivers via the CMD field mechanism.
The primary responsibility of module C06 is to determine which
additional jobs, drum translations, and/or program modules are
required to complete the digit analysis portion of call processing.
This is accomplshed by utilizing the NJR field as defined
below:
NJR Job Description 0 No More Translations Required. 1 AOS
Procedure. 2 ELACS Protected Office Code. 4 Four Digit translation.
5 Five Digit Translation. 6 Six Digit Translation. 7 Ambiguous
Code. 8 Route Number Translation. 9 EOP -- Wait for Digits.
Module C06 attempts to resolve existing ambiguities between NPA and
office codes (NJR = 7). This is accomplished utilizing the Incoming
Digit Count (IDC) and the values of the dialed digits. Most of the
time the RS is given a Totals (XTL) value of 10, and a Fast Timeout
(FTO) value of 7. In this case, when FTO occurs, a total of only
seven digits were dialed (IDC = 7), thus indicating an office code
was dialed. No more translations are required and the routing
information for the call is contained in table CTT. When IDC = 10,
an NPA code is indicated and a CGT translation is required in order
to retrieve the routing data. This occurs when a RS Translation
Interrupt (TRI = 1) is indicated (IDC = XTL).
When an office has ambiguous codes and if it also allows certain
special codes (e.g. toll operator NPA + 411), FTO must then be
engineered so that it equals 15. This enables the RS to perform
fast timing after each digit. Fast timing after each digit is
necessary since it is impossible to determine the total number of
digits to be received (XTL = 7,XTL = 6, XTL = 10). When a FTO
interrupt with a IDC equal to 6 occurs, the specific values of the
dialed digits are checked to determine which special code was
dialed. When IDC = 7 or 10, processing is performed as previously
discussed. When the ambiguity cannot be resolved, the subscriber is
given reorder tone because he is not following the dialing
plan.
8.2 TECHNIQUE
Module C06 utilizes the CMD mechanism to software idle receivers
via the Sender/Receiver Assigner Routine (module C27). In the
following two situations the CMD mechanism is set during Digit
Analysis by the Digit Translation Analyzer program (module
C08).
For the first situation, module C08 determines that all digits will
be received prior to the next scheduling of module C06, thus CMD is
set and written into RS Memory. When the RS finds a Totals-Incoming
Digit Count match (XTL = IDC), the attached receiver is dropped.
Module C06 is then given control on a TRI equal to 1 interrupt (IDC
= XTL). With TRI = 1and CMD = 1, module C06 accesses module C27 in
order to software idle the particular receiver dropped by the RS.
If a FTO occurs with CMD = 1, the second mechanism is then used to
idle the receiver.
For the second situation, module C08 determines that all digits are
received and then issues an Instruction Field instruction (IN = 14)
along with a CMD=1 indication to the RS. The RS then drops the
receiver (TRI = 7) and module C06 gains control. Module C06
discovers the CMD = 1 indication and utilizes module C27 to
software idle the assigned receiver.
C.phi.7 -- fig. 77
1. name --c.phi.7 -- local Pretranslator module.
2. PURPOSE
The Local Pretranslator program (module C07) prepares the local
subscribers digit trains for the digit analysis process. Any prefix
digits must be deleted from the Register-Sender (RS) Memory in
order to standardize all digit trains input for digit analysis.
3. FUNCTIONS
Module CO7 performs the following functions;
a. Indicates a 0 prefix dialed (CHQVPD= 3); deletes the 0 prefix
digit from RS Memory; and exits to the digit analysis program by
setting NJR = PJR = 3, where NJR is the Next Job to Run and PJR is
the Previous Job Run. This procedure is followed when 0+ dialing is
in effect (CEPZPD = 1), and the first digit dialed is a 0.
b. Indicates a 1 prefix dialed (CHQVPD = 2); deletes the 1 prefix
digit from RS Memory; sets up transfer control parameters (NJR =
PJR = 3); and exits to the digit analysis program. This procedure
is followed when 1+ dialing is in effect (CEPOPD = 1), and the
first digit dialed is a 1, and the second digit dialed is not a
1.
c. Indicates no prefix operation required (CHQVPD = 1); sets up
translation control parameters, and exits to the digit analysis
program for all other digit inputs.
d. Schedules the digit analysis program, after the RS collects
three digits. When insufficient digits (less than three) are
collected, an error message indicating a problem in the data base
is output on the Teletypewriter (TTY).
4. inputs
4.1 software
4.1.1 core Tables
Cep -- engineered Office Parameters.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register-Sender Memory Image.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chg -- code Translation Information.
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry. C07X01 Scheduled
by the Originating Class Of Service Analysis program (module C02)
after the RS receives three digits (actually four digits are
received when 0+ or 1+ dialing is in use). The dialing plan of the
office, the first, and possibly the second dialed digit determine
if the subscriber dialed a valid prefix. When a prefix is dialed,
its value is saved in a core table and the digit is deleted from RS
Memory. Digit Analysis therefore is given control, with the proper
first three digits, to perform a translation. 6.2 EXIT POINTS Exit
Points Reasons for Exit C06X01 Digit Translation Initialization
program: C06X01 is scheduled when additional digit translations are
required. C31X03 Local Call Process Maintenance Program (LCPMP):
This exit point is called when module C07 encounters an error. A
trouble index must be passed in X2 for use in outputting the
appropriate TTY message, the Work Area (WA) is released. 7.
SUBROUTINES USED Entry Points Functional Names F08X01
Register-Sender Write.
8. NARRATIVE
8.1 discussion
digit analysis is necessary in processing all calls; therefore, an
input format which is common to both local and non-local
originations is required. Under the 0+ and/or 1+ dialing option,
deletion of valid prefix digits is performed before initiating a
three digit translation. The local subscriber's pretranslation
process is performed by module C07. Module C07 also ensures that at
least three dialed digits are delivered to digit analysis.
8.2 TECHNIQUE -- Not applicable.
* NOTES TO FIG. 77
1. if a one has been dialed a check will be made for special codes
11x in which case the one is not considered a prefix.
2. probable error in initial digit reception instructions (xtl,
prf, zoc) when issufficient digits
c.phi.8 -- figs. 78-78b
1. name -- digit Translation Module.
2. PURPOSE
The Digit Translation Analyzer program (module C08) is responsible
for analyzing data retrieved from drum table translations (CCT/CGT)
initiated by the Digit Translation Initialization program (module
C06). The specific functions performed by module C08 depend upon
the job previously done by module C06 as indicated by the Previous
Job Run (PJR) field. The PJR field equals the Next Job Run (NJR)
field (NJR value prior to last translation) and is completely
internal to Digit Analysis.
Module C08 performs certain functions which are common to all
calls. These common functions include processing of Early
Outpulsing (EOP), disconnecting Touch Call Multifrequency (TCMF)
receivers, and restricting the allowable (engineerable) values of
NJR.
Module C08 sets up for additional digit analysis, exits to the
terminating process, or routes the call to intercept depending upon
the analysis of each call.
3. FUNCTIONS
Module C08 performs the following functions:
a. Indicates an error and schedules the Local Call Process
Maintenance Program (module C31) for a Teletypewriter (TTY) error
message when, upon entry to module C08, the PJR value is out of its
allowable range (PJR greater than or equal to 8).
b. Sets NJR equal to 0 to restrict further translations when no
coincidence is found on drum and module C08 is scheduled after a
drum translation is performed by module C06. Module C08 returns to
module CO6 only when insufficient digits are received (CHQADR =
0).
c. Performs the Allowed On Six (AOS) check when PJR=1 and
coincidence is found on the drum, if code is AOS, check the fourth
through sixth dialed digits (XD4-XD6) for a special code. If the
code is not AOS, route the call to intercept.
1. For Number Plan Area (NPA) + 411 toll information (XD4 through
XD6 equal 411 respectively) set the All Digits Received (ADR)
indicator to 1. When information calls are free (CEPFCI = 1) reset
the Coin Deposit Required (CDR) indicator and set NJR t0 0 to
restrict further translations.
2. For NPA + 555 + 1212 toll information (XD4 through XD6 equal 555
respectively), set the Register-Sender (RS) Totals to 10. When
information calls are free (CEPFCI = 1) reset the CDR indicator and
set NJR to 0 to restrict further translations.
d. Performs the same functions for PJR = 2 (ELACS Protected Office)
as for PJR = 3 when the first three digits are identified as an
office code.
e. Retrieves the Code Identification (CID) field and proceeds as a
function of its value when PJR = 3 and coincidence is found on the
drum:
1. For Strowger Automatic Toll Ticketing (SATT) Access codes (CDI =
1), set the Value Prefix Digit (VPD) to 2 to indicate 1 + dialing,
delete the first three digits, and set NJR = 3 for a three-digit
translation; then return to module C06.
2. for Reverting Call Access code (CID = 2) in an office arranged
for option "A" dialing (119--XY) set the XTL field to 2, set NJR to
0 for no more translations required indication, set the Reverting
Call Circuit (RCC), when equipped, to 1 to delete the first three
digits (119) from RS Memory and initialize the RS Memory for
reception of additional digits.
3. For Reverting Call Access code (CID = 2) in an office arranged
for option "E" dialing (119-NXX-XXXX), delete the first three
digits (119) set NJR = 3 for a three-digit translation (drum Table
CTT) on NXX, and set the XTL field in RS Memory to 3 to enable the
collection of additional digits.
4. For Home NPA (HNPA) code (CDI = 3) determine whether HNPA
dialing is allowed (CEPHCA). If allowed (CEPHCA = 1), delete the
first three digits and set NJR = 3 for a three-digit translation on
the next three digits. If not allowed (CEPHCA = 0), retrieve the
route number for the invalid code intercept.
5. For Unused or Service Codes (CID = 4), set the ADR indicator to
1 CHQADR = 1) and pass control to the Route Translation
Initialization program (module C10) for retrieval of routing
information. When a receiver is attached (CHQRSA = 1), issue an IN
instruction (IN = 14) and a Conditional Matrix Disconnect (CMD)
value equal to 1 in order to drop the receiver. Set NJR = 8 so
module C06 can schedule module C10 after processing the CMD =
1.
6. for Terminating Toll Center (TTC) or Operator Codes (CID = 5),
check the Special Code Allowed (SCA) indicator. If TTC or Operator
Codes are allowed (SCA = 1) the RS is instructed to continue normal
processing. If TTC or Operator Codes are not allowed (SCA = 0)
retrieve the route number for invalid code intercept and route the
call appropriately.
7. For INWATS Access Code (CDI = 6), continue processing. If NJR is
not equal to 0 a data base error exists and the Local Call Process
Maintenance Program (module C31) is scheduled to output a
Teletypewriter (TTY) message.
8. For Office Codes (CDI = 7), determine if the code is Extended
Local Area Calling Service (ELACS) protected (CHGECP = 1) with a
prefix digit dialed (1 + : CHQVPD = 2). If so, set NJR = 2 for an
ELACS translation. For NJR values of 4, 5, or 0 continue
processing. For all other NJR values indicate a data base error and
schedule module C31 to output an error message.
9. For Foreign NPA (FNPA) codes (CID = 8), continue processing if
NJR equals 1 or 6. Perform an Allowed On Six check or a six-digit
translation respectively. For all other NJR values, schedule module
C31 for an error message output.
10. For Special Codes (CDI = 9), continue processing as a function
of the NJR value.
11. For Ambiguous Codes (CDI = 10), save the NJR value from the
translation table, set NJB to 7 for ambiguous code processing in
module CO6, and initialize the RS according to the translation
data.
f. For four-digit translations (PJR = 4) when coincidence is found
on the drum and NJR = 0 or 5, continue processing, otherwise
schedule module C31 for an error message output.
g. For five-digit translations (PJR = 5) when coincidence is found
on the drum and NJR - 0 (no more translations required), continue
processing; otherwise schedule module C31 for an error message
output.
h. For six-digit translations (PJR = 6) when coincidence is found
on the drum and NJR = 0 (no more translations required), continue
processing, and perform the AOS check (AOS = 1); otherwise schedule
module C31 for an error message output.
i. For FNPA codes (PJR = 7) when coincidence is found on the drum
and the first three digits are identified as a FNPA code, perform
an AOS check or six-digit translation when NJR = 1 or 6
respectively. For all other values of NRJ schedule module C31 for
an error message output.
j. Module C08 utilizes an IN = 14 instruction and/or the CMD
mechanism in disconnecting any TCMF receivers before terminating
digit analysis.
4. INPUTS
4.1 software
4.1.1 core Tables
Cce -- core Class of Service Expansion,
Cdp -- call Processing Engineered Parameters Table.
Chq -- program Generated Indicators.
Chg -- code Translation Information.
Cja -- originators Class of Service Data.
Cxd -- drum Tables CTT and CGT.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chg -- program Generated Indicators.
Chq -- code Translation Information
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C08X01 Scheduled by
module CO6 after a successful CTT or CGT drum translation. C08X01
is responsible for completely analyzing the retrieved information.
It determines whether to schedule module C06 for additional data
collection (e.g. collect additional digits and/or perform another
drum translation) or to schedule some other module for continuing
call processing or processing an error condition. C08X02 Scheduled
by module C06 when the PJR entailed no additional drum translations
(PJR = 0, 8, or 9). C08X02 ensures that all digits are received,
drops any TCMF receivers which might be connected, and schedules
the Tandem Screening Check program (module C12). 6.2 EXIT POINTS
Exit Points Reasons for Exit C06X01 Digit Translation
Initialization program: C06X01 is scheduled when additional digit
translations are required. C10X02 Route Translation Initialization
prgram: C10X02 is called by module C08 when a special three-digit
code is dialed which does not require charge analysis. It is also
called by module C08 when the call is to be terminated to an
intercept route. C12X01 Tandem Screening Check program: C12X01 is
given control by module C08 to determine if a call initiated by a
non-local subscriber is allowed by EAX. C31X03 Local Call
Processing Maintenance Program (LCPMP): This exit point is called
when module C08 encounters an error. A trouble index must be passed
in X2 for use in outputting the appropriate TTY message. For module
C08 the subscriber is given lockout via C26X04. F08X01 RS Access
program: This exit point is used for writing in RS memory. It also
has the capability to write and to read-modify-write.
7. SUBROUTINES USED -- None
8. NARRATIVE
8.1 discussion
module CO8 is responsible for analyzing the data retrieved from
drum (tables CTT/CGT) by module CO6. The functions performed by
module CO8 depend upon the PJR field. The PJR field is an indicator
of the last job run by module CO6.
Module CO8 sets up all the requirements for additional digit
analysis (schedules module CO6), or terminates digit analysis by
either routing to intercept or exiting to module C12. The above is
accomplished as a function of CID when PJR = 3. When module CO8
determines that additional analysis is required the RS is
initialized by setting the XTL and Fast Timeout (FTO) fields as
required. Module CO6 is then scheduled to run on a RS translation
interrupt and the NJR field can be set to a new value. Module CO8
also also performs special code checks on the inputting digits.
These checks include instructions to route call to intercept when
necessary. Certain digits may be deleted from the RS module CO8.
Data base checks are made on the PJR, NJR, and CID values. When any
of the values are invalid, module C31 is scheduled.
8.2 TECHNIQUE
When, during the analysis of CID, it is determined that all digits
were received (ADR = 1) and when no more translations are required
(NJR = 0), module CO8 terminates digit analysis by scheduling
module C12. However, if a TCMF receiver is attached to the call, it
must first be disconnected. This accomplished by giving the RS an
IN instructions (IN = 14) and setting CMD to 1. The Translation
Interrupt (TRI) issued by the RS (TRI = 7) causes the scheduling of
module CO6. Module CO6 uses the CMD = 1 instruction as an
indication to software idle the receiver then returns to module CO8
to conclude digit analysis. C.phi.9
1. name -- pattern Recognition Handler module.
2. PURPOSE
The Pattern Recognition Handler program (module CO9) is scheduled
to analyze and handle Register Sender (RS) translation interrupts
caused by the detection of specific digit patterns. Two digit
patters (0 and 11) are recognized by the RS and handled by module
CO9. A 9 pattern implies that the call is to be routed immediately
to an operator. A 11 pattern implies that a special three digit
service code is being dialed.
3. FUNCTIONS
Module CO9 performs the following functions:
a. Sets CHQRTO to equal to 3 and exits to the Route Translation
Initialization program (module C10) when Q+ dialing is not in
effect (CEPZPD = 0) and the first dialed digit is zero. This routes
the call to an operator trunk.
b. Outputs a warning message (data base error) on the Office
Teletypewriter (TTY) then routes the call as in function (a) when
0+ dialing is in effect (CEPZPD = 1) and the first dialed digit is
a zero. Module CO9 should not be entered under the above
conditions.
c. Schedules the Local Pretranslator program (module CO7) on a TRI
= 1 interrupt after three digits are received with 1+ dialing is in
effect (CEPOPD = 1) and the first two digits are ones. This pattern
specifics that a special code was dialed.
d. Outputs a warning message (data base error) on the office TTY
and routes the call as in function (c) for all other digit
patterns.
4. INPUTS
4.1 software
4.1.1 core Tables
Cce -- core Class of Service Expansion.
Cep -- engineered Office Parameters.
Cja -- original Class Data.
Fwb -- call Processing Register Sender Memory Image.
Fwb -- call Processing Register Sender Memory Imate
4.1.2 Drum Tables - None.
4.1.3 Registers - None.
4.2 HARDWARE - None
5. OUTPUTS
5.1 software
5.1.1 core tables
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables - None.
5.1.3 Registers - None.
5.2 HARDWARE - None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C09X01 C09X01 is
scheduled by the RS Translation Interrupt Analysis program (module
C11) when a Translation Interrupt (TRI=2) is detected in RS Memory
and the Pattern Recognition Field (PRF) is non-zero (i.e. a valid
TRI due to a desired digit pattern being recognized by the RS).
Upon entry CO9XO1 must have an image of RS Memory (i.e. the dialed
digits) in the Work Area (FWB). 6.2 EXIT POINTS Exit Points Reasons
for Exit C10X03 Route Translation Initialization programs. C01X03
is called from module C09 when the call is to be selectively routed
to an operator (subscriber dialed 0). F08X01 RS Access program:
F08X01 is used for writing in RS Memory. This exit point has the
capability to write and to read-modify-write. 7. SUBROUTINES USED
Entry Points Functional Names C31X03 Local Call Process Maintenance
Program (LCPMP-A). F08X01 Register Sender Write.
8. NARRATIVE
8.1 discussion
eax is designed to start processing a call as soon as the
Originating Marker (OM) detects an origination. After the
originating process (e.g. dial tone) call processing normally
ceases until three digits are received. Therefore, call processing
relinquishes control to the RS, expecting to regain control after
three digits are received. (XTL = IDC = 3 where XTL is the Totals
Instruction and IDC is the Incoming Digit Count).
However if a subscriber dials a 0 only (operator assistance), the
XTL = IDC mechanism does not function (XTL = 3, IDC = 1). This
situation may be handled by using the Fast Timeout (FTO) or Zero
Timeout (ZTO) mechanism of the RS. Using the timeout mechanism,
however, may cause an unnecessary four second delay. Therefore the
RS PRF mechanism is utilized in recognizing a first dialed digit of
0. The PRF is not to be used to recognize a 0 in an office allowing
0+ dialing. The ZTO mechanism is utilized for this situation. Upon
recognition of a desired pattern, the PRF mechanism generates an
immediate interrupt (TRI = 2), thus no time delay is
encountered.
Another situation requiring the use of the PRF mechanism is when
the office allows 1+ dialing and a subscriber dials a special
service code in the form 11X, where X is any number between 1 and
0. Upon recognition of 1 as the first digit (1+ dialing), the RA
Zero-One Code (ZOC) mechanism increments the XTL from three to
four. However a 11X code is not part of 1+ dialing and therefore
XTL should remain equal to 3. The RS PRF mechanism is therefore
utilized to inform call processing that 11 was dialed call
processing will set XTL back to three. Both of these situations
utilize the PRF mechanism to generate a TRI = 2 interrupt. This
interrupt is initiated while call processing waits for a TRI = 1
interrupt, and therefore module CO9 is required for processing
TRI=2 interrupts.
8.2 TECHNIQUE -- Not applicable.
C1.phi. -- figs. 80-80a
1. name -- route Translation Initialization Module.
2. PURPOSE
The Route Translation Initialization program (module C10) is
responsible for initiating the proper drum translation to retrieve
the information required for terminating a call.
3. FUNCTIONS
Module C10 performs the following functions:
a. Initiates a directory number translation when the call
terminates locally.
b. Initiates a route number translation when a directory number
translation is not required, and selective routing is not
indicated.
c. Performs selective routing when required for proper termination.
A Traffic Type Number (TTN) field is either passed to or
constructed by C10 for use in accessing the drum to perform
selective routing translations.
4 INPUTS
4.1 software
4.1.1 core Tables
Cep -- engineering Office Parameters.
Fwa -- executive Interface Work Area.
Chg -- code Translation Information.
Chq -- program Generated Indicators.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chg -- code Translation Information.
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C10X01 C10X01 is
entered to perform a directory, route, or selective route number
translation. The data which indicates which translation to perform
must be contained in overlay CHG of the Call History Table (CHT),
and normally would be set up by the digit analysis process. C10X01
determines which translation is required, initiates that
translation and schedules the Route Number and Directory Number
Translation program (module C15). C10X02 C10X02 is entered only to
initiate a route number translation. It initiates the drum
translation (table CRN), then schedules module C15. C10X03 C10X03
is called by the Tandem Screening Check program (module C12) when
an allowed extended Area Service (EAS) tandem call is being
processed and selective routing is being used. It is also called by
the Final Processor program (module C26) and the Pattern
Recognition Handler program (module C09) when the call is
selectively routed to an operator (subscriber dialed 0). C10X03
uses data contained in CHT tables CHG and CHQ to set up its search
key. Then it initiates a drum translation of table CSR via the Data
Manipulator program (module F35). Module C15 is scheduled upon a
successful translation. 6.2 EXIT POINTS Exit Points Reasons for
Exit F35X01 Data Manipulator (MANIP) program: Used by resident and
non-resident program to access drum memory.
7. SUBROUTINES USED -- None.
8. NARRATIVE
8.1 discussion
to successfully process a call, Call Processing software must first
retrieve termination information. This termination information is
required to instruct the terminating marker to complete the call.
The software retrieves this information using one of three
different methods.
Method 1 employs a Directory Number Translation, method 2 employs a
Route Number translation, and method 3 employs a Selective Route
Number translation. Logic is required in determining which one of
these methods to utilize when retrieving the termination
information.
Logic required to select the proper translation and initiate any
one of the three translations is grouped together. Since every call
must be terminated to some destination, it must pass through this
combined logic. The logic acts as an interface between the modules
which analyze the received digits and the modules which are
responsible for terminating the call. This logic is incorporated in
module C10.
C11 -- fig. 81
1. name -- register Sender Translation Interrupt Analysis
Module.
2. PURPOSE
The Register Sender Translation Interrupt Analysis program (module
C11) analyzes unexpected Register Sender (RS) Translation
Interrupts (TRI). When the unexpected interrupt definitely is an
error, the Local Call Processing Maintenance Program (module C31)
is scheduled to handle the error condition. All other interrupts
are either processed by module C11 directly, or transferred to
another Call Processing module for additional analysis.
3. FUNCTIONS
Module C11 performs the following functions:
a. The RS Access program (module F08) writes into RS Memory to
enable interrupts (CTR = 1) and releases the Work Area (WA) when
the RS is in the process of disconnecting the Register Junctor
(RJ). A CHQTIE of 6 indication implies that Call Processing is
waiting for a TRI of 6 response from the RS.
b. Branches to the Pattern Recognition Handler program (module C09)
to process a TRI = 2 interrupt when the digit pattern indicated by
the Pattern Recognition Field (PRF) in RS memory is recognized.
c. Utilizes the Sender Receiver Assigner program (module C27) to
idle the receiver and branches to module F08 when a TRI = 7
interrupt (sender or receiver has been disconnected) occurs and a
receiver is assigned to the call (CHQRSA = 1). Module F08 will
enable interrupts and release the work area.
d. Branches to module C31 for all other unexpected TRI interrupts
or when an error is encountered during the C27 access.
4. INPUTS
4.1 software
4.1.1 core Tables
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C11X01 C11X01 is
scheduled by the RS Interrupt Handler program (module F51) or
called by the Call Condition Analysis program (module C29) when the
TRI generated by the RS does not match the expected interrupt
indicated in CHQTIE. C11X01 handles the three non-error situations
described above by properly interfacing with the Pattern
Recognition Handler program (module C09) and module F08. When the
unexpected interrupt is an error condition, C11X01 passes control
to module C31 to format an error message on the Teletypewriter
(TTY) and provide lockout for the subscriber. 6.2 EXIT POINTS Exit
Points Reasons for Exit C09X01 Pattern Recognition Handler program:
C09X01 is called by module C11 when a TRI of 2 is detected in RS
Memory and the PRF is not zero (i.e. a valid TRI due to a desired
digit pattern being recognized by the RS). C31X03 Local Call
Process Maintenance Program (LCPMP): This exit point is called when
module C11 encounters an error. A trouble index must be passed in
X2 for use in outputting the appropriate TTY message. For module
C11 the subscriber is given lockout via C26X04. F08X01 RS Access
Program: This exit point is used for writing in RS Memory. It also
has the capability to write and to read-modify-write. 7.
SUBROUTINES USED Entry Points Functional Names C27X01
Sender/Receiver Assigner.
8. NARRATIVE
8.1 discussion
call Processing (CP) has a well defined interface with the RS
subsystem in order to permit CP to perform a variety of tasks. The
interface is designed to allow straightforward normal processing of
a call. This interface enables CP to instruct the RS to perform a
specific task, and when the task is completed, the RS returns a
unique indication to CP. CP can instruct the RS to perform two
separate tasks, such as instructions for returning to CP after
three digits are collected or if a 0 is the first dialed digit
(operator assistance).
For the above two tasks, CP sets up to expect the response of the
three digits dialed; therefore, when a 0 is the first digit dialed,
the response from the RS would be unexpected by CP. Module C11 was
designed specifically to handle unexpected responses from the RS
subsystem. Some unexpected RS responses are analyzed as legitimate
so CP can continue. However, some unexpected RS responses are
categorized and treated as errors.
8.2 TECHNIQUE
The only technique employed by module C11 is its ability to
distinguish between valid interrupts and definite error conditions.
Thus it is necessary to know which valid translation interrupts are
detected and/or processed by module C11 to fully understand how
unexpected RS responses are handled.
The CP originating process is set up to expect a TRI of 1
interrupt. This TRI occurs when the Incoming Digit Counter (IDC)
equals the Totals (XTL) value. A TRI of 2 interrupt, due to the
detection of a specified PRF digit pattern, is unexpected in normal
call processing. Two situations where a TRI=2 interrupt occurs are
when a 0 is detected as the first dialed digit (operator
assistance), or when a 11 is detected as the first and second
dialed digits (special service code form 11X, where X is any number
from 1 to 0). Module C11 transfers control to module C09 where
valid TRI = 2 interrupts are handled. A mixed line subscriber may
input either Dial Pulses (DP) or Touch Call Multifrequency (TCMF).
A TCMF receiver is therefore assigned to the call by the
originating process and the RS is instructed to accept either DP or
TCMF inputs. On detection of the first dialed digit from a rotary
dial handset, the RS drops the TCMF receiver and generates a TRI =
7 interrupt. The TRI = 7 interrupt informs CP that a receiver was
dropped. CP is expecting a TRI = 1 interrupt (XTL = IDC);
therefore, the TRI = 7 interrupt is unexpected. Module C11
processes the TRI = 7 interrupt by idling the receiver and enabling
the RS to generate another interrupt.
When module C11 determines that the unexpected interrupt occured
while the RS was disconnecting the RJ (expecting a TRI=6
interrupt), it will ignore the interrupt, thus enabling the RS to
complete disconnection of the RJ.
C12 -- fig. 82
1. name -- tandem Screening Check Module.
2. PURPOSE
The Tandem Screening Check program (module C12) determines if a
call from a non-local originator is to be routed to the dialed
destination or to intercept.
3. FUNCTIONS
Module C12 performs the following functions:
a. Exits to the Charge and Coin Box Analysis program (module C13)
when the call originates locally.
b. Accesses the Tandem Screening Matrix Table (CTS), for nonlocal
originations, to determine if the originator's dialed destination
is allowed. Table CTA is accessed using the Zone Associated With
the Class of Service field (ZCL) of the Originating Class of
Service table (CTN) and the Tandem Screening Zone field (ZTS)
associated with the dialed destination (tables CTT or CGT).
c. Exits to the Route Translation Initialization program (module
C10) with the Tandem Screening Intercept Route Number (CEPTSI) when
the originator's dialed destination is not allowed.
d. Exits to module C10 to perform the correct routing translation
when the dialed destination is allowed and Tandem Selective Routing
is not required (CHGTSR = 0).
e. Exits to module C10 to perform a selective route translation
when the dialed destination is allowed and Tandem Selective Routing
is required (CHGTSR = 0).
4. inputs
4.1 software
4.1.1 core Tables
Cce -- core Class of Service Expansion.
Cep -- engineering Office Parameters.
Cts -- tandem Screening Check.
Fjb -- base Level Junk Storage.
Chg -- code Translation Information.
Cja -- originating Class of Service Data.
Fwa -- executive Interface Work Area.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chg -- code Translation Information.
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C12X01 C12X01 is
entered after the completion of digit analysis to determine if a
non-local originator is allowed to terminate through the EAX. If
the origination is local, control of the call is passed to charge
analysis. 6.2 EXIT POINTS Exit Points Reasons for Exit C10X01 Route
Translation Initialization program: This exit point is used when a
directory, route, or selective route number translation is to be
performed. C10X02 Route Translation Initialization program: This
exit point is used only to initiate a route number translation.
C10X03 Route Translation Initialization program: This exit point is
called by module C12 when an allowed Extended Area Service (EAS)
tandem call is being processed and selective routing is being used.
C13X01 Charge and Coin Box Analysis program: This exit point is
used by module C12 when the origination is determined to be
local.
7. SUBROUTINES USED -- None.
8. NARRATIVE
8.1 discussion
when neither the origination nor the termination is local to the
EAX, the call is said to be tandeming through the EAX. Toll
tandeming traffic is not allowed by No. 1 EAX; only EAS tandem
traffic is permitted. EAS traffic is defined as local (free) or
Message Rate Service (MRS) calls origintaing within an EAS zone.
EAS traffic is different from toll traffic in that toll traffic can
only be switched through the toll network.
Module C12 is assigned the task of determining if the tandem calls
are allowed, by screening out all toll tandem calls.
8.2 TECHNIQUE
Call processing employs a matrix table (CTS) in performing the
tandem screening function. Table CTS is accessed utilizing two
indices (ZCL and ZTS). ZCL is used to categorize any non-local
originator into one of eight possible groups of originators (toll
and up to seven possible EAS zones). ZTS is used to categorize any
possible destination into one of eight possible groups of
destinations (local, toll, and up to six possible EAS zones).
Module C12 is designed to allow the call when the table CTS entry
for a given non-local originator (ZCL) and destination (ZTS) is 0.
When the entry is 1, the call is blocked (i.e. routed to
intercept).
As an example of how table CTS is engineered. Assume the EAX
(office code 859) is assigned a ZTS value of 0 (local
destinations). Assume that all toll originations and destinations
are assigned a ZCL value of 5 and a ZTS value of 6 respectively.
Finally, assume that two EAS offices are allowed to tandem calls to
one another through EAX. Office 673 is assigned values of 2 and 3
to ZCL and ZTS respectively. Office 492 is assigned values of 3 and
2 to ZCL and ZTS respectively.
In the above example it is noted that all non-local originations
attempting to terminate locally (ZTS = 0) are allowed. Also, all
toll tandem traffic is blocked (ZCL = 5 and ZTS = 6).
Office 492 is allowed to tandem to 673 and vice-versa; however,
office 492 is blocked from tandeming back to itself. This also
applies to office 673.
C13 -- figs. 83-83b
1. name -- charge and Coin Box Analysis Module.
2. PURPOSE -- The Charge and Coin Box Analysis program (module C13)
performs additional analysis for all locally originated calls. More
specifically, module C13 determines if a call is toll and if a coin
was deposited for paystation originations.
3. FUNCTIONS
Module C13 performs the following functions:
a. Determines if a call is toll by comparing the Zone Associated
with the Originator (ZCL) to the Zone Associated with the
Destination (ZNC) via the Check Zone Table (CCZ).
b. If the call is toll:
1. Determines if the office has a Local Automatic Message
Accounting (LAMA) ticketer.
2. Determines if the call is to be ticketed by LAMA via the Toll
Check Table (CTC).
3. sets a flag indicating that selective routing should be employed
when a call is to be ticketed by a non-EAX ticketing system.
4. Inhibits Early Outpulsing (EOP) when the call is to be ticketed
by Centralized Automatic Message Accounting (CAMA), Strowger
Automatic Toll Ticketing (SATT), or Traffic Service Position System
(TSPS).
5. interfaces with the Sender/Receiver Assigner program (module
C27) to software idle a receiver when one has been dropped, usually
after all the digits are received. This situation arises when EOP
is inhibited.
6. Determines if Incoming Wide Area Telephone Service (INWATS) is
being used, and if so, indicates that the call is to be traffic
sampled.
7. Retrieves the Foreign WATS state route number (CEPRNI) for
INWATS calls which have originated in the foreign WATS state.
8. Retrieves a route number, via the Separate Toll Routing Table
(CDR), for calls which are ticketed by EAX and are to be routed
differently than non-toll calls.
c. If the call is non-toll:
1. Routes the call to an intercept route number when the subscriber
is not following the prescribed dialing plan (1+ prefix). The check
for 1+ is made via the Extended Local Area Calling Service (ELACS)
Check Table (CEC) and is optional within the office.
2. Determines if the originator has Message Rate Service (MRS) when
an EAX ticketer is present.
3. Determines if the origination is a paystation.
4. Determines if paystation originators have deposited the proper
coin when a coin deposit is required.
5. Routes the call to an intercept when a paystation originator
fails to deposit the required coin.
6. Schedules C1OXO1 if a route number translation is to be
performed.
4. INPUTS
4.1 software
4.1.1 core Tables
Cce -- core Class of Service Expansion.
Ccz -- check Zone.
Cdr -- toll Destination Route.
Cec -- elacs check.
Cep -- engineering Office Parameters.
Chg -- code Translation Information.
Chq -- program Generated Indicators.
Cja -- originating Class of Service Data.
Ctc -- toll Check Table.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chg -- code Translation Information.
Chh -- route and Path Data.
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C13X01 C13X01 is
entered by the Tandem Screening Check program (module C12) after
Digit Analysis determines the route (as per dialed destination) and
determines if the call was locally originated. C13X01 performs all
the functions involved in determining if the call is toll, if a
LAMA ticketer is present, and for paystation originations, if a
coin was deposited. C13X02 C13X02 is scheduled internally by module
C13 through an interface with the Register Sender (RS). The RS will
reschedule C13 via this entry line when all digits have been
received. 6.2 EXIT POINTS Exit Points Reasons for Exit C10X01 Route
Translation Initialization program: C10X01 is used to perform a
directory, route, or selective route number translation. C10X02
Route Translation Initialization program: C10X02 is only used to
initiate a route number translation. C31X01 Local Call Process
Maintenance Program (LCPMP): This exit point is called when module
C13 encounters an error. A trouble index must be passed in X2 for
use in outputting the appropriate Teletypewriter (TTY) message. For
module C13, the subscriber is given lockout via C26X04.
Notes to FIGS. 83-83B.
1. chqlwa is still set up from previous c13xo2 entry.
2. prepare to drop receivers:
fwbxin .fwdarw. 14
fwbcmd .fwdarw.1
fwbxtl .fwdarw. 0
fwbctr .fwdarw. 1
chqtie .fwdarw. 7
xr2 .fwdarw. 9
c14 -- fig. 84
1. name -- directory Number Retrieval Module.
2. PURPOSE -- The Directory Number Retrieval Program (module C14)
retrieves the directory number of an originator, from drum
memory.
3. FUNCTIONS
Module C14 performs the following functions:
a. Determines if a directory number if available for a particular
origination by accessing the Directory Number Availablility Table
(CDA).
b. Determines whether or not the origination is from a Private
Automatic Branch Exchange (PABX), when a directory number is
available.
c. Determines what type of PABX billing is in effect, when a
directory number is available and origination is from a PABX.
d. Initiates a Line Number Identity (LNI) or a Trunk Number
Identity (TNI) to a directory number translation (table CDN or
CTD), when individual line or trunk directory billing is in effect
for the PABX, and a directory number is available.
e. Initiates a Published Directory Number Billing Group (PDG) to
directory number translation (table CGD), when published directory
number billing is in effect for the PABX and a directory number is
available.
f. Initiates a LNI to directory number translation (table CDN),
when the origination is not a PABX and a directory number is
available.
g. Places zeros in the calling directory number field when
directory numbers are not available for local originations.
Directory numbers will never be available for non-local
originations.
h. Sets a flag indicating that an attempt was made to retrieve a
directory number for a particular call. This flag ensures that
module C14 is entered no more than once for any given
origination.
i. Sets a flag indicating if the directory number is associated
with a Home Number Plan Area (HNPA) or a Foreign Number Plan Area
(FNPA).
4. inputs
4.1 software
4.1.1 core Tables
Cce -- core Class Of Service Expansion.
Chc -- originating Marker Data Frame Received.
Cja -- originating Class of Service Data.
Cxk -- drum Tables CTD, CDN, and CGD.
Fwa -- executive Interface Work Area.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chl -- ticketing Interface Data.
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C14X01 C14X01 is
called from the Termination cycle program (module C19) when the
directory number of the calling party is required for ticketing
purposes. C14X02 C14X02 is scheduled by module C14 upon a
successful completion of the drum translation to retrieve the
calling party's directory number. 6.2 EXIT POINTS Exit Points
Reasons for Exit C19X03 Termination Cycle program: C19X03 is used
as the return point into module C19 after module C14 has retrieved
the calling party'directory number. F35X01 Data Manipulator (MANIP)
program: Used by resident and non-resident programs to access drum
memory. 7. SUBROUTINES USED Entry Points Functional Names C29X01
Call Condition Analysis.
8. NARRATIVE
8.1 discussion
A toll or software controlled Message Rate Service (MRS) call
requires the unique identification of the originator for proper
ticketing. Without this identification, the operating company would
be unable to properly bill its customers. This unique
identification is the originator's directory number. EAX calls may
be ticketed by EAX or they may be sent to another office for
ticketing. In either case the directory number of the calling party
is required. EAX is designed for Automatic Number Identification
(ANI); therefore, operator intervention for retrieving the
originator's directory number normally is not required. However,
EAX cannot uniquely identify the originator if from a four-party
line; therefore, Operator Number Identification (ONI) is required
for this case.
Module C14 is assigned the task of retrieving the calling party's
directory number when it is available.
8.2 TECHNIQUE -- Not applicable.
C15 - figs. 85-85d
1. name -- route Number and Directory Number Translation
Module.
2. PURPOSE
The Route Number and Directory Number Translation program (module
C15) provides for the preliminary analysis of data retrieved from
drum memory after a route or directory number translation.
3. FUNCTIONS
Module C15 performs the following functions:
a. The following functions are performed for directory number
translations:
1. Routes calls to vacant terminal intercept (CEPVTI) when no
coincidence is found on drum or when the invalidity bit is set.
2. Initiates a route number translation when the data from drum is
not in line matrix format.
b. The following functions are performed for selective route number
translations:
1. Ensures that all digits are received before continuing the
termination process if the dialed code had indicated Early
Outpulsing (EOP) and the terminating data did not indicate EOP.
2. initiates the outputting of a warning (possible permanent
condition) message on the Teletypewriter (TTY) when selective
routing was due to a permanent or interdigital timeout, and the
call is not being routed to a permanent signal trunk.
c. The following functions are performed for alternate route
translations:
1. Ensures that all digits are received before continuing the
terminating process (delayed alternate route), of the alternate
route data indicates no EOP and the primary route indicates
EOP.
2. ensures that the alternate route does not point to reorder tone,
busy tone, or lockout (no need to wait for all digits) prior to
collecting any more digits.
d. Passes control to the appropriate module for processing when the
route number points to reorder tone, busy tone, or lockout for
route number, alternate route number and selective route number
translations.
e. The following functions are performed for all translations:
1. Places the called number and all pertinent termination data into
the Call History Table (CHT).
2. performs a blocking check to ensure the originator is allowed to
access the dialed destination. Routes the call to intercept when
the dialed destination is not allowed.
3. Formats the alternate route indicator (so it may be used at a
later time) when an alternate route is available to the desired
termination, the originator is allowed to use the alternate
termination route, and the alternate route is not cancelled
(overload condition).
4. Accesses the Alternate Route Control program (module C21) when
an alternate route timeout or retrial attempt is being
processed.
5. Initiates a routing translation to the reverting call circuit
(when required).
6. Passes control to the Selector Matrix Routing program (module
C16).
4. inputs
4.1 software
4.1.1 core Tables
Car -- line Alternate Route.
Cbc -- blocked Call Route.
Cbm -- blocking Matrix.
Cce -- core Class of Service Expansion.
Cdc -- digit to Ringing Code.
Cep -- engineering Office Parameters.
Chc -- originating Marker Frame Received.
Chh -- route and Path Data.
Chl -- ticketing and Interface Data.
Chq -- program Generated Indicators.
Cja -- originating Class of Service Data.
Cox -- (where X = A, B, I or O) -- Trunk Expansion Table.
Cra -- recorded Announcement.
Cxf -- drum Tables CRN and CDN.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chh -- route and Path Data.
Chq -- program Generated Indicators.
Cwb -- pretranslator Drum Table CPD.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C15X01 Scheduled
upon successful completion of all route number translations. C15X02
Scheduled upon successful completion of all directory number
translations. C15X03 Scheduled upon successful completion of a
selective routing translation. C15X04 Scheduled after successful
completion of an alternate route number translation. C15X05
Scheduled upon successful completion of a retrial or delayed
alternate route number translation. C15X06 Scheduled internally by
module C15 when a delayed alternate route is being processed and it
becomes necessary to drop all existing paths while waiting for all
digits to be received. C15X06 will be scheduled after the Register
Sender (RS) successfully drops all paths. 6.2 EXIT POINTS Exit
Points Reasons for Exit C16X01 Selector Matrix Routing program:
C16X01 is used by each call on its initial attempt to establish
selector matrix routing. C21X01 Alternate Route Control program:
C21X01 is used by module C15 after it determines that the route it
is processing is an alternate route, timeout or retrial. C26X02
Final Processor program: C26X02 is used when a call is terminated
by sending the subscriber reorder tone. C26X03 Final Processor
program: C26X03 is used when a call is terminated by sending the
subscriber busy tone. C26X04 Final Processor program: C26X04 is
used when a call is terminated by sending the subscriber lockout
reorder tone. C29X03 Call Condition Analysis program: C29X03 is
used to release the Work Area (WA) from the call, and check if
there are any unprocessed RS interrupts. C31X03 Local Call Process
Maintenance Program: This exit point is called when module C15
encounters an error. A trouble index must be passed in X2 for use
in outputting the appropriate TTY message. For module C15 the
subscriber is given lockout via C26X04. E01X06 DPU Scheduler
(RESKED) program: E01X06 is used to cause the DPU Scheduler to add
a run request to a queue. F08X01 RS Access program: F08X01 is used
for writing in RS Memory. This exit point has the capability to
write and to read-modify-write. F35X01 Data Manipulator (MANIP)
program: F35X01 is used by resident and non-resident programs to
access drum memory.
7. SUBROUTINES USED Entry Points Functional Names C16X06 Selector
Matrix Routing. C28X01 Call Processing Printout Control. F08X01 RS
Access.
8. NARRATIVE
8.1 discussion
the following discussion covers both modules C15A and C15B. EAX
routing capabilities are extremely complex: therefore it is
inconceivable to have all the termination data under one format and
in a common translation table. The termination data is therefore
stored in several different translation tables. Call Processing
accesses these translation tables for any of the following
situations:
a. Directory Number Translations (normal).
b. Route Number Translations (normal).
c. Selective Route Number Translations (normal).
d. Alternate Route Number Translations.
e. Delayed Alternate Route Number Translations.
f. Selective Route Number Translation due to a permanent or an
interdigital timeout.
g. Retrial Attempt -- Directory Number Translation.
i. Retrial Attempt -- Route Number Translation.
A slight difference in processing is required for each the above
situations.
Module C15 is designed to perform an initial analysis of the
termination data and prepare for the common processing of the
terminating process.
8.2 TECHNIQUE
One of the many functions of module C15 is to determine if the
originator is permitted to terminate to the dialed destination. If
termination is not permitted, the call is routed to an
intercept.
Module C15 employs the Blocking Matrix (CBM) table in determining
if a given call is allowed. The CBM table is accessed utilizing the
Originating Blocking Type (OBT) and Terminating Blocking Type (TBT)
as indices. OBT is associated with an originator and is obtained
from the originating common Class Of Service (COS) data. TBT is
associated with the dialed destination and is obtained from the
routing translation (termination) data.
Both OBT and TBT may range in value from 0 to 31, making table CBM
a 32 by 32 matrix. Each entry within CBM may range in value from 0
to 7. When the entry is CBM at the desired intersection of OBT and
TBT is 0, the call is allowed. When the CBM entry is non-zero, the
call is blocked.
In order that blocked calls be given the flexibility of being
routed to several different intercept routes, blocked entries in
CBM may specify values from 1 to 7. This value is then utilized as
an index in the Blocked Call Route (CBC) table. Table CBD is then
used to retrieve one of seven possible intercept routes.
An example of the OBT-TBT blocking mechanism in use is when a
Private Automatic Branch Exchange (PABX) subscriber wants all
non-local calls blocked. For this particular situation a unique OBT
value is assigned to the PABX inlets. Table CBM is engineered to
block all calls whose TBT values indicate a non-local termination.
The intercept route can be to an operator or special recorded
announcement.
C16 -- figs. 86-86b
1. name -- selector Matrix Routing Module.
2. PURPOSE -- The Selector Matrix Routing program (module C16)
provides a means for systematically determining paths from the
Selector Group Inlet 7 (SGI) to the Selector Group Outlet (SGO).
The paths are chosen on the basis of the number of Terminating
Marker (TM) accesses required in the termination of the call.
3. FUNCTIONS
Module C16 performs the following functions:
a. Determines if an insertion junctor (annoyance call, block answer
supervision or section) is required.
b. Limits the total number of junctor hook-ups and restricts the
order in which the junctors are connected when insertion junctors
are required.
c. Determines the SGO for each unique insertion junctor and final
path required to complete the call.
1. Accesses table CTI to select a unique insertion junctor and
Terminating Trunk Group Number (TGN). The final path TGN value is
obtained from the routing data (tables CRN and CDN).
2. accesses table COX utilizing the TGN value to select the
appropriate SGO in order to complete the loop through the Selector
Matrix (SMX).
d. Establishes the final path through the SMX for alternate routes
when only the final loop is required.
e. Initiates an Originating junctor (OJ) translation (table CLO)
for all calls which originate on Line Matrix (LMX) equipment. This
determines the SGI for the first loop. This translation is
performed only once for a given call.
f. Passes the SGI of the origination and the SGO information of
each path to be pulled through the SMX to the Termination Cycle
program (module C19) to provide interface with the TM.
g. Initiates a trunk Message Rate Service (MRS) scan point
translation (table CSM) for all incoming MRS), Private Branch
Exchange (PBX), or Private Automatic Branch Exchange (PABX) trunks.
This translation is performed only once for a given call.
h. Informs the ticketing subsystem of new originations and passes
the OJ or trunk ticketing scan point to ticketing.
i. Determines if the trunk groups selected are Balanced Oversized
Trunk Groups (BOT). When BOT equals 1 it allows selection of a TGN
group based on a random indicator.
j. Transfers control (after performing OJ or trunk translations) to
module C19 for all line terminations (CXFLXT = 1), and to the Route
Number Expansion Analysis program (module C17) for all trunk
terminations (CXFLXT = 0).
4. inputs
4.1 software
4.1.1 core Tables
Cce -- core Class of Service Expansion.
Cep -- engineering Office Parameters.
Chc -- originating Marker Data Frame Received.
Chq -- program Generated Indicators.
Cox (=a,b,i,o) -- trunk Expansion Tables.
Cja -- originating Class of Service Data.
Cta -- trunk Group Number Access.
Cti -- trunk Group Number for Insertion Junctors.
Cwb -- termination Set-Up and Control Work Area.
Cxj -- drum Table CSM.
Cxh -- drum Table CLO.
Cxf -- drum Tables CRN and CDN.
Fwa -- executive Interface Work Area.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chh -- route and Path Data.
Chl -- ticketing Interface Data.
Chq -- program Generated Indicators.
Cwb -- termination Set-up and Control Work Area.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register/Sender Memory Image.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C16X01 is used by
each call on its initial attempt to establish SMX routing. C16X02
is entered on alternate routes when only the final SMX path needs
to be pulled. C16X03 is scheduled by the Data manipulator program
(module F35) after a successful return from a CLO drum translation
for retrieval of OJ SGI and MRS information. C16X04 is entered on
alternate routes when a path is already pulled and an insertion
junctor might be required. C16X05 is scheduled by module F35 after
a successful return from a CSM drum translation of MRS scan point
information. C16X06 is used to access core table COX for retrieval
of SGO data for each path pulled through the SMX. 6.2 EXIT POINTS
Exit Points Reasons for Exit C17X01 Route Number Expansion Analysis
program: C17X01 is branched to upon exit from module C16 when the
call is to terminate on a selector matrix outlet. C19X01
Termination Cycle program: C19X01 is used when the TM is required
to pull a path through the network. C31X03 Local Call Process
Maintenance Program: C31X03 is called when module C16 encounters an
error. A trouble index must be passed in X2 for use in outputting
the appropriate Teletypewriter (TTY) message. For module C16 the
subscriber is given lockout via C26X04. F35X01 Data Manipulator
(MANIP) program: F35X01 is used by resident and nonresident
programs to access drum memory. 7. SUBROUTINES USED Entry Points
Functional Names C16X06 Selector Matrix Routing. F08X01 Register
Sender Access. T01X01 Ticketing Strings.
8. NARRATIVE
8.1 discussion
as a part of the terminating process, Call Processing must
establish certain paths or loops through the SMX. This provides
intermediate distribution of the traffic from various trunks and
junctors on the SMX inlets, to various trunks and junctors on the
SMX outlets. The paths pulled through the SMX provide access to one
of a group of outlet equipment.
Module C16 is designed to set up these paths through the SMX.
Module C16 first must determine the type and quantity of insertion
junctors required. The three types of insertion junctors are:
1. Block Answer Supervision (BASJ).
2. annoyance Call Junctor (ACJ).
3. section Junctor (SJ).
No more than two insertion junctors are allowed on any one call;
thus no more than three paths can be pulled through the SMX (two
insertion junctor paths plus the final path to the Terminating
Junctor (TJ) or outgoing trunk). Because of the various functions
performed by insertion junctors, the order of their hook-up is
restricted. Following is a list of insertion junctors in the order
of hook-up (when two junctors are required):
CALL TYPE A CALL TYPE B CALL TYPE C (1) SJ (1) BASJ (1) ACJ (2)
BASJ (2) ACJ (2) SJ
To select an appropriate junctor and retrieve its TGN value, table
CTI is accessed when it is determined that an insertion junctor is
required. This TGN value is then used to access table COX (where X
= A,B,0, or 1) in order to obtains the SGO information. The SGO
data defines a subset of outlets on the C-matrix which the TM may
use to pull a path through the SMX. One of the many functions of
module C16 is in the order of insertion junctor hook-up.
Module C16 establishes the SGO information for all paths (including
the final path which connects to a TJ or outgoing trunk) required
for a particular call. Data defining the SGI for the first loop of
line originations is retrieved from drum translation table CLO. For
trunks there is a one to one relationship between incoming trunks
and selector matrix inlets thus requiring no drum translation in
C16 for SGI data. All of this data (SGI and SGO) is then passed to
the TM enabling the actual paths to be pulled by the hardware.
When the origination is a MRS trunk, module C16 performs a CSM drum
table translation in order to retrieve the MRS scan point for the
ticketing subsystem. The ticketing subsystem is also passed scan
point data from all OJ's which have MRS scan points.
For line terminations module C16 passes control to module C19 to
allow the pulling of the paths via the TM. For trunk terminations
control is passed to module C17 where sending requirements are
processed.
8.2 TECHNIQUE
Module C16 uses a special technique in its selection of trunk
groups when the TGN is set up as Balanced Oversize. Normally each
TGN has access of up to 80 outlets of the SMX. In some instances it
is desirable to provide access to additional SMX outlets. For
illustration purposes assume an office experiences a large amount
of traffic between office sections 1 and 2, thus requiring more
than 80 SJ's to handle the load.
One solution to the above problem is to use BOT alternate routing.
Using BOT, the SJ's are equally divided into two separate trunk
groups. When a SJ is required, the associated TGN is indicated as
BOT and module C16 randomly selects one of the two SJ groups. If
the first selection cannot be accessed, the second trunk group is
accessed via the internal alternate routing feature.
When module C16 performs a COX table access to retrieve SGO
information, it checks to see if the trunk group is BOT, then it
selects one of the trunk groups based on a random indicator.
Notes to fig. 86
1. this is an alternate route with a path already pulled. a bas,
acj, dr sj may be needed.
2. ir(x) .fwdarw. 0 bits 0-1
ir(x) .fwdarw. chcsec bits 2-3.
3. ir(x) .fwdarw. chcsec bits 0-1
ir(x) .fwdarw. cwbtsc bits 2-3.
4. ir(x) .fwdarw. chcsec bits 0-1
ir(x) .fwdarw. chcsec bits 2-3.
notes to fig. 86a
1. indicate last loop switching digits have been set up.
2. ir(x) .fwdarw. 0 bits 0-1
ir(x) .fwdarw. cwbtsc bits 2-3.
c17 -- fig. 87 - 87a
1. name -- route Number Expansion Analysis Module.
2. PURPOSE -- The Route Number Expansion Analysis program (module
C17) analyzes the termination routing data, for Selector Matrix
termination, to determine if the Register Sender (RS) is to be
initialized to allow Early Outpulsing (EOP) or Multifrequency (MF)
sending.
3. FUNCTIONS
Module C17 performs the following functions:
a. Ensures that the RS stopped collecting digits (XFD = 1) and
exits to the Termination Cycle program (module C19) when sending is
not required for the termination.
b. Ensures that the RS stopped collecting digits (XFD = 1) and
exits to module C19 when Dial Pulse (DP) sending is required and
EOP is not required.
c. Initializes the RS for EOP and exits to module C19 when DP
sending in the EOP mode is required. However, if an alternate route
is being processed such that the RS has already been set up for
EOP, C17 simply exits to module C19.
d. Attaches a MF Sender, when required, and schedules module C19 to
be run after the RS successfully completes the connection. However,
if an alternate route is being processed such that a MF sender is
already attached, simply exits to module C19.
4. inputs
4.1 software
4.1.1 core Tables
Chq -- program Generated Indicators.
Cwa -- sender/Receiver Assigner Interface.
Cwb -- termination Set-up and Control Work Area.
Cxf -- drum Tables CRN and CDN.
Fwa -- executve Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE
5. outputs
5.1 software
5.1.1 core Tables
Chh -- route and Path Data.
Chl -- ticketing Interface Data.
Chq -- program Generated Indicators.
Cwa -- sender/Receiver Assigner Interface.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C17X01 Branched to
upon exit from the Selector Matrix Routing program (module C16)
when the call is to terminate on the Selector Matrix. C17X02
Entered after the Sender/Receiver Assigner program (module C27)
obtains an idle, on-line, assigned MF sender. 6.2 EXIT POINTS Exit
Points Reasons for Exit C19X01 Termination Cycle program: C19X01 is
called by module C17 when the Terminating Marker (TM) is required
to pull a path through the Selector Matrix. C29X04 Call Condition
Analysis program: C29X04 is used to check for unprocessed RS
interrupts; control is released to the Exec; however, the Work Area
(WA) is attached to the Call History Table (CHT) to allow it to be
available for later use. C31X03 Local Call Process Maintenance
Program: C31X03 is called when module C17 encounters an error. A
trouble index must be passed in X2 for use in outputting the
appropriate Teletypewriter (TTY) message. For module C17, the
subscriber is given lockout via C26X04. 7. SUBROUTINES USED Entry
Points Functional Names C27X01 Sender/Receiver Assigner. F08X01
Register Sender Access. M09X01 Call Event Metering.
8. NARRATIVE
8.1 discussion
information sent to another office from an EAX office may be in one
of four different possible sending modes. These modes are listed as
follows:
1. DP without EOP.
2. dp with EOP.
3. mf.
4. a combination of DP and MF.
The EOP and MF modes require special considerations in the Register
Sender (RS) subsystem.
Module C17 was designed to analyze the termination data associated
with Selector Matrix Terminations to enable proper initialization
of the RS.
8.2 technique
module C17 employs a technique which is similar to the Originating
Class of Service program (Module C02). Module C17 utilizes module
C27 to obtain an idle, assigned, and on-line MF sender. A MF sender
must be connected to the call before proceeding with call
processing when non-local terminations require MF sensing. Module
C17 utilizes module C27 in making a single attempt to obtain a MF
sender. If an attempt fails, module C17 initiates a Sender/Receiver
timing mechanism in RS Memory and returns control to module C27
where continuous attempts are made to obtain a MF sender. If a MF
sender is obtained, module C17 continues its processing. However,
if a sender cannot be obtained, the timer runs out causing a RS
system trouble interrupt. Thus each call is given the greatest
possible opportunity to obtain the required MF sender.
Notes to fig. 87
1. this program gets control only on selector matrix outlet
termination (cxflxt .noteq. 1) and when all digits are received
except with eop and all recvrs disconnected.
2. fwbeop .fwdarw. 1; fwbctr .fwdarw. 1; chhrep .fwdarw. 1; chqtov
.fwdarw. 3 (c26x06); chqtie .fwdarw. 0; chqlwa .fwdarw. 0; ir2
.fwdarw. 16.
3. return address +0
4. return address +1
sender - assigned.
notes to fig. 87a
1. rst = 0 -- rtf is illegal or rst = 2 -- r/s is invalid.
2. attempt cont. until a sender is found. if a sender is not found,
a time-out will occur.
c19 -- figs. 88-89
1. name -- termination Cycle Module.
2. PURPOSE -- The Termination Cycle program (module C19) prepares
terminating information for the Register Sender (RS) and
Terminating Marker (TM). The TM utilizes the termination
information to establish connections through the network (selector
and line matrices). The RS utilizes the termination information to
time the terminating opertion.
3. FUNCTIONS
Module C19 performs the following functions:
a. Prepares routing and control information used by the
Communications Control Register (CCR) and the TM.
b. Retrieves the calling party's directory number, when
required.
c. Determines if a ticketing study is to be performed.
d. Determines sending requirements when sending is required.
e. Indicates that the TM Response Analysis program (module C24) is
to be scheduled by the CCR interrupt processor after the TM
operation is completed.
f. Indicates that the TM Response Analysis program (module C24) is
to be scheduled by the CCR interrupt processor after the TM
operation is completed.
g. Initiates scheduling a TM time via the CCR Handler program
(F32).
4. inputs
4.1 software
4.1.1 core Tables
Cce -- core Class of Service Expansion.
Ccp -- corrector and Pad Control.
Cct -- cut-Through Table.
Chh -- route and Path Data.
Chq -- program Generated Indicators.
Cha -- originating Class of Service Data.
Cox -- (where X = A, B, I, or 0) -- Trunk Expansion Table.
Cwb -- termination Set-Up and Control Work Area.
Cxf -- drum Tables CRN and CDN.
Cxn -- drum Table CSX.
Fwa -- executive Interface Work Area.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chl -- ticketing Interface Data.
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
Fwd -- terminating Marker Sent Information.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C19X01 Entered when
a path is to be pulled through the Selector Matrix (SMX). C19X01
may be entered from the Selector Matrix Routing program (module
C16) for pulling the first path, or from the TM Call Complete
Process program (module C25) for pulling the second and third
paths. The Route Number Expansion Analysis program (module C17)
schedules C19X01 after connecting a sender. Module C24 calls C29X01
when using internal alternate routing. C19X02 The return point into
module C19 after the Sending Patterns and Format Control program
(module C20) has completely initialized the RS for any sending
requirements. C19X03 The return point into module C19 after the
Directory Number Retrieval program (module C14) retrieves the
calling party's directory number. 6.2 EXIT POINTS Exit Points
Reasons for Exit C14X01 Directory Number Retrieval program: C14X01
is called from module C19 when the directory number of the calling
party is required for ticketing purposes. C20X01 Sending Pattern
and Format Control program: C20X01 is used when the final loop of
the call is ready to be pulled and sending is required for the
termination. C31X03 Local Call Process Maintenance Program (LCPMP):
C31X03 is called when module C19 encounters an error. A trouble
index must be passed in X2 for use in outputting the appropriate
Teletypewriter (TTY) message. For module C19 the subscriber is
given lockout via C26X04. E01X06 Data Processor (DPC) Scheduler
(RESKED) program: E01X06 is used to cause the DPU Scheduler to add
a run request to a queue. F31X01 CCR Scheduler (MARKER) program:
F31X01 is used by any program desiring communication with any party
of the Communication Register/Marker subsystem. 7. SUBROUTINES USED
Entry Points Functional Names C16X06 Selector Matrix Routing.
C29X01 Call Condition Analysis. F08X01 RS Access.
8. NARRATIVE
8.1 discussion
eax requires a minimum of one end and a maximum of three paths
through the network to process any call. Characteristics of the
origination and termination are utilized in determining the actual
number of paths required. There is a maximum of three loops per
call: one loop for the destination and two intermediate loops. The
intermediate loops consist of circuits which are inserted into the
call path. These circuits are listed below:
1. Annoyance Call Junctor (ACJ).
2. block Answer Supervision Junctor (BASJ).
3. section Junctor (SJ).
Module C19 was designed to interface with the TM to allow the
pulling of paths through the SMX. Module C19 pulls only one path at
a time and is re-entered until all the required paths are pulled
(initial analysis of the termination data has determined which
paths are necessary).
8.2 TECHNIQUE
Module C19 must prepare the Trunk Control (TKC) field for passage
to the TM via the TM data frame. The TKC field is utilized by the
TM to control the switching of outgoing trunk corrector and pad
circuits. Corrector circuits are a part of all trunk circuits and
are used to match impedance between switching equipment (e.g. match
line originations to trunk terminations). Pad circuits may
optionally be a part of a trunk circuit and are used to control the
quality of trunk transmission. Origination and termination
characteristics determine which circuit (pad or corrector) is to be
switched into a call.
The Originating Corrector Indicator (OCI) and the Originating Pad
Indicator (OPI), defined by the originators class of service data,
indicate whether a corrector or pad is to be associated with the
origination (e.g. incoming trunk circuit). Similarly, the
Terminating Corrector Indicator (TCI) and the Terminating Pad
Indicator (TPI), defined by the terminating class of service data,
indicate whether a corrector or pad is to be associated with the
termination (e.g. outgoing trunk circuit). Module C19 combines
these four one-bit indicators together to form an index into core
table CCP. This index is used to retrieve the appropriate TKC
value.
C20 -- fig. 90
1. name -- sending Patterns and Format Control.
2. PURPOSE -- The Sending Pattern and Format Control program
(module C20) prepares the called number, calling number, and prefix
digit storage cells in Register Sender (RS) Memory to meet the
requirements of the receiving office. The call termination sending
data, contained in the Route Number Expansion Table, is used to
prepare the prefix digit storage cells. RS sending control
information, contained in the termination data, is passed to the
RS.
3. functions
module C20 performs the following functions:
a. Deletes from RS Memory the number of called digits specified by
the termination data.
b. Modifies the Incoming Digit Count (IDC), Totals (XTL), and Fast
Timeout (FTO) fields in RS memory when the called digits are
deleted from RS Memory in the Early Outpulsing (EOP) mode.
c. Inserts the Key Pulse (KP), Start (ST), and Class of Service
(CSD) digits as specified by the termination data.
d. Inserts the calling directory number and prefix digits as
specified by the termination data.
e. Passes to the RS the sending control information as specified by
the termination data.
f. Transfers control to the Termination Cycle program (module C19)
when all processing is complete.
4. INPUTS
4.1 software
4.1.1 core Tables
Chl -- ticketing Interface Data.
Cxf -- drum Tables CRN and CSR.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chl -- ticketing Interface Data.
Chq -- program Generated Indicators.
Fwb -- call Processing Register Sender Memory Image.
Fwa -- executive Interface Work Area.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C20X01 Entered by
module C19 when the final loop is ready to be pulled and it is
determined that sending to the termination is required. 6.2 EXIT
POINTS Exit Points Reasons for Exit C19X02 Termination Cycle
program: C19X02 is the return point into module C19 when module
C20completely initializes the RS for any sending requirements. 7.
SUBROUTINES USED Entry Points Functional Names F08X01 RS Write
8. NARRATIVE
8.1 discussion
eax must be able to interface with all types of offices; therefore,
the sending patterns of EAX must conform to the receiving
requirements of the particular receiving office. To satisfy these
sending requirements, the RS subsystem provides three digit bins
for storage of digits which are to be outpulsed (e.g. called
number, calling number, and prefix digit bins). Each of these bins
may be sent in Dial Pulse (DP) or Multifrequency (MF) mode. Any
combination of 1, 2, or 3 of these bins may be outpulsed on any
given call. This feature of the RS, in conjunction with software
manipulation of digits in the bins, makes EAX completely flexible
in its sending capabilities.
The route number expansion data associated with a termination
uniquely specifies the sending requirements since each non-local
termination may require different sending requirements from EAX.
Module C20 performs an analysis of the termination data in order to
initialize the RS for sending to the desired termination.
8.2 TECHNIQUE -- Not applicable.
Notes to fig. 90
1. initialize digit formatting fields.
2. store st digit and do not update idc.
3. f08 deletes and adds digits in rs, modifying idc according to
del and adg values.
c21 -- figs. 91 - 91d
1. name -- alternate Route Control (ARC).
Notes to fig. 91a
1. fwbxin .fwdarw. 6; fwbctr .fwdarw. 1;
ir2 .fwdarw. 15; chqtie .fwdarw. 7;
chqlwa .fwdarw. 8 (c21x02);
fwbeop .fwdarw. 0.
2. fwbxin .fwdarw. 5; fwbctr .fwdarw. 1;
ir2 .fwdarw. 15; chqtie .fwdarw. 8;
chqlwa .fwdarw. 10 (c16x01);
fwbeop .fwdarw. 0. 3. fwbxin .fwdarw.6; fwbctr .fwdarw.1;
ir2 .fwdarw. 15; chqtie .fwdarw. 8;
chqlwa .fwdarw. 10 (c16x01);
fwbeop .fwdarw. 0.
notes to fig. 91b
1. ir2.fwdarw.15;chqtie.fwdarw.7;
chqlwa.fwdarw.5(<21x04).
2. three loops were to be pulled in one of three junctor
configurations:
acj-sj: or BASJ-ACJ: OR SJ-BASJ.
3. only the first junctor was pulled in one of the three
configurations above.
4. sj-basj were to be pulled.
5. basj-acj were to be pulled.
6. acj-sj were to be pulled.
notes to fig. 91c
1. two junctors were pulled in one of the three following
configurations: acj-sj; or basj-acj; or sj-basj.
2. sj-bas was pulled.
3. bas-acj was pulled.
4. acj-sj was pulled.
notes to fig. 91d
1. do not reset xin = 6.
rs will reset.
c24 -- figs. 92-94
1. name -- terminating Marker Response Analysis Module.
2. PURPOSE -- The Terminating Marker (TM) Response Analysis program
(module C24) determines the next course of action to be taken by
Call Processing upon analyzing the call-status-response. The
call-status-response is sent to the Data Processor by the TM.
3. functions
module C24 performs the following functions:
a. Turns control over to the Call Condition Analysis program
(module C29) if an unprocessed Register Sender (RS) interrupt has
occurred.
b. Determines if the TM termination effort was successful.
c. Stops RS timing of the TM operation for all unsuccessful
termination attempts and successful terminations to intermediate
loops (insertion junctors).
d. Initiates a drum translation to retrieve the Selector Group
inlet (SGI) identify of the junctor and schedules the TM Call
Complete Process program (module C25) upon successful termination
to an insertion junctor.
e. Passes control to module C25 upon successful termination to the
final loop of a call.
f. Performs the following functions for unsuccessful TM termination
attempts:
1. Interfaces with the metering subsystem.
2. Determines if there is an alternate trunk group or an alternate
route associated with the termination. If so, prepares to access
the alternate termination.
3. Passes control to the Final Processor program (module C26) when
an alternate route is not available or when the alternate
termination is not to a Selector Matrix (SMX) termination (i.e.
reorder tone).
4. Interfaces with the Call Processing Printout Control program
(module C28) when an attempt was made to terminate to a permanent
signal trunk.
4. INPUTS
4.1 software
4.1.1 core Tables
Cce -- core Class of Service Expansion.
Cep -- engineering Office Parameters.
Cha -- scheduling Information.
Chh -- route and Path Data.
Chl -- ticketing Interface Data.
Cja -- originating Class Of Service Data.
Cox -- (where X = A, B, I, or 0) -- Trunk Expansion Table.
Cwb -- termination Set-Up and Control Work Area.
Cxn -- drum Table CSX.
Fwa -- executive Interface Work Area.
Fwc -- terminating Marker Received Information.
Fwd -- terminating Marker Sent Information.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chh -- route and Path Data.
Chl -- ticketing Interface Data.
Chq -- program Generated Indicators.
Cwb -- termination Set-Up and Control Work Area.
Cxn -- drum Table CSX.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables - None.
5.1.3 Registers - None.
5.2 HARDWARE - None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C24X01 Scheduled by
the Communications Control Register (CCR) Handler program (module
F32) upon completion of a TM operation requested by Call
Processing. 6.2 EXIT POINTS Exit Points Reasons for Exit C19X01
Termination Cycle program: C19X01 is used when a path is pulled
through the SMX. Module C24 calls C19X01 when using internal
alternate routing. C25X01 Terminating Marker Call Complete Process
program: C25X01 is called by module C24 after the final loop of the
call is set-up. C26X02 Final Processor Program: C26X02 is called by
module C24 when reorder tone is to be returned to the originator.
C26X03 Final Processor program: C26X03 is called by module C24 when
busy tone is to be returned to the originator. C26X04 Final
Processor program: C26X04 is called by module C24 when lockout is
to be returned to the originator. C31X03 Local Call Processing
Maintenance program (LCPMP): C31X03 is called when module C24
encounters an error. A trouble index must be passed in X2 for use
in outputting the appropriate Teletypewriter (TTY) message. For
module C24 the subscriber is given lockout via C26X04. F35X01 Data
Manipulator (MANIP) program: F35X01 is used by resident and
nonresident programs to access drum memory. 7. SUBROUTINES USED
Entry Points Functional Names C16X06 SMX Routing. C28X01 Call
Processing Printout Control. C29X01 Call Condition Analysis. C31X03
LCPMP. F08X01 RS Write. M03X01 Overflow Metering. M05X04 Call Event
Metering -- Termination to Busy Lines. M05X05 Call Event Metering
-- Busy Paths -- Selector Group Outlets and Called Line. M05X06
Call Event Metering -- Busy Paths -- Selector Group Outlets and
Terminating Junctor. M05X08 Call Event Metering -- Blocked Selector
Group Matrix Connections. M06X01 Grade of Service Metering. M06X02
Grade of Service Metering. M09X03 Call Event Metering -- Blocked
Terminations to Trunk Group.
8. NARRATIVE
8.1 discussion
when the call processing software requests the TM to pull a path
through the switching network, an idle network path existing to the
desired termination cannot be guaranteed. The TM will inform the
call processing software of the status of the attempted network
path. There are only four network conditions belonging to Call
Processing. These conditions are listed as follows:
1. The network path was successfully connected.
2. The network path was not set-up because the called line is
busy.
3. The network path was not set-up because a blockage condition
exists (all paths busy) in the network.
4. A line circuit fault was encountered while connecting a path to
a line.
Module C24 analyzes the TM response data and determines the next
job Call Processing should perform. For network condition (1), Call
Processing continues the normal process of the call. For network
condition (2), an attempt to terminate to an alternate line (if one
is available) is initiated. For network condition (3), an attempt
to terminate to either an alternate trunk group or an alternate
termination (if either is available) is initiated. For network
condition (4) a warning message is output on the TTY for office
maintenance use, then the termination process continues
normally.
Due to metering subsystem requirements, the TM not only informs
Call Processing about a blockage, it also isolates the location of
the blockage to a specific area of the network. Module C24
therefore acts as a task dispenser to the appropriate metering
modules, depending upon the area of the network where the blockage
occurred.
8.2 TECHNIQUE -- Not applicable.
C25 -- figs. 95-95a
1. name -- terminating Marker (TM) Call Complete Process
module.
2. PURPOSE -- The TM Call Complete Process program (module C25)
determines the correct cut-through to be performed for the call,
then initiates the Register Sender (RS) cut-through function. Upon
completion of every call, the RS cuts-through the incoming trunk or
Originating Junctor (OJ) circuit to release RS control of the call.
For line terminations the Terminating Junctor (TJ) takes control of
the call. For trunk terminations the RS performs sending, allowing
another office to take control of the call.
3. FUNCTIONS
Module C25 performs the following functions:
a. Determines the appropriate cut-through type for the call, then
initiates the RS cut-through function when all required Selector
Matrix (SMX) loops are set up.
b. Resets the Message Rate Service (MRS) indicator when the
termination is free, to prevent ticketing of the call.
c. Initiates a Teletypewriter (TTY) warning message when the call
is terminated to a permanent signal trunk.
d. Performs a translation to retrieve the ticketing scan points
associated with a trunk when termination is to a ticketable trunk.
Also informs the ticketing subsystem of the trunk seizure.
e. Returns to the Termination Cycle program (module C19) to pull
another path through the SMX when only an intermediate loop was
connected.
f. Interfaces with the metering subsystem for all completed loops
and terminations.
g. Initiates the appropriate routing translation to begin the
terminating process for retrial and delayed alternate route
processing.
4. INPUTS
4.1 software
4.1.1 core Tables
Cce -- core Class of Service Expansion.
Ccp -- corrector and Pad Control.
Cct -- cut-Through Table.
Cep -- engineering Office Parameters.
Chc -- originating Marker Data Frame Received.
Chh -- route and Path Data.
Chl -- ticketing and Interface Data.
Chq -- program Generated Indicators.
Cha -- originating Class of Service Data.
Cox -- (where X = A,B,I, or 0) -- Trunk Expansion Table.
Cwb -- termination Set-Up and Control Work Area.
Cxf -- drum Tables CRN and CDN.
Cxn -- drum Table CSX.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
Fwc -- terminating Marker Received Information.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chh -- route and Path Data.
Chl -- ticketing and Interface Data.
Chq -- program Generated Indicators.
Cwb -- termination Set-Up and Control Work Area.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
Fwc -- terminating Marker Received Information.
Hti -- in Test Table.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C25X01 C25X01 is
called by the TM Response Analysis program (module C24) after the
final loop is set up. C25X01 also interfaces with the ticketing and
metering subsystems. C25X02 C25X02 is scheduled by module C24 when
an insertion junctor is successfully connected and a CSX
translation was performed. C25X03 C25X03 is scheduled internally by
module C25 upon completion of a drum translation (table CSX).
C25X04 C25X04 is entered when a call processing retrial is to be
performed or scheduled after all digits are collected on a delayed
alternate route. 6.2 EXIT POINTS Exit Points Reasons for Exit
C19X01 Termination Cycle program: C19X01 is used when a path is to
be pulled through the SMX. - C29X03 Call Condition Analysis
program: C29X03 is used to release the Work Area (WA) when there
are no unprocessed RS interrupts. C31X03 Local Call Process
Maintenance Program (LCPMP): C31X03 is called when module C25
encounters an error. A trouble index must be passed in X2 for use
in outputting the appropriate TTY message. For module C25 the
subscriber is given lockout via C26X04. F35X01 F35X01 is used by
resident and non-resident programs to access drum memory. 7.
SUBROUTINES USED Entry Points Functional Names C16X06 SMX Routing.
C28X01 Call Processing Printout Control. F08X01 RS Access During
Normal Processing. M04X01 Call Routing Metering. M05X03 Call Event
Metering -- Termination to Idle Lines. M05X07 Call Event Metering
-- Successful Selector Group Matrix Connections. M09X02 Call Event
Metering -- Successful Terminations to Trunk Group. T01X02
Ticketing Strings.
8. NARRATIVE
8.1 discussion
upon detection of an origination, the Originating Marker (OM)
connects the call to the RS subsystem. The RS then acts as an
interface between the originator and the call processing software.
Call Processing informs the RS that it is ready to receive digits;
then the RS returns dial tone to the subscriber. The RS collects
digits dialed by the subscriber; then passes them to call
processing for analysis. This two-way communication is necessary
while Call Processing is analyzing the dialed digits and attempting
to terminate the call to the intended destination. After the
terminating paths are set up by Call Processing, the RS equipment
is no longer required to control the call.
To drop the RS equipment from a call the RS performs a cut-through
function on the incoming trunk circuit or originating junctor. This
cut-through function connects the call through the SMX paths set up
by call processing; then the RS is dropped from the call path. When
the call terminates locally, control is given to the Terminating
Junctor (TJ). The TJ provides ringing of the called subscriber and
ringback tone to the calling subscriber. When the call terminates
to a trunk, the RS performs sending over the trunk before being
disconnected; then control is given to another office.
The cut-through function also controls the switching of pad and
corrector circuits in the incoming trunk circuits, controls coin
collection of paystations (OJ's only), and controls pegging of MRS
hardware meters (OJ's only).
Module C25 determines the particular cut-through function which is
appropriate for the call in progress, then initiates RS processing
of the cut-through function. For completed terminations module C25
interfaces with the metering subsystem.
8.2 TECHNIQUE
The cut-through function, denoted by the software as a Cut-Through
Type (CCT), controls the switching of pad and corrector circuits on
incoming trunk circuits. Pad circuits are used to control the
quantity of a trunk's transmission and optionally may be part of a
trunk circuit. Corrector circuits are used to match impedance
between switching equipment, and are part of all trunk circuits
(e.g. match trunk origination to line termination). Origination and
termination characteristics determine which circuit (pad or
corrector) is to be switched into a call.
The Originating Corrector Indicator (OCI) and the Originating Pad
Indicator (OPI), defined by the originator's class of service data,
indicate whether a corrector or pad is to be associated with the
origination (e.g. incoming trunk circuit). Similarly, the
Terminating Corrector Indicator (TCI) and the Terminating Pad
Indicator (TPI), defined by the terminating class of service data,
indicate whether a corrector or pad is to be associated with the
termination (e.g. outgoing trunk circuit). Module C25 combines
these four one-bit indicators together to form an index into core
table CPP. This index is used to retrieve the appropriate CCT
value.
C26 -- figs. 96-96c
1. name -- final Processor module.
2. PURPOSE -- The Final Processor program (module C26) performs all
processing required to release a call from the EAX common
control.
3. FUNCTIONS
Module C26 performs the following functions:
a. When a Call Abandon (CAB) occurs:
1. Interfaces with the Markers/Network Maintenance Strings program
(module K07).
2. provides the appropriate cut-through for coin refund when a
paystation origination is being handled.
3. Inhibits ticketing interface with the EAX Local Automatic
Message Accounting (LAMA) ticketing facility.
4. Disconnects a sender or receiver when one is associated with the
call.
5. Disconnects the Register Junctor (RJ) associated with the
call.
b. When a Translation Interrupt of 6 occurs (TRI = 6):
1. interfaces with the Sender/Receiver Assigner program (module
C27) to idle the Sender/Receiver (S/R) when a sender or receiver is
associated with the call.
2. Interfaces with the S/R Status program (module C34) placing the
sender or receiver off-line (maintenance request).
3. Interfaces with the ticketing subsystem when required. Also
retrieves a spare Work Area (WA) when ticketing interface is
required.
4. Interfaces with the Call Processing Printout Control program
(module C28) when an annoyance call printout is required.
5. Resets certain items in the Call History Table (CHT) associated
with the call in progress.
6. Clears the RJ Memory Slot associated with the call in
progress.
7. Places the RJ in an off-line state (by maintenance request).
8. Returns the RJ to an idle state.
(c) When reorder or busy tone is returned to the subscriber:
1. Inhibits ticketing interface with the EAX LAMA ticketing
facility.
2. Prepares to drop all terminating paths associated with the call
in progress.
3. Prepares to drop a sender or receiver (when one is assigned to
the call) and sets up to expect a TRI = 7 interrupt.
4. Generates busy tone from the RJ when required.
5. Generates reorder tone from the incoming trunk circuit when
required for trunk group matrix originations.
6. Generates reorder tone from the RJ when required for line matrix
originations.
7. Prepares for the occurrence of reorder or busy tone timeout.
d. When a reorder or busy tone timeout occurs (TRI = 6):
1. prepares to route the call to a permanent signal trunk (line
matrix originations).
2. Interfaces with module C28 to output a timeout message (trunk
group matrix originations).
3. Generates reorder tone from the trunk circuit for trunk group
originations.
(e) When a TRI of 7 occurs:
1. Interfaces with module C27 in order to idle the S/R.
2. prepares for the occurrence of reorder or busy tone timeout.
Also enables Register Sender (RS) interrupts (CTR = 1).
f. When a timeout occurs:
1. Allows normal call processing to continue (e.g., ignores the
timeout) when a TRI of 6 is expected or when all digits are
received and Finish Dial (FD) indication is not written into RS
Memory.
2. Sets the All Digits Received indicator to 1 (ADR = 1) and
inhibits any Early Outpulsing (EOP = 0).
3. returns lockout reorder tone when the subscriber is a Wirechief
(WC), Trunk Test Access (TTA), or a Communication Line (CL).
4. returns lockout reorder tone and outputs an error message when
digit reception is in the Multifrequency (MF) mode.
5. Determines if a Zero Timeout (ZTO) occurred. Also sets a flag
indicating selective routing for ZTO calls.
6. Determines if a permanent or interdigital timeout occurred for a
line matrix organization. If so, a flag is set to indicate that
selective routing of a call is required.
7. Determines if a permanent or interdigital timeout occurred for a
trunk register matrix organization. If so, a flag is set to
indicate that selective routing of a call is required.
g. When lockout reorder tone is returned to the subscriber:
1. Prepares the proper cut-through type to be given to the RC as a
function of the origination.
2. Inhibits interfacing with the EAX LAMA ticketing facility.
3. Prepares to drop any terminating paths (if set up), a S/R (if
attached), and the RJ associated with the call.
4. Initiates the generation of reorder tone from the Originating
Junctor (OJ) or incoming trunk circuit.
h. When a fast timeout (FTO) occurs for a call in the EOP mode:
1. Transfers control to the Terminating Marker Call Complete
Process program (module C25) when a delayed alternate route is
being processed.
2. Writes FD into RS memory to complete cut-through of the EOP
call.
4. INPUTS
4.1 software
4.1.1 core Tables
Cce -- core Class of Service Expansion.
Cct -- cut-Through Table.
Cep -- engineered Office Parameters.
Chc -- originating Marker Data Frame Received.
Chl -- ticketing Interface Data.
Chm -- call History Maintenance Table.
Chq -- program Generated Indicators.
Cja -- originating Class of Service Data.
Ctk -- ticketing Interface Allowed.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chh -- route and Path Data.
Chq -- program Generated Indicators.
Cwa -- sender/Receiver Assigner Interface.
Cwb -- termination Set-Up and Control Work Area.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C26X01 Scheduled
for any of the following RS interrupts: 1. Call Abandoned (CAB). 2.
Interdigital, or permanent, or zero timeout. 3. TRI = 5. 4. TRI =
6. 5. TRI = 7. C26X02 Scheduled when reorder tone is returned to
the subscriber from the RJ. C26X03 Scheduled when line busy tone is
returned from the RJ to the subscriber. C26X04 Scheduled to
"lockout" a given line or trunk (e.g. return lockout reorder tone
from the OJ or incoming trunk circuit). C26X05 Scheduled to
disconnect a RJ from a call and to idle it (clear the RS Memory).
C26X06 Scheduled upon a FTO interrupt after all digits are input in
the EOP mode. 6.2 EXIT POINTS Exit Points Reasons for Exit C10X02
Route Translation Initialization Program: C10X02 is used only to
initiate a route number translation. C10X03 Route Translation
Initialization program: C10X03 is used by module C26 when a call is
selectively routed to an operator (subscriber dialed 0). C19X01
Termination Cycle program: C19X01 is used when a path is to be
pulled through the Selector Matrix (SMX). C24X01 Terminating Marker
Response Analysis program: C2401 is used to direct call processing
depending on the response data received from the Terminating Marker
(TM). C29X04 Call Condition Analysis program: C29X04 is used when
it is desirable to have the Call Condition Analysis program (module
C29) save the WA by hitching it to the CHT if a RS interrupt has
not occurred. C31X03 Local Call Processing Maintenance Program
(LCPMP): C31X03 is used when module C26 encounters an error. A
trouble index must be passed in X2 for use in outputting the
appropriate Teletypewriter (TTY) message. F08X01 Register Sender
Access During Normal Processing program: F08X01 is used for writing
in RS Memory, and has the capability to write and to read
modify-write. 7. SUBROUTINES USED Entry Points Functional Names
C27X01 Sender/Receiver Assigner C28X01 Call Processing Printout
Control C34X05 Sender/Receiver Status F04X01 Work Area Assignment
(WASPAR) F08X01 Register-Sender Access During Normal Processing
K07X01 Call Abandon Rate Counter T02X01 Ticketing Strings
8. NARRATIVE
8.1 discussion
when the final routing of a call is determined and all paths are
set up, the common control software (e.g. Call Processing) has
essentially completed its processing of the call. The final
function of Call Processing is to release the common control
equipment (the RJ and possibly a sender or receiver) so that it can
be used by another call. Module C26 performs all the functions
necessary to release a call from the common control equipment.
For most calls (calls with terminating paths through the SMX), the
cut-through function of the RS is performed before entry to module
C26. For these calls, module C26 simply idles the common control
equipment and interfaces with the ticketing subsystem (when
required).
For calls which terminate by providing subscriber lockout or by
dropping the connection, the appropriate cut-through function is
initiated in the RS by module C26. The common control equipment is
then released from the call. This applies to CAB's and calls which
require lockout recorder tone from the OJ or trunk circuit.
When reorder or line busy tone is to be returned by the RJ as part
of the final termination of the call, the RJ cannot immediately be
idled because it is required to generate the appropriate tone to
the subscriber first. Module C26 initiates the generation of a
reorder or a line busy tone by the RJ, and waits for a CAB
(subscriber hangs up) before idling the RJ and releasing control of
the call. A timeout occurs when the subscriber fails to abandon the
call. In processing reorder or line busy tone timeouts, module C26
routes line originations to a permanent signal trunk and provides
lockout to trunk originations.
8.2 TECHNIQUE -- Not applicable.
Notes to fig. 96c
1. tri = 7 interrupt processing.
c27 -- figs. 97-97c
1. name -- sender Receiver Assigner Module.
2. PURPOSE -- The Sender/Receiver (S/R) Assigner program (module
C27) is designed to function as a closed subroutine, maintaining
the busy/idle status, and monitoring the assigned/unassigned,
on-line/off-line status of all senders and receivers. Module C27
provides for the software assigning and/or idling of all required
senders and receivers.
3. FUNCTIONS
Module C27 performs the following functions:
a. Returns to the calling program via an error return when the
Route Flag (RTF) is invalid (RTF = 3 or RTF>5). An error
indicator (RST) is set to zero when an illegal Route Flag is
encountered. The S/R Assigner field (RSA) is set to zero indicating
that this particular S/R is not assigned to any call.
b. While initiating one attempt in selecting an idle, on-line, and
assigned Sender or Receiver:
1. Determines which type of Sender or Receiver is required via the
Assigned Matrix Outlet Group (AOG).
aog = 1: touch Call Multifrequency (TCMF) Receiver.
AOG = 2: Multifrequency (MF) Receiver.
AOG =4: Multifrequency (MF) Sender.
2. Sets RST equal to 2 indicating an invalid AOG, and returns to
the calling program via an error return when one of the three types
of S/R's cannot be located.
3. Makes one attempt to select an idle, on-line, and assigned
Sender or Receiver. When the desired unit is found, it is marked as
busy (in the Busy-Idle table) and the unit's address is placed in
the SRA field in one of three core tables depending on the type
sender/receiver selected (table CBR for MF receivers, table CBS for
MF senders, table CMR for TCMF receivers) and also in the work area
field FWBSRA). The RSA field is set to one indicating the S/R is
assigned to a call. Register A is set positive, and is used as a
success indicator in returning control to the calling program.
4. Sets Register A negative (error indication) when the desired
unit is not located. Module C27 returns to the calling program with
one of the following error trouble indications:
CWARST = 0 -- RTF is illegal.
CWARST = 1 -- All assigned S/R's are busy and/or off-line.
CWARST = 2 -- AOG field is invalid.
c. When RTF equals 2:
1. Makes continuous attempts to select an idle, on-line, and
assigned S/R (RTF is internally set to 1).
2. Marks the unit busy in the Busy-Idle tables and places its
address in the SRA field in one of three core tables depending on
the type of S/R selected (table CBR for MF receivers, table CBS for
MF senders, table CMR for TCMF receivers) and also in the work area
(field FWBSRA) when the desired unit is found.
3. Sets Register A positive (success indication), and returns
control to the calling program when the S/R is located.
4. Causes a Register Sender (RS) System trouble indication when a
timeout occurs and the S/R is not located.
d. Makes continuous attempts to obtain an idle, on-line, and
assigned S/R when RTF equals 1. The continuous attempts are
performed in association with a S/R Timing mechanism located in RS
Memory. A timeout will occur if the desired S/R is not obtained.
(RTF is set to 1 on the first timing attempt, when RTF = 2).
e. When RTF = 4 or 5:
1. Determines if the S/R is assigned and busy. When the S/R is both
assigned and busy, and if RTF = 4, module C27 marks the S/R as idle
(in the S/R tables and in RS Memory). RSA is set to zero indicating
that this particular S/R is not assigned and Register A is set
positive (success indication) prior to returning to the calling
program.
2. Marks the S/R as idle (in the S/R tables) without affecting RS
Memory (e.g. the S/R is software idled only), when the S/R is both
assigned and busy and RTF = 5. Processing then continues as in
function (e) 1.
3. Marks the S/R as idle and on-line (in the S/R tables) and sets
RST to 4 to indicate that the S/R is not assigned to the Register
Junctor (RJ) when the S/R is found to be unassigned. RSA is set to
zero indicating the S/R is not assigned to any call. Register A is
set negative as an error indication prior to returning to the
calling program.
4. Sets RSA to 3 indicating the S/R is already in the idle state,
when S/R is found to be idle. RSA is set to zero and the A Register
is set negative prior to returning control to the calling
program.
4. INPUTS
4.1 software
4.1.1 core Tables
Cbr -- busy Idle Table For Multifrequency Receivers.
Cbs -- busy Idle Table for Multifrequency Senders.
Cbt -- busy Idle Table For Touch Call Multifrequency Receivers.
Ccw -- call Processing Counts of Work Areas on the Timer Queue for
Sender/Receiver Timing.
Cep -- engineered Office Parameters.
Chq -- program Generated Indicators.
Cmr -- on-/Off-Line Multifrequency Receivers.
Cms -- on-/Off-Line Multifrequency Senders.
Cmt -- on-/Off-Line Touch Call Multifrequency Receiver.
Ctp -- pointers To Sender/Receiver Assignment Table.
Cwa -- drum Table CDN.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
4.1.2 Drum Tables - None.
4.1.3 Registers - None.
4.2 HARDWARE - None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Cbr -- busy Idle Table for Multifrequency Receivers.
Cbs -- busy Idle Table for Multifrequency Senders.
Ccw -- call Processing Counts of Work Areas on the Timer Queue for
Sender/Receiver Timing.
Cmr -- on-Line/Off-Line Table for Multifrequency Receivers.
Chq -- program Generated Indicators.
Cwa -- drum Table CDN.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register/Sender Memory Image.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry E02X02 Internal
Timer Request Acceptor program: E02X02 is used to cause requests
for timing of specific time intervals to be added to the
Executive's timer queue. 6.2 EXIT POINTS Exit Points Reasons for
Exit C26X04 Final Processor Module: C26X04 is used to provide
lockout to those calls requesting a continuous attempt at finding
an idle, on-line, and assigned sender/receiver when the call is not
allowed to be placed on the exec timer queue. 7. SUBROUTINES USED
Entry Points Functional Names C29X01 Call Condition Analysis.
F08X01 Register Sender Write.
8. NARRATIVE
8.1 discussion
module C27 is used by various programs within the EAX system for
two basic purposes: (1) software assignment and/or idling of all
senders and receivers; (2) for maintenance of the software sender
and receiver busy/idler status table.
An access to module C27 is initiated when Call Processing requires
the call be assigned a sender or receiver. Module C27 initiates a
single attempt in obtaining a receiver. If this attempt fails,
module C27 is instructed to continue making attempts to obtain a
receiver until either one is found or a timeout occurs.
Module C27 may also be called to idle a given sender or receiver.
The sender or receiver is marked as idle (in the S/R status tables)
and the RS Memory is modified unless the calling program requested
only software idling (RTF = 5). For this situation, modification of
the RS Memory is by-passed.
8.2 TECHNIQUE
Module C27 employs a technique in the assignment of idle, on-line,
and assigned receivers to call originations in the Originating
Class Of Service Analysis program (module C02). When an origination
occurs which requires the assignment of a receiver, module C02
calls module C27 (RTF = 0). Module C27 then initiates a single
attempt in obtaining the required receiver. If this attempt fails,
module C27 returns control to module C02 with an appropriate error
indication.
Module C02 initiates a S/R timing mechanism in RS Memory and
instructs module C27 to begin a continuous search for an idle,
on-line, and assigned receiver (RTF = 2). The search continues
until either a receiver is obtained or the timer runs out, causing
a RS System trouble indication. Utilizing this technique, the
subscriber is afforded the best possible chance in obtaining the
required receiver.
Before initiating this S/R timing mechanism, however, C27 will
determine if the work area associated with the call is allowed to
be placed on the exec timer queue for S/R timing. When RTF=2, C27
will determine the type of work area associated with the call.
Then, depending on the type of work area, C27 will check a counter
(CCWS26 or CCWS38) to determine how many work areas of that type
are currently on the timer queue for S/R timing. C27 will then
compare this counter with a parameter in table CEP which specifies
the maximum number of work areas of that type allowed to be placed
on the exec timer queue. If the counter is less than the parameter
value, the work area will be allowed to be placed on the timer
queue. If the counter is greater than or equal to the parameter
value, the work area will be not be allowed to be placed on the
timer queue and C27 will send the call to lockout.
For those calls allowed to be placed on the timer queue, before
placing the work area on the timer queue, C27 will increment the
appropriate counter indicating how many work areas of that type are
on the timer queue for S/R timing.
For calls coming off the timer queue, C27 will determine the type
of work area associated with the call and then decrement the
appropriate counter indicating how many work areas of that type are
on the timer queue for S/R timing.
Another technique employed by C27 is the particular method used in
selecting an idle, on-line and assigned sender/receiver. When
called to obtain a sender/receiver, C27 will determine the
particular type of sender/receiver requested. Then depending on the
type of sender/receiver requested, C27 will access one of the three
core tables (CBR for MF receivers, CBS for MF senders, CMR for TCMF
receivers) to obtain the identity of the last used sender/receiver
of the type requested. This identity will be contained in the SRA
field of the core table accessed. C27 will then start searching for
a sender/receiver of the type requested from the location of the
last used sender/receiver plus one. When C27 finds an idle,
on-line, and assigned sender/receiver of the type requested, it
will place the identity in the SRA field of the appropriate core
table as mentioned above (table CBR for MF receivers, table CBS for
MF senders, table CMR for TCMF receivers). This technique of
sequential searching allows for equal use of all senders/receivers
in an office.
C28 -- fig. 98
1. name -- call Processing Printout Control Module.
2. PURPOSE -- The Call Processing Printout Control program (module
C28) is responsible for storing the information required for
annoyance and timeout printouts in a spare Work Area (WA). This
information is then passed to the Call Processing Format and Print
program (module C30) for message formatting.
3. FUNCTIONS
Module C28 performs the following functions:
a. Determines if the printout required is the result of a timeout
or an annoyance call.
b. Determines, for timeout printouts, if call processing timeout
printouts were disabled (FPICPP = 1). When disabled, the printout
is suppressed and control is returned to the calling program.
c. Determines, for a call requiring an annoyance printout, if a
timeout occurred. When a timeout occurs, the annoyance printout is
suppressed and control is returned to the calling program.
d. Attempts to retrieve a spare WA when a printout is to be
initiated. Only one attempt is initiated unless the printout is for
an annoyance origination or termination. When this situation
occurs, two separate attempts are initiated to obtain spare
WA's.
e. Stores in the new WA (CWC) all the data from the original WA and
Call History Table (CHT) necessary to format and print the message
via the Teletypewriter (TTY).
f. Schedules module C30 to format the printout message.
4. INPUTS
4.1 software
4.1.1 core Tables
Cce -- core Class of Service Expansion.
Chc -- originating Marker Data Frame Received.
Chh -- route and Path Data.
Chl -- ticketing Interface Data.
Chq -- program Generated Indicators.
Cja -- originating Class of Service Data.
Cwb -- termination Set-Up and Control Work Area.
Erc -- real Time Clock Storage.
Fpi -- printout Inhibit Items.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register-Sender Memory Image.
Fwc -- terminating Marker Received Information.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Cwc -- call Processing Printout Format Work Area Table.
Fwa -- executive Interface Work Area.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C28X01 Is called as
a subroutine when a timeout or annoyance printout is required. 6.2
EXIT POINTS Exit Points Reasons for Exit PGRTRN Is used to return
control to the calling program. 7. SUBROUTINES USED Entry Points
Functional Names E01X01 ACCEPT -- Data Processing Unit (DPU)
Scheduler. F04X01 WASPAR -- Work Area Assignment.
8. NARRATIVE
8.1 discussion
tty messages are provided to maintenance personnel when EAX
encounters certain error conditions. EAX also provides Call
Processing printout messages indicating timeouts and annoyance
calls. A timeout indicates that a line or trunk allowed too much
time between the digits input, or the subscriber failed to abandon
his call after receiving reorder or busy tone. An annoyance
printout provides information about originations or terminations
suspected of initiating or receiving annoying calls, respectively.
Module C28 is scheduled when a Call Processing Printout (CPPR)
message is required. The printout may either be a timeout or an
annoyance call message.
When a timeout printout is required, module C28 checks if Call
Processing printouts are disabled. When printouts are disabled
(FPICPP = 1), the printout is suppressed and control is returned to
the calling program. Printouts are also suppressed when the
printout is an annoyance call and a timeout occurred.
Once it is determined that a printout is to be initiated, module
C28 makes a single attempt to obtain a spare WA. If this attempt
fails, control is returned to the calling program. When a printout
is required for an annoyance originator or terminator, two attempts
are initiated to obtain spare WA's (one attempt for each message).
Module C28 moves all the information required to format and print
the message (via the TTY) into the new WA. Module C28 schedules
module C30 to format the printout after all the information is
retrieved and stored in the spare WA.
8.2 technique -- not applicable.
C29 -- fig. 99-99a
1. NAME -- Call Condition Analysis Module.
2. PURPOSE -- The Call Condition Analysis program (module C29)
determines if a Register Sender (RS) interrupt occurred during an
interval where immediate processing of the interrupt was
undesirable. Module C29 also determines what action to take as a
function of the interrupt detected.
3. FUNCTIONS
Module C29 performs the following functions:
a. Utilizes the THISPG macro, when entered via entry line C29X03 or
C29X04, to indicate that module C29 has control of the Work Area
(WA) (FWATPF = C29).
b. Returns to the calling program if a RS interrupt has not
occurred and the program in control of the WA is not module C29
(FWATPF does not equal C29).
c. Exits to the Data Processing Unit (DPU) Scheduler (RELEASE)
program (module E01) to release the WA if a RS interrupt has not
occurred and module C29 was entered via entry line C29X03.
d. Exits to module E01 (TIME) to allow for "next program"
scheduling, on expected Translation Interrupts (TRI's), if a RS
interrupt has not occurred and module C29 was entered via entry
line C29X04. The WA is hitched to and will not be released from the
Call History Table (CHT)(CHAHPB = 1). Program scheduling is enabled
by setting the Inhibit Program Scheduling (IPS) field to zero
(CHQIPS = 0).
e. Calls the Final Processor program (module C26) when a Call
Abandon (CAB) interrupt occurs. Before going to module C26,
interrupts are enabled and entry line C29X05 is called as a
subroutine to obtain a current image of RS Memory and to clear out
the previous interrupt (CHACCM = 0).
f. Performs the following functions when a RS timeout interrupt
occurs:
1. Calls module C26 if the timeout is not a fast timeout (FWBFTO =
0) and a 38-word WA is currently used. When the current WA is not a
38-word type, it is dropped after obtaining a spare 38-word WA.
Module C26 is then called.
2. Returns to the calling program when the timeout is a Fast
Timeout (FTO), and module C29 is not in control of the WA (FWATPF
does not equal C29); i.e., FTO is either set to 15 or is equal to
the Incoming Digit Counter (IDC).
3. exits to module E01 (TIME) when a FTO timeout occurs and module
C29 was entered via entry line C29X04 (i.e., FTO is either set to
15 or it is equal to IDC). This exit hitches the WA to the CHT
before going to the Executive for additional scheduling.
4. Schedules the next program to be run (drum resident programs) or
branches to the next program to be run (core resident programs)
when a FTO timeout occurs and module C29 was entered via line
C29C03 (FWATEL = 3). The next program is obtained from table FTT
utilizing CHQTOV as an index. Entry line C29X05 is called as a
subroutine to obtain a current image of RS Memory, and to reset the
RS interrupt indicator (CHACCM = 0) in the CHT.
g. Calls the RS Translation Interrupt Analysis program (module C11)
when a TRI is received which does not match the value of the
Translation Instruction Expected (TIE) field (unexpected TRI).
Interrupts are enabled and entry line C29X05 is called as a
subroutine to obtain a current image of RS Memory, and to clear out
the previous interrupt (CHACCM = 0).
h. Returns to the calling program when a TRI interrupt is received
which matches the TIE, and module C29 is not in control of the WA
(FWATPF does not equal C29).
i. Schedules the next program to be run (drum resident programs) or
branches to the next program to be run (core resident programs) as
a result of the TRI interrupt, when a TRI interrupt is received
which matches the TIE and module C29 is in control of the WA. The
next program is obtained from table FTE utilizing CHQLWA as an
index. Entry line C29X05 is called as a subroutine to obtain a
current image of RS Memory, and to clear out the previous interrupt
(CHACCM = 0).
j. Reads RS Memory words 1A, 2A, 4A, 6A, and 6B to obtain a current
image of RS Memory when entry line C29X05 is called as a
subroutine. Clears out the previous interrupt indicator (CHACCM =
0) in the CHT and places this data in FWBCCM to be used by other
programs.
4. INPUTS
4.1 software
4.1.1 core Tables
Cha -- scheduling Information.
Chq -- program Generated Indicators.
Eps -- executive Parameters Storage Table.
Esl -- executive Storage Logic Table.
Fte -- expectant TRI Schedule Table.
Ftt -- tmo scheduling Table.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Cha -- scheduling Information.
Chq -- program Generated Indicators.
Eps -- executive Parameters Storage Table.
Esl -- executive Storage Logic Table.
Fwa -- executive Interface Work Area.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C29X01 Scheduled
when it is desirable to have module C29 return directly to the
calling program if an RS interrupt has not occurred. C29X02
Scheduled internally when a WA overload condition is encountered
while attempting to obtain a spare 38-word memory (e.g., the S/R is
software idle only), when the S/R is in the WA via the WASPAR
subroutine (F04X01). C29X03 Scheduled when it is desirable to have
module C29 release the WA if a RS interrupt has not occurred.
C29X05 Scheduled internally as a subroutine in order to obtain a
current image of RS Memory and to clear out the previous interrupt
in RS Memory. 6.2 EXIT POINTS Exit Points Reasons for Exit C11X01
Register Sender Translation Interrupt Analysis program: C11C01 is
called by module C29 when the TRI generated by the RS does not
match the TIE field. C26X01 Final Processor program: C26X01 is used
when a CAB or timeout occurs to complete or abort the call. E01X03
Data Processing Unit (DPU) Scheduler (RELEASE) program: E01X03 is
used to inform the DPU Scheduler that the current job is finished.
E01X04 DPU Scheduler (TIME) program: E01X04 is used when the WA is
hitched to the CHT after no interrupts are detected. E01X06 EPU
Scheduler (RESKED) program: E01X06 is used to cause the DPU
Scheduler to add a run request to a queue. 7. SUBROUTINES USED
Entry Points Functional Names C29X05 Call Conditioning Analysis.
F04X01 WASPAR -- Work Area Assignment. F05X01 WADROP -- Work Area
Return. F08X01 Register Sender Access During Normal Processing.
8. NARRATIVE
8.1 discussion
the EAX software does not know when a subscriber will abandon his
call, or when the RS will return after collecting the required
digits. Therefore, an interrupt mechanism (actually a software
scanning of sense lines) is utilized to notify the software of
these events as they occur, to initiate the necessary
processing.
Normally, interrupts are processed as soon as they occur.
Processing an interrupt during certain intervals would be
impractical. The system could be in the process of a drum
translation when a subscriber abandons his call. In this situation
it is desirable to wait until the translation is complete before
processing the CAB.
Module C29 is designed to check for the occurrence of RS interrupts
during intervals where immediate processing is undesirable and to
schedule, as a function of the interrupt detected, the appropriate
jobs for additioal processing.
8.2 TECHNIQUE -- Not applicable.
C30 -- fig. 100-100a
1. name -- call Processing Format and Print module.
2. PURPOSE -- The Call Processing Format and Print program (module
C30) is responsible for formatting annoyance and timeout printouts
using the information gathered by the Call Processing Printout
Control program (module C28). Module C30 schedules the Output
Message and Print program (module F07) when a message is to be
output on the Teletypewriter (TTY).
3. functions
module C30 performs the following functions:
a. Attempts to obtain a spare Work Area (WA). If an overload
condition occurs, module C30 is rescheduled. This second WA (one
work area is provided by module C28) is required because the
message is in two parts.
b. Determines which type of printout is desired: annoyance
origination, annoyance termination, or timeout (e.g, busy tone,
reorder tone, interdigital or permanent).
c. Formats the data into the WA, one WA for each of the two message
parts.
d. Passes the formatted data to module F07 for outputting via the
TTY.
4. inputs
4.1 software
4.1.1 core Tables
Cwc -- call Processing Printout Format Work Area Table.
Fwa -- executive Interface Work Area.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1. core Tables
Cwc -- call Processing Printout Format Work Area Table.
Fwa -- executive Interface Work Area.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C30X01 Scheduled by
module C28 when a timeout or annoyance printout is required. 6.2
EXIT POINTS Exit Points Reasons for Exit E01X03 Data Processing
Unit (DPU) Scheduler (RELEASE) program: E01X03 is used to inform
the DPU Scheduler that the current job is completed. E01X06 DPU
Scheduler (RESKED) program: E01X06 is used to cause the DPU
Scheduler to add a run request to a queue. 7. SUBROUTINES USED
Entry Points Functional Names E01X01 ACCEPT -- DPU Scheduler.
F05X01 WADROP -- Work Area Return. 8.
8.1 DISCUSSION
EAX has the capability of informing maintenance personnel, via TTY
messages, when a timeout or annoyance call occurs. Module C28 is
initially called by Call Processing to set up the required data in
a spare WA. Module C28 then schedules module C30 to format this
data and provide for a TTY output.
Since the TTY messages are in two parts, module C30 attempts to
obtain a second WA for its processing. After obtaining the spare
WA, module C30 determines which type of printout is desired: an
annoyance origination or termination, or a timeout (from a line or
trunk origination). The timeouts may be interdigital, permanent,
busy tone, or reorder tone. A reorder tone timeout for a trunk
origination is an invalid message. When this condition is
encountered, both WA's are released and control is given to the
Executive.
After determining the type of printout, module C30 formats the data
in the two WA's. The first message contains the type, line
identity, trunk group incoming, party identity, and originating
junctor identity. The last two items are left blank for trunk
originations. The second message contains the type, permanent trunk
identity, called number, originating class of service, originating
service number, and time of printout. The permanent trunk identity
is left blank when the call is not terminated to a permanent
trunk.
After all necessary formatting is completed, module C30 passes the
first message via the ACCEPT entry line (E01X01) to module F07. The
second message is passed via the RESKED entry line (E01X01) to
module F07.
8.2 technique -- not applicable.
Notes to fig. 100a
1. schedule output format (f07x01) using wa1 and the resked entry
line.
c31 -- fig. 101-101b
1. name - local Call Process Maintenance Program (LCPMP)
Module.
2. PURPOSE - The Local Call Process Maintenance Program (module
C31) has two major responsibilities. First, it serves as the common
handler of all error message conditions encountered by Call
Processing. It provides all the information for error message
formatting to the Call Processing Error Message Formatter program
(module C33). Second, module C31 performs software retrials and
alternate routing for calls which encounter trouble with certain
Terminating Marker (TM) and Register Sender (RS) malfunctions.
3. FUNCTIONS
Module C31 performs the following functions:
a. Obtains a spare 64-word Work Area (WA) for all error conditions
detected by Call Processing. It moves the Call History Table (CHT)
and WA information required for search key construction into the
new WA. When the WA cannot be obtained on the initial attempt, the
error message printout is by-passed.
b. Schedules module C33 for all Call Processing error conditions,
unless printouts were disabled (CPE = 1).
c. Provides a lockout condition to calls encountering "fatal"
errors during Call Processing. The Call Event Metering -- Reorder
Tone Metering subroutine (M09X04) is accessed when a "fatal"
condition occurs.
d. Returns to the calling Call Processing module, after scheduling
module C33, for continued processing when the Call Processing error
condition is not "fatal."
e. Serves as the error handler for the RS Access program (module
F08) accesses from Call Processing.
f. Serves as the error handler for all the Data Manipulator (MANIP)
program (module F35) drum accesses from Call Processing. An
appropriate error message is generated utilizing Functions 3(a)
through 3(d).
g. Performs TM retrials when scheduled by TM maintenance. Prints a
TM error message and provides lockout when continuous retrials
fail.
h. Performs RS retrials when scheduled by the RS System Trouble
Monitor program (module J28). Prints an error message and provides
lockout when continuous retrails fail.
i. Provides lockout by overriding trouble in the RS. The Final
Process program (module C26) is scheduled to clear RS Memory after
successful lockout of the Register Junctor (RJ).
j. Software idles any senders or receivers previously dropped as a
result of RS system trouble.
k. Schedules the Route Number and Directory Number Translation
program (C15) for TM and RS retrials when an alternate route is
indicated.
4. INPUTS
4.1 software
4.1.1 core Tables
Chc -- originating Marker Data Frame Received.
Chh -- route and Path Data.
Chl -- ticketing Interface Data.
Chm -- call History Maintenance Table.
Chq -- program Generated Indicators.
Cht -- general Call History Table.
Cxf -- drum Tables CRN and CDN.
Fpi -- printout Inhibit Items.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
Fwc -- terminating Marker Received Information.
Hst -- system Status Table.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chh -- route and Path Data.
Chl -- ticketing Interface Data.
Chm -- call History Maintenance Table.
Chq -- program Generated Indicators.
Cwa -- sender/Receiver Assigner Interface.
Cwd -- call Processing Maintenance Printout Work Area.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C31X01 Scheduled by
module F35 when an error is encountered while attempting a drum
translation for Call Processing. C31X02 Scheduled as the error
program when Call Processing interfaces with module F08. C31X03
Scheduled by any Call Processing module encountering an error
condition requiring the output of a Teletypewriter (TTY) message.
C31X04 Scheduled as an error program for accesses. C31X05 Scheduled
internally by C31X02 when a Sender/Receiver (S/R) is assigned and
the bit is set. C31X06 Scheduled by module J28 to determine if a
S/R was dropped. C31X07 Scheduled by the Register Junctor Call
Clear program (module C32) to provide lockout. 6.2 EXIT POINTS Exit
Points Reasons for Exit C25X04 TM Call Complete Process program:
C25X04 is used to perform a Call Processing retrial. C26X04 Final
Processor program: C26X04 is used to "lockout" a given line or
trunk (e.g., return lockout reorder tone from the originating
junctor or incoming trunk circuit). C29X03 Call Condition Analysis
program: C29X03 is used when it is desirable to have module C29
save the WA by hitching it to the CHT, when a RS interrupt does not
occur. C31X05 LCPMP: Used as an internal return point and is
scheduled internally by C31X02 when a S/R is assigned and the TEM
bit is set. F08X01 RS Access During Normal Processing program:
F08X01 is used for writing in RS Memory and has the capability to
write and to read-modify-write. F35X01 Data Manipulator (MANIP)
Program: F35X01 is used by resident and non-resident programs to
access drum memory. 7. SUBROUTINES USED Entry Points Functional
Names C27X01 Sender/Receiver Assigner. E01X01 ACCEPT -- Data
Processing Unit (DPU) Scheduler. E01X06 RESKED -- DPU Rescheduler.
F04X01 WASPAR -- Work Area Assignment. F08X02 RS Access During
Maintenance Processing. M09X04 Call Event Metering -- Reorder Tone
Metering.
8. NARRATIVE
8.1 discussion
module C31 is designed to serve as the common handler for all error
conditions detected by Call Processing. Errors encountered by
module F35, while performing drum translations, are also handled by
module C31 logic.
In processing these errors, module C31 first obtains a spare
64-word WA. It then stores into the WA all the CHT and WA
information necessary for message key construction. Module C33 is
then scheduled, using this spare WA, to enable the required error
message to be formatted and printed via the TTY. For most errors,
the call is given reorder tone via lockout. For these situations,
subroutine M09X04 is called. When the error indicator is 56 (less
than three digits received), lockout is not provided; however, the
WA is released and additional digits are collected. Similarly, for
line circuit faults, ticketing and invalid Pattern errors, and
Recognition Field (PRF) errors, control is returned to Call
Processing for additional processing.
When printouts are disabled (CPE = 1) or a spare 64-word WA cannot
be obtained on the initial attempt, the call is given reorder tone,
released, or returned as discussed above without printing an error
message.
Module C31 also performs software retrials and attempts alternate
routing when a call encounters trouble due to certain TM and RS
malfunctions. For TM malfunctions, module C31 is scheduled by
either TM maintenance or the Communication Control Register (CCR)
Handler program (module C32). It is essential, upon entry to module
C31, that TM timing (1.5 second timer) be stopped (IN = 15) since
it is likely that a timeout will occur before the TM regains
control. Module C31 reads RS Memory to determine if the RS is in
trouble and if any paths were pulled. When the RS is in trouble,
module C31 releases control since module J28 is scheduled to handle
the error. When paths are pulled, the Loop Pulled Indicator (LPI)
is set and used by the Alternate Route Control program (module C21)
on retrial and alternate route processing. The Error Indicator
(E10) field from the I/O programs of the Executive is checked by
module C31. If EIO is equal to 8, 9, or 10 the retrial logic is
entered. If EIO is other than 8, 9, or 10 a TM error message is
printed and the call is given lockout.
When retrials are permitted (EIO = 8, 9, or 10), module C31 allows
a second retrial attempt at TM completion. If this retrial fails,
module C31 allows one trial on an alternate route (if one is
available) and one retrial on this route. Once these four attempts
(two attempts when no alternate route is available) prove
unsuccessful, a TTY error message is initiated and the call is
given lockout.
Module C31 is scheduled by module J28 when RS retrials are
required. Upon entry, module C31 checks for RS trouble indications.
If the RS is in trouble, module C32 is scheduled to clear down the
faulty RJ. If the RS is not in trouble, module C31 schedules the
S/R Assigner program (C27) to software idle any senders or
receivers dropped (Translation Interrupt of 7). If a S/R is
dropped, module C31 reschedules itself upon dropping a path
(Translation Interrupt of 8). If a S/R is not dropped, module C31
enters the retrial logic discussed for TM's.
8.2 TECHNIQUE -- Not applicable.
Notes to fig. 101b
1. entry line for tm retrials.
c32 -- figs. 102-102d
1. name -- register Junctor Call Clear Module.
2. PURPOSE -- The Register Junctor Call Clear program (module C32)
clears down either idle Register Junctors (RJ's) or RJ's which have
calls in progress. Module C32 may be called upon to clear a single
RJ or all the RJ's in one Register Sender (RS) Common Logic Unit
(CLU).
3. functions -- module C32 performs the following functions:
a. Entry line C32X01 performs the following functions to clear only
one RJ:
1. determines if the RS is in a fault condition. When a fault
condition exists, module C32 continuously reschedules itself until
the fault is cleared.
2. Modifies RS Memory to set the Service Bit (SB), Freeze Bit (FB),
and Processing Sequence State (PSS) to one; Timer A (TMA), Timer A
Counter (MDA), Connection Sequence State (CSS), and RS word 3B to
zero.
3. Indicates that the RJ is software on-line (CHQROL = 0), and
interfaces with the Manual Test Panel (MTP) Abort Routine (V81X04)
allowing maintenance to release any RJ under its control.
4. Resets the BY latch in RS Memory if the CSS was non-zero prior
to reset. When there is Trouble In Assignment (TAS = 1), the BY
latch is reset by the RS, thus module C32 is not needed to reset
the BY latch.
5. Sets a flag indicating that this particular RJ is being cleared
down using entry line C32X01 (CHQABC = 1).
6. modifies the Work Area (WA) to schedule entry line C32X04 as the
next program when the WA is linked to the Call History Table (CHT)
associated with this particular RJ (CHQWAL = 1) and the WA is
currently being used to schedule another program (CHQIPS = 1).
C32X04 will continue processing utilizing the linked WA. If the
work area of the call being processed was on the exec timer queue
for S/R timing when C32X04 will also decrement a counter which
indicates the number of work areas of that type that are on the
timer queue.
7. Modifies the CHT to schedule entry line C32X03 as the next
program, when a WA is not linked to the CHT associated with this
particular RJ (CHQWAL = 0) and the CHT is currently being used to
schedule another program (CHQIPS = 1). C32X03 obtains a spare
26-word WA, links this WA to the CHT, and continues processing the
RJ.
8. obtains a spare 26-word WA and links the WA to the CHT when a WA
is not linked to the CHT associated with this particular RJ (CHQWAL
= 0) and the CHT is not currently being used to schedule another
program (CHWIPS = 0). Module C32 will then continue processing.
9. Utilizes the WA to continue module C32 processing when a WA is
linked to the CHT associated with this particular RJ (CHQWAL = 1)
and the WA is not currently being used to shcedule another program
(CHQIPS = 0).
10. schedules the calling program back with the original WA passed
to module C32. Normal module C32 processing continues utilizing the
WA linked to the CHT.
11. writes into RS Memory, to zero those fields which are used in
clearing down this particular RJ.
12. indicates that maintenance is working with this particular RJ
(CHQCRJ = 1).
13. interfaces with the Reorder Tone Metering subroutine (M09X04)
for RJ's which are in the midst of processing a call.
14. Utilizes C31X07 to generate lockout for the subscriber.
b. Entry line C32X02 performs the following functions to clear down
one half of the RJ's in a RS section:
1. Determines which half of the RJ's should be cleared either CLUA
or CLUB), and which RS section is involved. The total number of
RJ's to be cleared is obtained from table CEP.
2. initializes the CHT address of the RJ, utilizing the RJ Identity
(FWARJI).
3. schedules the calling program's error return when the CLU being
cleared is not equipped in the office or an error occurs.
4. Interfaces with the MTP Abort Routine (V81X05).
5. determines if a particular RJ is currently being cleared down by
entry line C32X01 (CHQABC = 1) or if the RJ is currently off-line
(CHQROL = 1). For either of these situtations, the clearing down of
the particular RJ is bypassed, the number of RJ's to be cleared is
decremented by one, and the next RJ, along with the associated CHT,
is selected.
6. Clears eight RJ's then skips the next eight RJ's (located in the
other CLU) because RJ's are assigned to CLU's in increments of
eight.
7. Modifies RS Memory to set the FB and PSS to one; TMA, MDA, and
CSS are set to zero.
8. Indicates when the RJ and any associated Sender/Receiver (S/R)
are to be placed on-line (CHHRJS = CHHSRS = 0).
9. modifies the WA to schedule entry line C32X04 as the next
program when there is a WA linked to the CHT associated with the RJ
(CHQWAL = 1) which is currently being used to schedule another
program CHQIPS = 1). C32X04 then continues processing on this RJ
utilizing the linked WA. If the work area of the call being
processed was on the exec timer queue for S/R timing when C32X02
was called, C32X04 will also decrement a counter which indicates
the number of work areas of that type that are on the timer
queue.
10. Modifies the CHT to schedule entry line C32X03 as the next
program when there is no WA linked to the CHT associated with the
particular RJ (CHQIPS = 1). C32X03 then obtains a spare 26-word WA,
links it to the CHT, and continues processing on the particular
RJ.
11. sets a flag in the RJ's CHT indicating that entry line C32X02
is clearing the particular RJ (CHQDRP = 1) when no other programs
are currently scheduled (CHQIPS = 0) with either the CHT (CHQWAL =
0) or possibly a WA linked to the CHT (CHQWAL = 1).
12. resets the Temporary Configuration (TEM) bit along with the BY
and DMC latches after all RJ's are set up to be cleared.
13. Obtains a spare 26-word WA for use in clearing down the CLU
RJ's and schedules the calling program back with the original
WA.
14. determines if the RJ is allocated. If not allocated, processing
utilizing entry line C32X02 is completed and control is
released.
15. Determines if entry line C32X02 is to clear the particular RJ
(CHQDRP = 1) when RJ's are allocated. If the particular RJ is not
to be cleared, the next RJ in the CLU is similarly checked. This
procedure continues until a RJ requiring clearing is found.
16. Utilizes the WA to clear the RJ as in Functions (a) 11 through
14, when a WA is linked to the CHT (CHQWAL = 1).
17. obtains a spare 26-word WA and links it to the CHT when a WA is
not linked (CHQWAL = 0). The RJ is then cleared as in Functions (a)
11 through 14.
18. Reschedules C32X07 after each RJ is set up to be cleared, until
all allocated RJ's are processed. See Function (b) 14.
4. INPUTS
4.1 software
4.1.1 core Tables
Cep -- engineering Office Parameters.
Cha -- scheduling Information.
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
Hst -- system Status Table.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Ccw -- call Processing Counts of Work Areas on the Executive Timer
Queue for S/R Timing.
Cha -- scheduling Information.
Chl -- ticketing Interface Data.
Chm -- call History Maintenance Table.
Chq -- program Generated Indicators.
Fwa -- executive Interface Work Area.
Fwb -- call Processing Register Sender Memory Image.
5.1.2 Drum Tables --0 None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C32X01 Scheduled
when the system requires a single RJ to be cleared down as a result
of some trouble condition. C32X02 Scheduled when the system
requires the clearing of one half of the RJ's associated with an RS
Section (either CLUA or CLUB). C32X03 Scheduled internally when it
is determined that a WA is not linked to the CHT associated with
the RJ being processed (CHQWAL = 0), and that CHT is being utilized
to schedule another program (CHQIPS = 1). - C32X04 Scheduled
internally when it is determined that a WA is linked to the CHT
associated with the RJ being processed (CHQWAL = 1) and that WA is
being utilized to schedule another program (CHQIPS = 1). C32X05
Scheduled when entry line C32X01 is required to obtain a spare
26-word WA. C32X05 is rescheduled when a WA overload condition is
encountered. C32X06 Scheduled internally on an overload condition
while obtaining a spare 26-word WA prior to clearing down a RJ of a
given CLU. C32X07 Continuously scheduled until all the RJ's marked
for clearing are processed. 6.2 EXIT POINTS Exit Points Reasons for
Exit C31X07 Local Call Process Maintenance Program (LCPMP): C31X07
is used by module C32 to provide lock-out by overriding trouble in
the RS. E01X03 Data Processing Unit (DPU) Scheduler (RELEAS)
program: E01X03 is used to inform the DPU Scheduler that the
current job is completed. E01X06 DPU Scheduler (RESKED) program:
E01X06 is used to cause the DPU Scheduler to add a run request to a
queue. 7. SUBROUTINES USED Entry Points Functional Names E01X01
ACCEPT -- DPU Scheduler. F04X01 WASPAR -- Work Area Assignment.
F08X02 RS Access During Maintenance Processing. F14X01 CHT Address
Calculation. L01X04 CONFIG -- Configuration Control Program. M09X04
Call Event Metering -- Reorder Tone Metering. V81X04 Maintenance
Control Center (MCC) Maintenance Strings. V81X05 MCC Maintenance
Strings.
8. NARRATIVE
8.1 discussion
module C32 may be called by any program when either a single RJ or
an entire RS CLU requires clearing down. Module C32 has two major
entry points, one to clear a single RJ (C32X01), and one to clear
all the RJ's in a RS CLU (C32X02).
When C32X01 is called, a particular RJ is assumed to be in some
type of trouble condition. When the TEM bit is set, C32X01 is
continually rescheduled until the TEM bit is reset. The first task
is to modify the RS Memory allowing the clearing down process to
proceed without being inhibited by further hardware problems. Once
the required fields and latches are set up, module C32 obtains the
RJ's CHT address from the WA, and indicates in the CHT that this
particular RJ is being cleared down (CHQABC = 1).
Module C32 requires the use of a 26-word WA to clear down the
RJ(s). When a job is currently scheduled with the RJ being cleared
(CHQIPS = 1), the job is allowed to complete its tasks with module
C32 scheduled as the next program. If a WA is linked to the CHT of
this particular RJ (CHQWAL = 1), module C32 is scheduled via entry
line C32X04. If a WA is not linked, module C32 is scheduled via
entry line C32X03.
Entry to module C32 via entry line C32X04 implies that module C32
may utilize the 26-word WA previously linked to the CHT to clear
this particular RJ. Entry via C32X03 indicates that a spare 26-word
WA must be obtained before clearing down the RJ.
When module C32 determines that a job is not scheduled with this
particular RJ (CHQIPS = 0), processing continues without any
realtime breaks. If a WA is linked to this particular RJ's CHT
(CHQWAL = 1), that particular WA is used by module C32 to clear
down the RJ. If a WA is not linked, a spare 26-word WA must be
obtained before clearing down the RJ.
When module C32 indicates that a program is scheduled and a WA
linked to this particular RJ by setting the Inhibit Program
Scheduling (IPS) and Work Area Linked (WAL) indicators to one. The
Reorder Tone Metering Subroutine (M09X04) is called when a call was
in progress on this particular RJ. RS Memory is updated to effect a
final clearing of the RJ. The subscriber is then given reorder tone
via C31X07.
Module C32 is called via entry line C32X02 when the calling program
requires C32 to clear down all RJ's in a given RS CLU. This entry
line ensures that each RJ in the CLU is cleared down.
The first RJ, for the selected CLU, and its associated CHT address
are determined. The total number of RJ's in the particular RS
section is retrieved from table CEP. An interface with maintenance
is accomplished via subroutine V81X05, allowing the release of any
RJ's under its control. Each RJ in the CLU is checked. The RJ's
being cleared down by entry line C32X01 or those which are in an
off-line status are bypassed. RJ's not in a clear down process are
set up for eventual clearing down by entry line C32X02.
Entry lines C32X03 (WA not linked) and C32X04 (WA linked) are
employed, as in the single RJ clear process, when a job is already
scheduled on the RJ. When no other jobs are scheduled and the RJ is
to be cleared down, an indicator in its CHT (CHQDRP = 1) is set by
entry line C32X02.
The 192 RS's are assigned to the two CLU's in alternate groups of
eight. This grouping of the RJ's requires entry line C32X02 to
check only eight RJ's, then it skips the next eight since they are
assigned to the other CLU. Once all the RJ's in the CLU are
processed to determine if they require clearing, entry line C32X02
rests the TEM bit for the RS section being cleared. The BY and DMC
latches are also reset. A spare 26-word WA is obtained and the
calling program is scheduled with the original WA.
Module C32 proceeds with the actual clearing down of those RJ's
which are marked for clearing (CHQDRP = 1) and are in the selected
CLU. When a WA is not already linked to the RJ's CHT, a spare
26-word word WA is obtained, otherwise, the linked WA is utilized
to clear the RJ. C32X07 is rescheduled until all marked RJ's are
processed. The clearing down processes use logic common to entry
point C32X01. This common logic interfaces with subroutine M09X04
and provides lockout via C31X07.
8.2 technique -- not applicable.
1. NAME -- Call Processing Error Message Formatter Module.
2. PURPOSE -- The Call Processing Error Message Formatter program
(module C33) formats all pertinent information for either software
or hardware error messages, enabling printing of the error messages
via the Teletypewriter (TTY). Checks are initiated for the
detection of error conditions throughout the Call Processing
software modules. These errors may either be software (data base or
coding errors) or hardware in nature. When one of the errors is
encountered, a TTY message is output, notifying the craftsman to
take corrective action.
3. FUNCTIONS -- Module C33 performs the following functions:
a. Determines the particular type of error to be processed from the
error indicator passed by the calling program.
b. Formats a message with error indicators and search keys of zero,
when the error indicator is out of range.
c. Determines the value of the Drum Problem Indicator (DPI) and
retrieves the three-letter table name from table CMM, when drum
table errors are encountered.
d. Blanks the DPI and retrieves the three-letter table name from
table CMM for all core table errors.
e. Blanks the DPI and the three-letter table name for all other
valid errors.
f. Accesses table CMC to retrieve search key and message skeleton
information for all valid errors.
g. Accesses table CMD for specific search key data.
h. Obtains an additional Work Area (WA) via the WA Assignment
(WASPAR) program (module F04), when an error printout is divided
into two parts.
i. Schedules the Output Message and Print (OUTPUT) program (module
F07) for formatting the message into an internal code and for
outputting the message via the TTY.
4. inputs
4.1 software
4.1.1 core Tables
Cmc -- control Data Maintenance.
Cmd -- data Description Maintenance.
Cmm -- call Maintenance Mnemonics.
Cwd -- call Processing Maintenance Printout Work Area.
Fwa -- executive Interface Work Area.
4.1.2 Drum Tables -- None.
4.1.3 Registers -- None.
4.2 HARDWARE -- None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Cwd -- call Processing Maintenance Printout Work Area.
Fwa -- executive Interface Work Area.
5.1.2 Drum Tables -- None.
5.1.3 Registers -- None.
5.2 HARDWARE -- None.
6. CONTROL
6.1 ENTRY POINTS Entry Points Reasons for Entry C33X01 C33X01 is
scheduled by the Local Call Processing Maintenance Program (module
C31) to format Call Processing Error Messages. C33X02 C33X02 is
scheduled internally when a WA overload condition is encountered
while obtaining a second WA for a two-part message. C33X03 C33X03
is scheduled as a subroutine to retrieve the search key data from
the WA. 6.2 EXIT POINTS Exit Points Reasons for Exit E01X06 Data
Processing Unit (DPU) Scheduler (RESKED) program: E01X06 is used to
cause the DPU Scheduler to add a run request to a queue. 7.
SUBROUTINES USED Entry Points Functional Names E01X01 ACCEPT -- DPU
Scheduler. F04X01 WASPAR -- WA Assignment.
8. NARRATIVE
8.1 discussion
throughout the Call Processing, software module checks are
initiated to check for existence of certain errors. When any of
these errors are encountered, a TTY message is provided. This
message contains the necessary information to initiate corrective
action. Module C33 was designed as the common formatter for all
Call Processing error messages. Each error message processed by
module C33 is identified by an error indicator (IND). This
indicator is passed to module C33 by the program detecting the
error, and will be printed as a part of the TTY message. The TTY
message is of the following general format; however, for special
situations it can be varied:
A3 tt cpin aa, bbb, c
lni/tnk
tdn
sk1
sk2
where:
A3 TT CPIN Represents header information for Call Processing
messages. AA Represents the error indicator which uniquely
identifies each error (IND) passed to module C33. BB Represents a
three-letter table name. This field is used with drum and core
tables only. C Represents the drum problem indicator which also
identifies, the particular type of drum error encountered, and is
used with drum tables only. LNI/TNK Represent the inlet identity of
the originating subscriber associated with this error. LNI is used
for line originations. TNI is used for Trunk originations. TDN
Represents the Terminating Directory Number(s) input by the
subscriber at the time this particular error was detected. SK1/SK2
Represent search key values associated with a particular error.
These values may be considered the source data utilized by Call
Processing while detecting an error.
Module C33 utilizes IND in determining the type of error
encountered. There are three basic types of errors: drum table,
core table, and system errors. Message formatting is performed by
module C33 as a function of these error types.
When the IND indicates a drum error has occurred, module C33 sets
up the DPI for a message output utilizing the Error Indicators from
the I/O programs of the Executive (EIO) field set by the drum
handler. The EIO field defines the type of drum error (software,
hardware, invalidity, or no coincidence). The DPI field is used
with drum error messages only and is blanked for all other error
messages.
An appropriate three-letter table Name (MNE) must be output on the
message for both drum and core table errors. The MNE is retrieved
from table CMM utilizing IND as an index. The MNE field is blanked
when the error is not a table error.
Module C33 retrieves error control data from table CMC for all
valid errors. IND is again utilized as an index for table CMC. Four
pieces of data are retrieved: up to three search key codes and one
message format (or skeleton) number. Module C33 utilizes the search
key codes as inputs to a subroutine (C33X03), which then retrieves
the actual search key data from the WA. C33X03 then masks and
repositions the data in the WA to enable the data to be used as an
output. C33X03 utilizes table CMD for this data manipulation.
Module C33 then checks for error messages requiring special format
processing. Certain messages require unused digit positions, in the
terminating directory number field, to be zeroed out. For example,
an error on a 4-digit CGT translation only provides the four digits
utilized in the drum access (all others are blanked out). Some
message formats only require one search key to be output and for
these situations module C33 blanks search key 2.
Finally the message skeleton number is stored in the WA and module
F07 is scheduled to format the message into an internal code; it
then is output via the TTY.
8.2 technique -- not applicable.
EXECUTIVE PROGRAM MODULES
F.phi.2 -- figs. 106 - 106b
1. name: link to Queue Program
2. PURPOSE: The purpose of module F0x is to link a work area to a
specified queue.
3. FUNCTIONS:
a. Maintains current, total and empty queue statistics.
b. Initiates a validity check for the type field.
c. Links to the front or back of a queue.
d. Maintains maximum length queue has attained.
4. INPUTS
4.1 software
4.1.1 core table
Fwa -- executive Interface Work Area
Fra -- queue Root
Esl -- executive Storage Locations
4.1.2 DRUM TABLES
None
4.1.3 REGISTERS
X1 -- identity of Work Area to be Queued
X2 -- queue root identifier
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Fwa -- executive Interface Work Area
Fra -- queue Root
Esl -- executive Storage Locations
5.1.2 DRUM TABLES
None
5.1.3 REGISTERS
None
5.2 HARDWARE
None
6. CONTROL
6.1 ENTRY POINTS ENTRY REASONS FOR ENTRY POINTS F.phi.2X.phi.1 Link
to back of Queue F.phi.2X.phi.3 Link to front of Queue 6.2 EXIT
POINTS EXIT REASONS FOR EXIT POINTS Control is always returned to
the calling program. 7. SUBROUTINES USED ENTRY FUNCTIONAL NAMES
POINTS NONE
8.0narrative
8.1 discussion
the queue structure used by the executive consists of two parts:
the entries in the queue and the queue roots. Each queue has a
unique root, fixed table of six words, associated with it. The root
points to the first queue entry, the first points to the second,
etc. The last entry contains a zero instead of a pointer to
indicate the end of the queue. The queue root also contains the
last entry to facilitate adding new entries.
The F.phi.2 module provides two way linkage of a work area. A work
area may be linked to the front or the back of the queue depending
upon the entry line called. Both entry lines provide a route of
initializing first and last entry pointers in the queue root if the
queue is empty. Interrupts are disabled as a function of the LNKTAB
macro.
8.2 TECHNIQUE
When linking a work area to the back of a queue; entry is required
from line F.phi.2X.phi.1. Upon entry an initial check is made to
determine if the queue has other work areas in it. If it doesn't
the empty queue counter is incremented and a check is made to see
if the work area type is valid. If the work area type is valid the
linkage word of the new entry is stored in the zeroed link field
and the first and last entry pointers are stored in the queue root.
The total and current entry counts are incremented and the maximum
count is equated to the current count if the present maximum count
is less than the current count. The interrupts are enabled and
return is made to the caller.
When the initial check determines the queue is not empty and the
type field is valid the new entry address is merged into the old
last entry and the old last entry's linking address now points to
the now last entry. Return is made to the caller after the entry
counts are incremented and interrupts enabled as described
earlier.
When linkage is required to the front of a queue, entry line
F.phi.2X.phi.3 is called. If the queue is empty, processing remains
the same as for an empty queue in F.phi.2x.phi.1. If the queue is
not empty the address of the first entry is merged into the new
entry linkage in the work area and the address of the new entry is
placed in the queue root. The total and current empty counts are
incremented and the maximum count is equated to the current count
if the present maximum count is less than the current count. The
interrupts are enabled and return is made to the caller. If upon
any entry line (X.phi.1 or X.phi.3) the type field is found to be
invalid, a call to work area audit is initiated.
F.phi.3 -- fig. 107
1. name: -- unlink from queue program
2. purpose: -- the purpose of module F.phi.3 is to unlink work
areas from the front of the work area queue.
3. FUNCTIONS:
a. Maintains a current count of entries in the queue.
b. Passes the work area address of the entry being unlinked to the
calling program.
c. Adjust pointers to entries remaining in the queue.
4. INPUTS
4.1 software
4.1.1 core table
Fwa -- executive Interface Work Area
Fra -- queue Root
Esl -- executive Storage Locations
4.1.2 Drum Tables
None
4.1.3 Registers
X2 -- Queue Root Identifier
4.2 Hardware
None
5. Outputs
5.1 Software
5.1.1 Core tables
Fra -- queue Root
Esl -- executive Storage Locations
5.1.2 Drum Tables
None
5.1.3 Registers
Ra -- < .phi. -- queue empty
Ra -- > .phi. -- normal return
X1 -- work area identity if RA> .phi.
5.2 hardware
None
6. Control
6.1 Entry Points Entry Reasons for Entry Points F.phi.3X.phi.1
Unlink from top of Queue 6.2 Exit Points Exit Reasons for Exit
Points Control is always return to the calling program. 7.
Subroutines Used Entry Functional names Points None.
8.0 NARRATIVE
8.1 discussion
the F.phi.3 module provides the capability of unlinking a work area
from a queue over entry line F.phi.3X.phi.1. Unlike the linking
module F.phi.2 unlinking can only take place from the front of the
queue. The interrupts are disabled as a function of the LNKTAB
macro.
Technique:
upon entry via F.phi.3X.phi.1 the work area queue is checked to
determine if any entries are present. If the queue is empty the
error return indicator is set, the interrupts are enabled and
return is made to the caller.
If the queue is not empty, the count is decremented by one and the
queue is checked for additional entries. If only one entry is in
the queue the queue root address is used as the last entry
address.
The address of the entry being removed is stored for passage to the
caller. The new first entries address is put in the first entry
section of the queue root and a normal return is made to the caller
after the interrupts are enabled.
*NOTES TO FIG. 107
1. interrupts disabled in entry line table by use of dismac.
2. enimac
f03xc1 used to remove first entry from a queue.
inputs: (xr2) = queue root identity
outputs:
(xr1) - work area address if queue was not empty
(ra) .gtoreq. .phi. if queue was not empty
(ra) <0 if queue was empty
f.phi.4 -- figs. 108-108a
1. name:
f.phi.4 -- work area assignment program
2. purpose:
the purpose of module F.phi.4 is to assign a spare work area from
the queue to fulfill a request from the caller because of an
overload.
3. FUNCTIONS:
a. calls unlink to obtain a work area from the appropriate spare
work area queue.
b. calls lamplighter for overload lamps
c. checks for overload condition
d. returns indication to user of successful or overload condition
if requested
e. causes scheduling of user specified program overload, if
requested by user
4. Inputs
4.1 Software
4.1.1 Core Tables
Fra -- queue Root
Esl -- executive Storage Locations
Fwa -- executive Interface Work Area
Eps -- executive Parameter Storage
4.1.2 Drum Tables
NONE
4.1.3 registers
X1 -- work Area to be used for Executive overload handling
X2 -- work Area type indicator
Ra -- overload return program name and Entry line. Bit 24 set
indicates that Executive is to handle overload
4.2 Hardware
NONE
5. outputs
5.1 Software
5.1.1 Core tables
Fra -- queue Root
Esl -- executive Storage Location
Fwa -- executive Interface Work Area
5.1.2 Drum Tables
NONE
5.1.3 registers
Ra = .phi. if normal return
Ra = <.phi. if overload and caller is to handle Work Area
overload
X1 -- work area identity if RA = .phi.
5.2 hardware
NONE
6. control
6.1 Entry Points Entry Reasons for Entry Points F.phi.4X.phi.1
Obtain a spare Work Area 6.2 Exit points Exit Points Reasons for
exits E.phi.1X.phi.6 No Work Areas of size requested and executive
is to handle overload Otherwise, control is returned to the caller
7. Subroutines Entry Functional Name Points F03X.phi.1 UNLINK --
Obtain entry from Queue L25X.phi.1 LMPLTR -- Set work area overload
lamp on MCC
8.0 narrative:
8.1 discussion
module F.phi.4 assigns work areas on the basis of the specified
Work Area type indicator. Register A contains the program name and
entry line. If bits 24 is set the exec is to handle the overload
rather than returning to the caller at that time.
8.2 TECHNIQUE
Upon entry to F.phi.4 there is a call via macro PGLINK to unlink a
work area from a spare work area queue. If a work area is available
and is not the last one in the spare queue, the normal return
indicator is set and return is made to the caller.
When a work area of requested size is not available and the exec is
not to handle the overload the error return indicator is set.
Return is then made to the caller after enabling the
interrupts.
Upon non-availability of a requested work area the exec may be
called to handle the overload. This is accomplished by calling the
RESKED entry line (E.phi.1X.phi.6) for the overload rescheduling of
the specified program.
When a work area is retrieved and it is the last one in the queue
lamplighter is called to light the overload lamp. The interrupts
are enabled if applicable and normal return is made to the
caller.
F.phi.5 -- fig. 109
1. name
work Area Return (WADROP) Module.
2. PURPOSE
The Work Areas Return Program (Module F05) returns Work Areas
(WA's) to spare queues.
3. FUNCTIONS
Module F05 performs the following functions:
a. Calls the Link to Queue program (module FO2).
b. Calls the lamplighter (if applicable) to extinguish the WA
overload lamp.
4. INPUTS
4.1 software
4.1.1 core Tables
HLS -- Lamp Status Table.
4.1.2 Drum Tables
None.
4.1.3 Registers
X1 -- Contains the work area address.
4.2 HARDWARE
None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
None.
5.1.2 Drum Tables
None.
5.1.3 Registers
None.
5.2 HARDWARE
None.
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F05X01 F05X01 is
called to return temporary WA's to the proper spare WA queue. 6.2
EXIT POINTS Exit Reasons for Exit Points None. Control is returned
to the calling program. 7. SUBROUTINES USED Entry Functional Names
Points F02X01 Link to Priority Queue: Link to the Back of the
Queue. L25X01 Lamplighter (LMPLTR). 8. NARRATIVE
8.1 discussion
module F05 is entered by calling entry line F05X01. Upon entry,
information regarding the return of a WA to a spare queue and the
size of the queue is obtained by accessing the linkage word and
symbolic queue identifier.
A mask, indicating a Lit Lamp, is compared with the lamp status
table. If the lamp is already extinguished, a branch to module F02
is initiated. After control is returned to module F05, interrupts
are enabled and control is returned to the caller. If the overload
lamp is lit, a call to the Lamplighter subroutine is initiated to
extinguish the overlamp. Then a branch to module F02 is initiated.
After control is returned to module F05, interrupts are enabled and
control is returned to caller.
8.2 TECHNIQUE
Not applicable.
* NOTES to FIG. 109
1. interrupts disabled in entry line table by dsimac.
2. interrupts enabled when required by use of enimac.
3. type is used as queue root identity of appropriate spare
queue.
4. called to extinghish work area overload. f05x01 used to return
work areas to the spare queues.
input:
(xr1) = work area address
output: none
l13g
1. name
work Area (WA) and Call History Table (CHT) Initializer module.
2. PURPOSE
The WA and CHY Initializer program (module L13G) clears and
initializes regular WA's, special WA's, and CHT's.
3. FUNCTIONS
Module L13G performs the following functions:
a. Sets the Register Junctor (RJ) off-line bit, in the
corresponding CHT, for each unequipped RJ.
b. Initializes all regular and special WA's and links them to spare
queues or hitching posts.
4. INPUTS
4.1 software
4.1.1 core Tables
Cep -- engineered Office Parameters
Chq -- call History Table
Esw -- special Work Area Initialization Table.
Fjb -- base Level Junk
Hep -- engineered Parameters
4.1.2 Drum Tables
None.
4.1.3 Registers
None.
4.2 HARDWARE
None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Chq -- call History Tables
Fhp -- hitching Post Table
Fjb -- base Level Junk
Fza -- special Work Area Table
5.1.2 Drum Tables
None.
5.1.3 Registers
None.
5.2 HARDWARE
None.
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points L13G01 L13G01 is
branched to clear and initialize regular and special WA's, and
CHT's. 6.2 EXIT POINTS Exit Reason For Exit Points L13D01 (End)
L13D01 is used when all the WA's and CHT's are accounted for. 7.
SUBROUTINES USED Entry Functional Names Points F05X01 WADROP --
Work Area Return. 8. NARRATIVE
8.1 discussion
since WA's and CHT's are not imaged on drum memory, module L13G
must initialize these areas before control is transferred to the
EAX system. Before the system begins operation, all WA's must be
properly linked to a queue or hitching post, and each CHT must
reflect its RJ's installed status.
8.2 TECHNIQUE
Module L13G first initializes all allocated CHT's. The quantity of
CHT's in a section is an engineerable parameter. For each equipped
CHT, a check is performed (in table HEP) to determine if the
associated RJ is also equipped. When the bit in table HEP is not
set (the RJ is not installed), the off-line bit in the associated
CHT is set. A check is performed determining if Office Section two
is installed. When Office Section two is installed, module L13G
performs the same actions as in Office Section One.
Regular WA's are then initialized. Table HEP is utilized in
determining the size, type number, and quantity of each WA type.
The relative depth in the WA common area is computed for each WA.
After the computation, the WA is dropped via the WA return (WADROP)
program (module F05). This operation is performed for each WA
type.
Table ESW is utilized in the construction of the special WA's. Each
special WA described in table ESW is hitched to its respective
hitching post, and the type field of each WA is initialized.
F14 -- fig. 110
1. name
call History Table Address Calculator Subroutine.
2. PURPOSE
Module F14 provides centralized calculation of Call History table
addresses from Register Junctor identities.
3. FUNCTIONS
Module F14 performs the following functions:
a. Determines whether the Register Junctor identity input is within
the range of equipped units.
b. Calculates the relative address of the Call History Table slot
in the Call History Table.
c. Returns control to the calling program.
4. INPUTS
4.1 software
4.1.1 core Tables
CEP -- Call Processing Engineering Parameters Table.
4.1.2 Drum Tables
None.
4.1.3 Registers
RA -- Register Junctor identity consisting of Register Junctor
Number (0-191) in bits 4-11 and Register Sender Section in bit 12
(0 = Section 1; 1 = Section 2).
4.2 HARDWARE
None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
None.
5.1.2 Drum Tables
None.
5.1.3 Registers
A-register -- Validity Indicator
(0 indicates register junctor is not equipped)
(1indicates calculations successful)
Q-register -- Register Junctor identity received as input.
Xr2 -- call History Table slot relative address
Xr1 -- saved and restored
All other registers are destroyed.
5.2 HARDWARE
None
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F14X01 This is the
only entry point of module F14 and is called by any program
desiring Call History Table address calculation. It may be entered
in base level or any interrupt level. 6.2 EXIT POINTS Exit Reasons
for Exit Points The exit point is to return control to the calling
program.
7. SUBROUTINES USED
None.
8. NARRATIVE
8.1 discussion
the No. 1 EAX has many programs which need to access a Call History
Table slot corresponding to a particular register junctor. The
program may not have the index value for accessing the particular
slot. To centralize the calculations of that index, module F14,
Call History Table Address Calculator subroutine is provided.
8.2 TECHNIQUE
F14 makes a range check on the Register Junctor number before
making address calculation.
If bit 12 of A-Register is zero, indicating Register Sender section
1, the Register Junctor number is compared with CEPRE1. If Register
Junctor is not greater than CEPRE1, control is then returned to
calling program. If Register Junctor number is greater than CEPRE1,
A-Register is cleared and control is returned to calling
program.
If bit 12 of A-Register is set, indicating Register Sender Section
2, the Register Junctor number is compared with CEPRE2. If the
Register Junctor number is not greater than CEPRE2, XR2 is loaded
(Register number + CEPRE1) *12 and A-Register is set to 1; control
is then returned to calling program. If Register Junctor number is
greater than CEPRE2, A-Register is cleared and control is returned
to calling program.
Notes to fig. 110
inputs:
ra -- rj identity w/section bit
outputs:
ra -- validity indicator
xr2 -- call history table address
rq -- incoming rj identity
cepre1 = highest value of an equipped rj in rs unit 1
cepre2 = highest value of an equipped rj in rs unit 2
cepra1 = number of call history table entries for rs unit 1
f29 -- figs. 111-111c
1. name
drum Scheduler
2. PURPOSE
To accept requests for drum I/O, and to initiate or queue these
requests depending on the availability of an idle DCU.
3. functions
a. Accepts request from Manipulator or the user.
b. Provides control interlock for the non-resident area.
c. Performs boundary tests to insure that the user has provided
adequate buffer area to receive requested data.
d. Provides proper routing of accesses requiring gradual transition
when the Update program is active.
e. Provides proper routings of transient write accesses.
f. Determines if the job can be executed on the required
DCU(s).
g. Initiates the job if the required DCU(s) is (are) idle.
h. Queues the job on the appropriate drum queue if the required
DCU(s) is (are) busy.
i. Returns control to the caller or releases to the Executive.
4. INPUTS
4.1 software
4.1.1 core Tables
Fwa -- user's Work Area
Fje -- executive Junk Storage
Ncw -- update Status Word
Fdp -- drum Parameter Table
Cep -- engineering Parameter Table
Fsw -- work Area Size Table
Chq -- user's Call History Table
4.1.2 Drum Tables
None.
4.1.3 Registers
XR1 -- Work Area Address
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
FWA -- User's Work Area
5.1.2 Drum Tables
None
5.1.3 Registers
XR1 -- Work Area Address
5.2 HARDWARE
None
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Engry Points F29X01 This is the
only entry point, called by the Manipulator or certain users for
access to the drum.
6.2 EXIT POINTS
This module may take one of two exit paths, as specified by the
caller:
1. Return to the caller 2. Exit to the Executive's TIME Loop
(E01X04)
7. SUBROUTINES USED Entry Functional Names Points F30A15 Called to
determine if a job can be executed on a given idle DCU F30A11
Called to initiate a job on a specified DCU F30A03 Called to
schedule a user's error program, if required. F02X01 Called to link
a job to a specified drum queue
8. NARRATIVE
8.1 discussion
the scheduler acts as an interface between a requestor of drum I/O
and the drum handler. It performs routine functions such as NRA
control interlock, final initialization of the work area and
boundary size checks. The terminal function is to initiate the job
(if a required DCU available) or queue it for execution later.
8.2 TECHNIQUE
The bulk of the scheduler's function involves boundary checks on
user-provided buffer area, to prevent inadvertent overflow of this
area. Several dedicated code paths exist for these checks designed
to minimize the real-time required to make them. As employed
elsewhere in handling the drum the user's access mode (see
Technique section of Drum Handler, F30) is utilized to route the
access through the required buffer size tests. Failure to pass
these tests will result in termination of the job, and the user's
error program being scheduled.
If these tests are passed (or are not required), a check is made to
see if one or both DCU's of the specified DCU pair is idle. If so,
a subroutine of the Drum Handler is called to verify that the
status of the required DCU will permit execution at this time. If
so, the Drum Handler is again called, to initiate the job on the
DCU. If execution cannot proceed at this time (or the required DCU
is busy), then the job is queued up on the appropriate queue for
execution later.
F30 -- figs. 112-112f
1. name
drum Handler
2. PURPOSE
To provide centralized control of I/O with the drum memory system
and with DMS isolation programs.
3. FUNCTIONS
a. Provides external interfaces with:
1. Interrupt Cause and Analysis Program
2. DMS Isolation Programs
3. I/O Device Time-Out Audit
b. Initializes DCU Initialization Table with proper control
information as required for each specific access to drum
c. Scans queues of an idle DCU in search of jobs awaiting
execution.
d. Schedules a user's error program when required.
e. Schedules the user's next program, when appropriate.
f. Handles the occurrence of ready interrupts from DCU's.
g. Processes data from DCU spills into a format requested by the
user.
h. Initiates a DCU spill, if requested by the user.
i. Transfers data from DCU initialization table into a user's
specified buffer area.
j. Performs validity check on data and control bit removal from
data, if requested.
k. Deletes primary data cell and primary address of coincidence, if
requested.
l. Clears DCU hardware and associated software indicator in
preparation for next job.
m. Initiates a job on the DCU by issuing the appropriate CPD.
n. Supervises special hardware interface required for access into
off-line care.
o. Maintains interface with I/O Device Time-Out Audit program.
p. Honors Maniac requests of Reset and Ignore, or Direct/Scheduled
Reroute on either error or ready interrupts.
4. INPUTS
4.1 software
4.1.1 core Tables
Fwa -- user's Work Area
Fdp -- drum Parameter Table
Fsv -- status Verify Table
Hst -- system Status Table
Fjp -- interrupt Level Junk Storage Table
Fdi -- dcu initialization Table
Fdm -- drum Data Mask Table
Fhp -- hitching Post Table
Hrd -- dms isolation Status Table
4.1.2 Drum Tables
None
4.1.3 Registers
Xr1 -- work Area Address or DCU Identity
Xr2 -- subroutine Caller Identity
Xr3 -- entry Line Identity
4.2 HARDWARE
DCU(s) either ready; in error; or in undetermined state, SG-65 CCP
identity
5. OUTPUTS
5.1 software
5.1.1 core Tables
Fwa -- user's Work Area
Fjp -- interrupt Level Junk Storage
Fdi -- dcu initialization Table
Fdp -- drum Parameter Table
Fhp -- hitching Post Table
Eps -- executive Parameter Storage Table
Hel -- i/o device Time-Out Audit Timing Table
Cht -- user's Call History Table
5.1.2 Drum Tables
None
5.1.3 Registers
Xr1 -- work Area Address
Xr2 -- dcu identity
5.2 HARDWARE
DCU cleared: initialized; or placed in spill mode.
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F30X01 Not used
F30X02 Called by Interrupt Cause and Analysis Program for
processing of a DCU ready interrupt. F30X03 Called by Interrupt
Cause and Analysis Program for processing of a DCU error interrupt.
F30X04 Called by DMS Isolation to process a DCU ready interrupt
obtained from a retry of a job. F30X05 Called by DMS Isolation to
schedule a user's error program and clear the DCU in use. F30X06
Called by DMS isolation to re-execute a job on a specified DCU.
F30X07 Called by I/O Device Time-Out Audit to notify the handler
that a DCU has failed to generate a response in the normal amount
of time. F30A02 Called by Drum Handler Subroutines II (F41) to scan
the queues of an idle DCU. F30A03 Called by Drum Scheduler (F29) to
schedule a user's error program. F30A07 Called by Drum Handler
Subrouting I (F40) to schedule a user's next program. F30A10 Called
by Drum Handler Subroutines II (F41) to clear down a DCU and its
associated software. F30A11 Called by Drum Scheduler (F29) to
initiate a job on an idle DCU. F30A15 Called by Drum Scheduler
(F29) to clear a job for execution on a specified DCU.
6.2 exit points
return is always to the caller, regardless of which entry point is
utilized; thus each entry is in essence a closed subroutine.
7. SUBROUTINES USED Entry Functional Names Points P01X01 DMS
Isolation -- Called to handle DCU errors on which no Maniac
requests exist. L09X01 Maniac MANCHK Processor -- Called to obtain
Maniac information on a DCU error sense line. F03X01 UNLINK --
Called to unlink a task from one of the DCU queues. F02X01 LINK --
Called to link a job to a queue. F05X01 WADROP -- Called to return
a user's work area to the spare queue. P02X01 DMS Isolation Ignore
Error and Return Routine -- Called to handle user errors on DCU's
which have been allocated to a drum -- drum transfer. P01X03 DMS
Isolation Response/No Job Handler -- Called to handle an interrupt
from a DCU on which no job is in progress.
8. NARRATIVE
8.1 discussion
all logic required for actual access to the DCU hardware is
contained in this module. Those functions which are characteristic
to all system device handlers (e.g., MANIAC processing, ready and
error interrupt handling, etc.) are included, as well as functions
characteristic to the drum alone.
Concerning error handling: the decision logic associated with
isolating possible faults and performing necessary hardware
configuration is the sole responsibility of the DMS Isolation
Program. The Drum Handler provides several utilities that are
required for this process; e.g., retries, scheduling the user's
error program, processing a `pseudo` ready interrupt (i.e., success
occurred on a retry), etc. These utilities are incorporated into
the handler because:
1. The handler already contains the necessary code for these
procedures (i.e., it is required for normal job processing)
and/or,
2. Such an arrangement allows the handler to maintain more
efficient and accurate control of the drum as a resource.
8.2 TECHNIQUE
The major criterion in designing the handler was minimization of
the real-time requirement for call-processing-oriented accesses. To
effect this, the call-processing path is coded separate (where
feasible) from the more general processing paths. Since this
technique tends to increase the core storage requirement (also at a
premium) a secondary effort was made to minimize the additional
core storage required. As a result, the handler is organized into a
group of 14 functional subroutines, in order to consolidate
redundant functions and promote organization.
The result of employing these techniques was to effect the required
through put while actually decreasing the core storage
requirement.
Functionally, the subroutines are organized as follows:
F30a01 -- set up the DCU initialization table as required for a
given access to drum.
F30a02 -- scan the queues of an idle DCU pair in search of jobs
awaiting execution.
F30a03 -- schedule a user's error program with a specified error
code.
F30a04 -- place a work area on a specified executive work queue
F30a05 -- not allocated.
f30a06 -- process spill data following a DCU spill.
F30a07 -- schedule a user's next program.
F30a08 -- initiate a required DCU spill.
F30a09 -- transfer data from the ITE into the user's specified
buffer area.
F30a10 -- clear down a DCU and its associated software
indicators.
F30a11 -- initiate the specified job on the specified DCU.
F30a12 -- initialize the specified DCU.
F30a13 -- start the I/O device time-out audit on the specified
DCU.
F30a14 -- perform interrupt processing common to both ready and
error interrupts (i.e., handle response/no job, maintenance abort
of a user's job, Maniac reset and ignore, Maniac direct or
scheduled reroute, etc.).
F30a15 -- verify that a specified job can be executed on a
specified DCU, in view of that DCU's system status..
Such an organization allows the handler to function in a minimum
amount of core, while not significantly compromising the real-time
objective. In addition to being utilized internally, these
subroutines are also utilized by other drum modules (i.e., F29, F40
and F41) in order to satisfy interface requirements and promote
core reduction.
As noted previously, every practical attempt is made to segregate
call-processing accesses from other access types. Currently the
only method available for doing this is to use the user's access
mode. Each access to drum is assigned one of several access modes,
which identifies access for certain processing characteristics. For
call processing, the assigned access mode is zero; unfortunately,
many other non-call-processing accesses also utilize this access
mode, whose processing requirements may vary radically from those
normally attributed to call-processing. Therefore, the user's
access mode represents at best a `rule-of-thumb` for routing drum
requests into dedicated code paths. Nevertheless, use of this and
other techniqes has enabled attainment of the throughput and core
reduction goals.
F31 -- figs. 113-113b
1. name
communication Control Register (CCR) Scheduler
2. PURPOSE
In a general sense, the CCR hardware and software is for the
purpose of enabling communication between the Data Processing Unit
(DPU) and the Marker subsystems (Originating Marker -- OM and
Terminating Marker -- TM). In this context, F31 is the initial CCR
processor (scheduler) of DPU software programs (clients) that
desire to: (a) command the TM hardware for call processing
purposes, (b) command and/or interrogate the CCR, OM, or TM,
hardware for maintenance purposes.
The CCR, OM, or TM reply to a (F31 client) maintenance
interrogation or confirmation/response to a maintenance command is
always in the form of data words put in the CCR hardware, this
answer data will then be loaded into the F31 client work area. The
TM's final "response" to a (F31 client) call processing command, is
also in the form of data words put in the CCR hardware and then
loaded into the F31 client work area (actually, this "response" is
mostly the TM's indication that it has, or has not, completed the
conversation path).
On the other hand, one type of communication between the marker and
the DPU does not involve a F31 client; this is when the OM sends
call processing data to the DPU. This communication is initiated
solely by the OM and reaches the DPU without going through a F31
client.
F31, more specifically schedules clients with I/O requests, for
entry into the CCR Handler program F32, so that these requests may
be carried out. As stated above, these clients can be divided into
two general classes: Requests for normal call processing involving
the TM, or requests for maintenance upon CCR hardware, the OM, or
the TM.
3. functions
module F31 performs the following functions:
a. Checks that client requests are proper and fulfillable.
b. F31X01 classifies clients into one of the three following groups
for entry into the CCR Handler program (the clients are actually
put into 1 of 5 queues): (1) Maintenance on the CCR frame hardware,
(2) Maintenance on the OM, or TM and (3) normal call processing
involving the TM. Groups 1 and 2, above, are of a higher priority
than group 3.
c. F31X02 allows a quick status snapshot of the CCR frame hardware,
for CCR maintenance. In this case the client is branched directly
(not scheduled) to the CCR Handler, to obtain the data.
d. During the CCR performance of the client I/O task, the client
may, or may not, have control returned (as he requests). When
control is not returned to the client, during the performance of
the I/O task, then F31 branches to E01X04 so that other DPU work
may continue while the I/O task is being performed (the I/O task is
like a closed subroutine). After completion of the I/O task, the
events described below (item (e) will occur.
e. When F32 (and/or other CCR software) completes the I/O task for
a "F31 client," the NPG (next program client requests) is then
given control: this NPG is a F31 client parameter (selection), and
may be merely a return to the client himself. In the event of an
error occurring before completion of the I/O task, the ERP (error
program client requests) is given control via E01X01. After the I/O
task is completed, then a CCR software program (usually F32 or F31)
calls F38 which in turn calls the Executive scheduler E01X01, which
schedules the NPG.
4. inputs
4.1 software
4.1.1 core Tables
Eps -- (also an output table) Executive Parameter Storage
Esl -- (also an output table) Executive Storage Location
Fat -- ccr address Translation
Fsw -- work Area Size
Fwa -- (also an output table) Executive Interface Work Area
Fwd -- tm sent Information
Hst -- system Status
4.1.2 Drum Tables
None
4.1.3 Registers
X1 -- work Area Identity
X3 -- entry Line Number
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Eps -- (also an input table) Executive Parameter Storage
Esl -- (also an input table) Executive Storage Location
Fwa -- (also an input table) Executive Interface Work Area
Has -- mcr audit
Swb -- ccr dump Area B
5.1.2 drum Tables
None
5.1.3 Registers
X1 -- work area identity if client of F31X02 requests return
5.2 HARDWARE
None
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F31X01 Called by
clients wishing to communicate with the markers (OM or TM) by using
the CCR; or clients just wishing to communicate with the CCR only
F31X02 Called by clients wishing to obtain a quick status dump of
the CCR A or CCR B hardware unit. 6.2 EXIT POINTS Exit Reasons for
Exit Points E01X04 This exit returns control back to the Executive,
so that the usual DPU software programming can continue. Return to
Caller When exit E01X04 is not used, then return is always made to
the client of F31. 7. SUBROUTINES USED Entry Functional Names
Points F36X06 Places the status of CCR A or B into table SWB so
that the F31X02 client may receive it F02X01 Links the F31 client
to one of the five queues for entry into F32X01 F38X01 Used by
entry line F31X02, when F31 client does not ask for return F38X01
will schedule the program that this client wants to run (NPG).
F38X03 Used by entry line F31X02 and F31X01 to schedule the error
program (ERP). F32X01 Initiates the I/O task which is requested by
the F31 client. This program is not a usual F31 subroutine in the
sense that once initiated by F31, it may start an I/O task for the
highest priority F31 client and this task (being I/O) can continue
after control is returned to F31. Software processing and this CCR
I/O can occur at the same time, unlike the case of two software
programs where only one can have control at a time.
8. NARRATIVE
8.1 discussion
8.1.1 entry f31x01
the first check by F31 is to determine if the client desires: (1) a
Marker operation (which, of course, makes use of the CCR to
communicate with the marker), or (2) a CCR-only maintenance
operation. Checks are then made to ensure that a large enough work
area had been asked for by the client (depending on the type of CCR
or marker operation): if not, error field FWAEIO is set to 5. In
the case of a marker operation, when the client specified marker is
not in the present EAX office, error field FWAEI0 is set to 3. In
both of the above error situations, F31 will call subroutine F38X03
so that the client specified error program can be scheduled. After
F38X03 has scheduled the error program, F31 continues with other
client processing. Next, clients are classified into one of
hardware queues: queue 0 = CCR maintenance operation; queue 1 = OM
or TM maintenance operation; queue 2 = TM non-maintenance operation
(pair one); queue 3 = TM non-maintenance (pair 2); queue 4 = TM
non-maintenance operation (pair 3). The order of queue priority is
as follows: queue 0 is highest; queue 1 is second, queue 2, 3, and
4 are of third order priority. The placing of clients into the
above five queues is based on the values set in field FATQNU (for
OM's and TM's); except that a TM maintenance operation is put into
queue 1 rather than 2, 3, or 4. The decision to place a TM
operation into queue 1 (rather than 2, 3, or 4) is based on its
being a maintenance (high priority) rather than a call processing
(low priority) operation (when field FWAPQT is 1, then the client
is a high priority maintenance job, and the TM Client is put into
queue 1). A CCR maintenance operation is placed into queue 0 when
it is identified as such (by a 1 in field FWAOPT). When an OM
operation (queue 1) is to be performed, a check is made to
determine if the client has also asked for a high priority request
(field FWAPQT set to 1); this high priority request should be made
for all maintenance jobs, and an OM operation should be always be a
maintenance job for F31 clients. If the high priority request is
not made, then error field FWAEIO is set to 4, indicating a client
mistake, and subroutine F38X03 is called. For TM operations, as
stated above, field FWAPQT may be set to indicate either high or
low priority (maintenance or non-maintenance).
After classifying client into one of the above five queues, this
queue data is placed in junk storage FJE004, and a bias number is
added, FQ036. At this time subroutine F02X01 is called to place the
client job into the previously determined queue, for entry into the
CCR Handler F32. Next, F32 is momentarily given control to allow it
to initiate an I/O task for the highest priority job in its queues,
(probably not the current F31 client), F32 may or may not be able
to take advantage of this opportunity; if it does then it can
initiate the I/O task and then pass control back to F31. Whether or
not F32 can initiate an I/O task, control is shortly passed back to
F31 (the main purpose of this program step, which occurs during
every use of F31, is to allow every opportunity for the initiation
of a F32 I/O task-which once initiated can continue on its own,
while other processing continues by F31). The next program step by
F31 is to return control to the client, if the client has asked for
this option (field FWADGT set to 1); this allows the client freedom
to perform some other job while F32 is working its way around to
performing the client I/O task. When the client does not request
control, then: (1) If the client was a non-resident program and he
requested this non-resident area held for him, it is held;
otherwise it is not held, and (2) Program E01X04 is given control
so that other DPU processing may continue.
8.1.2 ENTRY F31X02
This entry line is used by clients wishing to obtain a quick status
dump of CCR A or CCR B hardware.
First a check is made to ensure that the work area is large enough;
if not, error field FWAEIO is set to 5, and if the client does not
ask to be returned to, then the client specified error program is
scheduled by F38X03 (this error program may be the client himself).
If the client wants to be returned to (field FWADGT = 1), then he
is and the error program is not scheduled. In any case (client
return or not), the usual end flow of the program is the same: (1)
F32 momentarily called to allow initiation of any pending I/O task
- this task would not relate to a F31X02 client, (2) F32 release of
non-resident area, if appropriate, and (3) calling of E01X04 to
allow other DPU processing to continue. Note that other errors
during F31X02 follow the same flow (other errors: CCR out of
service, FWAEIO = 1; CCX error, FWAEIO = 1).
Assuming no errors, the client requested hardward unit A or B is
selected and its status is looked up in core table HST. The status
data is loaded into table SWB (by subroutine F36X06) where the
client may access it. After this, when the client does not directly
ask for a self-return, subroutine F38X01 schedules the NPG (which
may also be just a return to the client; if client return is
requested, then the NPG is not scheduled. In any case, the final
sequence by F31 is the same as for the above error sequence: (1)
Calling of F31 to allow any current (but unrelated) I/O task
initiation (2) F31 release of nonresident area, if appropariate,
and (3) scheduling of E01X04.
8.1.3 input flow
this section lists the type of request that a F31 client may make
of the CCR software programs (principally, the CCR scheduler F31
and the CCR Handler F32) and thereby indicates the general
functional flow involved in fulfilling these requests. The input
which an F31 client must supply can be broken down into three
areas: (1) Client input options; covered in a general way, in the
description of input parameters (2) Client supplied input data, and
(3) General input restrictions for F31 clients, not covered in
other input parameter documents.
These three areas are listed below:
a. Client Input Options of Special Importance.
1. P1. The identity of the next program to schedule at the
completion of the I/O request (for a F31 client, the I/O task would
be completed by F32; for F31X02 client, the task would be completed
by F31). This parameter is not needed when the client is finished
with his overall job after the completion of the I/O task. This NPG
information is stored in field FWANPG. 2. P7: The logical request
number which specifies the mode of data transfer to employ. These
detailed options, for the F31 client, are listed in document
D-3.44.21* appendix A: which covers the pertinent fields of core
table FWA, dealing with the control of various I/O devices, (a F31
client would be employing the OM, TM and/or CCR). Some of the most
important P7 options are described below, along with the name of
the FWA field that relates to the option.
a. Enabling of the ability to specify a particular OM or TM:
contained in field FWASMR. Specification of the exact OM or TM is
accomplished in table FWD (see paragraph 8.1.3, (a), (2),
below).
b. Specification of a particular CCR (CCR A or CCR B): contained in
FWACRI and FWASCR.
c. Specification that the transmission be done in prime mode:
contained in FWASMP.
d. Specifying CCR data dumps (status and data data) before and
after the message is sent to the marker (OM or TM) and also after
the message is received back from the marker: contained in
FWADMC.
e. The ability to indicate that the client (who is performing
maintenance) is using an OM to simulate calls entering the EAX
office, and that if a malfunction occurs, maintenance recovery
routines should be called: contained in FWAVTS.
f. Specification that should the client requested OM be found to be
not on-line, then a standby CPD (control pulse directive) will or
will not be issued: contained in FWASOM.
g. Specification of special modes of data transfer and scheduling
in marker operations (includes direct commands to the markers):
contained in FWACDR.
h. Specification of special modes of data transfer and scheduling
in CCR operation, a 0 or 1 in this field specifies a marker or a
CCR operation: contained in FWAOPT.
Note: when unload-CCR-status-word is specified, (an option of a
F31X02 client) and return to client (FWADGT = 1) is also requested,
the scheduling of the NPG is not performed by F31.
i. Client can specify timer size he wants in field FWATMS. If the
client asks for timer size 5, and also requests FWACDR = 2 or 4,
then he has also specified a Schedule on Idle. This means that when
the marker is idle, the program will know that the client job is
completed; this is faster than the usual timeout method of knowing
that the client job is completed.
3. P8: The program type, which specifies the type of action to be
taken concerning return of control, scheduling of other programs,
release of work area, and control of the non-resident area (see
Document D-3.44.21*, appendix B, which describes the pertinent
field FWAPGT).
4. P9: The priority queue type, which specifies the type of queue
to link the client request to, for entry to F32.
b. Client Supplied Input Data
1. When a F31 client is using a TM for either call processing or
maintenance purposes, he may also supply Register Junctor Identity
(RJI) date (put into field FWARJI) and Register Sender Instruction
data (put into field FWARIN); note that when FWARIN is set to 0,
F31 will not act on this field: that is, the field will not be sent
to the Register Sender for translation (as in OM maintenance). In
the case of TM maintenance the client may employ field FWAVTS (when
he is simulating a normal call entering the EAX office) so that in
the event of an error, Maintenance recovery routines will be
employed - rather that call processing recovery routines. 2. When
the client wishes to send maintenance data to the OM, or TM, or to
send call processing data to the TM, he must employ core table FWD
words 00 through 03, among other options, this table allows
selection of a particular OM or TM (the client must have employed
field FWASMR so that table FWD can be used to specify an exact OM
or TM, see paragraph 8.1.3, (a); (2), a. This four-word area of
table FWD is set up to match the input format of the markers: the
first two data words for OM request; and all four data words for TM
requests.
c. General Restrictions to clients of F31.
1. F31 must be called from base level, it cannot be entered in the
interrupt mode.
2. Depending on the nature of the client requests, a large-enough
work area must be asked for by the client to hold all pertinent
data. The minimum size requirements for all clients are listed
below:
a. All clients using entry line F31X02 must have a minimum of a
28-word area.
b. F31X01 client: If CCR status dumps are requested (FWADMC = 1),
or if a CCR operation is requested (FWAOPT = 1) with a CCR-to-CCR
transfer (FWACDR = 6 or 7), then a minimum of a 40-word work area
is required.
c. F31X01 client: When a CCR status dump is not requested (FWADMC =
0) and a CCR operation is requested (FWAOPT = 1), other than a
CCR-to-CCR transfer (FWACDR = 1, 2, 3, 4, or 5: for a non
CCR-to-CCR transfer), then a minimum of a 28-word work area is
required.
d. F31X01 client: When a CCR status dump is not requested (FWADMC =
0), and any marker operation is requested (FWAOPT = 0), then a
minimum of a 20-word work area is required.
3. All F31 clients, other than TM call processing requests, should
be marked as high priority (FWAPQT = 1). In the event a OM request
is not marked high priority, F31 will give an error return because
an F31 client should only be making a maintenance request regarding
an OM.
4. If the client is non-resident (non-core-resident) and his error
program (P3) is scheduled, he will not be allowed to remain in
control of the non-resident area, even if he has asked to be. If
the error program is non-resident, it must be read from the
drum.
8.1.4 OUTPUT FLOW
The following description lists the type of output that an F31
client receives back from the CCR software programs (principally
the F32 and F31 programs) and thereby indicated the general
functional flow involved in fulfilling the F31 client request.
Types of outputs that an F31 client receives are:
1. Error outputs, principally from F31 and F32,
2. data outputs from F32, and
3. "Indirect" outputs from F31.
These three areas are listed below:
a. Error outputs to F31 clients are contained in field FWAEIO
(program F31 and F32 send the majority of these error outputs).
Error outputs coming from F31 only, back to client, are: field
FWAEIO = 1, 3, 4, or 5.
Another type of error output, actually a special maintenance data
output to F31 clients, is contained in an overlay of the FWAEIO
field: Maintenance data field FWAMDA (consists of bits MD1 through
MD5) and bit FID.
When bit FID IS 1, field FWAMDA is being presented, rather than
field EIO, and the five bits that comprise it must be interpreted
as individual bits, rather than one binary number. Specifically,
bit FID is 1 when a maintenance request is being processed (an F31
client from queue 0 or 1) and field MDA is interpreted as follows
(depending on the exact type of maintenance being performed by the
F31 client and the options he selects):
(1) Field FWAMDA (bits MD1 through MD5) Definition for given F31
Clients in Queue 1. a. OM maintenance client using FWACDR=1 option
(SR data) No-error is usually indicated by this
______________________________________ output Bit MD1 1=CPD
(control pulse directive sent out 1 from CCR. Bit MD2 1=Data
received from marker 1 Bit MD3 1=Marker malfunction 0 Bit MD4 A 1
is inappropriate * 0 Bit MD5 A 1 is inappropriate 0
*"Inappropriate" means that a 1 occurring under these conditions
indicate some unknown problem (for bit MD4 it is probably a sign of
marker error).
b. OM maintenance client using FWACDR=2 option (schedule on fault
or timeout): No-error is usually indicated by this
______________________________________ output: Bit MD1 1=Data sent
out from CCR 1 Bit MD2 1=Data received from marker 1 Bit MD3
1=Marker malfunction 0 Bit MD4 When marker is on-line 1, if marker
is on-line. 1=standby interrupt rec'd from marker 0, if marker is
off-line. When marker is off-line a 1 is inappropriate Bit MD5 If
client takes option,** 1, if either option 1=status dump provided
by is taken. CCR. If client takes option** 1=marker idle
(indicating job final) 0, if no option taken. If option not taken a
1 is inappropriate **FWADMC=1 for status dumps, timer size 5 and
FWACDR=2 or 4 for marker idle
c. OM maintenance client using FWACDR=3 option (schedule on
No-error is usually indicated by this
______________________________________ output: Bit MD1 1=Data sent
out from CCR 1 Bit MD2 1=Data received from marker 1 Bit MD3
1=marker malfunction 0 Bit MD4 When marker is on-line 1, if marker
is on-line 1=standby interrupt rec'd from marker 0, if marker is
off-line. When marker is off-line a 1 is inappropriate. Bit MD5 If
client takes option, 1, if option is taken. 1=status dump provided
by CCR 0, if no option is taken. If option not taken, a 1 is
inappropriate. d. OM maintenance client using FWACDR=4 option
(simulate No-error is usually indicated by this
______________________________________ output: Bit MD1 1=Data sent
out from CCR. 1 Bit MD2 1=Data received from marker 1 Bit MD3
1=marker malfunction 0 Bit MD4 When marker is on-line, 1, if marker
is on-line 1=standby interrupt rec'd from marker. 0, if marker is
off-line. When marker is off-line, a 1 is inappropriate. Bit MD5 If
client takes option, 1=status dump provided by 1, if option is
taken. 0, if no option is taken. If client takes option, 1=Marker
idle (indicating job finished). If no option taken, a 1 is
inappropriate. e. OM maintenance client using FWACDR=5 option
(reset CPD). No-error is usally indicated by the following output:
______________________________________ Bit MD1 1=CPD sent out from
CCR 1 Bit MD2 A 1 is inappropriate 0 Bit MD3 1=Marker malfunction.
0 Bit MD4 A 1 is inappropriate 0 Bit MD5 A 2 is inappropriate 0 f.
TM maintenance client using FWACDR=1 option (SR data): No-error is
usually indicated by the following output:
______________________________________ Bit MD1 1=CPD sent out from
CCR. 1 Bit MD2 1=Data received from marker 1 Bit MD3 1=Marker
malfunction. 0 Bit MD4 A 1 is inappropriate. 0 Bit MD5 A 1 is
inappropriate. 0 g. TM maintenance client using FWACDR=2 option
(schedule on fault or timeout): No-error is usually indicated by
the following output: ______________________________________ Bit
MD1 1=Data sent out from CCR. 1 Bit MD2 1=Data received from
marker. 1 Bit MD3 1=Marker malfunction. 0 Bit MD4 A 1 is
inappropriate 0 Bit MD5 If client takes option, 1=status dump
provided by 1, if option is taken. 0, if option is not taken If
option not taken, a 1 is inappropriate. h. TM maintenance client
using FWACDR=3 option (schedule on No-error is usually indicated by
the following output: ______________________________________ Bit
MD1 1=Data sent out from CCR. 1 Bit MD2 1=Data received from
marker. 1 Bit MD3 1=Marker malfunction. 0 Bit MD4 A 1 is
inappropriate 0 Bit MD5 If client takes option, 1=status dump
provided by 1, if option is taken. If option not taken, a 1 is
inappropriate. i. TM maintenance client using FWACDR=5 option
(reset CPD): No-error is usually indicated by the following output:
______________________________________ Bit MD1 1=CPD sent out from
CCR. 1 Bit MD2 A 1 is inappropriate. 0 Bit MD3 1=Marker
malfunction. 0 Bit MD4 A 1 is inappropriate. 0 Bit MD5 If client
takes option, 1=status dump provided by 1, if option is taken. 0,
if option is not taken. If option is not taken, a 1 is
inappropriate. (2) Field FWAMDA (bits MD1 through MD5) Definition
for an F31 client in Queue 0. CCR maintenance client employing CCR
to CCR transfer (FWAOPT=1, and FWACDR=6 or 7): No-error is
indicated by the following ______________________________________
output: Bit MD1:1=Data transmission initiated from CCR (to other
1CR). Bit MD2:1=Receiving CCR received data successfully. 1 Bit
MD3:1=Receiving CCR did not get data successfully, but status dumps
still provided. 0 Bit MD4:1=Data not successfully sent out from CCR
(to other CCR), but status dumps still provided. 0 Bit MD5:1=Data
successfully sent out from CCR (to other 1CR).
b. Data output concerning TM call processing, and OM, TM, or CCR
maintenance requests are contained in table FWC words 00 through
03. As in the case of input table FWD, output table FWC is set up
to match the output format of the markers: two data words for OM
outputs and four data words for TM outputs.
The other major output data is contained in words 00 through 03 of
tables SWA, SWB, SWC, SWD and SWE. This information is data
concerning certain CCR maintenance operations (this includes all
CCR status dumps). Output data from the OM maintenance operations
concerning a F31 client (performing maintenance) that is simulating
a normal OM call processing request, is contained in the following
fields: (1) FWARJI, which contains the RJ identity, and (2) FWACHT,
which contains the call history table address.
c. Indirect outputs from F31 are changes in certain work area
fields that F31 makes during the course of processing a client.
These changes are not usually thought of as outputs but the changed
field can be made use of by F31 clients, if desired. The following
fields may be altered F31 clients: FWANPG, FWAELN, FWAPRI, FWAFEP,
FWAFEL, and FWAFPR, and FWAFPR.
8.2 technique
not applicable.
F32a -- figs. 114-114h
1. name
f32a -- ccr i/o initiation handler
2. purpose
the purpose of F32A is to centralize control of hardware, to
perform operations necessary to prepare the markers and CCR for
operation and initiate data transfers between the CPU and the CCR
and between the CCR and the marker.
3. FUNCTION
A. determine if the on line active CCR is available for output.
B. determine if an reconfiguration of the CCR's is required and, if
so, call F36X08 -- CCR Reconfiguration Subroutine.
C. determine if a request for I/O is queued for an idle device.
D. unqueue the request.
E. initiate the request (which may involve interlocking between a
register junctor and a terminating marker.
F. interface with CCX recovery to detect and isolate faults in
CPU-CCX-CCR path.
G. return to the calling program.
H. f32x05 is provided to enable retries of transmission a
terminating marker by F37-CCR Error and Recovery.
I. f32x07 is a closed subroutine whose function is to attempt to
place a specified CCR MOS request CCR Isolation on the CCR, and set
a unit maniac just ignore on the device. It then will call F36X08
to achieve reconfiguration and return caller.
4. INPUTS
4.1 software
4.1.1 Core Tables
Els--exec. storage Location Table
Fat--ccr add trans. Table
Fcc--om-rj identity
Fhp--hitching Post Table
Ers--register Save Table
Fjp--interrupt Level Junk
Fq0-- --
fra--queue Root Table
Fwa--exec. interface Work Area
Fwb--cp reg/SNOR Memory Image
Fwd--tm sent Information
Hcd--diacon config. Table.
Hcx--ccx parity Error Flag
Hel--i/o abort Entry Line
Hpp-- --
hst--system Status Table
Spe-- --
sta-- --
swb--ccr dump Area B
4.1.2 drum Table
None
4.1.3 Registers
None
4.2 HARDWARE
None
Entry Points
F32x.phi.1 -- scan I/O Queues
F32x.phi.5
ersked
speccr
loadcr
status
chkcpd
start
f32x07 -- set CCR MOS, Calls DIACON, set MANIAC to just ignore and
reconfig. CCR's
5. OUTPUTS
5.1 software
5.1.1 Core Tables
Fcc -- om-rj identity
Fwa -- exec. interface Work Area
Fwb -- cp reg/SNOR Memory Image
Hak -- system Clear
Swb -- ccr dump Area B
Swd -- ccr dump Area D
5.1.2 drum Tables
None
5.1.3 Registers
None
5.2 Hardware
None
6. Controls
6.1 Entry Points
F32x01 -- scan I/O Queue
F32x.phi.5
f32x.phi.7 -- set CCR MOS, CALL DIACON, Set Maniac to just ignore,
and reconfigure CCR's
6.2 Exit Points
Return is made to client.
7. Subroutines Used
E01x03 -- dpu scheduler
E02x01 -- 1 cap level 1 (Start Interval Timer)
F01x01 -- rs scan interlock
F02x01 -- link to mkr maint. queue
f03x01 -- unlink work area from i/o queue
f04x01 -- work Area Assignment
F02x03 -- link work area back to I/O QUEUE
F34x01 -- cr handler 2
F36x08 -- ccr reconfiguration: CR Subroutine 1
F38x04 -- abort I/O TASK: CR Subroutine 2
F38x.phi.3 -- schedule ERROR Program
L01x04 -- mainf interrupt access
l20x01 -- elt, diarot, diabrt
l50x02 -- set Unit Maniacs
S31x03 -- channel Multiplex Recovery
S31x01 -- clock CCX Errors
8. NARRATIVE
8.1.1 discussion
when a call is received by F32X.phi.1, the standard status word of
the online active CCR is dumped by F36X.phi.6. If the CCR is idle
and scanning, a check for a reconfiguration request is made. If the
CCR is not idle and scanning the time out audit bit is set and the
system returns to the calling program. When reconfiguration is
required, it is accomplished by F36X.phi.8. Then a check is made
for a line transmission request by the Marker Fault Interrupt
Processor (52), if so the Maniac is set to reset and ignore. Checks
are now made for CCR requests, marker maintenances requests, and
termination requests (in that order). If none of these are
requested, the system is returned to the calling program.
Diagnostic Requests
In the event that the CCR queue are not empty (CCR request A
CCR-CCR transfer is tried. If successful F36X.phi.5 provides a sink
for CCR status dump in SWD and sets up the CCR's. F36X.phi.6 then
provides a source status dump in SWB. Four data words are loaded
and sent to the other CCR and the system returns to the calling
program. If the CCR transfer was unsuccessful, the status words are
dumped into SWB and the data words are dumped into FWC. F38X.phi.1
then schedules the next program and the CCR request is checked
again.
If there is a marker maintenance request, a marker is selected to
be tested. In the case where there are no markers available, the
check for a marker maintenance request is made again. When there is
a marker available, a check for a CPD request is made. In the case
of a CPD request, the CPD is sent. Then the check for the
termination request is made and the system returns to the calling
program. When there is no CPD request, a check is made to determine
if this is an OM or TM request. If a status dump in SWB is
requested, it is accomplished by F36X.phi.6. If this is a OM
request, two words are loaded and sent to the OM and the system
returns to the calling program. If this a TM request, a check is
made to see if RJ interlock is required. If there is trouble with
the interlock, EIO is set to 7 and the marker maintenance request
is check again. If there is no trouble, four data words are loaded
and sent to the TM and the system returns to the calling
program.
If there is a termination request, a check is made to see if the TM
is idle. If not idle, the termination request is check again. When
idle, a TM is picked and checked for its availability. If not
available, the termination request is checked again. If available
an RJ interlock is executed if it is required. If there is trouble
in the RJ interlock, EIO is set to 7, F38X.phi.3 schedules error
program, and the termination request is check again. If there is no
trouble, four data words are loaded into the CCR and sent to the
TM. Now the system returns to the calling program.
F32b -- figs. 114i-114n
1. name
f32b-ccr ready interrupt processor
2. purpose
module F32B is provided to handle all ready interrupts generated by
the CCR hardware.
3. FUNCTION
A. provides maniac functions reroute and reset and ignore.
B. handles originations, including performing RJ translation,
interlocking RJ with originating marker, and scheduling C.phi.1
with the call history table for the RJ selected by the OM.
C. completes termination attempts by putting 4 data words from
terminating marker in users work area and scheduling his next
program.
D. provides handling for diagnostic requests, including data words,
status dumps options and scheduling options.
E. calls F32X01 to attempt to initiate next I/O request.
F. return to ICAP.
4. inputs
4.1 software
4.1.1 Core Tables
Chq -- program generated INDEX
Fcc -- om-rj identity
Fhp -- hitching Post Table
Fwa -- exec. interface Work Area
Fwc -- tm received information
Hab -- 6 bit error count B Table
Has -- mcr audit Table
Hcd -- diacon configuration table
Hcs -- cxx parity error flag
Hmd -- marker Matrix Comb Table
Hmn -- maniac Condition Table
Ncw -- update control word
Swa -- ccr dump Area A
Swb -- ccr dump Area B
Swc -- ccr dump Area C
Swe -- ccr dump Area E
4.1.2 drum Table
None
4.1.3 Registers
None
4.2 Hardware
None
5. OUTPUTS
5.1 software
5.1.1 Core Tables
Cha -- scheduling Information
Chc -- om data frame record
Chq -- program generated index
Fjp -- interrupt Level Junk
Fom -- ccr handler Control
Fwa -- exec. Interface Work Area
Fwc -- tm received information
Hel -- i/o abort entry lines
5.1.2 Drum Tables
None
5.1.3 Registers
None
5.2 Hardware
None
6. Controls
6.1 Entry Points
F32x.phi.2
6.2 exit Points
Return is made to ICAP
7. subroutines Used
c.phi.X.phi.1 -- Class of service initialization
E.phi.1x.phi.1 -- schedule F.phi.7X06 to Output
(DPU Scheduler)
F.phi.4x.phi.1 -- work Area Assignment
F.phi.7x.phi.6 -- schedule Pre out
F.phi.2x.phi.1 -- link to CPU Queue
Schedule C.phi.1X.phi.1 with CHT as Work Area
F.phi.2x.phi.3 -- link WA back to I/O Queue
F14x.phi.1 -- call History Table Address Calculation
F32x.phi.1 -- scan I/O Queue
F32x.phi.3 -- return to ICAP
F33x.phi.1 -- rj translation
F36x.phi.2 -- handles Reroute
F36x.phi.6 -- cr subroutine: Dump Data into FWC and
Status into SWE
F38x.phi.1 -- schedule Next Program
F38x.phi.3 -- schedule Error Program
F38x.phi.4 -- abort I/O Operation
K.phi.5x.phi.1 -- om-cfs recognition Test
L20x.phi.5 -- elt, diarot, diabrt
l.phi.9 -- --
s31x.phi.1 -- check CCX Errors
8.1 DISCUSSION
This module handles data transmissions from CCR and markers to the
computer central processor. The first case to be treated here will
be a call processing origination. F32X.phi.3 is entered by the
interrupt cause and analysis program for a CCR ready interrupt.
F32B checks to see whether any MANIAC conditions exist on the ready
interrupt. The I/O time-out audit is reset for the particular ready
interrupt. The standard status word and data words .phi. and 1 are
gathered. At this point originations are separated from
terminations. The CSO field is interrogated to determine if any
blockage was indicated.
Next, the register junctor identity is translated from the marker
data words. Then the call history table address associated with the
call is calculated. The register sender memory is instructed and
call history table initialized. Marker malfunction interrupts are
checked for any MANIAC's. And C.phi.1 (the first call processing
module) is scheduled with the call history table used as a work
area.
The queues are scanned for any other jobs, if one is found it is
initiated if not control is returned to Interrupt Cause and
Analysis.
The second case is data sent from a Terminating marker to the
computer central processor for a termination. Four terminating
marker data words are unloaded from the CCR. The section field of
the TM frame word is altered to correspond with the frame word
passed by call processing. Call processing's next program is
scheduled and the queues are scanned for another job to initiate.
Afterwhich control is returned to Interrupt Cause and Analysis
program.
The third case is that of the diagnostic access. The options for
these accesses are:
1. Schedule upon ready
2. Schedule upon interval timer expiration
3. Reset the marker
4. Send shift register data
After retrieving the standard status word a check is made to
determine whether diagnostic was an originating marker, a
terminating marker or a CCR diagnostic. For a TM or a CCR
diagnostic a status dump is performed.
For marker diagnostics the shift register data access will abort
the job, schedule the next program and scan the queues.
For a fault or timeout with schedule on idle option the originating
marker in question will be reset and the queues will be
scanned.
For test calls an indicator will be set and RJ translation will be
done and call history table address will be calculated except that
C.phi.1 will not be scheduled because this is not a real
origination.
Status dump may be taken if the access indicates. The CCR hardware
is cleared down and reset for further use.
F-33--figs. 115-115a
1. name
f33 -- register Junctor Translation Program Module
2. PURPOSE
This module translates an Originating Marker communication frame,
containing a line matrix R-Unit Outlet identity (LRO) or a trunk
register B-Unit outlet identity (TBO), into the identity of the
connecting Register Junctor (RJ number and Register Sender secton
number). This allows completion of the path from the inlet into the
Register Sender.
3. FUNCTIONS
Module F33 performs the following functions:
a. Determines if the LRO or TBO identity input is within the range
of equipped units and is a valid unit.
b. Looks up, in the RJ translation tables, the local RJ or an
incoming trunk RJ that is valid and connects to the
client-specified LRO or TBO.
c. Returns to the program that requested the translation with the
local RJ or incoming RJ identity (this identity includes the
Register Sender section containing the RJ).
4. inputs
4.1 software
4.1.1 core Tables
Fap -- pointer to Absolute Matrix Table.
Fer -- error Constant Register Junctor Translation Table
Flb -- pointer-to-Line Register Junctors for Office Section 2
Table
Flr -- line Register Junctor Table
Fsa -- absolute Matrix For Subsection 1 Table
Fsb -- absolute Matrix for Subsection 2 Table
Fsc -- absolute Matrix for Subsection 3 Table
Fsp -- pointer-to-Section Tables for Register Junctor Table.
Fta -- pointer-to-Trunk Register Junctor for Office Section 1
Table
Ftb -- pointer-to-Trunk Register Junctor for Office Section 2
Table
Ftr -- trunk Register Junctor Table
Fts -- pointer for Trunk Register Junctor for Selector Section
Table.
4.1.2 Drum Tables
None
4.1.3 Registers
X1 -- work area identity (optional).
Ra -- originating Marker Data Frame word 0.
Rq -- originating Marker data frame word 1.
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
5.1.2 Drum Tables
None
5.1.3 Registers
X2 -- trouble indicator.
Ra -- rj identity
Rq -- indicates incoming RJ or local RJ.
5.2 hardware
none
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F33X01 This entry
point is called via the PGLINK macro to obtain RJ translation as a
closed subroutine.
6.2 EXIT POINTS
Return is made to client.
7. SUBROUTINES USED
None.
8. NARRATIVE
8.1 discussion
the general method used to determine the appropriate local RJ (LRJ)
or incoming RJ (IRJ) output is briefly described here. A lookup in
Table FLR (containing LRJ's) or Table FTR (containing IRJ's) is
made to find the RJ indexed by the input LRO or TBO. In this lookup
process, two levels of indexing are used, first X1 for the section,
then X2 for the matrix, to obtain a pointer to a block of 10 or 20
words in Table FLR or FTR. This block corresponds to a certain
value for SEC, SBS, and MTX. The precise location of the desired RJ
identity within the block is pointed to by the value of the RUO
(local RJ) or BUN and BUO (incoming RJ). Thus, the complete
definition of LRO or TBO identity points to the desired RJ
identity.
In order to establish the final link of the path from the line
group to the local RJ or from the trunk register group to the
incoming RJ, it is necessary to identify the one unique RJ that
connects to the specific RUO (for the trunk register group path),
or to the specific BUO (for the trunk register group path).
Therefore, when F33 is entered with part of an Originating Marker
data frame (data words 1 and 0), containing the identity of an LRO
or a TBO, F33 determines (translates) the identity of the RJ
related to his LRO or TBO.
The complete identity for an LRO consists of the following fields
in an Originating Marker data frame: Section (SEC), Subsection
(SBS), Line Matrix Number (MTX), B-Unit Outlet (BUO), and R-Unit
Outlet (RUO). The TBO consists of the following fields: Section,
Subsection, Trunk Register Matrix (MTX), B-Unit Outlet, and B-UNit
(BUN). The input to F33 also includes the AB group number. When the
value of the AB group is 1 through 5, then the input is an LRO.
F33 returns the RJ identity to the client in the form of the RJ
identity field of Table FWA.
Specifically, the output consists of an RJ number (0 through 191),
and a Register Sender Section number (0 or 1): all RJ's are within
RS section 0 or 1.
When the entry is an LRO, the RJ number identity is located by a
lookup in Table FLR. This table contains a listing for all local
(non-trunk serving) RJ's, and the location of the LRO identity
within Table FLR specifies a particular RJ.
The general block of 10 or 20 words within Table FLR specifies the
section, subsection, and matrix of the LRO which connects to a
given RJ. The same RJ number is at more than one location within
the same data block, because the RJ is connected to more than one
R-Unit. Additionally, the RJ number may be located within several
different data blocks, when the RJ is connected to more than one
matrix. (In the case of the incoming trunk RJ, the connection will
be to subsections and matrices.) Of course, only one RJ matches a
given LRO entry.
The RJ number identity contained in Table FLR also has a validity
bit indicating the useability of the particular RJ and LRO; when
the validity bit indicates unuseability, or when the RJ is not
found or is out of range. Register X2 equals 1, thereby indicating
general trouble.
A similar procedure is followed by TBO's, which connect to incoming
RJ's, as with LRO's, which connect to local RJ's, except that the
IRJ identities are contained in Table FTR. In addition, when the
given TBO is located in an EAX Selector Section, rather than Office
Section, then an additional decoding process must be performed
using Table FAP to determine the altered matrix identity associated
with the TBO input.
8.2 TECHNIQUE
None.
Input to FIG. 115
Ra = data word .phi.
rq - data word 1
output:
xr1 is saved
xr2 = trouble indicator
0 = no error
1 = error
ra = rj identity
rq = fwbirj bit
notes:
1. bun is used for trunk register mtx and ruo for line mtx.
2. at this point, we verify actual values for sec, sbs,mtx.
3. at this point, we verify actual values for ruo(bun) and buo.
f34 -- figs. 116-116a
1. name
f34 -- standby Interrupt and Timer Expiration Handler
2. PURPOSE
The purpose of module F34 is to properly handle Originating Marker
standby interrupts and to provide an entry line used (entered) when
a timer expiration occurs during a diagnostic request.
3. FUNCTIONS
Module F34 performs the following functions:
a. OM Standby Interrupt Handler -- F34X03
1. provides Reset and Ignore and Reroute MANIAC handling for
standby interrupt sense lines.
2. Resets interrupting marker's sense line.
3. Sets indicator for F32A that OM is ready for transmission
(FCCOMT).
4. calls F32X01 to scan I/O request queues.
5. Enables Schedule on Idle option for CCR users (F31 clients).
6. Returns to ICAP.
b. Timer Expiration Handler -- F34X01
1. terminates I/O request and schedules CCR user's next
program.
2. Hitches special timer work area (FIX) to special hitching post
(FHPA22).
3. provides status and data dumps of source and/or sink CCR's, if
not provided previously, for CCR to CCR transfer requests.
4. Calls F32X01 to scan I/O request queues (containing F31
clients).
c. Marker-Malfunction Cleanup Subroutine, F34X05.
1. terminates I/O request and schedules CCR user's next
program.
2. Calls F32X01 to scan I/O request queues.
3. Returns to calling program.
4. INPUTS
4.1 software
4.1.1 core Tables
Esl -- executive Storage Location
Fcc -- crr control Table.
Fhp -- hitching Post.
Fwa -- executive Interface Work Area
4.1.2 Drum Tables
None
4.1.3 Registers
X1 -- Work Area Address (F34X01).
4.2 hardware
none
5. OUTPUTS
5.1 software
5.1.1 core Tables
Esl -- executive Storage Location
Fcc -- ccr control Table
Fhp -- hitching Post
Fwa -- executive Interface Work Area
Fwc -- tm received Information
Swa -- ccr dump Area A
Swc -- ccr dump Area C.
Swe -- ccr dump Area E
5.1.2 drum Tables
None.
5.1.3 Registers
None.
5.2 HARDWARE
None.
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F34X01 Timer
Expiration. F34X03 Standby Interrupt F34X05 Marker Malfunction
Cleanup. 6.2 EXIT POINTS Exit Reasons for Exit Points None Return
to user. 7. SUBROUTINES USED Entry Functional Names Points F36X03
Program Name (F36): CCR I/O F36X08 Handler Subroutines No. 1 F36X06
None F32X01 Program Name (F32A): CCR I/O Initiation Handler. F38X03
Program Name (F38): CCR I/O. F38X0; Handler Subroutines No. 2 L20A
DIARQT -- Request Acceptor.
8. NARRATIVE
8.1 discussion
8.1.1 f34x03 -- om standby Interrupt Handler
After checking MANIAC function and finding none set, F34X03 checks
to see if a maintenance request F31 client is expecting this
interrupt. If no request is in progress, a request to DIACON is
made for maintenance routining of the marker. If a request is in
progress, the sense line is reset and a check is made to see if
transmission has been initiated. If not, FCCOMT is set indicating
the OM is ready for transmission and F32X01 is called to attempt
initiation of the transmission. If the transmission has been
initiated, a check is made to see if the user (F31 client)
requested scheduling or idle. If so, field FWAMD5 is set indicating
that marker went idle and the user's next program is scheduled.
Then F32X01 is called to scan I/O queues.
Finally control is returned to ICAP.
8.1.2 f34x01 -- timer Expiration Handler.
First, the special work area, table FIX, is hitched to the special
work area, hitching post FHPA22. Then the current I/O request is
terminated via a call to F36X03. A check is made to see if the
request was a CCR to CCR transfer. If so, the I/O Audit bits are
reset for both CCR's and a check is made to see if status and data
dumps were provided for the sending CCR (FWAMD5) and the receiving
CCR (FWAMD2). If either bit is reset, a status and data dump is
provided and bits FWAMD4 and FWAMD3 will both be set, thus
indicating that the dumps have been provided. The CCR's are then
restored to their original scan state.
The CCR's are then restored to their original scan state.
8.1.3 F34X05 -- Marker-Maintenance-Cleanup Subroutine
The operation is the same as for F34X01, except that the special
work area is not received input and therefore the work area is not
hitched.
8.2 TECHNIQUE
Not Applicable.
F35 -- figs. 117 - 117h
f35a
1. name: manipulator Request Analysis Routine
2. PURPOSE: This module performs a routine preliminary analysis and
routing of all requests for drum I/O.
3. functions:
a. Provides interlock for proper control of the nonresident
area.
b. Determines the type of access being requested.
c. Performs necessary routing of request for additional processing,
if required.
d. Properly formats the work area and calls the drum scheduler for
non-resident accesses.
4. INPUTS
4.1 software
4.1.1 core Tables
Fwa -- user's Work Area
Eps -- executive Parameter Storage
Fan -- access Number Table
Ftd -- table Directory
4.1.2 Drum Tables
Fcb -- control Buffer Table
4.1.3 Registers
Xr1 -- address of User's Work Area
Xr2 -- user's Access Number
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Fwa -- work Area
Fje -- executive Junk Storage
5.1.2 Drum Tables
None
5.1.3 Registers
Xr1 -- work Area Address
Xr2 -- index to Table Director (FTD)
5.2 hardware
none
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F35X01 Access point
whereby a user requests drum input/output. F35A02 Return from
module F35P, when access number is less than 25 but not a request
predefined for fast access processing. 6.2 EXIT POINTS Exit Reasons
for Exit Points F29X01 Drum Scheduler -- Called when access is
determined to be non-restricted. F35P01 Fast Access Formatter --
Called when access number is less than 25, for determination of
fast-access requirement and associated processing. F35B01 Parameter
Collection Routine -- Called for restricted accesses.
7. SUBROUTINES USED
None
8. NARRATIVE
8.1 discussion
all user access to the drum must be carried out via the
Manipulator. When an access request is first accepted from the
user, a certain amount of common processing is necessary to
properly control system interlock functions and determine the exact
nature of the request so that it can be channeled through required
and appropriate processing.
8.2 TECHNIQUE
Requests entering the Manipulator fall into two general
categories:
a. Requests from drum resident programs.
b. Requests from core resident programs.
In processing requests from drum resident programs, care must be
taken such that the non-resident area is properly controlled. For
this purpose, a special interface is provided between the
Manipulator and the Drum Scheduler/Handler. This will be further
clarified later.
For either drum or core resident requests, however, a determination
must be made as to the specific nature of the user's request; this
is accomplished by use of the user's access number. These access
numbers uniquely identify each request and are predefined by the
user and the Manipulator. These access numbers divide user's into
the following categories:
1. Core resident requests
a. qualifying for fast access
b. qualifying for general access
c. non-restricted
2. Drum resident requests
a. requiring control table access
b. non-restricted
All core resident accesses qualifying for fast access have access
numbers less than or equal to 25. The term "fast access" merely
means that a dedicated code path exists for each request so
designated (note: not all requests with access numbers less than 25
qualify for fast access processing). Requests which do not qualify
for fast access processing are channeled into a generalized, less
efficient processing path.
Whereas the control information for core resident requests is
itself core resident, the control information for drum resident
requests is drum resident. Therefore, drum resident requests which
require control information will require the reading of the
necessary table from drum before the access can be completed. The
Manipulator recognizes such requests, and will automatically
initiate the reading of the necessary control table as a
preliminary to processing the request. A second possibility is that
the requestor may provide all information necessary to properly
access the specified drum data; therefore, no control table is
required, and the Manipulator will forward the request on to the
Drum Scheduler, with only minimal processing. Such requests are
termed "non-restricted." It should be noted that non-restricted
accesses are not limited to drum resident programs; such accesses
may be utilized by core resident programs as well.
As noted previously, control of the non-resident area is an
important factor where the requestor is drum resident. For example,
the requestor may wish to release the non-resisdent area as a
function of requesting drum I/O. However, the Manipulator is
structured such that it can not concurrently process several
requests requiring access to its drum-resident control tables.
Therefore, to prevent the initiation of other requests, the
Manipulator will specify (via the special interface alluded to
previously) that the non-resident area is to be held during the
access of its control tables. When the control tables have been
brought in and the Manipulator, using the information contained
therein, makes the actual data access to drum as requested by the
user, the non-resident area is released. Such a mechanism prevents
attempted multiprocessing of drum resident requests.
F35b
1. name: manipulator Parameter Collection Routine
2. PURPOSE: This module collects various fields supplied by a
requestor of drum I/O and formats them into one or more key
parameters to be used in making the requested drum access.
3. FUNCTIONS:
a. Extracts parameters from either the call history table or work
area, as specified by the requestor.
b. Scales each parameter, if required, by a predefined scale
factor.
c. Range checks each parameter, if required, against a predefined
maximum value.
d. Compresses parameters, if required, according to a predefined
number base.
e. Formats collected parameters into one or more predefined key
words.
4. INPUTS
4.1 software
4.1.1 core Tables
Fwa -- user's Work Area
Cht -- user's History Table
Ftd -- table Directory
Fpc -- parameter Collection Table
4.1.2 Drum Tables
Fcb -- control Buffer Table
4.1.3 Registers
Xr1 -- work Area Address
Xr2 -- table Directory Index
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Fje -- executive Junk Storage
Fwa -- user's Work Area
5.1.2 Drum Tables
None
5.1.3 Registers
Xr1 -- work Area Address
Xr2 -- parameter Collection Table Index
5.2 HARDWARE
None
6. CONTROL
6.2 EXIT POINTS Exit Reasons for Exit Points F35N02 Error
Scheduling Routine -- Called if a parameter fails a required range
check. F35C01 Common Functions Routine -- This is the normal exit
and is called at the conclusion of parameter collection.
7. SUBROUTINES USED
None
8. NARRATIVE
8.1 discussion
one of the principal functions of the Manipulator is to provide an
interface between the user and the system data base, such that
changes in the data base structure need not be the concern of the
user. This objective is accomplished by the user providing those
parameters necessary to access a given drum table, not necessarily
in this format required for the actual access. The Manipulator,
using tables which describe the data base structure, then formats
these parameters as required to properly access the specified
data.
8.2 TECHNIQUE
Basically, the parameters which are passed by the user go to make
up the search key used to access the required table. But the
Manipulator must first format these various parameter fields into a
search key corresponding to the particular table structure.
Associated with each such access is an entry in table FPC, the
parameter collection table. This table entry in essence
describes;
1. parameter fields supplied by the user.
2. the composition of key words (e.g., a search key) which are to
be derived from these parameters fields.
3. special utility functions (e.g., range checking, scaling, etc.)
to be performed on specified parameter fields.
The Manipulator will accept input parameters from either the user's
work area or call history table, as specified. The control
information for each parameter specifies the position in the user's
buffer in which the parameter is located, its maximum permissible
value, a scale factor (if required), the position which the
parameter is to occupy in the key word being constructed, and other
factors. Using this control information, the Manipulator removes a
specified parameter from the user's buffer and performs any
requested utility functions (such as scaling or range checking).
The parameter is then merged into its appropriate position in the
key word under construction.
The end result of collecting several such parameters will be the
required keywords for the drum access. Generally, only one keyword,
the search key, need be constructed. However, some accesses require
construction of additional key words such as the number of words
contained in each cell of the table being accessed, or an index
value into a portal of the table.
F35c
1. name: manipulator Common Functions Routine
2. PURPOSE: This module performs functions common to all drum
accesses; i.e., certain parameters common to many access types are
generated here in preparation for the drum access.
3. FUNCTIONS
a. Generates following parameters:
1. DCU instruction word.
2. Number spill words required.
3. Data mask index.
4. Drum address (i.e., DCU pair, segment, and physical
address).
5. Read/Write indicator.
b. Determines, via a predefined algorithm, the portal number to be
accessed, using user-supplied parameters.
4. INPUTS
4.1 software
4.1.1 core Tables
Fwa -- user's Work Area
Ftd -- table Directory
Fpd -- portal Description Table
4.1.2 Drum Tables
None
4.1.3 Registers
Xr1 -- work Area Address
Xr2 -- tables Directory Index
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Fwa -- user's Work Area
Fje -- executive Junk Storage
5.1.2 Drum Tables
None
5.1.3 Registers
Xr1 -- work Area Address
Xr2 -- table Directory Index
5.2 HARDWARE
None
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F35C01 from F35B
following parameter collection. F35C02 Entered as return from F35M.
6.2 EXIT POINTS Exit Reasons for Exit Points F35D01 Single Level
Counter Search Routine -- Called to perform final processing unique
to counter -- start (block) accesses. F35E01 Single Level
Associative Search Routine -- Called to perform final processing
unique to associative search accesses. 7. SUBROUTINES USED Entry
Functional Names Points F35M Portal Number Calculator -- This
module is called to calculate the portal number; each entry line
corresponds to a specific algorithm unique to certain accesses for
which this calculation is required.
8. NARRATIVE
8.1 discussion
all accesses to drum must specify certain common parameters which
are not unique to any given access. An example of such a parameter
would be the DCU instruction word, required to instruct the
hardware as to what type of search is being requested. These
parameters may be predefined in some cases; in others, dynamic
calculations are required to determine them.
8.2 TECHNIQUE
Parameters which may be predefined at assembly time are coded into
the FTD (table directory) and FPD (portal description) entry for
each specific access. At run time, these parameters are retrieved
from FTD and FPD and placed in a temporary buffer area.
The portal number may be supplied by the user, in which case Manip
performs no calculation. However, generally, the portal number is
determined by parameters unique to a given call being processed
thru the system. In such cases, Manip will execute a predefined
algorithm, utilizing these call-dependant parameters, to arrive at
the appropriate portal numbers for the table being accessed.
F35d
1. name: manipulator Single Level Counter Search Routine
2. PURPOSE: The purpose of this module is to perform routine
initialization of those parameters unique to counter start drum
accesses.
3. FUNCTIONS
Generates certain parameters required for counter start
accesses.
4. INPUTS
4.1 software
4.1.1 core Tables
Fwa -- user's Work Area
Ftd -- table Directory
Fje -- executive Junk Storage
4.1.2 Drum Tables
None
4.1.3 Registers
Xr1 -- work Area Address
Xr2 -- table Directory Index
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Fwa -- user's Work Area
5.1.2 Drum Tables
None
5.1.3 Registers
Xr1 -- work Area Address
Xr2 -- table Directory Index
5.2 HARDWARE
None
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F35D01 Entered by
F35C for intialization of counter start parameters. 6.2 EXIT POINTS
Exit Reasons for Exit Points F35G01 Manipulator Termination Routine
-- Called for final processing and termination to Drum
Scheduler.
7. SUBROUTINES USED
None
8. NARRATIVE
8.1 discussion
this module performs generation of parameters required specifically
for counter start accesses to the drum.
8.2 TECHNIQUE
Certain parameters may be predefined at assembly time; these are
coded into the table directory (FTD) and retrieved by Manip during
execution for insertion into a temporary buffer.
Some parameters (i.e., the index into the portal and the word
count) may be specified by the user and supplied as input to the
Manipulator access. For these cases, Manip will utilize these
parameters; generally, these are generated during the parameter
collection process (see documentation on module F35B).
F35e
1. name: manipulator Single Level Associative Search Routine.
2. PURPOSE: To generate those parameters unique to an associative
search access to drum.
3. FUNCTIONS: Generates and formats those parameters which are
uniquely required for an associative search access of drum.
4. INPUTS
4.1 software
4.1.1 core Tables
Fwa -- user's Work Area
Ftd -- table Directory
Fje -- executive Junk Storage
4.1.2 Drum Tables
None
4.1.3 Registers
Xr1 -- work Area Address
Xr2 -- table Directory Index
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Fwa -- user's Work Area
Fje -- executive Junk Storage
5.1.2 Drum Tables
None
5.1.3 Registers
Xr1 -- work Area Address
Xr2 -- table Directory Index
5.2 HARDWARE
None
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F35E01 Called by
F35C for formatting and generation of parameters unique to
associative search accesses. 6.2 EXIT POINTS Exit Reasons for Exit
Points F35G01 Termination Routine -- Called for final processing
and termination to the Drum Scheduler.
7. SUBROUTINES USED
None
8. NARRATIVE
8.1 discussion
certain parameters are unique to the associative search access
(i.e., not required for a counter start access). These parameters
must therefore be initialized separately.
8.2 TECHNIQUE
As in other portions of Manipulator processing some parameters may
be pre-defined, while others may be constructed (if required) from
user-supplied access parameters.
The principle purpose of this module is to generate the word count,
index value, search key and mask word for the associative search
access. The word count and index value may be pre-defined or
dynamically calculated. The search key is always dynamically
calculated, while the mask word is always pre-defined. Pre-defined
items are retrieved from the respective table directory entry and
placed in a temporary buffer area. Items which are dynamically
calculated are generated in the parameter collection routine (F35B)
using user-supplied parameters as input.
F35g
1. name: manipulator Termination Routine
2. PURPOSE: The purpose of this module is to collect parameters
generated by previously processing routines and format them into
the work area.
3. FUNCTIONS:
a. Collects all generated parameters and completes final
initialization of the work area.
b. Terminates to Drum Scheduler.
4. INPUTS
4.1 software
4.1.1 core Tables
Fwa -- user's Work Area
Fje -- executive Junk Storage
4.1.2 Drum Tables
None
4.1.3 Registers
Xr1 -- work Area Address
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Fwa -- user's Work Area
Fje -- executive Junk Storage
5.1.2 Drum Tables
None
5.1.3 Registers
Xr1 -- work Area Address
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F36G01 Entered from
either F35D or F35E, to perform final processing and terminate to
Drum Scheduler F35G02 Entered from F35H for same purpose. 6.2 EXIT
POINTS Exit Reasons for Exit Points F29XQ1 (Drum Scheduler) --
Called to initiate or schedule the drum access.
7. SUBROUTINES USED
None
8. NARRATIVE
8.1 discussion
this routine serves as a final processor and common exit point from
the Manipulator.
8.2 TECHNIQUE
The various parameters generated by previous processing are now
collected from the temporary buffer and placed in the appropriate
fields within the work area. These include the drum address
register word and the DCU instruction word. Also, a "pseudo" spill
word is formatted and placed in the appropriate location if the
access is counter start and a single spill word is required. The
drum address, which is supplied in logical format, is converted by
algorithm to its physical counterpart, as required for input the
DCU hardware.
Finally, Manipulator processing is complete when control is
transferred to the Drum Scheduler.
F35h
1. name: manipulator Exhaustive Search Routine
2. PURPOSE: This module will successively search each portal of a
given table for the data requested by the user.
3. FUNCTIONS:
a. Determines if the required data has been located.
b. If so, schedules the user's next program.
c. If not, determines next portal to be searched and initiates the
access.
d. If all portals have been searched and coincidence has not been
found, schedules user's next program with indication of no
coincidence.
4. INPUTS
4.1 software
4.1.1 core Tables
Fwa -- user's Work Area
Fpd -- portal Description Table
4.1.2 Drum Tables
None
4.1.3 Registers
Xr1 -- work Area Address
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Fwa -- user's Work Area
5.1.2 Drum Tables
None
5.1.3 Registers
Xr1 -- work Area Address
5.2 HARDWARE
None
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F35X02 Entered from
executive as next program for each portal searched. 6.2 EXIT POINTS
Exit Reasons for Exit Points F35G02 Manipulator Termination Routine
-- Called to initiate an access to the next portal of a table.
F35N03 Schedule User's Next Program -- Called to schedule the
user's next program at the conclusion of the exhaustive search.
7. SUBROUTINES USED
None
8. NARRATIVE
8.1 discussion
some users may require that an entire table be searched for given
information, not knowing in which portal of the table the
information resides. To facilitate this process, the Manipulator
provides the internal capability to successively search all portals
of a given table. This frees the user from the code and logic
required to continue searching each portal of the table until
coincidence is found or all portals are exhausted.
8.2 TECHNIQUE
In order to ascertain the results of each portal search, Manip
specifies itself (F35X02) as the next program for each access to
drum. Upon regaining control at this entry point, the
non-coincidence indicator of the work area is checked. If it is not
set, coincidence was found in the last portal searched and the
access is complete; the user's next program is then scheduled by
Manip.
If this indicator is set, coincidence was not found in the last
portal searched. A test is made to see if all portals have now been
searched; if so, the user's next program is scheduled with the
indication that coincidence could not be found. If all portals have
not been searched, the information describing the table's next
portal is extracted from FPD and properly formatted into the work
area. The Manipulator Termination Routine is then called to
initiate the next drum access.
This process is reitereated until 1) coincidence occurs, or 2) all
portals of the specified table have been searched.
F35m
1. name: portal Number Calculator
2. PURPOSE: F35M contains algorithms to develop portal numbers for
drum access requested by call processing or update modules.
3. FUNCTIONS: F35M calculates portal numbers required to access the
following tables:
a. CDN
b. CLN
c. CRN
d. CSX
e. CGT
4. inputs
4.1 software
4.1.1 core Tables
Cep -- engineerable Office Parameters
Chc -- om data Frame Received
Cja -- original Class Data
Fac -- npa normalization Table
Fal -- search Key Conversion Table
Fdn -- directory Number Normalization Table
Fje -- executive Junk Storage
Ftd -- drum Access Description Table
Fwa -- executive Interface Work Area
Fwb -- cp register/Sender Memory Image
Fwc -- tm received Information
4.1.2 Drum Tables
None
4.1.3 Registers
X1 -- client's Executive Interface Work Area Address
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
FWA -- Executive Interface Work Area
FJE -- Executive Junk Storage
5.1.2 Drum Tables
None
5.1.3 Registers
Ra -- portal Number to be searched.
X1 -- executive Interface Work Area Address
5.2 HARDWARE
None
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F35M01 F35M01 is
entered to convert Directory Number to portal to search. F35M02
F35M02 is entered to convert office section and matrix to drum
portal to search. F35M03 F35M03 is entered to convert route number
from FWASW1 to drum portal to search. F35M05 F35M05 is entered to
convert office section and matrix to drum portal to search. F35M06
F35M06 is entered to search table FAC for area code match and add
NPA from FAC to the search table FAC for area code match and add
NPA from FAC to the search word for a six-digit translation. F35M07
F35M07 is entered to selected the proper party from a two-party
line and specify the drum portal where the LNI of the party
resides. F35M08 F35M08 is entered to load the A register with
FJE009 (Parameter collected in F35B) for drum portal to search.
F35M09 F35M09 is entered to test the search word to compute the
drum portal to search. F35M10 F35M10 is entered to extract
("collect") data from the client's work area to be processed by
F35M01. F35M11 F35M11 is entered to grab search word from client's
work area for processing by using table FAL and portal
determination routines in F35M05. F35M12 F35M12 is entered to
determine segment, drum address and DCU pair information for next
drum access. 6.2 EXIT POINTS Exit Reasons for Exit Points F35C02
Manipulator Common Functions Routine (F35C) is entered at F35C02
with a portal address to continue processing for a drum access.
F35N04 Manipulator Identifier Reconstruction Routine F35N04 is
entered to set client's no coincidence found indicator and schedule
client's next or error program. F35C03 Manipulator Common Functions
Routine (F35C) is entered at F35C03 with drum address information
to continue drum access.
8. NARRATIVE
8.1 discussion
f35m is called from F35C (Common Function Module) when no portal is
specified by the client program. The selected routine constructs
the required portal number for the access and returns to F35C02 or
F35C03.
8.2 technique
f35m01 selects the portal for table CDN. Using the first four
digits table FDN is searched for a match. When that is found the
portal number is extracted and control is returned to F35C02. If no
coincidence is found the error program is scheduled through
F35N04.
F35M02 determines whether the matrix number falls between 1 and 5
or 6 through 10. If the number is greater than 5, one is added to
the portal number. Control is then returned to F35C02.
F35M03 extracts the route number from the work area and clears all
but the two high order bits. The word is then properly positioned
in the A-register and control is returned to F35C02.
F35M05 extracts the section number and the matrix from the work
area. The two items are used as search key to find the proper
pointer to the portal description word in table FAL. Control is
then returned to F35C02.
F35M06 searches table FAC for the area code match. If a match is
found the normalized area code is extracted and added to the search
word for a six digit translation. If the search of table FAC is
successful control is returned to F35C02, otherwise F35N04 is
called to schedule the error program.
F35M07 extracts the pointer to the call history table; determines
if it is a two-party line; selects the proper party and specifies
the portal where the LNI of the party resides. Control is returned
to F35C02.
F35M08 loads the A register with FJE009 (Drum Address Register) and
returns to F35C02.
F35M09 tests the search word to determine the section number. If
the section number is greater than 2 the portal number is
incremented by 2. The matrix is range checked and if it is not
greater than 5, the portal number is incremented again by 1.
Control is then returned to F35C02.
F35M10 extracts data from the work area to form a search word to be
processed by F35M01.
F35M11 grabs the search word from the work area and formats the
search word for table FAL. The search of table FAL is an internal
routine found in F35M05. Upon completion of the search F35C02 is
called.
F35M12 determines whether the DCU pair and/or the portal number is
to be altered prior to calling F35C03.
F35n
1. name: identifier Reconstruction Routines
2. PURPOSE: The purpose of F35N is to extract data from the call
history table or the work area, order the data for the drum search,
and schedule F40.
3. functions: module F35N performs the following functions;
a. Extracts the first four digits of a 1 or 2 party line.
b. Schedules the error program is no coincidence is found in table
FDN.
c. Schedules users next program through closed subroutine
F40X06.
4. inputs
4.1 software
4.1.1 core Tables
Cep -- engineerable Office Parameters
Cja -- original Class Data
Esl -- executive Storage Location Table
Fdn -- directory Number Normalization Table
Fje -- executive Junk Storage
Fpd -- portal Description Table
Fwa -- executive Interface Work Area
Fwb -- cp register Sender Memory Image
4.1.2 Drum Tables
None
4.1.3 Registers
Ra -- client's Executive Interface Work Area Address
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Fwa -- executive Interface Work Area
5.1.2 Drum Tables
None
5.1.3 Registers
X1 -- client's Executive Interface Work Area Address.
Rq -- eio value for F40X04.
X2 -- tells F40X06 Manip is calling.
5.2 HARDWARE
None
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F35N01 F35N01 is
entered for LNI to Directory Number Conversion Completion. F35N02
F35N02 is entered to set EIO for parameter conversion and schedule
client's error program F35N03 F35N03 is entered when access is
complete to schedule user's next program. F35N04 F35N04 is entered
to schedule client's next or error program when drum coincidence
was not found. F35N10 F35N10 completes LNI to Directory Number
Translation for update. 6.2 EXIT POINTS Exit Reasons for Exit
Points E01X04 E01X04 is entered to release the control of the CPU 7
SUBROUTINES USED Entry Functional Names Points F40X04 Client's ERP
Scheduling Subroutine. F40X06 Client's NPG Scheduling
Subroutine.
8. NARRATIVE
8.1 discussion
f35n extracts a pointer for either the call history table or work
area and searches table FDN for a match of the pointer. If the
search is successful a four digit code is transferred from table
FDN to table CXK and F40X06 is called to schedule the next program.
Should the search not be successful the error program is scheduled
through F40X04.
Interrupts are disabled prior to entering F40 and enabled upon
return. Control is released to F01X04.
8.2 technique
f35n is called for identifier reconstruction from call processing
and update accesses. F35N01 services Call Processing and F35N10
services update. Both routines are capable of working with either
TPL or TPS offices. The major difference between the routines is
that the input data to F35N01 is in the call history table while
the input data for F35N10 resides in the work area.
F35N01 determines whether party one or party two is to be serviced.
The pseudo portal number is used as the Key to search table FDN.
The first four digits are extracted from the FDN entry and stored
in table CXK. If it is a TPL office F40X06 is called to schedule
the next program. If the office is TPS the address or coincidence
is converted to TBCD (digits 5, 6 and 7) and stored in table CXK.
F40X06 is then called to schedule the next program. F35N10 provides
a similar service for update requests. Input data is stored in the
work area instead of the call history table. Again a test is made
to determine whether the office is TPS or TPL. The TPS office
requires additional processing prior to calling F40X06 to schedule
the next program.
F35N02 is an error processing routine. Parameter errors are flagged
through this module. A call to F35N04 indicates no coincidence
found. An additional test is made to determine whether coincidence
is required. If not, the next program is scheduled; if coincidence
is required the error program is scheduled.
F35NO3 is the routine used to schedule F40X06. Upon return from
F40X06 or F40X04 control is returned to the executive through
E01X04.
F35p
1. name: manip fast Access Formatter.
2. PURPOSE: F35P processes Call Processing's most frequently used
accesses to drum. These accesses are coded away from the normal
line of processing to conserve on processing time of calls.
3. FUNCTIONS: The function of F35P is to do the following:
a. Collects and formats the required parameters for the access.
b. Performs range checks on the parameters if required.
c. Selects the portal on drum to be entered.
d. Sets the number of words per cell.
e. Initializes the mask word and the instruction word.
d. Formats the instruction words for the DCU scheduler and calls
the DCU scheduler.
4. INPUTS
4.1 software
4.1.1 core Tables
Cdn -- local Directory Number.
Cep -- engineerable Office Parameters.
Cgd -- tgn to Directory Number.
Chc -- om data Frame Received.
Che -- pretranslation Access Store Data.
Chh -- route and Path Data.
Cja -- original Class Data.
Cln -- line Equipment Number.
Clo -- line Matrix Outlet.
Cpd -- pretranslation Data.
Csx -- selector Matrix Outlet.
Ctn -- trunk Equipment Number.
Fal -- search Key Conversion Table.
Fdn -- directory Number Normalization Table.
Fje -- executive Junk Storage.
Fpd -- portal Description Table.
Fwa -- executive Interface Work Area.
Fwb -- cp register Sender Memory Image.
Fwc -- tm received Information.
4.1.2 Drum Tables
None
4.1.3 Registers
X1 -- executive Interface Work Area Address.
X2 -- manipulator Access Number.
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Fwa -- executive Interface Work Area Address.
5.1.2 Drum Tables
None
5.1.3 Registers
X1 -- executive Interface Work Area Address.
5.2 HARDWARE
None
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F35P01 F35P01 is
scheduled as the only entry point into F35P. 6.2 EXIT POINTS Exit
Reasons for Exit Points F29X01 DCU Scheduler program: F29X01 is
called to schedule the drum operation specified by the client thru
F35P. F35N02 Manip Parameter Error Routine: F35N02 is entered when
F35P finds an error in the parameters passed by the client. F35N02
schedules the user's ERP with an EIO of 2. F35N04 MANIP No
Coincidence Found Routine: F35N04 is entered when no coincidence is
found while associatively searching a table. F35N04 schedules the
user's ERP or NPG depending on whether the client has specified
coincidence required.
7. SUBROUTINES USED
None
8. NARRATIVE
8.1 discussion
f35p formats request for the following MANIP accesses: FM001 (CLO),
FM003 (CGD). FM004 (CSX), FM006 (CTN), FM007 (CDN), FM009 (CRN),
FM021 (CTT), FM022 (CPD), FM023 (CTT), FM025 (CLN). F35P is entered
with the work area address in X1 and the requested access number in
X2. The routine to process the access is entered through a BUN
table modified by X2. If it is not a fast access to be processed,
control is returned to F35A02.
Most handling the parameter collection is performed by the KEYGEN
macro. Special Handling is required in only a few cases. Portal
algorithms are required for several accesses (FM004, FM007, FM009,
and FM025). Special Handling is also required for FM007 to
determine whether the office is TPL or TPS.
8.2 technique
not Applicable
Notes to FIG. 117J
*1. f4.phi.x.phi.4 -- will Set FWAE1.phi. = (RO) and schedule the
error program.
2. F4.phi.X.phi.6 -- Will schedule the next program.
F36 -- figs. 118 - 118e
1. name: f36 -- ccr i/o handler Subroutines No. 1
2. PURPOSE: In order to centralize functions and conserve core
memory, six subroutines have been provided in module F36 for use by
other CCR I/O Handler modules.
3. FUNCTIONS: Module F36 performs the following functions:
a. F36X01 -- Unlike diagnostic request clients from I/O queue,
(containing "F31 clients") hitch request to maintenance hitching
post, and start timer for I/O request.
b. F36X02 -- Handles reroutes via scheduling or branching to the
appropriate requested module.
c. F36X03 -- Cleans up I/O request when complete. This includes
resetting timers and/or audits bit associated with request,
resetting hitching post and marker busy bit, and resetting markers
and restoring CCR's to original scan state if modified for this
request.
d. F36X05 -- Provides proper configuration of CCR's for requests
requiring special configurations.
e. F36X06 -- Unloads all data and/or status word from CCR's.
f. F36X08 -- Reconfigures CCR's as requested by CONFIG. INPUTS
4. inputs
4.1 software
4.1.1 core Tables
Fsl -- executive Storage Location.
Fcc -- cm-rj identity.
Fhp -- hitching Post.
Fwa -- executive Interface Work Area.
Hel -- i/o abort Entry Lines.
Fex -- executive Inst for F36.
Ftl -- timer.
Hst -- system Status.
4.1.2 Drum Tables
None
4.1.3 Registers
X1 -- work Area Identity.
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1. core Tables
Esl -- executive Storage Location.
Fcc -- om-rj identity.
Fex -- executive Instructions for F36.
Fhp -- hitching Post.
Fix -- ccr maintenanace Work Area.
Ftl -- timer.
Fwa -- executive Interface Work Area.
Hel -- i/o abort Entry Lines.
Hst -- system Status.
Swd -- ccr dump Area D.
5.1.2 drum Tables
None
5.1.3 Registers
Ra -- error Indicator for F36X06.
5.2 hardware
none
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F36X01 See Section
3 for all listed entry points F36X02 F36X03 F36X05 F36X06 F36X08
6.2 EXIT POINTS Exit Reasons for Exit Points None Return to client.
7. SUBROUTINES USED Entry Functional Names Points F03 Unlink from
Priority Queue. F34 Originating Marker Standby Interrupt Handler.
E02 Interval Timer Request Acceptor. E03X02 Stop Timer (STTIME)
E01X01 Timer Expired S31X01 Multiple Channel Recovery
8. NARRATIVE
8.1 discussion
f36x01 will unlink the diagnostic request from the I/O queue and
hitch the work area to FHPA08. Then set FCCMJI to indicate a
maintenance job in progress, and set FWAFID in the user's work area
indicating the request has been initiated. F36X01 will then index
into table FTL WITH FWATMS to obtain the number of 16.6 msec.
intervals to pass to E02X01 when it requests the timing of the I/O
request. F36X01 then unhitches special work are FIX (FZB) from
FHPA22 and calls E02X01 to time I/O request and transfer to F34X01
should timeout occur. It then returns to the calling program.
F36X02 receives as input the two reroute words from the MANIAC
program. It then transfers to/or schedules the appropriate module
and returns to the calling program.
F36X03 receives as input the scan address for the I/O request it is
to clean up and three indicators indicating whether this is a
maintenance request, whether to send a reset CPD to a marker.
If the maintenance request indicator is set, F36X03 resets FCCMJI
and FCCOMT. If FCCSCR is set, indicating that CCR's are in a
special scan state, and no reconfiguration bits for the CCR's are
set in FCCREC. F36X03 will set the appropriate bits in FCCREC to
restore CCR's to original state and then reset FCCSCR and FCCMIU.
Then F36X03 will unhitch the work area from FHPA08 and attempt to
remove special work area FIX from the timequeue. If the work area
was present in timer queue, it will hitch the work area back to
FHPA22.
If the input scan address is for TM, F36X03 will reset the I/O
Handler audit Bit for the TM, reset the pair busy bit, and reset
the TM pair hitching post.
Then F36X03 will issue the appropriate CPD's if any, and return to
the calling program.
F36X05 will set up CCR's for a specified CCR I/O request or a CCR
to CCR transfer request. First F36X05 checks the system status
table, HST, to be sure that the CCR(s) to be used is not OS. If it
finds a CCR OS, it will return to the calling program with an error
indication.
If the request is a CCR to CCR request, F36X05 will both CCR's into
standby scan mode and point the sink CCR toward the source CCR and
provide a status dump of sink CCR in word SWD via a call to F36X06
and then set FCCSCR to 1 and FCCMIU to the identity of the
originally online active CCR.
If the request is for a specified CCR, and the specified CCR is not
the CCR currently in active use, F36X05 will place both CCR's
online standby and master reset the active CCR to eliminate
interference during the transmissions. Then F36X05 will set FCCSCR
and FCCMUI as above.
In all cases, return is made to the calling program with the
sending CCR connected and the receiving CCR disconnected.
F36X06 is entered with five indicators set and two sink addresses
furnished and XR2 contains the channel identify of the CCR.
The first indicator checked is for a single status word dump. If
set, the standard status word is unloaded at the address in ERG001
and sense group 046 or 047 is stored in the next sequential
location.
The second indicator checked is for a full status word dump. If
set, the standard status word and the two error status words are
stored sequentially, followed by sense group 046 or 047, starting
at the address in ERG001.
The third option is a two word data dump. If requested, the first
two data words will be stored sequentially at the address in
ERG002.
The fourth option is a two word data dump. If requested, the first
two data words will be stored sequentially at the address in
ERG002.
The fifth indicator checked is whether CCR should be disconnected.
If set, the CCR will be disconnected.
Options one and two are mutually exclusive as are options three and
four. Control is always returned to the calling program.
F36X08 is entered with its input in FCCREC. FCCREC contains six
bits. They indicate:
1. CR B should be placed online and active.
2. CR A should be placed online and active.
3. CR B should be placed offline.
4. CR A should be placed offline.
5. CR A should be placed online and standby.
6. CR B should be placed online and standby.
F36X08 will process any bits set in the order listed and then reset
the bits. It will then return control to the calling program with
any reconfigured CCR's connected to the I/I bus.
8.2 TECHNIQUE
Not applicable.
Notes to FIG. 118A
Input: ra = second Reroute Word
F37 -- figs. 119 - 119d
1. name: f37 -- ccr error Isolation and Recovery Module.
2. PURPOSE: Module F37 has been provided to handle all error
interrupts from the CCR's.
3. FUNCTIONS: Module F37 performs the following functions:
a. Provides reroute and reset and ignore maniac functions on the
CCR error sense lines.
b. Provides fault/error isolation and CCR/MKR isolation.
c. Takes appropriate recovery steps to achieve a workable
subsystem.
4. INPUTS
4.1 software
4.1.1 core Tables
Fcc -- cm-rj identity.
Fjp -- executive Junk Storage.
Fwa -- executive Interface Work Area.
Fwc -- tm receiver Information.
Swb -- ccr dump Area B.
Swe -- ccr dump Area E.
4.1.2 drum Tables
None
4.1.3 Registers
None
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Erg -- pseudo Registers.
Fjp -- executive Junk Storage.
F38x03 -- schedule error program.
F38x04 -- abort Job.
I00 -- maintenance Interrupt Access.
I01 -- configuration Control.
I20 -- elt, diarqt, diabrt.
i50 -- extra Lines for L00.
S31x01 -- ccx errors Check.
8. NARRATIVE
8.1 discussion
after checking maniacs on the interrupting device, module F37 then
proceeds to determine the cause of the interrupt. If the interrupt
occurs during a CCR to CCR transfer, F37 will ignore the interrupt
and return to ICAP. If the interrupt occurs during a maintenance
request, F37 will schedule the user's error program with FWAEIO =
12 after providing a CCR status word dump in FWC and then reset and
ignore the error. If a transmission error interrupt occurs during
an origination or termination, F37 will immediately retry the I/O
operation, either by calling F32X05 to send data out again if error
was in sending or by backing up scanner one marker and allowing CCR
to receive data again. If the entry is successful, the ready
interrupt will be rerouted through F37X03 and counter. If the
transient error rate exceeds 1%, CCR Isolation is requested on the
device. If the entry is unsuccessful, we have found a fault, and
fault/error isolation is complete. F37 will proceed to CCR/MKR
isolation stage. If a timeout error occurs at any time during call
processing I/O, F37 will call CCR Isolation immediately. If an
error occurs with a MOS marker, F37 will set the disable receiving
errors latch in the active CCR to prevent constantly receiving
error interrupts.
Upon entry to the CCR/MKR isolation stage, F37 will attempt to
switch the active CCR by requesting that the active CCR be placed
MOS. If the request is denied because the other CCR is not
available, F37 will set the disable receive errors latch in the CCR
and reset and ignore the error. If the reconfiguration request is
allowed, F37 can then do more retry to accomplish CCR/MKR
isolation. If the retry is successful, F37X03 again receives
control via a reroute of the ready interrupt and will assume that
the original CCR is fault and will request, through DIACON, that
CCR Isolation be run on that CCR. If the retry is unsuccessful, F37
will assume the marker fault, and will request that CCR/MCR
Isolation be run on the original CCR and the faulty CCR after
putting the marker MCS.
When F37 has completed its isolation, it will call F32X01 to scan
the I/O queues and then return to ICAP.
F38 -- figs. 120 - 120c
1. name: f38 -- ccr i/o handler Subroutines -- 2
2. PURPOSE: F38 contains six subroutines used by other programs
associated with CCR and marker hardware.
3. FUNCTIONS:
a. F38X01 handles the interface between the I/O programs and the
non-I/O executive in regards to scheduling the user's next program
after successfull completion of I/O request.
b. F38X03 handles the interface between the I/O programs and the
non-I/O executive in regards to scheduling the user's error program
after unsuccessful completion of the I/O request.
c. F38X02 provides interface between the I/O Handler Timeout Audit
Program and the CCR I/O Handler for CCR timeouts.
d. F38X05 provides interface between the I/O Handler for
terminating marker timeouts.
e. F38X04 attempts to find and abort an I/O request associated with
a particular CCR scan address.
f. F38X07 provides interface between terminating marker isolation
programs and the I/O handler when isolation is completed. This
entry line will schedule either the next program or error program
of the termination request depending on a indicator passed by
calling program.
4. INPUTS
4.1 software
4.1.1 core Tables
Est -- priority State Table.
Fcc -- om-rj identity Table.
Fhp -- hitching Post Table.
Fjp -- interrupt level junk Table.
Fwa -- executive Work Area Table.
Has -- mcr audit Table.
4.1.2 Drum Tables
None
4.1.3 Registers
X1 -- work Area Address.
X2 -- scan Address of Marker.
Ra -- schedule Error or Next Program.
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Eps -- executive Parameter Storage Table.
Esl -- executive Storage Location Table.
Est -- priority State Table.
Fhp -- hitching Post Table.
Fwa -- executive Work Area Table.
Has -- mcr audit Table.
5.1.2 Drum Tables
None
5.1.3 Registers
X1 -- work Area Address.
X2 -- scan Address of Marker.
Ra -- error Indicator.
5.2 HARDWARE
None
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F38X01 Entered to
call the Executive Audit Program for CCR timeouts. F38X03 Entered
to call the Executive to schedule the user's error program. F38X04
Entered to find and abort an I/O request associated with a
particular scan address. F38X05 Entered for terminating marker
timeouts. F38X06 Entered to provide interface between terminating
marker isolation programs and CCR I/O handler when isolation is
complete. 6.2 EXIT POINTS Exit Reasons for Exit Points None Control
is always returned to the calling program. 7. SUBROUTINES USED
Entry Functional Names Points F02X02 Link to front of queue. E01X01
Schedule program and return control. F05X01 Return work area to
system pool. F36X01 Set marker MOS and just ignore. L20X01 Schedule
marker maintenance. F32X01 Scan CCR I/O queues.
8. NARRATIVE
8.1 discussion
f38x01 and F38X03 provide implementation of the "hold NRA" option
and the "drop work area" option in field FWAPGT of the I/O
request.
F38X02 and F38X05 provide interface between I/O Handler Timeout
Audit (IOHTOA) and I/O Handler. F38X02 will call F32X07 to put the
CCR MOS and Call CCRISO. F38X05 will call CONFIG to put the TM MOS,
make a DIARQT for MRK routining, set unit just ignore maniac on the
marker, and abort any request in progress via a call to F38X04, and
schedule the user's error program with FWAEIO = 9. Both F38X02 and
F38X05 will drive F38X02 to scan the I/O queues and then return to
the calling program.
F38X04 will abort any I/O request in progress on the CCR scan
number it receives as input and return the requestor's work area
address in index register one.
F38X07 will reset the hitched work area bit (FHPJHT) passed by
marker isolation and scheduler either the next program or the error
program (with FWAEIO = 8) of the request that was hitched to the
special hitching post.
8.2 TECHNIQUE
Not applicable.
Notes to FIG. 120
Inputs: xr1 = work Area Address of Program to Schedule.
Notes to FIG. 120C
This routine to reset TM H.P. after MKR fault and schedule hitched
program.
Inputs:
ra = .phi. indicates schedule next program.
Ra .noteq. .phi. indicates schedule error program.
X1 = waa -- will be saved.
X2 = scan Address -- will be saved.
Outputs:
ra = .phi. indicates no error found.
Ra = 1 indicates error was found.
Error conditions:
1. Invalid SCA (not in range) SCA 14)
2. job not hitched at spare HP. RJ and ERG.phi..phi.1 - .phi..phi.4
are destroyed.
F39 -- fig. 121
1. name: f39 -- ccr load/Unload Subroutine.
2. PURPOSE: This module performs certain I/O functions for S45, CCR
Link Localization. It is provided to minimize interface
requirements for that program.
3. FUNCTIONS:
a. Loads CCR standard status word from input.
b. Unloads CCR status words upon request.
c. Checks for CCX errors.
d. Returns to calling program.
4. INPUTS
4.1 software
4.1.1 core Tables
Rsa -- computer Communications Register Maintenance Table.
4.1.2 Drum Tables
None
4.1.3 Registers
X2 -- channel Controller Number (06000 or 07000).
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Sra -- ccr maintenanace Table.
5.1.2 Drum Tables
None
5.1.3 Registers
Rq - error Indicator
0 = No error
Negative = Error in loading CCR.
5.2 hardware
ccr scanner Address Loaded.
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F39X01 Entered to
load CCR scanner for link localization only. F39X02 Entered to give
CCR error status dumps for link localization only. 6.2 EXIT POINTS
Exit Reasons for Exit Points None Control is always returned to the
calling program. 7. SUBROUTINES USED Entry Functional Names Points
S31X01 CCX recovery to check for channel multiplex errors. F36X06
To dump 4 status words.
8. NARRATIVE
8.1 discussion
f39x01 loads input word into CCR standard status word and then
calls S31X01 to check for possible CCX errors. The module will do
retries if requested by S31X01. When standard status word has been
successfully loaded, F39 will return to S45 with a no error
indication. If CCX errors are encountered, F39 will return with
indication that errors occurred.
F39X02 formats interface information and the calls F36X06 to obtain
a status dump of the CCR. F39X02 then returns error indication from
F36X06 to S45.
8.2 technique
not applicable.
F40 -- figs. 122 - 122i
1. name: f40 -- drum Handler Subroutines I
2. purpose: provides required interface with the Manipulator and
DMS Isolation for scheduling a user's next or error program.
3. FUNCTIONS:
a. Schedules the next program.
b. Schedules an error program with a specified error code.
4. INPUTS
4.1 software
4.1.1 core Tables
Fwa -- user's Work Area
4.1.2 Drum Tables
None
4.1.3 Registers
Rq -- error Code.
Xr2 -- negative, indicating caller identity.
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
None
5.1.2 Drum Tables
None
5.1.3 Registers
None
5.2 HARDWARE
None
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F40X Called by
Manipulator and DMS Isolation to schedule a user's next or error
program. 6.2 EXIT POINTS Exit Reasons for Exit Points None Return
is always made to the caller. 7. SUBROUTINES USED Entry Functional
Names Points F30A07 Utilized to schedule the user's next program.
F30A03 Utilized to schedule the user's error program.
8. NARRATIVE
8.1 discussion
occasionally, the Manipulator and DMS Isolation will schedule a
user's next or error program as part of its processing. In order to
take advantage of the Drum Handler's program scheduling capability
(including work area release, non-resident area control, state
indicator control, etc.), a special entry line has been provided
for use by the Manipulator and DMS Isolation for this purpose.
8.2 TECHNIQUE
Module F40 exists solely to satisfy interface agreements with the
Manipulator and DMS Isolation. While these programs may call entry
lines F40X04 or F40X06 (per original agreement), entry actually
occurs at F40X (or F40X01) due to F40's special PIT (i.e., no
indexing by XR3). F40 determines which entry line is being accessed
(by the value in XR3), calls F30A03 or F30A07 to perform the
required program scheduling and returns control to the caller.
Interface requirements specify that calls to F40 be executed with
interrupts disabled (to eliminate re-entrancy problems associated
with F30). When calling F40X06 to schedule the next program, XR2
must be negative (to identify the caller of F30A07 as Manip, since
minor processing differences are associated with the Manip Call).
When F40X04 is called to schedule an error program, RQ must contain
the EIO Field (error code) with which the error program is to be
scheduled.
F41 -- figs. 123 - 123c
1. name: f41 -- drum Handler Subroutines II
2. purpose: provides required interface with DMS Isolation for
clearing down a specified DCU and its associated software
indicators, and an interface to allow DMS Isolation to initiate a
DCU queue scan (to ensure all queued jobs are found).
3. FUNCTIONS:
a. Clears the DCU and places it in an idle state.
b. Clears any software indicators associated with that DCU.
c. Initiates a DCU queue scan, when instructed to by DMS
Isolation.
4. INPUTS
4.1 software
4.1.1 core Tables
Fjp -- interrupt Level Junk Storage.
4.1.2 Drum Tables
None
4.1.3 Registers
None
4.2 HARDWARE
None
5. OUTPUTS
5.1 software
5.1.1 core Tables
Fdp -- drum Parameters Table.
Fhp -- hitching Post Table.
5.1.2 Drum Tables
None
5.1.3 Registers
None
5.2 HARDWARE
DCU in a clear, idle state.
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F41X Called by DMS
Isolation to clear down a specified DCU or initiate a queue scan on
a DCU pair. 6.2 EXIT POINTS Exit Reasons for Exit Points None
Return is always made to the caller. 7. SUBROUTINES USED Entry
Functional Names Points F30A10 Called to clear down the DCU and its
associated software indicators. F30A0Z Called to initiate a DCU
queue scan.
8. NARRATIVE
8.1 discussion
during the process of isolating a fault on a DCU pair and after two
retries on the error unit, the job may be tried on the mate unit.
It is therefore necessary to clear the error unit (should it be
placed back in service). DMS Isolation therefore makes use of an
existing Drum Handler subroutine to accomplish this task. Such an
arrangement enforces accurate and efficient control of the DCU as a
resource.
The queue scan entry is needed to ensure jobs queued on a DCU-pair
basis get started again after DMS isolation is finished. Without
this entry, a job queue would not get serviced again after
isolation, because queue scan is normally started only on an
interrupt basis, and no interrupts would come in on a DCU pair shut
down for isolation purposes.
8.2 TECHNIQUE
Module F31 exists solely to satisfy an interface agreement with DMS
Isolation. While Isolation calls entry line F41X02 (per original
agreement), entry actually occurs at F41X (or F41X01) due to F41's
special PLT (i.e., no indexing is XR3).
F41 immediately calls F30A10 to accomplish the necessary clearing
of the DCU and its associated software, and returns control to DMS
Isolation. Interface requirements specify that FJPB22 contain the
identity of the DCU to be cleared.
When DMS Isolation enters F41 calling for F41X01, F41 immediately
calls F30A02 to initiate a queue scan on the DCU pair indicated by
X2 and returns control to DMS Isolation.
F52 -- figs. 125 - 125a
1. name: f52 -- marker Malfunction Interrupt Handler.
2. PURPOSE: The purpose of module F52 is to enable approprate
handling of malfunction interrupts from both originating markers
and terminating markers.
3. FUNCTIONS: Module F52 performs the following functions:
a. Appropriately handles MANIAC conditions on the interrupts
associated with marker malfunction sense lines; see paragraphs
8.1(b) and (c).
b. Interfaces with maintenance diagnostic programs when malfunction
interrupts occur during the accessing of a marker by a normal
(non-maintenance) Call Processing client of F31.
c. Provides an indication of interrupt (associated with a marker
malfunction sense line) who is performing maintenance on a marker.
In the event of this marker interrupt:
1. F52 Terminates the program and returns control back to the F31
client (originating diagnostic program).
2. Cleans up the hardware and software for the requester: That is,
resets the malfunction sense line, and resets software indicators
so that other F31 clients may be properly acted on.
d. Attempts to initiate the next I/O request from F31, if such a
request is queued.
e. Returns to the calling program.
4. INPUTS
4.1 software
4.1.1 core Tables
Esl -- executive Storage Location. (Also an output table.)
Fcc -- ccr control Table. (Also an output table.)
Fhp -- hitching Post. (Also an output table.)
Fjp -- interrupt Level Junk.
Fwa -- executive Interface Work Area. (Also an output table.)
4.1.2 Drum Tables
None.
4.1.3 Registers
None.
4.2 HARDWARE
None.
5. OUTPUTS
5.1 software
5.1.1 core Tables
Esl -- executive Storage Location. (Also an input table).
Fcc -- ccr control Table. (Also an input table).
Fhp -- hitching Post. (Also an input table.)
Fwa -- executive Interface Work Area. (Also an input table.)
5.1.2 Drum Tables
None.
5.1.3 Registers
None.
5.2 HARDWARE
None.
6. CONTROL
6.1 ENTRY POINTS Entry Reasons for Entry Points F52X01 See Purpose
paragraph 2.0, above. 6.2 EXIT POINTS Exit Reasons for Exit Points
Return to calling program. -7. SUBROUTINES USED Entry Functional
Names Points F32 CCR Handler. F34 Originating Marker Standby
Interrupt Handler. F36 CCR Subroutines. F38 CCR Scheduler B and
Aborts. L00 MANIAC -- Maintenance Interrupt Access. L01 CONFIG --
Configuration Control Program. L20 DIACON -- Diagnostic Control
Program. L50 Unit MANIAC. K70 OMRJCL -- Originating Marker RJ
Clear.
8. NARRATIVE
8.1 discussion
the following is a summary of the major (flowchart) decisions and
actions performed by F52; see the F52 flowchart for the exact
detailed flow, not indicated here.
F52 first major action is to check the MANIAC passed by the
Interrupt Cause and Analysis Program (ICAP); this indicator is the
Reset-and-Ignore condition. One out of three major categories of
action is then performed by F52 (primarily dependent on the 1 or 0
state of the Reset-and-Ignore indicator); the three possibilities
which module F52 can perform are listed below under (a), (b), and
(c). Listed under these three major categories are several
subdivisions that are the additional necessary (or possible)
decisions comprising that area of the program; it must be
remembered, however, that the material below is only a general
overview of the major program decisions.
a. When Reset and Ignore is not set, then: Closed subroutine F36X02
is called if reroute is set, and only if reroute is set. Then,
whether reroute is set or not, a check is always made to see if the
malfunction is associated with a diagnostic request concerning the
marker:
1. If the malfunction is associated with a diagnostic request on
the marker (FCCMJI = 1), then closed subroutine F34X05 is called to
clean up the request and schedule the clients next program. In
addition, if test call mode is used, F52 performs the operation
listed under the second paragraph of condition.
Or 2. if the malfunction is not associated with a diagnostic
request on the marker (FCCMJI = 0), then control is passed to
closed subroutine F38X04 so that if the I/O request is in progress
(the job being a termination attempt by the TM), it may be aborted.
If the request is in progress, then in addition to the job being
aborted, the work area will be hitched to a special hitching post,
unless that hitching post is busy, in which case the user's error
program is scheduled with FWAEIO = 8.
next, the interupting marker is placed MOS (via a call to CONFIG).
A unit Just-Ignore MANIAC is then put on the interrupting marker, a
DIARQT for marker isolation is made, and the Reset and Ignore
malfunction MANIAC is put on the other marker pair. Then F32X01 is
called to scan the I/O queues, after which control is returned to
ICAP.
b. When Reset-and-Ignore is set, and an I/O request is in progress
with the marker, then: If the maintenance request is not waiting
for standby (see page 1 of flowchart), then: The client requested
error program is scheduled with FWAEIO = 8. Otherwise, if the
maintenance request is waiting for standby, then: The I/O request
is a diagnostic program for an OM, the (replacement) marker is not
yet employed by the diagnostic program, and at this time an
unrelated malfunction indication occurs in connection with the
marker (maintenance request not waiting for standby). This
malfunction indication, however, is ignored and the marker is still
employed by the diagnostic program; that is, F52 still continues
processing as if the marker malfunction was not indicated.
Next, whether the maintenance request is or is not waiting for
standby, the Reset and Ignore Override indicator (FWARIO) is
checked:
1. If FWARIO is set, the malfunction interrupt sense line will be
reset. Then, F32X01 is called to scan the I/O queues, and then
control is returned ICAP.
Or 2. if FWARIO is not set, the marker is reset and a on-line
transmission is sent to the marker. Then, F32X01 is called to scan
the I/O queues, and then control is returned to ICAP.
c. When Reset-and-Ignore is set, and an I/O request is not in
progress with the marker, then: K70X01 is called to check if RJ
(Register Junctor) needs to be cleared. An on-line transmission is
sent to the marker. Then F32X01 is called to scan the I/O queues,
and control is then returned to ICAP.
* * * * *