U.S. patent number 3,757,510 [Application Number 05/268,291] was granted by the patent office on 1973-09-11 for high frequency electronic watch with low power dissipation.
This patent grant is currently assigned to Hughes Aircraft Company. Invention is credited to Hans G. Dill.
United States Patent |
3,757,510 |
Dill |
September 11, 1973 |
HIGH FREQUENCY ELECTRONIC WATCH WITH LOW POWER DISSIPATION
Abstract
An extremely thin and small electronic watch made possible by a
crystal oscillating in the megahertz range and coupled to the
display of the watch through two frequency dividers having
basically different characteristics.
Inventors: |
Dill; Hans G. (Costa Mesa,
CA) |
Assignee: |
Hughes Aircraft Company (Culver
City, CA)
|
Family
ID: |
23022301 |
Appl.
No.: |
05/268,291 |
Filed: |
July 3, 1972 |
Current U.S.
Class: |
368/87; 331/116R;
331/116FE; 968/824; 968/902; 327/437; 968/879 |
Current CPC
Class: |
G04G
3/02 (20130101); G04F 5/063 (20130101); G04G
17/04 (20130101) |
Current International
Class: |
G04F
5/06 (20060101); G04G 3/02 (20060101); G04G
17/00 (20060101); G04F 5/00 (20060101); G04G
17/04 (20060101); G04G 3/00 (20060101); G04c
003/00 (); G04b 019/30 () |
Field of
Search: |
;58/23R,23A,5R,53
;235/92T ;307/225 ;328/44,48 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Wilkinson; Richard B.
Assistant Examiner: Jackmon; Edith S.
Claims
What is claim is:
1. An electronic watch comprising in combination:
a. a quartz crystal-controlled oscillator operating at a frequency
above one Mhz, and including
1. a quartz crystal and
2. a first integrated circuit chip formed of silicon-on-saphire and
having therein the circuit components of said oscillator connected
to said crystal and a frequency divider, connected to said
oscillator circuit to frequency divide its output by a first
factor;
c. a second integrated circuit chip formed of silicon and having an
inherently lower leakage current but inherently higher nodal
capacitance than said first chip, said second chip including a
second frequency divider connected to frequency divide the output
of said first frequency divider by a second factor which is
substantially greater than said first factor;
d. a display device; and
e. means for driving said display device in response to the output
of said second frequency divider.
2. In an electronic watch the combination comprising:
a. an insulating base panel;
b. an electrically conductive pedestal extending from a surface of
said base panel;
c. a rectangular, DT cut quartz crystal mounted on said base panel
parallel to the surface of said panel, with the center of the
crystal resting upon said pedestal for both electrical contact and
mechanical support; and
d. at least one integrated circuit chip mounted on said base panel,
said chip including elements connected to said crystal and to each
other to form an oscillator circuit and also including additional
elements interconnected to form a frequency-dividing circuit
connected to frequency divide the output of said oscillator
circuit.
3. The combination of claim 2 characterized further by the
provision of an electrically conductive holder for said crystal,
said holder making both electrical and mechanical contact with a
face of said crystal in exact alignment with said pedestal, and
being mechanically anchored upon said panel surface.
Description
Reduction in the size and particularly the thickness of electronic
watches to which the present invention pertains is a continuing
industry objective. Present electronic watch movements, utilizing a
quartz crystal time base, coupled through an electronic frequency
divider to a display, tend to be too thick, even for mens' watches.
For ladies' watches, their size is prohibitive. The reason for the
relative thickness of quartz-controlled watch movements is the
quartz crystal itself. It is hermetically sealed in a case and its
size is inversely proportional to the frequency at which it
vibrates. Presently quartz crystals for watches operate in the
relatively low frequency 30 to 50 kilohertz region, and at these
frequencies, they are more than a tenth of an inch thick and may be
as long as seven-tenths of an inch long.
Crystal size may, of course, be reduced by increasing its operating
frequency, but only at the cost of aggravating another problem
inherent in electronic watches -- power consumption. The higher the
frequency at which the quartz time base of an electronic watch
vibrates, the more stages are required to bring its frequency down
to that required for operating the watch display. And, since
frequency division in electronic watches is universally done
through a series of binary stages, each of which divides by only a
factor of two, it will be appreciated that each ten-fold increase
in crystal frequency requires the addition of more than three
binary dividing stages. Thus, crystal size reduction through
increased crystal operating frequency comes at the cost of a
considerable increase in power consumption. Moreover, in presently
used frequency dividers utilizing monolithic CMOS circuits, power
consumption in any given stage is proportional to frequency. Thus,
as operating frequency is increased from the tens of kilohertz
toward the thousands, power consumption using conventional CMOS
circuits increases geometrically. That is why watch control quartz
crystals are large and operate at relatively low frequencies. They
operate from power cells whose total energy output is limited.
Reduced size would come only at the expense of frequent and costly
energy cell changes.
It is the principal object of the present invention to overcome the
current impasse between the size and power consumption of quartz
controlled electronic watches and to produce such a watch of
radically reduced size while keeping its power consumption at an
acceptable level.
More specifically, it is the object of the present invention to
reduce the size of a quartz-controlled electronic watch by
increasing the frequency at which its crystal vibrates from the
kilohertz to the megahertz range, but without prohibitively
increasing the current drain of the watch.
A closely related object of the present invention is to provide a
megahertz to hertz frequency divider for a quartz crystal
controlled electronic watch whose current drain is comparable to
that of currently available kilohertz to hertz frequency
dividers.
Additional features and advantages of the invention will become
apparent from the following figures in which:
FIG. 1 is a perspective view of an exemplary ladies' wrist watch
embodying features of the invention;
FIG. 2 is a block diagram of the "movement" of the watch of FIG. 1
which incorporates all of the components necessary to generate and
display time signals;
FIG. 3 is a plan view of an assembly which includes the first three
blocks of FIG. 2 mounted on one side of a base panel;
FIG. 4 is a cross-section along lines 4--4 of FIG. 3 illustrating
generally the manner in which the quartz crystal is mounted upon
the base panel of FIG. 3;
FIG. 5 is a magnified diagram of a portion of FIG. 4 illustrating
in greater detail some of the aspects of the quartz crystal and its
mounting;
FIG. 6 is an enlarged cross-section through an alternative type of
quartz crystal which may be used instead of the crystal illustrated
in FIGS. 3-5;
FIG. 7 is a plan view of the quartz crystal illustrated in FIG.
6;
FIG. 8 is a plan view of the "movement" illustrated in block
diagram form in FIG. 2, and shows in particular the liquid crystal
display panel which may be used therewith;
FIG. 9 is a side view of the watch movement of FIG. 8 showing the
manner in which the liquid crystal display panel is mounted on one
side of a face support panel and the electronic package shown in
FIG. 3 is mounted on the opposite side thereof;
FIG. 10 is a plan view of the back side of the watch movement
illustrated in FIGS. 8 and 9, showing the possible disposition of
the components which comprise the electronic portion of the watch
movement;
FIG. 11 is a smaller and simpler alternative to the package shown
in FIGS. 3, 4 and 5, and is adapted for driving an electric motor
geared to the hands of a watch having a conventional type of
display face;
FIG. 12 is a block diagram of an exemplary oscillator and high
frequency divider which is depicted as a single block in FIG. 2,
with FIG. 12 showing it to be comprised of an oscillator, a
two-phase clock generator, and a series of dynamic divide-by-two
stages;
FIG. 13 is a functional circuit diagram of the oscillator and
two-phase clock generator referred to in FIG. 12;
FIG. 14 is a functional circuit diagram of the dynamic divider
referred to in FIG. 12;
FIG. 15 is a detailed circuit diagram of the oscillator and
two-phase clock generator depicted in FIGS. 12 and 13;
FIG. 16 is a detailed circuit diagram of the dynamic divider
depicted in FIGS. 12 and 14; and
FIG. 17 is a timing diagram showing the wave forms used to drive
the successive dynamic dividers and the conditions at several
points in those dividers which respond to the driving signals.
A ladies' wrist watch 11 made possible by the present invention is
shown approximately to scale in FIG. 1. In successive lines on the
face of the watch are shown the time in hours and minutes, the
seconds, and the month and day of the year.
In order to make possible the size of watch illustrated in FIG. 1,
the electronic "movement" is divided into four principal parts. In
addition to the quartz crystal 13, there is provided a first
microelectronic chip 15, which includes an oscillator circuit
connected to the quartz crystal 13 for generating a time base. The
chip 15 also includes a high frequency divider for converting the
extremely high frequency, preferably in excess of one megahertz,
timing signals generated by the oscillator into lower frequency
timing signals comparable to those generated by currently available
quartz crystal oscillators. The third principal component of the
watch movement is a second microelectronic chip 17 which includes
electronic circuitry for dividing the relatively low frequency
output of the first chip 15 to substantially real time frequency
signals. Also incorporated in the second chip 17 are additional
display electronic circuits for converting its real time signals
into signals suitable for driving the fourth principal element of
the watch movement, a display device 19, which may be either a
liquid crystal digital display, or a light-emitting diode digital
display or the equivalent
An electronic assembly 20 constructed in accordance with the
present invention to drive a digital display is illustrated in FIG.
3. Its approximate size is indicated to be approximately 400
.times. 500 mils, or about the size of a man's thumbnail. It will
be appreciated, of course, that the size of the circuit assembly
illustrated in FIG. 3, as well as those illustrated in the other
figures, are given for purpose of illustration only, to help the
reader appreciate the miniaturization effected by the invention. It
is not meant to indicate that all circuits constructed in
accordance with the invention will necessarily be of the
illustrated size. The assembly of FIG. 3 is built upon a
non-conductive base panel 21, upon one side of which the quartz
crystal 13 and the frequency divider chips 15 and 17 are mounted.
In keeping with the invention, the oscillator and high frequency
divider circuit 15 occupy a physically separate chip from the low
frequency divider and display electronic circuit 17. In order to
permit the oscillator and high frequency divider circuits 15 to
operate in the increased frequency range dictated by the quartz
crystal 13 which oscillates above a megacycle, the circuits 15 are
incorporated in an integrated circuit chip which is characterized
by low power dissipation at very high frequencies, this being
achieved by a uniquely low node capacitance. In particular, it is
proposed herein that the oscillator and high frequency divider
circuits 15 be incorporated in that type of an integrated circuit
wherein a semiconductor layer, such as silicon, is deposited on an
insulating layer such as sapphire.
A suitable circuit configuration for the oscillator and high
frequency divider 15 is shown in FIGS. 12 through 17. Suffice it to
say at this point that the circuit operates in cooperation with the
quartz crystal 13 to produce precisely timed pulses at a rate of
about one megacycle or higher and serves also to frequency-divide
those timed pulses by a pre-determined factor, which will typically
be of the order of 16 or 32. The output produced by the circuits
15, which will typically be a precisely timed pulse train having a
frequency of the order of 100 kilohertz to one megahertz, is then
applied to the low frequency divider and display electronic
circuitry incorporated in the larger chip 17, which may utilize
circuitry of conventional design. The input input pulse train
received by the circuit 17 is further divided in frequency down to
a frequency of one pulse per hour. Additionally, the display
electronic circuit portion of the chip 17 converts the pulses of
various frequencies to signals suitable for driving a digital
display such as a liquid crystal or a light-emitting diode array.
Further details concerning the low frequency divider and display
electronics chips 17 would unduly burden this description, since
such circuits are, by now, well known to those skilled in the art.
They are usually incorporated in a single silicon chip and feature
C/MOS circuit elements for minimum power consumption. See, for
example, "C/MOS Digital Wristwatch Features Liquid Crystal
Display," ELECTRONICS, April 10, 1972, page 93.
While the details of the circuit chip 17 do not form a part of the
present invention, it is an important feature of the invention that
the high frequency divider 15 and the low frequency divider portion
of the circuit 17 are formed in separate integrated circuit chips
having fundamentally different operating characteristics. In
particular, the high frequency divider 15 is characterized by low
node capacitance, achieved by the use of a silicon-on-insulator
chip, which because of its low nodal capacitance permits circuit
operation at extremely high frequencies without excessive power
consumption.. On the other hand, the lower portion of the frequency
dividing chain of the watch circuit illustrated in FIG. 3 is formed
in a monolithic semiconductor substrate such as silicon, and
features circuitry, such as C/MOS, characterized by a very low
leakage current but not necessarily the same low nodal capacitance
which characterizes the chip in which the high frequency divider
portion of the circuit is incorporated. Consequently, even though
it is contemplated that the circuit 17 would contain a
substantially larger number of frequency dividing stages than the
integrated circuit chip 15, the current consumption of the
integrated circuit chip 17 would not be excessive because of its
inherently low leakage current.
Another important advantage of utilizing separate integrated
circuit chips for the functions to be performed by the circuits 15
and 17 is that the type of integrated circuit necessary to permit
high frequency operation above one megacycle is quite expensive and
would raise the cost of the assembly 20 considerably if it were
also used for the remainder, or lower frequency portion, of the
circuit. Separating the high and low frequency portions of the
watch circuit permits the lower cost monolithic semiconductor
substrate technology to be utilized in those circuits which do not
require the advantages, such as the lower node capacitance, which
are attainable only with the higher cost integrated circuit
utilized for the high frequency portion 15 of the watch assembly.
Although the low frequency dividing stages and the display
electronics are described herein as being on a single monolithic
chip 17, it would be within the scope of the present invention to
put them on separate monolithic chips, to simplify fabrication.
Turning next to the quartz crystal 13, it is shown in FIGS. 3, 4
and 5 as being supported at its center upon an electrically
conductive pedestal 23, against which it is secured by a metal
bracket 25. For a frequency not much above (2.sup.20) one
megahertz, a DT cut quartz crystal may be used. A DT cut quartz
crystal vibrates in the face-shear mode wherein the crystal
alternately contracts and expands along intersecting diagonals.
Electrodes 14 and 16 extend along opposite faces of the quartz
crystal wafer 13 and serve to impose upon the crystal the
potentials which cause vibrations. In accordance with a structural
feature of the present invention, the pedestal 23 and the bracket
25 serve not only to support the crystal wafer securely parallel to
the base panel 21 at the center of the wafer, but they also serve
to apply the electric potentials to its electrode 14 and 16. For
this purpose, printed circuit connectors 27 and 29 lead up to the
pedestal 23 and the bracket so as to interconnect them with the
oscillator circuit incorporated in the integrated circuit chip 15.
Through conductors which may be formed on the panel 20 but which
are not shown, the chips 15 and 17 are interconnected to one
another, to the crystal 13 and to a set of feed-through connectors
32, so that the display signals generated by the chip 17 may be
applied to whatever digital display device may be supported on the
opposite face of the panel.
A quartz crystal and a manner of mounting it suitable for
frequencies in the nine megahertz range are shown in FIGS. 6 and 7.
They show a crystal 13a with an AT cut wherein the quartz crystal
is caused to vibrate in the thickness shear mode with major faces
of the crystal wafer moving in opposite directions which reverse
cyclically. Whereas the frequency of vibration of the DT cut
crystal illustrated in FIGS. 3-5 is determined by its width and
length, the vibration frequency of the AT cut quartz crystal is a
function of its thickness. For a vibration frequency in the nine
megahertz range the quartz crystal 13a should have a thickness
approximately 7 mils (thousandths of an inch). The size of the
quartz crystal wafer utilizing the AT cut will be approximately the
same as that of the DT cut crystal. Thus, a typical size for the
quartz crystal of FIG. 6 will be approximately 80 by 100 mils
whereas the typical size for the quartz crystal of FIGS. 4-5 will
be approximately 100 by 100 mils.
As shown in FIG. 6, the method of mounting the AT cut crystal 13a
may be considered more secure than that for mounting the DT cut
crystal. For this reason it may be preferable. Thus, the AT cut
crystal is mounted at opposite ends upon a pair of electrically
conductive pillars 33 to which the crystal is secured by means of a
suitable bond such as a silver filled epoxy 35. Electrical contact
is made from the respective pillars 33 through the silver filled
epoxy bond 35 to a pair of electrodes 16a and 14a which extend
respectively along the bottom and the top of the crystal. Electric
potentials for vibrating the crystal are again provided through
conductors which may be formed on the base panel 21. Further
details concerning the theory of operation of quartz crystals cut
either AT or DT may be found in the HANDBOOK OF PIEZOELECTRIC
CRYSTALS FOR RADIO EQUIPMENT DESIGNERS, WADC Technical Report
56-156, ASTIA Document No. AD110448, particularly at pages 38 and
42.
A "movement" for an electronic watch including a digital display is
illustrated in FIGS. 8, 9 and 10. Essentially it comprises an
electronic assembly 20a which corresponds to the electronic
assembly 20 showing FIGS. 3 and 4 but whose base panel 21a extends
to accommodate a battery 41, a 1.5 to 15 volt up-converter 43, to
convert the battery voltage to the voltage necessary for driving a
liquid crystal display, and a trimming capacitor 45 which is
connected into the oscillator circuit for adjusting its frequency.
Connected to the electronic assembly 20a through a series of
feed-through connecting pins 21 is a liquid crystal display panel
39 extending along the opposite face of the base panel 21a. Since
liquid crystal displays for watches are now commercially available
(see the above-referenced ELECTRONICS article), the display panel
39 need not be described in detail. Its importance to the
combination is the manner in which it is compactly packaged on one
side of a base panel, on the opposite side of which all of the
electronic circuitry required to drive the display panel are
mounted. In the illustrated display panel 39 the hour and minute
are shown in the top line, the first digit of the second is shown
in the second line, with the month and day appearing in the bottom
line of the display. Two rows of dots are disposed to the right of
the numeral indicating the first digit of the second, these dots
being illuminated in succession to indicate the passing of
successive seconds. Thus, when the 59th second of a given minute
arrives, nine of the ten dots are illuminated.
In the foregoing paragraphs, there has been described an electronic
assembly for driving a digital display and an electronic watch
"movement" incorporating both the digital display and the
electronic assembly. The present invention, however, also finds use
in driving a conventional display wherein a minute hand and an hour
hand are moved across the face of a watch by an electric motor. An
electronic assembly intended for this type of application will be
smaller than its counterpart intended for driving a digital display
because there will not be a need for generating the rather complex
set of signals which a digital display requires. Such an assembly
is shown in FIG. 11, drawn to the same scale as the more complex
assembly appearing in FIGS. 3-5. Otherwise the electronic assembly
of FIG. 11 for driving a watch motor is shown to be comprised of
the same principal components; namely, a quartz crystal 49, an
oscillator and high frequency divider chip 51, and a low frequency
divider chip 53, all mounted on a common base panel 55.
Feed-through connectors 57 provide the electrical path for applying
the output of the low frequency divider 53 to the watch motor which
will usually be mounted on the opposite side of the panel.
A suitable circuit for performing the function of the oscillator
and high frequency divider chip 15 is illustrated in FIGS. 12
through 17. Preferably, it is constructed in silicon-on-sapphire
(SOS) and uses CMOS circuit elements. As shown in FIG. 12, the
SOS-CMOS circuit chip 15 basically includes an oscillator 101, a
two-phase clock generator 103 driven by the oscillator, and a
series of dynamic divide by two stages 105 each dividing the output
of the preceding stage by two.
Referring to FIG. 12, the oscillator 101 is principally comprised
of an inverting amplifier 107 whose output is connected to its
input through a feedback loop 109. The two-phase clock generator
103 includes an inverting amplifier 111 for buffering the output of
the oscillator 101 and an additional inverting amplifier 113 to
derive the desired inverse of the output of the buffering amplifier
111. Also connected to the output of the inverting amplifier 111 is
a transfer gate 115 whose function is to delay the output of the
inverting amplifier 111 by the same amount as it is delayed by the
inverting amplifier 113. In this manner the .phi. or in-phase
output which appears at the output of the clock generator 103 will
be precisely out of phase with the .phi. output of the
generator.
Referring next to FIG. 14, each dynamic divide by two stage 105 is
comprised of a pair of transfer gates 116 and 119, with the output
of the first transfer gate 116 being applied to the input of the
second transfer gate 119 through an inverting amplifier 117 and
with the output of the second transfer gate 119 being fed through a
pair of series-connected inverting amplifiers 121 and 123 to the
output of the divider stage labelled .phi..sub.N. The inverse of
that output, .phi..sub.N, is derived from the output of the first
of the two inverters 121. During each two successive cycles of an
input signal received by a dynamic stage 105, that stage will go
through one complete cycle of its operation and will change states
twice. The state from which the dynamic divider 105 changes is
sensed through the feed-back loop 125 and determines the next state
which it will assume.
Turning next to FIG. 15 for a more detailed description of the
circuit of oscillator 101, it includes, as mentioned previously, an
inverting amplifier 107 having a feed-back loop 109 connected
between its output and its input. The inverting amplifier 107
includes a pair of MOS transistors 139 connected in series between
a pair of power terminals shown as ground and a source of positive
potential, labelled +.
The output of the amplifier 107 is taken from the junction of the
devices 139 and 141 and is labelled 143. The input of the amplifier
107 is the point 142 representing the connection between the gates
of the devices 139 and 141. Connecting the output 143 and the input
142 is the feedback loop 109 which includes the quartz crystal 13
having a pair of electrodes 14 and 16 and a biasing resistor 133 in
parallel therewith, with the function of the resistor being to
insure that the amplifier is biased into the linear region of its
operation. Also forming part of the feedback loop 109 are a pair of
capacitors 135 and 137, the former being connected from the point
142 to ground and the latter, a variable trimming capacitor, being
connected to ground from the junction point 143. Oscillation is
accomplished as a result of the 90.degree. phase shift introduced
by the inductive nature of the quartz crystal 13 and by an
additional 90.degree. phase shift introduced by the fixed capacitor
135. An additional phase shift of approximately 180.degree. is
introduced by the inverter amplifier 107 so that, with the
components properly selected, the total phase shift through the
entire circuit comes out to exactly 360.degree., thereby insuring
oscillation.
The output of the oscillator 101, taken from the point 143, is
buffered and inverted by the inverting amplifier 111 which is
comprised of a pair of MOS opposite conductivity type devices 145
and 147 connected in series between ground and the positive
potential source +. Then, as mentioned previously, the output of
the first inverter 111 is fed through a second inverter 113,
comprised of a pair of series-connected P and N transistors 157 and
159 to obtain the desired .phi. signal. The output of inverter 111
is also fed through a transfer gate 115 to delay it by the same
amount as the delay introduced by the inverter 113. The transfer
gate 115 is comprised of a pair of opposite conductivity type
devices 149 and 151 connected in parallel, with their gates biased
into conduction at all times so as to add a sufficient resistance
to the current path from the positive potential source + to the
output point 155 so as to bring the total resistance of that path
to the same level as the resistance of the path from the positive
potential source + to the .phi. output 156. Thus, by making the
resistances of the current paths to the .phi. and the .phi. output
points 155, 156 the same, the timing of the output pulses at those
points is also made identical.
Operation of the dynamic divider will be described in terms of
switching of a series of circuit points, or nodes, in the circuit
labelled 164, 166, 170, 172 and 174 in response to a pair of clock
signals .phi. and .phi.. The waveforms .phi. and .phi. are
complementary so that when one is at a logic 1, or high voltage
level, the other is at a logic 0, or low voltage level. In order to
turn on the first transfer switch 116 and to turn off the second
transfer switch 119 when clock signals .phi. and .phi. are
respectively high and low, .phi. is applied to the gates of the N
and P transistors 163 and 165 of the two switches, and .phi. is
applied to the gates of their P and N transistors 161 and 167. The
voltage levels assumed by the various nodes in response to the
switching of the clock signals .phi. and .phi. are represented by
the waveforms A and B in FIG. 17.
Considering first the initial state of the circuit prior to the
time t.sub.0 (see FIG. 17), .phi. is low and .phi. is high, causing
the transfer switch 116 to be off, or open, and causing the
transfer switch 119 to be on, or closed. For purpose of this
explanation, let it be assumed that the node 164, representing the
output of switch 116, is at a low level. As this description
proceeds, it will be seen that this assumption is justified by the
behavior of the circuit. If the node 164 is low, then the node 166
is high, as is the node 170, since the closed transfer switch 119
transmits the voltage level at its input. The node 172 is low, due
to the inverter 121, and the node 174 is, agains, high, because of
the inventer 123. Since the switch 116 is open, the signal at the
node 174 is stopped short of reaching the node 164. Therefore, node
164 remains low. The voltage level at the node 164 is represented
by the waveform A and the voltage levels at the nodes 170 and 174
are represented by the waveform B.
At time t.sub.0, .phi. and .phi. reverse states. With .phi. going
high, switch 116 is turned on, and with .phi. going low, the switch
119 is turned off. This puts the node 170 into a dynamic storage
mode in which it is isolated at the high voltage level and remains
at that same high level. It should be noted that the nodes 164 and
170 float when their associated switches 116 and 119 are open. In
this state, the nodes function as a dynamic storage capacitor which
retains a charge and an associated potential for a brief period of
time, after which the charge may leak off. Consequently, the switch
which works into the node must not operate too slowly.
Initially then, at t.sub.0 the voltage at the node 174, which
remains unchanged at a high level, is applied through the now
closed switch 116 to the node 164, causing it to go from low to
high (A is high). During t.sub.0 - t.sub.1 conditions remain
stable, with the node 170 being the only one of the two to be in a
dynamic storage mode.
At time t.sub.1, the clocks .phi. and .phi. again reverse, causing
switch 119 to close and 116 to open simultaneously. Node 164 is
isolated and remains at the high level. However, closing of the
switch 119 causes the node 170 to assume the state of node 166,
which is the inverse of the state of node 164 and is, hence, low.
Consequently, the node 170 also goes low (B is low).
At time t.sub.2, the clocks .phi. and .phi. again interchange,
closing the switch 116 and opening the switch 119. Node 170 is
again isolated and remains low. Node 164 assumes the state of node
174 through the feed-back loop 125 and the now-closed switch 116,
causing it to go from high to low (A goes low). This remains until
time t.sub.3 when .phi. and .phi. again reverse, causing the switch
116 to open and switch 119 to close. This isolates the node 164 at
its low level. The now closed switch 119 transfers the voltage
level at node 166 to the storage node 170, causing it to go from
low to high (B goes high). This returns the circuit to its initial
state and subsequent reversals of the clocks .phi. and .phi. simply
repeat the events described.
Outputs of each dynamic divider stage 105 are taken from the nodes
174 and 172 and become the clock signals .phi. and .phi. for the
next lower order stage in the chain of dividers.
From the foregoing it will be apparent that the present invention
makes it possible to produce a quartz crystal-controlled electronic
watch of greatly reduced size without unduly increasing its power
consumption. This is brought about by utilizing a quartz crystal
vibrating at a much higher frequency than those currently in use,
thus drastically reducing the size of the largest single component
of electronic watches. The use of such a high frequency crystal
without increasing power consumption due to the increased number of
frequency-dividing stages required is made possible by the use of
two frequency dividers of fundamentally different characteristics.
The high frequency end of the total frequency dividing chain used
to bring down the crystal frequency is designed to have an
acceptably low current drain at or near the crystal vibration
frequency. Yet, for the sake of minimizing circuit costs, the lower
frequency portion of the frequency dividing chain is formed of
conventional circuit components whose current drain at the lower
frequencies are within acceptable limits.
Not only does the use of a high frequency quartz crystal reduce
size, it also increase the accuracy of the watch, since it is well
known that the higher the clock frequency, the more accurate is the
watch. Reduced size also promotes a more rugged package and, by
using a sufficiently small crystal as suggested by the present
invention, the quartz crystal may be packaged in a single container
along with the semiconductor components used in the watch. This
tends to further reduce size and cost. Indeed, the expected size of
a watch "movement" made in accordance with the pre sent invention,
with a quartz crystal operating in the megacycle range, is
comparable to that of a currently used 32 kilohertz quartz crystal
and its housing.
* * * * *