U.S. patent number 3,718,502 [Application Number 04/866,692] was granted by the patent office on 1973-02-27 for enhancement of diffusion of atoms into a heated substrate by bombardment.
Invention is credited to James F. Gibbons.
United States Patent |
3,718,502 |
Gibbons |
February 27, 1973 |
ENHANCEMENT OF DIFFUSION OF ATOMS INTO A HEATED SUBSTRATE BY
BOMBARDMENT
Abstract
This invention describes a method of enhancing the diffusion of
atomic species carried on the surface of a solid substrate into the
substrate by elevating the temperature of the substrate to permit
atoms and vacancies to propagate and then creating vacancies in
selected regions of the substrate through bombardment by a beam of
protons or other particles, said bombard-ment acting to enhance
diffusion of the surface atom species into the substrate at said
regions.
Inventors: |
Gibbons; James F. (Palo Alto,
CA) |
Family
ID: |
25348179 |
Appl.
No.: |
04/866,692 |
Filed: |
October 15, 1969 |
Current U.S.
Class: |
438/536; 257/655;
257/E21.135; 427/523; 438/186; 438/375 |
Current CPC
Class: |
H01L
21/00 (20130101); H01L 21/22 (20130101); H01L
29/00 (20130101); H01L 21/263 (20130101) |
Current International
Class: |
H01L
21/00 (20060101); H01L 29/00 (20060101); H01L
21/02 (20060101); H01L 21/22 (20060101); B44d
001/18 (); B44d 001/20 () |
Field of
Search: |
;117/212,93.3,38,213
;148/188,183,191 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Kendall; Ralph S.
Assistant Examiner: Esposito; M. F.
Claims
I claim:
1. The method of enhancing diffusion of selected atom species in a
solid semiconductor substrate which comprises elevating the
temperature of the substrate to a temperature which permits
interstitial lattice atoms and lattice vacancies to move freely in
the substrate, providing said selected atom species at a surface of
the substrate, and bombarding at least one surface of said
substrate while the temperature is elevated with a beam of
non-dopant particles selected such that the particles collide with
atoms of the substrate to dislodge the atoms from their lattice
positions and create lattice vacancies which move freely in the
substrate, said temperature being such that said lattice vacancies
can move to interact with said selected atom species to cause atoms
of the species to diffuse in said substrate, said elevated
temperature and particles further being selected such that the
bombarding particles do not cause gross damage in the substrate at
said elevated temperature.
2. The method as in claim 1 wherein said temperature is below the
temperature which would produce significant diffusion of atomic
species in the solid substrate.
3. The method as in claim 2 in which said selected atom species at
a surface of the substrate is provided by the additional step of
predepositing on said surface a layer of material containing the
selected atom species which is to be diffused into the
substrate.
4. The method as in claim 2 wherein said substrate is silicon and
said predetermined temperature is in the range of 450.degree. -
700.degree.C.
5. The method as in claim 2 wherein said substrate is germanium and
the elevated temperature is in the range of 360.degree. -
500.degree.C.
6. The method as in claim 3 wherein said predeposited layer is
deposited only over selected areas of the surface.
7. The method as in claim 2 including additionally providing a mask
having one or more openings on said surface whereby to intercept
particles and prevent the formation of lattice vacancies in the
substrate beneath the mask and permit particles to pass through
said openings to bombard the substrate and form lattice vacancies
in the region of said openings by dislodging atoms from their
lattice positions.
8. The method as in claim 2 wherein selected areas are bombarded by
focusing and directing the particle beam.
9. The method as in claim 2 wherein said particle beam comprises a
proton beam having energies above 1 keV.
10. The method as in claim 1 wherein the damage previously existing
in the semiconductor is annealed on account of the enhanced
diffusion.
11. The method as in claim 10 wherein the damage is produced by
introducing the atomic species using the ion implantation
technique.
12. The method as in claim 10 wherein the damage is produced during
the formation of an oxide layer or other protective coating on said
semiconductor surface.
13. The method as in claim 10 wherein a protective layer is applied
over said semiconductor to inhibit the escape of atomic species
from the surface during the enhanced diffusion.
14. The method of enhancing diffusion of selected atom species into
a semiconductor substrate which comprises the steps of
predepositing on at least one surface of said substrate a layer of
material containing the selected atom species, elevating the
temperature of the substrate to a temperature which permits
interstitial lattice atoms and lattice vacancies to move freely in
the substrate, said temperature being below the temperature which
would produce significant diffusion of the selected atom species
into the substrate, and simultaneously bombarding at said surface
selected areas of the substrate with a non-dopant particle beam for
the substrate so that the particles collide with atoms in the
substrate to dislodge atoms from their lattice position and create
lattice vacancies which move freely in the substrate at said
elevated temperature to interact with said selected atom species at
said elevated temperature to enhance diffusion of the selected atom
species from the surface into the substrate, said temperature and
particle beam being such that no gross damage is caused in the
substrate.
15. The method as in claim 14 in which said substrate is
semiconductive material characterizing one conductivity type and
said layer contains atom species characterizing an opposite
conductivity type to thereby form a region in said substrate which
defines a rectifying junction in said substrate.
16. The method as in claim 14 in which said substrate is
semiconductor material characterizing one conductivity type and
said layer contains atom species characterizing said one
conductivity type.
17. The method as in claim 14 in which said substrate is
semiconductor material characterizing one conductivity type and
said layer contains atom species characterizing both said one
conductivity type and an opposite conductivity type, said atom
species of opposite conductivity type having a higher diffusion
coefficient than said atom species of said one conductivity type
whereby said atom species of said opposite conductivity type
diffuses further into said substrate than the atom species of said
one conductivity type to form two rectifying junctions in said
substrate.
18. The method as in claim 14 in which said layer is applied on
selected areas of said surface.
19. The method as in claim 14 wherein a mask is provided over said
layer, said mask containing openings in those regions which are to
be diffused into said substrate and serving to inhibit penetration
of said particles in said substrate in other regions.
20. The method as in claim 14 wherein said bombardment is focused
and directed to selected areas of said surface.
21. The method as in claim 15 in which there is provided the
additional step of applying a second layer of said one conductivity
type to said substrate, elevating the temperature of the substrate,
and thereafter bombarding said substrate to form a second region
which forms a rectifying junction with the first region.
22. The method as in claim 15 in which there is thereafter provided
a layer of said opposite conductivity type, the temperature is
elevated and the surface is bombarded to form an ohmic connection
to said region.
23. The method as in claim 14 in which the energy of said beam is
controlled to provide diffusions at different depths in said
substrate.
24. The method as in claim 14 wherein a protective coating is
applied over said layer and the energy of the bombarding beam is
selected to penetrate said layer into said substrate whereby to
inhibit the escape of either predeposited atom species or
semiconductor lattice atom species from the surface during the
enhanced diffusion.
25. The method as in claim 14 wherein the predeposited layer of
material contains atomic species that control carrier lifetime in
said semiconductor.
26. The method as in claim 14 wherein the predeposited layer of
material contains atomic species that act to compensate the doping
effect provided by atomic species previously introduced into the
semiconductor.
27. The method of enhancing diffusion of selected atom species in a
semiconductor substrate which comprises the steps of providing said
selected atom species, elevating the temperature of the substrate
to a temperature which permits interstitial lattice atoms and
lattice vacancies to move freely in said substrate and bombarding
at least one surface of said substrate while the temperature is
elevated with a non-dopant beam of particles selected such that the
particles collide with the atoms in the substrate to dislodge atoms
from the lattice positions, said temperature selected whereby no
gross damage is caused in the substrate by said particle beam, said
particle beam serving to create lattice vacancies which move freely
in the substrate at said elevated temperature to interact with the
atom species to enhance the diffusion of said selected atom species
in the substrate.
28. The method as in claim 27 wherein said selected atom species is
deposited on said surface.
29. The method as in claim 27 wherein said particle beam comprises
a proton beam having energies above 1 keV.
Description
BACKGROUND OF THE INVENTION
This invention describes a method for controlling and enhancing
diffusion of atoms into a solid substrate by employing a beam of
protons or other particles to raise the apparent temperature of the
substrate and more particularly to the use of such a method in the
formation of P-N junctions, alloyed contacts and ohmic contacts in
a solid substrate and in the control of surface effects and
reduction of surface imperfections.
In the prior art diffusion of atomic species predeposited on a
semiconductor surface has, in general, been carried out at
relatively high temperatures. As a consequence, there has been
resulting damage and imperfections formed, both in the diffused
layers and elsewhere in the substrate, said damage and
imperfections having detrimental effects on the characteristics of
devices produced by the conventional diffusion process. This
invention permits diffusion to occur without raising the substrate
to the high temperatures that produce detrimental effects.
Diffusion of atoms into a substrate to form a junction or ohmic
contact, in general, depends upon the movement of atoms into the
crystalline lattice of the substrate. In general, the impurity
atoms rest in substitutional lattice sites in the host crystal or
substrate. In order for the atoms to diffuse to an adjacent lattice
site, the host atom occupying the site must be moved away to create
a vacant lattice site and the impurity atom must be given
sufficient energy to move into the vacant lattice site. Two
energies correspond to these two processes: the host atom must
absorb an energy E.sub.f to escape from its lattice site, and the
impurity atom must absorb an energy E.sub.m to migrate from its
original position into the newly-created vacancy.
In a thermally-activated diffusion process, it can be shown that
the probability for the host atom to absorb an energy E.sub.f is
proportional to
exp(-E.sub.f /kT)
where k is Boltzmann's constant and T is the absolute temperature;
and similarly that the probability for the impurity atom to absorb
an energy E.sub.m is proportional to
exp(-E.sub.m /kT) . The probability P that both of these events
will occur is proportional to the product of the individual
probabilities, or
P .alpha. e.sup..sup.-E .sup./kT e.sup..sup.-E .sup./kT.
The diffusion coefficient for the impurity is proportional to the
probability P calculated above and can be expressed in the form
D = D.sub.o e.sup..sup.-E .sup./kT e.sup..sup.-E .sup./kT . 1
As an example, in a conventional diffusion of boron into silicon,
the constants take on the values D.sub.o = 10.sup.11 (.mu.m).sup.2
/(hr), E.sub.f .congruent.3 eV and E.sub.m .congruent. 0.3 eV. As a
result, it is necessary to raise the temperature of the silicon to
1,100.degree.C. to achieve a diffusion constant D = 0.16
(.mu.m).sup.2 /(hr).
Values of D of this magnitude are essential for efficient
fabrication of semiconductor devices by the diffusion process,
since the depth to which impurity atoms will diffuse from a surface
is
d .about. 5 .sqroot.dt .mu. m
where D is the diffusion coefficient and t is the time in hours. To
achieve boron doping to a depth d of 1.mu.m in a silicon substrate,
therefore, requires that the silicon be held at 1,100.degree.C. for
1.5 hours. If a substantially lower temperature is used, for
example, 700.degree.C., the value of D given by Eq. (1) becomes so
small that prohibitively long processing times are required.
It is clear from the above description that large values of D are
useful if diffusion processing is to be accomplished in reasonable
times. It is also clear that, if the diffusion process if thermally
activated, large values of D can only be achieved by increasing T
to large values. In some cases this is acceptable, though many
disadvantages can be cited. For instance, crystal imperfections
form more easily and residual dislocation loops increase in size
more rapidly at high temperatures than they do at low temperatures.
Hence, in a thermally activated diffusion, the process that permits
the desired species to diffuse also creates undesirable
imperfections in the crystal. These imperfections may affect the
diffusion of the desired species unfavorably and may also act as
trapping centers for carriers. The trapping centers produce short
carrier lifetimes, and, in general, have deleterious effects on the
performance of devices such as transistors and integrated circuits,
and particularly photodiodes, phototransistors and silicon
vidicons.
Furthermore, the fabrication of electroluminescent diodes in
silicon carbide requires the formation of P-N junctions that must
be diffused at temperatures of 1,800.degree. - 2,000.degree.C. on
account of the very high values of E.sub.f that characterize this
material. These very high temperatures are difficult to achieve.
This makes accurate fabrication difficult and, furthermore, results
in devices whose properties are frequently dominated by the crystal
imperfections introduced during high temperature diffusion
processes rather than the dopant which is introduced.
OBJECTS AND SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a method
of enhancing the diffusion of desired atom species into a solid
substrate.
It is another object of the present invention to provide a method
of diffusing desired atom species into a solid substrate at
relatively low temperatures.
It is another object of the present invention to provide a method
of forming P-N junctions, ohmic and alloyed contacts in a solid
substrate by enhancing diffusion through the use of a proton or
other high energy beam.
It is a further object of the present invention to provide a method
of treating semiconductor substrate to control electronic
properties characterizing the interfaces between the substrate and
the oxide surfaces forming interfaces therewith.
It is a further object of the present invention to provide a method
in which energetic protons and other particles create lattice
vacancies for enhancing the diffusion process.
The foregoing and other objects of the invention are achieved by
subjecting a solid substrate having a thin surface film containing
the desired atom species to be diffused into the substrate to
bombardment by energetic particles such as protons which create
lattice vacancies and enhance the diffusion of the atom species
into the substrate in those areas of the substrate where diffusion
of the atom species into the substrate is desired.
The foregoing and other objects of the invention may become more
clearly apparent from the following description taken in connection
with the accompanying drawing.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A - 1D show the steps in forming a P-N junction in
accordance with the invention.
FIG. 2 shows the vacancy concentration profile for two particle
beam energies.
FIG. 3 shows the impurity profile for boron diffusion in a silicon
semiconductor wafer with proton energies of 10 keV.
FIG. 4 shows the impurity profile for boron diffusion in a silicon
semiconductor wafer with proton energies of 50 keV.
FIGS. 5A - 5C show forming an inset region in a semiconductor
substrate.
FIGS. 6A - 6C show application of the process employing a mask to
define the diffusion region.
FIGS. 7A - 7E show the steps in forming an N-P-N device in
accordance with the invention.
FIGS. 8A - 8B show the steps in forming an N-P-N device by the use
of a single film or layer having two atom species.
FIGS. 9A - 9E show the steps of forming an inset region with an
oxide protected junction.
FIGS. 10A - 10C show the steps in forming an inset region in a
device in which the atom species is captured by protected film.
FIGS. 11A - 11F show the steps in forming a junction field effect
transistor.
DESCRIPTION OF PREFERRED EMBODIMENTS
The method of the present invention will be first described in
connection with the formation of a P-N junction in a semiconductor
substrate. Referring to FIG. 1A, the substrate may, for example, be
a silicon wafer having impurities characterizing N type
semiconductor material. The wafer is suitably etched and processed
to provide a clean upper surface 11. Thereafter, by thermal
deposition, evaporation from an elemental source, chemical
deposition, ion implantation or other well known technique to those
versed in the art, a shallow layer or film of material 12
containing atom species to be diffused into the semiconductor wafer
is applied to the upper surface of the slab, FIG. 1B. In order to
form a P-N junction, in silicon, the layer of material 12 may, for
example, be a relatively thin boron layer which is a P type dopant
for silicon. The wafer is then placed in an evacuated chamber and
means are provided within the chamber to elevate the temperature of
the semiconductor wafer, FIG. 1C. Preferably, the temperature of
the wafer is elevated to a temperature in which the interstitial
lattice atoms and lattice vacancies move relatively freely. This is
generally well below typical diffusion temperatures, being in the
range of 450.degree. - 700.degree.C. and above for silicon, and
360.degree. - 500.degree.C. and above for germanium. Thereafter,
the surface of the device is bombarded with protons using
conventional isotope separator equipment which delivers protons to
the wafer at any desired energy over a wide range of values, for
example, between 1 keV to several hundreds keV. The high energy
particles create lattice vacancies which tend to diffuse through
the structure and enhance the diffusion of the P type boron atoms
into the wafer to form the P-N junction 13, FIG. 1D.
The proton bombardment is continued for a time adequate for the
surface deposited atom species, boron in this instance, to diffuse
to a desired depth thereby forming the P-N junction 13 in the N
type silicon substrate. Typically, the time required may be 0.5 to
1.5 hours, but can be even shorter than this.
It is, of course, apparent that by starting with a P type substrate
and providing an N type layer or film and elevating the temperature
and bombarding the wafer, a P-N junction having a diffused N type
region with a P type substrate is formed. Furthermore, by applying
a layer containing atom species of the type characterizing the
conductivity type of the slab, an ohmic connection can be formed to
the upper surface of the wafer. The ohmic contact can have a
relatively high impurity concentration thereby providing an ohmic
contact having a very low resistance.
Operation of the invention to enhance diffusion can be explained
qualitatively as follows. The energetic protons enter the target
where they occasionally collide with atoms of the host crystal
(substrate) and dislodge them from their lattice positions. Both
the dislodged host atoms and the resulting vacancies in the host
crystal diffuse away from their point of creation, propagating a
region of high defect concentration both toward the surface and
deeper into the body of the crystal. An adequate propagation effect
can be achieved by maintaining the crystal (substrate) at an
elevated temperature. The temperature required will depend on the
substrate, being in the range of 450.degree. - 700.degree.C. and
above for silicon, 350.degree. - 500.degree.C. and above for
germanium. The propagation effect is necessary since otherwise
dislodged host atoms may simply fall back into the lattice sites
from which they came with no net effect; or possibly the vacancies
produced from damage clusters, dislocation loops or other crystal
imperfections.
When conditions for propagation of the bombardment-produced
vacancies are favorable, however, the vacancy concentration in the
surface layers of the substrate can be increased several orders of
magnitude above the value it would have at the substrate
temperature in the absence of proton bombardment. For qualitative
purposes the increase in vacancy concentration in the surface
layers can be thought of as an increase in the surface temperature
of the substrate. Experimental results to be presented later show
that the "equivalent temperature" of the surface layers can be
1,000 - 1,200.degree.C. in a silicon target where the body is
maintained at a temperature of only 700.degree.C. This permits the
atoms predeposited on the surface to diffuse rapidly into the
semiconductor until they reach the "cooler" portions of the target.
The final result is that impurity diffusion can be obtained to a
depth determined by the energy of the proton beam.
It should be mentioned that diffusion does not typically occur at
depths significantly greater than the range of the protons, nor
does it occur on those portions of the surface that may have been
masked by standard techniques or on which the beam is not allowed
to fall as a result of ion focusing arrangements.
A variety of different impurity profiles can be obtained by proper
choice of proton beam energy, dose rate, and diffusion time, as
will be shown later. In every case permanent damage in the body of
the target is avoided so the electronic properties and strength of
the material outside the region of diffusion are far superior to
what they would be if the predeposited species were driven into the
target by a conventional thermally activated high temperature
diffusion process.
Thus, the energetic protons create the lattice vacancies required
for diffusion. The mathematical effect is that the exponential
involving E.sub.f will be eliminated in Eq. (1) with the result
that
D .alpha. D.sub.o e.sup..sup.-E .sup./kT V(x) 2.
where V(x) is the vacancy concentration profile produced by the
bombarding protons. This is a very important modification since it
is the large value of E.sub.f in the exponent of Eq. (1) that
requires that a high temperature be reached before practical values
of the diffusion coefficient can be achieved. By controlling V(x),
D can be controlled without raising the substrate to temperatures
that produce imperfections or to diffusion temperatures which are
difficult to achieve for certain materials such as silicon
carbide.
Theoretical techniques exist for computing V(x). I have found that
many different forms for V(x) can be obtained, depending on initial
energy of the proton beam, the type of substrate used and the
temperature at which the substrate is maintained during the
process. To a first approximation V(x) takes the form
where A and B are constants that have to do with the efficiency
with which energetic protons produce vacancies, .mu. is the range
or average distance travelled by a proton in coming to rest in the
crystal, and .sigma. is a so-called range straggling parameter,
common in particle physics, which accounts for the fact that all
protons do not suffer exactly the same sequence of collisions, so
there is a distribution in the stopping points for the protons
about the average. A more precise form for V(x) can be obtained by
correcting .mu. and .sigma. for vacancy diffusion effects.
Precise computations of the vacancy concentration profiles
including all vacancy diffusion effects have been made for a
silicon target using two different proton energies with the results
shown in FIG. 2. For the case of 10 keV protons, the range .mu. of
the protons is small (0.15 .mu. m), so that the vacancies are all
produced near the surface. The curve labelled 50 keV shows V(x) for
a higher energy proton beam where the proton range is deeper
(.about. 0.55 .mu. m).
A precise mathematical form for the diffusion coefficient D can be
obtained by substituting these forms for V(x) into Eq. (2). It is
then possible to solve the impurity diffusion equation using these
spatially varying diffusion constants to obtain precise predictions
of the impurity doping profiles which would be obtained. However,
for present purposes, it will suffice to give a qualitative
picture.
If a relatively low energy proton beam is used, so that V(x) takes
on the form labelled 10 keV in FIG. 2, only the vacancy
concentration in the surface layers of the target will take on a
value substantially different from the thermal equilibrium value.
Where the vacancy concentration is high, the diffusion constant
will take on a large value. As a result, doping atoms predeposited
in the surface will diffuse rapidly into the surface layers until
they reach a depth where V(x) falls rapidly back to its thermal
equilibrium value. To a first approximation, the high vacancy
concentration in the surface layers is equivalent to a very high
temperature in the surface layers. Atoms can diffuse rapidly
through this highly agitated region, but they stop abruptly when
they reach the "cooler" portions of the target (i.e., portions not
affected by the proton beam).
Typical experimental impurity profiles for bombardment-enhanced
diffusion of boron into silicon are shown in FIG. 3 for a 10 KeV,
40 nanoampere proton beam and several different diffusion times. It
will be clear to persons skilled in the art that the diffusion
constant for boron in silicon has been increased many orders of
magnitude over its value at the substrate temperature of
700.degree.C.
A similar analysis can be made for a vacancy concentration profile
of the form shown in FIG. 2 for a 50 KeV proton beam. Here the
equivalent high temperature layer is inside the crystal rather than
on its surface, so the diffusion constant will be much higher
inside the substrate than it is on the surface. This results in
very gradually graded impurity profiles such as those shown in FIG.
4.
It should be noted that both abrupt impurity profiles such as those
shown in FIG. 3 and gradually graded impurity profiles such as
those shown in FIG. 4 are important in the semiconductor industry;
and further that a great variety of profiles in addition to those
shown can be generated by employing a sequence of different proton
bombardment cycles and substrates temperatures. Furthermore, the
bombarding particles need not be protons (e.g., electrons,
neutrons, helium atoms or other species could be used); though
protons have the advantage of producing vacancies at depths of
practical interest more efficiently than other types of bombarding
species.
The following description and figures are various examples of the
use of the process in forming devices. These are only illustrative
of the wide application of the process. One skilled in the art can
readily adapt the process to enhance various diffusion
processes.
FIG. 5 shows the formation of an inset P-N junction in a substrate.
The N type substrate, FIG. 5, is provided with a layer containing
atoms of the species which is to be diffused into the substrate,
for example, a layer of P type material such as boron. The
substrate is then heated to a temperature in which the interstitial
lattice atoms and lattice vacancies move freely and it is then
bombarded with high energy particles, such as protons, over the
selected area 14 as, for example, by controlling the proton beam to
only impinge upon the selected area, by masking as will be
presently described or other suitable means. The bombardment causes
the apparent temperature in the selected area or region 14 whereby
atoms from the P type layer diffuse into the substrate to a depth
corresponding generally to the depth of proton or particle
penetration. Thereafter, the substrate may be treated by etching
(not shown) to remove the layer and leave a planar P-N junction in
the device.
FIG. 6 illustrates the above process and shows the use of a mask
for defining the area which is bombarded. Thus, in FIG. 6A, there
is shown a substrate with a layer containing the desired species of
atoms which are to be diffused. In FIG. 6B, there is shown a mask
applied over the N type layer with an opening 15. The mask may be
relatively thick oxide, metal or the like which prevents
penetration of the beam particles into the substrate in the area
underlying the mask. Thereafter, the substrate is heated and the
complete surface is bombarded to provide the N type diffusion shown
in FIG. 6C.
FIG. 7 illustrates generally the use of the process in the
formation of an N-P-N junction. Thus, in FIG. 7A, there is shown a
properly treated substrate containing a P type layer. The substrate
is then heated and bombarded over a selected area to form an inset
P type region 16. Thereafter, there is provided a layer containing
impurity atoms of opposite conductivity type, for example,
phosphorus atoms, FIG. 7C. The wafer is then again heated and
bombarded over a selected smaller region or area to form another
inset region 17. The wafer can then be treated as, for example, by
etching to remove the surface layers and leave a device of the type
shown in FIG. 7E.
FIG. 8A shows an N type substrate provided with a layer containing
two atom species having different diffusion constants. Thereafter,
the substrate is heated and a selected area is bombarded with high
energy particles and the two atom species diffuse into the N type
substrate at different rates to form N and P inset regions in the
substrate thereby forming an N-P-N device.
FIGS. 9A - 9E illustrate the process in connection with a
semiconductor device having an oxide protected junction. FIG. 9A
shows an N type substrate. Thereafter, the substrate is provided
with an oxide layer 21, FIG. 9B. The oxide layer is etched to form
a window or opening 22, FIG. 9C, and thereafter, there is deposited
a P type layer which may, for example, be boron and which overlies
the oxide 21 and is in contact with the substrate at the window 22.
The wafer or substrate is then heated and bombarded to provide
diffusion into the substrate to form an inset P type region 23. The
wafer may then be suitably etched and diffused to form a P-N-P
device having oxide protected junctions.
FIG. 10 illustrates another embodiment of the invention. In certain
applications, for example, in the fabrication of ohmic contacts and
P-N junctions on material such as Group III-V and Group II-VI
compounds of the lattice species may have such high vapor pressure
that the lattice species escape from the surface during processing
so the surface must be protected. In the example shown in FIG. 10,
the substrate 24 has applied thereto a layer containing the desired
impurity atoms 25. Thereafter, a layer 26 which may be a relatively
thick protective oxide layer or the like is deposited over the
impurity dopant layer 25 to prevent escape of lattice species. The
device is then heated and bombarded by suitable high energy
particles such as proton particles to cause diffusion of the layer
25 in the region 25a into the underlying wafer. Thus, the proton
beam completely penetrates the protective layer, elevates the
temperature of the desired area whereby diffusion of the impurity
in layer 25 is enhanced into the material, while at the same time
the protective layer prevents the escape of lattice species due to
high vapor pressures.
It is, of course, apparent that the method of the present invention
can also be applied to the formation of field effect transistors
and the like. An example of the application of the process in the
formation of field effect transistors is shown in FIGS. 11A -
11F.
A P layer 26 is first formed on a lightly doped N substrate 27 as
described in FIG. 6. An oxide or other protective mask 28 is then
placed over selected areas of the surface as shown in FIG. 11B, and
a layer 29 containing P type dopant atoms is deposited. The
material is then heated and bombarded to diffuse the P type dopant
into the previously diffused P layer, producing heavily doped P+
source 30 and drain 31 contacts. The surface oxide and residual
dopant are then etched away and a second oxide layer 32 is placed
over the surface in the position shown in FIG. 11E. A layer 33
containing N type dopant atoms is then deposited and the material
is heated and bombarded to produce a heavily doped N+ gate contact
34, yielding the junction field effect transistor shown in FIG.
11F. Alternately, a depletion mode metal-oxide-semiconductor (MOS)
field effect transistor can be fabricated by depositing an oxide
layer over the structure shown in FIG. 11D, leaving windows over
the P+ regions to make ohmic contact to the source and drain
regions, and then, using well known masking and evaporation
techniques, place an appropriate metallic gate electrode to lie
parallel to the source and drain contacts overlying the oxide layer
in the region between said source and drain contacts.
From the foregoing description and explanation, it will be clear to
those versed in the art that both N and P type dopants can be
diffused into a semiconductor substrate of either N or P type
conductivity. The process of the present invention can now be
equally used for making both P-N junctions, diffused resistors and
ohmic contacts in a wide variety of semiconductor materials.
Materials such as copper, gold, platinum, lithium and chromium,
that are commonly introduced into semiconductors for the purpose of
controlling carrier lifetime or for producing high resistivity
material by impurity compensation, can be diffused to precise
depths in selected areas through use of my present enhanced
diffusion process. The process can be repeated several times with
different dopants to form multiple N and P type layers such as are
required in the fabrication of transistors, integrated circuits and
silicon controlled rectifiers and the like. Conventional oxide or
nitride masking may be utilized on the wafer before the dopant is
deposited so that predeposition and diffusion of the impurity can
be limited to those areas where it is desired, or ultimately the
ion or particle bean can be focused into selected areas of slabs so
that the selective diffusion can occur without requiring the
fabrication of masks. Furthermore, the process of the present
invention can be employed to enhance diffusion of atoms into metals
as well as semiconductors.
The process of the present invention can also be used to repair
heavy damage that occurs during an ion implantation of a heavy
atom. Thus, for example, if boron is implanted into silicon at an
energy of 80 keV, and the material is annealed at 625.degree.C.,
either during the implantation of afterward, then only 10 percent
of the boron atoms will have annealed into substitutional positions
in the crystal, where they produce electrical conductivity. If the
silicon is heated to 1,100.degree.C., nearly all of the boron atoms
will anneal into substitutional positions and, therefore, be
electrically active in the crystal.
However, one of the major advantages sought in the ion implantation
process is the possibility of processing semiconductor wafers at
low temperatures. Therefore, annealing the crystal at
1,100.degree.C. defeats one of the major reasons for introducing
dopant atoms by ion implantation.
From the previous description of the present invention, it will be
clear that the present invention can be used together with a low
temperature ion implantation process to achieve an equivalent high
annealing temperature in the layers that contain the implanted
species without raising the substrate to high temperatures. For
example, an 80 keV boron implantation can be performed into a
silicon wafer that is held at a temperature of 700.degree.C. When
sufficient boron ions have been implanted to achieve the desired
conductivity, the boron beam may be switched off and a proton beam
introduced, with the dose and energy of the protons being selected
to provide an equivalent temperature of approximately
1,100.degree.C. in the region where the implanted boron atoms lie.
The proton beam is applied for an adequate time (.about. 30 min.)
to ensure that the boron atoms will have annealed into proper
lattice positions.
Another application of this same type is related to repairing
damage produced at the interface between silicon and
silicon-dioxide during preparation of the oxide. It is known by
persons skilled in the art of silicon planar technology that when a
surface layer of silicon dioxide is formed on a silicon substrate
by any of the conventional techniques, undesirable surface states
remain until the oxide layer has been annealed at an elevated
temperature on the order of 1,050.degree.C. Using the process of
the present invention, the interfacial area between the silicon and
silicon dioxide, which contains the undesirable surface states, can
be annealed without raising the substrate to high temperatures that
create imperfections in the substrate crystal.
Having thus described the preferred embodiments of the invention
and set forth the basic steps of the process, it is not intended
that the description be limited except as may be required by the
appended claims.
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