U.S. patent number 11,131,693 [Application Number 16/717,802] was granted by the patent office on 2021-09-28 for vertical sense devices in vertical trench mosfet.
This patent grant is currently assigned to Vishay-Siliconix, LLC. The grantee listed for this patent is Vishay-Siliconix, LLC.. Invention is credited to M. Ayman Shibib, Wenjie Zhang.
United States Patent |
11,131,693 |
Shibib , et al. |
September 28, 2021 |
Vertical sense devices in vertical trench MOSFET
Abstract
Vertical sense devices in vertical trench MOSFET. In accordance
with an embodiment of the present invention, an electronic circuit
includes a vertical trench metal oxide semiconductor field effect
transistor configured for switching currents of at least one amp
and a current sensing field effect transistor configured to provide
an indication of drain to source current of the MOSFET. A current
sense ratio of the current sensing FET is at least 15 thousand and
may be greater than 29 thousand.
Inventors: |
Shibib; M. Ayman (San Jose,
CA), Zhang; Wenjie (San Jose, CA) |
Applicant: |
Name |
City |
State |
Country |
Type |
Vishay-Siliconix, LLC. |
San Jose |
CA |
US |
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Assignee: |
Vishay-Siliconix, LLC (San
Jose, CA)
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Family
ID: |
55348926 |
Appl.
No.: |
16/717,802 |
Filed: |
December 17, 2019 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20200124645 A1 |
Apr 23, 2020 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
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15634739 |
Jun 27, 2017 |
10527654 |
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14830324 |
Mar 19, 2019 |
10234486 |
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62039335 |
Aug 19, 2014 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G01R
19/15 (20130101); H01L 21/823487 (20130101); H01L
27/0207 (20130101); H01L 29/66734 (20130101); H01L
21/0217 (20130101); H01L 27/0629 (20130101); H01L
29/66666 (20130101); H01L 21/02129 (20130101); H01L
21/32133 (20130101); H01L 21/308 (20130101); H01L
29/41741 (20130101); H01L 29/7813 (20130101); H01L
21/28035 (20130101); G01R 19/0092 (20130101); H01L
21/30604 (20130101); H01L 29/407 (20130101); H01L
29/7815 (20130101); H01L 29/0692 (20130101); H01L
27/0727 (20130101); H01L 29/42372 (20130101); H01L
27/088 (20130101) |
Current International
Class: |
G01R
19/00 (20060101); H01L 27/088 (20060101); H01L
27/06 (20060101); H01L 29/06 (20060101); G01R
19/15 (20060101); H01L 21/8234 (20060101); H01L
29/40 (20060101); H01L 21/02 (20060101); H01L
21/28 (20060101); H01L 21/306 (20060101); H01L
21/308 (20060101); H01L 21/3213 (20060101); H01L
27/02 (20060101); H01L 29/417 (20060101); H01L
29/423 (20060101); H01L 29/66 (20060101); H01L
29/78 (20060101) |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Abdelaziez; Yasser A
Parent Case Text
RELATED APPLICATIONS
This application is a Divisional Application of, and claims
priority to co-pending, commonly owned U.S. patent application Ser.
No. 15/634,739, filed Jun. 27, 2017, entitled "Vertical Sense
Devices in Vertical Trench MOSFET" to Shibib and Zhang, which in
turn was a Divisional Application of, and claimed priority to U.S.
patent application Ser. No. 14/830,324, filed Aug. 19, 2015,
entitled "Vertical Sense Devices in Vertical Trench MOSFET" to
Shibib and Zhang, which in turn claimed priority to U.S.
Provisional Patent Application No. 62/039,335, filed Aug. 19, 2014,
entitled, "High Ratio Current Sense MOSFET structure in a Charge
Balanced Split Gate Trench Technology" to Shibib and Zhang. All
such applications are hereby incorporated herein by reference in
their entireties.
This application is related to co-pending, commonly owned U.S.
patent application Ser. No. 13/460,567, filed Apr. 20, 2012, to
Bobde et al., entitled "Hybrid Split Gate Semiconductor," which is
hereby incorporated herein by reference in its entirety.
Claims
What is claimed is:
1. A semiconductor device comprising: a vertical trench main field
effect transistor (main-FET) configured to control a drain source
current; a plurality of parallel main FET trenches, wherein said
main FET trenches comprise a first electrode coupled to a gate of
said main-FET; a vertical current sense field effect transistor
(sense-FET) configured to produce a voltage corresponding to said
drain source current comprising: a plurality of sense-FET trenches,
wherein each of said sense-FET trenches comprises a portion of one
of said main FET trenches; and at least two isolation trenches
configured to isolate said main-FET from said sense-FET.
2. The semiconductor device of claim 1 wherein each of said
plurality of parallel main FET trenches further comprises a main
gate electrode coupled to said main gate of said main-FET.
3. The semiconductor device of claim 2 wherein said main FET
trenches comprise a first electrode coupled to said gate of said
main-FET and a second electrode electrically isolated from said
main gate electrode.
4. The semiconductor device of claim 1 wherein portions of said
main MOSFET surrounds said current sense FET on at least three
sides.
5. The semiconductor device of claim 4 further comprising a surface
isolation region free of surface metallization between said current
sense-FET and said main MOSFET on said at least three sides.
6. The semiconductor device of claim 5 wherein portions of said
surface isolation region are formed between isolation trenches
crossing said parallel main trenches.
7. The semiconductor device of claim 1 further comprising: at least
two first isolation trenches crossing said parallel main
trenches.
8. The semiconductor device of claim 7 further comprising: a
plurality of second isolation trenches, formed outside of an active
area of said sense-FET, wherein each of said second isolation
trenches comprises a portion of one of said main trenches.
9. A semiconductor device comprising: a vertical trench main FET
configured to control a drain source current; a vertical trench
current sensing FET (sense-FET) configured to produce a voltage
corresponding to said drain source current; and an isolation trench
configured to isolate said main-FET from said sense-FET, wherein
said isolation trench is formed at an angle to, and intersects a
plurality of trenches of said main-FET.
10. The semiconductor device of claim 9 wherein vertical trenches
of said main-FET comprise at least two vertically aligned
electrodes, electrically insulated from one another.
11. The semiconductor device of claim 10 wherein a lower of said
electrodes is coupled to a source of said main-FET.
12. The semiconductor device of claim 10 wherein an upper of said
electrodes is coupled to a gate of said main-FET.
13. The semiconductor device of claim 9 wherein said angle is
substantially 90 degrees.
14. The semiconductor device of claim 9 wherein said sense-FET and
said main-FET comprise common drain terminal but separate source
and gate terminals.
15. A semiconductor device comprising: a split gate vertical trench
main FET, configured to control a drain source current, wherein
said main-FET comprises a main-FET source metal configured to
couple a plurality of main-FET source regions to a main-FET source
terminal; and a vertical trench current sensing FET (sense-FET),
configured to produce a signal corresponding to said drain source
current, wherein said sense-FET is surrounded on at least three
sides by said main-FET source metal.
16. The semiconductor device of claim 15 further comprising a
sense-FET source metal, disposed on the surface of said substrate,
configured to couple at least one sense-FET source region to at
least one sense-FET source terminal.
17. The semiconductor device of claim 16 wherein said sense-FET
source metal is electrically isolated from said main-FET source
metal by a surface isolation region that is devoid of metal at the
level of said main-FET source metal.
18. The semiconductor device of claim 17 comprising an insulator
deposited on the surface of said substrate in said surface
isolation region.
19. The semiconductor device of claim 15 comprising at least two
vertical trench current sensing FETs physically separated from one
another.
20. The semiconductor device of claim 15 wherein said sense-FET and
said main-FET comprise common gate and drain terminals.
Description
FIELD OF INVENTION
Embodiments of the present invention relate to the field of
integrated circuit design and manufacture. More specifically,
embodiments of the present invention relate to systems and methods
for vertical sense devices in vertical trench MOSFETs.
BACKGROUND
Measuring current in a power supply is an important consideration
in the design and implementation of modern power supplies. A
current sense function may be used for fault detection and/or
protection, for current-mode controlled voltage regulation, and for
current control, among other uses. Over the years, a variety of
systems have been used to measure current in a power supply,
including, for example, discrete resistors, use of a resistance
inherent to traces of printed circuit boards, use of resistance
inherent to an integrated circuit lead frame, use of inductors,
magnetic sensing devices including coils, transformers and Hall
effect sensors, and use of a drain-source resistance of a power
metal oxide semiconductor field effect transistor (MOSFET).
One of the leading systems to measure current in a power supply
uses a dedicated field effect transistor (FET) known as or referred
to as a "sense-FET." Generally, a sense-FET is small a FET,
separate from the main power FET, referred to herein as the
"main-FET." Generally, a sense-FET is configured to produce a
voltage corresponding to the current in the main-FET. The "current
sense ratio" (CSR) is a figure of merit of the implementation of
the sense-FET. The current sense ratio is a ratio of current in the
main-FET to current in the sense-FET, e.g., Imain/Isense. A higher
current sense ratio is generally desirable, so that the range of
current sensing is extended over many decades of current in the
main-FET. However, increasing CSR has been a challenge due to, for
example, complex interactions between sense-FET structures and
main-FET structures.
Conventional approaches to design and implementation of sense-FETs
have not been found to be applicable to Split Gate Charge Balanced
(SGCB) trench MOSFETs. A split gate device includes multiple layers
of polysilicon in the trenches with different electrical voltages,
and it has a special structure and layout to establish the proper
charge balance. For example, the trenches are spaced a certain
distance apart to establish a charge balance, and furthermore, any
active body junction in the device must be properly surrounded by
polysilicon shields that establish the charge balance.
SUMMARY OF THE INVENTION
Therefore, what is needed are systems and methods for vertical
sense devices in vertical trench metal oxide semiconductor field
effect transistors (MOSFETs). An additional need exists for systems
and methods for vertical sense devices in vertical trench MOSFETs
that are integral to the main-FET. What is further needed are
systems and methods for current sense MOSFETs in vertical trench
MOSFETs including an isolation region between the sense-FET and the
main-FET that preserves charge balance in the main-FET. A yet
further need exists for a sensing diode to sense temperature and/or
gate voltage of the main-FET. A still further need exists for
systems and methods for vertical sense devices in vertical trench
MOSFETs that are compatible and complementary with existing systems
and methods of integrated circuit design, manufacturing and test.
Embodiments of the present invention provide these advantages.
In accordance with an embodiment of the present invention, an
electronic circuit includes a vertical trench metal oxide
semiconductor field effect transistor configured for controlling
currents of at least one amp and a current sensing field effect
transistor configured to provide an indication of drain to source
current of the MOSFET. In some embodiments, a current sense ratio
of the current sensing FET is at least 15 thousand and may be
greater than 29 thousand.
In accordance with another embodiment of the present invention, a
power semiconductor device includes a main vertical trench metal
oxide semiconductor field effect transistor (main-MOSFET). The
main-MOSFET includes a plurality of parallel main trenches, wherein
the main trenches include a first electrode coupled to a gate of
the main-MOSFET and a plurality of main mesas between the main
trenches, wherein the main mesas include a main source and a main
body of the main-MOSFET. The power semiconductor device also
includes a current sense field effect transistor (sense-FET). The
sense-FET includes a plurality of sense-FET trenches, wherein each
of the sense-FET trenches includes a portion of one of the main
trenches and a plurality of source-FET mesas between the source-FET
trenches, wherein the source-FET mesas include a sense-FET source
that is electrically isolated from the main source of the
main-MOSFET.
In accordance with a further embodiment of the present invention, a
semiconductor device includes a main-FET including a main-FET
source region and a current sensing FET (sense-FET) configured to
produce a voltage corresponding to a drain source current of a the
main-FET. A gate and a drain of the sense-FET are coupled to a gate
and a drain of the main-FET. The sense-FET includes a plurality of
first trenches formed in a first horizontal dimension configured to
isolate a sense-FET source region from the main-FET source region.
Each of the trenches includes multiple alternating layers of
conductors and dielectrics in a vertical dimension. The
semiconductor device further includes at least one second trench in
a perpendicular horizontal dimension located between the sense-FET
source region and the main-FET source region and configured to
isolate the sense-FET source region from the main-FET source
region, and a buffer region separating sense-FET source region and
the main-FET source region.
In accordance with still another embodiment of the present
invention, a power semiconductor device includes a vertical trench
main MOSFET (main-FET) configured to control a drain source
current, a vertical trench current sensing FET (sense-FET)
configured to produce a voltage corresponding to the drain source
current, and an isolation trench configured to isolate the main-FET
from the sense-FET. The isolation trench is formed at an angle to,
and intersects a plurality of trenches of the main-FET.
In a still further embodiment in accordance with the present
invention, a power semiconductor device includes a substrate and a
split gate vertical trench main MOSFET (main-FET), formed in the
substrate, configured to control a drain source current. The
main-FET includes a main-FET source metal, disposed on the surface
of the substrate, configured to couple a plurality of main-FET
source regions to one another and to a plurality of main-FET source
terminals. The power semiconductor device also includes a vertical
trench current sensing FET (sense-FET), formed in the substrate,
configured to produce a voltage corresponding to the drain source
current. The sense-FET is surrounded on at least three sides by the
main-FET source metal. The substrate may include epitaxially grown
material.
In a still further yet embodiment in accordance with the present
invention, a power semiconductor device includes a substrate and a
split gate vertical trench main MOSFET (main-FET), formed in the
substrate, configured to control a drain source current. The power
semiconductor device also includes a vertical trench current
sensing FET (sense-FET), formed in the substrate, configured to
produce a voltage corresponding to the drain source current. The
sense-FET and the main-FET include common gate and drain terminals.
The sense-FET may include portions of trenches forming the
main-FET. The substrate may include epitaxially grown material.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and form a
part of this specification, illustrate embodiments of the invention
and, together with the description, serve to explain the principles
of the invention. Unless otherwise noted, the drawings are not
drawn to scale.
FIG. 1A illustrates a plan view of an exemplary current sense
MOSFET in a power semiconductor device, in accordance with
embodiments of the present invention.
FIG. 1B illustrates an exemplary schematic symbol for a power
semiconductor device, in accordance with embodiments of the present
invention.
FIG. 2 illustrates an exemplary enlarged plan view of a portion of
power semiconductor device, in accordance with embodiments of the
present invention.
FIG. 3 illustrates an exemplary cross-sectional view of a portion
of power semiconductor device, in accordance with embodiments of
the present invention.
FIG. 4 illustrates an exemplary cross-sectional view of a portion
of power semiconductor device, in accordance with embodiments of
the present invention.
FIG. 5 illustrates a graph of experimental measurements taken on
prototype devices constructed in accordance with embodiments of the
present invention.
FIG. 6 illustrates an exemplary process flow for constructing a
current sense MOSFET in a vertical trench MOSFET, in accordance
with embodiments of the present invention.
FIG. 7A illustrates a plan view of an exemplary sense diode in a
power semiconductor device, in accordance with embodiments of the
present invention.
FIG. 7B illustrates an exemplary schematic symbol for power
semiconductor device, in accordance with embodiments of the present
invention.
FIG. 8 illustrates an exemplary cross-sectional view of a portion
of power semiconductor device, in accordance with embodiments of
the present invention.
FIG. 9 illustrates exemplary characteristics of an exemplary
sense-diode as a function of gate voltage, in accordance with
embodiments of the present invention.
FIG. 10A illustrates a plan view of an exemplary current sense
MOSFET (sense-FET) and an exemplary sense diode in a power
semiconductor device, in accordance with embodiments of the present
invention.
FIG. 10B illustrates an exemplary schematic symbol for power
semiconductor device, in accordance with embodiments of the present
invention.
DETAILED DESCRIPTION
Reference will now be made in detail to various embodiments of the
invention, examples of which are illustrated in the accompanying
drawings. While the invention will be described in conjunction with
these embodiments, it is understood that they are not intended to
limit the invention to these embodiments. On the contrary, the
invention is intended to cover alternatives, modifications and
equivalents, which may be included within the spirit and scope of
the invention as defined by the appended claims. Furthermore, in
the following detailed description of the invention, numerous
specific details are set forth in order to provide a thorough
understanding of the invention. However, it will be recognized by
one of ordinary skill in the art that the invention may be
practiced without these specific details. In other instances, well
known methods, procedures, components, and circuits have not been
described in detail as not to unnecessarily obscure aspects of the
invention.
NOTATION AND NOMENCLATURE
The figures are not drawn to scale, and only portions of the
structures, as well as the various layers that form those
structures, may be shown in the figures. Furthermore, fabrication
processes and operations may be performed along with the processes
and operations discussed herein; that is, there may be a number of
process operations before, in between and/or after the operations
shown and described herein. Importantly, embodiments in accordance
with the present invention can be implemented in conjunction with
these other (perhaps conventional) processes and operations without
significantly perturbing them. Generally speaking, embodiments in
accordance with the present invention may replace and/or supplement
portions of a conventional process without significantly affecting
peripheral processes and operations.
The term "MOSFET" is generally understood to be synonymous with the
term insulated-gate field-effect transistor (IGFET), as many modern
MOSFETs comprise a non-metal gate and/or a non-oxide gate
insulator. As used herein, the term "MOSFET" does not necessarily
imply or require FETs that include metal gates and/or oxide gate
insulators. Rather, the term "MOSFET" includes devices commonly
known as or referred to as MOSFETs.
As used herein, the letter "n" refers to an n-type dopant and the
letter "p" refers to a p-type dopant. A plus sign "+" or a minus
sign "-" is used to represent, respectively, a relatively high or
relatively low concentration of such dopant(s).
The term "channel" is used herein in the accepted manner. That is,
current moves within a FET in a channel, from the source connection
to the drain connection. A channel can be made of either n-type or
p-type semiconductor material; accordingly, a FET is specified as
either an n-channel or p-channel device. Some of the figures are
discussed in the context of an n-channel device, more specifically
an n-channel vertical MOSFET; however, embodiments according to the
present invention are not so limited. That is, the features
described herein may be utilized in a p-channel device. The
discussion of an n-channel device can be readily mapped to a
p-channel device by substituting p-type dopant and materials for
corresponding n-type dopant and materials, and vice versa.
The term "trench" has acquired two different, but related meanings
within the semiconductor arts. Generally, when referring to a
process, e.g., etching, the term trench is used to mean or refer to
a void of material, e.g., a hole or ditch. Generally, the length of
such a hole is much greater than its width or depth. However, when
referring to a semiconductor structure or device, the term trench
is used to mean or refer to a solid vertically-aligned structure,
disposed beneath a primary surface of a substrate, having a complex
composition, different from that of the substrate, and usually
adjacent to a channel of a field effect transistor (FET). The
structure comprises, for example, a gate of the FET. Accordingly, a
trench semiconductor device generally comprises a mesa structure,
which is not a trench, and portions, e.g., one half, of two
adjacent structural "trenches."
It is to be appreciated that although the semiconductor structure
commonly referred to as a "trench" may be formed by etching a
trench and then filling the trench, the use of the structural term
herein in regards to embodiments of the present invention does not
imply, and is not limited to such processes.
Vertical Sense Devices in Vertical Trench MOSFET
A charge balanced split gate vertical trench metal oxide
semiconductor field effect transistor (MOSFET) generally comprises
trenches that extend into one or more epitaxial layers that are
grown on top of a heavily doped substrate. The trenches are etched
deep enough, typically a few micrometers, to be able to contain
several layers of oxide and polysilicon. The lower layer of the
polysilicon ("poly 1"), which is closest to the trench bottom, is
usually tied to the source electrical potential and is an essential
part of establishing the charge balance condition that results in a
desirable low "on" resistance for a given breakdown voltage. The
upper layer of the polysilicon ("poly 2") is usually used as the
gate of the device. Both layers are well inside the trench and
separated from the epitaxial regions by different thicknesses of
dielectric layers, for example, silicon dioxide.
In accordance with embodiments of the present invention, a
relatively small sense-FET is established proximate the top body of
a relatively larger split gate MOSFET, known as the "main-FET." A
sense-FET should be able to deliver a current in the sense-FET that
is a small fraction of the current passing through the main-FET.
For example, the sense-FET should be characterized as having a
large current sense ratio (CSR).
In general, a current sense ratio (CSR) may be a property of both
device geometry and temperature. For example, temperature
differences between a sense-FET and portions of a main-FET may
deleteriously change a CSR during operation.
In accordance with embodiments of the present invention, a
sense-FET may be positioned in an area of a main-FET where a
sense-FET can sense a high temperature of the die. The sense-FET
may be surrounded on at least three sides by portions of the
main-FET. In accordance with embodiments of the present invention,
multiple sense-FETs, e.g., sharing a common sense-FET source, may
be positioned in a plurality of locations throughout a main-FET.
Such multiple locations may improve current sensing corresponding
to thermal distribution across a large die, for example.
FIG. 1A illustrates a plan view of an exemplary current sense
MOSFET (sense-FET) 160 in a power semiconductor device 100, in
accordance with embodiments of the present invention. A principal
function of power semiconductor device 100 is to function as a
power MOSFET, e.g., to control a drain source current through the
power MOSFET. Power semiconductor device 100 comprises large areas
of main-FET 150. For example, main-FET 150 comprises numerous
trenches comprising gate and shield electrodes, and mesas
in-between the trenches comprising source and body regions. The
main-FET 150 comprises a gate coupled to a gate terminal 140, for
example, a bond pad. The main-FET 150 comprises a source coupled to
a main-FET source terminal 130. The drain of the main-FET 150 is
outside, e.g., below, the plane of FIG. 1A.
Power semiconductor device 100 comprises a sense-FET 160, formed
within a region of the main-FET 150, in accordance with embodiments
of the present invention. It is appreciated that die area of
main-FET 150 is very much greater than die area of sense-FET 160.
The gate and drain of the sense-FET 160 are in common, e.g., in
parallel, with the gate and drain of the main-FET 150. The source
of the sense-FET 160 is coupled to a sense source terminal 110,
e.g., a bond pad. The sense-FET outputs a voltage corresponding to
current in the main-FET 150. The node Kelvin may be coupled to a
terminal 120 for use off the die of power semiconductor device 100,
in some embodiments. The voltage Kelvin may also, or alternatively,
be used by circuitry (not shown) on the die of power semiconductor
device 100, for example, to turn main-FET 150 off for over-current
protection.
FIG. 1B illustrates an exemplary schematic symbol for power
semiconductor device 100, in accordance with embodiments of the
present invention.
FIG. 2 illustrates an exemplary enlarged plan view of a portion of
power semiconductor device 100 around and including sense-FET 160,
in accordance with embodiments of the present invention. Power
semiconductor device 100 comprises a plurality of primary trenches
210, illustrated horizontally in FIG. 2. The majority of primary
trenches 210 are utilized by the main-FET 150.
Power semiconductor device 100 comprises four isolation trenches
221, 222, 223 and 224, in accordance with embodiments of the
present invention. The isolation trenches 221-224 are part of a
group of isolation structures to isolate sense-FET 160 from the
main-FET 150. The isolation trenches 221-224 are perpendicular to
the primary trenches 210, in accordance with embodiments of the
present invention. Sense-FET 160 comprises a sense-FET source 230.
Sense-FET source 230 is bounded by two isolation trenches,
isolation trenches 222 and 223, and portions of two primary
trenches 210, primary trenches 210A and 210B. Overlying and
coupling sense-FET source 230 is sense-FET source metal 240.
Sense-FET source metal 240 overlaps the isolation trenches 222 and
224. Sense-FET source metal 240 may extend off the top of the FIG.
2 for coupling to sense source terminal 110 (FIG. 1A), for example,
in some embodiments. In accordance with other embodiments of the
present invention, the source of main-FET 150 may be coupled in a
different manner, e.g., out of the plane of FIG. 2. In such a case,
the surface isolation region 250 would form a square annulus around
the sense-FET 160 (FIG. 1), in accordance with embodiments of the
present invention.
A surface isolation region 250 is formed outside of sense-FET 160,
in accordance with embodiments of the present invention. In the
exemplary embodiment of FIG. 2, surface isolation region 250 is
generally "U" shaped. Surface isolation region 250 is formed
between isolation trenches 221 and 222, between isolation trenches
223 and 224, and between primary trenches 210B and 210C. In
general, portions of multiple primary trenches 220 should be used
to isolate a sense-FET 160 from a main-FET 150, in order to
maintain charge balance. P-type materials in the mesas of surface
isolation region 250 are left floating. The surface of surface
isolation region 250 may be covered with an insulator, for example,
borophosphosilicate glass (BPSG).
Outside of surface isolation region 250, e.g., to the left, right
and below surface isolation region 250 in the view of FIG. 2, are
regions of main-FET 150. For example, p-type material in mesas
between primary trenches 210 is coupled to the main-FET source
terminal 130 (FIG. 1), and such regions are overlaid with main-FET
source metal (not shown).
FIG. 3 illustrates an exemplary cross-sectional view of a portion
of power semiconductor device 100, in accordance with embodiments
of the present invention. FIG. 3 corresponds to cross section AA of
FIG. 2. The view of FIG. 3 is taken along a mesa, e.g., between
primary trenches 210 (FIG. 2), cutting an active region of
sense-FET 160 (FIG. 1A). Power semiconductor device 100 comprises
an epitaxial layer 310, e.g., N.sup.-, formed on an N.sup.+
substrate (not shown). A metallic drain contact (not shown) is
typically formed on the bottom the substrate. Isolation trenches
221, 222, 223 and 224 are formed in epitaxial layer 310. As
illustrated, isolation trenches 221, 222, 223 and 224 are
perpendicular to the primary trenches 210. However, a wide variety
of angles between isolation trenches 221-224 and primary trenches
210, e.g., from about 40 degrees to 90 degrees, are well suited to
embodiments in accordance with the present invention.
Primary trenches 210 are above and below the plane of FIG. 3. The
isolation trenches 221-224 should be deeper than the drain-body PN
junction, and may be about the same depth as the primary trenches
210. Such a depth establishes a physical barrier between the source
of the sense-FET 160 and the source of the main-FET 150. Thus, in
accordance with embodiments of the present invention, the body
implant may be performed without a mask, hence making the
manufacturing process more cost effective.
Within each trench 221-224 there are two polysilicon electrodes,
poly 1 (350) and poly 2 (340), separated by oxide, e.g., silicon
dioxide. The top electrode, poly 2 (340), is coupled to the gate
terminal, and the bottom electrode, poly 1 (35), is coupled to the
source terminal. Power semiconductor device 100 additionally
comprises a body implant 330, e.g., P.sup.+ doping, typically at a
depth below the surface of epitaxial layer 310. The implant region
360 between isolation trenches 221 and 222, and between isolation
trenches 223 and 224 is left floating to create a buffer region
between the body region 370 of the sense-FET and the electrically
separate body region of the main-FET 380, thus improving the
electrical isolation of the two FETs with minimal distance
separating the two body regions 370 and 380.
The region between isolation trenches 221 and 222, and between
isolation trenches 223 and 224 is a part of surface isolation
region 250 (FIG. 2). Surface isolation region 250 is covered with
an insulator, for example, borophosphosilicate glass (BPSG) 320.
There is generally a layer 312 of low temperature oxide (LTO)
underneath BPSG 320. The BPSG 320 isolates both sense-FET source
metal 240 and main-FET source metal from one another and from the
floating body implant 360.
Sense-FET source metal 240 couples the sources of the sense-FET 160
(not shown) and the sense-FET body 370 to a sense-FET source
terminal of power semiconductor device 100, e.g., sense-FET source
terminal 110 (FIG. 1A).
FIG. 4 illustrates an exemplary cross-sectional view of a portion
of power semiconductor device 100, in accordance with embodiments
of the present invention. FIG. 4 corresponds to cross section BB of
FIG. 2. The view of FIG. 4 is taken through an active region of
sense-FET 160 (FIG. 1A), perpendicular to primary trenches 210.
Portions of several primary trenches 210, e.g., under surface
isolation region 250 and BPSG 320, are utilized as isolation
trenches 440. The top electrode, poly 2 (340), is coupled to the
gate electrode, and the bottom electrode, poly 1 (350), is coupled
to the source of the main-FET. Portions of different primary
trenches 210 are used as trenches 430 to form sense-FET 160. It is
to be appreciated FIG. 4 illustrates only two trenches as part of a
sense-FET 160 for clarity. There would typically be many more
trenches 430 within a sense-FET 160.
Sense-FET 160 comprises a sense-FET source 410, which is typically
an N.sup.+ implant at or near the top of epitaxial layer 310.
Sense-FET 160 also comprises a sense-FET source-body contact 420.
Also illustrated in FIG. 4 is a sense-FET source metal extension
450, for example, used to route sense-FET source metal extension to
a sense-FET source contact, e.g., sense-FET source terminal 110 of
FIG. 1A.
FIG. 5 illustrates a graph 500 of experimental measurements taken
on prototype devices constructed in accordance with embodiments of
the present invention. Graph 500 illustrates a current sense ratio
(CSR), e.g., a ratio of Imain/Isense, on the left abscissa, across
a range of drain-source currents, Ids, of the main-FET, also known
as Imain, from 2 amps to 50 amps (ordinate). The ratio is at least
2.99.times.10.sup.4, e.g., at 2 amps, and may be as high as
3.1.times.10.sup.4, e.g., at 50 amps. In contrast, the highest
claimed CSR under the conventional art known to applicants at this
time is approximately 1.2.times.10.sup.3.
Graph 500 of FIG. 5 also illustrates a percentage mismatch across
the full main current range on the right abscissa. The mismatch
describes the accuracy of the ratio of Imain/Isense. The mismatch
is very small, e.g., within a range of +/-0.33 percent across a
range of Ids from 2 amps to 50 amps. Thus, the prototype very
accurately indicates Ids of the main-FET.
In accordance with embodiments of the present invention, a current
sense MOSFET in a vertical trench MOSFET may be formed without
additional process steps or additional mask layers in comparison to
process steps and mask layers required to produce a corresponding
vertical trench MOSFET by itself. For example, the perpendicular
isolation trenches, e.g., isolation trenches 221-224 of FIG. 2, may
be formed utilizing the same process steps and masks that form the
primary trenches 210 of FIG. 2. It is appreciated that several
masks, including, for example, a trench mask and metallization
masks, will be different between embodiments in accordance with the
present invention and the conventional art. For example, a single
mask for forming FET trenches, e.g., primary trenches 210 (FIG. 2)
and perpendicular isolation trenches, e.g., isolation trenches
221-224 (FIG. 2), is novel and unique, in accordance with
embodiments of the present invention. However, the processes and
numbers of masks may be the same.
FIG. 6 illustrates an exemplary process flow 600 for constructing a
current sense MOSFET in a vertical trench MOSFET, for example,
power semiconductor device 100 of FIG. 1A, in accordance with
embodiments of the present invention. In 605, a plurality of
trenches are etched with a hard mask to a depth, e.g., of typically
a few micrometers. The trenches include, for example, primary
trenches, e.g., primary trenches 210 (FIG. 2) and isolation
trenches, e.g., isolation trenches 221-224, formed at an angle to
the primary trenches. The primary trenches and isolation trenches
may be etched to about the same depth, but that is not
required.
In another embodiment, the vertical trenches are made slightly
wider than primary trenches 210 such that when both trenches are
etched (at the same process step) the vertical trenches are
somewhat deeper than the primary trenches.
In 610, thermal oxide is grown followed by a deposited oxide inside
the trench. In 615, first polysilicon, e.g., poly 1 (350) of FIG.
3, is deposited inside the trench. The first polysilicon may be
doped with a high concentration of Phosphorus. In 620, the first
polysilicon is recessed back to a desired depth, typically on the
order of 1 micrometer. In 625, a second oxide layer is grown or
deposited over and above the first polysilicon. In 630, a selective
oxide etch is performed to etch the active region where the gate
oxide is grown.
In 635, second polysilicon, e.g., poly 2 (340) of FIG. 3, is
deposited. In 640, the second polysilicon is recessed in the active
area to allow a layer of deposited oxide the fill the top of the
trenches by a fill and etch back process. The body and source
implants should be introduced consecutively. In 645, a layer of
silicon nitride and doped oxide is used to cover the surface before
contacts are etched to silicon, first polysilicon and second
polysilicon.
In 650 a layer of metal is deposited and etched forming the gate
and source contacts. It is appreciated that the source metal
patterns of embodiments in accordance with the present invention
differ from a conventional vertical MOSFET, for example, to
accommodate the separate sense source of the novel sense-FET. In
addition, there is no source metal in an isolation region around
the sense-FET.
In 655 a passivation layer of oxide and nitride are deposited over
the metallization and etched. In 660 a metal layer is deposited
forming the backside drain contact.
In accordance with embodiments of the present invention, a sense
diode may be established proximate the top body of a relatively
larger split gate MOSFET, known as the "main-FET." Such a sense
diode may be used to indicate temperature of the main-FET, in some
embodiments. Temperature of a main-FET may be used for numerous
purposes, e.g., to shut down a device responsive to an
over-temperature condition. A sense diode may also be used to
measure gate voltage of the main-FET, in some embodiments.
Measuring gate voltage of a main-FET may be desirable when the gate
terminal of a main-FET is not exposed, e.g., in packaged, high
function devices such as driver MOS ("DrMOS") devices.
FIG. 7A illustrates a plan view of an exemplary sense diode 720 in
a power semiconductor device 700, in accordance with embodiments of
the present invention. A principal function of power semiconductor
device 700 is to function as a power MOSFET, e.g., to control a
drain source current through the power MOSFET. Power semiconductor
device 700 comprises large areas of main-FET 750. For example,
main-FET 150 comprises numerous trenches comprising gate and shield
electrodes, and mesas in-between the trenches comprising source and
body regions. The main-FET 750 comprises a gate coupled to a gate
terminal 740, for example, a bond pad. The main-FET 750 comprises a
source coupled to a main-FET source terminal 730. The drain of the
MOSFET 750 is outside, e.g., below, the plane of FIG. 7A. The
function and structure of main-FET 750, main source 730 and gate
740 are generally equivalent to the comparable structures of device
100, as illustrated in FIG. 1A.
Power semiconductor device 100 comprises a sense-diode 720, formed
within a region of the main-FET 750, in accordance with embodiments
of the present invention. It is appreciated that die area of
main-FET 750 is very much greater than die area of sense-diode 720.
The cathode terminal of sense-diode 720 is in common with the drain
terminal of main-FET 750, outside the plane of FIG. 7A. The anode
terminal of sense-diode 720 is coupled to anode terminal 710, e.g.,
a bond pad.
FIG. 7B illustrates an exemplary schematic symbol for power
semiconductor device 700, in accordance with embodiments of the
present invention.
It is to be appreciated that sense-diode 720 is structurally very
similar to sense-FET 160 of FIGS. 1A, 2, 3 and 4. The isolation
trenches that isolate sense-diode 720 are equivalent to the
isolation trenches that isolate sense-FET 160. The salient
differences between sense-FET 160 and sense-diode 720 are that
sense-diode 720 may lack a source implant 410 and a source-body
contact 420 (FIG. 4), and the two poly layers within the trenches
are connected differently.
FIG. 8 illustrates an exemplary cross-sectional view of a portion
of power semiconductor device 700, in accordance with embodiments
of the present invention. FIG. 8 is generally equivalent to the
cross section illustration of FIG. 4. The view of FIG. 8 is taken
through an active region of sense-diode 720 (FIG. 7A),
perpendicular to primary trenches of main-FET 750. Portions of
several primary trenches, e.g., under surface isolation regions and
BPSG 825, are utilized as isolation trenches 840. The top
electrode, poly 2 (842), is coupled to the gate electrode, and the
bottom electrode, poly 1 (841), is coupled to the source of the
main-FET. Portions of different primary trenches are used as
trenches 830 to form sense-diode 820. It is to be appreciated FIG.
8 illustrates only two trenches as part of a sense-diode 720 for
clarity. There would typically be many more trenches 830 within a
sense-diode 720.
Sense diode 720 comprises a sense-diode anode 870. Optionally,
sense diode 720 may comprise a sense-diode anode contact 851,
similar to a source-body contact of a MOSFET, e.g., sense-FET
source-body contact 420 of FIG. 4. Also illustrated in FIG. 8 is a
sense-FET source metal extension 850, for example, used to route
sense-FET source metal extension to a sense-FET source contact,
e.g., sense-FET anode contact 710 of FIG. 7A.
In accordance with embodiments of the present invention,
sense-diode 720 may be used to sense temperature of the device,
e.g., a temperature of main-FET 750 and/or to indicate the voltage
of gate 740.
To measure temperature, in accordance with embodiments of the
present invention, the first field plate, poly 1 (841), should be
electrically coupled to the anode of the sense-diode 720, which has
a separate terminal distinct from the source of the main-FET 750
(or a sense-FET, if present). The second field plate, poly 2 (842),
uses the gate structure and should be electrically coupled to the
anode (not to the gate terminal 740 of the main-FET 750). The
cathode side of the diode is common to the drain of the main-FET
750 (and a sense-FET, if present). In this embodiment, the diode is
not affected by the main-FET 750 gate voltage and exhibits good
diode characteristics that can be calibrated as a function of
temperature for temperature sensing. Accordingly, this novel
structure of a vertical MOS diode within a vertical trench MOSFET
may be used to sense temperature of the device via well known
methods.
To indicate gate voltage, in accordance with embodiments of the
present invention, the second field plate, poly 2 (842), should be
electrically coupled to the gate terminal of the main-FET 750. In
this embodiment, the sense-diode 720 characteristics change as a
function of the gate voltage. For example, the sense-diode 720
current-voltage relation depends on gate terminal voltage if the
second field plate, poly 2 (842), is electrically coupled to the
gate terminal. In this embodiment, the sense-diode 720
current-voltage characteristic may be used to indicate the gate
voltage, at a given temperature, by calibrating the sense-diode 720
voltage at a given current to the gate voltage. This can be useful
if there is no gate terminal exposed to the outside, for example,
as is the case of a Driver-MOS ("DrMOS") package. FIG. 9, below,
illustrates exemplary characteristics of the sense-diode 720 as a
function of the gate voltage, to facilitate determining gate
voltage.
FIG. 9 illustrates exemplary characteristics 900 of an exemplary
sense-diode 720 as a function of gate voltage, in accordance with
embodiments of the present invention. Characteristics 900 may be
used to determine gate voltage based on diode current and anode
voltage. The modulation of the current--voltage characteristics of
the sense-diode 720 is seen here depending on the gate voltage, as
applied to the second field plate, poly 2 (842) as illustrated in
FIG. 8. When Vgs=0 volts, the channel is off, and the sense-diode
720 is working in a "pure diode mode." As Vgs increases, the
sense-diode 720 is modulated by the parasitic MOSFET. For example,
when Vgs=5 volts, the channel is on and channel current dominates
the characteristics. The sense-diode 720 in this mode of operation
can basically "detect the gate voltage" by calibrating the current
flowing through the diode, for example, at 1 .mu.a of drain-source
current, to the following Table 1:
TABLE-US-00001 TABLE 1 Vdiode @ 1 .mu.a = 0.62 V => Vgs = 0 V
Vdiode @ 1 .mu.a = 0.51 V => Vgs = 2.5 V Vdiode @ 1 .mu.a = 0.39
V => Vgs = 5 V Vdiode @ 1 .mu.a = 0.24 V => Vgs = 10 V
It is to be appreciated that embodiments in accordance with the
present invention are well suited to the formation and use of both
a sense-FET, e.g., sense-FET 160 of FIG. 1A, and a sense-diode,
e.g., sense-diode 720 of FIG. 7A.
FIG. 10A illustrates a plan view of an exemplary current sense
MOSFET (sense-FET) 160 and an exemplary sense diode 720 in a power
semiconductor device 1000, in accordance with embodiments of the
present invention. A principal function of power semiconductor
device 1000 is to function as a power MOSFET, e.g., to control a
drain source current through the power MOSFET. Power semiconductor
device 1000 comprises large areas of main-FET 1050. For example,
main-FET 1050 comprises numerous trenches comprising gate and
shield electrodes, and mesas in-between the trenches comprising
source and body regions. The main-FET 1050 comprises a gate coupled
to a gate terminal 140, for example, a bond pad. The main-FET 1050
comprises a source coupled to a main-FET source terminal 130. The
drain of the MOSFET 1050 is outside, e.g., below, the plane of FIG.
1A.
Power semiconductor device 1000 comprises a sense-FET 160, formed
within a region of the main-FET 1050, in accordance with
embodiments of the present invention. It is appreciated that die
area of main-FET 1050 is very much greater than die area of
sense-FET 160. The gate and drain of the sense-FET 160 are in
common, e.g., in parallel, with the gate and drain of the main-FET
1050. The source of the sense-FET 160 is coupled to a sense source
terminal 110, e.g., a bond pad. The sense-FET outputs a voltage
corresponding to current in the main-FET 1050. The node Kelvin may
be coupled to a terminal 120 for use off the die of power
semiconductor device 100, in some embodiments. The voltage Kelvin
may also, or alternatively, be used by circuitry (not shown) on the
die of power semiconductor device 1000, for example, to turn
main-FET 1050 off for over-current protection.
Power semiconductor device 1000 further comprises a sense-diode
720, formed within a region of the main-FET 1050, in accordance
with embodiments of the present invention. It is appreciated that
die area of main-FET 1050 is very much greater than die area of
sense-diode 720. The cathode of the sense-diode 720 is in common
with the drain of the main-FET 1050. The anode of sense-diode 720
is coupled to an anode terminal, e.g., a bond pad 710. The
sense-diode 720 may be used to measure temperature of the device
and/or gate voltage, as previously described. A power MOSFET device
comprising at least two sense-diodes is envisioned, and is
considered within the scope of the present invention. For example,
multiple sense diodes may be configured to measure temperature in
different regions of a MOSFET. In another embodiment, at least one
sense diode may be configured to indicate gate voltage in
conjunction with one or more sense diodes configured to measure
temperature.
Similarly, a power MOSFET device comprising at least two sense-FETs
is envisioned, and is considered within the scope of the present
invention. For example, due to temperature and manufacturing
process variations across a large die of a power MOSFET, current
within the MOSFET may not be uniformly distributed. Accordingly, it
may be advantageous to measure current via multiple sense-FETs at
different locations throughout such a device. As a beneficial
result of the novel high current sense ratio afforded by
embodiments of the present invention, small variations in current
may be observed in this manner.
FIG. 10B illustrates an exemplary schematic symbol for power
semiconductor device 1000, in accordance with embodiments of the
present invention.
It is to be appreciated that no additional masks or manufacturing
process steps are required to form sense-FET 160 and/or sense-diode
720. Both sense-FET 160 and sense-diode 720 utilize structures
common to a main-FET, e.g., trenches and poly layers, for their
function, and further utilize structures common to a main-FET,
e.g., trenches and BPSG, for isolation. Accordingly, the benefits
of a sense-FET 160 and/or sense-diode 720 may be realized with no
additional manufacturing cost in comparison to a trench MOSFET.
Embodiments in accordance with the present invention are well
suited to a variety of trench MOSFETs, including, for example,
single gate trench MOSFETs, split gate charge balanced trench
MOSFETs, Hybrid Split Gate MOSFETs, for example, as disclosed in
co-pending, commonly owned U.S. patent application Ser. No.
13/460,567, filed Apr. 20, 2012, to Bobde et al., entitled "Hybrid
Split Gate Semiconductor," which is hereby incorporated herein by
reference in its entirety, and dual trench MOSFETs, for example, as
described in the publication: "Poly Flanked VDMOS (PFVDMOS): A
Superior Technology for Superjunction Devices" by K. P. Gan, Y. C.
Liang, G. Samudra, S. M. Xu, L. Yong, IEEE Power Electronics
Specialist Conference, 2001.
Embodiments in accordance with the present invention provide
systems and methods for current sense metal oxide semiconductor
field effect transistors (MOSFETs) in vertical trench MOSFETs. In
addition, embodiments in accordance with the present invention
provide systems and methods for current sense MOSFETs in vertical
trench MOSFETs that are integral to the main-FET. Further,
embodiments in accordance with the present invention provide
systems and methods for current sense MOSFETs in vertical trench
MOSFETs that are integral to the main-FET. Yet further embodiments
in accordance with the present invention provide systems and
methods for a sensing diode to sense temperature and/or gate
voltage of the main-FET. Still further, embodiments in accordance
with the present invention provide systems and methods for systems
and methods for current sense MOSFETs and/or sense diodes in
vertical trench MOSFETs that are compatible and complementary with
existing systems and methods of integrated circuit design,
manufacturing and test.
Various embodiments of the invention are thus described. While the
present invention has been described in particular embodiments, it
should be appreciated that the invention should not be construed as
limited by such embodiments, but rather construed according to the
below claims.
* * * * *