U.S. patent number 10,636,910 [Application Number 15/629,885] was granted by the patent office on 2020-04-28 for semiconductor device structure and method of forming the same.
This patent grant is currently assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.. The grantee listed for this patent is TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.. Invention is credited to Kuan-Lun Cheng, Kuo-Cheng Ching, Kuan-Ting Pan, Chih-Hao Wang.
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United States Patent |
10,636,910 |
Ching , et al. |
April 28, 2020 |
Semiconductor device structure and method of forming the same
Abstract
A semiconductor device is provided, which includes a substrate,
a fin structure, a capping layer and an oxide layer. The substrate
has a well. The fin structure extends from the well. The capping
layer surrounds a top surface and side surfaces of the fin
structure. The oxide layer is over the substrate and covers the
capping layer. A thickness of a top portion of the oxide layer
above the capping layer is greater than a thickness of a sidewall
portion of the oxide layer.
Inventors: |
Ching; Kuo-Cheng (Hsinchu
County, TW), Pan; Kuan-Ting (Taipei, TW),
Cheng; Kuan-Lun (Hsinchu, TW), Wang; Chih-Hao
(Hsinchu County, TW) |
Applicant: |
Name |
City |
State |
Country |
Type |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
Hsinchu |
N/A |
TW |
|
|
Assignee: |
TAIWAN SEMICONDUCTOR MANUFACTURING
CO., LTD. (Hsinchu, TW)
|
Family
ID: |
64460843 |
Appl.
No.: |
15/629,885 |
Filed: |
June 22, 2017 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20180350969 A1 |
Dec 6, 2018 |
|
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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62512715 |
May 30, 2017 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
21/823431 (20130101); H01L 29/785 (20130101); H01L
29/1608 (20130101); H01L 27/0886 (20130101); H01L
29/16 (20130101); H01L 29/66545 (20130101); H01L
29/66795 (20130101) |
Current International
Class: |
H01L
27/088 (20060101); H01L 29/78 (20060101); H01L
29/16 (20060101); H01L 29/66 (20060101); H01L
21/8234 (20060101) |
Field of
Search: |
;257/288 ;438/197 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Han; Jonathan
Attorney, Agent or Firm: McClure, Qualey & Rodack,
LLP
Parent Case Text
RELATED APPLICATIONS
This application claims priority to U.S. Provisional Application
Ser. No. 62/512,715, filed May 30, 2017, which is herein
incorporated by reference.
Claims
What is claimed is:
1. A semiconductor device structure, comprising: a substrate having
a well; a fin structure extending from the well; a capping layer
surrounding a top surface and side surfaces of the fin structure,
wherein a thickness of a top portion of the capping layer above the
fin structure is greater than a thickness of a sidewall portion of
the capping layer; and a dielectric oxide layer over the substrate
and covering the capping layer, wherein a thickness of a top
portion of the dielectric oxide layer above the capping layer is
greater than a thickness of a sidewall portion of the dielectric
oxide layer.
2. The semiconductor device structure of claim 1, wherein the fin
structure comprises silicon germanium.
3. The semiconductor device structure of claim 1, wherein the fin
structure comprises silicon phosphoric, silicon carbide, or a
combination thereof.
4. The semiconductor device structure of claim 1, wherein the
thickness of the top portion of the dielectric oxide layer is
greater than the thickness of the sidewall portion of the
dielectric oxide layer by 10 angstroms to 50 angstroms.
5. The semiconductor device structure of claim 1, wherein the
dielectric oxide layer comprises silicon oxide, silicon oxynitride,
silicon oxycarbide, or a combination thereof.
6. The semiconductor device structure of claim 1, wherein the
thickness of the top portion of the capping layer above the fin
structure and the thickness of the sidewall portion of the capping
layer are at least 3 angstroms.
7. The semiconductor device structure of claim 1, further
comprising: a liner layer conformal to side surfaces of a protruded
portion of the well; and an isolation feature over the substrate
and the liner layer.
8. The semiconductor device structure of claim 1, further
comprising a metallic gate structure over the dielectric oxide
layer.
9. A semiconductor device structure, comprising: a substrate having
a first well of a first type and a second well of a second type,
wherein the first type is different from the second type; a first
fin structure extending from the first well; a second fin structure
extending from the second well; a capping layer surrounding a top
surface and side surfaces of each of the first fin structure and
the second fin structure; and a dielectric oxide layer over the
substrate and covering the capping layer, wherein the dielectric
oxide layer has a first top portion over the first fin structure, a
second top portion over the second fin structure, and a U-shaped
portion connecting the first top portion and the second top
portion, and a bottommost part of the U-shaped portion laterally
extending along STI region has a thickness smaller than thicknesses
of the first and second top portions, and the thickness of the
first top portion of the dielectric oxide layer above the capping
layer is greater than a thickness of each of sidewall parts of the
U-shaped portion of the dielectric oxide layer.
10. The semiconductor device structure of claim 9, wherein the
first fin structure comprises silicon germanium, and wherein the
second fin structure comprises silicon phosphoric, silicon carbide,
or a combination thereof.
11. The semiconductor device structure of claim 9, wherein the
thickness of the top portion of the dielectric oxide layer is
greater than the thickness of each of the sidewall parts of the
U-shaped portion of the dielectric oxide layer by 10 angstroms to
50 angstroms.
12. The semiconductor device structure of claim 9, wherein the
dielectric oxide layer comprises silicon oxide, silicon oxynitride,
silicon oxycarbide, or a combination thereof.
13. The semiconductor device structure of claim 9, wherein a
thickness of a top portion of the capping layer and a thickness of
each of sidewall portions of the capping layer are at least 3
angstroms.
14. The semiconductor device structure of claim 9, further
comprising a gate dielectric over the dielectric oxide layer.
15. A semiconductor device structure, comprising: a substrate
having a well; a fin structure extending from the well; a capping
layer covering the fin structure; and a dielectric oxide layer
having a top portion over a top surface of the fin structure and a
sidewall portion over a side surface of the fin structure, wherein
a thickness of the top portion of the dielectric oxide layer is
greater than a thickness of the sidewall portion of the dielectric
oxide layer, wherein the capping layer has a top portion in contact
with the top portion of the dielectric oxide layer and a sidewall
portion in contact with the sidewall portion of the dielectric
oxide layer, and a thickness of the top portion of the capping
layer is greater than a thickness of the sidewall portion of the
capping layer.
16. The semiconductor device structure of claim 15, wherein the fin
structure comprises silicon germanium.
17. The semiconductor device structure of claim 15, wherein the fin
structure comprises silicon phosphoric, silicon carbide, or a
combination thereof.
18. The semiconductor device structure of claim 15, wherein the
thickness of the top portion of the dielectric oxide layer is
greater than the thickness of the sidewall portion of the
dielectric oxide layer by 10 angstroms to 50 angstroms.
19. The semiconductor device structure of claim 15, wherein the
dielectric oxide layer comprises silicon oxide, silicon oxynitride,
silicon oxycarbide, or a combination thereof.
20. The semiconductor device structure of claim 15, further
comprising: a liner layer conformal to side surfaces of a protruded
portion of the well; and an isolation feature over the substrate
and the liner layer.
Description
BACKGROUND
The electronics industry has experienced an ever increasing demand
for smaller and faster electronic devices which are simultaneously
able to support a greater number of increasingly complex and
sophisticated functions. Accordingly, there is a continuing trend
in the semiconductor industry to manufacture low-cost,
high-performance, and low power consumption integrated circuits
(ICs). These goals have been achieved in large part by scaling down
semiconductor IC dimensions (e.g., minimum feature size) and
thereby improving production efficiency and lowering associated
costs. However, such scaling has also introduced increased
complexity to the semiconductor manufacturing process. Thus, the
realization of continued advances in ICs and semiconductor devices
calls for similar advances in semiconductor manufacturing processes
and technology.
BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the present disclosure are best understood from the
following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
FIG. 1 is a schematic layout diagram of a semiconductor device
structure in accordance with some embodiments of the present
disclosure.
FIG. 2A to FIG. 2G are schematic cross-sectional views of
intermediate stages in the formation of a semiconductor device
structure in accordance with some embodiments of the present
disclosure.
DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or
examples, for implementing different features of the provided
subject matter. Specific examples of components and arrangements
are described below to simplify the present disclosure. These are,
of course, merely examples and are not intended to be limiting. For
example, the formation of a first feature over or on a second
feature in the description that follows may include embodiments in
which the first and second features are formed in direct contact,
and may also include embodiments in which additional features may
be formed between the first and second features, such that the
first and second features may not be in direct contact.
Terms used herein are only used to describe the specific
embodiments, which are not used to limit the claims appended
herewith. For example, unless limited otherwise, the term "one" or
"the" of the single form may also represent the plural form. In
addition, the present disclosure may repeat reference numerals
and/or letters in the various examples. This repetition is for the
purpose of simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
discussed. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The device may
be otherwise oriented (rotated 90 degrees or at other orientations)
and the spatially relative descriptors used herein may likewise be
interpreted accordingly.
It will be understood that, although the terms "first," "second,"
etc., may be used in the claims to describe various elements and/or
features, these elements and/or features should not be limited by
these terms, and these elements and/or features correspondingly
described in the embodiments are presented by different reference
numbers. These terms are used to distinguish one element and/or
feature from another. For example, a first element could be termed
a second element, and, similarly, a second element could be termed
a first element, without departing from the scope of the
embodiments. As used herein, the term "and/or" includes any and all
combinations of one or more of the associated listed items.
Further, spatially relative terms, such as "upper," "lower," "on,"
and the like, may be used herein for ease of description to
describe one element or feature's relationship to another
element(s) or feature(s) as illustrated in the figures. The
spatially relative terms are intended to encompass different
orientations of the device in use or operation in addition to the
orientation depicted in the figures. The apparatus may be otherwise
oriented (rotated 90 degrees or at other orientations) and the
spatially relative descriptors used herein may likewise be
interpreted accordingly.
The fins may be patterned by any suitable method. For example, the
fins may be patterned using one or more photolithography processes,
including double-patterning or multi-patterning processes.
Generally, double-patterning or multi-patterning processes combine
photolithography and self-aligned processes, allowing patterns to
be created that have, for example, pitches smaller than what is
otherwise obtainable using a single, direct photolithography
process. For example, in one embodiment, a sacrificial layer is
formed over a substrate and patterned using a photolithography
process. Spacers are formed alongside the patterned sacrificial
layer using a self-aligned process. The sacrificial layer is then
removed, and the remaining spacers may then be used to pattern the
fins.
Embodiments of the present disclosure are directed to a
semiconductor device structure and a method of forming the same. In
the semiconductor device structure, a non-uniform thickness oxide
layer with a of the oxide layer. Particularly, a portion of the
oxide layer above fin structures is formed by oxidating a portion
of an underlying capping layer, such that a thickness of the top
portion of the oxide layer is increased without producing an
overhang structure at the top portion of the oxide layer. In
addition, the etching window to a dummy gate structure can be
increased, and damages and notching issues of the fin structure can
be avoided when performing the etching process with higher power to
the dummy gate structure, and thus threshold voltage of the gate
structure of the final semiconductor device structure is controlled
to a desired value according to a design requirement. Further, the
capping layer is formed over the fin structures for providing a
protection function for the fin structures and during the
subsequent processes (such as forming and removing of a dummy gate
structure, forming of a gate structure and a gate dielectric,
etc.). A top portion of the capping layer may be at least 3
angstroms, in order to reduce the interface trap density of the
oxide layer. Embodiments of the present disclosure provide at least
the foregoing advantages for fabricating a semiconductor device,
e.g. of 7 nm technology node or beyond.
FIG. 1 is a cross-sectional view of a semiconductor device
structure 100 in accordance with some embodiments of the present
disclosure. In the semiconductor device structure 100, a substrate
102 is provided, which may be a semiconductor substrate, such as a
bulk semiconductor, a silicon-on-insulator (SOI) substrate, or the
like. In a case of SOI substrate, a semiconductor material layer is
formed on an insulator layer which may be, for example, a buried
oxide (BOX) layer, a silicon oxide layer, or the like. The
insulator layer is provided on a substrate, typically a silicon
substrate or a glass substrate. Another substrate, such as a
multi-layered or gradient substrate may also be used. In some
embodiments, the semiconductor material layer may be formed from,
for example, silicon, germanium, silicon carbide, silicon
germanium, gallium arsenide, gallium phosphide, gallium arsenide
phosphide, indium arsenide, indium phosphide, indium antimonide,
aluminium indium arsenide, aluminium gallium arsenide, gallium
indium arsenide, gallium indium phosphide, gallium indium arsenide
phosphide, combinations thereof, or another suitable material. In
some examples, the substrate 102 includes a silicon germanium layer
and a silicon layer lying on the silicon germanium layer.
As shown in FIG. 1, the substrate 102 is separated into two device
regions, i.e., a P-type device region 102A and an N-type device
region 102B. An N-type well N-well and a P-type well P-well are on
the substrate 102 and respectively in the P-type device region 102A
and in the N-type device region 102B. The N-type well N-well and
the P-type well P-well may have dopants of appropriate types. For
example, the N-type well N-well may include N-type dopants, such as
phosphorus, antimony, arsenic, and/or the like, and the P-type well
P-well may include P-type dopants, such as boron, gallium, indium,
and/or the like. Each of the N-type well N-well and the P-type well
P-well includes protruded portions, and a liner layer 104 and an
isolation feature 106 are between two neighboring protruded
portions of the N-type well N-well and/or the P-type well P-well.
The liner layer 104 is conformal to side surfaces of the protruded
portions of the N-type well N-well and the P-type well P-well. The
liner layer 104 may include silicon nitride, silicon carbide,
silicon carbon nitride, silicon oxycarbonitride, combinations
thereof, or the like. The isolation feature 106 is formed for
electrically isolating fin structures 108A in the P-type device
region 102A from fin structures 108B in the N-type device region
102B. The isolation feature 106 may include flowable oxide, such as
phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped
phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS)
oxide, titanium nitride, silicon oxycabride (SiOC), or another
low-k nonporous dielectric material.
In the P-type device region 102A, the fin structures 108A extend
from the N-type well N-well, and in the N-type device region 102B,
the fin structures 108B extends from the P-type well P-well. The
fin structures 108A are respectively on the protruded portions of
the N-type well N-well, and the fin structures 108B are
respectively on the protruded portions of the P-type well P-well.
The fin structures 108A may include, for example, silicon,
germanium, silicon germanium, germanium boron, silicon germanium
boron, a III-V material (such as indium antimonide, gallium
antimonide, indium gallium antimonide), combinations thereof, or
the like. The fin structures 108B may include, for example,
silicon, silicon phosphide, silicon carbide, silicon phosphide
carbide, germanium, germanium phosphide, a III-V material (such as
indium phosphide, aluminium arsenide, gallium arsenide, indium
arsenide, gallium indium arsenide and aluminium indium arsenide),
combinations thereof, or the like. In addition, the fin structures
108A and 108B are doped with dopants of appropriate types and
concentrations. For example, P-type dopants, such as boron, boron
fluorine, silicon, germanium, carbon, zinc, cadmium, beryllium,
magnesium, indium, combinations thereof, and/or the like, may be
implanted into the fin structures 108A with a concentration of
about 10.sup.18 atoms/cm.sup.3 to about 10.sup.22 atoms/cm.sup.3,
and N-type dopants, such as phosphorus, arsenic, antimony, silicon,
germanium, carbon, oxygen, sulfur, selenium, tellurium,
combinations thereof, and/or the like, may be implanted into the
fin structures 108B with a concentration of about 10.sup.18
atoms/cm.sup.3 to about 10.sup.22 atoms/cm.sup.3.
A capping layer 110 is over the fin structures 108A and 108B, and
an oxide layer 112 is over the substrate 102 and covers the
isolation feature 106 and the capping layer 110. As shown in FIG.
1, the capping layer 110 includes a top portion 110A and a sidewall
portion 110B; the top portion 110A surrounds a top surface of each
of the fin structures 108A and 108B, while the sidewall portion
110B surrounds side surface of each of the fin structures 108A and
108B. The capping layer 110 may include essential silicon. A
thickness T.sub.110A of the top portion 110A and a thickness
T.sub.110B of the sidewall portion 110B of the capping layer 110
may be the same or different. In some embodiments, the thickness
T.sub.110A of the top portion 110A may be at least 3 angstroms, in
order to reduce the interface trap density of the oxide layer 112.
Further, the thickness T.sub.110B of the sidewall portion 110B may
also be at least 3 angstroms.
The oxide layer 112 may include silicon oxide, silicon oxynitride,
silicon oxycarbide, combinations thereof, or the like, and may be
formed by a deposition process, such as a chemical vapor deposition
(CVD) process, a sub-atmospheric CVD (SACVD) process, a physical
vapor deposition (PVD) process, an atomic layer deposition (ALD)
process, or another suitable process. In some embodiments, a
portion of the oxide layer 112 is formed by performing an oxidation
process on the capping layer 110.
The oxide layer 112 includes a top portion 112A and a sidewall
portion 112B. For example, for the semiconductor device structure
100 of 7 nm technology node, a thickness T.sub.112B of the sidewall
portion 112B may be about 37 angstroms; for the semiconductor
device structure 100 of 5 nm technology node or beyond, the
thickness T.sub.112B of the sidewall portion 112B may be about 26
angstroms or less. A thickness T.sub.112A of the top portion 112A
is greater than the thickness T.sub.112B of the sidewall portion
112B. In some embodiments, the thickness T.sub.112A of the top
portion 112A is greater than the thickness T.sub.112B of the
sidewall portion 112B by about 10 angstroms to about 50 angstroms.
For example, the thickness T.sub.112A of the top portion 112A may
be greater than the thickness T.sub.112B of the sidewall portion
112B by about 15 angstroms to about 25 angstroms.
A gate dielectric 114 is over the fin structures 108A and 108B, the
capping layer 110 and the oxide layer 112. As shown in FIG. 1, the
gate dielectric 114 covers the top portion 112A and the sidewall
portion 112B of the oxide layer 112. The gate dielectric 114 may
include a material such as, but not limited to, silicon oxide,
hafnium oxide, titanium oxide, aluminum oxide, tin oxide, zinc
oxide, high-k dielectrics, combinations thereof, and/or the like.
In some embodiments, the gate dielectric 114 includes multi-layer
structure of, for example, silicon oxide or silicon oxynitride with
a high-k dielectric. In alternative embodiments, an interfacial
layer (not shown) may also be formed between the oxide layer 112
and gate dielectric 114.
A gate structure 116 is over the fin structures 108A and 108B, the
capping layer 110, the oxide layer 112 and the gate dielectric 114.
The gate structure 116 may include a metallic material (such as
titanium, tantalum, tungsten, aluminum, molybdenum, platinum and
hafnium), a metal silicide material (such as titanium silicide,
tantalum silicide, tungsten silicate, molybdenum silicate, nickel
silicide and cobalt silicide), a metal nitride material (such as
titanium nitride, tantalum nitride, tungsten nitride, molybdenum
silicate, nickel nitride and cobalt nitride), silicided metal
nitride (such as titanium silicon nitride, tantalum silicon nitride
and tungsten silicon nitride), polysilicon, amorphous silicon,
combinations thereof, and/or another suitable material.
FIG. 2A to FIG. 2G illustrate cross-sectional views of various
intermediary steps of forming a semiconductor device structure in
accordance with various embodiments. In FIG. 2A, a substrate 202 is
illustrated. The substrate 202 may be a semiconductor substrate,
such as a bulk semiconductor, an SOI substrate, or the like. In a
case of SOI substrate, a semiconductor material layer is formed on
an insulator layer which may be, for example, a BOX layer, a
silicon oxide layer, or the like. The insulator layer is provided
on a substrate, typically a silicon substrate or a glass substrate.
Another substrate, such as a multi-layered or gradient substrate
may also be used. In some embodiments, the semiconductor material
layer may be formed from, for example, silicon, germanium, silicon
carbide, silicon germanium, gallium arsenide, gallium phosphide,
gallium arsenide phosphide, indium arsenide, indium phosphide,
indium antimonide, aluminium indium arsenide, aluminium gallium
arsenide, gallium indium arsenide, gallium indium phosphide,
gallium indium arsenide phosphide, combinations thereof, or another
suitable material.
The substrate 202 includes a P-type device region 202A and an
N-type device region 202B, and an N-type well N-well and a P-type
well P-well on the substrate 202 are respectively in the P-type
device region 202A and the N-type device region 202B. The N-type
well N-well and the P-type well P-well may be formed by implanting
dopants of appropriate types into the substrate 202. For example,
the N-type well N-well may be formed by implanting N-type dopants,
such as phosphorus, antimony, arsenic, and/or the like, and the
P-type well P-well may be formed by implanting P-type dopants, such
as boron, gallium, indium, and/or the like.
Semiconductor layers 204A and 204B are formed over the substrate
202. As shown in FIG. 2A, the semiconductor layer 204A is formed on
the N-type well N-well and in the P-type device region 202A, and
the semiconductor layer 204B is formed on the P-type well P-well
and in the N-type device region 202B. The semiconductor layer 204A
may be formed from, for example, silicon, germanium, silicon
germanium, germanium boron, silicon germanium boron, a III-V
material (such as indium antimonide, gallium antimonide, indium
gallium antimonide), combinations thereof, or the like. The
semiconductor layer 204B may be formed from, for example, silicon,
silicon phosphide, silicon carbide, silicon phosphide carbide,
germanium, germanium phosphide, a III-V material (such as indium
phosphide, aluminium arsenide, gallium arsenide, indium arsenide,
gallium indium arsenide and aluminium indium arsenide),
combinations thereof, or the like. Each of the semiconductor layers
204A and 204B may be formed by using an epitaxy process, such as a
metal-organic (MO) CVD process, a liquid phase epitaxy (LPE)
process, a vapor phase epitaxy (VPE) process, a molecular beam
epitaxy (MBE) process, a selective epitaxial growth (SEG) process,
combinations thereof, and/or another suitable process. Then, the
semiconductor layers 204A and 204B are doped with dopants of
appropriate types and concentrations. For example, P-type dopants,
such as boron, boron fluorine, silicon, germanium, carbon, zinc,
cadmium, beryllium, magnesium, indium, combinations thereof, and/or
the like, may be implanted into the semiconductor layer 204A with a
concentration of about 10.sup.18 atoms/cm.sup.3 to about 10.sup.22
atoms/cm.sup.3, and N-type dopants, such as phosphorus, arsenic,
antimony, silicon, germanium, carbon, oxygen, sulfur, selenium,
tellurium, combinations thereof, and/or the like, may be implanted
into the semiconductor layer 204B with a concentration of about
10.sup.18 atoms/cm.sup.3 to about 10.sup.22 atoms/cm.sup.3.
In some embodiments, as shown in FIG. 2A, a spacer 206 is formed
between the semiconductor layers 204A and 204B, in order to
separate the semiconductor layers 204A and 204B from each other.
The spacer 206 may be formed including a material such as silicon
nitride, silicon oxynitride, silicon carbide, and/or the like.
Further, a planarization process, such as a chemical mechanical
polishing (CMP) process, is performed to planarize the
semiconductor layers 204A and 204B and the spacer 206.
In FIG. 2B, an epitaxial layer 208 is formed over the substrate
202, the semiconductor layers 204A and 204B and the spacer 206. The
epitaxial layer 208 may be formed from essential silicon, and may
be formed by an epitaxial growth process, a CVD process, a PVD
process, and/or another suitable deposition process. In some
embodiments, the epitaxial layer 208 is formed with a thickness of
about 40 angstroms.
In FIG. 2C, a dielectric layer 210 and a hard mask layer 212 are
sequentially formed over the epitaxial layer 208. The dielectric
layer 210 may be used as an adhesive layer between the epitaxial
layer 208 and the hard mask layer 212, and may be used as a etch
stop layer for etching the hard mask layer 212. The dielectric
layer 210 may be formed from an oxide material, such as silicon
oxide, hafnium oxide, combinations thereof, and/or the like, and
may be formed by using a thermal oxidation process or another
suitable process. The hard mask layer 212 may be formed from a
nitride material, such as silicon nitride, silicon carbon nitride,
titanium nitride, combinations thereof, and/or the like, and may be
formed by using a deposition process, such as a CVD process, a low
pressure CVD (LPCVD) process, a plasma enhanced CVD (PECVD)
process, a PVD process, an ALD process, combinations thereof,
and/or another suitable process. Then, a patterned photoresist
layer (not shown) is formed over the hard mask layer 212, and an
etching process, such as a dry etching process, is performed to
remove the spacer 206 and portions of the substrate 202, the
semiconductor layers 204A and 204B, the epitaxial layer 208, the
dielectric layer 210 and the hard mask layer 212, so as to form fin
structures 204A' from the semiconductor layer 204A and fin
structures 204B' from the semiconductor layer 204B. In some other
embodiments, each of the fin structures 204A' and 204B' has a width
that gradually increases from the top portion to the lower portion.
A pitch between two adjacent fin structures 204A' or 204B' (e.g.
the pitch P between the fin structures 204B') may be about 26
angstrom or less. After forming the fin structures 204A' and 204B',
the dielectric layer 210 and the hard mask layer 212 are removed by
one or more etching processes and/or another suitable removing
process.
In FIG. 2D, a liner layer 214 is formed surrounding a lower portion
of the side surfaces of each of the fin structures 204A' and 204B',
and an isolation feature 216 is formed over the substrate 202, the
fin structures 204A' and 204B' and the liner layer 214. The liner
layer 214 may be formed from, for example, silicon nitride, silicon
carbide, silicon carbon nitride, silicon oxycarbonitride,
combinations thereof, or the like, and may be formed by a
deposition process (such as a CVD process, a PVD process and an ALD
process) and a thermal oxidation process. The isolation feature 216
is formed for electrically isolating the fin structures 204A' in
the P-type device region 202A from the fin structures 204B' in the
N-type device region 202B. The isolation feature 216 may be formed
including flowable oxide, such as PSG, BSG, BPSG, TEOS oxide,
titanium nitride, silicon oxycabride, and/or another low-k
nonporous dielectric material. The isolation feature 216 may be
formed from a flowable oxide by using a flowable CVD process or
another suitable process.
In FIG. 2E, portions of the liner layer 214 and the isolation
feature 216 above the substrate 202 are removed are removed by
using one or more processes, such as a CMP process, an etching back
process, combinations thereof, and/or the like. Next, a capping
layer 218 is formed surrounding side surfaces of the fin structures
and on the epitaxial layer 208. The capping layer 218 and the
epitaxial layer 208 provide a protection function for the fin
structures 204A' and 204B' during the subsequent processes. The
capping layer 218 may be formed from essential silicon by using an
ALD process, a plasma enhanced ALD (PEALD) process, or another
suitable process.
In FIG. 2F, an oxide layer 220 is formed over the epitaxial layer
208, the isolation feature 216 and the capping layer 218. The oxide
layer 220 may be formed from silicon oxide, silicon oxynitride,
silicon oxycarbide, or a combination thereof, and may be formed by
using a CVD process, an SACVD process, a PVD process, an ALD
process, or another suitable process. Then, an oxidation process is
performed on the epitaxial layer 208 and the capping layer 218,
such that an upper portion of epitaxial layer 208 and the capping
layer 218 are oxidated by an oxygen plasma to form an oxide layer
222. Therefore, the overall oxide layer (labeled as "224" in FIG.
2F) includes the oxide layers 220 and 222 with reduced silicon
variation.
In some embodiments, after the oxidation process, a thickness
T.sub.218 of the capping layer 218 is at least 3 angstroms, in
order to reduce the interface trap density of the oxide layer 224.
In further embodiments, a thickness T.sub.208 of the remained
epitaxial layer 208 is also at least 3 angstroms.
As shown in FIG. 2F, the oxide layer 224 includes a top portion
224A and a sidewall portion 224B. For the oxide layer 224, a
thickness of a top portion 224A above the epitaxial layer 208 and
the capping layer 218 is greater than a thickness of a sidewall
portion 224B. With such criterion, overhang issue subsequent
processes. A thickness T.sub.224A of the top portion 224A is
greater than a thickness T.sub.224B of the sidewall portion 224B.
In some embodiments, the thickness T.sub.224A of the top portion
224A is greater than the thickness T.sub.224B of the sidewall
portion 224B by about 10 angstroms to about 50 angstroms. For
example, the thickness T.sub.224A of the top portion 224A may be
greater than the thickness T.sub.224B of the sidewall portion 224B
by about 15 angstroms to about 25 angstroms.
In FIG. 2G, a dummy gate structure 226 is formed over the fin
structures 204A' and 204B', the epitaxial layer 208, the capping
layer 218 and the oxide layer 224, a dielectric layer 228 is formed
over the dummy gate structure 226, and a hard mask layer 230 is
formed over the dummy gate structure 226 and the dielectric layer
228. The dummy gate structure 226 may be formed from polysilicon,
amorphous silicon, combinations thereof, or another suitable
material. The dummy gate structure 226 may be formed by using, for
example, a CVD process, a PVD process or another suitable
deposition process. The dielectric layer 228 may be formed from an
oxide material, such as silicon oxide, hafnium oxide, combinations
thereof, and/or the like, and may be formed by using a thermal
oxidation process or another suitable process. The hard mask layer
230 may be formed from a nitride material, such as silicon nitride,
silicon carbon nitride, titanium nitride, combinations thereof,
and/or the like, and may be formed by using a deposition process,
such as a CVD process, an LPCVD process, a PECVD process, a PVD
process, an ALD process, combinations thereof, and/or another
suitable process.
After the process illustrated in FIG. 2G, the hard mask layer 230,
the dielectric layer 228 and the dummy gate structure 226 may be
sequentially removed during the subsequent processes, and a gate
structure and a gate dielectric may be formed in the locations of
the substrate 202 where the dummy gate structure 226 is removed.
Thus, the semiconductor device structure formed by a method in
accordance with the present disclosure is similar to the
semiconductor device structure 100 of FIG. 1. Particularly, the
feature of non-uniform oxide layer thickness of the oxide layer 224
in accordance with the present disclosure provides several
advantages. Because a portion of the oxide layer 224 above the fin
structures 204A' and 204B' are formed by oxidating the upper
portion of the epitaxial layer 208 and the capping layer 218, the
thickness T.sub.224A of the top portion 224A of the oxide layer 224
is increased without producing an overhang structure at the top
portion 224A of the oxide layer 224. In addition, the etching
window to the dummy gate structure 226 can be increased, and
damages and notching issues of the fin structures 204A' and 204B'
can be avoided when performing the etching process with higher
power to the dummy gate structure 226, and thus threshold voltage
of the gate structure of the final semiconductor device structure
is controlled to a desired value according to a design
requirement.
In accordance with some embodiments, a semiconductor device
structure includes a substrate, a fin structure, a capping layer
and an oxide layer. The substrate has a well. The fin structure
extends from the well. The capping layer surrounds a top surface
and side surfaces of the fin structure. The oxide layer is over the
substrate and covers the capping layer. A thickness of a top
portion of the oxide layer above the capping layer is greater than
a thickness of a sidewall portion of the oxide layer.
In accordance with certain embodiments, a method of forming a
semiconductor device structure includes the following steps. A
substrate is provided, which has a well. A semiconductor layer and
an epitaxial layer are formed over the substrate. The semiconductor
layer and the epitaxial layer are etched to form a fin structure
that extends from the well. A capping layer is formed surrounding
side surfaces of the fin structure and on the epitaxial layer. A
first oxide layer is formed over the capping layer and the
substrate. A portion of the capping layer and a portion of the
epitaxial layer are oxidized to form a second oxide layer between
the remained epitaxial layer and the first oxide layer.
In accordance with some embodiments, a semiconductor device
structure includes a substrate, a first fin structure, a second fin
structure, a capping layer and an oxide layer. The substrate has a
first well of a first type and a second well of a second type
different from the first type. The first fin structure extends from
the first well, and the second fin structure extends from the
second well. The capping layer surrounds a top surface and side
surfaces of each of the first fin structure and the second fin
structure. The oxide layer is over the substrate and covers the
capping layer. A thickness of a top portion of the oxide layer
above the capping layer is greater than a thickness of each of
sidewall portions of the oxide layer.
The foregoing outlines features of several embodiments so that
those skilled in the art may better understand the aspects of the
present disclosure. Those skilled in the art should appreciate that
they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
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