U.S. patent number 10,510,802 [Application Number 15/486,756] was granted by the patent office on 2019-12-17 for semiconductor device and method of manufacturing the same.
This patent grant is currently assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.. The grantee listed for this patent is TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.. Invention is credited to Tien-Wei Chiang, Harry-Hak-Lay Chuang, Wu-Chang Tsai.
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United States Patent |
10,510,802 |
Chuang , et al. |
December 17, 2019 |
Semiconductor device and method of manufacturing the same
Abstract
A semiconductor device includes a first conductive wiring, at
least one first dielectric layer, at least one second dielectric
layer and a second conductive wiring. The at least one first
dielectric layer is over the first conductive wiring. The at least
one second dielectric layer is over the at least one first
dielectric layer. The second conductive wiring is over the at least
one second dielectric layer. The dielectric constant of the at
least one second dielectric layer is higher than the dielectric
constant of the at least one first dielectric layer.
Inventors: |
Chuang; Harry-Hak-Lay
(Crescent, SG), Tsai; Wu-Chang (Hsinchu,
TW), Chiang; Tien-Wei (Taipei, TW) |
Applicant: |
Name |
City |
State |
Country |
Type |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. |
Hsinchu |
N/A |
TW |
|
|
Assignee: |
TAIWAN SEMICONDUCTOR MANUFACTURING
COMPANY LTD. (Hsinchu, TW)
|
Family
ID: |
63790971 |
Appl.
No.: |
15/486,756 |
Filed: |
April 13, 2017 |
Prior Publication Data
|
|
|
|
Document
Identifier |
Publication Date |
|
US 20180301505 A1 |
Oct 18, 2018 |
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
23/53295 (20130101); H01L 23/5226 (20130101); H01L
43/08 (20130101); H01L 27/222 (20130101); H01L
43/12 (20130101) |
Current International
Class: |
H01L
27/22 (20060101); H01L 23/532 (20060101); H01L
23/522 (20060101); H01L 43/08 (20060101); H01L
43/12 (20060101) |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Garber; Charles D
Assistant Examiner: Sabur; Alia
Attorney, Agent or Firm: WPAT, P.C., Intellectual Property
Attorneys King; Anthony
Claims
What is claimed is:
1. A semiconductor device, comprising: a first conductive wiring;
at least one first dielectric layer over the first conductive
wiring; at least one second dielectric layer comprises a first
layer and a second layer over the at least one first dielectric
layer; a second conductive wiring over the at least one second
dielectric layer; a conductive via electrically connected to the
first conductive wiring and the second conductive wiring, wherein a
dielectric constant of the at least one second dielectric layer is
higher than a dielectric constant of the at least one first
dielectric layer, the dielectric constant of the at least one first
dielectric layer is within a range of about 3.5 to about 4.5, the
dielectric constant of the at least one second dielectric layer is
within a range of about 4 to about 7; and a memory device
comprising: a first conductive structure under the at least one
first dielectric layer; a second conductive structure over the at
least one second dielectric layer; and a memory cell between the
first conductive structure and the second conductive structure, and
through the at least one first dielectric layer and the at least
one second dielectric layer, wherein the memory cell comprises: a
bottom electrode via over the first conductive structure; a bottom
electrode over and electrically connected to the bottom electrode
via; a top electrode over the bottom electrode a top electrode via
over the top electrode; and a magnetic tunnel junction (MTJ)
between the top electrode and the bottom electrode, wherein the at
least one first dielectric layer is below the bottom electrode and
surrounds edges of the bottom electrode via, wherein the second
layer of the at least one second dielectric layer surrounds the
entire sidewalls of the top electrode via, wherein the first layer
of the at least one second dielectric layer surrounds sidewalls of
the bottom electrode, sidewalls of the MTJ and sidewalls of the top
electrode, wherein both the first layer and the second layer of the
at least one second dielectric layer surround the sidewalls of the
conductive via.
2. The semiconductor device of claim 1, wherein a thickness of the
at least one second dielectric layer is larger than a thickness of
the at least one first dielectric layer.
3. The semiconductor device of claim 2, wherein a thickness of the
at least one first dielectric layer is within a range of about 50
angstroms to about 600 angstroms, and a thickness of the at least
one second dielectric layer is within a range of about 500
angstroms to about 1000 angstroms.
4. The semiconductor device of claim 1, further comprising a first
low-k dielectric layer surrounding an edge of the first conductive
wiring, wherein a dielectric constant of the first low-k dielectric
layer is lower than the dielectric constant of the at least one
first dielectric layer.
5. The semiconductor device of claim 4, wherein the dielectric
constant of the first low-k dielectric layer is equal to or less
than about 3.
6. The semiconductor device of claim 1, further comprising at least
one third dielectric layer over the at least one second dielectric
layer, wherein a dielectric constant of the at least one third
dielectric layer is lower than the dielectric constant of the at
least one second dielectric layer.
7. The semiconductor device of claim 6, wherein the dielectric
constant of the at least one third dielectric layer is within a
range of about 3.5 to about 4.5.
8. The semiconductor device of claim 6, further comprising a second
low-k dielectric layer over the at least one third dielectric
layer, wherein a dielectric constant of the second low-k dielectric
layer is lower than the dielectric constant of the at least one
third dielectric layer, and the at least one third dielectric layer
and the second low-k dielectric layer surround an edge of the
second conductive wiring.
9. The semiconductor device of claim 8, wherein the dielectric
constant of the second low-k dielectric layer is equal to or less
than about 3.
10. The semiconductor device of claim 8, further comprising at
least one fourth dielectric layer over the at least one third
dielectric layer and the second conductive wiring, wherein a
dielectric constant of the at least one fourth dielectric layer is
lower than the dielectric constant of the at least one second
dielectric layer.
11. The semiconductor device of claim 1, wherein the conductive via
through the at least one first dielectric layer and the at least
one second dielectric layer.
12. The semiconductor device of claim 1, wherein the sidewalls of
the top electrode via is free of the first layer of the at least
one second dielectric layer.
13. A semiconductor device, comprising: at least one first
dielectric layer; at least one second dielectric layer over the at
least one first dielectric layer, wherein a dielectric constant of
the at least one second dielectric layer is higher than a
dielectric constant of the at least one first dielectric layer; a
memory device comprising: a first conductive structure under the at
least one first dielectric layer; a second conductive structure
over the at least one second dielectric layer; a memory cell
between the first conductive structure and the second conductive
structure, and through the at least one first dielectric layer and
the at least one second dielectric layer; a top electrode via
between the second conductive structure and the memory cell; and a
bottom electrode via between the memory cell and the first
conductive structure; and a stacked conductive wiring device
comprising; a first conductive wiring under the at least one first
dielectric layer; a second conductive wiring over the at least one
second dielectric layer; and a conductive via between the first
conductive wiring and the second conductive wiring, and through the
at least one first dielectric layer and the at least one second
dielectric layer, wherein the at least one second dielectric layer
comprises a first layer configured as a spacer layer surrounding
edges of the memory cell and extending to the stacked conductive
wiring device, and a second layer over the first layer and
surrounds the entire sidewalls of the top electrode via, wherein
sidewalls of the memory cell are entirely in contact with the first
layer, and a top surface of the memory cell is free of the first
layer, wherein both the first layer and the second layer of the at
least one second dielectric layer surround the sidewalls of the
conductive via.
14. The semiconductor device of claim 13, further comprising at
least one third dielectric layer over the at least one second
dielectric layer, wherein a dielectric constant of the at least one
third dielectric layer is lower than the dielectric constant of the
at least one second dielectric layer.
15. The semiconductor device of claim 14, further comprising: a
first low-k dielectric layer under the at least one first
dielectric layer, and surrounding an edge of the first conductive
wiring and an edge of the first conductive structure, wherein a
dielectric constant of the first low-k dielectric layer is lower
than the dielectric constant of the at least one first dielectric
layer; and a second low-k dielectric layer over the at least one
third dielectric layer, wherein the at least one third dielectric
layer and the second low-k dielectric layer surround an edge of the
second conductive wiring and an edge of the second conductive
structure, and a dielectric constant of the second low-k dielectric
layer is lower than the dielectric constant of the at least one
third dielectric layer.
16. The semiconductor device of claim 13, wherein the memory cell
comprises: a bottom electrode via over the first conductive
structure; a bottom electrode over the bottom electrode via; a
magnetic tunnel junction (MTJ) over the bottom electrode; a top
electrode over the MTJ; and a top electrode via over the top
electrode.
17. The semiconductor device of claim 16, wherein the spacer layer
surrounds edges of the bottom electrode, the MTJ and the top
electrode of the memory cell.
18. A method for manufacturing a semiconductor device, comprising:
receiving a substrate; forming a first conductive wiring and a
first conductive structure over the substrate; forming at least one
first dielectric layer over the first conductive wiring and the
first conductive structure; forming at least one second dielectric
layer over the at least one first dielectric layer, wherein the at
least one second dielectric layer comprises a first layer and a
second layer, wherein a dielectric constant of the at least one
second dielectric layer is higher than a dielectric constant of the
at least one first dielectric layer, the dielectric constant of the
at least one first dielectric layer is within a range of about 3.5
to about 4.5, and the dielectric constant of the at least one
second dielectric layer is within a range of about 4 to about 7;
forming a conductive via in the at least one first dielectric layer
and the at least one second dielectric layer; forming a memory cell
over the first conductive structure, wherein the memory cell
comprises: a bottom electrode via over the first conductive
structure; a bottom electrode over and electrically connected to
the bottom electrode via, wherein the at least one first dielectric
layer is below the bottom electrode and surrounds edges of the
bottom electrode via; a top electrode over the bottom electrode;
and a magnetic tunnel junction (MTJ) between the top electrode and
the bottom electrode, and forming a second conductive wiring and a
second conductive structure over the at least one second dielectric
layer wherein the first layer of the at least one second dielectric
layer surrounds sidewalls of the top electrode, sidewalls of the
MTJ and sidewalls of the bottom electrode, wherein the second layer
of the at least one second dielectric layer surrounds the entire
sidewalls of the top electrode via, wherein both the first layer
and the second layer of the at least one second dielectric layer
surround the sidewalls of the conductive via.
19. The method of claim 18, further comprising: forming at least
one third dielectric layer over the at least one second dielectric
layer; and forming a low-k dielectric layer over the at least one
third dielectric layer, wherein the at least one third dielectric
layer and the low-k dielectric layer surround an edge of the second
conductive wiring, a dielectric constant of the at least one third
dielectric layer is lower than the dielectric constant of the at
least one second dielectric layer, and a dielectric constant of the
low-k dielectric layer is lower than the dielectric constant of the
at least one third dielectric layer.
20. The method of claim 18, wherein a top surface of the memory
cell is free of the first layer of the at least one second
dielectric layer.
Description
BACKGROUND
Electronic device such as memory device and peripheral device such
as logic device normally have different electrical requirements
such as capacitance requirements. It requires additional processes
to form different dielectric layers in the memory device and in the
logic device, and thus manufacturing cost and complexity are
increased.
BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the embodiments of the present disclosure are best
understood from the following detailed description when read with
the accompanying figures. It is noted that, in accordance with the
standard practice in the industry, various structures are not drawn
to scale. In fact, the dimensions of the various structures may be
arbitrarily increased or reduced for clarity of discussion.
FIG. 1 is a flow chart illustrating a method for manufacturing a
semiconductor device according to various aspects of one or more
embodiments of the present disclosure.
FIG. 2A, FIG. 2B and FIG. 2C are schematic views at one of various
operations of manufacturing a semiconductor device according to one
or more embodiments of the present disclosure.
FIG. 3 is a schematic cross-sectional view of a semiconductor
device according to one or more embodiments of the present
disclosure.
FIG. 4A, FIG. 4B, FIG. 4C and FIG. 4D are schematic views at one of
various operations of manufacturing an semiconductor device
according to one or more embodiments of the present disclosure.
FIG. 5 is a schematic cross-sectional view of a semiconductor
device according to a comparative embodiment of the present
disclosure.
FIG. 6 is an equivalent circuit diagram of a stacked conductive
wiring device.
DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or
examples, for implementing different features of the provided
subject matter. Specific examples of elements and arrangements are
described below to simplify the present disclosure. These are, of
course, merely examples and are not intended to be limiting. For
example, the formation of a first feature over or on a second
feature in the description that follows may include embodiments in
which the first and second features are formed in direct contact,
and may also include embodiments in which additional features may
be formed between the first and second features, such that the
first and second features may not be in direct contact. In
addition, the present disclosure may repeat reference numerals
and/or letters in the various examples. This repetition is for the
purpose of simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
discussed.
Further, spatially relative terms, such as "beneath", "below",
"lower", "above", "upper", "on" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
As used herein, the terms such as "first" and "second" describe
various elements, components, regions, layers and/or sections,
these elements, components, regions, layers and/or sections should
not be limited by these terms. These terms may be only used to
distinguish one element, component, region, layer or section from
another. The terms such as "first", "second", and "third" when used
herein do not imply a sequence or order unless clearly indicated by
the context.
As used herein, the terms "approximately," "substantially,"
"substantial" and "about" are used to describe and account for
small variations. When used in conjunction with an event or
circumstance, the terms can refer to instances in which the event
or circumstance occurs precisely as well as instances in which the
event or circumstance occurs to a close approximation. For example,
when used in conjunction with a numerical value, the terms can
refer to a range of variation of less than or equal to .+-.10% of
that numerical value, such as less than or equal to .+-.5%, less
than or equal to .+-.4%, less than or equal to .+-.3%, less than or
equal to .+-.2%, less than or equal to .+-.1%, less than or equal
to .+-.0.5%, less than or equal to .+-.0.1%, or less than or equal
to .+-.0.05%. For example, two numerical values can be deemed to be
"substantially" the same or equal if a difference between the
values is less than or equal to .+-.1.0% of an average of the
values, such as less than or equal to .+-.5%, less than or equal to
.+-.4%, less than or equal to .+-.3%, less than or equal to .+-.2%,
less than or equal to .+-.1%, less than or equal to .+-.0.5%, less
than or equal to .+-.0.1%, or less than or equal to .+-.0.05%. For
example, "substantially" parallel can refer to a range of angular
variation relative to 0.degree. that is less than or equal to
.+-.10.degree., such as less than or equal to .+-.5.degree., less
than or equal to .+-.4.degree., less than or equal to
.+-.3.degree., less than or equal to .+-.2.degree., less than or
equal to .+-.1.degree., less than or equal to .+-.0.5.degree., less
than or equal to .+-.0.1.degree., or less than or equal to
.+-.0.05.degree.. For example, "substantially" perpendicular can
refer to a range of angular variation relative to 90.degree. that
is less than or equal to .+-.10.degree., such as less than or equal
to .+-.5.degree., less than or equal to .+-.4.degree., less than or
equal to .+-.3.degree., less than or equal to .+-.2.degree., less
than or equal to .+-.1.degree., less than or equal to
.+-.0.5.degree., less than or equal to .+-.0.1.degree., or less
than or equal to .+-.0.05.degree..
FIG. 1 is a flow chart illustrating a method for manufacturing a
semiconductor device according to various aspects of one or more
embodiments of the present disclosure. The method 100 begins with
operation 110 in which a substrate is received. The method 100
continues with operation 120 in which a first conductive wiring is
formed over the substrate. The method 100 proceeds with operation
130 in which at least one first dielectric layer is formed over the
first conductive wiring. The method 100 continues with operation
140 in which at least one second dielectric layer is formed over
the at least one first dielectric layer, wherein a dielectric
constant of the at least one second dielectric layer is higher than
a dielectric constant of the at least one first dielectric layer.
The method 100 proceeds with operation 150 in which a second
conductive wiring is formed over the at least one second dielectric
layer.
The method 100 is merely an example, and is not intended to limit
the present disclosure beyond what is explicitly recited in the
claims. Additional operations can be provided before, during, and
after the method 100, and some operations described can be
replaced, eliminated, or moved around for additional embodiments of
the method.
FIG. 2A, FIG. 2B and FIG. 2C are schematic views at one of various
operations of manufacturing a semiconductor device according to one
or more embodiments of the present disclosure. As depicted in FIG.
2A, a substrate 10 is received. In some embodiments, the substrate
10 includes a semiconductor substrate. By way of example, the
material of the substrate 10 may include elementary semiconductor
such as silicon or germanium; a compound semiconductor such as
silicon germanium, silicon carbide, gallium arsenic, gallium
phosphide, iridium phosphide or indium arsenide; or combinations
thereof.
In some embodiments, a first low-k dielectric layer 12 is formed
over the substrate 10. In some embodiments, the first low-k
dielectric layer 12 is a low-k dielectric or an extreme low-k (ELK)
dielectric having a dielectric constant equal to or less than about
3. In some embodiments, the material of the first low-k dielectric
layer 12 may include, but is not limited to, a carbon-doped silicon
oxide such as Black Diamond, CORAL or AURORA; a mixture of organic
material and silicon oxide such as HOSP; Nanoglass; aluminum
fluoride; bromine fluoride; combinations thereof; or other low-k or
ELK dielectric materials. In some embodiments, the thickness of the
first low-k dielectric layer 12 is ranging from about 1000
angstroms to about 1500 angstroms, but not limited thereto.
A first conductive wiring 14 is formed in the first low-k
dielectric layer 12. In some embodiments, the first low-k
dielectric layer 12 surrounds an edge of the first conductive
wiring 14, and an upper surface of the first conductive wiring 14
is exposed from the first low-k dielectric layer 12. The first
conductive wiring 14 is formed from conductive material such as
metal or alloy. For example, the material of the first circuit
layer includes copper, but not limited thereto.
As depicted in FIG. 2B, at least one first dielectric layer 16 is
formed over the first low-k dielectric layer 12. The dielectric
constant of the at least one first dielectric layer 16 is higher
than the dielectric constant of the first low-k dielectric layer
12. In some embodiments, the dielectric constant of the at least
one first dielectric layer 16 is ranging from about 3.5 to about
4.5, but not limited thereto. In some embodiments, the material of
the at least one first dielectric layer 16 may include silicon
oxide, silicon carbide, zinc oxide, titanium oxide, tantalum oxide,
combinations thereof or the like. In some embodiments, the
thickness of the at least one first dielectric layer 16 is ranging
from about 50 angstroms to about 600 angstroms. In some
embodiments, the at least one first dielectric layer 16 is a
single-layered structure. In some embodiments, the at least one
first dielectric layer 16 includes a first dielectric 161 and a
second dielectric 162 stacked to each other and formed from
different dielectric materials. In some embodiments, the first
dielectric 161 is configured to improve adhesion with the
underlying first low-k dielectric layer 12, and the second
dielectric 162 is configured to improve adhesion with an overlying
layer. In some embodiments, the thickness of the first dielectric
161 is ranging from about 50 angstroms to about 300 angstroms, and
the thickness of the second dielectric 162 is ranging from about 50
angstroms to about 300 angstroms.
At least one second dielectric layer 18 is formed over the at least
one first dielectric layer 16. In some embodiments, the dielectric
constant of the at least one second dielectric layer 18 is higher
than the dielectric constant of the at least one first dielectric
layer 16. In some embodiments, the dielectric constant of the at
least one second dielectric layer 18 is ranging from about 4 to
about 7, but not limited thereto. In some embodiments, the material
of the at least one second dielectric layer 18 may include silicon
nitride, silicon oxynitride, aluminum oxide, asbestos, chloroform,
tantalum oxide, combination thereof, or the like. In some
embodiments, the at least one second dielectric layer 18 is a
multi-layered dielectric. By way of example, the at least one
second dielectric layer 18 may include oxide/nitride/oxide (ONO).
The at least one second dielectric layer 18 may be single-layered
or multi-layered. In some embodiments, the thickness of the at
least one second dielectric layer 18 is ranging from about 500
angstroms to about 1000 angstroms.
In some embodiments, a conductive via 19 is formed in the at least
one first dielectric layer 16 and the at least one second
dielectric layer 18. The conductive via 19 penetrates through the
at least one first dielectric layer 16 and the at least one second
dielectric layer 18 to electrically connect a portion of the first
conductive wiring 14. The conductive via 19 is formed from
conductive material such as metal or alloy. For example, the
material of the first circuit layer includes copper, but not
limited thereto.
As depicted in FIG. 2C, at least one third dielectric layer 20 is
formed over the at least one second dielectric layer 18. In some
embodiments, the dielectric constant of the at least one third
dielectric layer 20 is lower than the dielectric constant of the at
least one second dielectric layer 18. In some embodiments, the
dielectric constant of the at least one third dielectric layer 20
is ranging from about 3.5 to about 4.5, but not limited thereto. In
some embodiments, the material of the at least one third dielectric
layer 20 may include silicon oxide, silicon carbide, zinc oxide,
titanium oxide, tantalum oxide, combinations thereof or the like.
In some embodiments, the thickness of the at least one third
dielectric layer 20 is ranging from about 50 angstroms to about 600
angstroms. In some embodiments, the at least one third dielectric
layer 20 is a single-layered structure. In some embodiments, the at
least one third dielectric layer 20 includes a first dielectric 201
and a second dielectric 202 stacked to each other and formed from
different dielectric materials. In some embodiments, the first
dielectric 201 is configured to improve adhesion with the
underlying second dielectric layer 18, and the second dielectric
202 is configured to improve adhesion with an overlying layer. In
some embodiments, the thickness of the first dielectric 201 is
ranging from about 50 angstroms to about 300 angstroms, and the
thickness of the second dielectric 202 is ranging from about 50
angstroms to about 300 angstroms.
In some embodiments, a second low-k dielectric layer 22 is formed
over the at least one third dielectric layer 20. The dielectric
constant of the second low-k dielectric layer 22 is lower than the
dielectric constant of the at least one third dielectric layer 20.
In some embodiments, the second low-k dielectric layer 22 is a
low-k dielectric or an extreme low-k dielectric having a dielectric
constant equal to or less than about 3. In some embodiments, the
material of the second low-k dielectric layer 22 may include, but
is not limited to, a carbon-doped silicon oxide such as Black
Diamond, CORAL or AURORA; a mixture of organic material and silicon
oxide such as HOSP; Nanoglass; aluminum fluoride; bromine fluoride;
combinations thereof; or other low-k dielectric materials. In some
embodiments, the thickness of the second low-k dielectric layer 22
is ranging from about 100 angstroms to about 900 angstroms, but not
limited thereto.
In some embodiments, a second conductive wiring 24 is formed over
the at least one second dielectric layer 18. The second conductive
wiring 24 is formed from conductive material such as metal or
alloy. For example, the material of the second conductive wiring 24
includes copper, but not limited thereto. In some embodiments, the
at least one third dielectric layer 20 and the second low-k
dielectric layer 22 surround an edge of the second conductive
wiring 24, and an upper surface of the second conductive wiring 24
is exposed from the second low-k dielectric layer 20. In some
embodiments, a portion of the second conductive wiring 24 is
electrically connected to the first conductive wiring 14 through
the conductive via 19.
In some embodiments, at least one fourth dielectric layer 26 is
formed over the second low-k dielectric layer 22 to form a
semiconductor device 1. The dielectric constant of the at least one
fourth dielectric layer 26 is lower than the dielectric constant of
the second low-k dielectric layer 22. In some embodiments, the
dielectric constant of the at least one fourth dielectric layer 26
is ranging from about 3.5 to about 4.5, but not limited thereto. In
some embodiments, the material of the at least one fourth
dielectric layer 26 may include silicon oxide, silicon carbide,
zinc oxide, titanium oxide, tantalum oxide, combinations thereof or
the like. In some embodiments, the thickness of the at least one
fourth dielectric layer 26 is ranging from about 50 angstroms to
about 600 angstroms. In some embodiments, the at least one fourth
dielectric layer 26 includes a first dielectric 261 and a second
dielectric 262 stacked to each other and formed from different
dielectric materials. In some embodiments, the first dielectric 261
is configured to improve adhesion with the underlying second low-k
dielectric layer 22, and the second dielectric 262 is configured to
improve adhesion with an overlying layer. In sonic embodiments, the
thickness of the first dielectric 261 is ranging from about 50
angstroms to about 300 angstroms, and the thickness of the second
dielectric 262 is ranging from about 50 angstroms to about 300
angstroms.
The semiconductor device of the present disclosure is not limited
to the above-mentioned embodiments, and may have other different
embodiments. To simplify the description and for the convenience of
comparison between each of the embodiments of the present
disclosure, the identical components in each of the following
embodiments are marked with identical numerals. For making it
easier to compare the difference between the embodiments, the
following description will detail the dissimilarities among
different embodiments and the identical features will not be
redundantly described.
FIG. 3 is a schematic cross-sectional view of a semiconductor
device according to one or more embodiments of the present
disclosure. As shown in FIG. 3, different from the semiconductor
device 1 illustrated in FIG. 2C, the at least second dielectric
layer 18 of the semiconductor device 2 includes a first layer 181
and a second layer 182 stacked to each other and formed from
different dielectric materials. In some embodiments, the first
dielectric 181 is configured to improve adhesion with the
underlying first dielectric layer 16, and the second dielectric 182
is configured to improve adhesion with the overlying third
dielectric layer 20.
FIG. 4A, FIG. 4B, FIG. 4C and FIG. 4D are schematic views at one of
various operations of manufacturing an semiconductor device
according to one or more embodiments of the present disclosure. As
depicted in FIG. 4A, a substrate 10 is received. The substrate 10
includes a first region 101 and a second region 102. In some
embodiments, the first region 101 is configured to accommodate an
electronic device such as a memory device, and the second region
102 is configured to accommodate a logic device such as a stacked
conductive wiring device.
In some embodiments, a first low-k dielectric layer 12 is formed
over the substrate 10 in the first region 101 and in the second
region 102. In some embodiments, the first low-k dielectric layer
12 is a low-k dielectric or an extreme low-k dielectric having a
dielectric constant equal to or less than about 3. In some
embodiments, the material of the first low-k dielectric layer 12
may include, but is not limited to, carbon-doped silicon oxide such
as Black Diamond, CORAL or AURORA; mixture of organic material and
silicon oxide such as HOSP; Nanoglass; aluminum fluoride; bromine
fluoride; combinations thereof; or other low-k dielectric
materials. In some embodiments, the thickness of the first low-k
dielectric layer 12 is ranging from about 1000 angstroms to about
1500 angstroms, but not limited thereto.
In some embodiments, a first conductive structure 13 is formed in
the first low-k dielectric layer 12 in the first region 101 and a
first conductive wiring 14 is formed in the first low-k dielectric
layer 12 in the second region 102. In some embodiments, the first
conductive structure 13 and the first conductive wiring 14 can be
formed by the same conductive layer. In some embodiments, the first
low-k dielectric layer 12 surrounds an edge of the first conductive
wiring 14 and an edge of the first conductive structure 13, and an
upper surface of the first conductive wiring 14 and an upper
surface of the first conductive structure 13 are exposed from the
first low-k dielectric layer 12.
As depicted in FIG. 4B, at least one first dielectric layer 16 is
formed over the first low-k dielectric layer 12. The dielectric
constant of the at least one first dielectric layer 16 is higher
than the dielectric constant of the first low-k dielectric layer
12. In some embodiments, the dielectric constant of the at least
one first dielectric layer 16 is ranging from about 3.5 to about
4.5, but not limited thereto. In some embodiments, the material of
the at least one first dielectric layer 16 may include silicon
oxide, silicon carbide, zinc oxide, titanium oxide, tantalum oxide,
combinations thereof, or the like. In some embodiments, the
thickness of the at least one first dielectric layer 16 is ranging
from about 50 angstroms to about 600 angstroms. In some
embodiments, the at least one first dielectric layer 16 includes a
first dielectric 161 and a second dielectric 162 stacked to each
other and formed from different dielectric materials. In some
embodiments, the first dielectric 161 is configured to improve
adhesion with the underlying first low-k dielectric layer 12, and
the second dielectric 162 is configured to improve adhesion with an
overlying layer. In some embodiments, the thickness of the first
dielectric 161 is ranging from about 50 angstroms to about 300
angstroms, and the thickness of the second dielectric 162 is
ranging from about 50 angstroms to about 300 angstroms.
As depicted in FIG. 4C, an electronic device is formed in the first
region 101. In some embodiments, the electronic device includes a
memory device. In some embodiments, a magnetic random access memory
(MRAM) device is exemplarily illustrated as an example. A bottom
electrode via 32 is formed in the first region 101 and electrically
connected to the exposed first conductive structure 13. A bottom
electrode 34 is formed over the bottom electrode via 32. A magnetic
tunnel junction (MTJ) 36 is formed over the bottom electrode 34. A
top electrode 38 is formed over the MTJ 36. In some embodiments, at
least one second dielectric layer 18 is formed over the at least
one first dielectric layer 16. In some embodiments, the at least
one second dielectric layer 18 includes a first layer 181 and a
second layer 182. In some embodiments, the first layer 181 is
configured as a spacer layer surrounding edges of the bottom
electrode 34, the MTJ 36 and the top electrode 38 of the MRAM
device in the first region 101, and extending to the second region
102. In some embodiments, a top electrode via 40 is formed in the
second layer 182 of the at least one second dielectric layer 18 of
the first region 101. In some embodiments, a conductive via 19 is
formed in the at least one first dielectric layer 16 and the at
least one second dielectric layer 18 of the second region 102.
As depicted in FIG. 4D, at least one third dielectric layer 20 is
formed over the at least one second dielectric layer 18. In some
embodiments, the dielectric constant of the at least one third
dielectric layer 20 is lower than the dielectric constant of the at
least one second dielectric layer 18. In some embodiments, the
dielectric constant of the at least one third dielectric layer 20
is ranging from about 3.5 to about 4.5, but not limited thereto. In
some embodiments, the material of the at least one third dielectric
layer 20 may include silicon oxide, silicon carbide, zinc oxide,
titanium oxide, tantalum oxide, combinations thereof or the like.
In some embodiments, the thickness of the at least one third
dielectric layer 20 is ranging from about 50 angstroms to about 600
angstroms. In some embodiments, the at least one third dielectric
layer 20 includes a first dielectric 201 and a second dielectric
202 stacked to each other and formed from different dielectric
materials. In some embodiments, the thickness of the first
dielectric 201 is ranging from about 50 angstroms to about 300
angstroms, and the thickness of the second dielectric 202 is
ranging from about 50 angstroms to about 300 angstroms.
In some embodiments, a second low-k dielectric layer 22 is formed
over the at least one third dielectric layer 20. The dielectric
constant of the second low-k dielectric layer 22 is lower than the
dielectric constant of the at least one third dielectric layer 20.
In some embodiments, the second low-k dielectric layer 22 is a
low-k dielectric or an extreme low-k dielectric having a dielectric
constant equal to or less than about 3. In some embodiments, the
material of the second low-k dielectric layer 22 may include, but
is not limited to, a carbon-doped silicon oxide such as Black
Diamond, CORAL or AURORA; a mixture of organic material and silicon
oxide such as HOSP; Nanoglass; aluminum fluoride; bromine fluoride;
combinations thereof; or other low-k dielectric materials. In some
embodiments, the thickness of the second low-k dielectric layer 22
is ranging from about 100 angstroms to about 900 angstroms, but not
limited thereto.
In some embodiments, a top electrode 42 is formed over the at least
one second dielectric layer 18 of the first region 101, and a
second conductive wiring 24 is formed over the at least one second
dielectric layer 18 of the second region 102. In some embodiments,
the top electrode 42 and the second conductive wiring 24 can be
formed by the same conductive layer. In some embodiments, the at
least one third dielectric layer 20 and the second low-k dielectric
layer 22 surround an edge of the top electrode 42 and an edge of
the second conductive wiring 24, and an upper surface of the top
electrode 42 and an upper surface of the second conductive wiring
24 are exposed from the second low-k dielectric layer 20. In some
embodiments, a portion of the second conductive wiring 24 is
electrically connected to the first conductive wiring 14 through
the conductive via 19.
In some embodiments, at least one fourth dielectric layer 26 is
formed over the second low-k dielectric layer 22 to form a
semiconductor device 3. The dielectric constant of the at least one
fourth dielectric layer 26 is lower than the dielectric constant of
the second low-k dielectric layer 22. In some embodiments, the
dielectric constant of the at least one fourth dielectric layer 26
is ranging from about 3.5 to about 4.5, but not limited thereto. In
some embodiments, the material of the at least one fourth
dielectric layer 26 may include silicon oxide, silicon carbide,
zinc oxide, titanium oxide, tantalum oxide, combinations thereof or
the like. In some embodiments, the thickness of the at least one
fourth dielectric layer 26 is ranging from about 50 angstroms to
about 600 angstroms. In some embodiments, the at least one fourth
dielectric layer 26 includes a first dielectric 261 and a second
dielectric 262 stacked to each other and formed from different
dielectric materials. In some embodiments, the thickness of the
first dielectric 261 is ranging from about 50 angstroms to about
300 angstroms, and the thickness of the second dielectric 262 is
ranging from about 50 angstroms to about 300 angstroms.
In some embodiments, the material and/or thickness of the
dielectric layers such as the first dielectric layer 16 and the
second dielectric layer 18 are configured to meet the capacitance
requirement for a stacked conductive wiring device such as a logic
device in a peripheral region. The dielectric layers such as the
first dielectric layer 16 and the second dielectric layer 18 are
not low-k dielectric layers, and thus can be used as dielectric for
both the electronic device such as a MRAM device and a stacked
conductive wiring device such as a logic device in a peripheral
region. Accordingly, the operations of forming the dielectric
layers for the electronic device such as a MRAM device and a
stacked conductive wiring device such as a logic device in a
peripheral region can be integrated, and thus the method for
manufacturing a semiconductor device can be simplified.
FIG. 5 is a schematic cross-sectional view of a semiconductor
device according to a comparative embodiment of the present
disclosure. As shown in FIG. 5, the semiconductor device 50 of the
comparative embodiment includes a first conductive wiring 14, a
first dielectric layer 54, a second dielectric layer 56, a low-k
dielectric layer 58 and a second conductive wiring 24. The
dielectric constant of the low-k dielectric layer 58 is lower than
3, and the dielectric constant of the first dielectric layer 54 and
the second dielectric layer 56 is ranging from 3.5 to 4.5. The
thickness of the first dielectric layer 54 is between 50 angstroms
and 300 angstroms, and the thickness of the second dielectric layer
56 is between 50 angstroms and 300 angstroms. The thickness of the
low-k dielectric layer 58 under the second conductive wiring 60
i.e. the gap between the lower surface of the second conductive
wiring 60 and the upper surface of the second dielectric layer 56
is between 200 angstroms and 300 angstroms.
FIG. 6 is an equivalent circuit diagram of a stacked conductive
wiring device. As shown in FIG. 6, a capacitance Cab exists between
the first conductive wiring 14 and the second conductive wiring 24
in a perpendicular direction, and two capacitances Cfb exist
between the first conductive wiring 14 and the second conductive
wiring 24 in two oblique directions, respectively. Refer to Table
1. Table 1 shows a simulation of capacitance between the first
conductive wiring and the second conductive wiring.
TABLE-US-00001 TABLE 1 Thickness of Overall second capacitance
dielectric (Cab + 2*Cfb) Cab Cfb ab layer (.ANG.) (fF/um) (fF/um)
(fF/um) Comparative 4.27E-02 1.73E-02 1.27E-02 embodiment
Embodiments 811 4.28E-02 1.62E-02 1.33E-02 of the present 761
4.47E-02 1.71E-02 1.38E-02 disclosure 746 4.54E-02 1.73E-02
1.40E-02 Offset 811 0.2% -6.4% 4.7% 761 4.7% -1.2% 8.7% 746 6.3%
0.0% 10.2%
From the simulation result in Table 1, the dielectric layers such
as the first dielectric layer and the second dielectric layer,
which are not low-k dielectric materials, are able to generate a
capacitance between the first conductive wiring and the second
conductive wiring similar to a low-k dielectric material. The first
dielectric layer and the second dielectric layer not only can meet
the capacitance requirement for a stacked conductive wiring device
such as a logic device in a peripheral region, but also can be
integrated with the inter-metal dielectric (IMD) in the electronic
device such as a MRAM device. Accordingly, the method for
manufacturing a semiconductor device can be simplified, and the
planarization of the semiconductor device is improved.
In one exemplary aspect, a semiconductor device includes a first
conductive wiring, at least one first dielectric layer, at least
one second dielectric layer and a second conductive wiring. The at
least one first dielectric layer is over the first conductive
wiring. The at least one second dielectric layer is over the at
least one first dielectric layer. The second conductive wiring is
over the at least one second dielectric layer. The dielectric
constant of the at least one second dielectric layer is higher than
the dielectric constant of the at least one first dielectric
layer.
In another aspect, a semiconductor device includes at least one
first dielectric layer, at least one second dielectric layer, a
memory device and a stacked conductive wiring device. The at least
one second dielectric layer is formed over the at least one first
dielectric layer. The dielectric constant of the at least one
second dielectric layer is higher than the dielectric constant of
the at least one first dielectric layer. The memory device includes
a first conductive structure under the at least one first
dielectric layer, a second conductive structure over the at least
one second dielectric layer, and a memory cell between the first
conductive structure and the second conductive structure and
through the at least one first dielectric layer and the at least
one second dielectric layer. The stacked conductive wiring device
includes a first conductive wiring under the at least one first
dielectric layer, a second conductive wiring over the at least one
second dielectric layer, and a conductive via between the first
conductive wiring and the second conductive wiring and through the
at least one first dielectric layer and the at least one second
dielectric layer.
In yet another aspect, a method for manufacturing a semiconductor
device is provided. A substrate is received. A first conductive
wiring is formed over the substrate. At least one first dielectric
layer is formed over the first conductive wiring. At least one
second dielectric layer is formed over the at least one first
dielectric layer, wherein a dielectric constant of the at least one
second dielectric layer is higher than a dielectric constant of the
at least one first dielectric layer. A second conductive wiring is
formed over the at least one second dielectric layer.
The foregoing outlines structures of several embodiments so that
those skilled in the art may better understand the aspects of the
present disclosure. Those skilled in the art should appreciate that
they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *