U.S. patent number 10,672,650 [Application Number 15/898,618] was granted by the patent office on 2020-06-02 for via blocking layer.
This patent grant is currently assigned to Intel Corporation. The grantee listed for this patent is INTEL CORPORATION. Invention is credited to Mark T. Bohr, Ruth A. Brain, Florian Gstrein, Rami Hourani, Marie Krysak.
![](/patent/grant/10672650/US10672650-20200602-C00001.png)
![](/patent/grant/10672650/US10672650-20200602-D00000.png)
![](/patent/grant/10672650/US10672650-20200602-D00001.png)
![](/patent/grant/10672650/US10672650-20200602-D00002.png)
![](/patent/grant/10672650/US10672650-20200602-D00003.png)
![](/patent/grant/10672650/US10672650-20200602-D00004.png)
![](/patent/grant/10672650/US10672650-20200602-D00005.png)
![](/patent/grant/10672650/US10672650-20200602-D00006.png)
![](/patent/grant/10672650/US10672650-20200602-D00007.png)
United States Patent |
10,672,650 |
Hourani , et al. |
June 2, 2020 |
Via blocking layer
Abstract
Techniques are disclosed for insulating or electrically
isolating select vias within a given interconnect layer, so a
conductive routing can skip over those select isolated vias to
reach other vias or interconnects in that same layer. Such a via
blocking layer may be selectively implemented in any number of
locations within a given interconnect as needed. Techniques for
forming the via blocking layer are also provided, including a first
methodology that uses a sacrificial passivation layer to facilitate
selective deposition of insulator material that form the via
blocking layer, a second methodology that uses spin-coating of
wet-recessible polymeric formulations to facilitate selective
deposition of insulator material that form the via blocking layer,
and a third methodology that uses spin-coating of nanoparticle
formulations to facilitate selective deposition of insulator
material that form the via blocking layer. Harmful etching
processes typically associated with conformal deposition processes
is avoided.
Inventors: |
Hourani; Rami (Portland,
OR), Krysak; Marie (Portland, OR), Gstrein; Florian
(Portland, OR), Brain; Ruth A. (Portland, OR), Bohr; Mark
T. (Aloha, OR) |
Applicant: |
Name |
City |
State |
Country |
Type |
INTEL CORPORATION |
Santa Clara |
CA |
US |
|
|
Assignee: |
Intel Corporation (Santa Clara,
CA)
|
Family
ID: |
56151201 |
Appl.
No.: |
15/898,618 |
Filed: |
February 18, 2018 |
Prior Publication Data
|
|
|
|
Document
Identifier |
Publication Date |
|
US 20180174893 A1 |
Jun 21, 2018 |
|
Related U.S. Patent Documents
|
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
|
15528427 |
|
9899255 |
|
|
|
PCT/US2014/072252 |
Dec 23, 2014 |
|
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
21/76807 (20130101); H01L 23/3171 (20130101); H01L
23/528 (20130101); H01L 21/76831 (20130101); H01L
23/5226 (20130101); H01L 2221/1063 (20130101); H01L
2221/1031 (20130101) |
Current International
Class: |
H01L
23/48 (20060101); H01L 23/528 (20060101); H01L
29/40 (20060101); H01L 23/52 (20060101); H01L
23/522 (20060101); H01L 23/31 (20060101); H01L
21/768 (20060101) |
Field of
Search: |
;257/758,750,760,622 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
|
|
|
|
|
|
|
2008205019 |
|
Sep 2008 |
|
JP |
|
1020110048194 |
|
May 2011 |
|
KR |
|
200629539 |
|
Aug 2006 |
|
TW |
|
201342529 |
|
Oct 2013 |
|
TW |
|
9857373 |
|
Dec 1998 |
|
WO |
|
2016105402 |
|
Jun 2016 |
|
WO |
|
Other References
International Search Report and Written Opinion received for
PCT/US2014/072252. dated Aug. 28, 2015. 10 pages. cited by
applicant .
International Preliminary Report on Patentability received for
PCT/US2014/072252. dated Jun. 27, 2017. 6 pages. cited by applicant
.
Extended European Search Report received for EP Application No.
14909245.4, dated Jul. 18, 2018. 8 pages. cited by applicant .
Office Action and Search Report received for TW Application No.
104138782, dated Dec. 26, 2018. 16 pages. cited by
applicant.
|
Primary Examiner: Clark; S. V.
Attorney, Agent or Firm: Finch & Maloney PLLC
Parent Case Text
RELATED APPLICATIONS
This patent application is a continuation of U.S. application Ser.
No. 15/528,427 filed May 19, 2017, now U.S. Pat. No. 9,899,255,
which is a U.S. National Stage Application of International
Application No. PCT/US2014/072252 filed Dec. 23, 2014. Each of
these applications is incorporated herein by reference in its
entirety.
Claims
The invention claimed is:
1. An integrated circuit comprising: a first layer including one or
more dielectric materials, the first layer including a first trench
and a second trench, wherein metal material is below the first
trench and metal material is below the second trench; a first
structure in the first trench, the first structure including one or
more metal materials; a second structure in the second trench, the
second structure including one or more metal materials; and a
second layer between the first structure and the metal material
below the first trench, wherein the second layer includes one or
more dielectric materials and electrically isolates the first
structure from the metal material below the first trench.
2. The integrated circuit of claim 1, wherein the second layer is
absent between the second structure and the metal material below
the second trench, such that the second structure and the metal
material below the second trench collectively form a conductive
pathway.
3. The integrated circuit of claim 1, wherein the second layer is
absent between the first structure and the first layer.
4. The integrated circuit of claim 1, wherein the first trench has
a lower portion and an upper portion, a via portion of the first
structure in the lower portion of the first trench and a fill
portion of the first structure in the upper portion of the first
trench.
5. The integrated circuit of claim 1, wherein the second layer
includes silicon and oxygen.
6. The integrated circuit of claim 1, wherein the second layer
includes silicon and nitrogen.
7. The integrated circuit of claim 1, wherein the second layer
includes one or more of hafnium, oxygen, and/or one or more high-k
dielectric materials.
8. The integrated circuit of claim 1, wherein the second layer has
a thickness between the first structure and the metal material
below the first trench in the range of 1 to 5 nanometers.
9. The integrated circuit of claim 1, further comprising a third
structure including one or more metals, the third structure
included in a third trench, the third trench included in the first
layer, wherein the first structure is between the second structure
and the third structure.
10. The integrated circuit of claim 9, wherein the second layer is
absent from the second trench and also absent from the third
trench.
11. The integrated circuit of claim 1, wherein the first structure
and the second structure are electrically connected by a lateral
conductive interconnect structure.
12. The integrated circuit of claim 11, wherein the lateral
conductive interconnect structure is completely above the first
layer.
13. A computing system comprising the integrated circuit of claim
1.
14. An integrated circuit comprising: a first layer including one
or more dielectric materials, the first layer including a first
trench and a second trench, wherein metal material is below the
first trench and metal material is below the second trench; a first
structure in the first trench, the first structure including one or
more metal materials; a second structure in the second trench, the
second structure including one or more metal materials; and an
second layer having a thickness in the range of 0.5 to 10
nanometers between the first structure and the metal material below
the first trench, wherein the second layer includes oxygen.
15. The integrated circuit of claim 14, wherein the thickness of
the second layer is in the range of 1 to 5 nanometers.
16. An integrated circuit comprising: a first layer including one
or more dielectric materials, the first layer including a first
structure and a second structure, wherein the first structure
includes one or more metal materials, and the second structure
includes one or more metal materials; a second layer including one
or more dielectric materials, the second layer including a third
structure above the first structure, the second layer also
including a fourth structure above the second structure, wherein
the third structure includes one or more metal materials, and the
fourth structure includes one or more metal materials; and a third
layer between the third structure and the first structure, thereby
isolating the first structure from the third structure, the third
layer including one or more dielectric materials.
17. The integrated circuit of claim 16, wherein the third layer
includes hafnium and oxygen.
18. The integrated circuit of claim 1, further comprising: an etch
stop layer, wherein the second layer is at least partly in the same
horizontal plane as the etch stop layer, and is different from the
etch stop layer.
19. The integrated circuit of claim 1, wherein the metal material
below the first trench and the metal material below the second
trench are from a same metallization level.
20. The integrated circuit of claim 1, wherein the second layer is
in direct contact with the first structure and in direct contact
with the metal material below the first trench.
Description
BACKGROUND
In the manufacture of integrated circuits, interconnects are
generally formed on a semiconductor substrate using a copper dual
damascene process. Such a process typically begins with a trench
being etched into a dielectric layer and then filled with a
barrier/adhesion layer and a seed layer using a physical vapor
deposition (PVD) sputtering process. An electroplating process is
then used to fill the via and trench with copper metal to form the
interconnect. However, as device dimensions scale down and the
features become narrower, the aspect ratio of the features becomes
more aggressive. Typically, there is a plurality of vias within a
given layer of an integrated circuit structure. Vias in one area of
the structure can be connected to vias or interconnects in other
areas of the structure by routing through one or more subsequent
dielectric layers.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates an integrated circuit structure configured in
accordance with an embodiment of the present disclosure.
FIGS. 2a-c illustrate various process details for forming a via
blocking layer using selective deposition, in accordance with an
embodiment of the present disclosure.
FIGS. 2d-f illustrate alternate cross-sectional views of the
example processes shown in FIGS. 2a-c.
FIGS. 3a-d illustrate various process details for forming a via
blocking layer using spin-coating, in accordance with another
embodiment of the present disclosure.
FIGS. 3e-h illustrate alternate cross-sectional views of the
example processes shown in FIGS. 3a-d.
FIG. 4 illustrates further process details for forming a via
blocking layer using selective deposition, in accordance with
various embodiments of the present disclosure.
FIG. 5 illustrates further process details for forming a via
blocking layer using spin-coating, in accordance with various
embodiments of the present disclosure.
FIG. 6a illustrates the chemical structure of nanoparticles that
can be used in a spin-coating based process for forming a via
blocking layer, in accordance with an embodiment of the present
disclosure.
FIG. 6b illustrates scanning electron microscope (SEM) images of an
actual interconnect structure configured with a via blocking layer
made with nanoparticles, in accordance with an embodiment of the
present disclosure.
FIG. 7 illustrates a computing system implemented with one or more
integrated circuits comprising interconnect structures configured
in accordance with an embodiment of the present disclosure.
DETAILED DESCRIPTION
Techniques are disclosed for insulating or electrically isolating
select vias within a given interconnect layer, so a conductive
routing can skip over those select isolated vias to reach other
vias or interconnects in that same layer. Such a via blocking layer
may be selectively implemented in any number of locations within a
given interconnect as needed. A first embodiment for forming a via
blocking layer includes a selective passivation of trench sidewalls
followed by a selective deposition of insulator material to cover
the metal at the bottom of the trench. The passivation layer is
sacrificial in nature, in that it is removed after the insulator
material is deposited, and can be implemented with any materials
that will block or otherwise inhibit the subsequent deposition of
insulator material from adhering to the trench sidewalls. A second
embodiment for forming a via blocking layer includes the use of
wet-recessible insulator materials that effectively restrict the
presence of those materials to metal at the bottom of the trench.
In one such case, the insulator materials are formed by an
etch-free wet recess of polymeric materials that can be turned into
a smooth dielectric film upon curing, to provide the via blocking
layer. In another such case, the insulator materials for the via
blocking layer are formed by suspending a dielectric nanoparticles
solution in an organic solvent. These particles can be controllably
spin-coated and restricted to the bottom of the trench with desired
thickness and eventually converted to a smooth insulating
dielectric film upon curing, to provide the via blocking layer.
General Overview
As previously explained, in a typical interconnect structure there
is a plurality of vias within each dielectric layer, or so-called
interlay dielectric (ILD) layer. Traditionally, vias in one area of
a given layer can be electrically connected to vias or
interconnects in other areas of that same layer by routing through
one or more subsequent dielectric layers. Such multilayer routing
tends to increase the thickness of the integrated circuit structure
and further involves additional complicated processing steps. To
this end, there is a need for interconnect routing options.
Thus, and in accordance with an embodiment of the present
disclosure, techniques are provided for insulating or electrically
isolating select vias within a given ILD layer, so a conductive
routing can skip over those select isolated vias to reach other
vias or interconnects in that same ILD layer. Normally, such
lateral conductive interconnection is not possible, as unintended
shorting between non-isolated vias would occur. Thus, and as will
be appreciated in light of this disclosure, the techniques provided
herein allow for more routing options within each ILD layer of a
given interconnect structure. The selectively applied insulator
layer can be implemented, for example, as a relatively thin,
patterned electrically insulating dielectric film. The selectively
applied insulating layer can generally be thought of as an inverse
via connect or an anti-via or a via blocking layer. For purposes of
simplicity, going forward, such an insulating layer is referred to
herein as a via blocking layer
The via blocking layer may be implemented in any number of
locations within a given interconnect as needed. For instance, the
via blocking layer can be provided between a given source/drain
(S/D) contact and the local interconnect. In a more general sense,
one or more intervening vias can be electrically isolated with such
a via blocking layer so that two outer vias within that same layer
can be electrically connected by way of a lateral conductive
interconnect that runs through the intervening but electrically
isolated vias. So, even though the intervening via metal may be in
contact with the lateral conductive interconnect, the intervening
vias themselves are electrically open-circuited by operation of the
via blocking layer. Numerous other uses and configurations will be
apparent in light of this disclosure. As will be further
appreciated in light of this disclosure, by allowing vias in a
given ILD layer to be bypassed or skipped over or otherwise
electrically isolated, routing within that ILD layer can be more
orthogonal to the gate direction (OGD), and more parallel to the
gate direction (PGD). Such orthogonality is particularly helpful in
layers above the local interconnect (sometimes referred to as M0
and M1), such as layers M2, M3, and so on, depending on the device
architecture. This in turn allows for more inter-cell (PGD) and
intra-cell (OGD) routing resources and flexibility, and greatly
increases the block density.
As will be further appreciated in light of this disclosure, it
would be very difficult to pattern or deposit a via blocking layer
in a specific location within the interconnect using traditional
techniques such as conformal deposition followed by lithography and
etch steps. For instance, the etch requirements of such traditional
processes are relatively harsh and can damage other components.
Moreover, the conformal deposition on the trench walls increases
the difficulty of subsequent gap fills due to increased aspect
ratio. To this end, and in accordance with an embodiment, a
methodology is provided herein that allows metal at the bottom of a
given trench to be selectively capped or otherwise covered with a
layer of insulator material (or anti-via or inverse via), and
without corrupting the sidewalls of the trench with insulator
material. The metal subsequently provided in the via and upper
trench is therefore electrically isolated from the underlying
metal. Hence, the selectively provisioned insulator material is
referred to as a via blocking layer.
A first embodiment for depositing insulator material in locations
where a via blocking layer is desired includes a selective
passivation of trench sidewalls followed by a selective atomic
layer deposition (ALD) of insulator material into the bottom of the
trench. In some such embodiments, the selective passivation is
selectively applied to the trench sidewalls only. In other
embodiments, the selective passivation is applied to both the
trench sidewalls and the bottom, but then selectively removed from
the trench bottom. In any such cases, the passivation layer is
sacrificial in nature, in that it is removed after the insulator
material is deposited, and can be implemented with any materials
that will block the subsequent deposition of insulator material
from adhering to the trench sidewalls. In accordance with an
example embodiment, the sacrificial passivation layer is achieved
by selectively passivating only the dielectrics using
self-assembled monolayers (SAMs). As will be appreciated in light
of this disclosure, such an approach blocks ALD deposition on the
dielectrics (trench sidewalls) but maintains deposition of a smooth
insulating film on the metal (trench bottom). The insulator
material can be, for instance, a high-k dielectric material, in
some embodiments. Other embodiments may use any suitable insulator
materials, such as silicon dioxide. While the thickness of via
blocking layers formed in this manner (e.g., using a sacrificial
passivation to protect sidewalls and a high-k dielectric for the
via blocking layer) can vary from one embodiment to the next and
will depend on factors such as the dielectric constant of the
insulator material used and the current/voltage profile associated
with the particular node of the interconnect or integrated circuit
being fabricated, in some such example embodiments, the thickness
of the via blocking layer is in the range of 2-3 nm.
A second embodiment for depositing insulator material in locations
where a via blocking layer is desired includes the use of
wet-recessible dielectrics that restrict the presence of that
dielectric material to the bottom of the trench, on the metal to be
insulated or otherwise electrically isolated. In one such case, the
insulator materials are formed by an etch-free wet recess of
polymeric materials that can eventually be turned into a smooth
dielectric film upon curing, to provide the via blocking layer. In
another such case, the insulator materials for the via blocking
layer are formed by suspending metal oxide nanoparticles solution
in an organic solvent. These particles can be controllably
spin-coated and restricted to the bottom of the trench with desired
thickness and eventually converted to a smooth insulating
dielectric film upon curing, to provide the via blocking layer.
While the thickness of via blocking layers formed in this manner
(e.g., using spin-coating of polymeric or nanoparticle formulations
for the via blocking layer) can vary from one embodiment to the
next and will depend on factors such as the insulator material used
and the current/voltage profile associated with that particular
circuit node, in some such example embodiments, the thickness of
the via blocking layer is in the range of 5-10 nm.
Thus, techniques are provided for constructing via blocking layers
in desired locations without the need for conformal deposition
thereby eliminating aggressive etch processes, in accordance with
an embodiment. The techniques also prevent deposition on the trench
sidewalls that results in a higher aspect ratio which in turn makes
metal fill more difficult (such as the case where fill metal
deposition causes pinch-off at top of trench, thereby leaving an
unfilled void in trench bottom). Numerous configurations and
embodiments will be apparent in light of this disclosure.
System Architecture
FIG. 1 illustrates an integrated circuit structure configured in
accordance with an embodiment of the present disclosure. As can be
seen, the structure includes a device layer and a number of ILD
layers each having metal features therein. The structure might be,
for example, a memory such as dynamic random access memory (DRAM).
As can be seen, the device layer of the substrate is configured
with various memory cell components integrated therein, such as
access transistor T and word line WL. Such memory devices typically
include a plurality of bit cells, with each cell generally
including a storage capacitor communicatively coupled to a bitline
by way of an access transistor that is gated by a word line. Other
typical memory components and features not shown can also be
included (e.g., row and column select circuitry, sense circuitry,
power select circuitry, etc).
Each ILD layer includes various metal lines (M1, M1', and M1', M2,
M2', and M2'') and corresponding vias (V0, V0', V0'', V1, V1', and
V1'') formed within the dielectric material. Note that the layout
shown is not intended to implicate any particular feature spacing
or density. Rather, this layout is simply an arbitrary example, and
any number of layout designs can benefit from an embodiment of the
present disclosure, where via blocking layers are formed as
described herein. Each ILD layer in this example structure is
generally isolated or otherwise demarcated from neighboring layers
by an etch stop layer, as is sometimes done. In addition, each
metal line and via of this example embodiment is configured with a
barrier layer to prevent migration of metal into the ILD. Other
embodiments may include fewer or more such layers (e.g., barrier
layers, adhesion layers, and/or liners).
In this particular example embodiment, via V1' is electrically
isolated from the underlying metal line M1' by via blocking layer
101. Hence, via V1' is further designated as isolated/skipped via
105. As explained herein, the blocking layer 101 is an insulator
layer that breaks the electrical contact between a via and its
neighboring conductor so as to allow that particular via to be
skipped over. So, in this example configuration shown in FIG. 1,
the lateral interconnect 103 electrically connects metal line M2 to
metal line M2'' by passing over (or through, as the case may be)
metal line M2', which is electrically isolated by operation of the
isolated/skipped via 105. Note that metal line M2', can still be
filled with metal and processed like all the other metal lines,
even though it will be electrically isolated from the underlying
circuit. Likewise, note that the lateral interconnect 103 may
effectively pass directly through or otherwise be in conductive
contact with metal line M2'.
As will be appreciated, such via blocking layers 101 can be
provided in any part of a given interconnect structure, and the
present disclosure is not intended to be limited to any particular
location. As will be further appreciated, a via blocking layer 101
as provided herein may have any number of shapes and profiles and
need not be planar. Rather, in other embodiments, the via blocking
layer 101 may be non-planar and include vertical sections,
horizontal sections, diagonal sections, and/or rounded or curved
sections. Nor do the via blocking layers 101 need to have a uniform
thickness through its entire length. To this end, via blocking
layers 101 can be formed with any number of profiles, shapes, and
geometries, so long as they provide the electrical
insulating/isolating effect so that the corresponding conductor can
be skipped over without causing a short circuit or faulty operation
of the integrated circuitry. Numerous routing schemes are thus
possible.
FIGS. 2a-f illustrate various process details for forming a via
blocking layer using selective deposition and example resulting
structures, in accordance with an embodiment of the present
disclosure. As will be appreciated in light of this disclosure, the
techniques provided herein can be used to fabricate integrated
circuitry including any type of transistor topology, including
planar topologies and non-planar topologies such as fin-based
transistors, nanowire-based transistors, and nanoribbon-based
transistors. In this example embodiment, assume a fin-based
topology, wherein FIGS. 2a-c show cross-section side views of the
fin region, and FIGS. 2d-f show alternate cross-section side views
of the source/drain region (view rotated 90 degrees from the view
of FIGS. 2a-c). In general, the downward-going (left to right)
diagonal cross-hatched portions are dielectric materials (e.g.,
such as silicon dioxide, silicon nitride, high-k dielectrics, and
low-k dielectrics) and etch stops (e.g., silicon nitride), and the
plain or unshaded portions are conductive materials (e.g., metals
such as silver, gold, tungsten, titanium, and alloys thereof),
unless otherwise indicated. As can be further seen, the
upward-going (left to right) diagonal cross-hatched portions are
semiconductor fins (best shown in FIGS. 2d-f) which can be, for
example, silicon, germanium, SiGe, III-V materials, or some other
suitable substrate/fin material, and the horizontal cross-hatching
represents the via blocker layers (e.g., insulator material such as
silicon dioxide, hafnium oxide, hafnium silicon oxide, or other
suitable dielectric material). As will be further appreciated in
light of this disclosure, the specific details of the example
structures shown are not intended to be limiting in any way and are
only provided to show different contexts in which a blocking layer
can be provided. Indeed, a via blocking layer as provided herein
can be used in any interconnect structure, and the surrounding
integrated circuit structure itself is not particularly relevant.
Hence, description of that surround structure is limited.
As can be seen in FIGS. 2a and 2d, the example process flow
includes patterning the via blocking area using a mask material
(e.g., photoresist, carbon hard mask, or some other suitable making
material). FIGS. 2b and 2e show selective deposition of insulator
material (via blocker) on the metal in the exposed via area, which
can be achieved using a selective passivation layer as will be
discussed in more detail with reference to FIG. 4. This approach
will block ALD deposition on the trench sidewalls but maintain
deposition of a smooth insulating high-k film on the metal, in
accordance with some such embodiments. FIGS. 2c and 2f show the
structure after the mask has been removed, which can be carried
out, for instance, by a dry ash other suitable etch process. The
process may continue with a metal fill process that effectively
creates a lateral conductive interconnect running across the top of
the structure thereby connective the first and third via shown,
wherein the via blocking layer causes the middle via to be skipped
over. Other features, such as barrier layers and liners, may also
be provided in the trench
Note in this embodiment, the via blocker layer is planar. In other
embodiments, the via blocking layer may be non-planar. In one such
case, the via blocking layer be configured as shown, but also be
deposited over the two middle intervening ILD columns, shown in
FIGS. 2e and 2f As previously explained, the via blocking layer can
be implemented in any form needed to electrically isolate one or
more vias from other vias in that same layer of the interconnect
structure.
FIGS. 3a-d illustrate various process details for forming a via
blocking layer using spin-coating, in accordance with another
embodiment of the present disclosure. The previous relevant
discussion with respect to FIGS. 2a-f regarding the structure and
materials and nature of the via blocking layer is equally
applicable here, as will be appreciated. FIGS. 3a and 3e show the
resulting example structure after a via blocker material (e.g.,
high-k polymeric material, or nanoparticle laden formulation, or
other suitable spin-on insulator coatings) is spin-coated onto the
structure. FIGS. 3b and 3f show the example resulting structure
after a wet recess is carried out to remove excess via blocker
material. Note in this example case, the via blocker layer passes
over intervening dielectric materials in addition to the metal vias
being electrically isolated (FIG. 3f).
FIGS. 3c and 3g show the example resulting structure after
patterning the mask for the local interconnect (or other feature of
the semiconductor), and FIGS. 3d and 3h down the resulting
structure after the wet strip process to remove the excess via
blocker material, in accordance with an embodiment. In this example
case, note the mask includes an etch stop layer to further assist
in the forming process. In particular, the strip rate of the etch
stop materials is slower than the strip rate of the via blocking
material, with respect to the wet strip chemistry. Further details
of example spin-on forming processes for making via blocking layers
will be provided in turn with respect to FIG. 5.
Methodology
FIG. 4 illustrates further process details for forming a via
blocking layer using selective deposition, in accordance with
various embodiments of the present disclosure. As can be seen, two
example process flows are provided (A and B). In general, each
process flow involves the use of a sacrificial passivation layer
that prevents or otherwise inhibits the subsequently deposited
insulator material used for the via blocking layer from adhering to
the trench sidewalls. In this way, the sacrificial passivation
layer allows for the selective deposition of the via blocking
insulator material. As will be appreciated, FIG. 4 has been
simplified to only show a trench formed in an ILD layer, with metal
to be covered by the via blocking layer underlying the trench.
Numerous other configurations will be apparent. For instance, the
trench may have a lower via portion and a wider upper line portion.
Also, while the metal is shown below the trench, in other
embodiments the metal may actually be within the trench. Further
note that the trench configuration may vary. For instance, in
another embodiment the trench is a dual damascene trench having a
lower via portion containing the lower metal and an upper trench
portion containing the fill metal (e.g., metal line or other
conductive feature). In such embodiments, note that the lower metal
may be inside the lower portion of the dual damascene trench or
below the lower portion of that trench. Also, the trench may
further include one or more barrier layers or liners. The
techniques provided herein can be used with any such
configurations.
Process Flow A:
Process flow A includes selective passivation at 401, wherein a
sacrificial passivation layer is provided only on the trench
sidewalls and not on the trench bottom. Thus, the metal at the
bottom of the trench is left uncovered by the sacrificial
passivation layer. The process flow continues at 403, which
includes a selective deposition of insulator material which will
form the via blocking layer 101. In some example embodiments, the
selectively deposited insulator material can be, for example, any
suitable oxide such as SiO.sub.2 or high-k gate dielectric
materials. The process flow A continues at 405, with passivation
removal.
Process Flow B:
Process flow B includes non-selective passivation of the trench at
402, wherein a sacrificial passivation layer is provided on both
the trench sidewalls and on the trench bottom. The process flow
continues at 404, which includes a selective removal of the
passivation layer from the trench bottom, which can be
accomplished, for instance, by way of a directional (anisotropic)
etch. The process flow continues at 406, which includes a selective
deposition of insulator material which will form the via blocking
layer 101. In some example embodiments, the selectively deposited
insulator material can be, for example, any suitable oxide such as
SiO.sub.2 or high-k gate dielectric materials. The process flow A
continues at 408, with passivation removal.
Examples of high-k dielectric materials that can be used for the
insulator material deposited at 403 and 406 include, for instance,
hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum
aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum
oxide, titanium oxide, barium strontium titanium oxide, barium
titanium oxide, strontium titanium oxide, yttrium oxide, aluminum
oxide, lead scandium tantalum oxide, and lead zinc niobate. In some
embodiments, an annealing process may be carried out on the via
blocking layer 101 to improve its quality when a high-k material is
used. In general, the thickness of the via blocking layer 101
should be sufficient to electrically isolate the targeted via from
its adjacent metal interconnect feature.
As will be appreciated in light of this disclosure, selective
deposition at 403 and 406 can be engineered by first depositing the
sacrificial blocking layer at 401 or 402. In one embodiment, the
sacrificial passivation layer is implemented with a self-assembled
monolayer (SAM) on the trench surfaces where no high-k or other
insulator film (via blocker) is desired. SAMs that attach
preferentially to dielectric surfaces (such as the trench
sidewalls) can be made, for example, from silane chemistries such
as chloro-, alkoxy-, and amino silanes with long alkane (octadecyl
trichlorosilane, trimethoxy(octadecyl)silane, etc) or fluorocarbon
(triethoxy(3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,10-heptadecafluorodecyl,
1-(3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,10-heptadecafluorodecyl)-N,N,N',N',N-
'',N''-hexamethylsilanetriamine, etc) silane, chains. As will be
appreciated, carbon chain length can vary from 10-20 carbons, in
accordance with an embodiment. Other suitable sacrificial
passivation materials that allow for the selective deposition of
the via blocking material in the trench bottom will be apparent in
light of this disclosure.
In one specific example embodiment, the passivant molecules form a
blanket monolayer that blocks all but the metal surface to be
blocked/isolated. Other thicknesses may be used as well, depending
on the material used for the passivation layer. If the selectivity
of the passivation layer is insufficient due to, for example, the
possible reactivity of the passivant on both the metal and
dielectric surfaces, then at least one of thermal annealing (e.g.,
450.degree. C. for 30 minutes) and wet etch (e.g., 50:1 HF:H.sub.2O
for 1 minute) can be used to completely remove any passivant that
reacted on the metal surface while maintaining passivation on the
dielectric part (trench sidewalls).
After the insulator material for the via blocking layer 101 is
deposited, removal of the passivation layer at 405 and 408 can be
carried out, for example, by at least one of thermal treatments at
temperatures higher than 450.degree. C. and by other wet etch
conditions. For instance, in one example embodiment, the
sacrificial passivation layer is implemented with self-assembled
monolayers and can be removed by any wet method, such as with an
oxidizing or reducing agent to break the covalent bond between
substrate and monolayer, by etching away a very thin layer of the
substrate thereby releasing the molecules. The resulting via
blocking layer 101 can have a thickness in the range of, for
example, 0.5-10 nm, or 1-5 nm, or 2-3 nm, in accordance with a few
example embodiments.
There are a number of low temperature ALD processes suitable for
depositing high-k materials such as HfO.sub.2 or ZrO.sub.2
compatible with a SAM-based passivation layer blocking. For
example, tetrakis(dimethylamido)hafnium will react with water at
250.degree. C. in an ALD process to produce HfO.sub.2 films with
good electrical/leakage properties, as further indicated by
Equation 1 below.
##STR00001##
Once the via blocking layer 101 is provided, a subsequent metal
fill deposition process can be performed to fill in the
interconnect layer, wherein the via blocking layer 101 allows that
trench to be electrically isolated and skipped over as previously
explained. Other processes for that layer will be apparent in light
of this disclosure, such as CMP-based planarization and deposition
of an etch stop layer.
FIG. 5 illustrates further process details for forming a via
blocking layer using spin-coating, in accordance with various
embodiments of the present disclosure. As can be seen, two example
process flows are provided (A and B). In general, each process flow
involves the use of a spin-coating process for depositing insulator
material used for the via blocking layer. As will be appreciated,
FIG. 5 has been simplified to only show a trench formed in an ILD
layer, with metal to be covered by the via blocking layer
underlying the trench. Numerous other configurations will be
apparent. For instance, the trench may have a lower via portion and
a wider upper line portion. Also, while the metal is shown below
the trench, in other embodiments the metal may actually be within
the trench. Also, the trench may further include one or more
barrier layers or liners. The techniques provided herein can be
used with any such configurations.
Process Flow A:
Process flow A includes spin-coating of a nanoparticle formulation
at 501, thereby providing a deposition of nanoparticle-laden
insulator material which will form the via blocking layer 101. In
some example embodiments, the spin-on nanoparticles formulation
comprises, for instance, HfOx, ZrOx, TiOx, WOx, TaOx, and CeOx, to
name a few examples. In one specific example case, hafnium oxide
nanoparticles are coated in a mixture of methacrylate and benzoate
ligands to promote solubility in common organic spinning solvents.
FIG. 6a illustrates the chemical structure of such Hf-BZA
nanoparticles. As will be appreciated, the particle size can vary
from one embodiment to the next (e.g., 1-10 nm), but in one example
case the diameter of the nanoparticles is in the range of 1-2 nm so
as to enable good gapfill of narrow trenches. In one specific
example such process flow, a dilute nanoparticle solution in
propylene glycol monomethyl ether acetate or so-called PGMEA (e.g.,
1.6 wt % particles in PGMEA) is dispensed onto a wafer and puddled
for .about.5 sec, then spun off, so as to allow the nanoparticles
to settle into the bottom of the trench. The example process flow A
further continues with a low temperature soft bake at 503 to drive
off excess solvent (e.g., 110.degree. C. for 60 seconds) of the
nanoparticle solution, followed by a high temperature hard bake at
505 to remove the organic ligands and thermally cross-link the
hafnium oxide core (e.g., 400-450.degree. C., for 1-2 hours) to
form the via blocking layer 101.
Process Flow B:
Process flow B includes spin-coating of a wet-recessible polymeric
formulation at 502, thereby providing a deposition of polymer-laden
insulator material which will form the via blocking layer 101. In
some example embodiments, the spin-on polymeric formulation
comprises, for instance, HfOx, ZrOx, TiOx, WOx, TaOx, and CeOx. As
can be further seen, the polymer-laden insulator material deposited
into the existing trenches by way of spin-coating may form an
overburden. The process flow continues with a soft bake at 504 to
remove excess solvent (e.g., 80-250.degree. C., for 1-30 minutes),
and may further include planarization to provide a desired degree
of thickness uniformity. The process flow continues with a wet
recess at 506 to recess the polymer-laden insulator material to a
desired thickness. In one example embodiment, for instance, a
controlled dissolution of the material in an organic solvent (e.g.,
PGMEA, tetramethylammonium hydroxide or so-called TMAH, ethyl
lactate, toluene, methyl ethyl ketone, butyl acetate, acetone,
methoxybenzene, or other non-polar solvents) is used to recess the
polymer-laden insulator material to a desired thickness. Finally,
the wafer is subject to a high-temperature cure (e.g.,
400-450.degree. C., for 1-2 hours) to densify and cross-link the
remaining material.
The resulting via blocking layer 101 resulting from such
spin-coating based process flows can have a thickness in the range
of, for example, 2-15 nm, or 4-12 nm, or 5-10 nm, in accordance
with a few example embodiments. FIG. 6b illustrates scanning
electron microscope (SEM) images of an actual interconnect
structure configured with a via blocking layer 101 made with
spin-coated nanoparticles in accordance with the process flow A of
FIG. 5, in accordance with an embodiment. This example blocking
layer 101 is implemented with HfO.sub.2 film with
nanoparticles.
Just as explained with reference to FIG. 4, once the via blocking
layer 101 shown in FIG. 5 is provided, a subsequent metal fill
deposition process can be performed to fill in the interconnect
layer, wherein the via blocking layer 101 allows that trench to be
electrically isolated and skipped over as previously explained.
Other processes for that layer will be apparent in light of this
disclosure, such as deposition of barrier layers, CMP-based
planarization, and deposition of an etch stop layer.
Example System
FIG. 7 illustrates a computing system 700 implemented with one or
more integrated circuits comprising interconnect structures
configured and/or otherwise fabricated in accordance with an
example embodiment of the present disclosure. As can be seen, the
computing system 700 houses a motherboard 702. The motherboard 702
may include a number of components, including but not limited to a
processor 704 and at least one communication chip 706, each of
which can be physically and electrically coupled to the motherboard
702, or otherwise integrated therein. As will be appreciated, the
motherboard 702 may be, for example, any printed circuit board,
whether a main board or a daughterboard mounted on a main board or
the only board of system 700, etc. Depending on its applications,
computing system 700 may include one or more other components that
may or may not be physically and electrically coupled to the
motherboard 702. These other components may include, but are not
limited to, volatile memory (e.g., DRAM), non-volatile memory
(e.g., ROM), a graphics processor, a digital signal processor, a
crypto processor, a chipset, an antenna, a display, a touchscreen
display, a touchscreen controller, a battery, an audio codec, a
video codec, a power amplifier, a global positioning system (GPS)
device, a compass, an accelerometer, a gyroscope, a speaker, a
camera, and a mass storage device (such as hard disk drive, compact
disk (CD), digital versatile disk (DVD), and so forth). Any of the
components included in computing system 700 may include one or more
integrated circuit structures configured with one or more
conductive interconnect features as variously described herein,
such as an interconnect having one or more isolated/skipped vias
105 by virtue of corresponding via blocking layers 101. These
integrated circuit structures can be used, for instance, to
implement an on-board processor cache or memory array or other
circuit feature that includes interconnects. In some embodiments,
multiple functions can be integrated into one or more chips (e.g.,
for instance, note that the communication chip 706 can be part of
or otherwise integrated into the processor 704).
The communication chip 706 enables wireless communications for the
transfer of data to and from the computing system 700. The term
"wireless" and its derivatives may be used to describe circuits,
devices, systems, methods, techniques, communications channels,
etc., that may communicate data through the use of modulated
electromagnetic radiation through a non-solid medium. The term does
not imply that the associated devices do not contain any wires,
although in some embodiments they might not. The communication chip
706 may implement any of a number of wireless standards or
protocols, including but not limited to Wi-Fi (IEEE 802.11 family),
WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE),
Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT,
Bluetooth, derivatives thereof, as well as any other wireless
protocols that are designated as 3G, 4G, 5G, and beyond. The
computing system 700 may include a plurality of communication chips
706. For instance, a first communication chip 706 may be dedicated
to shorter range wireless communications such as Wi-Fi and
Bluetooth and a second communication chip 706 may be dedicated to
longer range wireless communications such as GPS, EDGE, GPRS, CDMA,
WiMAX, LTE, Ev-DO, and others.
The processor 704 of the computing system 700 includes an
integrated circuit die packaged within the processor 704. In some
embodiments of the present disclosure, the integrated circuit die
of the processor includes onboard memory circuitry that is
implemented with one or more integrated circuit structures
configured with one or more conductive interconnect features as
variously described herein. The term "processor" may refer to any
device or portion of a device that processes, for instance,
electronic data from registers and/or memory to transform that
electronic data into other electronic data that may be stored in
registers and/or memory.
The communication chip 706 may also include an integrated circuit
die packaged within the communication chip 706. In accordance with
some such example embodiments, the integrated circuit die of the
communication chip includes one or more devices implemented with
one or more integrated circuit structures formed as variously
described herein (e.g., interconnect having one or more via
blocking layers). As will be appreciated in light of this
disclosure, note that multi-standard wireless capability may be
integrated directly into the processor 704 (e.g., where
functionality of any chips 706 is integrated into processor 704,
rather than having separate communication chips). Further note that
processor 704 may be a chip set having such wireless capability. In
short, any number of processors 704 and/or communication chips 706
can be used. Likewise, any one chip or chip set can have multiple
functions integrated therein.
In various implementations, the computing system 700 may be a
laptop, a netbook, a notebook, a smartphone, a tablet, a personal
digital assistant (PDA), an ultra-mobile PC, a mobile phone, a
desktop computer, a server, a printer, a scanner, a monitor, a
set-top box, an entertainment control unit, a digital camera, a
portable music player, or a digital video recorder. In further
implementations, the system 700 may be any other electronic device
that processes data or employs integrated circuit features
configured with one or more conductive interconnect features, as
variously described herein.
Further Example Embodiments
The following examples pertain to further embodiments, from which
numerous permutations and configurations will be apparent.
Example 1 is an integrated circuit device. The device includes an
interlayer dielectric (ILD) layer having a plurality of trenches
formed therein, each trench having sidewalls and a bottom defined
by a lower metal. The device further includes an insulator layer on
the bottom of a middle trench included in the plurality, the
insulator layer covering the lower metal defining the bottom of the
middle trench. The device further includes a fill metal in each of
the trenches, the fill metal in electrical contact with the lower
metal defining the bottom of each trench, except that the lower
metal defining the bottom of the middle trench is isolated from the
fill metal by the insulator layer.
Example 2 includes the subject matter of Example 1, wherein the
plurality of trenches includes three trenches, including a left
trench, the middle trench, and a right trench, the device further
comprising a lateral interconnect that electrically connects the
fill metal of the left, middle, and right trenches.
Example 3 includes the subject matter of Example 1 or 2, wherein
the insulator layer comprises a high-k dielectric.
Example 4 includes the subject matter of Example 3, wherein the
insulator layer comprises at least one of hafnium oxide, hafnium
silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium
oxide, zirconium silicon oxide, tantalum oxide, titanium oxide,
barium strontium titanium oxide, barium titanium oxide, strontium
titanium oxide, yttrium oxide, aluminum oxide, lead scandium
tantalum oxide, and lead zinc niobate.
Example 5 includes the subject matter of any of the previous
Examples, and further includes at least one of: another ILD layer
over the fill metal; a passivation layer over the fill metal; an
electronic device layer below the ILD layer; an electronic device
layer over the fill metal; and a contact layer over the fill
metal.
Example 6 includes the subject matter of any of the previous
Examples, wherein the insulator layer has a thickness in the range
of 0.5 nm to 10 nm.
Example 7 includes the subject matter of any of the previous
Examples, wherein the thickness of the insulator layer is uniform,
such that the thinnest part of the insulator layer is within 10% of
the thickest part of that layer, or within 5% of the thickest part
of that layer, or within 2% of the thickest part of that layer.
Example 8 includes the subject matter of any of the previous
Examples, and further includes a barrier layer between the trench
sidewalls and the fill metal. Other trench layers may also be
provided, such as liners, adhesion layers, and seed layers.
Example 9 includes the subject matter of any of the previous
Examples, wherein the trench is a dual damascene trench having a
lower via portion containing the lower metal and an upper trench
portion containing the fill metal. Note that the lower metal may be
in the trench or below the trench.
Example 10 is a mobile computing system comprising the device of
any of the previous Examples.
Example 11 includes the subject matter of Example 10, wherein the
system is a smartphone or tablet computer. Other mobile computing
devices will be apparent, such as wearable computing systems (e.g.,
glasses, bracelets, watches, fabrics). In still other embodiments,
the computing system need not be mobile and may be, for instance, a
work station or set-top box or desktop computer or game console. In
a more general sense, the interconnect structures provided herein
can be used in any electronic device of any kind.
Example 12 is a memory comprising the device of any of Examples
1-9. The memory may be volatile or non-volatile memory (e.g., RAM,
DRAM, SRAM, Flash, ROM, PROM, EPROM, to name a few examples), and
may be a standalone memory device or an integrated memory device
(such as on-board cache or embedded memory).
Example 13 is a processor comprising the device of any of Examples
1-9. The processor may be, for example, a central processing unit,
graphics processor, co-processor, video processor, or
microcontroller. Any such processing environments can employ the
various interconnect structures provided herein.
Example 14 is communication chip comprising the device of any of
Examples 1-9. The communication chip may be, for example, a Wi-Fi
chip or chip set or a network interface chip for wired or wireless
communication links. Any such wired or wireless communication
devices can employ the various interconnect structures provided
herein.
Example 15 is a method for forming an interconnect structure. The
method includes forming an interlayer dielectric (ILD) layer having
a plurality of trenches formed therein, each trench having
sidewalls and a bottom defined by a lower metal. The method further
includes forming an insulator layer on the bottom of a middle
trench included in the plurality, the insulator layer covering the
lower metal defining the bottom of the middle trench. The method
further includes depositing a fill metal in each of the trenches,
the fill metal in electrical contact with the lower metal defining
the bottom of each trench, except the lower metal defining the
bottom of the middle trench is isolated from the fill metal by the
insulator layer.
Example 16 includes the subject matter of Example 15, wherein
forming the insulator layer comprises: depositing a sacrificial
passivation layer that inhibits subsequently deposited insulator
material from adhering to the trench sidewalls; and depositing the
insulator material into the trench to cover the lower metal
defining the bottom of the middle trench.
Example 17 includes the subject matter of Example 16, wherein
depositing the insulator material comprises atomic layer
deposition.
Example 18 includes the subject matter of Example 16 or 17, wherein
the sacrificial passivation layer is deposited substantially on the
trench sidewalls and not on the lower metal defining the bottom of
the middle trench thereby leaving the lower metal substantially
uncovered by the sacrificial passivation layer.
Example 19 includes the subject matter of Example 16 or 17, wherein
the sacrificial passivation layer is deposited on both the trench
sidewalls and on the lower metal defining the bottom of the middle
trench. In one such case, the process further includes: selective
removal of the passivation layer from the lower metal defining the
bottom of the middle trench.
Example 20 includes the subject matter of any of Examples 16-19,
wherein depositing the sacrificial passivation layer further
comprises performing at least one of a thermal anneal and wet etch
to remove any passivant that reacted on the lower metal.
Example 21 includes the subject matter of any of Examples 16-20,
wherein the sacrificial passivation layer is implemented with a
self-assembled monolayer (SAM).
Example 22 includes the subject matter of any of Examples 16-21,
and further includes removing the sacrificial passivation
layer.
Example 23 includes the subject matter of Example 22, wherein
removing the sacrificial passivation layer includes at least one of
thermal treatments and wet etch.
Example 24 includes the subject matter of Example 15, wherein
forming the insulator layer comprises spin-coating a nanoparticle
formulation.
Example 25 includes the subject matter of Example 24, wherein the
nanoparticle formulation comprises hafnium oxide nanoparticles
coated in a mixture of methacrylate and benzoate ligands.
Example 26 includes the subject matter of Example 24 or 25, wherein
the nanoparticle formulation comprises nanoparticles having a
diameter in the range of 1-2 nm.
Example 27 includes the subject matter of any of Examples 24-26,
and further includes a soft bake to drive off excess solvent.
Example 28 includes the subject matter of Example 27, and further
includes a hard bake to at least one of remove organic ligands and
thermally cross-link the insulator layer.
Example 29 includes the subject matter of Example 15, wherein
forming the insulator layer comprises spin-coating of a
wet-recessible polymeric formulation.
Example 30 includes the subject matter of Example 29, and further
includes a soft bake to drive off excess solvent.
Example 31 includes the subject matter of Example 30, and further
includes planarization of the wet-recessible polymeric
formulation.
Example 32 includes the subject matter of Example 30 or 31, and
further includes a wet recess to recess the wet-recessible
polymeric formulation to a desired thickness.
Example 33 includes the subject matter of any of Examples 30-32,
and further includes a hard bake to at least one of densify and
cross-link the insulator layer.
Example 34 includes the subject matter of any of Examples 15-33,
wherein the plurality of trenches includes three trenches,
including a left trench, the middle trench, and a right trench, the
method further comprising forming a lateral interconnect that
electrically connects the fill metal of the left, middle, and right
trenches.
Example 35 is an integrated circuit device. The device includes an
interlayer dielectric (ILD) layer having a plurality of trenches
formed therein, each trench having sidewalls and a bottom defined
by a lower metal, and wherein the plurality of trenches includes
three trenches, including a left trench, the middle trench, and a
right trench. The device further includes an insulator layer on the
bottom of a middle trench included in the plurality, the insulator
layer covering the lower metal defining the bottom of the middle
trench, wherein the insulator layer comprises a high-k dielectric
and has a thickness in the range of 0.5 nm to 10 nm. The device
further includes a fill metal in each of the trenches, the fill
metal in electrical contact with the lower metal defining the
bottom of each trench, except that the lower metal defining the
bottom of the middle trench is isolated from the fill metal by the
insulator layer. The device further includes a lateral interconnect
that electrically connects the fill metal of the left, middle, and
right trenches.
Example 36 includes the subject matter of Example 35, and further
includes at least one of: another ILD layer over the fill metal; a
passivation layer over the fill metal; an electronic device layer
below the ILD layer; an electronic device layer over the fill
metal; and a contact layer over the fill metal.
Example 37 includes the subject matter of Example 35 or 36, wherein
the insulator layer has a thickness in the range of 1 nm to 5
nm.
Example 38 includes the subject matter of any of Examples 35-37,
wherein the thickness of the insulator layer is uniform, such that
the thinnest part of the insulator layer is within 5% of the
thickest part of that layer.
Example 39 includes the subject matter of any of Examples 35-38,
and further includes a barrier layer between the trench sidewalls
and the fill metal.
Example 40 includes the subject matter of any of Examples 35-39,
wherein the trench is a dual damascene trench having a lower via
portion containing the lower metal and an upper trench portion
containing the fill metal. Note that the lower metal may be in the
trench or below the trench.
Example 41 is a mobile computing system comprising the device of
any of Examples 35-40.
Example 42 includes the subject matter of Example 41, wherein the
system is a smartphone or tablet computer. Other mobile computing
devices will be apparent, such as wearable computing systems (e.g.,
glasses, bracelets, watches, fabrics). In still other embodiments,
the computing system need not be mobile and may be, for instance, a
work station or set-top box or desktop computer or game console. In
a more general sense, the interconnect structures provided herein
can be used in any electronic device of any kind.
Example 43 is a memory comprising the device of any of Examples
35-40. The memory may be volatile or non-volatile memory (e.g.,
RAM, DRAM, SRAM, Flash, ROM, PROM, EPROM, to name a few examples),
and may be a standalone memory device or an integrated memory
device (such as on-board cache or embedded memory).
Example 44 is a processor comprising the device of any of Examples
35-40. The processor may be, for example, a central processing
unit, graphics processor, co-processor, video processor, or
microcontroller. Any such processing environments can employ the
various interconnect structures provided herein.
Example 45 is communication chip comprising the device of any of
Examples 35-40. The communication chip may be, for example, a Wi-Fi
chip or chip set or a network interface chip for wired or wireless
communication links. Any such wired or wireless communication
devices can employ the various interconnect structures provided
herein.
The foregoing description of example embodiments has been presented
for the purposes of illustration and description. It is not
intended to be exhaustive or to limit the present disclosure to the
precise forms disclosed. Many modifications and variations are
possible in light of this disclosure. It is intended that the scope
of the present disclosure be limited not by this detailed
description, but rather by the claims appended hereto. Future filed
applications claiming priority to this application may claim the
disclosed subject matter in a different manner, and may generally
include any set of one or more limitations as variously disclosed
or otherwise demonstrated herein.
* * * * *