| Patent | Date |
|---|
Semiconductor device having tipless epitaxial source/drain regions
Grant 11,437,514 - Bohr September 6, 2 | 2022-09-06 |
Multi Version Library Cell Handling And Integrated Circuit Structures Fabricated Therefrom
App 20220149075 - KUMAR; Ranjith ; et al. | 2022-05-12 |
Distributed Semiconductor Die And Package Architecture
App 20220139896 - GOMES; Wilfred ; et al. | 2022-05-05 |
Multi version library cell handling and integrated circuit structures fabricated therefrom
Grant 11,271,010 - Kumar , et al. March 8, 2 | 2022-03-08 |
Distributed semiconductor die and package architecture
Grant 11,257,804 - Gomes , et al. February 22, 2 | 2022-02-22 |
Integrated Circuit Device With Crenellated Metal Trace Layout
App 20220028779 - Morrow; Patrick ; et al. | 2022-01-27 |
Techniques for die stacking and associated configurations
Grant 11,222,863 - Hua , et al. January 11, 2 | 2022-01-11 |
Functionally Redundant Semiconductor Dies And Package
App 20210375825 - GOMES; Wilfred ; et al. | 2021-12-02 |
Integrated circuit device with crenellated metal trace layout
Grant 11,139,241 - Morrow , et al. October 5, 2 | 2021-10-05 |
Functionally redundant semiconductor dies and package
Grant 11,127,712 - Gomes , et al. September 21, 2 | 2021-09-21 |
Through Gate Fin Isolation
App 20210233908 - BOHR; Mark T. ; et al. | 2021-07-29 |
Hyperchip
App 20210225808 - BOHR; Mark T. ; et al. | 2021-07-22 |
Power shared cell architecture
Grant 11,068,640 - Kumar , et al. July 20, 2 | 2021-07-20 |
Techniques For Die Stacking And Associated Configurations
App 20210193613 - HUA; Fay ; et al. | 2021-06-24 |
Multiple reticle field semiconductor devices
Grant 11,043,459 - Burton , et al. June 22, 2 | 2021-06-22 |
Through gate fin isolation
Grant 11,037,923 - Bohr , et al. June 15, 2 | 2021-06-15 |
Hyperchip
Grant 11,024,601 - Bohr , et al. June 1, 2 | 2021-06-01 |
Self-aligned Contacts
App 20210134673 - BOHR; Mark T. ; et al. | 2021-05-06 |
Integrated Circuit Device With Back-side Inerconnection To Deep Source/drain Semiconductor
App 20210111115 - Morrow; Patrick ; et al. | 2021-04-15 |
Self-aligned contacts
Grant 10,930,557 - Bohr , et al. February 23, 2 | 2021-02-23 |
Metal on both sides with power distributed through the silicon
Grant 10,892,215 - Nelson , et al. January 12, 2 | 2021-01-12 |
Integrated circuit device with back-side interconnection to deep source/drain semiconductor
Grant 10,886,217 - Morrow , et al. January 5, 2 | 2021-01-05 |
Multi Version Library Cell Handling And Integrated Circuit Structures Fabricated Therefrom
App 20200357823 - KUMAR; Ranjith ; et al. | 2020-11-12 |
Semiconductor Device Having Tipless Epitaxial Source/drain Regions
App 20200335626 - Bohr; Mark T. | 2020-10-22 |
Distributed Semiconductor Die And Package Architecture
App 20200312833 - GOMES; WILFRED ; et al. | 2020-10-01 |
Gate-all-around Integrated Circuit Structures Having Source Or Drain Structures With Epitaxial Nubs
App 20200303502 - BOMBERGER; Cory ; et al. | 2020-09-24 |
Semiconductor device having tipless epitaxial source/drain regions
Grant 10,770,587 - Bohr Sep | 2020-09-08 |
Power Shared Cell Architecture
App 20200279069 - KUMAR; Ranjith ; et al. | 2020-09-03 |
Self-aligned Contacts
App 20200251387 - Kind Code | 2020-08-06 |
Distributed semiconductor die and package architecture
Grant 10,685,947 - Gomes , et al. | 2020-06-16 |
Via blocking layer
Grant 10,672,650 - Hourani , et al. | 2020-06-02 |
Active Silicon Bridge
App 20200144186 - THOMAS; Thomas P. ; et al. | 2020-05-07 |
Self-aligned contacts
Grant 10,629,483 - Bohr , et al. | 2020-04-21 |
Multiple Reticle Field Semiconductor Devices
App 20200066651 - Burton; Edward A. ; et al. | 2020-02-27 |
Hyperchip
App 20200066679 - BOHR; Mark T. ; et al. | 2020-02-27 |
Semiconductor Device Having Tipless Epitaxial Source/drain Regions
App 20200058791 - Bohr; Mark T. | 2020-02-20 |
Uniform Layouts For Sram And Register File Bit Cells
App 20200058656 - GUO; Zheng ; et al. | 2020-02-20 |
Via blocking layer
Grant 10,535,601 - Hourani , et al. Ja | 2020-01-14 |
Semiconductor device having tipless epitaxial source/drain regions
Grant 10,490,662 - Bohr Nov | 2019-11-26 |
Integrated Circuit Device With Crenellated Metal Trace Layout
App 20190312023 - Morrow; Patrick ; et al. | 2019-10-10 |
Metal On Both Sides With Power Distributed Through The Silicon
App 20190267316 - NELSON; Donald W. ; et al. | 2019-08-29 |
Integrated Circuit Device With Back-side Inerconnection To Deep Source/drain Semiconductor
App 20190259699 - Morrow; Patrick ; et al. | 2019-08-22 |
Distributed Semiconductor Die And Package Architecture
App 20190221556 - GOMES; WILFRED ; et al. | 2019-07-18 |
Functionally Redundant Semiconductor Dies And Package
App 20190206834 - Gomes; Wilfred ; et al. | 2019-07-04 |
Metal on both sides with power distributed through the silicon
Grant 10,325,840 - Nelson , et al. | 2019-06-18 |
Via Blocking Layer
App 20190122982 - Hourani; Rami ; et al. | 2019-04-25 |
Self-aligned Contacts
App 20190051558 - Bohr; Mark T. ; et al. | 2019-02-14 |
Self-aligned contacts
Grant 10,141,226 - Bohr , et al. Nov | 2018-11-27 |
Semiconductor device having tipless epitaxial source/drain regions
Grant 10,141,442 - Bohr Nov | 2018-11-27 |
Metal On Both Sides With Power Distributed Through The Silicon
App 20180218973 - NELSON; Donald W. ; et al. | 2018-08-02 |
Via Blocking Layer
App 20180174893 - HOURANI; RAMI ; et al. | 2018-06-21 |
Self-aligned Contacts
App 20180096891 - Bohr; Mark T. ; et al. | 2018-04-05 |
Via blocking layer
Grant 9,899,255 - Hourani , et al. February 20, 2 | 2018-02-20 |
Self-aligned contacts
Grant 9,892,967 - Bohr , et al. February 13, 2 | 2018-02-13 |
Semiconductor Device Having Tipless Epitaxial Source/drain Regions
App 20170338347 - Bohr; Mark T. | 2017-11-23 |
Via Blocking Layer
App 20170330794 - HOURANI; RAMI ; et al. | 2017-11-16 |
Replacement metal gates to enhance transistor strain
Grant 9,646,890 - Bohr May 9, 2 | 2017-05-09 |
Self-aligned Contacts
App 20170040218 - Bohr; Mark T. ; et al. | 2017-02-09 |
3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
Grant 9,530,740 - Lee , et al. December 27, 2 | 2016-12-27 |
Self-aligned contacts
Grant 9,508,821 - Bohr , et al. November 29, 2 | 2016-11-29 |
Self-aligned contacts
Grant 9,466,565 - Bohr , et al. October 11, 2 | 2016-10-11 |
3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
Grant 9,449,913 - Lee , et al. September 20, 2 | 2016-09-20 |
Replacement Metal Gates To Enhance Transistor Strain
App 20160247727 - Bohr; Mark T. | 2016-08-25 |
3D integrated circuit package with window interposer
Grant 9,391,013 - Mallik , et al. July 12, 2 | 2016-07-12 |
Self-aligned contacts
App 20160155815 - BOHR; Mark T. ; et al. | 2016-06-02 |
Semiconductor Device Having Tipless Epitaxial Source/drain Regions
App 20160133749 - Bohr; Mark T. | 2016-05-12 |
Replacement metal gates to enhance tranistor strain
Grant 9,337,336 - Bohr May 10, 2 | 2016-05-10 |
Semiconductor device having tipless epitaxial source/drain regions
Grant 9,276,112 - Bohr March 1, 2 | 2016-03-01 |
Replacement Metal Gates To Enhance Tranistor Strain
App 20160049510 - Bohr; Mark T. | 2016-02-18 |
3d Interconnect Structure Comprising Through-silicon Vias Combined With Fine Pitch Backside Metal Redistribution Lines Fabricated Using A Dual Damascene Type Approach
App 20150364425 - Lee; Kevin J. ; et al. | 2015-12-17 |
3d Integrated Circuit Package With Window Interposer
App 20150332994 - MALLIK; Debendra ; et al. | 2015-11-19 |
Replacement metal gates to enhance transistor strain
Grant 9,159,566 - Bohr October 13, 2 | 2015-10-13 |
Self-aligned Contacts
App 20150270216 - Bohr; Mark T. ; et al. | 2015-09-24 |
3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
Grant 9,142,510 - Lee , et al. September 22, 2 | 2015-09-22 |
3D integrated circuit package with window interposer
Grant 9,129,958 - Mallik , et al. September 8, 2 | 2015-09-08 |
Self-aligned contacts
Grant 9,093,513 - Bohr , et al. July 28, 2 | 2015-07-28 |
Die Package Architecture With Embedded Die And Simplified Redistribution Layer
App 20150187608 - GANESAN; Sanka ; et al. | 2015-07-02 |
Self-aligned contacts
Grant 9,054,178 - Bohr , et al. June 9, 2 | 2015-06-09 |
Replacement Metal Gates To Enhance Transistor Strain
App 20150104935 - BOHR; MARK T. | 2015-04-16 |
Replacement gates to enhance transistor strain
Grant 8,946,016 - Bohr February 3, 2 | 2015-02-03 |
3d Integrated Circuit Package With Window Interposer
App 20140191419 - Mallik; Debendra ; et al. | 2014-07-10 |
Self-aligned Contacts
App 20140151817 - Bohr; Mark T. ; et al. | 2014-06-05 |
Penetrating implant for forming a semiconductor device
Grant 8,741,720 - Curello , et al. June 3, 2 | 2014-06-03 |
Through Gate Fin Isolation
App 20140001572 - BOHR; Mark T. ; et al. | 2014-01-02 |
3d Interconnect Structure Comprising Through-silicon Vias Combined With Fine Pitch Backside Metal Redistribution Lines Fabricated Using A Dual Damascene Type Approach
App 20130285257 - Lee; Kevin J. ; et al. | 2013-10-31 |
Replacement Gates To Enhance Transistor Strain
App 20130267070 - Bohr; Mark T | 2013-10-10 |
3d Interconnect Structure Comprising Fine Pitch Single Damascene Backside Metal Redistribution Lines Combined With Through-silicon Vias
App 20130256910 - Lee; Kevin J. ; et al. | 2013-10-03 |
Semiconductor Device Having Tipless Epitaxial Source/drain Regions
App 20130240950 - Bohr; Mark T. | 2013-09-19 |
Penetrating Implant For Forming A Semiconductor Device
App 20130224926 - Curello; Giuseppe ; et al. | 2013-08-29 |
Self-aligned Contacts
App 20130178033 - Bohr; Mark T. ; et al. | 2013-07-11 |
Semiconductor device having tipless epitaxial source/drain regions
Grant 8,450,165 - Bohr May 28, 2 | 2013-05-28 |
Self-aligned contacts
Grant 8,436,404 - Bohr , et al. May 7, 2 | 2013-05-07 |
Penetrating implant for forming a semiconductor device
Grant 8,426,927 - Curello , et al. April 23, 2 | 2013-04-23 |
Replacement gates to enhance transistor strain
Grant 8,101,485 - Bohr January 24, 2 | 2012-01-24 |
Replacement Gates To Enhance Transistor Strain
App 20120003798 - Bohr; Mark T. | 2012-01-05 |
Penetrating Implant For Forming A Semiconductor Device
App 20110215422 - Curello; Giuseppe ; et al. | 2011-09-08 |
Replacement gates to enhance transistor strain
Grant 8,013,368 - Bohr September 6, 2 | 2011-09-06 |
Self-aligned contacts
App 20110156107 - Bohr; Mark T. ; et al. | 2011-06-30 |
Penetrating implant for forming a semiconductor device
Grant 7,943,468 - Curello , et al. May 17, 2 | 2011-05-17 |
Transistor with improved tip profile and method of manufacture thereof
Grant 7,821,044 - Bohr , et al. October 26, 2 | 2010-10-26 |
Penetrating Implant For Forming A Semiconductor Device
App 20090242998 - Curello; Giuseppe ; et al. | 2009-10-01 |
Replacement gates to enhance transistor strain
App 20090057772 - Bohr; Mark T. | 2009-03-05 |
Transistor with improved tip profile and method of manufacture thereof
Grant 7,494,858 - Bohr , et al. February 24, 2 | 2009-02-24 |
Semiconductor Device Having Tipless Epitaxial Source/drain Regions
App 20080283906 - Bohr; Mark T. | 2008-11-20 |
Transistor with improved tip profile and method of manufacture thereof
App 20080135894 - Bohr; Mark T. ; et al. | 2008-06-12 |
Replacement gates to enhance transistor strain
App 20070138559 - Bohr; Mark T. | 2007-06-21 |
Silicide layers in contacts for high-k/metal gate transistors
App 20070141798 - Bohr; Mark T. | 2007-06-21 |
Method and apparatus for improved power routing
Grant 7,208,402 - Bohr , et al. April 24, 2 | 2007-04-24 |
Method and apparatus for improved power routing
Grant 7,180,195 - Bohr , et al. February 20, 2 | 2007-02-20 |
PMOS transistor strain optimization with raised junction regions
App 20070034945 - Bohr; Mark T. ; et al. | 2007-02-15 |
Transistor with improved tip profile and method of manufacture thereof
App 20070004123 - Bohr; Mark T. ; et al. | 2007-01-04 |
Hermetic passivation structure with low capacitance
Grant 7,145,235 - Bohr December 5, 2 | 2006-12-05 |
Interposer and method of making same
Grant 6,982,225 - Bohr January 3, 2 | 2006-01-03 |
Method and apparatus for improved power routing
App 20050233570 - Bohr, Mark T. ; et al. | 2005-10-20 |
Hermetic passivation structure with low capacitance
App 20050158978 - Bohr, Mark T. | 2005-07-21 |
Method and apparatus for improved power routing
App 20050133894 - Bohr, Mark T. ; et al. | 2005-06-23 |
On-die de-coupling capacitor using bumps or bars
Grant 6,888,716 - List , et al. May 3, 2 | 2005-05-03 |
Wafer passivation structure and method of fabrication
Grant 6,875,681 - Bohr April 5, 2 | 2005-04-05 |
Interposer and method of making same
App 20050017333 - Bohr, Mark T. | 2005-01-27 |
PMOS transistor strain optimization with raised junction regions
App 20040262683 - Bohr, Mark T. ; et al. | 2004-12-30 |
On-die de-coupling capacitor using bumps or bars
App 20040184217 - List, Richard Scott ; et al. | 2004-09-23 |
On-die de-coupling capacitor using bumps or bars and method of making same
Grant 6,706,584 - List , et al. March 16, 2 | 2004-03-16 |
Method of making an interposer
Grant 6,671,947 - Bohr January 6, 2 | 2004-01-06 |
Alternate bump metallurgy bars for power and ground routing
Grant 6,653,563 - Bohr November 25, 2 | 2003-11-25 |
Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
Grant 6,624,032 - Alavi , et al. September 23, 2 | 2003-09-23 |
Interposer and method of making same
Grant 6,617,681 - Bohr September 9, 2 | 2003-09-09 |
On-die de-coupling capacitor using bumps or bars and method of making same
App 20030001284 - List, Richard Scott ; et al. | 2003-01-02 |
Alternate bump metallurgy bars for power and ground routing
App 20020141171 - Bohr, Mark T. | 2002-10-03 |
Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
App 20020098657 - Alavi, Mohsen ; et al. | 2002-07-25 |
Interposer and method of making same
App 20020081838 - Bohr, Mark T. | 2002-06-27 |
Novel Passivation Structure And Its Method Of Fabrication
App 20020064929 - BOHR, MARK T. | 2002-05-30 |
Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
Grant 6,392,271 - Alavi , et al. May 21, 2 | 2002-05-21 |
Structure And Process Flow For Fabrication Of Dual Gate Floating Body Integrated Mos Transistors
App 20020034853 - ALAVI, MOHSEN ; et al. | 2002-03-21 |
Silicide agglomeration fuse device
Grant 6,258,700 - Bohr , et al. July 10, 2 | 2001-07-10 |
Self-aligned contact process using low density/low k dielectric
Grant 6,124,191 - Bohr September 26, 2 | 2000-09-26 |
Channel dopant implantation with automatic compensation for variations in critical dimension
Grant 6,020,244 - Thompson , et al. February 1, 2 | 2000-02-01 |
Low damage doping technique for self-aligned source and drain regions
Grant 5,976,939 - Thompson , et al. November 2, 1 | 1999-11-02 |
Silicide agglomeration device
Grant 5,969,404 - Bohr , et al. October 19, 1 | 1999-10-19 |
Polysilicon polish for patterning improvement
Grant 5,911,111 - Bohr , et al. June 8, 1 | 1999-06-08 |
Memory cell design with vertically stacked crossovers
Grant 5,734,187 - Bohr , et al. March 31, 1 | 1998-03-31 |
Pre-poly emitter implant
Grant 5,420,051 - Bohr , et al. May 30, 1 | 1995-05-30 |
CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors
Grant 4,536,947 - Bohr , et al. August 27, 1 | 1985-08-27 |
Process for forming contact openings through oxide layers
Grant 4,372,034 - Bohr February 8, 1 | 1983-02-08 |
CMOS process
Grant 4,282,648 - Yu , et al. August 11, 1 | 1981-08-11 |
| 