U.S. patent number 10,366,775 [Application Number 15/849,457] was granted by the patent office on 2019-07-30 for memory device using levels of dynamic redundancy registers for writing a data word that failed a write operation.
This patent grant is currently assigned to SPIN MEMORY, INC.. The grantee listed for this patent is SPIN TRANSFER TECHNOLOGIES, INC.. Invention is credited to Neal Berger, Lester M Crudele, Mourad El-Baraji, Daniel L Hillman, Barry Hoberman, Benjamin Stanley Louie.
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United States Patent |
10,366,775 |
El-Baraji , et al. |
July 30, 2019 |
Memory device using levels of dynamic redundancy registers for
writing a data word that failed a write operation
Abstract
Dynamic redundancy buffers for use with a device are disclosed.
The dynamic redundancy buffers allow a memory array of the device
to be operated with high write error rate (WER). A first level
redundancy buffer (e1 buffer) is couple to the memory array. The e1
buffer may store data words that have failed verification or have
not been verified. The e1 buffer may transfer data words to another
dynamic redundancy buffer (e2 buffer). The e1 buffer may transfer
data words that have failed to write to a memory array after a
predetermined number of re-write attempts. The e1 buffer may also
transfer data words upon power down.
Inventors: |
El-Baraji; Mourad (Fremont,
CA), Berger; Neal (Cupertino, CA), Louie; Benjamin
Stanley (Fremont, CA), Crudele; Lester M (Tomball,
TX), Hillman; Daniel L (San Jose, CA), Hoberman;
Barry (Fremont, CA) |
Applicant: |
Name |
City |
State |
Country |
Type |
SPIN TRANSFER TECHNOLOGIES, INC. |
Fremont |
CA |
US |
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Assignee: |
SPIN MEMORY, INC. (Fremont,
CA)
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Family
ID: |
61686568 |
Appl.
No.: |
15/849,457 |
Filed: |
December 20, 2017 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20180114590 A1 |
Apr 26, 2018 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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15277799 |
Sep 27, 2016 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G11C
11/1673 (20130101); G11C 11/1675 (20130101); G11C
7/1039 (20130101); G11C 11/1697 (20130101); G06F
13/16 (20130101); G11C 11/1653 (20130101); G11C
7/20 (20130101); G11C 11/1677 (20130101); G11C
29/785 (20130101); G11C 11/1693 (20130101); G06F
12/0804 (20130101) |
Current International
Class: |
G11C
11/00 (20060101); G11C 11/16 (20060101); G06F
12/0804 (20160101); G11C 7/20 (20060101); G11C
29/00 (20060101); G11C 7/10 (20060101); G06F
13/16 (20060101) |
References Cited
[Referenced By]
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Other References
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Primary Examiner: Byrne; Harry W
Assistant Examiner: Begum; Sultana
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATION
The present application is a Divisional of, claims the benefit of
and priority to U.S. application Ser. No. 15/277,799, filed Sep.
27, 2016, entitled "DEVICE WITH DYNAMIC REDUNDANCY REGISTERS" and
hereby incorporated by reference in its entirety.
Claims
We claim:
1. A memory device comprising: a memory array of memory cells,
wherein the memory array is configured to store a data word at one
of a plurality of memory addresses; a first level dynamic
redundancy buffer comprising data storage elements; and a pipeline
coupled to the memory array and the first level dynamic redundancy
buffer, wherein the pipeline is configured to: write a data word
into the memory array at a selected one of the plurality of memory
addresses; verify the data word written into the memory array to
determine whether the data word was successfully written by the
write; responsive to a determination that the data word was not
successfully written by the write, writing the data word and the
selected one of the plurality of memory addresses into the first
level dynamic redundancy buffer; and attempt to re-write the data
word stored in the first level dynamic redundancy buffer into the
memory array at the selected one of the plurality of memory
addresses.
2. The memory device of claim 1, wherein the memory cells of the
memory array comprise a plurality of spin-transfer torque magnetic
random access memory (STT-MRAM) cells.
3. The memory device of claim 1, wherein the pipeline is further
configured to: perform a verification to determine if the data word
was successfully written to the memory array by the re-write; and
responsive to a determination that the data was not successfully
written by the re-write, write the data word and the selected one
of the plurality of memory addresses into a second level dynamic
redundancy buffer.
4. The memory device of claim 3, wherein the pipeline is further
configured to: remap the data word from the second level dynamic
redundancy buffer to an address in the memory array, wherein the
second level dynamic redundancy buffer stores a remap address for
the data word.
5. The memory device of claim 1, wherein the pipeline is further
configured to: attempt the re-write to the memory array a
predetermined number of times prior to writing the data word and
the selected one of the plurality of memory addresses into the
second level dynamic redundancy buffer, and wherein the
predetermined number is stored using control bits.
6. The memory device of claim 5, wherein the predetermined number
is stored using control bits of the first level dynamic redundancy
buffer.
7. The memory device of claim 5, wherein the memory array comprises
a pseudo-dual port memory array, wherein the pseudo-dual port
memory array is operable to attempt the re-write and a verify in a
same clock cycle, and wherein the re-write and the verify comprise
data words that share a common row address.
8. The memory device of claim 5, wherein the first level dynamic
redundancy buffer comprises volatile memory.
9. The memory device of claim 5, wherein the first level dynamic
redundancy buffer comprises non-volatile memory.
10. The memory device of claim 5, wherein the second level dynamic
redundancy buffer comprises non-volatile memory.
11. The memory device of claim 5, wherein the second level dynamic
redundancy buffer comprises volatile memory.
12. A memory device comprising: a memory array comprising memory
cells, wherein the memory array is configured to store a data word
at one of a plurality of memory addresses; a first level dynamic
redundancy buffer comprising data storage elements; a second level
dynamic redundancy buffer comprising data storage elements; and a
pipeline coupled to the memory array, the first level dynamic
redundancy buffer, and the second level dynamic redundancy buffer,
wherein the pipeline is configured to: write a data word into the
memory array at a selected one of the plurality of memory
addresses; verify the data word written into the memory array to
determine whether the data word was successfully written by the
write; responsive to a determination that the data word was not
successfully written by the write, writing the data word and the
selected one of the plurality of memory addresses into the first
level dynamic redundancy buffer; re-write the data word stored in
the first level dynamic redundancy buffer into the memory array at
the selected one of the plurality of memory addresses; perform
verification to determine if the data word was successfully written
to the memory array responsive to the re-writing; and responsive to
a determination that the data was not successfully written during
the re-writing, write the data word and the selected one of the
plurality of memory addresses into a second level dynamic
redundancy buffer.
13. The memory device of claim 12, wherein the pipeline is further
configured to: attempt the re-write to the memory array a
predetermined number of times prior to writing the data word and
the selected one of the plurality of memory addresses into the
second level dynamic redundancy buffer, and wherein the
predetermined number is stored using control bits associated with
re-write attempts.
14. The memory device of claim 12, wherein the memory cells of the
memory array comprise a plurality of spin-transfer torque magnetic
random access memory (STT-MRAM) cells.
15. The memory device of claim 12, wherein the pipeline is further
configured to: write the data word and the selected one of the
plurality of memory addresses into the second level dynamic
redundancy buffer on power down, wherein the first level dynamic
redundancy buffer comprises volatile memory, and wherein the second
level dynamic redundancy buffer comprises non-volatile memory.
16. The memory device of claim 12, wherein the pipeline is further
configured to: restore the data word and the selected one of the
plurality of memory addresses into the first level dynamic
redundancy buffer from the second level dynamic redundancy buffer
during power up.
17. The memory device of claim 12, wherein the pipeline is further
configured to: write the data word and the selected one of the
plurality of memory addresses into the memory array from the second
level dynamic redundancy buffer on power down, wherein the second
level dynamic redundancy buffer comprises volatile memory.
18. The memory device of claim 12, wherein the pipeline is further
configured to: invalidate entries in the second level dynamic
redundancy buffer associated with the data word responsive to a
determination that the data word for the selected one of the
plurality of memory addresses was successfully written into the
memory array by a different write for the selected one of the
plurality of memory addresses.
19. The memory device of claim 12, wherein the pipeline is further
configured to: invalidate entries in the first level dynamic
redundancy buffer associated with the data word responsive to a
determination that the data word for the selected one of the
plurality of memory addresses was successfully written into the
memory array by a different write for the selected one of the
plurality of memory addresses.
20. The memory device of claim 12, wherein the pipeline is further
configured to: transfer data from the first level dynamic
redundancy buffer to the second level dynamic redundancy buffer to
make vacant memory in the first level dynamic redundancy
buffer.
21. The memory device of claim 12, wherein the second level dynamic
redundancy buffer comprises status bits, wherein the status bits
are operable to allow data manipulation of a particular entry
within the second level dynamic redundancy buffer only if a
predetermined number of status bits are flagged.
22. The memory device of claim 12, wherein the second level dynamic
redundancy buffer comprises multiple copies of each data word
stored in the second level dynamic redundancy buffer, and wherein a
most reliable copy of a respective data word is selected.
23. A memory device comprising: a memory array comprising memory
cells, the memory array configured to store a data word at one of a
plurality of memory addresses, wherein the memory cells of the
memory array comprise a plurality of spin-transfer torque magnetic
random access memory (STT-MRAM) cells; a first level dynamic
redundancy buffer comprising data storage elements; and a pipeline
coupled to the memory array and the first level dynamic redundancy
buffer, wherein the pipeline is configured to: write a data word
into the memory array at a selected one of the plurality of memory
addresses; verify the data word written into the memory array to
determine whether the data word was successfully written by the
write; responsive to a determination that the data word was not
successfully written by the write, writing the data word and the
selected one of the plurality of memory addresses into the first
level dynamic redundancy buffer; and responsive to a determination
that the data was not successfully written, re-write the data word
stored in the first level dynamic redundancy buffer into the memory
array at the selected one of the plurality of memory addresses.
24. The memory device of claim 12, wherein the second level dynamic
redundancy buffer performs a more stringent error correction code
(ECC) scheme than the memory array.
Description
FIELD
The present patent document relates to registers that are added to
devices, and more particularly registers added to random access
memory (RAM). The methods and devices described herein are
particularly useful in spin-transfer torque magnetic memory
(STT-MRAM) devices.
BACKGROUND
Magnetoresistive random-access memory ("MRAM") is a non-volatile
memory technology that stores data through magnetic storage
elements. These magnetic storage elements are two ferromagnetic
plates or electrodes that can hold a magnetic field and are
separated by a non-magnetic material, such as a non-magnetic metal
or insulator. In general, one of the plates has its magnetization
pinned (i.e., a "reference layer"), meaning that this layer has a
higher coercivity than the other layer and requires a larger
magnetic field or spin-polarized current to change the orientation
of its magnetization. The second plate is typically referred to as
the free layer and its magnetization direction can be changed by a
smaller magnetic field or spin-polarized current relative to the
reference layer.
MRAM devices store information by changing the orientation of the
magnetization of the free layer. In particular, based on whether
the free layer is in a parallel or anti-parallel alignment relative
to the reference layer, either a "1" or a "0" can be stored in each
MRAM cell. Due to the spin-polarized electron tunneling effect, the
electrical resistance of the cell changes due to the orientation of
the magnetization of the two layers. The cell's resistance will be
different for the parallel and anti-parallel states and thus the
cell's resistance can be used to distinguish between a "1" and a
"0." MRAM devices are generally considered as non-volatile memory
devices since they maintain the information even when the power is
off. The two plates can be sub-micron in lateral size and the
magnetization direction can still be stable with respect to thermal
fluctuations.
MRAM devices are considered as the next generation structures for a
wide range of memory applications. MRAM products based on spin
torque transfer switching are already making its way into large
data storage devices. Spin transfer torque magnetic random access
memory ("STT-MRAM") has an inherently stochastic write mechanism,
wherein bits have certain probability of write failure on any given
write cycle. The write failures are most generally random, and have
a characteristic failure rate. A high write error rate (WER) may
make the memory unreliable.
In memory devices, and especially STT-MRAM, methods and systems for
verifying and re-writing data words are beneficial.
SUMMARY AND CLAIMABLE SUBJECT MATTER
In an embodiment, a device with dynamic redundancy registers is
disclosed. In one aspect, a memory device comprising random access
memory (RAM) device, and specifically an STT-MRAM device, is
provided. The present disclosure provides backup dynamic redundancy
registers that allow the device to operate with high write error
rate (WER). The dynamic redundancy registers allow verifies,
re-writes, and relocation of data words that fail to write
correctly to a memory bank, generally, without loss of throughput,
speed, or restriction on random access addressing.
In one aspect, the present disclosure teaches a memory bank that is
coupled to an e1 register. The e1 register is coupled to the e2
register. The e1 register stores data words that are to be verified
or re-written to the memory bank. The e1 register also stores an
associated address for data words within the memory bank. Data
words in the e1 register may be verified against data words in the
memory bank at the associated address within the memory bank. If a
system write operation fails on the memory bank, a re-write
operation may be tried by writing a data word from the e1 register
to the memory bank. The fact that the system write operation failed
may be determined through a verify operation. Re-write operation
from e1 register to memory bank may be tried as many times as
necessary to successfully complete write operation or may not be
tried at all. In one example, the number of re-write operations may
be configurable based on control bit(s) associated with re-write
attempts. In one aspect, the number of re-write operations may be
configurable on a per-bank basis or per-segment of bank basis.
These control bits may be stored in the e1 register and associated
with a particular data word and communicated and updated as
appropriate.
In one aspect, the re-write operation may be tried only when memory
bank is idle (that is there are no write or read operations for
that memory bank). In this way, re-write operations may be
transparent to and with no delay of incoming system read and system
write operations. After the desired number of re-write attempts (0
to n) from the e1 register, the memory device moves (relocates)
data word from the e1 register to the e2 register. The memory
device may also move associated address within memory bank for data
word from the e1 register to the e2 register. In one embodiment, a
re-write operation may occur only once from the e1 register to the
memory bank. The memory device then relocates the data word and
associated address from the e1 register to the e2 register if the
re-write operation failed. Although explained with reference to one
memory bank and two dynamic redundancy registers, one or more
memory banks and two or more dynamic redundancy registers may also
be used.
Typically, the first level dynamic redundancy register (e1
register) may operate at clock cycle speed of memory bank (some
operations may operate at clock cycle speed of memory bank while
other operations may occur independent or multiples of memory bank
clock cycle speed). The e1 register may be either non-volatile or
volatile, and may typically comprise SRAM. The e1 register may also
comprise a content addressable memory (CAM) array which allows
reduced size of e1 register. In one embodiment, e1 register may be
high-speed, smaller register than a last level register.
Typically, the last level dynamic redundancy register (e2 register)
may operate at clock cycle speed of main memory bank (some
operations may operate at clock cycle speed of memory bank while
other operations may occur independent or multiples of memory bank
clock cycle speed). The last level may be either non-volatile or
volatile, and may typically comprise MRAM. The e2 register may also
comprise a CAM. The last level dynamic register may beneficially
comprise non-volatile memory which allows data to be backed up on
power down. The e2 register typically prioritizes reliability over
size as compared to memory bank. In one embodiment, the last level
register may comprise more entries than the e1 register. In one
embodiment, e2 register entries may be invalidated when a write
operation occurs for a data word having associated address common
with data word in e2 register.
In one aspect, the e1 register stores a data word and an associated
address for data words in a pipeline structure that have not had an
opportunity to verify. For example, a data word may not have an
opportunity to verify because of row address change. That is, a
write operation may occur on a different row address than a verify
operation. Thus, the data word for a verify operation would be
stored within e1 register and verify would be performed, if
possible, on another data word from e1 register having common row
address with the data word for write operation. This feature is
especially beneficial in pseudo-dual port memory banks. A dual port
memory bank allows read and write operations to be performed
simultaneously. A pseudo-dual port allows read and write operations
to be simultaneously (e.g., substantially within the same memory
device clock cycle) performed on less than all ports. In one
example, a pseudo-dual port MRAM may allow verify and write
operations to be simultaneously performed as long as the operations
share a common row address and different column addresses. In one
aspect, a data word may be read from the e1 register rather than
main memory bank if the data word failed to write or verify to
memory bank.
In another aspect, the e1 or e2 register data word, associated
address, and control bits can be deleted, overwritten, invalidated
such that the data is not used, or otherwise considered garbage
when another write operation for the same associated address occurs
on the memory bank. In one aspect, a data word may be read from the
e2 register rather than the main memory bank if such read operation
is beneficial. For example, if e1 register relocated a data word to
e2 register. In another aspect, data stored in the e2 SRAM and CAM
is backed up onto the e2 non-volatile RAM for storage during power
down. In another embodiment, data stored in e2 non-volatile RAM may
be transferred to e2 volatile RAM during power up. In another
aspect, the memory device may move data from the e1 register to the
e2 register in order to free room in the e1 register. In another
aspect, e2 register may not store data words and associated
addresses but instead remap data words and associated addresses
received from e1 register into a different area of memory bank. In
another aspect e2 register may move data words to memory bank upon
power down.
Typically, e2 register should be more reliable than memory bank
because data may not be recoverable in case of e2 register failure.
Thus, schemes can be implemented to increase reliability of e2
register. For example, e2 register may comprise status bits that
allow data manipulation of a particular data word or other entry
within e2 only if all or a predetermined number of status bits are
set to one. In another scheme, multiple copies of data word may be
maintained in e2 register and selected based on a voting scheme. In
another scheme, a more stringent error correction code (ECC) scheme
may be performed within e2 register than in memory bank. In another
scheme, e2 register points to particular addresses within main
memory for storing data words rather than storing the data word
within e2 itself.
In one aspect, the present disclosure teaches an access method and
system into memory banks. Pseudo-dual ports allow using the
disclosed Y-mux structure to simultaneously perform verify and
write operations on two data words sharing a common row address
(e.g., sharing a common word line). In other embodiments, dual port
memory bank could allow simultaneous read and write operations. The
Y-mux structure of the present disclosure operates using two column
decoders for the column address. One column decoder allows decoding
for write column addresses. The other column decoder allows
decoding for read and verify column addresses. The disclosed
pseudo-dual port memory bank with Y-mux structure requires only a
single-port memory cell. As explained, a dual port memory bank may
allow read and write operations to be simultaneously performed, but
requires a dual port memory cell. A single port memory cells, for
example an STT MRAM memory cell, may be more area efficient than a
dual port memory cell, for example a dual port STT MRAM memory
cell. Thus, the present disclosure teaches, in one embodiment, a
Y-mux structure to create a pseudo dual port memory bank with
single port memory cells. Thus, e1 register operates with the
disclosed pseudo dual port memory bank to permit write and verify
operations sharing common row address to occur simultaneously.
In another aspect, the memory device includes control bits and
signals that are used for the control logic of this disclosure. The
memory device may thus know whether data is located in a memory
bank, pipeline bank, e1 register, or e2 register for read
operations. In another aspect, data for operations may invalidated
based on control bits and signals to maintain consistency of
operations. Such control bits and signals may include valid bit,
active bank signal, fail count bits, e2 entry inactive bit. A valid
bit indicates that particular data within a register is valid for
data manipulation operations. An active bank signal indicates
whether the memory bank for operation is active (i.e., that a
system write or system read is being performed in that bank). Fail
count bits indicate the number of re-write operations have occurred
for the data word. The e2 entry inactive bit indicates that the
associated entry in e2 should not be used for data manipulation
operations.
In another aspect, the present disclosure teaches a memory device
having pipeline structure for write and verify, among other data
manipulation operations. This pipeline structure may be used to
control system write, verify, and re-write operations, among other
data manipulation operations. Using the pipeline structure of the
present disclosure, data integrity is maintained and data flow is
structured. In one embodiment, a delay register implements a delay
cycle allowing memory to reach stable state before performing a
verify operation on a data word. This delay cycle allows a write
operation to be performed for a data word, followed by a delay
cycle, followed by a verify operation for the data word.
These and other objects, features, aspects, and advantages of the
embodiments will become better understood with reference to the
following description and accompanying drawings. Moreover, the
object, features, aspect, and advantages of the embodiments can be
modified and combined without departing from the teachings of the
present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are included as part of the
present specification, illustrate the presently preferred
embodiments and, together with the general description given above
and the detailed description given below, serve to explain and
teach the principles of the MTJ devices described herein.
FIG. 1 is a block diagram of exemplary memory device of the present
disclosure having redundancy registers.
FIG. 2 is an exemplary embodiment for a process flow showing a
write operation using exemplary memory device of the present
disclosure and illustrates the high-level write operation performed
on a memory device.
FIG. 3 is a block diagram of exemplary embodiment of a memory
device of the present disclosure having dynamic redundancy
registers.
FIG. 4 is a block diagram of exemplary embodiment of a memory
device of the present disclosure showing Y-mux structure.
FIG. 5 is a block diagram of exemplary embodiment of a memory
device of the present disclosure showing pipeline structure that
allows verification and re-write operations.
FIG. 6 is an exemplary process flow showing an embodiment of a
system read operation using an embodiment of memory device of the
present disclosure.
FIG. 7 is a block diagram of an embodiment of a memory device
showing a first level dynamic redundancy register.
FIG. 8 is a block diagram of an embodiment of a memory device of
the present disclosure showing a last level dynamic redundancy
register.
The figures are not necessarily drawn to scale and the elements of
similar structures or functions are generally represented by like
reference numerals for illustrative purposes throughout the
figures. The figures are only intended to facilitate the
description of the various embodiments described herein; the
figures do not describe every aspect of the teachings disclosed
herein and do not limit the scope of the claims.
DETAILED DESCRIPTION
The following description is presented to enable any person skilled
in the art to create and use dynamic redundancy registers that
allow devices, and especially magnetic semiconductor device such as
an MRAM, to operate with high write error rate (WER). Each of the
features and teachings disclosed herein can be utilized separately
or in conjunction with other features to implement the disclosed
system and method. Representative examples utilizing many of these
additional features and teachings, both separately and in
combination, are described in further detail with reference to the
attached drawings. This detailed description is merely intended to
teach a person of skill in the art further details for practicing
preferred aspects of the present teachings and is not intended to
limit the scope of the claims. Therefore, combinations of features
disclosed in the following detailed description may not be
necessary to practice the teachings in the broadest sense, and are
instead taught merely to describe particularly representative
examples of the present teachings.
In the following description, for purposes of explanation only,
specific nomenclature is set forth to provide a thorough
understanding of the present teachings. However, it will be
apparent to one skilled in the art that these specific details are
not required to practice the present teachings.
FIG. 1 is a block diagram of exemplary memory device of the present
disclosure having dynamic redundancy registers (e1 register 104 and
e2 register 106, in this case). FIG. 1 shows memory devices 100
described herein that includes memory bank 102, e1 register 104,
and e2 register 106. Moreover, memory device 100 communicates with
data signals, for example, address signal 108, data word signal
110, clock signal 112, write and chip select signals 114, power
down signal 116, power up signal 118. Note that FIG. 1 illustrates
certain teachings of the present disclosure. However, it should be
understood that the specific signals 108-118 illustrated may be
modified by those with ordinary skill in the art without departing
from the teachings of the present disclosure. Moreover, other
communication interfaces, for example a double data rate (DDR)
interface, to the memory device may be used. Although shown with
only two dynamic redundancy registers here (e1 register 104 and e2
register 106) and one memory bank (memory bank 102), memory device
100 may comprise two or more dynamic redundancy registers and one
or more memory banks. The two or more dynamic redundancy registers
could be implemented using some combination e1 register 104 and e2
register 106. The two or more dynamic redundancy registers may also
operate hierarchically or in parallel.
Memory bank 102 comprises an array of data storage elements
comprising data bits and may be implemented by volatile or
non-volatile RAM technologies such as static random-access memory
(SRAM), dynamic random-access memory (DRAM), resistive
random-access memory (RRAM), phase-change memory (PCM), MRAM,
STT-MRAM, or other RAM technologies. In an exemplary embodiment,
memory bank 102 may include an error correcting code block (not
pictured). The teachings of the present disclosure are especially
beneficial when memory bank 102 comprises STT-MRAM which suffers
from an inherently stochastic write mechanism, wherein bits have
certain probability of write failure on any given write cycle. The
teachings of the present disclosure allow memory bank 102 to be
operated with high WER. However, many such errors can be corrected
using the teachings of the present disclosure. Operating with high
WER may allow memory bank 102 to operate under other beneficial
conditions. For example, memory bank 102 could operate under high
write speed, low write voltage (which may enable higher bitcell
endurance), reducing ECC bits, or increased ECC decode speed, among
other beneficial conditions.
In one embodiment, memory bank 102 may comprise 65,536.times.50
addressable bits. Further, the 50 bits comprise a 32-bit data word
and 18 parity bits for error correction. Operations may be
performed on memory bank 102 including system read, system write,
re-write and verify operations, among other data manipulations. A
particular operation, for example a write operation, may occur at a
particular address within memory bank 102. The operation may have a
row address, indicating a word line, and a column address. The
address for write operations may be communicated through a write
port of memory bank 102. The address for read or verify operations
may be communicated through a read port of memory bank 102.
In one embodiment, memory bank 102 comprises a pseudo-dual port
memory bank allowing memory device 100 to simultaneously (e.g.,
substantially within a memory device clock cycle) perform a write
operation and a verify operation sharing a common row (word line)
address. System read operations to memory bank 102 generally
supersede write and verify operations. Thus, system read operation
would be performed before the scheduled write and verify
operations. Write and verify operation could then happen on a
subsequent clock cycle. If a dual-port memory bank 102 is used,
read and write operations may be simultaneously performed.
The e1 register 104 is coupled to memory bank 102 and e2 register
106. The e1 register 104 comprises an array of data storage
elements comprising data bits and may be implemented by volatile
and non-volatile RAM technologies. The e1 register 104 may also
comprise control bits and communicate using control signals that
maintain consistency of operations within memory device 100.
Typically, data is more reliably written to e1 register 104 than
within memory bank 102. Thus, if memory bank 102 comprises
STT-MRAM, then e1 register 104 might comprise SRAM. In other
embodiments, e1 register may comprise non-volatile RAM such as
STT-RAM. The e1 register may also comprise a dual-port STT-RAM to
allow simultaneous read and write operations. In this case, e1
register 104 can run at the same cycle throughput speed as a memory
bank. The e1 register 104 may also comprise content addressable
memory (CAM).
Generally, e1 register 104 stores data words and associated
addresses for data in memory bank 102 that has not been verified or
has failed verification. In one embodiment, e1 register 104 may
store data words that have not been verified. For example, e1
register 104 receives ROWchg signal that indicates row address
change within a pipeline structure of the present disclosure. The
ROWchg signal indicates that the data word and the associated
address from the pipeline structure should be stored within e1
register 104. The ROWchg signal may also indicate that that another
data word and associated address should be transmitted from e1
register 104 to the pipeline structure for verify operation. If a
pseudo-dual port memory bank is used, e1 register 104 may choose a
data word and an associated address such that they share a common
row address with a data word in the write register of the pipeline
structure. In this way, write operation and verify operation can be
simultaneously performed since the data words share a common row
address.
In another embodiment, e1 register 104 may store data words that
have failed verification. For example, the pipeline structure may
transmit signal to e1 register 104 indicating that a data word has
failed to write (i.e., failed verification) to memory bank 102. The
pipeline structure may also transmit data word and associated
address (in the case that e1 register 104 does not already contain
the data word and associated address) to e1 register 104 in order
to later try to re-write the data word to memory bank 102. In
another example, read operation may occur and pipeline structure
may determine that read operation did not occur within a
predetermined error budget. The pipeline structure may then
transmit a signal indicating that the read operation failed and
transmit the data word and associated address to e1 register 104
for storage.
From the preceding, one of ordinary skill in the art will
understand that e1 register 104 may store data words and associated
addresses for future verification. For example, a data word may not
have had an opportunity to verify due to row address change. Thus,
e1 register 104 may transmit the data word and associated address
to the pipeline structure of the present disclosure during some
subsequent clock cycle to verify the data word. Typically, a
control signal may indicate to e1 register 104 that a row address
change will occur or that memory bank 102 will become inactive
during subsequent clock cycles. The e1 register 104 may then
determine the appropriate data word sharing common row address with
data word to be written (in case of row address change) during the
subsequent clock cycle. The e1 register 104 then transmits the data
word and associated address to verify register of the pipeline
structure. In one embodiment, e1 register 104 may also transmit
physical address within e1 register 104 if the data word is already
stored within e1 register 104. In this way, control bits associated
with the data word may be updated.
From the preceding, a person skilled in the art will understand
that e1 register 104 may also store data words for future re-write
attempts. The e1 register 104 may receive data words that have
failed verification from the pipeline structure of the present
disclosure. Memory device 100 may have attempted a write operation
and the data word failed a verify operation. Memory device 100 may
also have attempted a read operation and the data word may have
failed to read within a specified error budget. In both cases, the
pipeline structure of the present disclosure may transmit the data
word to e1 register 104. Memory bank 102 may become inactive during
a subsequent cycle. The e1 register 104 may then determine an
appropriate data word to attempt to re-write to memory bank 102. In
this case, e1 register 104 may transmit a data word and associated
address to the pipeline structure. The e1 register 104 transmits
the data word such that a write register could re-write the data
word during the clock cycle that memory bank 102 would otherwise be
inactive.
Generally, e1 register 102 may also relocate data words, associated
addresses, and control bits to e2 register 106. If no more re-write
attempts are desired, e1 register 104 may relocate data word and
associated address to e2 register 106. The e1 register may also
relocate data to memory bank 102 or e2 register 106 on power down
so that data is stored in non-volatile memory in the case that e1
register 104 comprises volatile memory. The e1 register 104 may
also relocate data to e2 register 106 in the case that e1 register
104 lacks space for data words.
The e1 register comprises control bits and communicates using
control signals. In one embodiment, e1 register comprises valid
bits indicating whether the associated data word is a valid entry
within e1 register. In another embodiment, e1 register comprises
fail count bits indicating the number of re-write attempts
associated with a data word. In this way, memory device 100 may try
only a specified number of re-write attempts. In another
embodiment, e1 register comprises bits indicating that the
associated data word has not been verified due to row address
change and should be verified.
The e2 register 106 is coupled to e1 register 104 and may also be
coupled to memory bank 102. The e2 register 106 comprises an array
of data storage elements comprising data bits and may be
implemented by volatile and non-volatile RAM technologies. The e2
register 106 may also comprise an ECC block and CAM. The e2
register 106 may comprise data words, associated addresses, and
control bits. Typically, e2 register 106 will comprise a
non-volatile memory technology, for example STT-MRAM.
The e2 register 106 stores data words and associated addresses
relocated from e1 register 104. In another embodiment, rather than
storing data words and associated data words from e1 register 104,
e2 register 106 remaps those data words to addresses within memory
bank 102. For example, e2 register 106 may store remap addresses in
memory bank 102. The e2 register 106 then temporarily stores a data
word from e1 register and then writes it to an appropriate remap
address in memory bank 102. When a data word should be read, e2
register contains the appropriate remap address for reading the
data word from memory bank 102.
Data words and associated addresses may be relocated to e2 register
106 or remapped based on different conditions. In one embodiment,
e1 register 104 relocates data words and associated addresses to e2
register 106 because the data words failed to write to memory bank
102 after the specified number of re-write attempts. In another
embodiment, e1 register 104 relocates data words and associated
addresses to e2 register 106 because power down signal 116
indicates that data word and associated address should be moved to
non-volatile memory, such as e2 register 106 comprising STT-MRAM.
In another embodiment, e1 register 104 relocates data words and
associated addresses to e2 register 106 because e1 register 104
lacks space. One of ordinary skill in the art will understand that
desired control bits may also be relocated with associated data
word. In another embodiment, if data word fails to write to a
physical address within e2 register 106 after a predetermined
number of write attempts a different physical address may be chosen
for data word.
The e2 register 106 may also be coupled to an input register of a
pipeline structure. In this way, e2 register 106 may receive
control signals indicating that a write operation for a data word
sharing a common associated address with a data word within e2
register 106 may be occurring. Thus, control bits within e2
register 106 may indicate that a data word within e2 register 106
is invalid because of a system write operation.
Memory device 100 also communicates using exemplary signals
108-118. Address signal 108 comprises address within memory bank
102 of data to be written to or read from (or otherwise
manipulated). Data word signal 110 comprises a data word to be
written to (or otherwise manipulated) memory bank 102. Clock signal
112 comprises a memory device 100 clock signal or other clock
signal (such as for specific components within memory device 100).
Write and chip select signals 114 comprise signals used to
determine the operation to be performed within memory bank 102. For
example, if write signal is high and chip select signal is low a
read operation might be performed on memory bank 102. Power down
signal 116 indicates whether power will be removed from memory
device 100 or specific components within memory device 100. Thus,
power down signal 116 may be used to determine that contents of e1
register 104 should be written to memory or e2 register 106. Power
up signal 118 indicates that power is provided to memory device
100. Power up signal may indicate that e2 non-volatile memory
contents should be loaded to e2 volatile memory. One of ordinary
skill in the art will recognize that the specific signals 108-118
may be modified without departing from the present disclosure.
Power down signal 116 may indicate that e2 register 106 volatile
memory contents should be moved to e2 register 106 non-volatile
memory. For example, e2 register 106 volatile memory contents not
already stored in e2 non-volatile memory may be moved to e2
register 106 non-volatile memory. In another embodiment, power down
signal 116 may indicate that e2 register 106 contents should be
moved to non-volatile memory bank 102. In another embodiment, power
down signal 116 may indicate that certain data words within e1
register 104 should be verified to memory bank 102. In another
embodiment, power down signal 116 indicates that certain data words
within e1 register 104 should be re-written to memory bank 102.
FIG. 2 depicts an exemplary embodiment for a process flow showing a
write operation using an exemplary memory device of the present
disclosure and illustrates the high-level write operation performed
on a memory device. In step 202, a write operation to be performed
on primary memory (e.g., input register to memory bank 102) exists
within a memory device. In step 202, the system write operation may
be performed on primary memory. In step 204, it is determined
whether system write operation was successful. For example, a
verify operation could determine whether the write operation
successfully occurred (for example, whether the data word was
written with an acceptable error budget or perfectly) within
primary memory. If the write operation was successful, process flow
200 proceeds to end step 210. On the other hand, if the write
operation was unsuccessful, a determination is made whether write
operation should be retried in step 206. One retry is illustrated
during process flow 200 of FIG. 2, but as many tries to write data
into memory bank may be tried as desired (0 to n retries). If a
retry should be tried, the data will be written from e1 register to
primary memory when process flow 200 returns to step 202. From this
description a person having ordinary skill in the art will
understand the operation of steps 202-206 and 210. However, in some
instances, a write operation from e1 register to primary memory may
be unsuccessful despite the total desired number of retries. In
that case, if a determination is made at step 206 that no more
tries should be made to write data from e1 register to primary
memory, process flow 200 will proceed to step 208. In step 208,
data is written to alternate storage (e.g., from e1 register to e2
register).
FIG. 3 is a block diagram of exemplary embodiment of a memory
device 300 of the present disclosure having dynamic redundancy
registers. FIG. 3 is a block diagram of memory device 300 described
herein that include memory banks 304 and 306, pipeline banks 308
and 310, input register 312, e1 register 314, and e2 register 316.
Memory device 300 communicates using signals 318-324. Memory device
300 includes ports 326-336 for performing read, write, and verify
(or other data manipulation) operations on memory banks 304 and
306. Memory device 300 is described herein to describe aspects of
the present disclosure. One of ordinary skill would understand how
to modify memory device 300 without departing from the teachings of
the present disclosure. Thus, for example, the specific signals
318-324 may be modified by those with ordinary skill in the art
without departing from the teachings of the present disclosure.
Although shown with only two dynamic redundancy registers here (e1
register 314 and e2 register 316) and two memory banks (memory
banks 304 and 306), memory device 300 may comprise two or more
dynamic redundancy registers and one or more memory banks.
Memory banks 304 and 306 have previously been described with
respect to FIG. 1. Memory banks 304 and 306 also include two ports
(326 and 328; 332 and 334, respectively) for performing read,
write, and verify (or other data manipulation) operations. Memory
bank 304 could, for example, comprise data words having even
addresses while memory bank 306 comprises data words having odd
addresses. Two ports 326 and 328 of memory bank 304 are coupled to
bit lines of memory bank 304. Likewise, two ports 332 and 334 of
memory bank 306 are coupled to bit lines of memory bank 306.
Although shown with one read and one write port per memory bank,
memory device 300 may comprise any desired number of read and write
ports. In one embodiment, a dual port memory bank is used. Thus,
each port 326-336 could perform simultaneous read and write
operations. However, one of ordinary skill in the art will
understand that the discussion proceeds with pseudo-dual port
memory banks 304-306 in mind to highlight specific teachings of the
present disclosure. The Y-mux structure of the present disclosure
allows pseudo-dual port memory banks 304-308 to perform
simultaneous write and verify operations sharing common row address
and different column address.
With respect to memory bank 304, write port 326 allows transmission
of signals comprising write address and write data to memory bank
304 from pipeline bank 308. Port 328 allows transmission of data
signals comprising read address or verify address to memory bank
304 from pipeline bank 308. Port 330 allows transmission of data
signals comprising read data word from memory bank 304 to pipeline
bank 308.
Pipeline banks 308 and 310 comprise data registers for implementing
the write, read, and verify (and other data manipulation)
operations of the present disclosure. Pipeline banks 308 and 310
are coupled to memory banks 304 and 306, respectively, using
pseudo-dual port structures, as explained above, for providing
simultaneous write and verify operations. Moreover, pipeline banks
308 and 310 are coupled to input register 312. As explained in
connection with FIG. 5, pipeline banks 308 and 310 implement a
pipeline structure that allows verify and write operations to be
simultaneously performed on memory banks 304 and 306. Moreover,
pipeline banks communicate with e1 register 314 to implement a
pipeline structure of the present disclosure.
Input register 312 comprises data storage elements comprising data
bits. Input register comprises a data word, an associated addresses
within memory banks, and control bits indicating a system operation
such as system read or system write. For example, input register
312 may comprise a data word to be written to memory banks
(received from data signal 322), the address of the data (received
from address signal 324), and control bits. Input register 312 may
be coupled to pipeline bank 308 and pipeline bank 310 to
communicate a data word, its associated address, and control bits.
One of ordinary skill in the art will recognize that other
connections are possible and consistent with the teachings of the
present disclosure and the specific connections are shown for ease
of understanding. For example, input register 312 may be coupled to
e1 register 314 for transferring the associated address of data
word to e1 register 312 and control signals.
The e1 register 314 has been described in connection with FIG. 1,
and will also be further described in connection with FIG. 7. The
e1 register 314 is coupled to pipeline banks 308 and 310 and e2
register 316. The e1 register 314 comprises data storage elements
comprising data bits. For example, e1 register 314 may comprise
data word and associated addresses for data words that have failed
to verify correctly within memory banks 304 and 306. The e1
register 314 may comprise data words and associated addresses for
data words that have not yet been verified within memory banks 304
and 306. The e1 register 314 may also comprise data words and
associated addresses for data words that have failed to read from
memory banks 304 and 306 within an associated error budget.
The e2 register 316 has been described in connection with FIG. 1,
and will also further be described in connection with FIG. 8. The
e2 register 316 may be coupled to e1 register 314. The e2 register
316 comprises data storage elements comprising data bits. The e2
register 316 comprises data words, associated addresses, and
control bits. These data words have typically failed to write to
memory banks 304 and 306. These words may have also been written
from e1 register 314 to e2 register 316 because of power down of
memory device 300 or lack of space within e1 register. In one
embodiment, e2 register 316 may optionally be coupled to pipeline
banks 308 and 310 or memory banks 304 and 306 in order to write
data words (or other signals). For example, rather than storing
data words and associated address from e1 register 316, e2 register
may store remap addresses within memory banks 304 and 306 for
writing directly to memory banks through a remap process. In
another embodiment, e2 register 316 writes data to memory banks 304
and 306 during power down.
FIG. 4 is a block diagram of exemplary embodiment of a memory
device of the present disclosure showing a Y-mux structure. FIG. 4
shows portion of memory device 400 comprising memory bank 402, row
decoder 404, write column decoder and y-mux 406, read column
decoder and y-mux 408, and muxes 410-412. FIG. 4 shows a Y-mux
structure for decoders 406-408. The Y-mux structure allows
simultaneous verify and write operations for data words sharing a
common row address (word line) in the memory bank but different
column address.
Memory bank 402 is coupled to decoders 404-408. Row decoder 404
takes as an input the row of address for data word that is to be
written to or read or verified from memory bank 402. Row decoder
then determines appropriate row for the data word. In various
embodiments, a data word is a pre-defined number of bits for a
piece of information handled by a memory device. For example, a
data word may comprise 8, 16, 24, etc. bits. The size of a data
word is dependent on the memory device and may be varied as
necessary.
Mux 410 is coupled to row decoder 404. Mux 410 takes as inputs the
pipeline row address (Pipeline_A_Row) and read row address
(Read_A_Row). Pipeline row address indicates the row address for
data words received from the pipeline for either a write or verify
operation. Typically, the pipeline row address indicates a shared
row address between a data word to be written to memory bank 402
and another data word to be simultaneously verified in memory bank
402. Read row address indicates a row address for a data word to be
read from memory bank 402. Read row address generally takes
precedence over pipeline row address when pseudo-dual port memory
bank 402 is used. Mux 410 then outputs appropriate row address to
row decoder 404. Row address decoder 404 then activates the
appropriate row in memory bank 402. Appropriate activation schemes
will be known to those with ordinary skill in the art.
Write column decoder and y-mux 406 is coupled to memory bank 402.
Write column decoder and y-mux 406 takes as inputs write address
column WR_A_Col and write data WR_D, such as data word. Write
address column indicates a column address for a system write or
re-write operation received from the pipeline structure of the
present disclosure. Write column decoder and y-mux 406 then
determines appropriate column address for write operation. Write
column decoder and y-mux 406 then activates the appropriate column
in memory bank 402. Appropriate activation schemes will be known to
those with ordinary skill in the art.
Read column decoder and y-mux 408 is coupled to memory bank 402.
Read column decoder and y-mux 408 takes as its input the column
address output from mux 412. Read column decoder and y-mux 408 then
determines the appropriate column for read operation. Read column
decoder and y-mux 408 then activates the appropriate column in
memory bank 402. Appropriate activation schemes will be known to
those with ordinary skill in the art.
Mux 412 is coupled to read column decoder and y-mux 408. Mux 412
takes as inputs pipeline column address (Pipeline_A_Col) and read
column address (Read_A_Col). Pipeline column address indicates
column address of data word that should be verified in memory bank
402. Pipeline column address is received from the pipeline
structure. Read column address indicates a column address for a
data word that should be read from memory bank 402. Typically, read
column address takes precedence when a pseudo-dual port memory bank
402 is used. Mux 402 outputs signal comprising column address for
read operation or verify operation to read column decoder and y-mux
408. Thus, operating together, row and column decoders 404-408
perform operation on specific addresses within memory bank 402 (for
example, read, write, or verify).
One of ordinary skill in the art will understand that the Y-mux
structure of column decoders and y-mux 406-408 allows memory bank
402 to be operated as a pseudo-dual port memory bank. A single port
memory cell may thus be used, but memory bank 402 may
simultaneously perform verify and write operations when those
operations share a common row address but different column
addresses. If a dual port memory bank 402 was used, read and write
or verify and write operations could be performed
simultaneously.
FIG. 5 is a block diagram of exemplary embodiment of a memory
device of the present disclosure showing pipeline structure that
allows verification and re-write operations. FIG. 5 shows exemplary
pipeline 500 for implementing the pipeline flow for system write,
re-write, and verify operations, among other data manipulation
operations. Pipeline 500 is implemented using system operations
502, input register 504, pipeline bank 506, e1 register 508, and
memory bank 510. Pipeline bank 506 comprises write register 512,
delay register 514, verify register 516, and verify results
register 518. Moreover pipeline 500 comprises compare memory logic
520.
System operation 502 comprises signals for performing a desired
operation such as system write and system read, among other data
manipulation operations. As such, system operation 502 typically
includes signals indicating a data word, the associated data
address within memory bank 510, and control signals indicating the
operation to be performed on memory bank 510 (such as write or chip
select signal), among other signals for performing data
manipulation operations and maintaining appropriate states.
Typically, the signals from system operation 502 are stored in
input register 504. Other configurations for signals from system
operation 502 may be used without departing from the scope of the
present disclosure. Moreover, other embodiments of pipeline 500 are
possible without departing from the teachings of this disclosure.
For example, delay register 514 allows delay between write and
verify operation on a data word. STT-MRAM may require a delay
between write operations at a particular address and verify
operation at the common address. The delay cycle allows data
storage elements within memory bank 510 to return to a stable state
before performing verify operation. Other RAM technologies, and in
some instances STT-MRAM itself, may not require such delay and
delay register 514 is not necessary.
Input register 504 is coupled to write register 512. Input register
504 comprises data storage elements comprising data bits. In
certain embodiments, input register 504 can include data bits for a
data word, associated address, a valid bit, and other desired
control bits. The valid bit indicates whether data manipulation
operations such as system write operation should be performed or
the register should not be used to perform such operations. For
example, valid bits based on a write signal and chip select signal
provided by system operation 502 may indicate whether data word in
input register is used for write. Input register 504 may also be
coupled to e1 register 508, for example, to transmit associated
address and control bits to e1 register 508. This associated
address and control bits may be used in case of row address change
in the pipeline or to invalidate an e1 register 500 entry with the
same associated address, for example.
An active memory bank of an embodiment of the present disclosure
denotes a memory bank in which a system write or system read is
taking place. Thus, an active bank signal (or an active bank bit)
prevents re-writes during that clock cycle, and instead indicates
that a system write or read will occur during that clock cycle. For
example, an active bank signal indicates that write register 512
will write a data word previously received from input register 504
to memory bank 510 during that clock cycle. Thus, e1 register knows
that data word for re-write operation should not be transmitted to
write register 512 during that clock cycle. Input register 504
transmits data word, associated address, and desired control bits
to write register 512.
The e1 register 508 has previously been described with respect to
FIG. 1 and will be described in conjunction with FIG. 7. The e1
register 508 is coupled to input register 504, write register 512,
delay register 514, verify register 516, and verify results
register 520. The e1 register 508 may supply data word, associated
address of a data word within memory bank 510, and control signals
to write register 512, and verify register 516. The e1 register 508
may receive a data word, its associated address, and control
signals from delay register 514 and verify results register 518.
The e1 register 508 may also transmit a physical address within e1
register 508 in case the data word is already stored within e1
register 508. Although not shown, if delay register 514 were not
used, e1 register 508 may receive data word, associated address,
and control signals from write register 512. Moreover, e1 register
508 may communicate with input register to receive signals such as
data word signal and control signal such as inactive bank
signal.
Write register 512 is coupled to delay register 514 and memory bank
510. In other embodiments, write register 512 may be coupled to
verify register 516. Write register 512 comprises data storage
elements comprising data bits. Typically, write register 512
comprises data bits for a data word, its associated address, valid
bit, and other desired control bits. The valid bit is a valid
register bit and may be set to one when write register 512 contents
are valid such that write operation may occur. Write register 504
receives data word, associated address, and desired control bits
from input register 504 for system write operations. For memory
bank clock cycles that write register 504 would not otherwise be
writing system data words to that memory bank, e1 register 508
transmits data words, associated address, and desired control bits
to write register 512. This allows write register 512 to attempt
re-write operations when write register 512 would not otherwise be
writing system data words to memory bank 510. As previously
explained, when pseudo-dual port memory bank 510 is used, read
operations generally take precedence over write operations from
write register 512. Moreover, when pseudo-dual port memory bank 510
is used, write register 512 may perform write operation
simultaneously with verify operation performed by verify register
516 if the operations share a common row address. Write register
512 also transmits data word, associated address, and desired
control bits to delay register 514 (or verify register 516 if no
delay register is used).
Delay register 514 is coupled to verify register 516 and e1
register 508. Delay register 514 comprises data storage elements
comprising data bits. Typically, delay register 514 comprises a
data word, associated address bits, a valid bit, and other desired
control bits. Valid bit indicates if delay register 514 contents
are valid. The delay register or multiple delay register could
provide more clock cycle delay between write and verify. As
previously explained, the delay register 514 is optional for RAM
technologies that require delay between write and verify operations
for a particular address within memory bank 510. If row address
change occurs within pipeline bank 504, delay register 514
transmits data word, associated address, and desired control bits
to e1 register 508. Thus, data word may be verified on a later
clock cycle when write register will write a data word sharing a
common row address. In another embodiment, data word may be
verified on a later clock cycle when no verify operation will
otherwise occur to the memory bank. If no row address change occurs
within pipeline bank 504, after desired delay clock cycles, delay
register 514 transmits the data word, associated address, and
desired control bits to verify register 516.
Verify register 516 is coupled to memory bank 510 and verify
results register 520. Verify register 516 comprises data storage
elements comprising data bits. Typically, verify register 516
comprises a data word, its associated address, valid bit, and other
desired control bits. Verify register 156 may comprise internal e1
address if data word was received as a result of re-write operation
or verify operation from e1 register. Valid bit indicates whether
verify register 516 contents are valid for verify operation. Verify
register 516 contents, such as data word, can be sourced from
either delay register 514 (or write register 512 in case delay
register 512 is not used) or e1 register 508. Verify register 516
would receive contents from delay register 514 if no row address
change has occurred. Verify register 516 would receive contents
from e1 register 508 if row address change occurred. In one
embodiment, verify register 516 receives the data word, its
associated address, address within e1 register, fail count bits,
and other desired control bits from e1 register 508. Verify
register 516 transmits the associated address to memory bank 510
for the data word to be verified. Verify register 516 transmits the
data word, fail count bits, and other desired status bits to
compare data logic 520. Verify register 516 transmits the data word
and its associated address to verify results register 518 in case
of a system write. Verify register 516 transmits internal e1
address in case of re-write operation or verify from e1 register
508. Thus, if the data word and the associated address already
exist e1 register 508, verify register 516 need not transmit the
data word and the associated address to verify results register
518.
Compare memory logic 520 is coupled to verify register 516. Compare
memory logic 520 comprises data storage elements comprising data
bits. Compare memory logic 520 may comprise read or sense
amplifiers to read a data word from memory bank 510. Hardware logic
for implementing compare memory logic 520 can be used by those with
ordinary skill in the art.
In the case of verify operation, compare memory logic 520 receives
input from verify register 516 and memory bank 510. Memory bank 510
outputs a data word to compare memory logic 520 based on the
associated address transmitted from verify register 516. Compare
memory logic 520 also receives the data word from verify register
516. Thus, compare memory logic 520 determines whether the write
operation passed or failed. Compare memory logic 520 makes the
pass/fail determination based on methods desired by those with
ordinary skill in the art. In one embodiment, compare memory logic
520 determines whether the data word from verify register 516
matches the data word from memory bank 510. In other embodiments,
compare memory logic 520 deems that the operation passed if a
predetermined number of bits match. If verify operation passed,
compare memory logic 520 passes appropriate control bits to verify
results register 518, for example fail count bits may be set to 0.
Verify results register 518 may then invalidate the entry within e1
register if needed. If verify operation failed, verify results
register 518 updates fail count bits within e1 register (in case of
re-write or verify from e1) or transmits the data word, the
associated address, and control bits to e1 register (in case of
system write).
In the case of read operation, memory bank 510 outputs a data word,
the associated address, and desired control bits to compare memory
logic 520. Compare memory logic 520 determines whether the read
operation passed or whether re-write operation should be performed
on memory bank 510 because too many errors occurred while reading
the data word. In one embodiment, compare memory logic 520 corrects
data words using ECC and parity bits associated with data words. If
ECC determines that too many errors occurred (e.g., errors above a
predetermined threshold), compare memory logic 520 also transmits
the data word and control bits to verify results register 518.
Verify results register 518 is coupled to compare memory logic 520
and e1 register 508. Verify results register 518 comprises data
storage elements comprising data bits. Typically, verify results
register 518 comprises data bits for a data word, associated
address, valid bit, and desired control bits. Valid bit indicates
that contents of verify results stage register 518 are valid to be
written to e1 register 508. Verify results register 518 may also
comprise internal e1 address. Verify results register 518 transmits
data to e1 register as previously explained.
One of ordinary skill in the art will understand that pipeline
structure 500 is exemplary and may include more write, delay,
verify, verify results registers, and compare logic blocks to allow
more re-write attempts before writing failed data words to e1
register. Moreover, more registers and memory banks may be added
without departing from the scope of the present disclosure.
FIG. 6 is an exemplary process flow showing an embodiment of a
system read operation using an embodiment of memory device of the
present disclosure. FIG. 6 shows process flow 600 for system read
operation of the present disclosure. Process flow 600 illustrates
the high-level read operation performed on a memory device. In step
602, a system read operation to be performed on memory bank exists
within a memory device. In step 604, the valid address stored in
both pipeline banks are checked to determine whether the data word
associated with system read operation exists there. If no, e1
register checks address to determine whether the data word
associated with system read operation exists there in step 606. If
no, e2 register checks the address to determine whether the data
word associated with system read operation exists there in step
608. If no, the data word is read from memory bank at the
associated address of system read operation in step 610. If the
result of step 608 is yes, the data word is read from e2 register
in step 618. If the answer to step 604 returned yes, then data word
is read from pipeline 614. If the answer to step 606 is yes, then
the data word is read from e1 register in step 616. One of ordinary
skill in the art may recognize other process flows for system read
operations without departing from the teachings of the present
disclosure.
System read process flow 600 may include additional steps. After
step 610, compare logic may determine whether system data word from
memory bank was read within a predetermined error budget in step
612. If the data word output from memory bank contains errors, such
errors may be corrected though ECC. If the data word output from
memory bank contained more errors than allowed by a predetermined
error budget, the data word may also be corrected and stored in e1
register in step 619. In this way, e1 register may attempt to
re-write data word back to memory bank so that the data word may be
read within a predetermined error budget on future read operations.
The corrected data word and associated address would be stored
within e1 register.
FIG. 7 is a block diagram of an embodiment of a memory device
showing a first level dynamic redundancy register. FIG. 7 shows
exemplary e1 register 700 described herein that comprises physical
address decoder 702, CAM 704, mux 706, RAM 708, status logic 710,
and control logic 712. One of ordinary skill in the art will
recognize that e1 register 700 is exemplary, and includes features
such as CAM 704 which are not required for achieving the teachings
of the present disclosure. Moreover, e1 register 700 communicates
control signals for maintaining consistency of operations both
internally and to communicate with components of memory device such
as pipeline banks and e2 register. Such control signals may be
modified without departing from the teachings of the present
disclosure.
Physical address decoder 702 is coupled to CAM 704, mux 706, and
control logic 712. Physical address decoder 702 receives an address
input from control logic 712. Physical address decoder 702 uses the
address input to determine the appropriate physical addresses
within CAM 704 and RAM 708 for performing data manipulation
operation, such as read and write. Physical address decoder 702
selects an entry within CAM 704 using decode signal. Physical
address decoder 702 may also select an entry within RAM 708 using
decode signal to mux 706.
In one embodiment, physical address decoder 702 may take pointers
as input from control logic 712. Different pointers from control
logic 712 indicate available addresses for writing data to CAM 704
and RAM 708 or reading data from CAM 704 and RAM 708, or other
pointers may be used. For example, pointers from control logic 712
may keep track of lowest open addresses within CAM 704 and RAM 704.
Thus, e1 register 700 keeps track of addresses for storing new
data. Pointers from control logic 712 may also keep track of oldest
stored data within CAM 704 and RAM 708. Thus, re-write operations
may be tried on a First-In-First-Out (FIFO) basis. Other schemes
for addressing data within e1 register 700 and selecting data for
data manipulation operations may be used by those with ordinary
skill in the art without departing from the scope of this
disclosure.
CAM 704 is coupled to mux 706. CAM 704 takes as input decode signal
from physical address decoder 702. CAM 704 also takes as input an
associated address which may be received from input register, delay
register, or verify results register of a pipeline structure. CAM
704 also takes as input control bits such as read, write, or search
signal received from control logic 712. CAM 704 also takes as input
other control bits from status logic 710.
The associated address signals indicate addresses within a memory
bank. Associated address signal is typically received from input
register, delay register, or verify results register. Thus, e1
register 700 receives an address within a memory bank where data
word should be verified or written. The e1 register 700 may also
receive associated address from input register to be searched for
words with matching row addresses which may be verified. CAM 704
will typically write associated address from delay register or
verify results registers to itself, so that associated address may
be used later for re-write or verify operation.
Status signal, such as valid bit, indicates whether physical
address within CAM 704 contains valid data for data manipulation
operation. CAM 704 may receive status signal from status logic
710.
Read signal indicates that CAM 704 should output an associated
address, and RAM 708 should output the corresponding data word. CAM
704 may use decode and read signal to output an associated address
of the data word stored in RAM 708. For example CAM 704 may output
an associated address of the data word to write register. In this
way, write register may write data from e1 register in a clock
cycle during which it would otherwise be inactive.
Write signal indicates that the associated address should be stored
within CAM 704 and the corresponding data word should be stored
within RAM 708. For example, CAM 704 may use the associated address
signal, decode signal, and write signal to write the associated
address to a physical address within CAM 704. In one embodiment,
this may occur because row address change occurred within pipeline
structure and delay register sent a data word, an associated
address, and control bits to e1 register 700 for storage. In
another embodiment, verify results register may send a data word,
an associated address, and control bits to e1 register 700 for
storage because verify operation failed or data was not read within
a predetermined error budget.
Search signal indicates that CAM 704 should search itself for an
appropriate address. For example, CAM 704 uses search signal
received from control logic 712 to search itself for an associated
address to output to verify register. Thus, if row change has
occurred in pipeline structure, CAM 704 may output the associated
address of a data word sharing a common row address with the data
word to be written from the pipeline. In addition, e1 RAM 708
outputs a data word matching the associated address within CAM 704
to the pipeline.
CAM 704 outputs associated addresses to the pipeline structure,
such as to write register and verify register. CAM 704 also outputs
associated addresses to e2 register. CAM 704 may only output a
portion of associated address. For example, if row address change
occurred and CAM 704 searched itself for an appropriate address for
verify operation, CAM 704 may output only the column address since
the row address may be known. CAM 704 also outputs match signal to
mux 706. Match signal indicates the physical address within RAM 708
of a data word that corresponds to the associated address within
CAM 704. Match signal may be used when reading a data word from RAM
708.
Mux 706 takes as input read, write, search signal from control
logic 712. Mux 706 also takes as input decode signal received from
physical address decoder. Mux 706 also takes as input match signal
from CAM 704. Mux then transmits select signal to RAM 708 for data
manipulation operation. If mux 706 receives read signal, mux 706
typically transmits decode signal to RAM 708 because decode signal
indicates the physical address within RAM 708 for read operation.
If mux 706 receives write signal, mux 706 typically transmits
decode signal to RAM 708 because decode signal indicates the
physical address within RAM 708 for write operation. If mux 706
receives search signal, mux 706 typically transmits match signal to
RAM 708 because match signal indicates the physical address within
RAM 708 for outputting data word.
RAM 708 takes as input select signal from mux 706. RAM 708 also
takes as input a data word received from pipeline structure, such
as from delay register or verify results register. RAM 708 also
takes as input read and write signals received from control logic
712. Select signal from mux 706 indicates the physical address
within RAM 708 for performing data manipulation operation such as
read or write operation. Data word signal indicates the data word
for storage within RAM 708. Read signal indicates whether the
physical address signal should be used for read operation such that
data should be read from RAM 708 and output to pipeline structure
or e2 register. Write signal indicates whether select signal should
be used for write operation such that data word signal should be
written to RAM 708. RAM 708 typically comprises volatile memory
such as SRAM, but may comprise non-volatile memory such as
STT-MRAM.
Status logic 710 comprises hardware logic that drives the selection
of addresses within control logic 710. Status logic 710 takes as
input control signals from pipeline structure and e2 register.
Control signals may include ROWchg flag previously discussed.
Pipeline structure may also transmit fail count bits to status
logic 710. In one embodiment, status logic 710 updates a valid bit
associated with a data word to invalid in the case that status
logic 710 receives fail count bits set to 0. That is, because
control signals received from verify results register indicated
that verify operation passed, e1 register 700 invalidates the entry
associated with data word (associated addresses, data word, any
associated control bits). Status logic may also take as input
inactive signal indicating that memory bank may become inactive
during a subsequent clock cycle. Thus, e1 register should output a
data word to write register for a re-write operation. Status logic
710 may also receive control signals from e2 register. For example,
status logic 710 may receive signal indicating that e2 register is
ready for a new data word. Status logic 710 may also receive decode
signal from physical decoder 702. Decode signal will indicate the
entry or entries within e1 register 700 which are being
updated.
Status logic 710 transmits status signals. Status logic 710
transmits status signals both internally and externally. Status
logic 710 transmits status signals to control logic 710. Status
logic 710 may also transmit status signals, such as fail count bit,
to pipeline structure and e2 register. Thus, control signals from
status logic 710 may be used to maintain consistency of operations
both within e1 register 700 and within pipeline structure.
Control logic 712 comprises hardware logic for determining
operations to be performed on CAM 704 and RAM 708. Control logic
712 also comprises hardware logic for outputting address signal to
physical address decoder 702. Control logic 712 takes as input
status signals from status logic 710. Status signals drive the
selection of addresses by control logic 712. For example, status
signals may indicate that write operation should be performed on
CAM 704 and RAM 708. Control logic may then increment a pointer to
next address, indicating empty addresses within CAM 704 and RAM 708
for writing associated addresses and data words. The address signal
output from control logic 712 may comprise pointers that are
decoded by physical address decoder 702 to select appropriate
physical addresses within CAM 704 or RAM 708 for performing data
manipulation operation. The address signal output from control
logic 712 may also be output to the pipeline to indicate physical
addresses within e1 register 700.
In this way, e1 register 700 may transmit a data word, its
associated address, and its physical address within e1 register 700
to pipeline structure. The physical address within e1 register 700
may be used to update e1 register 700 control bits after verify or
re-write operation occurs. If the re-write operation failed, for
example, fail count bits within e1 register 700 may be updated
using the physical address within e1 register 700.
One of ordinary skill in the art will understand that the specific
control signals, logic and structures disclosed with respect to
FIG. 7 are merely exemplary, and illustrate one of many possible
implementations of e1 register 700. Other implementations of e1
register 700 may be used in conjunction with the teachings of the
present disclosure.
FIG. 8 is a block diagram of an embodiment of a memory device of
the present disclosure showing a last level dynamic redundancy
register. FIG. 8 shows exemplary e2 register 800 described herein
that comprises CAM/RAM/Enbl/Pointers block 802, mux 816, e2 RAM
818, and physical y-mux 832, sense amplifier 834, error correction
code bits 836, write register 838, and control logic 840. One of
ordinary skill in the art will recognize that e2 register 800 is
exemplary, and includes features such as RAM Memory bank FC 814
which are not necessary for achieving the teachings of the present
disclosure. Moreover, e2 register 800 communicates control signals
for maintaining consistency of operations both internally and to
communicate with components of memory device such as pipeline
banks, memory banks, and e1 register. Such control signals may be
modified without departing from the teachings of the present
disclosure.
CAM/RAM/Enbl/Pointers block 802 comprises physical address decoder
804, address CAM 806, RAM update flag 807, RAM enable 808, RAM e2
fail count 810, RAM used count 812, and RAM memory bank FC 814.
Thus, block 802 comprises data storage elements comprising data
bits. Block 802 is used for storing control bits and associated
addresses of data words.
Physical address decoder 804 receives an address inputs from
control logic 840. As explained in relation to e1 register and FIG.
7, physical address decoder 804 uses address inputs to determine
physical addresses for writing associated addresses and data words
to CAM 806 and RAM 818, respectively. Physical address decoder 804
outputs decode signal to CAM 806 and mux 816. Moreover, physical
address decoder 804 may output decode signal to physical y-mux
832.
CAM 806 stores associated addresses for data words. As explained in
relation to e1 register and FIG. 7, CAM 806 may take as inputs
various control signals and associated addresses. CAM 806 can then
write associated addresses to itself or determine appropriate
physical address within RAM 818 for matching data word. Typically,
such data word would be output, for example, to pipeline banks or
memory banks.
RAM update flag 807 comprises control bits for determining whether
associated data should be updated within RAM 818. For example,
control signals received from control logic 840 may indicate that
RAM 818 entry should be updated based on a new data word. RAM
update flag 807 thus provides a mechanism to track data words that
should be updated in case it is not possible to update the data
word immediately.
RAM enable 808 comprises control bits indicating whether e2 RAM 818
contains a valid data word. RAM enable 808 may thus require that
all bits be set to one, for example, to provide a stringent
mechanism to ensure that RAM 818 includes valid data. RAM enable
808 may be output to control logic 840 so that control logic may
keep track of valid data within block 802 and RAM 818. One of
ordinary skill in the art will recognize that other schemes may be
used to ensure reliability of data words. For example, multiple
copies of data word may be maintained in RAM 818 and selected based
on a voting scheme. In another scheme, a more stringent error
correction code (ECC) scheme may be performed within e2 register
800 than in memory bank. In another scheme, RAM 818 points to
particular addresses within main memory for storing data words
rather than storing the data words within e2 register 800
itself.
RAM e2 fail count 810 indicates the number of times a data word has
failed to write to e2 RAM 818. For example, RAM 818 may comprise
non-volatile STT-MRAM in an embodiment. In that case, e2 register
800 may write to RAM 818 until write operation is successful in
order to maintain reliability within e2 register 800. Thus, e2 fail
count indicates the number of times a data word has failed to write
to RAM 818. RAM e2 fail count 810 may be output to control logic
840, so that control logic 840 may output appropriate addresses for
writing to RAM 818.
RAM used count 812 indicates the number of times that a physical
address within e2 RAM 818 has been used. The e2 register 800 may
desire to keep track of the number of times that a particular
physical address within RAM 818 has been used. For example, the
number of times that a read operation has occurred, write operation
has occurred, or both to a specific physical address within RAM
818.
RAM memory bank FC 814 indicates the number of times that a data
word has failed to write to a memory bank. For example, e2 register
800 may desire to keep track of the number of times that a write
operation from e2 register 800 has failed to the memory bank. This
may be useful so that only a desired number of re-write operations
are tried. The specific components of block 802 are exemplary and
may be modified without departing from the teachings of the present
disclosure. For example, one of ordinary skill in the art will
recognize that RAM memory bank FC 814 is optional and provides a
mechanism for controlling the number of re-write attempts to memory
bank.
Mux 816 is coupled to CAM/RAM/Enbl/Pointers block 802 and e2 RAM
818. Mux 816 takes as input decode signal from physical address
decoder 804 indicating physical address within e2 RAM 818 and match
signal from CAM 806 indicating that match exists within e2 RAM 818.
Thus, as explained with respect to e1 register 700 of FIG. 7, e2
RAM 818 can perform read or write operation. If e2 RAM 818
comprises MRAM, write operations may be tried a number of times
based on RAM e2 fail count 810. In another embodiment, after a
predetermined number of write attempts to physical address within
e2 RAM 818, RAM used count 812 may operate to indicate that another
location within e2 RAM 818 should be chosen for write
operation.
The e2 RAM 818 comprises RAM data 820, RAM address 822, RAM enable
824, RAM used count 826, and Memory Bank FC 830. The e2 RAM 818 may
comprise volatile or non-volatile memory. In one embodiment, The e2
RAM 818 comprises non-volatile memory such as MRAM so that contents
may be saved on during power down.
RAM data 820 comprises data storage elements comprising data bits
storing a data word received from e1 register. RAM address 822
stores an associated address within a memory bank for the data word
stored within RAM data 820. For example, CAM 806 may store an
associated address to RAM address 822. RAM enable 824 stores the
same enable bits as RAM enable 808. RAM used count 826 stores the
same used count as in RAM used count 812. Memory Bank FC 830 stores
the same fail count as RAM Memory Bank FC 814. Thus, block 802
comprising volatile storage (e.g., SRAM) may be backed up to
non-volatile storage (e.g., MRAM).
Similar to the explanation given with respect to FIG. 4, y-mux 832
allows read and write operations to be performed on RAM 818. Sense
amplifiers 824 are used to read RAM 818. ECC block 836 allows error
correcting on RAM 818. Write Register 938 may comprise CAM for
searching write register contents. Write register 838 receives data
word and address from e1 register. Write register 838 also
communicates with e2 control logic 840 to, for example, send ready
e2 ready signal when write register 838 is ready for new data word
from e1 register.
Control logic 840 comprises hardware logic. Control logic 840
determines appropriate operations (such as read, write, and search)
to be performed on e2 register 800. Control logic 840 also
determines addresses. As previously explained in connection with
FIG. 7, control logic 840 may use many different addressing
schemes. In one embodiment, control logic 840 uses pointers to
determine physical addresses within block 802 and RAM 818 for
writing data words. Control logic 840 may also communicate with
other components of memory device including pipeline banks, memory
banks, and e1 register. For example control logic 840 transmits e2
flag to e1 register to indicate that e2 register 800 may receive a
new data word to write register 838.
The above description and drawings are only to be considered
illustrative of specific embodiments, which achieve the features
and advantages described herein. Modifications and substitutions to
specific process conditions can be made. Accordingly, the
embodiments in this patent document are not considered as being
limited by the foregoing description and drawings.
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