U.S. patent application number 17/841513 was filed with the patent office on 2022-09-29 for backside illumination type solid-state imaging device, manufacturing method for backside illumination type solid-state imaging device, imaging apparatus and electronic equipment.
This patent application is currently assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION. The applicant listed for this patent is SONY SEMICONDUCTOR SOLUTIONS CORPORATION. Invention is credited to Masaki HANEDA, Tadashi IIJIMA, Naoki KOMAI, Masaya NAGATA, Yoichi OOTSUKA, Suguru SAITO, Taizo TAKACHI, Kaori TAKIMOTO, Satoru WAKIYAMA, Yuichi YAMAMOTO.
Application Number | 20220310680 17/841513 |
Document ID | / |
Family ID | 1000006402608 |
Filed Date | 2022-09-29 |
United States Patent
Application |
20220310680 |
Kind Code |
A1 |
TAKACHI; Taizo ; et
al. |
September 29, 2022 |
BACKSIDE ILLUMINATION TYPE SOLID-STATE IMAGING DEVICE,
MANUFACTURING METHOD FOR BACKSIDE ILLUMINATION TYPE SOLID-STATE
IMAGING DEVICE, IMAGING APPARATUS AND ELECTRONIC EQUIPMENT
Abstract
The present disclosure relates to a backside illumination type
solid-state imaging device, a manufacturing method for a backside
illumination type solid-state imaging device, an imaging apparatus,
and electronic equipment by which the manufacturing cost can be
reduced. A singulated memory circuit and a singulated logic circuit
are laid out in a horizontal direction and are embedded by an oxide
film and flattened, and then are stacked so as to be contained in a
plane direction under a solid-state imaging element. The present
disclosure can be applied to an imaging apparatus.
Inventors: |
TAKACHI; Taizo; (Kanagawa,
JP) ; YAMAMOTO; Yuichi; (Kanagawa, JP) ;
SAITO; Suguru; (Kanagawa, JP) ; WAKIYAMA; Satoru;
(Kanagawa, JP) ; OOTSUKA; Yoichi; (Kanagawa,
JP) ; KOMAI; Naoki; (Kanagawa, JP) ; TAKIMOTO;
Kaori; (Kanagawa, JP) ; IIJIMA; Tadashi;
(Kanagawa, JP) ; HANEDA; Masaki; (Kanagawa,
JP) ; NAGATA; Masaya; (Kanagawa, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SONY SEMICONDUCTOR SOLUTIONS CORPORATION |
Kanagawa |
|
JP |
|
|
Assignee: |
SONY SEMICONDUCTOR SOLUTIONS
CORPORATION
Kanagawa
JP
|
Family ID: |
1000006402608 |
Appl. No.: |
17/841513 |
Filed: |
June 15, 2022 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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16758535 |
Apr 23, 2020 |
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PCT/JP2018/038423 |
Oct 16, 2018 |
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17841513 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/14603 20130101;
H01L 27/1464 20130101; H01L 27/14636 20130101 |
International
Class: |
H01L 27/146 20060101
H01L027/146 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 30, 2017 |
JP |
2017-208864 |
Mar 28, 2018 |
JP |
2018-062477 |
Claims
1-26. (canceled)
27. A light detecting device comprising: a first section including:
a first semiconductor element including a first semiconductor
substrate at a light incident side and a first multilayer wiring
layer at a opposite side of the light incident side; and a second
section including: a second semiconductor element including a
second semiconductor substrate and a second multilayer wiring
layer; and a third semiconductor element including a third
semiconductor substrate and a third multilayer wiring layer,
wherein the first semiconductor element and the second
semiconductor element are bonded together such that the first
multilayer wiring layer and the second multilayer wiring layer face
each other, wherein the first semiconductor element and the third
semiconductor element are bonded together such that the first
multilayer wiring layer and the third multilayer wiring layer face
each other, and wherein a size of the first semiconductor element
is larger than a size of the second semiconductor element.
28. The light detecting device according to claim 27, wherein the
size of the first semiconductor element is larger than a size of
the third semiconductor element.
29. The light detecting device according to claim 27, wherein the
size of the second semiconductor element is larger than a size of
the third semiconductor element.
30. The light detecting device according to claim 27, wherein the
first, second, and third multilayer wiring layers include a
plurality of pads, wherein the plurality of pads of the first and
second multilayer wiring layers are directly bonded, and wherein
the plurality of pads of the first and third multilayer wiring
layers are directly bonded.
31. The light detecting device according to claim 30, wherein the
plurality of pads are directly bonded with a CuCu connection.
32. The light detecting device according to claim 27, wherein the
second section further includes an insulation film.
33. The light detecting device according to claim 32, wherein the
second and the third semiconductor elements are covered by the
insulation film.
34. The light detecting device according to claim 32, wherein the
second semiconductor element other than a bonding surface is
covered by the insulation film.
35. The light detecting device according to claim 32, wherein the
third semiconductor element other than a bonding surface is covered
by the insulation film.
36. The light detecting device according to claim 32, wherein at
least a portion of the insulation film is disposed between the
second and the third semiconductor elements in a cross-sectional
view.
37. The light detecting device according to claim 27, wherein the
first semiconductor substrate includes photoelectric conversion
elements configured to generate pixel signals.
38. The light detecting device according to claim 27, wherein the
second semiconductor substrate includes a first signal process
circuit configured to process pixel signals.
39. The light detecting device according to claim 27, wherein the
third semiconductor substrate includes a second signal process
circuit configured to process pixel signals.
40. The light detecting device according to claim 27, wherein the
second semiconductor substrate includes a memory circuit.
41. The light detecting device according to claim 27, wherein the
third semiconductor substrate includes a logic circuit.
42. An imaging apparatus comprising: a backside illumination type
solid-state imaging device that includes: a first section
including: a first semiconductor element including a first
semiconductor substrate at a light incident side and a first
multilayer wiring layer at a opposite side of the light incident
side; and a second section including: a second semiconductor
element including a second semiconductor substrate and a second
multilayer wiring layer; and a third semiconductor element
including a third semiconductor substrate and a third multilayer
wiring layer, wherein the first semiconductor element and the
second semiconductor element are bonded together such that the
first multilayer wiring layer and the second multilayer wiring
layer face each other, wherein the first semiconductor element and
the third semiconductor element are bonded together such that the
first multilayer wiring layer and the third multilayer wiring layer
face each other, and wherein a size of the first semiconductor
element is larger than a size of the second semiconductor
element.
43. The imaging apparatus according to claim 42, wherein the first
semiconductor substrate includes photoelectric conversion elements
configured to generate pixel signals.
44. The imaging apparatus according to claim 42, wherein the second
semiconductor substrate includes a memory circuit.
45. The imaging apparatus according to claim 42, wherein the third
semiconductor substrate includes a logic circuit.
46. The imaging apparatus according to claim 42, wherein the size
of the first semiconductor element is larger than a size of the
third semiconductor element, and wherein the size of the second
semiconductor element is larger than the size of the third
semiconductor element.
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a backside illumination
type solid-state imaging device, a manufacturing method for a
backside illumination type solid-state imaging device, an imaging
apparatus and electronic equipment, and particularly to a backside
illumination type solid-state imaging device, a manufacturing
method for a backside illumination type solid-state imaging device,
an imaging apparatus and electronic equipment by which the
manufacturing cost can be reduced.
BACKGROUND ART
[0002] A solid-state imaging device achieves high picture quality
in the form of Hi-Vision, 4 k.times.2 k Super Hi-Vision and a super
slow-motion function, and together with this, the number of pixels
increases and a high frame rate and a high gradation are
attained.
[0003] Since the transmission rate is calculated by the number of
pixels.times.frame rate.times.gradation, for example, in the case
of 4 k.times.2 k=8M pixels, a frame rate of 240 f/s and a gradation
of 14 bits, the transmission rate is 8M.times.240 f/s.times.14
bits=26 Gbps.
[0004] After signal processing by the succeeding stage of a
solid-state imaging element, RGB signals of a color coordinate are
outputted, and therefore, higher-speed transmission of
26G.times.3=78 Gbps is required.
[0005] If high-speed transmission is performed with a reduced
number of connection terminals, then the signal rate per one
connection terminal becomes high and the difficulty for impedance
matching of a high-speed transmission path increases. Further,
since not only the clock frequency but also the loss increases,
power consumption increases.
[0006] In order to avoid this, it is sufficient if the number of
connection terminals is increased such that transmission is divided
to decrease the signal rate. However, increase of the number of
connection terminals increases the package size of individual
circuits because terminals necessary for connection between a
solid-state imaging element and a signal processing circuit or a
memory circuit on the following stage are arranged.
[0007] Also, as a substrate for electric wiring necessary for a
signal processing circuit or a memory circuit on the succeeding
stage, a substrate having a finer wire density based on stacked
wiring is required, and this further increases the wiring path
length. Together with this, the power consumption increases.
[0008] If the package size of individual circuits becomes great,
then also the size of a substrate itself for mounting becomes
great, and the imaging apparatus configuration itself in which the
solid-state imaging element is to be incorporated finally becomes
great.
[0009] Therefore, as a technology for downsizing the configuration
of an imaging apparatus, a technology is proposed by which a
solid-state imaging element and a circuit such as a signal
processing circuit or a memory circuit are stacked by WoW (Wafer on
Wafer) for connecting the circuits both in the form of a wafer
(refer to PTL 1).
[0010] Since, by a stacking technology using the WoW, a
semiconductor can be connected by many fine wires, the transmission
speed per one wire becomes low and the power consumption can be
suppressed.
CITATION LIST
Patent Literature
[0011] [PTL 1] [0012] Japanese Patent Laid-Open No. 2014-099582
SUMMARY
Technical Problem
[0013] However, in the case of the WoW, if chips of wafers to be
stacked have a same size, there is no problem. However, if the
sizes of the chips configured as wafers are different from each
other, then the sizes must be adjusted to that of the greatest
chip, and the theoretical yield for each circuit is degraded and
the cost increases.
[0014] Further, in regard to the yield of each of wafers to be
stacked, by a defect of a chip of each wafer, also a chip of the
stacked wafers is treated as a defect, and since the yield of the
wafers in the entire stacked layers is given by the product (cross)
of the yields of the wafers, the yield is degraded and the cost
increases.
[0015] Also, a technology has been proposed by which chips whose
sizes are different from each other are connected to each other by
forming small bumps on them. In this case, since chips selected as
good products and having different sizes are connected through the
bumps, the influence of the theoretical yield difference between
the wafers and the yield of the chips is small.
[0016] However, since it is difficult to form small bumps and the
connection pitch is limited, a greater number of connection
terminals than that by the WoW cannot be obtained. Further, since
the connection is performed by a mounting process, if the number of
connection terminals increases, then the cost increases due to
yield degradation by the connection. Further, since also connection
in the mounting process is performed for individual wires, long
time is required for the connection and the process cost
increases.
[0017] The present disclosure has been made in view of such a
situation as described above and specifically makes it possible to
reduce the manufacturing cost of a solid-state imaging device.
Solution to Problem
[0018] A solid-state imaging element of one aspect of the present
disclosure is a backside illumination type solid-state imaging
device including: a first semiconductor element including an
imaging element configured to generate a pixel signal in a unit of
a pixel; a second semiconductor element in which signal processing
circuits necessary for signal processing of the pixel signal are
embedded by an embedding member; and a wire that electrically
connects the first semiconductor element and the second
semiconductor element; the first semiconductor element and the
second semiconductor element being stacked by oxide film
joining.
[0019] The first semiconductor element may be greater than the
second semiconductor element.
[0020] The first semiconductor element may smaller than the second
semiconductor element.
[0021] The backside illumination type solid-state imaging device
may be configured such that the signal processing circuits include
a first signal processing circuit and a second signal processing
circuit, and the second semiconductor element has therein the first
signal processing circuit and the second signal processing circuit
arranged in a juxtaposed relation in a horizontal direction and
embedded by the embedding member.
[0022] The backside illumination type solid-state imaging device
may be configured such that the signal processing circuits include
a first signal processing circuit and a second signal processing
circuit, the wire includes a first wire and a second wire, the
second semiconductor element has therein the first signal
processing circuit embedded by the embedding member, the
solid-state imaging device includes a third semiconductor element
in which the second signal processing circuit is embedded by the
embedding member, the first wire electrically connects the first
semiconductor element and the second semiconductor element to each
other, the second wire electrically connects the second
semiconductor element and the third semiconductor element to each
other, and the second semiconductor element and the third
semiconductor element are stacked by oxide film joining.
[0023] The wire may be joined by CuCu joining.
[0024] The wire may electrically connect the first semiconductor
element and the second semiconductor element through a
through-via.
[0025] The wire may electrically connect the first semiconductor
element and the second semiconductor element through a through-via
formed from an imaging face side of the imaging element.
[0026] The wire may electrically connect the first semiconductor
element and the second semiconductor element through a through-via
formed from a face on an opposite side to an imaging face of the
imaging element.
[0027] The embedding member may include an oxide film.
[0028] The embedding member may include an organic material.
[0029] The backside illumination type solid-state imaging device
may be configured such that, in the second semiconductor element,
the signal processing circuits are laid out such that a gap between
the signal processing circuits is minimized, and the gap is filled
with the embedding member including the organic material.
[0030] In the second semiconductor element, in addition to the
signal processing circuits, a dummy circuit configured from a
semiconductor element and including a dummy wire may be embedded by
the embedding member.
[0031] A heat dissipation member that includes a member having a
thermal conductivity higher than a predetermined thermal
conductivity and dissipates heat may be stacked on a face of the
second semiconductor element opposite to a face on which the first
semiconductor element is stacked.
[0032] The heat dissipation member may include SiC, AlN, SIN, Cu,
Al, and C.
[0033] The heat dissipation member may include a waterway for
circulating cooling water.
[0034] The signal processing circuits may include a logic circuit,
a memory circuit, a power supply circuit, an image signal
compression circuit, a clock circuit, and an optical communication
conversion circuit.
[0035] The signal processing circuits may be embedded in the first
semiconductor element by the embedding member.
[0036] The signal processing circuits may be each embedded by the
embedding member after contacted at part thereof in a positioned
state with the first semiconductor element and gradually joined to
the first semiconductor element beginning with a portion around the
contacted portion.
[0037] The part may include an end side and an end point of the
signal processing circuit.
[0038] The signal processing circuit may be smaller than the first
semiconductor element.
[0039] The signal processing circuits may be each embedded by the
embedding member after contacted at part thereof in a positioned
state with the second semiconductor element and gradually joined to
the second semiconductor element beginning with a portion around
the contacted portion.
[0040] The part may include an end side and an end point of the
signal processing circuit.
[0041] A manufacturing method for a solid-state imaging device of
one aspect of the present disclosure is a manufacturing method for
a backside illumination type solid-state imaging device that
includes a first semiconductor element including an imaging element
configured to generate a pixel signal in a unit of a pixel, a
second semiconductor element in which signal processing circuits
necessary for signal processing of the pixel signal are embedded by
an embedding member, and a wire that electrically connects the
first semiconductor element and the second semiconductor element,
the first semiconductor element and the second semiconductor
element being stacked by oxide film joining. A first wafer
including the imaging element formed by a semiconductor process and
a second wafer in which the signal processing circuit decided as a
good product by electric inspection from among the signal
processing circuits formed by a semiconductor process is rearranged
and embedded by the embedding member are stacked by oxide film
joining such that the wire between the first semiconductor element
and the second semiconductor element is electrically connected and
then are singulated.
[0042] An imaging apparatus of one aspect of the present disclosure
is an imaging apparatus including a backside illumination type
solid-state imaging device that includes a first semiconductor
element including an imaging element configured to generate a pixel
signal in a unit of a pixel, a second semiconductor element in
which signal processing circuits necessary for signal processing of
the pixel signal are embedded by an embedding member, and a wire
that electrically connects the first semiconductor element and the
second semiconductor element, the first semiconductor element and
the second semiconductor element being stacked by oxide film
joining.
[0043] Electronic equipment of one aspect of the present disclosure
is electronic equipment including a backside illumination type
solid-state imaging device that includes a first semiconductor
element including an imaging element configured to generate a pixel
signal in a unit of a pixel, a second semiconductor element in
which signal processing circuits necessary for signal processing of
the pixel signal are embedded by an embedding member, and a wire
that electrically connects the first semiconductor element and the
second semiconductor element, the first semiconductor element and
the second semiconductor element being stacked by oxide film
joining.
[0044] According to one aspect of the present disclosure, the first
semiconductor element including the imaging element configured to
generate a pixel signal in a unit of a pixel and the second
semiconductor device in which signal processing circuits necessary
for signal processing of the pixel signal are embedded by the
embedding member are electrically connected by the wire, and the
first semiconductor element and the second semiconductor element
are stacked by oxide film joining.
Advantageous Effect of the Invention
[0045] According to one aspect of the present disclosure, the
manufacturing cost especially of the solid-state imaging device can
be decreased.
BRIEF DESCRIPTION OF DRAWINGS
[0046] FIG. 1 is a view illustrating the yield.
[0047] FIG. 2 is a view illustrating reduction of the theoretical
yield.
[0048] FIG. 3 is a view illustrating connection using a bump.
[0049] FIG. 4 is a view illustrating an overview of a manufacturing
method for a solid-state imaging device of a first embodiment of
the present disclosure.
[0050] FIG. 5 is a view illustrating an example of a configuration
of the solid-state imaging device of the first embodiment of the
present disclosure.
[0051] FIG. 6 is a view illustrating the manufacturing method for a
solid-state imaging device of FIG. 5.
[0052] FIG. 7 is a view illustrating the manufacturing method for a
solid-state imaging device of FIG. 5.
[0053] FIG. 8 is a view illustrating the manufacturing method for a
solid-state imaging device of FIG. 5.
[0054] FIG. 9 is a view illustrating the manufacturing method for a
solid-state imaging device of FIG. 5.
[0055] FIG. 10 is a view illustrating an overview of a
manufacturing method for a solid-state imaging device of a second
embodiment of the present disclosure.
[0056] FIG. 11 is a view illustrating an example of a configuration
of a solid-state imaging device of the second embodiment of the
present disclosure.
[0057] FIG. 12 is a view illustrating the manufacturing method for
a solid-state imaging device of FIG. 10.
[0058] FIG. 13 is a view illustrating the manufacturing method for
a solid-state imaging device of FIG. 10.
[0059] FIG. 14 is a view illustrating an example of a configuration
of a solid-state imaging device of a third embodiment of the
present disclosure.
[0060] FIG. 15 is a view illustrating the manufacturing method for
the solid-state imaging device of FIG. 14.
[0061] FIG. 16 is a view illustrating the manufacturing method for
the solid-state imaging device of FIG. 14.
[0062] FIG. 17 is a view illustrating an example of a configuration
of a solid-state imaging device of a fourth embodiment of the
present disclosure.
[0063] FIG. 18 is a view illustrating an example of a configuration
of a solid-state imaging device of a fifth embodiment of the
present disclosure.
[0064] FIG. 19 is a view illustrating a manufacturing method of the
solid-state imaging device of FIG. 18.
[0065] FIG. 20 is a view illustrating the manufacturing method of
the solid-state imaging device of FIG. 18.
[0066] FIG. 21 is a view illustrating the manufacturing method of
the solid-state imaging device of FIG. 18.
[0067] FIG. 22 is a view illustrating the manufacturing method of
the solid-state imaging device of FIG. 18.
[0068] FIG. 23 is a view illustrating an example of a configuration
of a solid-state imaging device that is a modification of the fifth
embodiment of the present disclosure.
[0069] FIG. 24 is a view illustrating an overview of a
manufacturing method of a solid-state imaging device of a sixth
embodiment of the present disclosure.
[0070] FIG. 25 is a view illustrating an example of a configuration
of a solid-state imaging device of a sixth embodiment of the
present disclosure.
[0071] FIG. 26 is a view illustrating a manufacturing method of the
solid-state imaging device of FIG. 25.
[0072] FIG. 27 is a view illustrating the manufacturing method of
the solid-state imaging device of FIG. 25.
[0073] FIG. 28 is a view illustrating the manufacturing method of
the solid-state imaging device of FIG. 25.
[0074] FIG. 29 is a view illustrating a first connection example to
the solid-state imaging element.
[0075] FIG. 30 is a view illustrating a manufacturing method of the
solid-state imaging device of FIG. 29.
[0076] FIG. 31 is a view illustrating the manufacturing method of
the solid-state imaging device of FIG. 29.
[0077] FIG. 32 is a view illustrating the manufacturing method of
the solid-state imaging device of FIG. 29.
[0078] FIG. 33 is a view illustrating a second connection example
to the solid-state imaging element.
[0079] FIG. 34 is a view illustrating a manufacturing method of the
solid-state imaging device of FIG. 33.
[0080] FIG. 35 is a view illustrating the manufacturing method of
the solid-state imaging device of FIG. 33.
[0081] FIG. 36 is a view illustrating the manufacturing method of
the solid-state imaging device of FIG. 33.
[0082] FIG. 37 is a view illustrating a first modification of the
connection example to the solid-state imaging element.
[0083] FIG. 38 is a view illustrating a second modification of the
connection example to the solid-state imaging element.
[0084] FIG. 39 is a view illustrating a third modification of the
connection example to the solid-state imaging element.
[0085] FIG. 40 is a view illustrating a fourth modification of the
connection example to the solid-state imaging element.
[0086] FIG. 41 is a view illustrating a fifth modification of the
connection example to the solid-state imaging element.
[0087] FIG. 42 is a view illustrating a sixth modification of the
connection example to the solid-state imaging element.
[0088] FIG. 43 is a view illustrating a heat dissipation structure
of the solid-state imaging device.
[0089] FIG. 44 is a view illustrating a manufacturing method of the
solid-state imaging device.
[0090] FIG. 45 is a view illustrating a first modification of the
heat dissipation structure of the solid-state imaging device.
[0091] FIG. 46 is a view illustrating a second modification of the
heat dissipation structure of the solid-state imaging device.
[0092] FIG. 47 is a view illustrating a third modification of the
heat dissipation structure of the solid-state imaging device.
[0093] FIG. 48 is a view illustrating a fourth modification of the
heat dissipation structure of the solid-state imaging device.
[0094] FIG. 49 is a block diagram depicting an example of a
configuration of an imaging apparatus as electronic equipment to
which the configuration of the imaging apparatus of the present
disclosure is applied.
[0095] FIG. 50 is a view illustrating an example of use of the
imaging apparatus to which the technology of the present disclosure
is applied.
[0096] FIG. 51 is a view depicting an example of a schematic
configuration of an endoscopic surgery system.
[0097] FIG. 52 is a block diagram depicting an example of a
functional configuration of a camera head and a camera control unit
(CCU).
[0098] FIG. 53 is a block diagram depicting an example of schematic
configuration of a vehicle control system.
[0099] FIG. 54 is a diagram of assistance in explaining an example
of installation positions of an outside-vehicle information
detecting section and an imaging section.
DESCRIPTION OF EMBODIMENTS
[0100] In the following, a mode for carrying out the present
disclosure is described. It is to be noted that, in the present
specification and the drawings, components having substantially
same functional configurations are denoted by same reference signs,
and overlapping description of them is omitted.
[0101] The description is given in the following order.
[0102] 1. Overview of the Present Disclosure
[0103] 2. First Embodiment
[0104] 3. Second Embodiment
[0105] 4. Third Embodiment
[0106] 5. Fourth Embodiment
[0107] 6. Fifth Embodiment
[0108] 7. Modification of Fifth Embodiment
[0109] 8. Sixth Embodiment
[0110] 9. Example of Connection to Solid-State Imaging Element
[0111] 10. Modification of Example of Connection to Solid-State
Imaging Element
[0112] 11. Heat Dissipation Structure
[0113] 12. Example of Application to Electronic Equipment
[0114] 13. Example of Use of Imaging Element
[0115] 14. Example of Application to Endoscopic Surgery System
[0116] 15. Example of Application to Mobile Body
1. Overview of the Present Disclosure
[0117] The present disclosure reduces the manufacturing cost of a
solid-state imaging device.
[0118] Here, before the present disclosure is described, the WoW
(Wafer on Wafer) disclosed in PTL 1 is described.
[0119] The WoW is a technology for joining and stacking a
solid-state imaging device, a signal processing circuit, and
circuits including ICs such as memory circuits each in the form of
wafer, for example, as depicted in FIG. 1.
[0120] FIG. 1 schematically represents a WoW in which a wafer W1 on
which a plurality of solid-state imaging elements 11 is formed, a
wafer W2 on which a plurality of memory circuits 12 is formed, and
a wafer W3 on which a plurality of logic circuits 13 is formed are
joined to and stacked on each other in a state in which they are
positioned accurately relative to each other.
[0121] By singulating the wafers stacked in this manner, such a
solid-state imaging device as depicted, for example, in FIG. 2 is
formed.
[0122] The solid-state imaging device 1 of FIG. 2 is configured
such that an on-chip lens and on-chip color filter 10, a
solid-state imaging element 11, a memory circuit 12, a logic
circuit 13 and a support substrate 14 are stacked in this order
from above.
[0123] Here, by applying the technology of the WoW, wires 21-1 for
electrically connecting the solid-state imaging element 11 and the
memory circuit 12 and wires 21-2 for electrically connecting the
memory circuit 12 and the logic circuit 13 can be connected at a
fine pitch.
[0124] As a result, since the number of wires can be increased, the
transmission speed in signal lines can be reduced and power saving
can be anticipated.
[0125] However, since the areas necessitated for the solid-state
imaging element 11, memory circuit 12 and logic circuit 13 to be
stacked are different from one another, a space Z1 in which neither
circuit nor wire are formed appears on the left and right in the
figure of the memory circuit 12 that has an area smaller than that
of the solid-state imaging element 11 that is greatest. Further, on
the left and right of the logic circuit that has an area smaller
than that of the memory circuit 12, a space Z2 in which neither
circuit nor wire are formed appears.
[0126] In particular, the spaces Z1 and Z2 appear arising from that
the areas necessitated by the solid-state imaging element 11,
memory circuit 12 and logic circuit 13 are different from one
another and, in FIG. 2, arising from that the they are stacked with
reference to the solid-state imaging element 11 for which the
largest area is necessitated.
[0127] This decreases the theoretical yield relating to manufacture
of the solid-state imaging device 1 and, as a result, increases the
cost required for manufacture.
[0128] Further, in FIG. 1, elements that are defective in the
solid-state imaging element 11, the memory circuit 12, and the
logic circuit 13 formed on the wafers W1 to W3, respectively, are
individually represented by filled cells. In particular, FIG. 1
depicts that two defective elements appear in each of the wafers W1
to W3.
[0129] As depicted in FIG. 1, the defective elements appearing in
the solid-state imaging element 11, the memory circuit 12, and the
logic circuit 13 formed on the wafers W1 to W3, respectively, are
not necessarily formed at same positions. Therefore, as depicted in
FIG. 1, in the solid-state imaging device 1 formed from the stack
suffer from six defectives each indicated by a cross mark applied
to the wafer W1 of the solid-state imaging element 11.
[0130] Consequently, in the six defective solid-state imaging
devices 1, although at least two parts from among the three parts
of the solid-state imaging element 11, memory circuit 12 and logic
circuit 13 are not defective, they are treated as six defectives.
Thus, although it is sufficient if the yield in regard to each part
is two, the yield in regard to each part becomes six that is equal
to an integrated number by the number of wafers.
[0131] As a result, the yield of the solid-state imaging devices 1
is decreased and the manufacturing cost is increased.
[0132] Further, as depicted in FIG. 3, it is conceivable to
singulate solid-state imaging elements 11, memory circuits 12 and
logic circuits 13 having chip sizes different from each other,
selectively arrange only good products and form small bumps to
connect them.
[0133] In the solid-state imaging device 1 of FIG. 3, an on-chip
lens and on-chip color filter 10 and a solid-state imaging element
11 are stacked from above, and below them, a memory circuit 12 and
a logic circuit 13 are stacked in a same layer, under which a
support substrate 14 is provided and stacked. Further, the
solid-state imaging element 11 and the memory circuit 12 and logic
circuit 13 that are arranged in the same layer are electrically
connected to each other through small-sized bumps 31.
[0134] In the solid-state imaging device 1 of FIG. 3, chips of
sizes selected as good products are connected through the bumps 31
and the theoretical yield difference between the wafers and the
influence of the yields the chips are reduced.
[0135] However, formation of the small-sized bumps 31 is difficult,
and since there is a limitation to decrease of the connection
pitches d2 as depicted in FIG. 3, the connection pitches d2 cannot
be made smaller than the connection pitches d1 of FIG. 2 in the
case where the WoW is used.
[0136] Therefore, the solid-state imaging device 1 of FIG. 3 in
which the chips are stacked using bumps cannot have a great number
of connection terminals in comparison with the solid-state imaging
device 1 of FIG. 2 stacked by the WoW. Further, in the case of the
connection that uses bumps like the solid-state imaging device 1 of
FIG. 3, if the connection terminal number increases, then since the
connection terminals are joined by a mounting process, reduction of
the yield relating to joining occurs and increases the cost.
Further, since the connection of the bumps in the mounting process
is performed by individual works, each process requires long time
and also the process cost increases.
[0137] From the foregoing, the imaging element of the present
disclosure decreases the cost for manufacture in terms of the
theoretical yield, implementation cost and process cost.
2. First Embodiment
[0138] FIG. 4 is a view illustrating a structure in which a
plurality of wafers is stacked by the WoW technology that is
applied when the solid-state imaging device of the present
disclosure is to be manufactured.
[0139] In manufacturing the solid-state imaging device of the
present disclosure, two wafers including a wafer 101 on which a
plurality of solid-state imaging element (CMOS (Complementary Metal
Oxide Semiconductor)) image sensors and CCDs (Charge Coupled
Devices) 120 are formed and a wafer 102 on which memory circuits
121 and logic circuits 122 are rearranged are stacked in a state in
which wires are positioned accurately relative to each other.
[0140] The wafer 101 has a plurality of solid-state imaging
elements 120 formed thereon by a semiconductor process.
[0141] The wafer 102 has rearranged thereon a plurality of memory
circuits 121 that has been subjected, after the memory circuits 121
have been formed on a wafer 103 by a semiconductor process and
singulated, to electric inspection individually and has been
confirmed as good chips through the electric inspection.
[0142] The wafer 102 has rearranged thereon a plurality of logic
circuits 122 that has been subjected, after the logic circuits 122
have been formed on a wafer 104 by a semiconductor process and
singulated, to electric inspection individually and has been
confirmed as good chips through the electric inspection.
[0143] <Example of configuration of solid-state imaging device
including wafers stacked by WoW technology of FIG. 4>
[0144] After a plurality of wafers is stacked by such a WoW
technology as depicted in FIG. 4, the wafers are singulated to
configure a solid-state imaging device 111 (FIG. 5) of the present
disclosure.
[0145] The solid-state imaging device of the present disclosure has
such a configuration, for example, as depicted in FIG. 5. It is to
be noted that, in FIG. 5, an upper stage is a side elevational
sectional view and a lower stage is a view illustrating an
arrangement relation in a horizontal direction when the solid-state
imaging element 120, memory circuit 121 and logic circuit 122 are
viewed from above.
[0146] In the solid-state imaging device 111 at the upper stage of
FIG. 5, an on-chip lens and on-chip color filter 131 and a
solid-state imaging element 120 are stacked from above in the
figure, and below them, a memory circuit 121 and a logic circuit
122 are arranged left and right and stacked in a same layer, below
which a support substrate 132 is formed. In other words, as
depicted by the upper stage of FIG. 5, the solid-state imaging
device 111 of FIG. 5 has: a semiconductor device element E1
including the solid-state imaging element 120 including the wafer
101; and a semiconductor element layer E2 formed on the wafer 102
and including the memory circuit 121 and the logic circuit 122.
[0147] Of terminals 120a of the solid-state imaging element 120,
the terminals 120a on the memory circuit 121 are electrically
connected to wires 134 connected by CuCu connection to terminals
121a of the memory circuit 121.
[0148] Further, of the terminals 120a of the solid-state imaging
element 120, the terminals 120a on the logic circuit 122 are
electrically connected to wires 134 connected to terminals 122a of
the logic circuit 122 by CuCu connection.
[0149] A space around the memory circuit 121 and the logic circuit
122 in the semiconductor element layer E2 in which memory circuit
121 and the logic circuit 122 are formed is in a state in which it
is filled with an oxide film 133. Consequently, in the
semiconductor element layer E2, the memory circuit 121 and the
logic circuit 122 are in a state in which they are embedded in the
oxide film 133. Further, on the boundary between the semiconductor
element layer E1 in which the solid-state imaging element 120 is
formed and the semiconductor element layer E2 in which the memory
circuit 121 and the logic circuit 122 are formed, an oxide film
joining layer 135 is formed and joins them together by oxide film
joining. Furthermore, the semiconductor element layer E2 of the
memory circuit 121 and the logic circuit 122 and the support
substrate 132 are joined together by an oxide film joining layer
135 formed between them by oxide film joining.
[0150] Further, as depicted at the lower stage of FIG. 5, the
memory circuit 121 and the logic circuit 122 are arranged such that
they are included in a range in which the solid-state imaging
element 120 of the uppermost layer is contained as viewed from
above. By such arrangement, in the layer of the memory circuit 121
and the logic circuit 122, the free space other than the memory
circuit 121 and the logic circuit 122 is reduced, and therefore,
theoretical yield can be improved.
[0151] On the wafer 102 of FIG. 4, when each solid-state imaging
device 111 is singulated, the memory circuit 121 and the logic
circuit 122 are rearranged in an elaborately adjusted state such
that they are arranged in a range of the solid-state imaging
element 120 as viewed from above.
[0152] <Manufacturing method of solid-state imaging device of
FIG. 5>
[0153] Now, a manufacturing method of the solid-state imaging
device 111 of FIG. 5 is described with reference to FIGS. 6 to 9.
It is to be noted that side elevational sectional views 6A to 6L of
FIGS. 6 to 9 depict side elevational sectional views of the
solid-state imaging device 111.
[0154] At a first step, as depicted by the side elevational
sectional view 6A of FIG. 6, after electric inspection is
performed, a memory circuit 121 and a logic circuit 122 that have
been confirmed as good products are rearranged on a rearrangement
substrate 151 such that they have such a layout as depicted at the
lower stage of FIG. 5. On the rearrangement substrate 151, adhesive
152 is applied, and the memory circuit 121 and the logic circuit
122 are rearranged on and fixed to the rearrangement substrate 151
by the adhesive 152.
[0155] At a second step, as depicted by the side elevational
sectional view 6B of FIG. 6, the memory circuit 121 and the logic
circuit 122 depicted in the side elevational sectional view 6A are
reversed such that the upper face thereof becomes a lower face, and
an oxide film joining layer 135 is formed on a support substrate
161 flattened by an oxide film formed thereon and is joined by
oxide film joining.
[0156] At a third step, the rearrangement substrate 151 is
debonded, exfoliated, and removed together with the adhesive 152 as
depicted in the side elevational sectional view 6C of FIG. 6.
[0157] At a fourth step, as depicted in the side elevational
sectional view 6D of FIG. 7, the silicon layer at the upper face
portion in the figure of the memory circuit 121 and the logic
circuit 122 is thinned to such a height H that does not have an
influence on a property of the devices.
[0158] At a fifth step, as depicted by the side elevational
sectional view 6E of FIG. 7, an oxide film 133 that functions as an
insulating film is formed to embed the chip including the
rearranged memory circuit 121 and logic circuit 122. At this time,
the face of the oxide film 133 is flattened at a height
corresponding to the memory circuit 121 and the logic circuit
122.
[0159] At a sixth step, as depicted by the side elevational
sectional view of FIG. 6F of FIG. 7, an oxide film joining layer
135 is formed on the flattened oxide film 133 and a support
substrate 171 is joined to the oxide film 133 by oxide film
joining.
[0160] At a seventh step, as depicted by the side elevational
sectional view 6G of FIG. 8, the support substrate 171 is removed
by debonding or etching. By the processes from the first step to
the seventh step, the wafer 102 is placed into a completed state in
which the memory circuit 121 and the logic circuit 122 are
rearranged in the layout depicted at the lower stage of FIG. 5 and
filled with the insulating film including the oxide film 133 and
has the oxide film joining layer 135 formed on the flattened
uppermost face.
[0161] At an eighth step, as depicted by the side elevational
sectional view 6H of FIG. 8, wires 134 are formed for terminals
121a of the memory circuit 121 and terminals 122a of the logic
circuit 122 for electrically connecting to the solid-state imaging
element 120.
[0162] At a ninth step, as depicted by the side elevational
sectional view 6I of FIG. 8, positioning is performed such that the
wires 134 from the terminals 121a of the memory circuit 121 and the
terminals 122a of the logic circuit 122 of the wafer 102 and the
wires 134 from the terminals 120a of the solid-state imaging
element 120 of the wafer 101 are positioned in an appropriately
opposing relation to each other.
[0163] At a tenth step, as depicted by the side elevational
sectional view 6J of FIG. 9, the wafers 101 and 102 are pasted to
each other by the WoW such that the wires 134 from the terminals
121a of the memory circuit 121 and the terminals 122a of the logic
circuit 122 of the wafer 102 and the wires 134 from the terminals
120a of the solid-state imaging element 120 of the wafer 101 are
connected by CuCu joining. By this process, the memory circuits 121
and the logic circuits 122 of the wafer 102 are placed into an
electrically connected state to the individual solid-state imaging
elements 120 of the wafer 101.
[0164] At an eleventh step, as depicted by the side elevational
sectional view 6K of FIG. 9, the silicon layer that is an upper
layer in the figure of the solid-state imaging element 120 is
thinned.
[0165] At a twelfth step, as depicted by the side elevational
sectional view 6L of FIG. 9, an on-chip lens and on-chip color
filter 131 is provided on the solid-state imaging element 120 and
singulation is performed to form the solid-state imaging device
111.
[0166] By such steps as described above, the solid-state imaging
device 111 including the first layer on which the solid-state
imaging element 120 is formed and the second layer on which the
memory circuit 121 and the logic circuit 122 are formed is
manufactured.
[0167] By such configuration as described above, since circuit
connection between the solid-state imaging element 120 and the
memory circuit 121 and the logic circuit 122 can be established
through terminals formed in a wire density of fine wires by a
lithography technique of semiconductors similarly as in the WoW,
the number of connection terminals can be increased and the signal
processing speed by each wire can be reduced. Therefore, reduction
of the power consumption can be anticipated.
[0168] Further, since the memory circuit 121 and the logic circuit
122 are connected only where they are good chips, defective wafers
that are a defect of the WoW decrease, and therefore, occurrence of
the yield loss can be reduced.
[0169] Furthermore, since the memory circuit 121 and the logic
circuit to be connected can be formed, different from the WoW, in a
size as small as possible irrespective of the chip size of the
solid-state imaging element 120 and arranged each in the shape of
an independent island as indicated by the lower stage of FIG. 5,
the theoretical yield of the memory circuit 12 and the logic
circuit 122 to be connected can be improved.
[0170] In this regard, since the solid-state imaging element 120
necessitates a requisite minimum pixel size for reacting with
optical light, the manufacturing process for the solid-state
imaging element 120 does not necessarily require a fine wiring
process, and therefore, the process cost can be reduced. Further,
if the manufacturing process for the logic circuit 122 uses a
state-of-the-art fine wiring process, then the power consumption
can be reduced. Furthermore, it is possible to improve the
theoretical yield of the memory circuit 121 and the logic circuit
122. As a result, the cost required for the manufacture of the
solid-state imaging device 111 can be reduced.
[0171] Further, since the solid-state imaging element 120 is
structured such that chips can be rearranged on and joined to a
wafer, heterogeneous processes by which analog circuits such as a
power supply IC and a clock circuit and the logic circuits 122 can
be stacked in one chip even by heterogeneous processes by which it
is difficult to manufacture circuits configured by processes quite
different from each other in the same wafer or even if there is a
difference in wafer size.
[0172] Further, although the foregoing description is directed to
an example in which the memory circuit 121 and the logic circuit
122 are used as circuits to be connected to the solid-state imaging
element 120, any signal processing circuit other than the memory
circuit 121 and the logic circuit 122 may be connected if it is a
signal processing circuit necessitated for operation of the
solid-state imaging element 120 such as a circuit that relates to
control of the solid-state imaging element 120 or a circuit
relating to processing of a captured pixel signal. The signal
processing circuit necessitated for operation of the solid-state
imaging element 120 may be, for example, a power supply circuit, an
image signal compression circuit, a clock circuit, an optical
communication conversion circuit or the like.
3. Second Embodiment
[0173] Although the foregoing description is given of the
solid-state imaging device 111 having a two-layer structure in
which a layer in which the solid-state imaging element 120 is
formed and a layer in which the memory circuit 121 and the logic
circuit 122 are rearranged are stacked, the solid-state imaging
device 111 may otherwise have a three-layer configuration.
[0174] FIG. 10 is a view illustrating a stack structure of wafers
configured by the WoW technology that is applied when a solid-state
imaging device of a three-layer structure of the present disclosure
is manufactured.
[0175] In FIG. 10, a wafer 101 on which a solid-state imaging
element 120 is formed, a wafer 201 on which a memory circuit 121 is
rearranged and a wafer 202 on which a logic circuit 122 is
rearranged are stacked in order from above.
[0176] The wafer 101 is similar to the wafer 101 of FIG. 4, and a
plurality of solid-state imaging elements 120 is formed by a
semiconductor process on the wafer 101.
[0177] On the wafer 201, a plurality of memory circuits 121 that
has been subjected, after the memory circuits 121 have been formed
on a wafer 103 by a semiconductor process and singulated, to
electric inspection individually and confirmed to be good chips is
selected and rearranged.
[0178] On the wafer 202, a plurality of logic circuits 122 that has
been subjected, after the logic circuits 122 have been formed on a
wafer 104 by a semiconductor process and singulated, to electric
inspection individually and confirmed to be good chips is selected
and rearranged.
[0179] <Example of configuration of solid-state imaging device
including wafers stacked by wow technology of FIG. 1>
[0180] The solid-state imaging device of the present disclosure is
formed by singulation of such wafers stacked by the WoW technology
as depicted in FIG. 10. The solid-state imaging device of the
present disclosure is configured, for example, in such a manner as
depicted in FIG. 11. It is to be noted that, in FIG. 11, the upper
stage is a side elevational sectional view, and the lower stage is
an arrangement view of the solid-state imaging element 120, memory
circuit 121 and logic circuit 122 as viewed from above.
[0181] In particular, in the solid-state imaging device 111 at the
upper stage of FIG. 11, an on-chip lens and on-chip color filter
131, a solid-state imaging element 120, a memory circuit 121, a
logic circuit 122 and a support substrate 132 are formed in order
from above in the figure. In particular, as depicted in the upper
stage of FIG. 11, the solid-state imaging device Ill of FIG. 11
has: a semiconductor element layer E11 including a solid-state
imaging element 120 including the wafer 101; a semiconductor
element layer E12 including a memory circuit 121 formed on the
wafer 201; and a semiconductor element layer E13 including a logic
circuit 122 formed on the wafer 202.
[0182] Terminals 120a of the solid-state imaging element 120 are
electrically connected to the terminals 121a-1 of the memory
circuit 121 by wires 134-1 connected by Cucu connection to the
terminals 121a-1.
[0183] Meanwhile, terminals 121a-2 of the memory circuit 121 are
electrically connected to the terminals 122a of the logic circuit
122 by wires 134-2 connected by CuCu connection to the terminals
122a.
[0184] In a space around the solid-state imaging element 120, the
memory circuit 121, the logic circuit 122, and the support
substrate 132, an oxide film 133 is formed. Further, on the
boundary between the semiconductor element layer E11 in which the
solid-state imaging element 120 is formed and the semiconductor
element layer E12 in which the memory circuit 121 is formed such
that it is embedded in the oxide film 133, an oxide film joining
layer 135 is formed and the layers are joined together by oxide
film joining. Furthermore, on the boundary between the
semiconductor element layer E12 in which the memory circuit 121 is
formed in an embedded relation in the oxide film 133 and the
semiconductor element layer E13 in which the logic circuit 122 is
formed in an embedded relation in the oxide film 133, an oxide film
joining layer 135 is formed, and the layers are joined together by
oxide film joining. On the boundary between the semiconductor
element layer E12 in which the logic circuit 122 is formed and the
support substrate 132, an oxide film joining layer 135 is formed,
and the layers are joined together by oxide film joining.
[0185] Further, as depicted at the lower stage of FIG. 11, the
memory circuit 121 is formed at a substantially central position in
the layer lower than the solid-state imaging element 120 and the
logic circuit 122 is arranged at a substantially central position
in the lower layer than the memory circuit 121 as viewed from
above.
[0186] In particular, on the wafer 201 of FIG. 10, the memory
circuit 121 is rearranged so as to coincide with a central position
of the solid-state imaging element 120 when each solid-state
imaging devices 111 is singulated, and on the wafer 202, the logic
circuit 122 is rearranged so as to coincide with a central position
of the solid-state imaging element 120.
[0187] <Manufacturing method of solid-state imaging device of
FIG. 11>
[0188] Now, a manufacturing method of the solid-state imaging
device 111 of FIG. 11 is described with reference to FIGS. 12 and
13. It is to be noted that side elevational sectional views 12A to
12F in FIGS. 12 and 13 depict side elevational sectional views of
the solid-state imaging device 111.
[0189] At a first step, as depicted by the side elevational
sectional view 12A of FIG. 12, a solid-state imaging element 120
and a memory circuit 121 are stacked on a support substrate 132-1
from above as depicted by the side elevational sectional view 12A
of FIG. 12, and a space between the solid-state imaging element 120
and the memory circuit 121 around the memory circuit 121 is in a
state filled with an oxide film 133 such that the memory circuit
121 is filled in the oxide film 133.
[0190] It is to be noted that, since steps until the side
elevational sectional view 12A of FIG. 12 is formed are similar to
those in the case where only the memory circuit 121 is formed by
the steps of the side elevational sectional view 6A of FIG. 6 to
the side elevational sectional view 6J of FIG. 9, and therefore,
description of them is omitted.
[0191] At a second step, as depicted in the side elevational
sectional view 12B of FIG. 12, the support substrate 132-1 is
removed, and wires 134-2 are formed at the terminals 121a-2 of the
memory circuit 121.
[0192] At a third step, as depicted by a range surrounded by an
alternate long and short dashes line in the side elevational
sectional view 12C of FIG. 12, the logic circuit 122 on which the
wires 134-2 are formed at the terminals 122a and which is provided
on a support substrate 132-2 is positioned such that the memory
circuits 121 and the wires 134-2 are opposed to each other.
[0193] It is to be noted that a portion surrounded by an alternate
long and short dashes line in which the memory circuit 121 is
configured on the support substrate 132-2 is similar to that in the
case where only the logic circuit 122 is formed by the steps of the
side elevational sectional view 6A of FIG. 6 to the side
elevational sectional view 6H of FIG. 8, and therefore, description
of them is omitted.
[0194] At a fourth step, as depicted in the side elevational
sectional view 12D of FIG. 13, a lower face portion of the memory
circuit 121 and an upper face portion of the logic circuit 122 are
coupled to each other by oxide film coupling, and the terminals
121a-2 of the memory circuit 121 and the terminals 122a of the
logic circuit 122 are connected to each other via the wires 134-2.
Consequently, the memory circuit 121, the logic circuit 122, and
the solid-state imaging element 120 are electrically connected to
each other.
[0195] At a fifth step, as depicted by the side elevational
sectional view 12E of FIG. 13, the silicon layer of the solid-state
imaging element 120 is thinned.
[0196] At a sixth step, as depicted by the side elevational
sectional view 12F of FIG. 13, the on-chip lens and on-chip color
filter 131 is provided on the solid-state imaging element 120 and
singulation is performed, thereby to complete the solid-state
imaging device 111.
[0197] In this manner, the solid-state imaging device 111 of a
totaling three layer structure including the first layer in which
the solid-state imaging element 120 is formed, the second layer in
which the memory circuit 121 is formed and the third layer in which
the logic circuit 122 are formed is manufactured.
[0198] Also, in such a configuration as described above, since
circuit connection between the solid-state imaging element 120, the
memory circuit 121, and the logic circuit 122 can be established
through terminals formed in a wire density of fine wires by a
lithography technique of semiconductors similarly as in the WoW,
the number of connection terminals can be increased and reduction
of the power consumption can be anticipated.
[0199] Further, since the memory circuit 121 and the logic circuit
122 are connected only where they are good chips, the yield of
wafers, which is a defect of the WoW, can be decreased and
occurrence of the yield loss can be reduced.
[0200] Furthermore, as depicted in the side elevational sectional
views 12A to 12C of FIG. 12 described above, a configuration of
three or more layers can be implemented by forming wires (rear face
wires) on a lower face in the figures.
4. Third Embodiment
[0201] <Example of configuration of solid-state imaging device
in case where solid-state imaging element is smaller than memory
circuit or logic circuit>
[0202] Although the foregoing description is given of an example of
a case in which the solid-state imaging element 120 is greater than
both the memory circuit 121 and the logic circuit 122, it may be
configured otherwise such that it is smaller than at least any one
of the memory circuit 121 or the logic circuit 122.
[0203] FIG. 14 depicts an example of a configuration of the
solid-state imaging device 111 having a two-layer configuration in
the case where the solid-state imaging element 120 is smaller than
the memory circuit 121 but is greater than the logic circuit
122.
[0204] In particular, as depicted at the upper portion of FIG. 14,
a solid-state imaging element 120 is formed on a configuration that
a layer in which a memory circuit 121 and a logic circuit 122 are
formed is provided on a support substrate 132 and wires 134 are
formed at terminals 121a and 122a. Further, the solid-state imaging
element 120 is provided at a position at which it extends between
the memory circuit 121 and the logic circuit 122 as viewed from
above as indicated at the lower portion of FIG. 14. In particular,
as depicted at the upper stage of FIG. 14, the solid-state imaging
device 111 of FIG. 14 has: a semiconductor element layer E1
including the solid-state imaging element 120 including the wafer
101; and a semiconductor element layer E2 including the memory
circuit 121 and the logic circuit 122 formed on the wafer 102.
[0205] It is to be noted that an insulating film including an oxide
film 133 is formed around the solid-state imaging element 120.
[0206] <Manufacturing method of solid-state imaging device of
FIG. 14>
[0207] Now, a manufacturing method of the solid-state imaging
device 111 of FIG. 14 is described with reference to FIGS. 15 and
16. It is to be noted that side elevational sectional views 15A to
15F of FIGS. 15 and 16 depict side elevational sectional views of
the solid-state imaging device 111.
[0208] At a first step, as depicted by the side elevational
sectional view 15A of FIG. 15, a memory circuit 121 and a logic
circuit 122 are formed on a support substrate 132 and are embedded
into an insulating film including an oxide film 133, and an oxide
film joining layer 135 is formed on the uppermost layer. Further,
wires 134 are formed at terminals 121a and 122a.
[0209] It is to be noted that the steps up to the formation of the
side elevational sectional view 15A of FIG. 15 are similar to those
in the case where a memory circuit 121 and a logic circuit 122 are
formed on a support substrate 132 by the steps of the side
elevational sectional view 6A of FIG. 6 to the side elevational
sectional view 6H of FIG. 9, and therefore, description of them is
omitted.
[0210] At a second step, as depicted by the side elevational
sectional view 15B of FIG. 15, a singulated solid-state imaging
element 120 is rearranged on a rearrangement substrate 211, to
which adhesive 212 is applied, such that the imaging face side
thereof is opposed to the rearrangement substrate 211. Further, as
depicted by the lower stage of FIG. 14, the solid-state imaging
element 120 is rearranged on the rearrangement substrate 211 at a
position at which it extends between the memory circuit 121 and the
logic circuit 122 in a plane direction.
[0211] At a third step, as depicted by the side elevational
sectional view 15C of FIG. 15, the solid-state imaging element 120
having the state of the side elevational sectional view 15B is
reversed, and wires 134 of the memory circuit 121 and the logic
circuit 122 of the side elevational sectional view 15A are
connected by CuCu joining and besides opposing layers are joined
together by oxide film joining.
[0212] At a fourth step, as depicted by the side elevational
sectional view 15D of FIG. 16, the rearrangement substrate 211 is
removed.
[0213] At a fifth step, as depicted by the side elevational
sectional view 15E of FIG. 16, the silicon layer of the solid-state
imaging element 120 is thinned.
[0214] At a sixth step, as depicted by the side elevational
sectional view 15F of FIG. 16, an on-chip lens and on-chip color
filter 131 is provided on the solid-state imaging element 120, and
the solid-state imaging device 111 is completed therewith. It is to
be noted that, in the present example, in the solid-state imaging
element 120, memory circuit 121 and logic circuit 122 are all
singulated at a stage before they are assembled.
[0215] In this manner, also in the case where the size of the
solid-state imaging element 120 is smaller than that of the memory
circuit 121 but greater than that of the logic circuit 122, the
solid-state imaging device 111 of the totaling two-layer structure
including the first layer in which the solid-state imaging element
120 is formed and the second layer in which the memory circuit 121
and the logic circuit 122 are formed is manufactured.
[0216] Also, in such a configuration as described above, since
circuit connection between the solid-state imaging element 120, the
memory circuit 121, and the logic circuit 122 can be established
through terminals formed in a wire density of fine wires by a
lithography technique of semiconductors similarly as in the WoW,
the number of connection terminals can be increased and reduction
of the power consumption can be anticipated.
[0217] Further, since the memory circuit 121 and the logic circuit
122 are connected only where they are good chips, the yield of
wafers, which is a defect of the WoW, can be decreased and
occurrence of the yield loss can be reduced.
[0218] It is to be noted that, also in the case where the
solid-state imaging element 120 is smaller than the logic circuit
122 but is greater than the memory circuit 121, the solid-state
imaging device 111 can be manufactured by similar steps. Similarly,
also in the case where the solid-state imaging element 120 is
smaller than both the logic circuit 122 and the memory circuit 121,
the solid-state imaging device 111 can be manufactured by similar
steps.
5. Fourth Embodiment
[0219] <Example of Configuration of Solid-State Imaging Device
of Three-Layer Structure in Case where Solid-State Imaging Element
is Smaller than Memory Circuit and Logic Circuit>
[0220] Although the foregoing description is directed to an example
of a configuration of the solid-state imaging device 111 of a
two-layer structure in the case where the solid-state imaging
element 120 is smaller than the memory circuit 121 but is greater
than the logic circuit 122, the solid-state imaging device 111 may
have a three-layer structure even in the case where the solid-state
imaging element 120 is smaller than the memory circuit 121 but is
greater than the logic circuit 122.
[0221] FIG. 17 depicts an example of a configuration of a
solid-state imaging device 111 having a three-layer structure in
the case where the solid-state imaging element 120 is smaller than
the memory circuit 121 but is greater than the logic circuit
122.
[0222] In particular, as depicted by the upper portion of FIG. 17,
a logic circuit 122 is formed on a support substrate 132 such that
it is oxide-film-coupled by an oxide film joining layer 135, and a
memory circuit 121 is formed on the logic circuit 122 such that it
is oxide-film-coupled by the oxide film joining layer 135. Further,
a solid-state imaging element 120 is formed on the memory circuit
121 such that it is oxide-film-coupled by the oxide film joining
layer 135, and an on-chip lens and on-chip color filter 131 is
formed on the solid-state imaging element 120. In particular, as
indicated by the upper stage of FIG. 17, the solid-state imaging
device 111 of FIG. 17 has: a semiconductor element layer E11
including the solid-state imaging element 120 including the wafer
101; a semiconductor element layer E12 including the memory circuit
121 formed on the wafer 201; and a semiconductor element layer E13
including the logic circuit 122 formed on the wafer 202.
[0223] Further, terminals 120a of the solid-state imaging element
120 and terminals 121a-1 of the memory circuit 121 are electrically
connected to each other by wires 134-1 through CuCu joining, and
terminals 121a-2 of the memory circuit 121 and terminals 122a of
the logic circuit 122 are electrically connected by wires 134-2
through CuCu joining.
[0224] In this case, as indicated by the lower portion of FIG. 17,
the solid-state imaging element 120, memory circuit 121 and logic
circuit 122 are formed such that the center positions thereof are
aligned with one another.
[0225] It is to be noted that an insulating film including an oxide
film 133 is formed around the solid-state imaging element 120.
[0226] As a manufacturing method of the solid-state imaging device
111 in FIG. 17, it is sufficient if only the logic circuit 122 is
formed by the steps of the side elevational sectional view 6A of
FIG. 6 to the side elevational sectional view 6H of FIG. 8 and then
the memory circuit 121 is placed on the rearrangement substrate 211
as indicated by the side elevational sectional view 15B of FIG. 15
and is connected to the logic circuit 122 as indicated by the side
elevational sectional view 15C of FIG. 15, whereafter the
solid-state imaging element 120 is formed by a similar method.
Therefore, description with reference to the drawings is
omitted.
[0227] Also, in such a configuration as described above, since
circuit connection between the solid-state imaging element 120, the
memory circuit 121, and the logic circuit 122 can be established
through terminals formed in a wire density of fine wires by a
lithography technique of semiconductors similarly as in the WoW,
the number of connection terminals can be increased and reduction
of the power consumption can be anticipated.
[0228] Further, since the memory circuit 121 and the logic circuit
122 are connected only where they are good chips, the yield of
wafers, which is a defect of the WoW, can be decreased and
occurrence of the yield loss can be reduced.
[0229] It is to be noted that, also in the case where the
solid-state imaging element 120 is smaller than the logic circuit
122 but is greater than the memory circuit 121, the solid-state
imaging device 111 can be manufactured by similar steps. Similarly,
also in the case where the solid-state imaging element 120 is
smaller than both the logic circuit 122 and the memory circuit 121,
the solid-state imaging device 111 can be manufactured by similar
steps.
6. Fifth Embodiment
[0230] <Example of configuration of solid-state imaging device
in case where memory circuit and logic circuit are formed directly
on wafer of solid-state imaging element>
[0231] The foregoing description is directed to an example in
which, after the memory circuit 121 and the logic circuit 122 are
singulated and it is confirmed that they are good chips, they are
formed on the wafer 102 (support substrate 132). However, a memory
circuit 121 and a logic circuit 122 that have been singulated and
have been confirmed as good chips may be formed directly on the
solid-state imaging element 120 on the wafer 101.
[0232] FIG. 18 is a view illustrating a manufacturing method of a
solid-state imaging device in which a memory circuit 121 and a
logic circuit 122 that have been singulated and have been confirmed
as good chips are formed directly on a solid-state imaging element
120 on a wafer 101.
[0233] In particular, referring to FIG. 18, a plurality of
solid-state imaging elements 120 is formed on a wafer 101 by a
semiconductor process. Further, a plurality of memory circuits 121
that has been subjected, after the memory circuits 121 are formed
on a wafer 103 by a semiconductor process and singulated, to
electric inspection and confirmed as good chips through the
electric inspection and a plurality of logic circuits 122 that has
been subjected, after the logic circuits 122 are formed on a wafer
104 by a semiconductor process and singulated, to electric
inspection and confirmed as good chips through the electric
inspection are selected and rearranged on the solid-state imaging
element 120 formed on the wafer 101. In other words, since the
memory circuits 121 and the logic circuits 122 having been
confirmed as good chips are rearranged on the solid-state imaging
element 120, the memory circuits 121 and the logic circuits 122
here are configured smaller than the solid-state imaging elements
120.
[0234] It is to be noted that an example of a configuration of a
solid-state imaging device 111 having a two-layer configuration in
the case where a memory circuit 121 and a logic circuit 122 having
been singulated and confirmed as good chips are formed directly on
the solid-state imaging element 120 on the wafer 101 is similar to
that of FIG. 5. Therefore, description of the example is
omitted.
[0235] <Manufacturing method of solid-state imaging device of
FIG. 14>
[0236] Now, a manufacturing method of the solid-state imaging
device 111 of FIG. 18 is described with reference to FIGS. 19 and
20. Side elevational sectional views 19A to 19E of FIGS. 19 and 20
depict side elevational sectional views of the solid-state imaging
device 111.
[0237] At a first step, as depicted by the side elevational
sectional view 19A of FIG. 19, a memory circuit 121 and a logic
circuit 122 that have been confirmed as good chips through electric
inspection are formed on a solid-state imaging element 120 on a
wafer 101 such that they have such a layout as depicted in the
lower stage of FIG. 5 and wires 134 are formed on terminals 120a
and 121a. Further, positioning is performed such that wires 134
from the terminals 121a of the memory circuit 121 and terminals
122a of the logic circuit 122 and wires 134 from terminals 120a of
the solid-state imaging element 120 of the wafer 101 are positioned
in an appropriately opposing relation to each other and are
connected by CuCu joining and besides opposing layers are joined
together by oxide film joining to form an oxide film joining layer
135.
[0238] At a second step, as depicted by the side elevational
sectional view 19B of FIG. 19, the silicon layer on the memory
circuit 121 and an upper face portion in the figure of the logic
circuit 122 is thinned to a height that does not have an influence
on properties of the device and an oxide film 133 that functions as
an insulating film is formed such that the chip including the
rearranged memory circuit 121 and logic circuit 122 is embedded
therein.
[0239] At a third step, as depicted by the side elevational
sectional view 19C of FIG. 19, a support substrate 132 is joined to
an upper portion of the memory circuit 121 and the logic circuit
122. At this time, layers at which the support substrate 132 and
the memory circuit 121 and logic circuit 122 are opposed to each
other are joined together by oxide film joining to form an oxide
film joining layer 135.
[0240] At a fourth step, as depicted by the side elevational
sectional view 19D of FIG. 20, upside down is performed such that
the solid-state imaging element 120 comes to the top and the
silicon layer that is an upper layer in the figure of the
solid-state imaging element 120 is thinned.
[0241] At a fifth step, as depicted by the side elevational
sectional view 19E of FIG. 20, an on-chip lens and on-chip color
filter 131 is provided on the solid-state imaging element 120 and
singulation is performed to complete a solid-state imaging device
111.
[0242] It is to be noted that, at the first step, when the memory
circuit 121 and the logic circuit 122 are to be rearranged and
joined to the solid-state imaging element 120, after they are
individually subjected to hydrophilic treatment, they are contacted
with each other in such a state that part of the singulated memory
circuit 121 or logic circuit 122 such as an end side or an end
point is positioned with certainly with respect to the solid-state
imaging element 120, for example, as depicted in the upper stage of
FIG. 21. Then, as depicted in the lower stage of FIG. 21, the
memory circuit 121 or the logic circuit 122 is gradually contacted
with the solid-state imaging element 120 beginning, from among
portions of the same, with a portion near to the portion contacted
with the solid-state imaging element 120 until it is entirely
contacted and joined by oxide film joining.
[0243] After a portion such as an end side or an end point of the
memory circuit 121 or the logic circuit 122 is positioned with high
accurately and contacted with the solid-state imaging element 120,
the memory circuit 121 or the logic circuit 122 is gradually
contacted beginning with a portion near to the contacted portion
until it is rearranged in this manner. Consequently, the alignment
accuracy of the memory circuit 121 and the logic circuit 122 with
the solid-state imaging element 120 can be improved.
[0244] Further, since the memory circuit 121 and the logic circuit
are gradually joined entirely after part of the memory circuit 121
or the logic circuit 122 and the solid-state imaging element 120
are contacted with each other in the state in which they are
positioned in this manner, it is possible to join them while voids
(air bubbles) appearing in the joining face are gradually pushed
out.
[0245] As a result, since appearance of voids in a joining face can
be suppressed, even if the solid-state imaging device 111 is placed
into a high temperature state at a different manufacturing step or
upon operation, air in voids (air bubbles) is suppressed from
expanding and exploding and the product accuracy can be improved.
It is to be noted that, also at the first step in the first
embodiment described hereinabove with reference to the side
elevational sectional view 6A of FIG. 6, the entirety of the memory
circuit 121 and the logic circuit may be joined gradually after
part of the memory circuit 121 or the logic circuit 122 and the
solid-state imaging element 120 are contacted in a positioned
state.
[0246] Further, at the second step, after the memory circuit 121
and logic circuit 122 and the solid-state imaging element 120 are
joined together as depicted at the upper stage of FIG. 22
(similarly to the lower stage of FIG. 21), the silicon layer at an
upper face portion in the figures of the memory circuit 121 and the
logic circuit 122 is thinned to a height with which the properties
of the device are not influenced as depicted at the lower stage of
FIG. 22. Then, the memory circuit 121 and the logic circuit 122 are
embedded into an insulating film including the oxide film 133 and
an oxide film joining layer 135 is formed on the flattened
uppermost face, by which such a configuration as indicated by the
side elevational sectional view 19B of FIG. 19 is obtained.
[0247] By such manufacturing steps as described above, the
solid-state imaging device 111 including the first layer in which
the solid-state imaging element 120 is formed and the second layer
in which the memory circuit 121 and the logic circuit 122 are
formed is manufactured.
[0248] As a result, since the memory circuit 121 and the logic
circuit 122 are connected to the solid-state imaging element 120,
the step of arranging them on a support substrate is eliminated and
the man-hours can be reduced. Further, since the support substrate
partly becomes unnecessary in manufacture, the manufacturing cost
can be reduced. Furthermore, since the memory circuit 121 and the
logic circuit 122 are rearranged on the solid-state imaging element
120 in a state in which they are directly positioned relative to
each other, the alignment accuracy of the memory circuit 121 and
the logic circuit 122 with respect to the solid-state imaging
element 120 can be improved.
7. Modification of Fifth Embodiment
[0249] <Modification of solid-state imaging device in case where
memory circuit and logic circuit are formed directly on wafer of
solid-state imaging element>
[0250] Although the solid-state imaging apparatus described above
is configured such that the memory circuit 121 and the logic
circuit 122 are embedded in an insulating film including the oxide
film 133 and the oxide film joining layer 135 is formed on a
flattened uppermost face so as to have such a configuration as
depicted in the side elevational sectional view 19B of FIG. 19,
high heat resistant resin may be applied or laminated in place of
the oxide film 133.
[0251] In particular, after a memory circuit 121 and a logic
circuit 122 are formed on a solid-state imaging element 120 on a
wafer 101, a high heat resistant resin 251 including an organic
film or the like may be applied to or laminated on the memory
circuit 121 and the logic circuit 122 as depicted at the upper
stage of FIG. 23.
[0252] By joining the support substrate 132 in a state in which the
high heat resistant resin 251 remains in the applied or laminated
state as depicted at the lower stage of FIG. 23, it becomes
possible to paste the support substrate 132 without thinning a
silicon layer at an upper face portion of the memory circuit 121
and the logic circuit 122, and the man-hours can be reduced.
[0253] It is to be noted that the oxide film 133 that serves as an
embedding member as an insulating film for the memory circuit 121
and the logic circuit 122 preferably is a Si-based oxide film such
as, for example, SiO2, SiO and SRO. Further, for the high heat
resistant resin 241, a polyimide-based film of PI, PBO or the like
or a polyamide-based film is preferably used as a high heat
resistant material including an organic film.
8. Sixth Embodiment
[0254] <Example of configuration of solid-state imaging device
in case where memory circuit and logic circuit are formed in plural
layers on wafer on which solid-state imaging element is
formed>
[0255] The foregoing description is directed to an example in which
a memory circuit 121 and a logic circuit 122 singulated and
confirmed as good chips are rearranged in one layer on a
solid-state imaging element 120 formed on a wafer 101 to form a
solid-state imaging device. However, a memory circuit 121 and a
logic circuit 122 confirmed as good chips may be rearranged in a
plurality of layers to form a solid-state imaging device.
[0256] FIG. 24 is a view illustrating a stacked structure of a
wafer configured by the WoW technology applied to a solid-state
imaging device that is manufactured by forming memory circuits 121
and logic circuits 122, which have been singulated and confirmed as
good chips, in two layers on a solid-state imaging element 120
formed on a wafer 101 of the present disclosure.
[0257] In FIG. 24, a wafer 102 on which memory circuits 121 and
logic circuits 122 are rearranged and a wafer 101 on which memory
circuits 121 and logic circuits 122 are rearranged on a solid-state
imaging element 120 are stacked from above in the figure. It is to
be noted that, in FIG. 24, the wafer 102 and the wafer 101 are
configured such that individual faces thereof on which the memory
circuit 121 and the logic circuit 122 are rearranged are opposed to
each other. In particular, in FIG. 24, that the memory circuits 121
and the logic circuits 122 on the wafer 102 are indicated by broken
lines represents that the face thereof on which the memory circuits
121 and the logic circuits 122 are reconfigured are opposed to the
wafer 101.
[0258] <Example of configuration of solid-state imaging device
including wafers stacked by wow technology in FIG. 24>
[0259] Such wafers stacked by the WoW technology as depicted in
FIG. 24 are singulated to form the solid-state imaging device of
the present disclosure. The solid-state imaging device of the
present disclosure has such a configuration as, for example,
depicted by the side elevational sectional view of FIG. 25.
[0260] In particular, the solid-state imaging device 111 of FIG. 25
includes an on-chip lens and on-chip color filter 131, a
solid-state imaging element 120, a memory circuit 121-11 and a
logic circuit 122-11 in a first layer from above, a memory circuit
121-11 and a logic circuit 122-12 in a second layer from above, and
a support substrate 132.
[0261] In particular, as depicted in FIG. 25, the solid-state
imaging device 111 of FIG. 24 has: a semiconductor element layer
E31 including a solid-state imaging element 120 including a wafer
101; a semiconductor element layer E32 including a memory circuit
121-11 and a logic circuit 122-11 of the first layer formed
directly by rearrangement on the solid-state imaging element 120;
and a semiconductor element layer E33 including a memory circuit
121-12 and a logic circuit 122-12 of the second layer formed on the
wafer 102.
[0262] Terminals 120a of the solid-state imaging element 120 are
electrically connected to terminals 121a-11 of the memory circuit
121-11 and terminals 122a-11 of the logic circuit 122-11 of the
semiconductor element layer E32 by wires 134-11 connected by CuCu
connection. Further, the terminals 121a-11 of the memory circuit
121-11 and the terminals 122a-11 of the logic circuit 122-11 of the
semiconductor element layer E32 are electrically connected to
terminals 121a-12 of the memory circuit 121-12 and terminals
122a-12 of the logic circuit 122-12 of the semiconductor element
layer E33 by wires 134-12 connected by CuCu connection.
[0263] In a space around the solid-state imaging element 120, and
the memory circuits 121-11 and 121-12 and the logic circuits 122-11
and 122-12 of the semiconductor element layers E32 and E33, and the
support substrate 132, an oxide film 133 is formed. Further, on the
boundary between semiconductor element layer E31 on which the
solid-state imaging element 120 is formed and the semiconductor
element layer E32 in which the memory circuit 121-11 and the logic
circuit 122-11 are formed and embedded in the oxide film 133, the
oxide film joining layer 135 is formed and the layers are joined
together by oxide film joining. Further, on the boundary between
the semiconductor element layer E32 in which the memory circuit
121-11 and the logic circuit 122-11 are formed and embedded in the
oxide film 133 and the semiconductor element layer E33 in which the
memory circuit 121-12 and the logic circuit 122-12 are formed and
embedded in the oxide film 133, the oxide film joining layer 135 is
formed and the layers are joined together by oxide film joining. On
the boundary between the support substrate 132 and the
semiconductor element layer E33 in which the memory circuit 121-12
and the logic circuit 122-12 are formed and embedded in the oxide
film 133, the oxide film joining layer 135 is formed and the layers
are joined together by oxide film joining.
[0264] <Manufacturing method of solid-state imaging device of
FIG. 25>
[0265] Now, a manufacturing method of the solid-state imaging
device 111 of FIG. 25 is described with reference to FIGS. 26 to
28. It is to be noted that side elevational sectional views 26A to
26G of FIGS. 26 to 28 depict side elevational sectional views of
the solid-state imaging device 111.
[0266] At a first step, as depicted by the side elevational
sectional view 26A of FIG. 26, after electric inspection for the
solid-state imaging element 120 on the wafer 101 is performed,
memory circuits 121 and logic circuits 122 that are confirmed as
good products are formed in such a layout as depicted at the lower
stage of FIG. 5 and wires 134-11 are formed to the terminals 120a
and 121a. Further, positioning is performed such that wires 134-11
from the terminals 121a-11 of the memory circuit 121-11 and the
terminals 122a-11 of the logic circuit 122-11 and the wires 134-11
from the terminals 120a of the solid-state imaging element 120 in
the wafer 101 are positioned in an appropriately opposed relation
to each other, and they are connected to each other by CuCu joining
and the opposing layers are joined together by an oxide film
joining layer 135 formed by oxide film joining.
[0267] At a second step, as depicted by the side elevational
sectional view 26B of FIG. 26, wires 134-12 formed, for example,
from through-electrodes (TSVs) are formed for the terminals 121a-11
of the memory circuit 121-11 and the terminals 122a-11 of the logic
circuit 122-11.
[0268] At a third step, as depicted by the side elevational
sectional view 26C of FIG. 26, PADS for connection and an oxide
film joining layer 135 for connection are formed for the wires
134-12.
[0269] At a fourth step, as depicted by the side elevational
sectional view 26D of FIG. 27, terminals 121a-12 of the memory
circuit 121-12 and terminals 122a-12 of the logic circuit 122-12
are formed in an electrically connected state through the wires
134-12 by a method similar to the method described hereinabove with
reference to the side elevational sectional views 19A and 19B of
FIG. 19 and FIGS. 21 and 22.
[0270] At a fifth step, as depicted by the side elevational
sectional view 26E of FIG. 27, a support substrate 132 is joined to
an upper portion of the memory circuit 121-12 and the logic circuit
122-12. At this time, the opposing layers of the support substrate
132 and the memory circuit 121-12 and logic circuit 122-12 are
joined together by an oxide film joining layer 135 formed by oxide
film joining.
[0271] At a sixth step, as depicted by the side elevational
sectional view 26F of FIG. 27, upside down is performed such that
the solid-state imaging element 120 comes to the top and the
silicon layer that is a layer at the top in the figure of the
solid-state imaging element 120 is thinned.
[0272] At a seventh step, as depicted by the side elevational
sectional view 26G of FIG. 28, an on-chip lens and on-chip color
filter 131 is provided on the solid-state imaging element 120, and
singulation is performed to complete the solid-state imaging device
111.
[0273] By such joining as described above, the memory circuit 121
and the logic circuit 122 can be stacked in a plurality of
layers.
[0274] It is to be noted that, although the foregoing description
is directed to an example in which the memory circuit 121 and the
logic circuit 122 are formed in two layers, they may otherwise be
stacked in three or more layers by using a similar method.
9. Example of Connection to Solid-State Imaging Element
First Connection Example
[0275] Although the foregoing description is directed to an example
in which, in regard to joining, oxide film coupling is applied to
portions other than terminals and CuCu joining is applied to
terminals to form wires 134 to establish electric connection, other
connection methods may be used.
[0276] FIG. 29 depicts connection examples 29A to 29D in the case
where terminals 120a and 122a of a solid-state imaging element 120
and a logic circuit 122 within a range indicated by a frame Z11 of
a solid-state imaging device Ill at a left upper stage are
connected to each other.
[0277] In the connection example 29A, the terminals 122a of the
logic circuit 122 and the terminals 120a of the solid-state imaging
element 120 are arranged at a same position in a horizontal
direction in the figure, and the terminals 122a of the logic
circuits 122 are disposed in a displaced relation to the boundary
side with the solid-state imaging element 120 in a vertical
direction in the figure. Further, through-vias are formed such that
they extend through the terminals 122a and 120a from the rear face
side (lower side in the figure) of the solid-state imaging device
111, and a wire 134A is formed in each through-via.
[0278] In the connection example 29B, the terminals 122a of the
logic circuit 122 and the terminals 120a of the solid-state imaging
element 120 are arranged in a displaced relation from each other in
the horizontal direction in the figure while the terminals 122a of
the logic circuit 122 are arranged in a displaced relation to the
boundary side with the solid-state imaging element 120 in the
vertical direction in the figure. Further, through-vias are formed
such that they extend through the terminals 122a and 120a
independently of each other from the rear face side (lower side in
the figure) of the solid-state imaging device 111. Further, wires
134B are formed in the through-vias, and wires are connected to
them on the surface on the rear face side.
[0279] In the connection example 29C, the terminals 122a of the
logic circuit 122 and the terminals 120a of the solid-state imaging
element 120 are arranged at a same position in the horizontal
direction in the figure while the terminals 122a of the logic
circuit 122 are arranged in a displaced relation to the rear face
side (lower side in the figure) from the solid-state imaging
element 120 in the vertical direction in the figure. Further,
through-vias are formed such that they extend through the terminals
122a and 120a from the rear face side (lower side in the figure) of
the solid-state imaging device 111, and wires 134C are formed in
the through-vias.
[0280] In the connection example 29D, the terminals 122a of the
logic circuit 122 and the terminals 120a of the solid-state imaging
element 120 are arranged in a displaced relation from each other in
the horizontal direction in the figure while the terminals 122a of
the logic circuit 122 are arranged in a displaced relation to the
rear face side (lower side in the figure) from the solid-state
imaging element 120 in the vertical direction in the figure.
Further, vias are formed such that they extend through the
terminals 122a and 120a independently of each other from the rear
face side (lower side in the figure) of the solid-state imaging
device 111, and wires 134D are formed in the vias and wires are
connected to them on the surface on the rear face side.
[0281] <Manufacturing method of solid-state imaging device in
which connection examples to solid-state imaging element of FIG. 29
are used>
[0282] Now, a manufacturing method of the solid-state imaging
device 111 for which the connection examples of FIG. 29 are used is
described with reference FIGS. 30 to 32. It is to be noted that
side elevational sectional views 30A to 30H of FIGS. 30 to 32
depict side elevational sectional views of the solid-state imaging
device 111. Here, the connection example 29A is described here.
[0283] At a first step, as depicted by the side elevational
sectional view 30A of FIG. 30, after electric inspection is
performed, memory circuits 121 and logic circuits 122 confirmed as
good products are rearranged on the rearrangement substrate 151
corresponding to the wafer 102. The rearrangement substrate 151 has
adhesive 152 applied thereto, and the memory circuits 121 and the
logic circuits 122 are rearranged on and fixed to the rearrangement
substrate 151 by the adhesive 152. It is to be noted that, after a
portion such as an end face or an end point of the memory circuit
121 or the logic circuit 122 is contacted with the solid-state
imaging element 120, the other portion of the memory circuit 121 or
the logic circuit 122 is gradually contacted, joined and rearranged
beginning with a portion near to the contacted portion as described
hereinabove with reference to FIG. 22.
[0284] At a second step, as depicted by the side elevational
sectional view 30B of FIG. 30, upside down is performed such that
the upper face of the memory circuit 121 and the logic circuit 122
depicted in the side elevational sectional view 30A comes to the
bottom, and an oxide film joining layer 135 is formed on the
solid-state imaging element 120 to couple them to the solid-state
imaging element 120 by oxide film coupling.
[0285] At a third step, as depicted by the side elevational
sectional view 30C of FIG. 30, the rearrangement substrate 151 is
debonded, exfoliated and removed together with the adhesive
152.
[0286] At a fourth step, as depicted by the side elevational
sectional view 30D of FIG. 31, the silicon layer at an upper face
portion in the figure of the memory circuit 121 and the logic
circuit 122 is thinned to a width that does not have an influence
on performances of the device.
[0287] At a fifth step, as depicted by the side elevational
sectional view 30E of FIG. 31, an oxide film 133 that functions as
an insulating film is formed such that a chip including the
rearranged memory circuit 121 and logic circuit 122 is embedded in
the oxide film 133 and then the oxide film 133 is flattened.
Further, the terminals 121a of the memory circuit 121 and the
terminals 120a of the solid-state imaging element 120 are arranged
at a same position in the horizontal direction, and through-vias
are formed so as to extend through the terminals 120a and 121a.
Thereafter, metal is embedded into the through-vias to form a wire
134A in each of the through-vias.
[0288] At a sixth step, as depicted by the side elevational
sectional view 30F of FIG. 31, the configuration depicted in the
side elevational sectional view 30E is reversed, and an oxide film
joining layer 135 is formed on the support substrate 132 and then
the configuration is coupled to the support substrate 132 by oxide
film coupling.
[0289] At a seventh step, as depicted by the side elevational
sectional view 30G of FIG. 32, the silicon layer of the solid-state
imaging element 120 is thinned.
[0290] At an eighth step, as depicted by the side elevational
sectional view 30H of FIG. 32, an on-chip lens and on-chip color
filter 131 is provided on the solid-state imaging element 120 and
singulation is performed, and a solid-state imaging device 111 is
completed therewith.
[0291] By such steps as described above, the wires 134A are formed
in the through-vias formed to extend from the rear face side to
establish a state in which the solid-state imaging element 120 and
the memory circuit 121 and logic circuit 122 are electrically
connected to each other, and the solid-state imaging device 111 is
manufactured thereby.
[0292] It is to be noted that also the wires 134B to 134D depicted
in the connection examples 29B to 29C can be manufactured by
similar steps although they are different in terms of the position,
depth and number of through-vias.
[0293] Also, in such a configuration as described above, since
circuit connection between the solid-state imaging element 120 and
the memory circuit 121 and logic circuit 122 can be established
through terminals formed in a wire density of fine wires by a
lithography technique of semiconductors similarly as in the WoW,
the number of connection terminals can be increased and reduction
of the power consumption can be anticipated.
Second Connection Example
[0294] Although the foregoing description is directed to an example
in which a through-via is formed from the rear face side (from the
opposite side to the imaging face) of the solid-state imaging
device 111 and a wire for electrically connecting a terminal is
formed, a wire may be formed by forming a through-via from the
front face side (imaging face side) and pouring metal into the
through-via.
[0295] FIG. 33 depicts connection examples 33A to 33D in the case
where the terminals 120a and 122a of the solid-state imaging
elements 120 and the logic circuits 122 within a range indicated by
a frame Z21 of the solid-state imaging device 111 at the left upper
stage are connected to each other.
[0296] In the connection example 33A, the terminals 122a of the
logic circuits 122 and the terminals 120a of the solid-state
imaging elements 120 are arranged at a same position in the
horizontal direction in the figure and the terminals 122a of the
logic circuits 122 are arranged in a displaced relation to the
boundary side with the solid-state imaging element 120 in the
vertical direction in the figure. Further, through-vias are formed
such that they extend in a skewered state through the terminals
122a and 120a from the front face side (upper side in the figure)
of the solid-state imaging device 111 and wires 134E are formed in
the through-vias.
[0297] In the connection example 33B, the terminals 122a of the
logic circuits 122 and the terminals 120a of the solid-state
imaging elements 120 are arranged in a displaced relation from each
other in the horizontal direction in the figure and the terminals
122a of the logic circuits 122 are arranged in a displaced relation
to the boundary side with the solid-state imaging element 120 in
the vertical direction in the figure. Further, through-vias are
formed such that they extend independently of each other through
the terminals 122a and 120a from the front face side (upper side in
the figure) of the solid-state imaging device 111 and wires 134F
are formed in the through-vias, and the wires are connected on the
surface on the front face side.
[0298] In the connection example 33C, the terminals 122a of the
logic circuits 122 and the terminals 120a of the solid-state
imaging elements 120 are arranged at a same position in the
horizontal direction in the figure and the terminals 122a of the
logic circuits 122 are arranged in a displaced relation to the rear
face side (lower side in the figure) to the solid-state imaging
element 120 in the vertical direction in the figure. Further,
through-vias are formed such that they extend in a skewered state
through the terminals 122a and 120a from the front face side (upper
side in the figure) of the solid-state imaging device 111 and wires
134G are formed in the through-vias.
[0299] In the connection example 33D, the terminals 122a of the
logic circuits 122 and the terminals 120a of the solid-state
imaging elements 120 are arranged in a displacement relation from
each other in the horizontal direction in the figure and the
terminals 122a of the logic circuits 122 are arranged in a
displaced relation to the rear face side (lower side in the figure)
to the solid-state imaging element 120 in the vertical direction in
the figure. Further, through-vias are formed such that they extend
independently of each other through the terminals 122a and 120a
from the front face side (upper side in the figure) of the
solid-state imaging device 111 and wires 134H are formed in the
through-vias, and the wires are connected on the surface on the
rear face side.
[0300] It is to be noted that, since it is necessary to form the
through-vias from the imaging plane, all of the wires 134E to 134H
are formed on the outside of the pixel region of the solid-state
imaging elements 120 in the horizontal direction.
[0301] <Manufacturing method of solid-state imaging device in
which connection examples to solid-state imaging element of FIG. 33
are used>
[0302] Now, a manufacturing method of the solid-state imaging
device 111 for which the connection examples of FIG. 33 are used is
described with reference to FIGS. 34 to 36. It is to be noted that
side elevational sectional views 34A to 34H of FIGS. 34 to 36
depict side elevational sectional views of the solid-state imaging
device 111. Further, description here is given of the connection
example 33A.
[0303] At a first step, as depicted by the side elevational
sectional view 34A of FIG. 34, after electric inspection is
performed, a memory circuit 121 and a logic circuit 122 configured
as good products are rearranged on a rearrangement substrate 151
corresponding to a wafer 102. The rearrangement substrate 151 has
adhesive 152 applied thereto, and the memory circuit 121 and the
logic circuit 122 are rearranged on and fixed to the rearrangement
substrate 151 by the adhesive 152. It is to be noted that, after a
portion such as an end face or an end point of the memory circuit
121 or the logic circuit 122 is contacted with the solid-state
imaging element 120, the other portion of the memory circuit 121 or
the logic circuit 122 is gradually contacted, joined and rearranged
beginning with a portion near to the contacted portion as described
hereinabove with reference to FIG. 22.
[0304] At a second step, as depicted by the side elevational
sectional view 34B of FIG. 34, upside down is performed such that
the upper face of the memory circuit 121 and the logic circuit 122
depicted in the side elevational sectional view 34B now becomes a
lower face, and an oxide film joining layer 135 is formed on the
solid-state imaging element 120 to achieve oxide film joining.
[0305] At a third step, as depicted in the side elevational
sectional view 34C of FIG. 34, the rearrangement substrate 151 is
debonded, exfoliated and removed together with the adhesive
152.
[0306] At a fourth step, as depicted by the side elevational
sectional view 34D of FIG. 35, the silicon layer at an upper face
portion in the figure of the memory circuit 121 and the logic
circuit 122 is thinned to an extent that does not have an influence
on the performances of the device.
[0307] At a fifth step, as depicted by the side elevational
sectional view 34E of FIG. 35, an oxide film 133 that functions as
an insulating film is formed such that the chip including the
rearranged memory circuit 121 and logic circuit 122 is embedded in
the oxide film 133 and is flattened.
[0308] At a sixth step, as depicted by the side elevational
sectional view 34F of FIG. 35, the configuration depicted in the
side elevational sectional view 34F is reversed and an oxide film
joining layer 135 is formed on the support substrate 132 to achieve
oxide film joining.
[0309] At a seventh step, as depicted by the side elevational
sectional view 34G of FIG. 36, the silicon layer of the solid-state
imaging element 120 is thinned. Further, the terminals 121a of the
memory circuit 121 and the terminals 120a of the solid-state
imaging element 120 are arranged at a same position in the
horizontal direction, and through-vias are formed so as to extend
through the terminals 120a and 121a from the front face side such
that the terminals 120a and 121a are placed into a skewered state.
Then, metal is embedded into the through-vias to form wires
134E.
[0310] At an eighth step, as depicted by the side elevational
sectional view 34H of FIG. 36, an on-chip lens and on-chip color
filter 131 is provided on the solid-state imaging element 120, and
singulation is performed to complete the solid-state imaging device
111.
[0311] By such steps as described above, the wires 134A are formed
by the through-vias formed from the front face side (imaging face
side) to establish a state in which the solid-state imaging element
120 and the memory circuit 121 and logic circuit 122 are
electrically connected to each other, and the solid-state imaging
device 111 is manufactured thereby.
[0312] It is to be noted that also the wires 134F to 134H depicted
in the connection examples 33B to 33C can be manufactured by
similar steps although they are different in terms of the position,
depth and number of through-vias.
[0313] Also, in such a configuration as described above, since
circuit connection between the solid-state imaging element 120 and
the memory circuit 121 and logic circuit 122 can be established
through terminals formed in a wire density of fine wires by a
lithography technique of semiconductors similarly as in the WoW,
the number of connection terminals can be increased and reduction
of the power consumption can be anticipated.
10. Modification of Example of Connection to Solid-State Imaging
Element
[0314] <First modification of connection example to solid-state
imaging element>
[0315] The electric connection between the solid-state imaging
element 120 and the memory circuit 121 and logic circuit 122 may be
different from the connection examples of FIGS. 29 and 33.
[0316] FIG. 37 depicts a modification of the electric connection
example between the solid-state imaging element 120 and the memory
circuit 121 and logic circuit 122 of the solid-state imaging device
111.
[0317] In FIG. 37, a first semiconductor substrate 321, a second
semiconductor substrate 322 and a third semiconductor substrate 323
are stacked from above, and it is assumed that a solid-state
imaging element 120 is formed in the first semiconductor substrate
321 while the memory circuit 121 is formed in the second
semiconductor substrate 322 and the logic circuit 122 is formed in
the third semiconductor substrate 323. It is to be noted that the
substrates in which the memory circuit 121 and the logic circuit
122 are formed may be replaced with each other.
[0318] Further, in the first semiconductor substrate 321, the
second semiconductor substrate 322, and the third semiconductor
substrate 323, multilayer wiring layers 331, 332, and 333 for the
solid-state imaging element 120, the memory circuit 121, and the
logic circuit 122 are formed, respectively. Further, in FIG. 37,
the multilayer wiring layer 332 is directed to the third
semiconductor substrate 323, and the multilayer wiring layers 332
and 333 are structured such that they are pasted to each other on
the boundary between the second semiconductor substrate 322 and the
third semiconductor substrate 323.
[0319] Furthermore, pads 341 and 342 for external connection
including metal such as, for example, aluminum are provided, and a
signal to and from an external apparatus connected through a pad
hole 350 is inputted and outputted through a pad 341 connected to
the pad 342.
[0320] As depicted in FIG. 37, the pad hole 350 is formed in the
first semiconductor substrate 321 such that it extends to the pad
341 from the rear face side (light receiving face side) of the
first semiconductor substrate 321. Further, the pad 342 is formed
in the multilayer wiring layer 331 of the first semiconductor
substrate 321.
[0321] Further, in the configuration of FIG. 37, a contact 351 used
for electric connection between the first semiconductor substrate
321 and the second semiconductor substrate 322 and a contact 352
used for electric connection between the second semiconductor
substrate 322 and the third semiconductor substrate 323 are
provided. The contact 351 and the contact 352 are configured as
twin contacts.
[0322] In particular, for electric connection between the
solid-state imaging element 120 and the memory circuit 121 and
logic circuit 122, the twin contacts 351 and 352 may be used as
depicted in FIG. 37.
[0323] <Second modification of connection example to solid-state
imaging element>
[0324] As depicted in FIG. 38, the multilayer wiring layer 331 of
the first semiconductor substrate 321 may be directed to the second
semiconductor substrate 322 side (upper side in the figure) such
that the multilayer wiring layers 331 and 332 are pasted to each
other on the boundary between the first semiconductor substrate 321
and the second semiconductor substrate 322.
[0325] In the configuration of FIG. 38, different from that of the
case of FIG. 37, the pad 342 is provided in the multilayer wiring
layer 332 of the second semiconductor substrate 322. Further, in
the first semiconductor substrate 321, the pad hole 350 is formed
so as to extend to the pad 341 from the rear face side (light
receiving face side) of the first semiconductor substrate 321.
[0326] Further, in the configuration of FIG. 38, a contact 361 used
for electric connection between the first semiconductor substrate
321 and the second semiconductor substrate 322 and a contact 362
used for electric connection between the second semiconductor
substrate 322 and the third semiconductor substrate 323 are
provided. The contacts 361 and 362 are configured as twin
contacts.
[0327] In the case of the configuration of FIG. 38, different from
that of the case of FIG. 37, the contact 362 extends through the
first semiconductor substrate 321 and the second semiconductor
substrate 322 to the multilayer wiring layer 333 of the third
semiconductor substrate 323.
[0328] In particular, as depicted in FIG. 38, for electric
connection between the solid-state imaging element 120 and the
memory circuit 121 and logic circuit 122, the twin contacts 361 and
362 may be used.
[0329] <Third modification of connection example to solid-state
imaging element>
[0330] In the configuration of FIG. 39, the first semiconductor
substrate 321 and the second semiconductor substrate 322 are pasted
to each other such that an insulating film layer 371 for the second
semiconductor substrate 322 is directed to the third semiconductor
substrate 323 side (lower side in the figure).
[0331] Further, in the configuration of FIG. 39, similarly as in
FIG. 37, a contact 351 used for electric connection between the
first semiconductor substrate 321 and the second semiconductor
substrate 322 and a contact 352 used for electric connection
between the second semiconductor substrate 322 and the third
semiconductor substrate 323 are provided. The contacts 351 and 352
are configured as twin contacts.
[0332] Furthermore, in the configuration of FIG. 39, different from
that of the case of FIG. 37, the insulating film layer 371 is
formed between the first semiconductor substrate 321 and the second
semiconductor substrate 322. Further, the pad 341 is arranged in
the insulating film layer 371, and the pad 341 is connected to a
contact 372 connected to the multilayer wiring layer 332 of the
second semiconductor substrate 322.
[0333] Further, in the configuration of FIG. 39, the pad hole 350
is formed in the first semiconductor substrate 321 such that it
extends to the pad 341 in the insulating film layer 371 from the
rear face side (light receiving face side) of the first
semiconductor substrate 321.
[0334] In particular, as depicted in FIG. 39, for electric
connection between the solid-state imaging element 120 and the
memory circuit 121 and logic circuit 122, the twin contacts 351 and
352 may be used. Further, the pad 341 may be configured so as to be
connected to the insulating film layer 372 connected to the
multilayer wiring layer 332 of the second semiconductor substrate
322.
[0335] <Fourth modification of connection example to solid-state
imaging element>
[0336] In the configuration of FIG. 40, similarly as in that of the
case of FIG. 37, the pad hole 350 is formed in the first
semiconductor substrate 321 such that it extends from the rear face
side (light receiving face side) of the first semiconductor
substrate 321 to the pad 341. Further, the pad 342 is formed in the
multilayer wiring layer 331 of the first semiconductor substrate
321.
[0337] In the configuration of FIG. 40, similarly to that in the
case of FIG. 37, the first semiconductor substrate 321 and the
second semiconductor substrate 322 are pasted to each other such
that the multilayer wiring layer 332 of the second semiconductor
substrate 322 is directed to the third semiconductor substrate 323
side (lower side in the figure).
[0338] Further, in the configuration of FIG. 40, similarly as in
the case of FIG. 37, the contact 351 used for electric connection
between the first semiconductor substrate 321 and the second
semiconductor substrate 322 is provided. The contact 351 is
configured as a twin contact.
[0339] In the configuration of FIG. 40, different from that of the
case of FIG. 37, the contact 352 used for electric connection
between the second semiconductor substrate 322 and the third
semiconductor substrate 323 is not provided. On the other hand,
contacts 381 and 382 used for electric connection between the
second semiconductor substrate 322 and the third semiconductor
substrate 323 are provided.
[0340] Each of the contacts 381 and 382 is formed by providing a
through hole that extends through the second semiconductor
substrate 322 to the multilayer wiring layer 333 of the third
semiconductor substrate 323 and embedding a conductor in the
through hole. In particular, each of the contacts 381 and 382 is
configured so as to connect the multilayer wiring layer 332 of the
second semiconductor substrate 322 and the multilayer wiring layer
333 of the third semiconductor substrate 323 only by providing one
through hole.
[0341] In short, each of the contacts 381 and 382 is configured as
a shared contact.
[0342] Also, in the solid-state imaging devices 111 having the
configurations described above with reference to FIGS. 37 to 39, a
shared contact may be used for electric connection between the
first semiconductor substrate 321 and the second semiconductor
substrate 322 or for electric connection between the second
semiconductor substrate 322 and the third semiconductor substrate
323.
[0343] In particular, as depicted in FIG. 40, the twin contact 351
and the contacts 381 and 382 may be used for electric connection
between the solid-state imaging element 120 and the memory circuit
121 and logic circuit 122.
[0344] <Fifth modification of connection example to solid-state
imaging element>
[0345] In the configuration of FIG. 41, similarly as in the case of
FIG. 37, the pad hole 350 is formed in the first semiconductor
substrate 321 such that it extends to the pad 341 from the rear
face side (light receiving face side) of the first semiconductor
substrate 321. Further, the pad 342 is formed in the multilayer
wiring layer 331 of the first semiconductor substrate 321.
[0346] Further, in the configuration of FIG. 41, similarly to that
in the case of FIG. 37, the first semiconductor substrate 321 and
the second semiconductor substrate 322 are pasted to each other
such that the multilayer wiring layer 332 of the second
semiconductor substrate 322 is directed to the third semiconductor
substrate 323 side (lower side in the figure).
[0347] Furthermore, in the configuration of FIG. 41, a contact 391
used for electric connection between the second semiconductor
substrate 322 and the third semiconductor substrate 323 is
provided. The contact 391 is configured as a twin contact.
[0348] Further, in the configuration of FIG. 41, a metal wire 332a
in the multilayer wiring layer 332 of the second semiconductor
substrate 322 and a metal wire 333a in the multilayer wiring layer
333 of the third semiconductor substrate 323 are joined directly to
each other. Furthermore, a metal wire 332b in the multilayer wiring
layer 332 and a metal wire 333b in the multilayer wiring layer 333
are joined directly to each other. Consequently, the second
semiconductor substrate 322 and the third semiconductor substrate
323 are electrically connected to each other.
[0349] In short, in the case of the configuration of FIG. 41, not a
contact but direct joining is used for electric connection between
the second semiconductor substrate 322 and the third semiconductor
substrate 323. Accordingly, the manufacturing step can be
simplified and the area on the substrate can be reduced.
[0350] In particular, as depicted in FIG. 41, for electric
connection between the solid-state imaging element 120 and the
memory circuit 121 and logic circuit 122, the twin contact 391 and
the metal wires 332a, 333a and 332b, 333b may be used.
[0351] <Modification of connection example to solid-state
imaging element of sixth embodiment>
[0352] In the configuration of FIG. 42, different from that of the
case of FIG. 41, contacts 401 and 402 used for electric connection
between the first semiconductor substrate 321 and the second
semiconductor substrate 322 are provided. In particular, in the
case of the configuration of FIG. 42, a lower side end portion of
the left side in the figure of the contact 401 is connected to an
upper side end portion in the figure of the contact 402 to
electrically connect the first semiconductor substrate 321 and the
second semiconductor substrate 322 to each other. It is to be noted
that the contact 401 is configured as a twin contact.
[0353] In the configuration of FIG. 42, it is not necessary to
provide a hole that extends to the multilayer wiring layer 332 from
the light receiving face, for example, as in the formation of the
contact 391 of FIG. 41. Therefore, it is possible to perform
formation of a contact more simply.
[0354] The configuration of the other part in FIG. 42 is similar to
that of the case of FIG. 41, and therefore, detailed description of
the same is omitted.
[0355] In particular, as depicted in FIG. 42, for electric
connection between the solid-state imaging element 120 and the
memory circuit 121 and logic circuit 122, the twin contacts 401 and
402 and the metal wires 332a, 333a and 332b, 333b may be used.
[0356] <<11. Heat Dissipation Structure>>
[0357] Since the solid-state imaging element 120 of high picture
quality and a high frame rate is likely to generate heat, heat
dissipation measures are required. Since the solid-state imaging
element 120 performs optical sensing, the surface to be sensed
takes in light, and therefore, a lens 431 is arranged at a
preceding stage to the solid-state imaging element 120 and a space
432 of air exists as depicted by a side elevational sectional view
43A of FIG. 43.
[0358] Heat generated in the solid-state imaging element 120 moves
in response to the thermal conductivity of the material. Since the
thermal conductivity of the air is approximately 7000 times the
thermal conductivity of silicon, almost all of the generated heat
is dissipated not through the space 432 of the air but through the
material contacting with the solid-state imaging element 120.
Accordingly, for example, in such a configuration as depicted in
the side elevational sectional view 43A of FIG. 43, heat generated
by the solid-state imaging element 120 moves to and is dissipated
by the oxide film 133 and logic circuit 122 and the support
substrate 132 as indicated by arrow marks.
[0359] As depicted by the side elevational sectional view 43A of
FIG. 43, the logic circuit 122 (or memory circuit 121) is covered
therearound with the oxide film 133 in order to bury the height for
flattening.
[0360] Since the thickness of the oxide film joining layer 135 of
each substrate is very small, the heat resistance is low. However,
the height of the logic circuit 122 (or the memory circuit 121) is
great in comparison with the thickness of the oxide film joining
layer 135, and the thermal conductivity of the oxide film 133 is
lower than that of silicon that is the material of the logic
circuit 122 (or the memory circuit 121). Therefore, the heat
mobility differs between an area in which the logic circuit 122 (or
the memory circuit 121) is connected and another area that is
covered with the oxide film 133.
[0361] It is to be noted that, in the side elevational sectional
view 43A of FIG. 43, a magnitude of an arrow mark represents a
magnitude of the heat mobility, and it is represented that, as the
arrow mark becomes great, the heat mobility becomes high and the
heat dissipation efficiency becomes high. In particular, in the
side elevational sectional view 43A of FIG. 43, it is represented
that, since the thermal conductivity of the logic circuit 122 (or
the memory circuit 121) is higher than that of the oxide film 133,
the heat dissipation efficiency of the logic circuit 122 (or the
memory circuit 121) is higher.
[0362] Therefore, as depicted by the side elevational sectional
view 43B of FIG. 43, a dummy circuit 441 including silicon and
similar to a member configuring the logic circuit 122 (or the
memory circuit 121) may be provided in an area of the oxide film
133 in which the logic circuit 122 (or the memory circuit 121) is
not formed. Since the thermal conductivity of silicon configuring
the dummy circuit 441 is higher than the thermal conductivity of
the oxide film 133, heat dissipation can be performed more
efficiently than where heat is dissipated through the oxide film
133 as indicated by arrow marks.
[0363] As depicted by the side elevational sectional view 43B of
FIG. 43, in the case where the dummy circuit 441 is provided, when
the WoW technology is applied for manufacturing, from among logic
circuits 122 formed on the wafer 104 by a semiconductor process,
those logic circuits 122 that are determined as good products as a
result of electric inspection are rearranged on a wafer 451 as
depicted in FIG. 44.
[0364] Thereupon, on the wafer 451, the dummy circuit 441 is
rearranged in advance around the logic circuit 122 (or the memory
circuit 121) on the wafer 451 such that such arrangement as
depicted by the side elevational sectional view 43A of FIG. 43 is
obtained. Then, after the wafer 101 on which the solid-state
imaging element 120 is formed by a semiconductor process is
positioned and stacked on the wafer 451, it is singulated to
complete a solid-state imaging device 111.
[0365] <First Modification of Heat Dissipation Structure>
[0366] Although the foregoing description is directed to an example
in which the dummy circuit 441 is arranged in place of the oxide
film 133 around the logic circuit 122 or the memory circuit 121, a
dummy wire including metal having a higher thermal conductivity may
be included for the dummy circuit 441.
[0367] For example, the dummy circuit 441 may further include a
dummy wire 441a as depicted in FIG. 45.
[0368] In particular, in the case of FIG. 45, since the dummy wire
441a including a metal having a thermal conductivity higher than
that of silicon is included in the dummy circuit 441, heat can be
dissipated in a higher efficiency.
[0369] <Second Modification of Heat Dissipation
Structure>
[0370] Although the foregoing description is directed to an example
in which the dummy circuit 441 including the dummy wire 441a is
provided in place of the oxide film 133 around the logic circuit
122 or the memory circuit 121 to improve the heat dissipation
efficiency, a high thermal conductivity material member may be
pasted to the rear side of the support substrate 132 to improve the
heat dissipation efficiency.
[0371] FIG. 46 depicts an example of a configuration of the
solid-state imaging device 111 in which a high thermal conductive
material is pasted to the rear side of the support substrate
132.
[0372] In particular, as depicted by the side elevational sectional
view 46A, a high thermal conductivity material member 471 including
a high thermal conductivity material is pasted to the rear side
(lower side in the figure) of the support substrate 132. The high
thermal conductivity material member 471 is, for example, SiC, AlN,
SIN, Cu, Al, C or the like.
[0373] In the case where the high thermal conductivity material
member 471 is pasted to the rear side of the support substrate 132,
when the WoW technology is used for manufacturing, as depicted by
the perspective view 46B, a wafer 481 including the high thermal
conductivity material member 471 is stacked under the wafer 201 on
which, from among logic circuits 122 formed on the wafer 104 by a
semiconductor process, those logic circuits 122 that are deemed as
good products as a result of electric inspection are
rearranged.
[0374] In particular, in this case, three wafers including the
wafer 101 on which the solid-state imaging elements 120 are formed
by a semiconductor process, wafer 201 on which the logic circuits
122 of good products are rearranged and wafer 481 including the
high thermal conductivity material member 471 are stacked from
above in the figure.
[0375] Further, as depicted by the side elevational sectional view
46C of FIG. 46, the high thermal conductivity material member 471
may be formed in a space around the logic circuit 122 and embedded
into the oxide film 133.
[0376] <Third Modification of Heat Dissipation Structure>
[0377] Although the foregoing description is directed to an example
in which the high thermal conductivity material member 471 is
pasted to the rear side of the support substrate 132 to improve the
heat dissipation efficiency, a heat radiation mechanism of the
water cooled type may be provided further by providing a waterway
for circulating cooling water in the high thermal conductivity
material member 471.
[0378] FIG. 47 depicts an example of a configuration of the
solid-state imaging device 111 in which a heat dissipation
mechanism of the water cooled type is formed to further improve the
heat dissipation efficiency.
[0379] In particular, although the solid-state imaging device 111
of FIG. 47 has, as depicted by the side elevational sectional view
47A of FIG. 47, a basic configuration similar to the configuration
of the solid-state imaging device 111 described hereinabove with
reference to FIG. 46, a waterway 491 for cooling water is further
provided in the high thermal conductivity material member 471.
[0380] By circulating cooling water in the waterway 491, a heat
dissipation mechanism of the water cooled type is formed, and this
makes it possible to dissipate heat generated by the solid-state
imaging element 120 through the cooling water and dissipate heat
more efficiently.
[0381] In the case where the heat dissipation mechanism of the
water cooled type is provided, as depicted by the perspective view
47B of FIG. 47, the wafers 101 and 201 to be stacked are stacked on
the wafer 481 in a state in which the waterway 491 is formed such
that it is positioned relative to the solid-state imaging element
120 and the logic circuit 122 of the wafers 101 and 201 to be
stacked.
[0382] <Fourth Modification of Heat Dissipation
Structure>
[0383] Although the foregoing description is directed to an example
in which a region that forms a gap is filled up with the oxide film
133 around the memory circuit 121 and the logic circuit 122 as
depicted by the left upper portion of FIG. 48, much time is
required to fill up the oxide film 133, and therefore, the process
cost increases.
[0384] Therefore, a gap in a peripheral portion of the memory
circuit 121 and the logic circuit 122 may be filled with an organic
material member 495 including an organic material in place of the
oxide film 133 as depicted by the right upper portion of FIG. 48 to
form a heat dissipation structure.
[0385] However, if a peripheral portion of the memory circuit 121
and the logic circuit 122 is filled up with the organic material
member 495, then when the oxide film joining layer 135 is formed on
the uppermost face, the flatness of the oxide film joining layer
135 is damaged by an influence of heat or warping or swelling is
generated by a difference in linear expansion coefficient of the
embedded material. Thus, pasting of the support substrate 132 is
sometimes disabled.
[0386] Therefore, as indicated by the lower portion of FIG. 48,
preferably the layout is formed so as to minimize the gap based on
the shape of the shape of the memory circuit 121, logic circuit 122
and dummy circuit 441. By performing layout of them so as to
minimize the gap in this manner, the amount of use of the organic
material member 495 is made to the minimum necessity. Consequently,
the influence of heat when the oxide film joining layer 135 is
formed on the uppermost face and the influence of warping or
swelling caused by a difference in linear expansion coefficient of
the embedded material can be minimized, and pasting to the support
substrate 132 can be implemented.
12. Example of Application to Electronic Equipment
[0387] The imaging element described above can be applied to
various electronic equipment such as, for example, an imaging
apparatus such as a digital still camera or a digital video camera,
a portable telephone set having an imaging function or other
equipment having an imaging function.
[0388] FIG. 49 is a block diagram depicting an example of a
configuration of an imaging apparatus as electronic equipment to
which the present technology is applied.
[0389] The imaging apparatus 501 depicted in FIG. 49 includes an
optical system 502, a shutter device 503, a solid-state imaging
element 504, a drive circuit 505, a signal processing circuit 506,
a monitor 507 and a memory 508 and can capture a still image and a
moving image.
[0390] The optical system 502 includes one or a plurality of lenses
and introduces light (incident light) from an imaging target to the
solid-state imaging element 504 such that an image is formed on a
light receiving face of the solid-state imaging element 504.
[0391] The shutter device 503 is arranged between the optical
system 502 and the solid-state imaging element 504 and controls a
light irradiation period and a light blocking period to the
solid-state imaging element 504 under the control of the drive
circuit 505.
[0392] The solid-state imaging element 504 includes a package
including the solid-state imaging element described hereinabove.
The solid-state imaging element 504 accumulates signal charge for a
period of time in response to light of an image formed on the light
receiving face thereof through the optical system 502 and the
shutter device 503. The signal charge accumulated in the
solid-state imaging element 504 is transferred in accordance with a
driving signal (timing signal) supplied from the drive circuit
505.
[0393] The drive circuit 505 outputs driving signals for
controlling transfer operation of the solid-state imaging element
504 and shutter operation of the shutter device 503 to drive the
solid-state imaging element 504 and the shutter device 503,
respectively.
[0394] The signal processing circuit 506 performs various signal
processes for signal charge outputted from the solid-state imaging
element 504. An image (image data) obtained by the signal processes
performed by the signal processing circuit 506 is supplied to and
displayed on the monitor 507 or is supplied to and stored
(recorded) into the memory 508.
[0395] Also, in the imaging apparatus 501 configured in this
manner, by applying the solid-state imaging device 111 described
hereinabove to the optical system 502 and the solid-state imaging
element 204, the yield can be improved and the cost required for
manufacture can be reduced.
13. Example of Use of Imaging Element
[0396] FIG. 50 is a view depicting examples of use where the
solid-state imaging device 111 described hereinabove is used.
[0397] The imaging element described above can be used for various
cases in which visible rays, infrared rays, ultraviolet rays,
X-rays or the like are used, for example, as described below.
[0398] An apparatus that captures an image to be used for
appreciation such as a digital camera, a portable apparatus with a
camera function and so forth
[0399] An apparatus used in traffic such as automotive sensors for
capturing the front, back, surrounding, inside and so forth of an
automobile for safe driving such as automatic stop, recognition of
a state of the driver and so forth, surveillance cameras for
monitoring a travelling vehicle or a road, distance measurement
sensors that perform distance measurement between vehicles and so
forth and like sensors
[0400] An apparatus used in home appliances such as a TV, a
refrigerator, an air conditioner and so forth in order to image a
gesture of a user to perform apparatus operation according to the
gesture
[0401] An apparatus for medical use or health care use such as an
endoscope, an apparatus for angiography by light reception of
infrared rays and so forth
[0402] An apparatus for security use such as surveillance cameras
for security applications, cameras for person authentication and so
forth
[0403] An apparatus for beauty such as skin measuring instruments
for imaging the skin, microscopes for imaging the scalp and so
forth
[0404] An apparatus for sports use such as action cameras, wearable
cameras and so forth for sports applications
[0405] An apparatus for agricultural use such as cameras for
monitoring the state of the fields, produces and so forth
14. Example of Application to Endoscopic Surgery System
[0406] The technology according to the present disclosure (present
technology) can be applied to various products. For example, the
technology according to the present disclosure may be applied to an
endoscopic surgery system.
[0407] FIG. 51 is a view depicting an example of a schematic
configuration of an endoscopic surgery system to which the
technology according to an embodiment of the present disclosure
(present technology) can be applied.
[0408] In FIG. 51, a state is illustrated in which a surgeon
(medical doctor) 11131 is using an endoscopic surgery system 11000
to perform surgery for a patient 11132 on a patient bed 11133. As
depicted, the endoscopic surgery system 11000 includes an endoscope
11100, other surgical tools 11110 such as a pneumoperitoneum tube
11111 and an energy device 11112, a supporting arm apparatus 11120
which supports the endoscope 11100 thereon, and a cart 11200 on
which various apparatus for endoscopic surgery are mounted.
[0409] The endoscope 11100 includes a lens barrel 11101 having a
region of a predetermined length from a distal end thereof to be
inserted into a body cavity of the patient 11132, and a camera head
11102 connected to a proximal end of the lens barrel 11101. In the
example depicted, the endoscope 11100 is depicted which includes as
a rigid endoscope having the lens barrel 11101 of the hard type.
However, the endoscope 11100 may otherwise be included as a
flexible endoscope having the lens barrel 11101 of the flexible
type.
[0410] The lens barrel 11101 has, at a distal end thereof, an
opening in which an objective lens is fitted. A light source
apparatus 11203 is connected to the endoscope 11100 such that light
generated by the light source apparatus 11203 is introduced to a
distal end of the lens barrel 11101 by a light guide extending in
the inside of the lens barrel 11101 and is irradiated toward an
observation target in a body cavity of the patient 11132 through
the objective lens. It is to be noted that the endoscope 11100 may
be a forward-viewing endoscope or may be an oblique-viewing
endoscope or a side-viewing endoscope.
[0411] An optical system and an image pickup element are provided
in the inside of the camera head 11102 such that reflected light
(observation light) from the observation target is condensed on the
image pickup element by the optical system. The observation light
is photo-electrically converted by the image pickup element to
generate an electric signal corresponding to the observation light,
namely, an image signal corresponding to an observation image. The
image signal is transmitted as RAW data to a CCU 11201.
[0412] The CCU 11201 includes a central processing unit (CPU), a
graphics processing unit (GPU) or the like and integrally controls
operation of the endoscope 11100 and a display apparatus 11202.
Further, the CCU 11201 receives an image signal from the camera
head 11102 and performs, for the image signal, various image
processes for displaying an image based on the image signal such
as, for example, a development process (demosaic process).
[0413] The display apparatus 11202 displays thereon an image based
on an image signal, for which the image processes have been
performed by the CCU 11201, under the control of the CCU 11201.
[0414] The light source apparatus 11203 includes a light source
such as, for example, a light emitting diode (LED) and supplies
irradiation light upon imaging of a surgical region to the
endoscope 11100.
[0415] An inputting apparatus 11204 is an input interface for the
endoscopic surgery system 11000. A user can perform inputting of
various kinds of information or instruction inputting to the
endoscopic surgery system 11000 through the inputting apparatus
11204. For example, the user would input an instruction or a like
to change an image pickup condition (type of irradiation light,
magnification, focal distance or the like) by the endoscope
11100.
[0416] A treatment tool controlling apparatus 11205 controls
driving of the energy device 11112 for cautery or incision of a
tissue, sealing of a blood vessel or the like. A pneumoperitoneum
apparatus 11206 feeds gas into a body cavity of the patient 11132
through the pneumoperitoneum tube 11111 to inflate the body cavity
in order to secure the field of view of the endoscope 11100 and
secure the working space for the surgeon. A recorder 11207 is an
apparatus capable of recording various kinds of information
relating to surgery. A printer 11208 is an apparatus capable of
printing various kinds of information relating to surgery in
various forms such as a text, an image or a graph.
[0417] It is to be noted that the light source apparatus 11203
which supplies irradiation light when a surgical region is to be
imaged to the endoscope 11100 may include a white light source
which includes, for example, an LED, a laser light source or a
combination of them. Where a white light source includes a
combination of red, green, and blue (RGB) laser light sources,
since the output intensity and the output timing can be controlled
with a high degree of accuracy for each color (each wavelength),
adjustment of the white balance of a picked up image can be
performed by the light source apparatus 11203. Further, in this
case, if laser beams from the respective RGB laser light sources
are irradiated time-divisionally on an observation target and
driving of the image pickup elements of the camera head 11102 are
controlled in synchronism with the irradiation timings. Then images
individually corresponding to the R, G and B colors can be also
picked up time-divisionally. According to this method, a color
image can be obtained even if color filters are not provided for
the image pickup element.
[0418] Further, the light source apparatus 11203 may be controlled
such that the intensity of light to be outputted is changed for
each predetermined time. By controlling driving of the image pickup
element of the camera head 11102 in synchronism with the timing of
the change of the intensity of light to acquire images
time-divisionally and synthesizing the images, an image of a high
dynamic range free from underexposed blocked up shadows and
overexposed highlights can be created.
[0419] Further, the light source apparatus 11203 may be configured
to supply light of a predetermined wavelength band ready for
special light observation. In special light observation, for
example, by utilizing the wavelength dependency of absorption of
light in a body tissue to irradiate light of a narrow band in
comparison with irradiation light upon ordinary observation
(namely, white light), narrow band observation (narrow band
imaging) of imaging a predetermined tissue such as a blood vessel
of a superficial portion of the mucous membrane or the like in a
high contrast is performed. Alternatively, in special light
observation, fluorescent observation for obtaining an image from
fluorescent light generated by irradiation of excitation light may
be performed. In fluorescent observation, it is possible to perform
observation of fluorescent light from a body tissue by irradiating
excitation light on the body tissue (autofluorescence observation)
or to obtain a fluorescent light image by locally injecting a
reagent such as indocyanine green (ICG) into a body tissue and
irradiating excitation light corresponding to a fluorescent light
wavelength of the reagent upon the body tissue. The light source
apparatus 11203 can be configured to supply such narrow-band light
and/or excitation light suitable for special light observation as
described above.
[0420] FIG. 52 is a block diagram depicting an example of a
functional configuration of the camera head 11102 and the CCU 11201
depicted in FIG. 51.
[0421] The camera head 11102 includes a lens unit 11401, an image
pickup unit 11402, a driving unit 11403, a communication unit 11404
and a camera head controlling unit 11405. The CCU 11201 includes a
communication unit 11411, an image processing unit 11412 and a
control unit 11413. The camera head 11102 and the CCU 11201 are
connected for communication to each other by a transmission cable
11400.
[0422] The lens unit 11401 is an optical system, provided at a
connecting location to the lens barrel 11101. Observation light
taken in from a distal end of the lens barrel 11101 is guided to
the camera head 11102 and introduced into the lens unit 11401. The
lens unit 11401 includes a combination of a plurality of lenses
including a zoom lens and a focusing lens.
[0423] The number of image pickup elements which is included by the
image pickup unit 11402 may be one (single-plate type) or a plural
number (multi-plate type). Where the image pickup unit 11402 is
configured as that of the multi-plate type, for example, image
signals corresponding to respective R, G and B are generated by the
image pickup elements, and the image signals may be synthesized to
obtain a color image. The image pickup unit 11402 may also be
configured so as to have a pair of image pickup elements for
acquiring respective image signals for the right eye and the left
eye ready for three dimensional (3D) display. If 3D display is
performed, then the depth of a living body tissue in a surgical
region can be comprehended more accurately by the surgeon 11131. It
is to be noted that, where the image pickup unit 11402 is
configured as that of stereoscopic type, a plurality of systems of
lens units 11401 are provided corresponding to the individual image
pickup elements.
[0424] Further, the image pickup unit 11402 may not necessarily be
provided on the camera head 11102. For example, the image pickup
unit 11402 may be provided immediately behind the objective lens in
the inside of the lens barrel 11101.
[0425] The driving unit 11403 includes an actuator and moves the
zoom lens and the focusing lens of the lens unit 11401 by a
predetermined distance along an optical axis under the control of
the camera head controlling unit 11405. Consequently, the
magnification and the focal point of a picked up image by the image
pickup unit 11402 can be adjusted suitably.
[0426] The communication unit 11404 includes a communication
apparatus for transmitting and receiving various kinds of
information to and from the CCU 11201. The communication unit 11404
transmits an image signal acquired from the image pickup unit 11402
as RAW data to the CCU 11201 through the transmission cable
11400.
[0427] In addition, the communication unit 11404 receives a control
signal for controlling driving of the camera head 11102 from the
CCU 11201 and supplies the control signal to the camera head
controlling unit 11405. The control signal includes information
relating to image pickup conditions such as, for example,
information that a frame rate of a picked up image is designated,
information that an exposure value upon image picking up is
designated and/or information that a magnification and a focal
point of a picked up image are designated.
[0428] It is to be noted that the image pickup conditions such as
the frame rate, exposure value, magnification or focal point may be
designated by the user or may be set automatically by the control
unit 11413 of the CCU 11201 on the basis of an acquired image
signal. In the latter case, an auto exposure (AE) function, an auto
focus (AF) function and an auto white balance (AWB) function are
incorporated in the endoscope 11100.
[0429] The camera head controlling unit 11405 controls driving of
the camera head 11102 on the basis of a control signal from the CCU
11201 received through the communication unit 11404.
[0430] The communication unit 11411 includes a communication
apparatus for transmitting and receiving various kinds of
information to and from the camera head 11102. The communication
unit 11411 receives an image signal transmitted thereto from the
camera head 11102 through the transmission cable 11400.
[0431] Further, the communication unit 11411 transmits a control
signal for controlling driving of the camera head 11102 to the
camera head 11102. The image signal and the control signal can be
transmitted by electrical communication, optical communication or
the like.
[0432] The image processing unit 11412 performs various image
processes for an image signal in the form of RAW data transmitted
thereto from the camera head 11102.
[0433] The control unit 11413 performs various kinds of control
relating to image picking up of a surgical region or the like by
the endoscope 11100 and display of a picked up image obtained by
image picking up of the surgical region or the like. For example,
the control unit 11413 creates a control signal for controlling
driving of the camera head 11102.
[0434] Further, the control unit 11413 controls, on the basis of an
image signal for which image processes have been performed by the
image processing unit 11412, the display apparatus 11202 to display
a picked up image in which the surgical region or the like is
imaged. Thereupon, the control unit 11413 may recognize various
objects in the picked up image using various image recognition
technologies. For example, the control unit 11413 can recognize a
surgical tool such as forceps, a particular living body region,
bleeding, mist when the energy device 11112 is used and so forth by
detecting the shape, color and so forth of edges of objects
included in a picked up image. The control unit 11413 may cause,
when it controls the display apparatus 11202 to display a picked up
image, various kinds of surgery supporting information to be
displayed in an overlapping manner with an image of the surgical
region using a result of the recognition. Where surgery supporting
information is displayed in an overlapping manner and presented to
the surgeon 11131, the burden on the surgeon 11131 can be reduced
and the surgeon 11131 can proceed with the surgery with
certainty.
[0435] The transmission cable 11400 which connects the camera head
11102 and the CCU 11201 to each other is an electric signal cable
ready for communication of an electric signal, an optical fiber
ready for optical communication or a composite cable ready for both
of electrical and optical communications.
[0436] Here, while, in the example depicted, communication is
performed by wired communication using the transmission cable
11400, the communication between the camera head 11102 and the CCU
11201 may be performed by wireless communication.
[0437] An example of an endoscopic surgery system to which the
technology according to the present disclosure can be applied has
been described. The technology according to the present disclosure
can be applied to the endoscope 11100, (image pickup unit 11402 of
the) camera head 11102, and so forth among the components described
hereinabove. In particular, the solid-state imaging device 111 of
the present disclosure can be applied to the image pickup unit
10402. By applying the technology of the present disclosure to the
endoscope 11100, (image pickup unit 11402 of the) camera head 11102
or the like, it is possible to improve the yield and reduce the
cost required for manufacture.
[0438] It is to be noted here that, although the endoscopic surgery
system has been described as an example, the technology according
to the present disclosure may be further applied, for example, to a
microscopic surgery system or the like.
15. Example of Application to Mobile Body
[0439] The technology according to the present disclosure (present
technology) can be applied to various products. For example, the
technology according to the present disclosure may be implemented
as an apparatus incorporated in a mobile body of any type such as,
for example, an automobile, an electric vehicle, a hybrid electric
vehicle, a motorcycle, a bicycle, a personal mobility, an airplane,
a drone, a ship, a robot and so forth.
[0440] FIG. 53 is a block diagram depicting an example of schematic
configuration of a vehicle control system as an example of a mobile
body control system to which the technology according to an
embodiment of the present disclosure can be applied.
[0441] The vehicle control system 12000 includes a plurality of
electronic control units connected to each other via a
communication network 12001. In the example depicted in FIG. 53,
the vehicle control system 12000 includes a driving system control
unit 12010, a body system control unit 12020, an outside-vehicle
information detecting unit 12030, an in-vehicle information
detecting unit 12040, and an integrated control unit 12050. In
addition, a microcomputer 12051, a sound/image output section
12052, and a vehicle-mounted network interface (I/F) 12053 are
illustrated as a functional configuration of the integrated control
unit 12050.
[0442] The driving system control unit 12010 controls the operation
of devices related to the driving system of the vehicle in
accordance with various kinds of programs. For example, the driving
system control unit 12010 functions as a control device for a
driving force generating device for generating the driving force of
the vehicle, such as an internal combustion engine, a driving
motor, or the like, a driving force transmitting mechanism for
transmitting the driving force to wheels, a steering mechanism for
adjusting the steering angle of the vehicle, a braking device for
generating the braking force of the vehicle, and the like.
[0443] The body system control unit 12020 controls the operation of
various kinds of devices provided to a vehicle body in accordance
with various kinds of programs. For example, the body system
control unit 12020 functions as a control device for a keyless
entry system, a smart key system, a power window device, or various
kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a
turn signal, a fog lamp, or the like. In this case, radio waves
transmitted from a mobile device as an alternative to a key or
signals of various kinds of switches can be input to the body
system control unit 12020. The body system control unit 12020
receives these input radio waves or signals, and controls a door
lock device, the power window device, the lamps, or the like of the
vehicle.
[0444] The outside-vehicle information detecting unit 12030 detects
information about the outside of the vehicle including the vehicle
control system 12000. For example, the outside-vehicle information
detecting unit 12030 is connected with an imaging section 12031.
The outside-vehicle information detecting unit 12030 makes the
imaging section 12031 image an image of the outside of the vehicle,
and receives the imaged image. On the basis of the received image,
the outside-vehicle information detecting unit 12030 may perform
processing of detecting an object such as a human, a vehicle, an
obstacle, a sign, a character on a road surface, or the like, or
processing of detecting a distance thereto.
[0445] The imaging section 12031 is an optical sensor that receives
light, and which outputs an electric signal corresponding to a
received light amount of the light. The imaging section 12031 can
output the electric signal as an image, or can output the electric
signal as information about a measured distance. In addition, the
light received by the imaging section 12031 may be visible light,
or may be invisible light such as infrared rays or the like.
[0446] The in-vehicle information detecting unit 12040 detects
information about the inside of the vehicle. The in-vehicle
information detecting unit 12040 is, for example, connected with a
driver state detecting section 12041 that detects the state of a
driver. The driver state detecting section 12041, for example,
includes a camera that images the driver. On the basis of detection
information input from the driver state detecting section 12041,
the in-vehicle information detecting unit 12040 may calculate a
degree of fatigue of the driver or a degree of concentration of the
driver, or may determine whether the driver is dozing.
[0447] The microcomputer 12051 can calculate a control target value
for the driving force generating device, the steering mechanism, or
the braking device on the basis of the information about the inside
or outside of the vehicle which information is obtained by the
outside-vehicle information detecting unit 12030 or the in-vehicle
information detecting unit 12040, and output a control command to
the driving system control unit 12010. For example, the
microcomputer 12051 can perform cooperative control intended to
implement functions of an advanced driver assistance system (ADAS)
which functions include collision avoidance or shock mitigation for
the vehicle, following driving based on a following distance,
vehicle speed maintaining driving, a warning of collision of the
vehicle, a warning of deviation of the vehicle from a lane, or the
like.
[0448] In addition, the microcomputer 12051 can perform cooperative
control intended for automatic driving, which makes the vehicle to
travel autonomously without depending on the operation of the
driver, or the like, by controlling the driving force generating
device, the steering mechanism, the braking device, or the like on
the basis of the information about the outside or inside of the
vehicle which information is obtained by the outside-vehicle
information detecting unit 12030 or the in-vehicle information
detecting unit 12040.
[0449] In addition, the microcomputer 12051 can output a control
command to the body system control unit 12020 on the basis of the
information about the outside of the vehicle which information is
obtained by the outside-vehicle information detecting unit 12030.
For example, the microcomputer 12051 can perform cooperative
control intended to prevent a glare by controlling the headlamp so
as to change from a high beam to a low beam, for example, in
accordance with the position of a preceding vehicle or an oncoming
vehicle detected by the outside-vehicle information detecting unit
12030.
[0450] The sound/image output section 12052 transmits an output
signal of at least one of a sound and an image to an output device
capable of visually or auditorily notifying information to an
occupant of the vehicle or the outside of the vehicle. In the
example of FIG. 53, an audio speaker 12061, a display section
12062, and an instrument panel 12063 are illustrated as the output
device. The display section 12062 may, for example, include at
least one of an on-board display and a head-up display.
[0451] FIG. 54 is a diagram depicting an example of the
installation position of the imaging section 12031.
[0452] In FIG. 54, the imaging section 12031 includes imaging
sections 12101, 12102, 12103, 12104, and 12105.
[0453] The imaging sections 12101, 12102, 12103, 12104, and 12105
are, for example, disposed at positions on a front nose, sideview
mirrors, a rear bumper, and a back door of the vehicle 12100 as
well as a position on an upper portion of a windshield within the
interior of the vehicle. The imaging section 12101 provided to the
front nose and the imaging section 12105 provided to the upper
portion of the windshield within the interior of the vehicle obtain
mainly an image of the front of the vehicle 12100. The imaging
sections 12102 and 12103 provided to the sideview mirrors obtain
mainly an image of the sides of the vehicle 12100. The imaging
section 12104 provided to the rear bumper or the back door obtains
mainly an image of the rear of the vehicle 12100. The imaging
section 12105 provided to the upper portion of the windshield
within the interior of the vehicle is used mainly to detect a
preceding vehicle, a pedestrian, an obstacle, a signal, a traffic
sign, a lane, or the like.
[0454] Incidentally, FIG. 54 depicts an example of photographing
ranges of the imaging sections 12101 to 12104. An imaging range
12111 represents the imaging range of the imaging section 12101
provided to the front nose. Imaging ranges 12112 and 12113
respectively represent the imaging ranges of the imaging sections
12102 and 12103 provided to the sideview mirrors. An imaging range
12114 represents the imaging range of the imaging section 12104
provided to the rear bumper or the back door. A bird's-eye image of
the vehicle 12100 as viewed from above is obtained by superimposing
image data imaged by the imaging sections 12101 to 12104, for
example.
[0455] At least one of the imaging sections 12101 to 12104 may have
a function of obtaining distance information. For example, at least
one of the imaging sections 12101 to 12104 may be a stereo camera
constituted of a plurality of imaging elements, or may be an
imaging element having pixels for phase difference detection.
[0456] For example, the microcomputer 12051 can determine a
distance to each three-dimensional object within the imaging ranges
12111 to 12114 and a temporal change in the distance (relative
speed with respect to the vehicle 12100) on the basis of the
distance information obtained from the imaging sections 12101 to
12104, and thereby extract, as a preceding vehicle, a nearest
three-dimensional object in particular that is present on a
traveling path of the vehicle 12100 and which travels in
substantially the same direction as the vehicle 12100 at a
predetermined speed (for example, equal to or more than 0 km/hour).
Further, the microcomputer 12051 can set a following distance to be
maintained in front of a preceding vehicle in advance, and perform
automatic brake control (including following stop control),
automatic acceleration control (including following start control),
or the like. It is thus possible to perform cooperative control
intended for automatic driving that makes the vehicle travel
autonomously without depending on the operation of the driver or
the like.
[0457] For example, the microcomputer 12051 can classify
three-dimensional object data on three-dimensional objects into
three-dimensional object data of a two-wheeled vehicle, a
standard-sized vehicle, a large-sized vehicle, a pedestrian, a
utility pole, and other three-dimensional objects on the basis of
the distance information obtained from the imaging sections 12101
to 12104, extract the classified three-dimensional object data, and
use the extracted three-dimensional object data for automatic
avoidance of an obstacle. For example, the microcomputer 12051
identifies obstacles around the vehicle 12100 as obstacles that the
driver of the vehicle 12100 can recognize visually and obstacles
that are difficult for the driver of the vehicle 12100 to recognize
visually. Then, the microcomputer 12051 determines a collision risk
indicating a risk of collision with each obstacle. In a situation
in which the collision risk is equal to or higher than a set value
and there is thus a possibility of collision, the microcomputer
12051 outputs a warning to the driver via the audio speaker 12061
or the display section 12062, and performs forced deceleration or
avoidance steering via the driving system control unit 12010. The
microcomputer 12051 can thereby assist in driving to avoid
collision.
[0458] At least one of the imaging sections 12101 to 12104 may be
an infrared camera that detects infrared rays. The microcomputer
12051 can, for example, recognize a pedestrian by determining
whether or not there is a pedestrian in imaged images of the
imaging sections 12101 to 12104. Such recognition of a pedestrian
is, for example, performed by a procedure of extracting
characteristic points in the imaged images of the imaging sections
12101 to 12104 as infrared cameras and a procedure of determining
whether or not it is the pedestrian by performing pattern matching
processing on a series of characteristic points representing the
contour of the object. When the microcomputer 12051 determines that
there is a pedestrian in the imaged images of the imaging sections
12101 to 12104, and thus recognizes the pedestrian, the sound/image
output section 12052 controls the display section 12062 so that a
square contour line for emphasis is displayed so as to be
superimposed on the recognized pedestrian. The sound/image output
section 12052 may also control the display section 12062 so that an
icon or the like representing the pedestrian is displayed at a
desired position.
[0459] An example of a vehicle control system to which the
technology according to the present disclosure can be applied has
been described. The technology according to the present disclosure
can be applied, for example, to the imaging section 12031 and so
forth from among the components described above. In particular, the
solid-state imaging device 111 of the present disclosure can be
applied to the imaging section 12031. By applying the technology
according to the present disclosure to the imaging section 12031,
it is possible to improve the yield and reduce the cost required
for manufacture.
[0460] The technology according to the present disclosure can be
applied to such a solid-state imaging device as described
above.
[0461] It is to be noted that the present disclosure can have such
configurations as described below.
[0462] <1> A backside illumination type solid-state imaging
device including:
[0463] a first semiconductor element including an imaging element
configured to generate a pixel signal in a unit of a pixel;
[0464] a second semiconductor element in which signal processing
circuits necessary for signal processing of the pixel signal are
embedded by an embedding member; and
[0465] a wire that electrically connects the first semiconductor
element and the second semiconductor element; [0466] the first
semiconductor element and the second semiconductor element being
stacked by oxide film joining.
[0467] <2> The backside illumination type solid-state imaging
device according to <1>, in which
[0468] the first semiconductor element is greater than the second
semiconductor element.
[0469] <3> The backside illumination type solid-state imaging
device according to <1>, in which
[0470] the first semiconductor element is smaller than the second
semiconductor element.
[0471] <4> The backside illumination type solid-state imaging
device according to any one of <1> to <3>, in which
[0472] the signal processing circuits include a first signal
processing circuit and a second signal processing circuit, and
[0473] the second semiconductor element has therein the first
signal processing circuit and the second signal processing circuit
arranged in a juxtaposed relation in a horizontal direction and
embedded by the embedding member.
[0474] <5> The backside illumination type solid-state imaging
device according to any one of <1> to <4>, in which
[0475] the signal processing circuits include a first signal
processing circuit and a second signal processing circuit,
[0476] the wire includes a first wire and a second wire,
[0477] the second semiconductor element has therein the first
signal processing circuit embedded by the embedding member,
[0478] the solid-state imaging device includes a third
semiconductor element in which the second signal processing circuit
is embedded by the embedding member,
[0479] the first wire electrically connects the first semiconductor
element and the second semiconductor element to each other,
[0480] the second wire electrically connects the second
semiconductor element and the third semiconductor element to each
other, and
[0481] the second semiconductor element and the third semiconductor
element are stacked by oxide film joining.
[0482] <6> The backside illumination type solid-state imaging
device according to any one of <1> to <5>, in which
[0483] the wire is joined by CuCu joining.
[0484] <7> The backside illumination type solid-state imaging
device according to any one of <1> to <5>, in which
[0485] the wire electrically connects the first semiconductor
element and the second semiconductor element through a
through-via.
[0486] <8> The backside illumination type solid-state imaging
device according to <7>, in which
[0487] the wire electrically connects the first semiconductor
element and the second semiconductor element through a through-via
formed from an imaging face side of the imaging element.
[0488] <9> The backside illumination type solid-state imaging
device according to <7>, in which
[0489] the wire electrically connects the first semiconductor
element and the second semiconductor element through a through-via
formed from a face on an opposite side to an imaging face of the
imaging element.
[0490] <10> The backside illumination type solid-state
imaging device according to any one of <1> to <9>, in
which
[0491] the embedding member includes an oxide film.
[0492] <11> The backside illumination type solid-state
imaging device according to any one of <1> to <9>, in
which
[0493] the embedding member includes an organic material.
[0494] <12> The backside illumination type solid-state
imaging device according to <11>, in which,
[0495] in the second semiconductor element, the signal processing
circuits are laid out such that a gap between the signal processing
circuits is minimized, and the gap is filled with the embedding
member including the organic material.
[0496] <13> The backside illumination type solid-state
imaging device according to any one of <1> to <12>, in
which,
[0497] in the second semiconductor element, in addition to the
signal processing circuits, a dummy circuit configured from a
semiconductor element and including a dummy wire is embedded by the
embedding member.
[0498] <14> The backside illumination type solid-state
imaging device according to any one of <1> to <13>, in
which
[0499] a heat dissipation member that includes a member having a
thermal conductivity higher than a predetermined thermal
conductivity and dissipates heat is stacked on a face of the second
semiconductor element opposite to a face on which the first
semiconductor element is stacked.
[0500] <15> The backside illumination type solid-state
imaging device according to <14>, in which
[0501] the heat dissipation member includes SiC, AlN, SIN, Cu, Al,
and C.
[0502] <16> The backside illumination type solid-state
imaging device according to <14>, in which
[0503] the heat dissipation member includes a waterway for
circulating cooling water.
[0504] <17> The backside illumination type solid-state
imaging device according to any one of <1> to <16>, in
which
[0505] the signal processing circuits include a logic circuit, a
memory circuit, a power supply circuit, an image signal compression
circuit, a clock circuit, and an optical communication conversion
circuit.
[0506] <18> The backside illumination type solid-state
imaging device according to any one of <1> to <17>, in
which
[0507] the signal processing circuits are embedded in the first
semiconductor element by the embedding member.
[0508] <19> The backside illumination type solid-state
imaging device according to <18>, in which
[0509] the signal processing circuits are each embedded by the
embedding member after contacted at part thereof in a positioned
state with the first semiconductor element and gradually joined to
the first semiconductor element beginning with a portion around the
contacted portion.
[0510] <20> The backside illumination type solid-state
imaging device according to <19>, in which
[0511] the part includes an end side and an end point of the signal
processing circuit.
[0512] <21> The backside illumination type solid-state
imaging device according to <19>, in which
[0513] the signal processing circuit is smaller than the first
semiconductor element.
[0514] <22> The backside illumination type solid-state
imaging device according to any one of <1> to <17>, in
which
[0515] the signal processing circuits are each embedded by the
embedding member after contacted at part thereof in a positioned
state with the second semiconductor element and gradually joined to
the second semiconductor element beginning with a portion around
the contacted portion.
[0516] <23> The backside illumination type solid-state
imaging device according to <22>, in which
[0517] the part includes an end side and an end point of the signal
processing circuit.
[0518] <24> A manufacturing method for a backside
illumination type solid-state imaging device that includes
[0519] a first semiconductor element including an imaging element
configured to generate a pixel signal in a unit of a pixel,
[0520] a second semiconductor element in which signal processing
circuits necessary for signal processing of the pixel signal are
embedded by an embedding member, and
[0521] a wire that electrically connects the first semiconductor
element and the second semiconductor element,
[0522] the first semiconductor element and the second semiconductor
element being stacked by oxide film joining, wherein
[0523] a first wafer including the imaging element formed by a
semiconductor process and
[0524] a second wafer in which the signal processing circuit
decided as a good product by electric inspection from among the
signal processing circuits formed by a semiconductor process is
rearranged and embedded by the embedding member
[0525] are stacked by oxide film joining such that the wire between
the first semiconductor element and the second semiconductor
element is electrically connected and then are singulated.
[0526] <25> An imaging apparatus including:
[0527] a backside illumination type solid-state imaging device that
includes [0528] a first semiconductor element including an imaging
element configured to generate a pixel signal in a unit of a pixel,
[0529] a second semiconductor element in which signal processing
circuits necessary for signal processing of the pixel signal are
embedded by an embedding member, and [0530] a wire that
electrically connects the first semiconductor element and the
second semiconductor element, [0531] the first semiconductor
element and the second semiconductor element being stacked by oxide
film joining.
[0532] <26> Electronic equipment including:
[0533] a backside illumination type solid-state imaging device that
includes [0534] a first semiconductor element including an imaging
element configured to generate a pixel signal in a unit of a pixel,
[0535] a second semiconductor element in which signal processing
circuits necessary for signal processing of the pixel signal are
embedded by an embedding member, and [0536] a wire that
electrically connects the first semiconductor element and the
second semiconductor element, [0537] the first semiconductor
element and the second semiconductor element being stacked by oxide
film joining.
REFERENCE SIGNS LIST
[0538] 101 to 104 Wafer, 111 Solid-state imaging device, 120
Solid-state imaging element, 120a Terminal, 121 Memory circuit,
121a, 121a-1, 121a-2 Terminal, 122 Logic circuit, 122a Terminal,
131 On-chip lens and on-chip color filter, 132 Support substrate,
133 Oxide film, 134, 134-1, 134-2, 134A to 134H Wire, 135 Oxide
film joining layer, 151 Rearrangement substrate, 152 Adhesive, 161,
171 Support substrate, 321 First semiconductor substrate, 322
Second semiconductor substrate, 323 Third semiconductor substrate,
331 to 333 Multilayer wiring layer, 351, 352, 361, 362, 372, 381,
382, 391, 401, 402 Contact, 441 Dummy circuit, 441a Dummy wire, 471
High thermal conductivity material member, 491 Waterway, 495
Organic material member
* * * * *