U.S. patent application number 17/474411 was filed with the patent office on 2022-09-22 for semiconductor device.
This patent application is currently assigned to KABUSHIKI KAISHA TOSHIBA. The applicant listed for this patent is KABUSHIKI KAISHA TOSHIBA. Invention is credited to Katsuya SATO, Toshihide TAKAHASHI, Masayuki UCHIDA, Tetsuya YAMAMOTO.
Application Number | 20220302074 17/474411 |
Document ID | / |
Family ID | 1000005901021 |
Filed Date | 2022-09-22 |
United States Patent
Application |
20220302074 |
Kind Code |
A1 |
UCHIDA; Masayuki ; et
al. |
September 22, 2022 |
SEMICONDUCTOR DEVICE
Abstract
A semiconductor device includes: a first chip including a first
electrode; a wiring member; a second chip located between the first
chip and the wiring member, including a second electrode; a first
conductive plate located on the first electrode, in a second
direction a dimension of the first conductive plate being greater
than a dimension of the first chip, the second direction crossing a
first direction being from the first chip toward the second chip; a
second conductive plate located on the second electrode, in a
second direction a dimension of the second conductive plate being
greater than a dimension of the second chip; and a first wire being
bonded to the wiring member, a portion of the first conductive
plate protruding further in the second direction than the first
chip, and a portion of the second conductive plate protruding
further in the second direction than the second chip.
Inventors: |
UCHIDA; Masayuki; (Yokohama,
JP) ; YAMAMOTO; Tetsuya; (Sagamihara, JP) ;
TAKAHASHI; Toshihide; (Yokohama, JP) ; SATO;
Katsuya; (Yokohama, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
KABUSHIKI KAISHA TOSHIBA |
Tokyo |
|
JP |
|
|
Assignee: |
KABUSHIKI KAISHA TOSHIBA
Tokyo
JP
|
Family ID: |
1000005901021 |
Appl. No.: |
17/474411 |
Filed: |
September 14, 2021 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 24/73 20130101;
H01L 2224/73265 20130101; H01L 2224/484 20130101; H01L 24/48
20130101; H01L 24/32 20130101; H01L 2924/13091 20130101; H01L 24/05
20130101; H01L 2224/48091 20130101; H01L 25/072 20130101; H01L
2224/05082 20130101; H01L 24/85 20130101; H01L 25/18 20130101 |
International
Class: |
H01L 23/00 20060101
H01L023/00; H01L 25/07 20060101 H01L025/07; H01L 25/18 20060101
H01L025/18 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 17, 2021 |
JP |
2021-043742 |
Claims
1. A semiconductor device, comprising: a first chip including a
first electrode; a wiring member separated from the first chip; a
second chip located between the first chip and the wiring member,
the second chip including a second electrode; a first conductive
plate located on the first electrode and electrically connected to
the first electrode, a maximum dimension in a second direction of
the first conductive plate being greater than a maximum dimension
in the second direction of the first chip, the second direction
crossing a first direction, the first direction being from the
first chip toward the second chip; a second conductive plate
located on the second electrode and electrically connected to the
second electrode, a maximum dimension in the second direction of
the second conductive plate being greater than a maximum dimension
in the second direction of the second chip; and a first wire, the
first wire being bonded to the wiring member, a portion of the
first conductive plate protruding further in the second direction
than the first chip, and a portion of the second conductive plate
protruding further in the second direction than the second
chip.
2. The device according to claim 1, further comprising: a second
wire, the first chip further including a third electrode located at
a surface at which the first electrode is located, the first
conductive plate not covering the third electrode, the second chip
further including a fourth electrode located at a surface at which
the second electrode is located, the second conductive plate not
covering the fourth electrode, the second wire being bonded to the
third electrode, extending from the third electrode toward the
fourth electrode, and being bonded to the fourth electrode.
3. The device according to claim 2, wherein the first chip and the
second chip each are MOSFETs, the first electrode is a source
electrode of the first chip, the third electrode is a gate
electrode of the first chip, the second electrode is a source
electrode of the second chip, and the fourth electrode is a gate
electrode of the second chip.
4. The device according to claim 1, further comprising: a third
wire, the third wire being bonded to the wiring member, a portion
of the first conductive plate positioned directly above the first
chip, and a portion of the second conductive plate positioned
directly above the second chip.
5. The device according to claim 1, wherein a maximum dimension in
the first direction of the first conductive plate is less than a
maximum dimension in the first direction of the first chip, and a
maximum dimension in the first direction of the second conductive
plate is less than a maximum dimension in the first direction of
the second chip.
6. The device according to claim 1, further comprising: a first
metal layer located on the first electrode, the first metal layer
including gold; a second metal layer located on the second
electrode, the second metal layer including gold; a first bonding
member positioned between the first metal layer and the first
conductive plate, the first bonding member being conductive and
bonding the first metal layer and the first conductive plate; and a
second bonding member positioned between the second metal layer and
the first conductive plate, the second bonding member being
conductive and bonding the second metal layer and the second
conductive plate, the first electrode and the second electrode each
including aluminum.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No.
2021-043742, filed on Mar. 17, 2021; the entire contents of which
are incorporated herein by reference.
FIELD
[0002] Embodiments relate to a semiconductor device.
BACKGROUND
[0003] A conventional semiconductor device is known in which
multiple chips are electrically connected by bonding wires.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 is a top view showing a semiconductor device
according to an embodiment;
[0005] FIG. 2 is an enlarged top view of a region surrounded with
broken line A of FIG. 1;
[0006] FIG. 3 is a cross-sectional view along line B-B' of FIG.
2;
[0007] FIG. 4 is an enlarged top view of the region surrounded with
broken line A of FIG. 1 in which the conductive plates and the
wires of FIG. 1 are not illustrated;
[0008] FIG. 5 is an enlarged top view of the region surrounded with
broken line A of FIG. 1 in which the wires of FIG. 1 are not
illustrated; and
[0009] FIG. 6 is an enlarged top view of a portion of a
semiconductor device of a reference example.
DETAILED DESCRIPTION
[0010] In general, according to one embodiment, a semiconductor
device, includes: a first chip including a first electrode; a
wiring member separated from the first chip; a second chip located
between the first chip and the wiring member, the second chip
including a second electrode; a first conductive plate located on
the first electrode and electrically connected to the first
electrode, a maximum dimension in a second direction of the first
conductive plate being greater than a maximum dimension in the
second direction of the first chip, the second direction crossing a
first direction, the first direction being from the first chip
toward the second chip; a second conductive plate located on the
second electrode and electrically connected to the second
electrode, a maximum dimension in the second direction of the
second conductive plate being greater than a maximum dimension in
the second direction of the second chip; and a first wire, the
first wire being bonded to the wiring member, a portion of the
first conductive plate protruding further in the second direction
than the first chip, and a portion of the second conductive plate
protruding further in the second direction than the second
chip.
[0011] Various embodiments will be described hereinafter with
reference to the accompanying drawings.
[0012] FIG. 1 is a top view showing a semiconductor device
according to an embodiment.
[0013] FIG. 2 is an enlarged top view of a region surrounded with
broken line A of FIG. 1.
[0014] FIG. 3 is a cross-sectional view along line B-B' of FIG.
2.
[0015] The semiconductor device 100 according to the embodiment is
a power semiconductor device. For example, the semiconductor device
100 is mounted in a vehicle such as an automobile, a train, etc.,
and is used in the switching control of a motor mounted in the
vehicle. It is desirable for such a semiconductor device 100 to
output a large current. However, the application objects of the
semiconductor device are not particularly limited to those
described above.
[0016] As shown in FIG. 1, the semiconductor device 100 includes a
substrate 110, a drain connection leadframe 121 that is located on
the substrate 110, multiple gate connection leadframes 122 that are
located on the substrate 110, and multiple source connection
leadframes 123 (wiring members) that are located on the substrate
110. As shown in FIGS. 2 and 3, the semiconductor device 100
further includes multiple chips 130 that are located on the drain
connection leadframe 121, multiple conductive plates 140 that are
located respectively on the multiple chips 130, and multiple wires
151, 152, 153, and 154.
[0017] The components of the semiconductor device 100 will now be
elaborated. An XYZ orthogonal coordinate system is used for easier
understanding of the following description. The direction from the
substrate 110 toward the chip 130 is taken as a "Z-direction".
Although the Z-direction is taken as the "upward direction" and the
opposite direction of the Z-direction is taken as the "downward
direction", these directions are independent of the direction of
gravity. A direction orthogonal to the Z-direction is taken as an
"X-direction". A direction orthogonal to the Z-direction and the
X-direction is taken as a "Y-direction".
[0018] For example, the substrate 110 is made of an insulating
material. The substrate 110 is flat-plate shaped. When viewed in
top-view, the substrate 110 has a rectangular shape of which the
X-direction is the longitudinal direction and the corners are
rounded. However, the shape of the substrate 110 is not limited to
that described above. As shown in FIG. 3, the surfaces of the
substrate 110 include an upper surface 110a and a lower surface
110b that are substantially parallel to the X-direction and the
Y-direction.
[0019] The drain connection leadframe 121, the gate connection
leadframe 122, and the source connection leadframe 123 are located
at the upper surface 110a of the substrate 110. A heat dissipation
member such as a metal plate, etc., may be located under the
substrate 110.
[0020] The leadframes 121, 122, and 123 are made of a metal
material such as copper (Cu), etc. The leadframes 121, 122, and 123
are flat-plate shaped.
[0021] As shown in FIG. 1, the drain connection leadframe 121
includes multiple support portions 121a and multiple connection
portions 121b.
[0022] According to the embodiment, ten chips 130 are located on
each support portion 121a. The ten chips 130 on each support
portion 121a are located in a matrix of two columns in the
X-direction and five rows in the Y-direction. However, the number
of chips located on each support portion is not limited to the
number described above as long as the number is not less than 2.
Also, the arrangement of the chips on each support portion is not
limited to that described above.
[0023] According to the embodiment, the number of the support
portions 121a included in the semiconductor device 100 is 8. The
eight support portions 121a are arranged to have two support
portions 121a next to each other in the Y-direction and four
support portions 121a arranged in the X-direction.
[0024] According to the embodiment, the number of the connection
portions 121b included in the semiconductor device 100 is 4. One of
the four connection portions 121b connects the support portion 121a
positioned furthest at the -X side and furthest at the +Y side and
the support portion 121a positioned furthest at the +X side and
furthest at the +Y side. Another one of the four connection
portions 121b connects the support portion 121a positioned furthest
at the -X side and furthest at the -Y side and the support portion
121a positioned furthest at the +X side and furthest at the -Y
side. Another one of the four connection portions 121b connects the
support portion 121a positioned furthest at the -X side and
furthest at the +Y side and the support portion 121a positioned
furthest at the -X side and furthest at the -Y side. Another one of
the four connection portions 121b connects the support portion 121a
positioned furthest at the +X side and furthest at the +Y side and
the support portion 121a positioned furthest at the +X side and
furthest at the -Y side. However, the number and location of the
support portions are not limited to those described above.
[0025] According to the embodiment, the semiconductor device 100
includes eight gate connection leadframes 122 that correspond to
the eight support portions 121a of the drain connection leadframe
121. Each gate connection leadframe 122 is located next to the
corresponding support portion 121a in the X-direction.
Specifically, each gate connection leadframe 122 is located inward
of the corresponding support portion 121a in the X-direction. Each
gate connection leadframe 122 extends in the Y-direction. However,
the shapes and positions of the gate connection leadframes are not
limited to those described above.
[0026] Similarly, according to the embodiment, the semiconductor
device 100 includes eight source connection leadframes 123 that
correspond to the eight support portions 121a of the drain
connection leadframes 121. Each source connection leadframe 123 is
located so that the gate connection leadframe 122 is sandwiched
between the source connection leadframe 123 and the corresponding
support portion 121a. Specifically, each source connection
leadframe 123 is located inward of the corresponding drain
connection leadframe 121 and the corresponding gate connection
leadframe 122 in the X-direction.
[0027] The source connection leadframe 123 that is positioned
furthest at the -X side and furthest at the +Y side is linked to
the support portion 121a positioned at the +X side of the source
connection leadframe 123. The source connection leadframe 123 that
is positioned furthest at the +X side and furthest at the +Y side
is linked to the support portion 121a positioned at the -X side of
the source connection leadframe 123. The source connection
leadframe 123 that is positioned furthest at the -X side and
furthest at the -Y side is linked to the support portion 121a
positioned at the +X side of the source connection leadframe 123.
The source connection leadframe 123 positioned furthest at the +X
side and furthest at the -Y side is linked to the support portion
121a positioned at the -X side of the source connection leadframe
123. The other source connection leadframes 123 extend in the
Y-direction and are not linked to the support portions 121a.
However, the shapes and positions of the source connection
leadframes are not limited to those described above.
[0028] The gate connection leadframe 122 is separated from the
drain connection leadframe 121 and the source connection leadframe
123.
[0029] FIG. 4 is an enlarged top view of the region surrounded with
broken line A of FIG. 1 in which the conductive plates and the
wires of FIG. 1 are not illustrated.
[0030] According to the embodiment, the chips 130 are MOSFETs
(metal-oxide-semiconductor field-effect transistors). The chips 130
are substantially flat-plate shaped. When viewed in top-view, the
chips 130 are rectangular. However, the shapes of the chips are not
limited to those described above.
[0031] As shown in FIG. 3, the surface of each chip 130 includes a
lower surface 130a that faces the drain connection leadframe 121,
and an upper surface 130b that is positioned at the side opposite
to the lower surface 130a. A drain electrode 131 is located at the
lower surface 130a. The drain electrode 131 is electrically
connected to the drain connection leadframe 121. As shown in FIG.
4, a gate electrode 132 and a source electrode 133 are located at
the upper surface 130b.
[0032] According to the embodiment, the drain electrode 131, the
gate electrode 132, and the source electrode 133 each include
aluminum (Al) as a major material. The drain electrode, the gate
electrode 132, and the source electrode 133 each are made of
aluminum (Al) having a purity that is not less than 95% and not
more than 100%. However, the materials included in the drain
electrode, the gate electrode, and the source electrode are not
limited to those described above as long as a conductive material
such as a metal or the like is used.
[0033] When viewed in top-view, the gate electrode 132 is
substantially rectangular. The gate electrode 132 is located at the
X-direction end portion of the upper surface 130b at the
Y-direction central portion. However, the shape and position of the
gate electrode are not limited to those described above.
[0034] When viewed in top-view, the source electrode 133 includes a
substantially rectangular first region 133a, and a pair of second
regions 133b that is separated from each other in the Y-direction
and protrudes in the X-direction from the first region 133a. The
gate electrode 132 is located between the pair of second regions
133b. The gate electrode 132 and the source electrode 133 are
electrically insulated from each other in each chip 130.
[0035] FIG. 5 is an enlarged top view of the region surrounded with
broken line A of FIG. 1 in which the wires of FIG. 1 are not
illustrated.
[0036] The conductive plate 140 is located on the source electrode
133 of each chip 130. For example, the conductive plate 140 is made
of a metal material such as copper (Cu), etc. The conductive plate
140 is substantially flat-plate shaped.
[0037] The conductive plate 140 does not cover the gate electrode
132 and is electrically insulated from the gate electrode 132.
Specifically, a recess 141 that is concave in the X-direction is
formed in the side surface of the conductive plate 140 so that the
gate electrode 132 is exposed. However, the shape of the conductive
plate is not limited to that described above. For example, when
viewed in top-view, the conductive plate may be rectangular, and
the conductive plate may be separated from the gate electrode in
the X-direction.
[0038] A maximum dimension L1 in the Y-direction of the conductive
plate 140 is greater than a maximum dimension L2 in the Y-direction
of the chip 130. Therefore, the two Y-direction end portions of the
conductive plate 140 protrude from the chip 130. However, one
Y-direction end portion of the conductive plate may protrude from
the chip; and the other Y-direction end portion may not protrude
from the chip. A maximum dimension L3 in the X-direction of the
conductive plate 140 is less than a maximum dimension L4 in the
X-direction of the chip 130. However, the size relationship between
the maximum dimension in the X-direction of the conductive plate
and the maximum dimension in the X-direction of the chip is not
limited to that described above.
[0039] As shown in FIG. 3, the conductive plate 140 is electrically
connected to the source electrode 133 of the chip 130 via a metal
layer 160 and a bonding member 170. Specifically, the metal layer
160 that includes gold (Au) is located on the source electrode 133.
The metal layer 160 and the conductive plate 140 are bonded by the
bonding member 170 that is made from solder, a sintering material,
etc. As described above, because the source electrode 133 includes
aluminum (Al) as a major material, it is difficult to bond the
conductive plate 140 directly to the source electrode 133 by
solder, a sintering material, etc. Conversely, according to the
embodiment, by covering the source electrode 133 with the metal
layer 160 that includes gold (Au), the conductive plate 140 can be
bonded to the source electrode 133 via the metal layer 160.
However, the connection structure between the conductive plate and
the source electrode is not limited to that described above.
[0040] As shown in FIG. 2, the chips 130 that are next to each
other in the X-direction are connected in parallel. Hereinbelow,
the chip 130 that is distant to the source connection leadframe 123
among the chips 130 next to each other in the X-direction is called
a "first chip 130A". The chip 130 that is proximate to the source
connection leadframe 123 among the chips 130 next to each other in
the X-direction is called a "second chip 130B". In other words, the
second chip 130B is the chip 130 that is positioned between the
source connection leadframe 123 and the first chip 130A. The
conductive plate 140 that is on the first chip 130A is called a
"first conductive plate 140A"; and the conductive plate 140 that is
on the second chip 130B is called a "second conductive plate
140B".
[0041] The gate electrodes 132 of the first and second chips 130A
and 130B are electrically connected via the gate connection
leadframe 122 and the wire 151 (a second wire). Specifically, one
end portion of the wire 151 is bonded to the gate electrode 132 of
the first chip 130A by wire bonding. The other end portion of the
wire 151 is bonded to the gate connection leadframe 122 by wire
bonding. The middle portion of the wire 151 is bonded to the gate
electrode 132 of the second chip 130B by wire bonding. The bonding
portions between the chips 130 and the wires 151 to 154 are shown
as black filled circles for easier understanding of the description
in FIG. 2.
[0042] The source electrodes 133 of the first and second chips 130A
and 130B are electrically connected to the source connection
leadframe 123 via two wires 152 (first wires). Specifically, one
end portion of each wire 152 is bonded by wire bonding to the
portion of the first conductive plate 140A protruding in the
Y-direction from the first chip 130A. The other end portion of each
wire 152 is bonded by wire bonding to the source connection
leadframe 123. The middle portion of each wire 152 is bonded by
wire bonding to the portion of the second conductive plate 140B
protruding in the Y-direction from the second chip 130B.
[0043] One of the two wires 152 is connected to one Y-direction end
portion of the first conductive plate 140A and one Y-direction end
portion of the second conductive plate 140B. The other of the two
wires 152 is connected to the other Y-direction end portion of the
first conductive plate 140A and the other Y-direction end portion
of the second conductive plate 140B.
[0044] The source electrodes 133 of the first and second chips 130A
and 130B also are electrically connected to the source connection
leadframe 123 via the two wires 153 (third wires). Specifically,
one end portion of the wires 153 is bonded by wire bonding to the
portion of the first conductive plate 140A positioned directly
above the first chip 130A. The other end portion of each wire 153
is bonded by wire bonding to the source connection leadframe 123.
The middle portion of each wire 153 is bonded by wire bonding to
the portion of the second conductive plate 140B positioned directly
above the second chip 130B.
[0045] The source electrode 133 of the second chip 130B is
electrically connected to the source connection leadframe 123 via
the two wires 154. Specifically, one end portion of each wire 154
is bonded by wire bonding to the portion of the second conductive
plate 140B positioned directly above the second chip 130B. The
other end portion of each wire 154 is bonded by wire bonding to the
source connection leadframe 123.
[0046] The wire 151 is sandwiched between the two wires 154 in the
Y-direction when viewed in top-view. The wires 151 and 154 are
sandwiched between the two wires 153 in the Y-direction when viewed
in top-view.
[0047] The positions in the X-direction of the bonding portions of
the wires 152, 153, and 154 to the first chip 130A are different
from each other. Similarly, the positions in the X-direction of the
bonding portions of the wires 152, 153, and 154 to the second chip
130B are different from each other. However, the positions of the
bonding portions of the wires 152, 153, and 154 to the first chip
130A may be the same; and the positions in the X-direction of the
bonding portions of the wires 152, 153, and 154 to the second chip
130B may be the same. Although states in which the wire 153 and the
wire 154 do not overlap when viewed in top-view are shown in FIGS.
1 and 2, the wire 153 and the wire 154 may partially overlap when
viewed in top-view.
[0048] Thus, the chips 130 that are next to each other in the
X-direction are connected in parallel by the multiple wires 152 and
153. The current amount that can be output by the semiconductor
device 100 can be increased thereby. The number of wires used in
the electrical connection between the source connection leadframe
123 and the chips 130 next to each other in the X-direction is not
limited to 6. The wires may connect the source connection leadframe
and three or more chips in parallel. Two or more wires may be
bonded to the portion of each conductive plate that protrudes from
the chip.
[0049] FIG. 6 is an enlarged top view showing a portion of a
semiconductor device of a reference example. The semiconductor
device 100A of the reference example differs from the semiconductor
device 100 according to the embodiment in that the conductive plate
140 is not included. When the conductive plate 140 is not included,
the number of wires that can be bonded to the source electrode 133
of the chip 130 is dependent on the surface area of the source
electrode 133.
[0050] In particular, there are cases where the number of wires
that can be bonded to the source electrode 133 of the second chip
130B is less than the number of wires that can be bonded to the
source electrode 133 of the first chip 130A. Specifically, even
when one end portion of a wire 152A can be bonded to the source
electrode 133 of the first chip 130A on the same straight line
extending in the X-direction as the wire 153, there are cases where
there is no location to bond the middle portion of the wire 152A to
the source electrode 133 of the second chip 130B because the wires
153 and 154 are bonded. In such a case, the wire 152A is bonded to
the source electrode 133 of the first chip 130A and the source
connection leadframe 123 and is not bonded to the source electrode
133 of the second chip 130B.
[0051] Therefore, in a configuration such as that of the
semiconductor device 100A of the reference example, the length
between the bonding portions of the wire 152A is greater than the
length between the bonding portions of the wire 152 according to
the embodiment. The deformation amount due to a temperature change
increases as the length between the bonding portions of the wire
152A increases. As the deformation amount increases, the bonding
portion breaks easily because the stress acting on the bonding
portion of the wire 152A increases.
[0052] Conversely, in the semiconductor device 100 according to the
embodiment as shown in FIG. 2, the conductive plate 140 is located
on each chip 130. The middle portion of the wire 152 is bonded to
the conductive plate 140 on the source electrode 133 of the chip
130 proximate to the source connection leadframe 123. Therefore,
the increase of the length between the bonding portions of the wire
152 can be suppressed. The breakage of the bonding portion of the
wire 152 can be suppressed thereby. As a result, a highly-reliable
semiconductor device 100 can be provided.
[0053] Effects of the embodiment will now be described.
[0054] In the semiconductor device 100 according to the embodiment,
the first conductive plate 140A is located on the first chip 130A;
and the second conductive plate 140B is located on the second chip
130B. The maximum dimension L1 of the first conductive plate 140A
in the second direction (the Y-direction) crossing the first
direction (the X-direction) that is from the first chip 130A toward
the second chip 130B is greater than the maximum dimension L2 in
the Y-direction of the first chip 130A. Similarly, the maximum
dimension L1 in the Y-direction of the second conductive plate 140B
is greater than the maximum dimension L2 in the Y-direction of the
second chip. The wire 152 is bonded to the source connection
leadframe 123, the portion of the first conductive plate 140A
protruding further in the Y-direction than the first chip 130A, and
the portion of the second conductive plate 140B protruding further
in the Y-direction than the second chip 130B. Therefore, the
increase of the length of the wire 152 can be suppressed. The
increase of the deformation amount due to the temperature change of
the wire 152 can be suppressed thereby. As a result, the breakage
of the bonding portion of the wire 152 due to the temperature
change can be suppressed. Thus, a highly-reliable semiconductor
device 100 can be provided.
[0055] The conductive plates 140 do not cover the gate electrodes
132 of the chips 130. Therefore, the gate electrode 132 of the
first chip 130A and the gate electrode 132 of the second chip 130B
can be electrically connected by the wire 151.
[0056] The semiconductor device 100 further includes a wire 153
that is bonded to the source connection leadframe 123, the portion
of the first conductive plate 140A positioned directly above the
first chip 130A, and the portion of the second conductive plate
140B positioned directly above the second chip 130B. Therefore, the
current amount that can be output by the semiconductor device 100
can be increased.
[0057] The maximum dimension L3 in the X-direction of the first
conductive plate 140A is less than the maximum dimension L4 in the
X-direction of the first chip 130A; and the maximum dimension L3 in
the X-direction of the second conductive plate 140B is less than
the maximum dimension L4 in the X-direction of the second chip
130B. Therefore, the first conductive plate 140A and the second
conductive plate 140B can be prevented from being proximate.
[0058] The source electrode 133 includes aluminum (Al); and the
metal layer 160 that includes gold (Au) is located on the source
electrode 133. Therefore, the source electrode 133 and the
conductive plate 140 can be bonded by the bonding member 170 such
as solder, a sintering material, etc.
[0059] An example is described in embodiments described above in
which the wiring member is a leadframe. However, it is sufficient
for the wiring member to be a member that is electrically connected
to the first electrode of the first chip and the second electrode
of the second chip and is included in the wiring of the
semiconductor device. Accordingly, the wiring member may be, for
example, a terminal or a wiring layer provided in a substrate.
[0060] While certain embodiments have been described, these
embodiments have been presented by way of example only, and are not
intended to limit the scope of the inventions. Indeed, the novel
embodiments described herein may be embodied in a variety of other
forms; furthermore, various omissions, substitutions, and changes
in the form of the embodiments described herein may be made without
departing from the spirit of the inventions. The accompanying
claims and their equivalents are intended to cover such forms or
modifications as would fall within the scope and spirit of the
inventions. Additionally, the embodiments described above can be
combined mutually.
* * * * *