U.S. patent application number 17/833643 was filed with the patent office on 2022-09-22 for systems, methods, and apparatuses for zeroing a matrix.
The applicant listed for this patent is Intel Corporation. Invention is credited to Menachem ADELMAN, Mark J. CHARNEY, Jesus CORBAL, Alexander F. HEINECKE, Elmoustapha OULD-AHMED-VALL, Stanislav SHWARTSMAN, Zeev SPERBER, Bret L. TOLL, Robert VALENTINE, Barukh ZIV.
Application Number | 20220300286 17/833643 |
Document ID | / |
Family ID | 1000006381604 |
Filed Date | 2022-09-22 |
United States Patent
Application |
20220300286 |
Kind Code |
A1 |
VALENTINE; Robert ; et
al. |
September 22, 2022 |
SYSTEMS, METHODS, AND APPARATUSES FOR ZEROING A MATRIX
Abstract
Embodiments detailed herein relate to matrix operations. In
particular, performing a matrix operation of zeroing a matrix in
response to a single instruction. For example, a processor detailed
which includes decode circuitry to decode an instruction having
fields for an opcode and a source/destination matrix operand
identifier; and execution circuitry to execute the decoded
instruction to zero each data element of the identified
source/destination matrix.
Inventors: |
VALENTINE; Robert; (Kiryat
Tivon, IL) ; ADELMAN; Menachem; (Haifa, IL) ;
SPERBER; Zeev; (Zichron Yackov, IL) ; CHARNEY; Mark
J.; (Lexington, MA) ; TOLL; Bret L.;
(Hillsboro, OR) ; CORBAL; Jesus; (King City,
OR) ; HEINECKE; Alexander F.; (San Jose, CA) ;
ZIV; Barukh; (Haifa, IL) ; OULD-AHMED-VALL;
Elmoustapha; (Chandler, AZ) ; SHWARTSMAN;
Stanislav; (Haifa, IL) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Intel Corporation |
Santa Clara |
CA |
US |
|
|
Family ID: |
1000006381604 |
Appl. No.: |
17/833643 |
Filed: |
June 6, 2022 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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16487784 |
Aug 21, 2019 |
11360770 |
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PCT/US2017/040538 |
Jul 1, 2017 |
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17833643 |
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62473732 |
Mar 20, 2017 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F 9/3818 20130101;
G06F 9/30196 20130101; G06F 9/30112 20130101; G06F 7/4876 20130101;
G06F 9/30109 20130101; G06F 2212/454 20130101; G06F 9/3016
20130101; G06F 9/30036 20130101; G06F 9/30043 20130101; G06F 7/762
20130101; G06F 9/3836 20130101; G06F 9/3001 20130101; G06F 9/30145
20130101; G06F 9/30134 20130101; G06F 7/485 20130101; G06F 9/30185
20130101; G06F 9/30149 20130101; G06F 17/16 20130101; G06F 9/30032
20130101 |
International
Class: |
G06F 9/30 20060101
G06F009/30; G06F 7/485 20060101 G06F007/485; G06F 7/487 20060101
G06F007/487; G06F 17/16 20060101 G06F017/16; G06F 7/76 20060101
G06F007/76; G06F 9/38 20060101 G06F009/38 |
Claims
1. A processor comprising: decode circuitry to decode an
instruction having fields for an opcode and a source/destination
matrix operand identifier; and execution circuitry to execute the
decoded instruction to zero each data element of the identified
source/destination matrix.
2. The processor of claim 1, wherein the execution circuitry is to
zero each row of the source/destination matrix operand.
3. The processor of claim 1, wherein the source/destination matrix
operand is a plurality of registers configured to represent a
matrix.
4. The processor of claim 1, wherein the execution circuitry to
fault upon a determination the source/destination matrix operand
identifier is not configured as a matrix.
5. The processor of claim 1, wherein the execution circuitry is to
set a status bit regarding the identified source/destination matrix
as being zero.
6. A method comprising: decoding an instruction having fields for
an opcode and a source/destination matrix operand identifier; and
executing the decoded instruction to zero each data element of the
identified source/destination matrix.
7. The method of claim 6, wherein the zeroing is done a row of the
source/destination matrix operand at a time.
8. The method of claim 6, wherein the source/destination matrix
operand is a plurality of registers configured to represent a
matrix.
9. The method of claim 6, further comprising: faulting upon a
determination the source/destination matrix operand identifier is
not configured as a matrix.
10. The method of claim 6, further comprising: setting a status bit
regarding the identified source/destination matrix as being
zero.
11. A non-transitory machine-readable medium storing an instruction
which causes a processor to perform a method, the method
comprising: decoding the instruction having fields for an opcode
and a source/destination matrix operand identifier; and executing
the decoded instruction to zero each data element of the identified
source/destination matrix.
12. The non-transitory machine-readable medium of claim 11, wherein
the zeroing is done a row of the source/destination matrix operand
at a time.
13. The non-transitory machine-readable medium of claim 11, wherein
the source/destination matrix operand is a plurality of registers
configured to represent a matrix.
14. The non-transitory machine-readable medium of claim 11, further
comprising: faulting upon a determination the source/destination
matrix operand identifier is not configured as a matrix.
15. The non-transitory machine-readable medium of claim 11, further
comprising: setting a status bit regarding the identified
source/destination matrix as being zero.
16. A system comprising: a processor; and an accelerator coupled to
the processor, the accelerator including: decode circuitry to
decode an instruction having fields for an opcode and a
source/destination matrix operand identifier; and execution
circuitry to execute the decoded instruction to zero each data
element of the identified source/destination matrix.
17. The system of claim 16, wherein the execution circuitry is to
zero each row of the source/destination matrix operand.
18. The system of claim 16, wherein the source/destination matrix
operand is a plurality of registers configured to represent a
matrix.
19. The system of claim 16, wherein the execution circuitry to
fault upon a determination the source/destination matrix operand
identifier is not configured as a matrix.
20. The system of claim 16, wherein the execution circuitry is to
set a status bit regarding the identified source/destination matrix
as being zero.
Description
FIELD OF INVENTION
[0001] The field of invention relates generally to computer
processor architecture, and, more specifically, to matrix
manipulation.
BACKGROUND
[0002] Matrices are increasingly important in many computing tasks
such as machine learning and other bulk data processing.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] The present invention is illustrated by way of example and
not limitation in the FIGS. of the accompanying drawings, in which
like references indicate similar elements and in which:
[0004] FIG. 1 illustrates an embodiment of configured tiles;
[0005] FIG. 2 illustrates several examples of matrix storage;
[0006] FIG. 3 illustrates an embodiment of a system utilizing a
matrix (tile) operations accelerator;
[0007] FIGS. 4 and 5 show different embodiments of how memory is
shared using a matrix operations accelerator;
[0008] FIG. 6 illustrates an embodiment of matrix multiply
accumulate operation using tiles ("TMMA");
[0009] FIG. 7 illustrates an embodiment of a subset of the
execution of an iteration of a chained fused multiply accumulate
instruction;
[0010] FIG. 8 illustrates an embodiment of a subset of the
execution of an iteration of a chained fused multiply accumulate
instruction;
[0011] FIG. 9 illustrates an embodiment of a subset of the
execution of an iteration of a chained fused multiply accumulate
instruction;
[0012] FIG. 10 illustrates an embodiment of a subset of the
execution of an iteration of chained fused multiply accumulate
instruction;
[0013] FIG. 11 illustrates power-of-two sized SIMD implementations
wherein the accumulators use input sizes that are larger than the
inputs to the multipliers according to an embodiment;
[0014] FIG. 12 illustrates an embodiment of a system utilizing
matrix operations circuitry;
[0015] FIG. 13 illustrates an embodiment of a processor core
pipeline supporting matrix operations using tiles;
[0016] FIG. 14 illustrates an embodiment of a processor core
pipeline supporting matrix operations using tiles;
[0017] FIG. 15 illustrates an example of a matrix expressed in row
major format and column major format;
[0018] FIG. 16 illustrates an example of usage of matrices
(tiles);
[0019] FIG. 17 illustrates an embodiment a method of usage of
matrices (tiles);
[0020] FIG. 18 illustrates an exemplary execution of a TILECONFIG
instruction;
[0021] FIGS. 19(A)-(D) illustrate examples of register(s);
[0022] FIG. 20 illustrates an embodiment of a description of the
matrices (tiles) to be supported;
[0023] FIG. 21 illustrates an embodiment of method performed by a
processor to process a TILECONFIG instruction;
[0024] FIG. 22 illustrates a more detailed description of an
execution of a TILECONFIG instruction using memory addressing;
[0025] FIG. 23 illustrates exemplary pseudocode for an execution of
a TILECONFIG instruction;
[0026] FIG. 24 illustrates an exemplary execution of a TILEZERO
instruction;
[0027] FIG. 25 illustrates an embodiment of method performed by a
processor to process a TILEZERO instruction;
[0028] FIG. 26 depicts pseudocode of a method of execution of a
TILEZERO instruction;
[0029] FIGS. 27(A)-(C) illustrate an exemplary instruction
format;
[0030] FIG. 28 is a block diagram of a register architecture
according to one embodiment of the invention;
[0031] FIGS. 29A-B illustrate the in-order pipeline and in-order
core;
[0032] FIGS. 30A-B illustrate a block diagram of a more specific
exemplary in-order core architecture, which core would be one of
several logic blocks (including other cores of the same type and/or
different types) in a chip;
[0033] FIG. 31 is a block diagram of a processor 3100 that may have
more than one core, may have an integrated memory controller, and
may have integrated graphics according to embodiments of the
invention;
[0034] FIGS. 32-35 are block diagrams of exemplary computer
architectures; and
[0035] FIG. 36 is a block diagram contrasting the use of a software
instruction converter to convert binary instructions in a source
instruction set to binary instructions in a target instruction set
according to embodiments of the invention.
DETAILED DESCRIPTION
[0036] In the following description, numerous specific details are
set forth. However, it is understood that embodiments of the
invention may be practiced without these specific details. In other
instances, well-known circuits, structures and techniques have not
been shown in detail in order not to obscure the understanding of
this description.
[0037] References in the specification to "one embodiment," "an
embodiment," "an example embodiment," etc., indicate that the
embodiment described may include a particular feature, structure,
or characteristic, but every embodiment may not necessarily include
the particular feature, structure, or characteristic. Moreover,
such phrases are not necessarily referring to the same embodiment.
Further, when a particular feature, structure, or characteristic is
described in connection with an embodiment, it is submitted that it
is within the knowledge of one skilled in the art to affect such
feature, structure, or characteristic in connection with other
embodiments whether or not explicitly described.
[0038] In many mainstream processors, handling matrices is a
difficult and/or instruction intensive task. For example, rows of a
matrix could be put into a plurality of packed data (e.g., SIMD or
vector) registers and then operated on individually. For example,
an add two 8.times.2 matrices may require a load or gather into
four packed data registers depending upon data sizes. Then a first
add of packed data registers corresponding to a first row from each
matrix is performed and a second add of packed data registers
corresponding to a second row from each matrix is performed. Then
the resulting packed data registers are scattered back to memory.
While for small matrices this scenario may be acceptable, it is
often not acceptable with larger matrices.
[0039] I. High-Level Discussion
[0040] Described herein are mechanisms to support matrix operations
in computer hardware such as central processing units (CPUs),
graphic processing units (GPUs), and accelerators. The matrix
operations utilize 2-dimensional (2-D) data structures representing
one or more packed regions of memory such as registers. Throughout
this description, these 2-D data structures are referred to as
tiles. Note that a matrix may be smaller than a tile (use less than
all of a tile), or utilize a plurality of tiles (the matrix is
larger than the size of any one tile). Throughout the description,
matrix (tile) language is used to indicate operations performed
using tiles that impact a matrix; whether or not that matrix is
larger than any one tile is not typically relevant.
[0041] Each tile may be acted upon by different operations such as
those that are detailed herein and include, but are not limited to:
matrix (tile) multiplication, tile add, tile subtract, tile
diagonal, tile zero, tile transpose, tile dot product, tile
broadcast, tile row broadcast, tile column broadcast, tile
multiplication, tile multiplication and accumulation, tile move,
etc. Additionally, support for operators such as the use of a scale
and/or bias may be used with these operations or in support of
non-numeric applications in the future, for instance, OpenCL "local
memory," data compression/decompression, etc.
[0042] Portions of storage (such as memory (non-volatile and
volatile), registers, cache, etc.) are arranged into tiles of
different horizontal and vertical dimensions. For example, a tile
may have horizontal dimension of 4 (e.g., four rows of a matrix)
and a vertical dimension of 8 (e.g., 8 columns of the matrix).
Typically, the horizontal dimension is related to element sizes
(e.g., 2-, 4-, 8-, 16-, 32-, 64-, 128-bit, etc.). Multiple
datatypes (single precision floating point, double precision
floating point, integer, etc.) may be supported.
[0043] A. Exemplary usage of configured tiles
[0044] FIG. 1 illustrates an embodiment of configured tiles. As
shown, there are four tiles 111, 113, 115, and 117 that are loaded
from application memory 101. In this example, tiles T0 111 and T1
113 have M rows and N columns with 4 element bytes (e.g., single
precision data). Tiles T2 115 and T3 117 have M rows and N/2
columns with 8 element bytes (e.g., double precision data). As the
double precision operands are twice the width of single precision,
this configuration is consistent with a palette, used to provide
tile options, supplying at least 4 names with total storage of
16*N*M bytes. Depending upon the instruction encoding scheme used,
the number of tiles available varies.
[0045] In some embodiments, tile parameters are definable. For
example, a "palette" is used to provide tile options. Exemplary
options include, but are not limited to: the number of tile names,
the number of bytes in a row of storage, the number of rows and
columns in a tile, etc. For example, a maximum "height" (number of
rows) of a tile may be defined as:
[0046] Tile Max Rows=Architected Storage/(The Number of Palette
Names*The Number of Bytes per row)
[0047] As such, an application can be written such that a fixed
usage of names will be able to take advantage of different storage
sizes across implementations.
[0048] Configuration of tiles is done using a tile configuration
("TILECONFIG") instruction, where a particular tile usage is
defined in a selected palette. This declaration includes the number
of tile names to be used, the requested number of rows and columns
per name (tile), and, in some embodiments, the requested datatype
of each tile. In some embodiments, consistency checks are performed
during the execution of a TILECONFIG instruction to determine that
it matches the restrictions of the palette entry.
[0049] B. Exemplary tile storage types
[0050] FIG. 2 illustrates several examples of matrix storage. In
(A), a tile is stored in memory. As shown, each "row" consists of
four packed data elements. To get to the next "row," a stride value
is used. Note that rows may be consecutively stored in memory.
Strided memory accesses allows for access of one row to then next
when the tile storage does not map the underlying memory array row
width.
[0051] Tile loads from memory and stores to memory are typically
strided accesses from the application memory to packed rows of
data. Exemplary TILELOAD and TILESTORE instructions, or other
instruction references to application memory as a TILE operand in
load-op instructions, are, in some embodiments, restartable to
handle (up to) 2*rows of page faults, unmasked floating point
exceptions, and/or interrupts per instruction.
[0052] In (B), a matrix is stored in a tile comprised of a
plurality of registers such as packed data registers (single
instruction, multiple data (SIMD) or vector registers). In this
example, the tile is overlaid on three physical registers.
Typically, consecutive registers are used, however, this need not
be the case.
[0053] In (C), a matrix is stored in a tile in non-register storage
accessible to a fused multiple accumulate (FMA) circuit used in
tile operations. This storage may be inside of a FMA, or adjacent
to it. Additionally, in some embodiments, discussed below, the
storage may be for a data element and not an entire row or
tile.
[0054] The supported parameters for the TMMA architecture are
reported via CPUID. In some embodiments, the list of information
includes a maximum height and a maximum SIMD dimension. Configuring
the TMMA architecture requires specifying the dimensions for each
tile, the element size for each tile and the palette identifier.
This configuration is done by executing the TILECONFIG
instruction.
[0055] Successful execution of a TILECONFIG instruction enables
subsequent TILE operators. A TILERELEASEALL instruction clears the
tile configuration and disables the TILE operations (until the next
TILECONFIG instructions executes). In some embodiments, XSAVE,
XSTORE, etc. are used in context switching using tiles. In some
embodiments, 2 XCR0 bits are used in XSAVE, one for TILECONFIF
metadata and one bit corresponding to actual tile payload data.
[0056] TILECONFIG not only conFIGS. the tile usage, but also sets a
state variable indicating that the program is in a region of code
with tiles configured. An implementation may enumerate restrictions
on other instructions that can be used with a tile region such as
no usage of an existing register set, etc.
[0057] Exiting a tile region is typically done with the
TILERELEASEALL instruction. It takes no parameters and swiftly
invalidates all tiles (indicating that the data no longer needs any
saving or restoring) and clears the internal state corresponding to
being in a tile region.
[0058] In some embodiments, tile operations will zero any rows and
any columns beyond the dimensions specified by the tile
configuration. For example, tile operations will zero the data
beyond the configured number of columns (factoring in the size of
the elements) as each row is written. For example, with 64 byte
rows and a tile configured with 10 rows and 12 columns, an
operation writing FP32 elements would write each of the first 10
rows with 12*4 bytes with output/result data and zero the remaining
4*4 bytes in each row. Tile operations also fully zero any rows
after the first 10 configured rows. When using 1K tile with 64 byte
rows, there would be 16 rows, so in this example, the last 6 rows
would also be zeroed.
[0059] In some embodiments, a context restore (e.g., XRSTOR), when
loading data, enforces that the data beyond the configured rows for
a tile will be maintained as zero. If there is no valid
configuration, all rows are zeroed. XRSTOR of tile data can load
garbage in the columns beyond those configured. It should not be
possible for XRSTOR to clear beyond the number of columns
configured because there is not an element width associated with
the tile configuration.
[0060] Context save (e.g., XSAVE) exposes the entire TILE storage
area when writing it to memory. If XRSTOR loaded garbage data in to
the rightmost part of a tile, that data will be saved by XSAVE.
XSAVE will write zeros for rows beyond the number specified for
each tile.
[0061] In some embodiments, tile instructions are restartable. The
operations that access memory allow restart after page faults. The
computational instructions that deal with floating point operations
also allow for unmasked floating point exceptions, with the masking
of the exceptions controlled by a control and/or status
register.
[0062] To support restarting instructions after these events, the
instructions store information in the start registers detailed
below.
[0063] II. Matrix (Tile) Operation Systems
[0064] A. Exemplary Hardware Support
[0065] FIG. 3 illustrates an embodiment of a system utilizing a
matrix (tile) operations accelerator. In this illustration, a host
processor/processing system 301 communicates commands 311 (e.g.,
matrix manipulation operations such as arithmetic or matrix
manipulation operations, or load and store operations) to a matrix
operations accelerator 307. However, this is shown this way for
discussion purposes only. As detailed later, this accelerator 307
may be a part of a processing core. Typically, commands 311 that
are tile manipulation operator instructions will refer to tiles as
register-register ("reg-reg") or register-memory ("reg-mem")
format. Other commands such as TILESTORE, TILELOAD, TILECONFIG,
etc., do not perform data operations on a tile. Commands may be
decoded instructions (e.g., micro-ops) or macro-instructions for
the accelerator 307 to handle.
[0066] In this example, a coherent memory interface 303 is coupled
to the host processor/processing system 301 and matrix operations
accelerator 405 such that they can share memory. FIGS. 4 and 5 show
different embodiments of how memory is shared using a matrix
operations accelerator. As shown in FIG. 4, the host processor 401
and matrix operations accelerator circuitry 405 share the same
memory 403. FIG. 5 illustrates an embodiment where the host
processor 501 and matrix operations accelerator 505 do not share
memory, but can access each other's memory. For example, processor
501 can access tile memory 507 and utilize its host memory 503 as
normal. Similarly, the matrix operations accelerator 505 can access
host memory 503, but more typically uses its own memory 507. Note
these memories may be of different types.
[0067] The matrix operations accelerator 307 includes a plurality
of FMAs 309 coupled to data buffers 305 (in some implementations,
one or more of these buffers 305 are stored in the FMAs of the grid
as shown). The data buffers 305 buffer tiles loaded from memory
and/or tiles to be stored to memory (e.g., using a tileload or
tilestore instruction). Data buffers may be, for example, a
plurality of registers. Typically, these FMAs are arranged as a
grid of chained FMAs 309 which are able to read and write tiles. In
this example, the matrix operations accelerator 307 is to perform a
matrix multiply operation using tiles T0, T1, and T2. At least one
of tiles is housed in the FMA grid 309. In some embodiments, all
tiles in an operation are stored in the FMA grid 309. In other
embodiments, only a subset are stored in the FMA grid 309. As
shown, T1 is housed and T0 and T2 are not. Note that A, B, and C
refer to the matrices of these tiles which may or may not take up
the entire space of the tile.
[0068] FIG. 6 illustrates an embodiment of matrix multiply
accumulate operation using tiles ("TMMA").
[0069] The number of rows in the matrix (TILE A 601) matches the
number of serial (chained) FMAs comprising the computation's
latency. An implementation is free to recirculate on a grid of
smaller height, but the computation remains the same.
[0070] The source/destination vector comes from a tile of N rows
(TILE C 605) and the grid of FMAs 611 performs N vector-matrix
operations resulting in a complete instruction performing a matrix
multiplication of tiles. Tile B 603 is the other vector source and
supplies "broadcast" terms to the FMAs in each stage.
[0071] In operation, in some embodiments, the elements of matrix B
(stored in a tile B 603) are spread across the rectangular grid of
FMAs. Matrix B (stored in tile A 601) has its elements of a row
transposed to match up with the columnar dimension of the
rectangular grid of FMAs. At each FMA in the grid, an element of A
and B are multiplied and added to the incoming summand (from above
in the Figure) and the outgoing sum is passed to the next row of
FMAs (or the final output).
[0072] The latency of a single step is proportional to K (row
height of matrix B) and dependent TMMAs typically have enough
source-destination rows (either in a single tile or across tile) to
hide that latency. An implementation may also split the SIMD
(packed data element) dimension M (row height of matrix A) across
time steps, but this simply changes the constant that K is
multiplied by. When a program specifies a smaller K than the
maximum enumerated by the TMACC, an implementation is free to
implement this with "masking" or "early outs."
[0073] The latency of an entire TMMA is proportional to N*K. The
repeat rate is proportional to N. The number of MACs per TMMA
instruction is N*K*M.
[0074] FIG. 7 illustrates an embodiment of a subset of the
execution of an iteration of a chained fused multiply accumulate
instruction. In particular, this illustrates execution circuitry of
an iteration of one packed data element position of the
destination. In this embodiment, the chained fused multiply
accumulate is operating on signed sources wherein the accumulator
is 2.times. the input data size.
[0075] A first signed source (source 1 701) and a second signed
source (source 2 703) each have four packed data elements. Each of
these packed data elements stores signed data such as floating
point data. A third signed source (source 3 709) has two packed
data elements, each of which stores signed data. The sizes of the
first and second signed sources 701 and 703 are half that of the
third signed source (initial value or previous result) 709. For
example, the first and second signed sources 701 and 703 could have
32-bit packed data elements (e.g., single precision floating point)
while the third signed source 709 could have 64-bit packed data
elements (e.g., double precision floating point).
[0076] In this illustration, only the two most significant packed
data element positions of the first and second signed sources 701
and 703 and the most significant packed data element position of
the third signed source 709 are shown. Of course, the other packed
data element positions would also be processed.
[0077] As illustrated, packed data elements are processed in pairs.
For example, the data of the most significant packed data element
positions of the first and second signed sources 701 and 703 are
multiplied using a multiplier circuit 705, and the data from second
most significant packed data element positions of the first and
second signed sources 701 and 703 are multiplied using a multiplier
circuit 707. In some embodiments, these multiplier circuits 705 and
707 are reused for other packed data elements positions. In other
embodiments, additional multiplier circuits are used so that the
packed data elements are processed in parallel. In some contexts,
parallel execution is done using lanes that are the size of the
signed third source 709. The results of each of the multiplications
are added using addition circuitry 711.
[0078] The result of the addition of the results of the
multiplications is added to the data from most significant packed
data element position of the signed source 3 709 (using a different
adder 713 or the same adder 711).
[0079] Finally, the result of the second addition is either stored
into the signed destination 715 in a packed data element position
that corresponds to the packed data element position used from the
signed third source 709, or passed on to the next iteration, if
there is one. In some embodiments, a writemask is applied to this
storage such that if a corresponding writemask (bit) is set, the
storage happens, and, if not set, the storage does not happen.
[0080] FIG. 8 illustrates an embodiment of a subset of the
execution of an iteration of a chained fused multiply accumulate
instruction. In particular, this illustrates execution circuitry of
an iteration of one packed data element position of the
destination. In this embodiment, the chained fused multiply
accumulate is operating on signed sources wherein the accumulator
is 2.times. the input data size.
[0081] A first signed source (source 1 801) and a second signed
source (source 2 803) each have four packed data elements. Each of
these packed data elements stores signed data such as integer data.
A third signed source (source 3 809) has two packed data elements,
each of which stores signed data. The sizes of the first and second
signed sources 801 and 803 are half that of the third signed source
809. For example, the first and second signed sources 801 and 803
could have 32-bit packed data elements (e.g., single precision
floating point) the third signed source 809 could have 64-bit
packed data elements (e.g., double precision floating point).
[0082] In this illustration, only the two most significant packed
data element positions of the first and second signed sources 801
and 803 and the most significant packed data element position of
the third signed source 809 are shown. Of course, the other packed
data element positions would also be processed.
[0083] As illustrated, packed data elements are processed in pairs.
For example, the data of the most significant packed data element
positions of the first and second signed sources 801 and 803 are
multiplied using a multiplier circuit 805, and the data from second
most significant packed data element positions of the first and
second signed sources 801 and 803 are multiplied using a multiplier
circuit 807. In some embodiments, these multiplier circuits 805 and
807 are reused for other packed data elements positions. In other
embodiments, additional multiplier circuits are used so that the
packed data elements are processed in parallel. In some contexts,
parallel execution is done using lanes that are the size of the
signed third source (initial value or previous iteration result)
809. The results of each of the multiplications are added to the
signed third source 809 using addition/saturation circuitry
811.
[0084] Addition/saturation (accumulator) circuitry 811 preserves a
sign of an operand when the addition results in a value that is too
big. In particular, saturation evaluation occurs on the infinite
precision result between the multi-way-add and the write to the
destination or next iteration. When the accumulator 811 is floating
point and the input terms are integer, the sum of products and the
floating point accumulator input value are turned into infinite
precision values (fixed point numbers of hundreds of bits), the
addition of the multiplication results and the third input is
performed, and a single rounding to the actual accumulator type is
performed.
[0085] Unsigned saturation means the output values are limited to a
maximum unsigned number for that element width (all 1s). Signed
saturation means a value is limited to the be in the range between
a minimum negative number and a max positive number for that
element width (for bytes for example, the range is from -128
(=-2{circumflex over ( )}7) to 127(=2{circumflex over (
)}7-1)).
[0086] The result of the addition and saturation check is stored
into the signed result 815 in a packed data element position that
corresponds to the packed data element position used from the
signed third source 809, or passed on to the next iteration if
there is one. In some embodiments, a writemask is applied to this
storage such that if a corresponding writemask (bit) is set, the
storage happens, and, if not set, the storage does not happen.
[0087] FIG. 9 illustrates an embodiment of a subset of the
execution of an iteration of a chained fused multiply accumulate
instruction. In particular, this illustrates execution circuitry of
an iteration of one packed data element position of the
destination. In this embodiment, the chained fused multiply
accumulate is operating on a signed source and an unsigned source
wherein the accumulator is 4.times. the input data size.
[0088] A first signed source (source 1 901) and a second unsigned
source (source 2 903) each have four packed data elements. Each of
these packed data elements has data such as floating point or
integer data. A third signed source (initial value or result 915)
has a packed data element of which stores signed data. The sizes of
the first and second sources 901 and 903 are a quarter of the third
signed source 915. For example, the first and second sources 901
and 903 could have 16-bit packed data elements (e.g., word) and the
third signed source 915 could have 64-bit packed data elements
(e.g., double precision floating point or 64-bit integer).
[0089] In this illustration, the four most significant packed data
element positions of the first and second sources 901 and 903 and
the most significant packed data element position of the third
signed source 915 are shown. Of course, other packed data element
positions would also be processed if there are any.
[0090] As illustrated, packed data elements are processed in
quadruplets. For example, the data of the most significant packed
data element positions of the first and second sources 901 and 903
are multiplied using a multiplier circuit 907, data from second
most significant packed data element positions of the first and
second sources 901 and 903 are multiplied using a multiplier
circuit 907, data from third most significant packed data element
positions of the first and second sources 901 and 903 are
multiplied using a multiplier circuit 909, and data from the least
significant packed data element positions of the first and second
sources 901 and 903 are multiplied using a multiplier circuit 911.
In some embodiments, the signed packed data elements of the first
source 901 are sign extended and the unsigned packed data elements
of the second source 903 are zero extended prior to the
multiplications.
[0091] In some embodiments, these multiplier circuits 905-911 are
reused for other packed data elements positions. In other
embodiments, additional multiplier circuits are used so that the
packed data elements are processed in parallel. In some contexts,
parallel execution is done using lanes that are the size of the
signed third source 915. The results of each of the multiplications
are added using addition circuitry 911.
[0092] The result of the addition of the results of the
multiplications is added to the data from most significant packed
data element position of the signed source 3 915 (using a different
adder 913 or the same adder 911).
[0093] Finally, the result 919 of the second addition is either
stored into the signed destination in a packed data element
position that corresponds to the packed data element position used
from the signed third source 915, or passed to the next iteration.
In some embodiments, a writemask is applied to this storage such
that if a corresponding writemask (bit) is set, the storage
happens, and, if not set, the storage does not happen.
[0094] FIG. 10 illustrates an embodiment of a subset of the
execution of an iteration of chained fused multiply accumulate
instruction. In particular, this illustrates execution circuitry of
an iteration of one packed data element position of the
destination. In this embodiment, the chained fused multiply
accumulate is operating on a signed source and an unsigned source
wherein the accumulator is 4.times. the input data size.
[0095] A first signed source (source 1 1001) and a second unsigned
source (source 2 1003) each have four packed data elements. Each of
these packed data elements stores data such as floating point or
integer data. A third signed source (initial or previous result
1015) has a packed data element of which stores signed data. The
sizes of the first and second sources 1001 and 1003 are a quarter
of the third signed source 1015. For example, the first and second
sources 1001 and 1003 could have 16-bit packed data elements (e.g.,
word) and the third signed source 1015 could have 64-bit packed
data elements (e.g., double precision floating point or 64-bit
integer).
[0096] In this illustration, the four most significant packed data
element positions of the first and second sources 1001 and 1003 and
the most significant packed data element position of the third
signed source 1015 are shown. Of course, other packed data element
positions would also be processed if there are any.
[0097] As illustrated, packed data elements are processed in
quadruplets. For example, the data of the most significant packed
data element positions of the first and second sources 1001 and
1003 are multiplied using a multiplier circuit 1007, data from
second most significant packed data element positions of the first
and second sources 1001 and 1003 are multiplied using a multiplier
circuit 1007, data from third most significant packed data element
positions of the first and second sources 1001 and 1003 are
multiplied using a multiplier circuit 1009, and data from the least
significant packed data element positions of the first and second
sources 1001 and 1003 are multiplied using a multiplier circuit
1011. In some embodiments, the signed packed data elements of the
first source 1001 are sign extended and the unsigned packed data
elements of the second source 1003 are zero extended prior to the
multiplications.
[0098] In some embodiments, these multiplier circuits 1005-1011 are
reused for other packed data elements positions. In other
embodiments, additional multiplier circuits are used so that the
packed data elements are processed in parallel. In some contexts,
parallel execution is done using lanes that are the size of the
signed third source 1015. The result of the addition of the results
of the multiplications is added to the data from most significant
packed data element position of the signed source 3 1015 using
addition/saturation circuitry 1013.
[0099] Addition/saturation (accumulator) circuitry 1013 preserves a
sign of an operand when the addition results in a value that is too
big or too small for signed saturation. In particular, saturation
evaluation occurs on the infinite precision result between the
multi-way-add and the write to the destination. When the
accumulator 1013 is floating point and the input terms are integer,
the sum of products and the floating point accumulator input value
are turned into infinite precision values (fixed point numbers of
hundreds of bits), the addition of the multiplication results and
the third input is performed, and a single rounding to the actual
accumulator type is performed.
[0100] The result 1019 of the addition and saturation check is
stored into the signed destination in a packed data element
position that corresponds to the packed data element position used
from the signed third source 1015, or passed to the next iteration.
In some embodiments, a writemask is applied to this storage such
that if a corresponding writemask (bit) is set, the storage
happens, and, if not set, the storage does not happen.
[0101] FIG. 11 illustrates power-of-two sized SIMD implementations
wherein the accumulators use input sizes that are larger than the
inputs to the multipliers according to an embodiment. Note the
source (to the multipliers) and accumulator values may be signed or
unsigned values. For an accumulator having 2.times. input sizes (in
other words, the accumulator input value is twice the size of the
packed data element sizes of the sources), table 1101 illustrates
different configurations. For byte sized sources, the accumulator
uses word or half-precision floating-point (HPFP) values that are
16-bit in size. For word sized sources, the accumulator uses 32-bit
integer or single-precision floating-point (SPFP) values that are
32-bit in size. For SPFP or 32-bit integer sized sources, the
accumulator uses 64-intenger or double-precision floating-point
(DPFP) values that are 64-bit in size.
[0102] For an accumulator having 4.times. input sizes (in other
words, the accumulator input value is four times the size of the
packed data element sizes of the sources), table 1103 illustrates
different configurations. For byte sized sources, the accumulator
uses 32-bit integer or single-precision floating-point (SPFP)
values that are 32-bit in size. For word sized sources, the
accumulator uses 64-bit integer or double-precision floating-point
(DPFP) values that are 64-bit in size in some embodiments.
[0103] For an accumulator having 8.times. input sizes (in other
words, the accumulator input value is eight times the size of the
packed data element sizes of the sources), table 1105 illustrates a
configuration. For byte sized sources, the accumulator uses 64-bit
integer.
[0104] As hinted at earlier, matrix operations circuitry may be
included in a core, or as an external accelerator. FIG. 12
illustrates an embodiment of a system utilizing matrix operations
circuitry. In this illustration, a plurality of entities are
coupled with a ring interconnect 1245.
[0105] A plurality of cores 1201, 1203, 1205, and 1207 provide
non-tile based instruction support. In some embodiments, matrix
operations circuitry is provided in a core 1203, and in other
embodiments matrix operations circuitry 1211 and 1213 is accessible
on the ring interconnect 1245.
[0106] Additionally, one or more memory controllers 1223-1225 are
provided to communicate with memory 1233 and 1231 on behalf of the
cores and/or matrix operations circuitry.
[0107] FIG. 13 illustrates an embodiment of a processor core
pipeline supporting matrix operations using tiles. Branch
prediction and decode circuitry 1303 performs branch predicting of
instructions, decoding of instructions, and/or both from
instructions stored in instruction storage 1301. For example,
instructions detailed herein may be stored in instruction storage.
In some implementations, separate circuitry is used for branch
prediction and in some embodiments, at least some instructions are
decoded into one or more micro-operations, micro-code entry points,
microinstructions, other instructions, or other control signals
using microcode 1305. The branch prediction and decode circuitry
1303 may be implemented using various different mechanisms.
Examples of suitable mechanisms include, but are not limited to,
look-up tables, hardware implementations, programmable logic arrays
(PLAs), microcode read only memories (ROMs), etc.
[0108] The branch prediction and decode circuitry 1303 is coupled
to a rename/allocator circuitry 1307 which is coupled, in some
embodiments, to scheduler circuitry 1309. In some embodiments,
these circuits provide register renaming, register allocation,
and/or scheduling functionality by performing one or more of: 1)
renaming logical operand values to physical operand values (e.g., a
register alias table in some embodiments), 2) allocating status
bits and flags to the decoded instruction, and 3) scheduling the
decoded instruction for execution on execution circuitry out of an
instruction pool (e.g., using a reservation station in some
embodiments).
[0109] The scheduler circuitry 1309 represents any number of
different schedulers, including reservations stations, central
instruction window, etc. The scheduler unit(s) scheduler circuitry
1309 is coupled to, or includes, physical register file(s) 1315.
Each of the physical register file(s) 1315 represents one or more
physical register files, different ones of which store one or more
different data types, such as scalar integer, scalar floating
point, packed integer, packed floating point, vector integer,
vector floating point, status (e.g., an instruction pointer that is
the address of the next instruction to be executed), tiles, etc. In
one embodiment, the physical register file(s) 1315 comprises vector
registers circuitry, write mask registers circuitry, and scalar
registers circuitry. These register circuits may provide
architectural vector registers, vector mask registers, and general
purpose registers. The physical register file(s) 1315 is overlapped
by a retirement circuit 1317 to illustrate various ways in which
register renaming and out-of-order execution may be implemented
(e.g., using a reorder buffer(s) and a retirement register file(s);
using a future file(s), a history buffer(s), and a retirement
register file(s); using a register maps and a pool of registers;
etc.). The retirement circuit 1317 and the physical register
file(s) 1315 are coupled to the execution circuit(s) 1311.
[0110] While register renaming is described in the context of
out-of-order execution, it should be understood that register
renaming may be used in an in-order architecture. While the
illustrated embodiment of the processor may also include separate
instruction and data cache units and a shared L2 cache unit,
alternative embodiments may have a single internal cache for both
instructions and data, such as, for example, a Level 1 (L1)
internal cache, or multiple levels of internal cache. In some
embodiments, the system may include a combination of an internal
cache and an external cache that is external to the core and/or the
processor. Alternatively, all of the cache may be external to the
core and/or the processor.
[0111] The execution circuitry 1311 a set of one or more execution
circuits 1321, 1323, and 1327 and a set of one or more memory
access circuits 1325. The execution circuits 1321, 1323, and 1327
perform various operations (e.g., shifts, addition, subtraction,
multiplication) and on various types of data (e.g., scalar floating
point, packed integer, packed floating point, vector integer,
vector floating point). While some embodiments may include a number
of execution units dedicated to specific functions or sets of
functions, other embodiments may include only one execution unit or
multiple execution units that all perform all functions. The scalar
circuitry 1321 performs scalar operations, the vector/SIMD
circuitry 1323 performs vector/SIMD operations, and matrix
operations circuitry 1327 performs matrix (tile) operations
detailed herein.
[0112] The set of memory access units 1364 is coupled to the memory
unit 1370, which includes a data TLB unit 1372 coupled to a data
cache unit 1374 coupled to a level 2 (L2) cache unit 1376. In one
exemplary embodiment, the memory access units 1364 may include a
load unit, a store address unit, and a store data unit, each of
which is coupled to the data TLB unit 1372 in the memory unit 1370.
The instruction cache unit 1334 is further coupled to a level 2
(L2) cache unit 1376 in the memory unit 1370. The L2 cache unit
1376 is coupled to one or more other levels of cache and eventually
to a main memory.
[0113] By way of example, the exemplary register renaming,
out-of-order issue/execution core architecture may implement a
pipeline as follows: 1) an instruction fetch circuit performs fetch
and length decoding stages; 2) the branch and decode circuitry 1303
performs a decode stage; 3) the rename/allocator circuitry 1307
performs an allocation stage and renaming stage; 4) the scheduler
circuitry 1309 performs a schedule stage; 5) physical register
file(s) (coupled to, or included in, the scheduler circuitry 1307
and rename/allocate circuitry 1307 and a memory unit perform a
register read/memory read stage; the execution circuitry 1311
performs an execute stage; 6) a memory unit and the physical
register file(s) unit(s) perform a write back/memory write stage;
7) various units may be involved in the exception handling stage;
and 8) a retirement unit and the physical register file(s) unit(s)
perform a commit stage.
[0114] The core may support one or more instructions sets (e.g.,
the .times.86 instruction set (with some extensions that have been
added with newer versions); the MIPS instruction set of MIPS
Technologies of Sunnyvale, Calif.; the ARM instruction set (with
optional additional extensions such as NEON) of ARM Holdings of
Sunnyvale, Calif.), including the instruction(s) described herein.
In one embodiment, the core 1390 includes logic to support a packed
data instruction set extension (e.g., AVX1, AVX2), thereby allowing
the operations used by many multimedia applications to be performed
using packed data.
[0115] It should be understood that the core may support
multithreading (executing two or more parallel sets of operations
or threads), and may do so in a variety of ways including time
sliced multithreading, simultaneous multithreading (where a single
physical core provides a logical core for each of the threads that
physical core is simultaneously multithreading), or a combination
thereof (e.g., time sliced fetching and decoding and simultaneous
multithreading thereafter such as in the Intel.RTM. Hyperthreading
technology).
[0116] FIG. 14 illustrates an embodiment of a processor core
pipeline supporting matrix operations using tiles. Branch
prediction and decode circuitry 1403 performs branch predicting of
instructions, decoding of instructions, and/or both from
instructions stored in instruction storage 1401. For example,
instructions detailed herein may be stored in instruction storage.
In some implementations, separate circuitry is used for branch
prediction and in some embodiments, at least some instructions are
decoded into one or more micro-operations, micro-code entry points,
microinstructions, other instructions, or other control signals
using microcode 1405. The branch prediction and decode circuitry
1403 may be implemented using various different mechanisms.
Examples of suitable mechanisms include, but are not limited to,
look-up tables, hardware implementations, programmable logic arrays
(PLAs), microcode read only memories (ROMs), etc.
[0117] The branch prediction and decode circuitry 1403 is coupled
to a rename/allocator circuitry 1407 which is coupled, in some
embodiments, to scheduler circuitry 1409. In some embodiments,
these circuits provide register renaming, register allocation,
and/or scheduling functionality by performing one or more of: 1)
renaming logical operand values to physical operand values (e.g., a
register alias table in some embodiments), 2) allocating status
bits and flags to the decoded instruction, and 3) scheduling the
decoded instruction for execution on execution circuitry out of an
instruction pool (e.g., using a reservation station in some
embodiments).
[0118] The scheduler circuitry 1409 represents any number of
different schedulers, including reservations stations, central
instruction window, etc. The scheduler unit(s) scheduler circuitry
1409 is coupled to, or includes, physical register file(s) 1415.
Each of the physical register file(s) 1415 represents one or more
physical register files, different ones of which store one or more
different data types, such as scalar integer, scalar floating
point, packed integer, packed floating point, vector integer,
vector floating point, status (e.g., an instruction pointer that is
the address of the next instruction to be executed), tiles, etc. In
one embodiment, the physical register file(s) 1415 comprises vector
registers circuitry, write mask registers circuitry, and scalar
registers circuitry. These register circuits may provide
architectural vector registers, vector mask registers, and general
purpose registers. The physical register file(s) 1415 is overlapped
by a retirement circuit 1417 to illustrate various ways in which
register renaming and out-of-order execution may be implemented
(e.g., using a reorder buffer(s) and a retirement register file(s);
using a future file(s), a history buffer(s), and a retirement
register file(s); using a register maps and a pool of registers;
etc.). The retirement circuit 1417 and the physical register
file(s) 1415 are coupled to the execution circuit(s) 1411.
[0119] While register renaming is described in the context of
out-of-order execution, it should be understood that register
renaming may be used in an in-order architecture. While the
illustrated embodiment of the processor may also include separate
instruction and data cache units and a shared L2 cache unit,
alternative embodiments may have a single internal cache for both
instructions and data, such as, for example, a Level 1 (L1)
internal cache, or multiple levels of internal cache. In some
embodiments, the system may include a combination of an internal
cache and an external cache that is external to the core and/or the
processor. Alternatively, all of the cache may be external to the
core and/or the processor.
[0120] The execution circuitry 1411 a set of one or more execution
circuits 1427 and a set of one or more memory access circuits 1425.
The execution circuits 1427 perform matrix (tile) operations
detailed herein.
[0121] The set of memory access units 1464 is coupled to the memory
unit 1470, which includes a data TLB unit 1472 coupled to a data
cache unit 1474 coupled to a level 2 (L2) cache unit 1476. In one
exemplary embodiment, the memory access units 1464 may include a
load unit, a store address unit, and a store data unit, each of
which is coupled to the data TLB unit 1472 in the memory unit 1470.
The instruction cache unit 1434 is further coupled to a level 2
(L2) cache unit 1476 in the memory unit 1470. The L2 cache unit
1476 is coupled to one or more other levels of cache and eventually
to a main memory.
[0122] By way of example, the exemplary register renaming,
out-of-order issue/execution core architecture may implement a
pipeline as follows: 1) an instruction fetch circuit performs fetch
and length decoding stages; 2) the branch and decode circuitry 1403
performs a decode stage; 3) the rename/allocator circuitry 1407
performs an allocation stage and renaming stage; 4) the scheduler
circuitry 1409 performs a schedule stage; 5) physical register
file(s) (coupled to, or included in, the scheduler circuitry 1407
and rename/allocate circuitry 1407 and a memory unit perform a
register read/memory read stage; the execution circuitry 1411
performs an execute stage; 6) a memory unit and the physical
register file(s) unit(s) perform a write back/memory write stage;
7) various units may be involved in the exception handling stage;
and 8) a retirement unit and the physical register file(s) unit(s)
perform a commit stage.
[0123] The core may support one or more instructions sets (e.g.,
the x86 instruction set (with some extensions that have been added
with newer versions); the MIPS instruction set of MIPS Technologies
of Sunnyvale, Calif.; the ARM instruction set (with optional
additional extensions such as NEON) of ARM Holdings of Sunnyvale,
Calif.), including the instruction(s) described herein. In one
embodiment, the core 1490 includes logic to support a packed data
instruction set extension (e.g., AVX1, AVX2), thereby allowing the
operations used by many multimedia applications to be performed
using packed data.
[0124] It should be understood that the core may support
multithreading (executing two or more parallel sets of operations
or threads), and may do so in a variety of ways including time
sliced multithreading, simultaneous multithreading (where a single
physical core provides a logical core for each of the threads that
physical core is simultaneously multithreading), or a combination
thereof (e.g., time sliced fetching and decoding and simultaneous
multithreading thereafter such as in the Intel.RTM. Hyperthreading
technology).
[0125] B. Layout
[0126] Throughout this description, data is expressed using row
major data layout. Column major users should translate the terms
according to their orientation. FIG. 15 illustrates an example of a
matrix expressed in row major format and column major format. As
shown, matrix A is a 2.times.3 matrix. When this matrix is stored
in row major format, the data elements of a row are consecutive.
When this matrix is stored in column major format, the data
elements of a column are consecutive. It is a well-known property
of matrices that A.sup.T*B.sup.T=(BA).sup.T, where superscript T
means transpose. Reading column major data as row major data
results in the matrix looking like the transpose matrix.
[0127] In some embodiments, row-major semantics are utilized in
hardware, and column major data is to swap the operand order with
the result being transposes of matrix, but for subsequent
column-major reads from memory it is the correct, non-transposed
matrix.
[0128] For example, if there are two column-major matrices to
multiply:
a .times. b .times. g .times. i .times. k .times. ag + bh .times.
ai + bj .times. ak + bl .times. c .times. d * h .times. j .times. l
= cg + dh .times. ci + dj .times. ck + dl .times. e .times. f
.times. eg + fh .times. ei + fj .times. ek + fl .times. ( 3 .times.
2 ) .times. ( 2 .times. 3 ) .times. ( 3 .times. 3 )
##EQU00001##
[0129] The input matrices would be stored in linear memory
(column-major) as:
[0130] a c e b d f
[0131] and
[0132] g h i j k l.
[0133] Reading those matrices as row-major with dimensions
2.times.3 and 3.times.2, they would appear as:
a .times. c .times. e .times. and .times. g .times. h .times. b
.times. d .times. f .times. i .times. j .times. k .times. l
##EQU00002##
[0134] Swapping the order and matrix multiplying:
g .times. h .times. a .times. c .times. e .times. ag + bh .times.
cg + dh .times. eg + fh .times. i .times. j * b .times. d .times. f
= ai + bj .times. ci + dj .times. ei + fj .times. k .times. l
.times. ak + bl .times. ck + dl .times. ek + fl ##EQU00003##
[0135] the transpose matrix is out and can then be stored in in
row-major order:
ag + bh .times. cg + dh .times. eg + fh .times. ai + bj .times. ci
+ dj .times. ei + fj .times. ak + bl .times. ck + dl .times. ek +
fl ##EQU00004##
[0136] and used in subsequent column major computations, it is the
correct un-transposed matrix:
ag + bh .times. ai + bj .times. ak + bl .times. cg + dh .times. ci
+ dj .times. ck + dl .times. eg + fh .times. ei + fj .times. ek +
fl ##EQU00005##
[0137] III. Exemplary Usage
[0138] FIG. 16 illustrates an example of usage of matrices (tiles).
In this example, matrix C 1601 includes two tiles, matrix A 1603
includes one tile, and matrix B 1605 includes two tiles. This
figure shows an example of the inner loop of an algorithm to
compute a matrix multiplication. In this example, two result tiles,
tmm0 and tmm1, from matrix C 1601 are used to accumulate the
intermediate results. One tile from the A matrix 1603 (tmm2) is
re-used twice as it multiplied by two tiles from the B matrix 1605.
Pointers to load a new A tile and two new B tiles from the
directions indicated by the arrows. An outer loop, not shown,
adjusts the pointers for the C tiles.
[0139] The exemplary code as shown includes the usage of a tile
configuration instruction and is executed to configure tile usage,
load tiles, a loop to process the tiles, store tiles to memory, and
release tile usage.
[0140] FIG. 17 illustrates an embodiment of usage of matrices
(tiles). At 1701, tile usage is configured. For example, a
TILECONFIG instruction is executed to configure tile usage
including setting a numbers of rows and columns per tile.
Typically, at least one matrix (tile) is loaded from memory at
1703.
[0141] IV. Exemplary Instructions
[0142] A. Tile Configuration
[0143] As discussed above, tile usage typically needs to be
configured prior to use. For example, full usage of all rows and
columns may not be needed. Not only does not configuring these rows
and columns save power in some embodiments, but the configuration
may be used to determine if an operation will generate an error.
For example, a matrix multiplication of the form (N.times.M)*(L*N)
will typically not work if M and L are not the same.
[0144] Detailed herein are embodiments of a matrix (tile)
configuration ("TILECONFIG") instruction and its execution. Prior
to using matrices using tiles, in some embodiments, tile support is
to be configured. For example, how many rows and columns per tile,
tiles that are to be used, etc. are configured. A TILECONFIG
instruction is an improvement to a computer itself as it provides
for support to configure the computer to use a matrix accelerator
(either as a part of a processor core, or as an external device).
In particular, an execution of the TILECONFIG instruction causes a
configuration to be retrieved from memory and applied to matrix
(tile) settings within a matrix accelerator.
i. Exemplary Execution
[0145] FIG. 18 illustrates an exemplary execution of a TILECONFIG
instruction. The TILECONFIG instruction format includes fields for
an opcode and a memory address.
[0146] As illustrated, the TILECONFIG instruction uses the address
as a pointer to a memory 1801 location containing the description
of the matrices (tiles) to be supported 1803.
[0147] Execution circuitry 1811 of a processor/core 1805 performs
the TILECONFIG by retrieving the description 1803 from memory 1801
via a memory controller 1815, configuring tiles for a palette
(setting the number of rows and columns) in a tile configuration
1817, and marking that matrix support is in use. In particular,
instruction execution resources 1811 are configured to use tiles as
specified by setting tile configurations 1817. The instruction
execution resources may also include a machine specific register or
configuration register to indicate tile usage.
[0148] Tile configurations 1817 are set to indicate parameters per
tile as indicated by the tile description 1803 via the execution of
the TILECONFIG instruction. The set parameters are the number of
rows and columns per tile. Additional values such as in-use and
start values are also set. The tile configurations 1817 utilize one
or more registers 1819 to store tile usage and configuration
information.
ii. Exemplary Tile Storage
[0149] FIGS. 19(A)-(D) illustrate examples of register(s) 1819.
FIG. 19(A) illustrates a plurality of registers 1819. As shown each
tile (TMM0 1901 . . . TMMN 1903) has a separate register with each
register storing a row and column size for that particular tile.
StartK and StartM are stored in separate registers 1911 and 1913.
One or more status registers 1915 are set (e.g.,
TILES_CONFIGURED=1) to indicate tiles are configured for use.
[0150] FIG. 19(B) illustrates a plurality of registers 1819. As
shown each tile has separate registers for its rows and columns For
example, TMM0 rows configuration 1921, TMM0 columns configuration
1923, StartK and StartM are stored in separate registers 1911 and
1913. One or more status registers 1915 are set (e.g.,
TILES_CONFIGURED=1) to indicate tiles are configured for use.
[0151] FIG. 19(C) illustrates a single register 1819. As shown,
this register stores tile configurations (rows and columns per
tile) 1931, StartK 1933, and StartM 1933 are stored in single
register as packed data registers. One or more status registers
1915 are set (e.g., TILES_CONFIGURED=1) to indicate tiles are
configured for use.
[0152] FIG. 19(D) illustrates a plurality of registers 1819. As
shown, a single register stores tile configurations (rows and
columns per tile) 1931. StartK and StartM are stored in separate
registers 1911 and 1913. One or more status registers 1915 are set
(e.g., TILES_CONFIGURED=1) to indicate tiles are configured for
use.
[0153] Other combinations are contemplated such as combining the
start registers into a single register where they are shown
separately, etc.
iii. Exemplary Stored Matrix (Tile) Description
[0154] FIG. 20 illustrates an embodiment of a description of the
matrices (tiles) to be supported. In this example, each field is a
byte. In byte[0], a palette ID 2001 is stored. The palette ID is
used to index a palette table 1813 which stores, per palette ID, a
number of bytes in a tile, and bytes per row of the tiles that are
associated with this ID as defined by the configuration. Bytes 1-7
are reserved and are typically zero.
[0155] Bytes 8-9 store a value for a "startM" register 2003 and
bytes 10-11 store a value for a "startK" register 2005. To support
restarting instructions after these events, the instructions store
information these registers. The startM indicates a row that should
be used for restart. The startK indicates a position in the
inner-product for relevant operations. The position in the row (the
column) is not needed. Two-dimensional operations like the
element-wise addition/subtraction/multiplication only use startM.
Three-dimensional operations use values from both startM and
startK. Typically, operations that only require startM will zero
startK when writing startM.
[0156] Any time an interrupted tile instruction is not restarted,
in some embodiments, it is the responsibility of software to zero
the startM and startK values. For example, unmasked floating point
exception handlers might decide to finish the operation in software
and change the program counter value to another instruction,
usually the next instruction. In this case the software exception
handler must zero the startM and startK values in the exception
frame presented to it by the operating system before resuming the
program. The operating system will subsequently reload those
values.
[0157] Bytes 16-17 store the number of rows 2013 and columns 2015
for tile 0, bytes 18-19 store the number of rows and columns for
tile 1, etc. In other words, each 2 byte group specifies a number
of rows and columns for a tile. If a group of 2 bytes is not used
to specify tile parameters, they should have the value zero.
Specifying tile parameters for more tiles than the implementation
limit or the palette limit results in a fault. Unconfigured tiles
are set to the INIT state with 0 rows, 0 columns
[0158] Finally, the configuration in memory typically ends with an
ending delineation such as all zeros for several consecutive
bytes.
iv. Exemplary Format(s)
[0159] An embodiment of a format for a TILECONFIG instruction is
TILECONFIG Address. In some embodiments, TILECONFIG is the opcode
mnemonic of the instruction. Address is a pointer to a matrix
(tile) description in memory. In some embodiments, the address
field is a R/M value (such as 2446).
[0160] In embodiments, encodings of the instruction include a
scale-index-base (SIB) type memory addressing operand that
indirectly identifies multiple indexed destination locations in
memory (e.g., field 2450). In one embodiment, an SIB type memory
operand may include an encoding identifying a base address
register. The contents of the base address register may represent a
base address in memory from which the addresses of the particular
destination locations in memory are calculated. For example, the
base address may be the address of the first location in a block of
potential destination locations for an extended vector instruction.
In one embodiment, an SIB type memory operand may include an
encoding identifying an index register. Each element of the index
register may specify an index or offset value usable to compute,
from the base address, an address of a respective destination
location within a block of potential destination locations. In one
embodiment, an SIB type memory operand may include an encoding
specifying a scaling factor to be applied to each index value when
computing a respective destination address. For example, if a
scaling factor value of four is encoded in the SIB type memory
operand, each index value obtained from an element of the index
register may be multiplied by four and then added to the base
address to compute a destination address.
[0161] In one embodiment, an SIB type memory operand of the form
vm32{x,y,z} may identify a vector array of memory operands
specified using SIB type memory addressing. In this example, the
array of memory addresses is specified using a common base
register, a constant scaling factor, and a vector index register
containing individual elements, each of which is a 32-bit index
value. The vector index register may be a 128-bit register (e.g.,
XMM) register (vm32x), a 256-bit (e.g., YMM) register (vm32y), or a
512-bit (e.g., ZMM) register (vm32z). In another embodiment, an SIB
type memory operand of the form vm64{x,y,z} may identify a vector
array of memory operands specified using SIB type memory
addressing. In this example, the array of memory addresses is
specified using a common base register, a constant scaling factor,
and a vector index register containing individual elements, each of
which is a 64-bit index value. The vector index register may be a
128-bit register (e.g., XMM) register (vm64x), a 256-bit (e.g.,
YMM) register (vm64y) or a 512-bit (e.g., ZMM) register
(vm64z).
v. Exemplary Method(s) of Execution
[0162] FIG. 21 illustrates an embodiment of method performed by a
processor to process a TILECONFIG instruction.
[0163] At 2101, an instruction is fetched. For example, a
TILECONFIG instruction is fetched. An embodiment of the TILECONFIG
instruction includes fields for an opcode and a memory address
operand.
[0164] The fetched instruction is decoded at 2103. For example, the
fetched TILECONFIG instruction is decoded by decode circuitry such
as that detailed herein.
[0165] A description found at the memory address of the memory
address operand is are retrieved at 2105 and the decoded
instruction is scheduled (as needed).
[0166] At 2107, the decoded instruction is executed by execution
circuitry (hardware) such as that detailed herein. For the
TILECONFIG instruction, the execution will cause execution
circuitry to configure usage of tiles in a tile configuration
(setting the number of rows and columns) and marking that matrix
(tile) support is in use (active). For example, configuration one
or more registers 1819. Tile support usage (e.g.,
"TILES_CONFIGURED") is typically indicated by setting a bit in a
status, control, or machine specific register. In particular,
instruction execution resources 1811 are configured to use tiles as
specified by the retrieved configuration.
[0167] In some embodiments, the instruction is committed or retired
at 2109.
[0168] FIG. 22 illustrates a more detailed description of an
execution of a TILECONFIG instruction using memory addressing.
Typically, this is performed by execution circuitry such as that
detailed above after the description has been retrieved from
memory. While not illustrated, in some embodiments, a check is
first performed to determine if tiles are supported. Support is
usually found by a CPUID check.
[0169] At 2201, a determination of if the palette ID is supported
is made. For example, does the CPUID state that this ID is
supported? If not, then a general protection fault occurs at
2203.
[0170] At 2205, a first tile specific grouping is read. For
example, the number of rows and columns for tile 0 (T0) is
read.
[0171] A determination of if the read grouping is valid is made at
2207. For example, if one the number of rows or columns (not both)
is set 0, then the grouping is not valid and the configuration
halts and tiles are not considered to be in use at 2203. Invalid
groups occur, for example, when one of rows or columns (not both)
are zero. Additionally, when a value for the number of rows is
greater than the maximum of rows supported (this is found by
dividing the tile byte size of the palette ID with the number of
bytes per row for the palette ID as found in the palette table) as
fault occurs. Another potential fault is when there are more names
than supported.
[0172] If the read grouping is valid, then the tile associated with
the read grouping is configured to use the number of rows and
columns specified by the grouping in a tile configuration at 2211.
The size of the elements in the tile are set by the palette table
entry for the palette ID.
[0173] A determination of if all tiles of the retrieved
configuration have been configured is made at 2213. For example,
have all of the possible tile names been processed? In some
embodiments, when the rows and columns for a particular tile are
both 0, then all tiles have been processed.
[0174] When all tiles have not been configured, at 2215, the tile
number is incremented such that the next tile in the configuration
will be evaluated.
[0175] At 2217, the incremented tile's grouping is read. For
example, the number of rows and columns for tile 1 (T1) is read. A
determination of if the read grouping is valid is made at 2207,
etc.
[0176] When all tiles have been configured, then the instruction
completes at 2209. The tiles will be marked as being in use for
matrix operations, for example, by setting an in-use indicator in a
register.
vi. Exemplary Pseudocode
[0177] FIG. 23 illustrates exemplary pseudocode for an execution of
a TILECONFIG instruction.
[0178] B. Tile Zero
[0179] There are times when a matrix of all zeros is desirable for
a given operation. Detailed herein are embodiments of a matrix
(tile) zeroing ("TILEZERO") instruction and its execution to
generate that matrix. A TILEZERO instruction is an improvement a
computer itself as it provides for support to zero data of a matrix
(tile). In particular, the execution of the TILEZERO instruction
causes all data from a source matrix (tile) to be set to zero.
i. Exemplary Execution
[0180] FIG. 24 illustrates an exemplary execution of a TILEZERO
instruction. The TILEZERO instruction format includes fields for an
opcode and a source/destination matrix (tile) operand (shown as
"SOURCE/DESTINATION MATRIX (TILE)").
[0181] The source/destination matrix (tile) operand field
represents a source matrix (tile) 2401 and an updated version of
the source matrix (tile) as the destination 2407. As detailed
earlier, a matrix may be stored in a collection of registers
(tile), locations in memory, or in other storage accessible to
execution circuitry.
[0182] As shown, execution circuitry 2403 executes a decoded
TILEZERO instruction to zero the source data of the source matrix
(tile) operand 2401 and store that data in the source matrix (tile)
operand as a destination of the instruction 2407.
ii. Exemplary Format(s)
[0183] An embodiment of a format for a TILEZERO instruction is
TILEZERO TMM1. In some embodiments, TILEZERO is the opcode mnemonic
of the instruction. SRC is a field for a source matrix (tile)
operand. In some embodiments, the SRC/DST field is a R/M value
(such as 2746) and in others the field is REG 2744.
[0184] In embodiments, encodings of the instruction include a
scale-index-base (SIB) type memory addressing operand that
indirectly identifies multiple indexed destination locations in
memory (e.g., field 2750). In one embodiment, an SIB type memory
operand may include an encoding identifying a base address
register. The contents of the base address register may represent a
base address in memory from which the addresses of the particular
destination locations in memory are calculated. For example, the
base address may be the address of the first location in a block of
potential destination locations for an extended vector instruction.
In one embodiment, an SIB type memory operand may include an
encoding identifying an index register. Each element of the index
register may specify an index or offset value usable to compute,
from the base address, an address of a respective destination
location within a block of potential destination locations. In one
embodiment, an SIB type memory operand may include an encoding
specifying a scaling factor to be applied to each index value when
computing a respective destination address. For example, if a
scaling factor value of four is encoded in the SIB type memory
operand, each index value obtained from an element of the index
register may be multiplied by four and then added to the base
address to compute a destination address.
[0185] In one embodiment, an SIB type memory operand of the form
vm32{x,y,z} may identify a vector array of memory operands
specified using SIB type memory addressing. In this example, the
array of memory addresses is specified using a common base
register, a constant scaling factor, and a vector index register
containing individual elements, each of which is a 32-bit index
value. The vector index register may be a 128-bit register (e.g.,
XMM) register (vm32x), a 256-bit (e.g., YMM) register (vm32y), or a
512-bit (e.g., ZMM) register (vm32z). In another embodiment, an SIB
type memory operand of the form vm64{x,y,z} may identify a vector
array of memory operands specified using SIB type memory
addressing. In this example, the array of memory addresses is
specified using a common base register, a constant scaling factor,
and a vector index register containing individual elements, each of
which is a 64-bit index value. The vector index register may be a
128-bit register (e.g., XMM) register (vm64x), a 256-bit (e.g.,
YMM) register (vm64y) or a 512-bit (e.g., ZMM) register
(vm64z).
iii. Exemplary Method(s) of Execution
[0186] FIG. 25 illustrates an embodiment of method performed by a
processor to process a TILEZERO instruction.
[0187] At 2501, an instruction is fetched. For example, a TILEZERO
instruction is fetched. The TILEZERO instruction includes fields
for an opcode and a source/destination matrix (tile) operand. In
some embodiments, the instruction is fetched from an instruction
cache. The opcode of the TILEZERO instruction indicates a zeroing
of the data from the source/destination matrix (tile) operand is to
occur.
[0188] The fetched instruction is decoded at 2503. For example, the
fetched TILEZERO instruction is decoded by decode circuitry such as
that detailed herein.
[0189] Data values associated with the source/destination matrix
(tile) operand of the decoded instruction are retrieved at 2505 and
the decoded instruction is scheduled (as needed).
[0190] At 2507, the decoded instruction is executed by execution
circuitry (hardware) such as that detailed herein. For the TILEZERO
instruction, the execution will cause execution circuitry to write
every element position of the source/destination matrix (tile)
operand with a zero. In some embodiments, each row of the
source/destination matrix (tile) operand is set to zero at a time.
In some embodiments, an actual writing of zeroes does not occur,
rather, a status bit for the matrix (tile) is set to indicate that
all of the data is zero.
[0191] In some embodiments, the instruction is committed or retired
at 2509.
iv. Exemplary Pseudocode
[0192] FIG. 26 depicts pseudocode of a method of execution of a
TILEZERO instruction.
v. Examples
[0193] EXAMPLE 1 A processor comprising: decode circuitry to decode
an instruction having fields for an opcode and a source/destination
matrix operand identifier; and execution circuitry to execute the
decoded instruction to zero each data element of the identified
source/destination matrix.
[0194] EXAMPLE 2 The processor of example 1, wherein the execution
circuitry is to zero each row of the source/destination matrix
operand.
[0195] EXAMPLE 3 The processor of any of examples 1-2, wherein the
source/destination matrix operand is a plurality of registers
configured to represent a matrix.
[0196] EXAMPLE 4 The processor of any of examples 1-2, wherein the
execution circuitry to fault upon a determination the
source/destination matrix operand identifier is not configured as a
matrix.
[0197] EXAMPLE 5 The processor of any of examples 1 and 3-5,
wherein the execution circuitry is to set a status bit regarding
the identified source/destination matrix as being zero.
[0198] EXAMPLE 6 A method comprising: decoding an instruction
having fields for an opcode and a source/destination matrix operand
identifier; and executing the decoded instruction to zero each data
element of the identified source/destination matrix.
[0199] EXAMPLE 7 The method of example 6, wherein the zeroing is
done a row of the source/destination matrix operand at a time.
[0200] EXAMPLE 8 The method of any of examples 6-7, wherein the
source/destination matrix operand is a plurality of registers
configured to represent a matrix.
[0201] EXAMPLE 9 The method of any of examples 6-8, further
comprising faulting upon a determination the source/destination
matrix operand identifier is not configured as a matrix.
[0202] EXAMPLE 10 The method of any of examples 6 and 8-9, further
comprising setting a status bit regarding the identified
source/destination matrix as being zero.
[0203] EXAMPLE 11 A non-transitory machine-readable medium storing
an instruction which causes a processor to perform a method, the
method comprising: decoding an instruction having fields for an
opcode and a source/destination matrix operand identifier; and
executing the decoded instruction to zero each data element of the
identified source/destination matrix.
[0204] EXAMPLE 12 The non-transitory machine-readable medium of
example 11, wherein the zeroing is done a row of the
source/destination matrix operand at a time.
[0205] EXAMPLE 13 The non-transitory machine-readable medium of any
of examples 11-12, wherein the source/destination matrix operand is
a plurality of registers configured to represent a matrix.
[0206] EXAMPLE 14 The non-transitory machine-readable medium of any
of examples 11-13, further comprising faulting upon a determination
the source/destination matrix operand identifier is not configured
as a matrix.
[0207] EXAMPLE 15 The non-transitory machine-readable medium of any
of examples 11 and 13-14, further comprising setting a status bit
regarding the identified source/destination matrix as being
zero.
[0208] EXAMPLE 16 A system comprising: a processor; and an
accelerator coupled to the processor, the accelerator including:
decode circuitry to decode an instruction having fields for an
opcode and a source/destination matrix operand identifier; and
execution circuitry to execute the decoded instruction to zero each
data element of the identified source/destination matrix.
[0209] EXAMPLE 17 The system of example 16, wherein the execution
circuitry is to zero each row of the source/destination matrix
operand.
[0210] EXAMPLE 18 The system of any of examples 16-17, wherein the
source/destination matrix operand is a plurality of registers
configured to represent a matrix.
[0211] EXAMPLE 19 The system of any of examples 16-18, wherein the
execution circuitry to fault upon a determination the
source/destination matrix operand identifier is not configured as a
matrix.
[0212] EXAMPLE 20 The system of any of examples 16 and 18-19,
wherein the execution circuitry is to set a status bit regarding
the identified source/destination matrix as being zero.
[0213] V. Detailed Exemplary Systems, Processors, and Emulation
[0214] Detailed herein are examples of hardware, software, etc. to
execute the above described instructions. For example, what is
described below details aspects of instruction execution including
various pipeline stages such as fetch, decode, schedule, execute,
retire, etc.
[0215] An instruction set includes one or more instruction formats.
A given instruction format defines various fields (number of bits,
location of bits) to specify, among other things, the operation to
be performed (opcode) and the operand(s) on which that operation is
to be performed. Some instruction formats are further broken down
though the definition of instruction templates (or subformats). For
example, the instruction templates of a given instruction format
may be defined to have different subsets of the instruction
format's fields (the included fields are typically in the same
order, but at least some have different bit positions because there
are less fields included) and/or defined to have a given field
interpreted differently. Thus, each instruction of an ISA is
expressed using a given instruction format (and, if defined, in a
given one of the instruction templates of that instruction format)
and includes fields for specifying the operation and the operands.
For example, an exemplary ADD instruction has a specific opcode and
an instruction format that includes an opcode field to specify that
opcode and operand fields to select operands (source1/destination
and source2); and an occurrence of this ADD instruction in an
instruction stream will have specific contents in the operand
fields that select specific operands.
[0216] A. Exemplary Instruction Formats
[0217] Embodiments of the instruction(s) described herein may be
embodied in different formats. Additionally, exemplary systems,
architectures, and pipelines are detailed below. Embodiments of the
instruction(s) may be executed on such systems, architectures, and
pipelines, but are not limited to those detailed.
[0218] VEX Instruction Format
[0219] VEX encoding allows instructions to have more than two
operands, and allows SIMD vector registers to be longer than 128
bits. The use of a VEX prefix provides for three-operand (or more)
syntax. For example, previous two-operand instructions performed
operations such as A=A+B, which overwrites a source operand. The
use of a VEX prefix enables operands to perform nondestructive
operations such as A=B+C.
[0220] FIG. 27A illustrates an exemplary instruction format
including a VEX prefix 2702, real opcode field 2730, Mod R/M byte
2740, SIB byte 2750, displacement field 2762, and IMM8 2772. FIG.
27B illustrates which fields from FIG. 27A make up a full opcode
field 2774 and a base operation field 2741. FIG. 27C illustrates
which fields from FIG. 27A make up a register index field 2744.
[0221] VEX Prefix (Bytes 0-2) 2702 is encoded in a three-byte form.
The first byte is the Format Field 2790 (VEX Byte 0, bits [7:0]),
which contains an explicit C4 byte value (the unique value used for
distinguishing the C4 instruction format). The second-third bytes
(VEX Bytes 1-2) include a number of bit fields providing specific
capability. Specifically, REX field 2705 (VEX Byte 1, bits [7-5])
consists of a VEX.R bit field (VEX Byte 1, bit [7]--R), VEX.X bit
field (VEX byte 1, bit [6]--X), and VEX.B bit field (VEX byte 1,
bit[5]--B). Other fields of the instructions encode the lower three
bits of the register indexes as is known in the art (rrr, xxx, and
bbb), so that Rrrr, Xxxx, and Bbbb may be formed by adding VEX.R,
VEX.X, and VEX.B. Opcode map field 2715 (VEX byte 1, bits
[4:0]--mmmmm) includes content to encode an implied leading opcode
byte. W Field 2764 (VEX byte 2, bit [7]-- W)--is represented by the
notation VEX.W, and provides different functions depending on the
instruction. The role of VEX.vvvv 2720 (VEX Byte 2, bits
[6:3]--vvvv) may include the following: 1) VEX.vvvv encodes the
first source register operand, specified in inverted (1s
complement) form and is valid for instructions with 2 or more
source operands; 2) VEX.vvvv encodes the destination register
operand, specified in 1s complement form for certain vector shifts;
or 3) VEX.vvvv does not encode any operand, the field is reserved
and should contain 1111b. If VEX.L 2768 Size field (VEX byte 2, bit
[2]-L)=0, it indicates 128 bit vector; if VEX.L=1, it indicates 256
bit vector. Prefix encoding field 2725 (VEX byte 2, bits [1:0]-pp)
provides additional bits for the base operation field 2741.
[0222] Real Opcode Field 2730 (Byte 3) is also known as the opcode
byte. Part of the opcode is specified in this field.
[0223] MOD R/M Field 2740 (Byte 4) includes MOD field 2742 (bits
[7-6]), Reg field 2744 (bits [5-3]), and R/M field 2746 (bits
[2-0]). The role of Reg field 2744 may include the following:
encoding either the destination register operand or a source
register operand (the rrr of Rrrr), or be treated as an opcode
extension and not used to encode any instruction operand. The role
of R/M field 2746 may include the following: encoding the
instruction operand that references a memory address, or encoding
either the destination register operand or a source register
operand.
[0224] Scale, Index, Base (SIB)--The content of Scale field 2750
(Byte 5) includes SS2752 (bits [7-6]), which is used for memory
address generation. The contents of SIB.xxx 2754 (bits [5-3]) and
SIB.bbb 2756 (bits [2-0]) have been previously referred to with
regard to the register indexes Xxxx and Bbbb.
[0225] The Displacement Field 2762 and the immediate field (IMM8)
2772 contain data.
[0226] B. Exemplary Register Architecture
[0227] FIG. 28 is a block diagram of a register architecture 2800
according to one embodiment of the invention. In the embodiment
illustrated, there are 32 vector registers 2810 that are 512 bits
wide; these registers are referenced as zmm0 through zmm31. The
lower order 256 bits of the lower 31 zmm registers are overlaid on
registers ymm0-15. The lower order 128 bits of the lower 31 zmm
registers (the lower order 128 bits of the ymm registers) are
overlaid on registers xmm0-15.
[0228] General-purpose registers 2825--in the embodiment
illustrated, there are sixteen 64-bit general-purpose registers
that are used along with the existing x86 addressing modes to
address memory operands. These registers are referenced by the
names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through
R15.
[0229] Scalar floating point stack register file (x87 stack) 2845,
on which is aliased the MMX packed integer flat register file
2850--in the embodiment illustrated, the x87 stack is an
eight-element stack used to perform scalar floating-point
operations on 32/64/80-bit floating point data using the x87
instruction set extension; while the MMX registers are used to
perform operations on 64-bit packed integer data, as well as to
hold operands for some operations performed between the MMX and XMM
registers.
[0230] In some embodiments, tiles 2820 are supported using an
overlay over physical registers. For example, a tile may utilize 16
1,024-bit registers, 32 512-bit registers, etc. depending on the
implementation.
[0231] Alternative embodiments of the invention may use wider or
narrower registers. Additionally, alternative embodiments of the
invention may use more, less, or different register files and
registers.
[0232] Exemplary Core Architectures, Processors, and Computer
Architectures
[0233] Processor cores may be implemented in different ways, for
different purposes, and in different processors. For instance,
implementations of such cores may include: 1) a general purpose
in-order core intended for general-purpose computing; 2) a high
performance general purpose out-of-order core intended for
general-purpose computing; 3) a special purpose core intended
primarily for graphics and/or scientific (throughput) computing.
Implementations of different processors may include: 1) a CPU
including one or more general purpose in-order cores intended for
general-purpose computing and/or one or more general purpose
out-of-order cores intended for general-purpose computing; and 2) a
coprocessor including one or more special purpose cores intended
primarily for graphics and/or scientific (throughput). Such
different processors lead to different computer system
architectures, which may include: 1) the coprocessor on a separate
chip from the CPU; 2) the coprocessor on a separate die in the same
package as a CPU; 3) the coprocessor on the same die as a CPU (in
which case, such a coprocessor is sometimes referred to as special
purpose logic, such as integrated graphics and/or scientific
(throughput) logic, or as special purpose cores); and 4) a system
on a chip that may include on the same die the described CPU
(sometimes referred to as the application core(s) or application
processor(s)), the above described coprocessor, and additional
functionality. Exemplary core architectures are described next,
followed by descriptions of exemplary processors and computer
architectures. Detailed herein are circuits (units) that comprise
exemplary cores, processors, etc.
[0234] C. Exemplary Core Architectures
[0235] In-order and out-of-order core block diagram
[0236] FIG. 29A is a block diagram illustrating both an exemplary
in-order pipeline and an exemplary register renaming, out-of-order
issue/execution pipeline according to embodiments of the invention.
FIG. 29B is a block diagram illustrating both an exemplary
embodiment of an in-order architecture core and an exemplary
register renaming, out-of-order issue/execution architecture core
to be included in a processor according to embodiments of the
invention. The solid lined boxes in FIGS. 29A-B illustrate the
in-order pipeline and in-order core, while the optional addition of
the dashed lined boxes illustrates the register renaming,
out-of-order issue/execution pipeline and core. Given that the
in-order aspect is a subset of the out-of-order aspect, the
out-of-order aspect will be described.
[0237] In FIG. 29A, a processor pipeline 2900 includes a fetch
stage 2902, a length decode stage 2904, a decode stage 2906, an
allocation stage 2908, a renaming stage 2910, a scheduling (also
known as a dispatch or issue) stage 2912, a register read/memory
read stage 2914, an execute stage 2916, a write back/memory write
stage 2918, an exception handling stage 2922, and a commit stage
2924.
[0238] FIG. 29B shows processor core 2990 including a front end
unit 2930 coupled to an execution engine unit 2950, and both are
coupled to a memory unit 2970. The core 2990 may be a reduced
instruction set computing (RISC) core, a complex instruction set
computing (CISC) core, a very long instruction word (VLIW) core, or
a hybrid or alternative core type. As yet another option, the core
2990 may be a special-purpose core, such as, for example, a network
or communication core, compression engine, coprocessor core,
general purpose computing graphics processing unit (GPGPU) core,
graphics core, or the like.
[0239] The front end unit 2930 includes a branch prediction unit
2932 coupled to an instruction cache unit 2934, which is coupled to
an instruction translation lookaside buffer (TLB) 2936, which is
coupled to an instruction fetch unit 2938, which is coupled to a
decode unit 2940. The decode unit 2940 (or decoder) may decode
instructions, and generate as an output one or more
micro-operations, micro-code entry points, microinstructions, other
instructions, or other control signals, which are decoded from, or
which otherwise reflect, or are derived from, the original
instructions. The decode unit 2940 may be implemented using various
different mechanisms. Examples of suitable mechanisms include, but
are not limited to, look-up tables, hardware implementations,
programmable logic arrays (PLAs), microcode read only memories
(ROMs), etc. In one embodiment, the core 2990 includes a microcode
ROM or other medium that stores microcode for certain
macroinstructions (e.g., in decode unit 2940 or otherwise within
the front end unit 2930). The decode unit 2940 is coupled to a
rename/allocator unit 2952 in the execution engine unit 2950.
[0240] The execution engine unit 2950 includes the rename/allocator
unit 2952 coupled to a retirement unit 2954 and a set of one or
more scheduler unit(s) 2956. The scheduler unit(s) 2956 represents
any number of different schedulers, including reservations
stations, central instruction window, etc. The scheduler unit(s)
2956 is coupled to the physical register file(s) unit(s) 2958. Each
of the physical register file(s) units 2958 represents one or more
physical register files, different ones of which store one or more
different data types, such as scalar integer, scalar floating
point, packed integer, packed floating point, vector integer,
vector floating point, status (e.g., an instruction pointer that is
the address of the next instruction to be executed), etc. In one
embodiment, the physical register file(s) unit 2958 comprises a
vector registers unit and a scalar registers unit. These register
units may provide architectural vector registers, vector mask
registers, and general purpose registers. The physical register
file(s) unit(s) 2958 is overlapped by the retirement unit 2954 to
illustrate various ways in which register renaming and out-of-order
execution may be implemented (e.g., using a reorder buffer(s) and a
retirement register file(s); using a future file(s), a history
buffer(s), and a retirement register file(s); using a register maps
and a pool of registers; etc.). The retirement unit 2954 and the
physical register file(s) unit(s) 2958 are coupled to the execution
cluster(s) 2960. The execution cluster(s) 2960 includes a set of
one or more execution units 2962 and a set of one or more memory
access units 2964. The execution units 2962 may perform various
operations (e.g., shifts, addition, subtraction, multiplication)
and on various types of data (e.g., scalar floating point, packed
integer, packed floating point, vector integer, vector floating
point). While some embodiments may include a number of execution
units dedicated to specific functions or sets of functions, other
embodiments may include only one execution unit or multiple
execution units that all perform all functions. The scheduler
unit(s) 2956, physical register file(s) unit(s) 2958, and execution
cluster(s) 2960 are shown as being possibly plural because certain
embodiments create separate pipelines for certain types of
data/operations (e.g., a scalar integer pipeline, a scalar floating
point/packed integer/packed floating point/vector integer/vector
floating point pipeline, and/or a memory access pipeline that each
have their own scheduler unit, physical register file(s) unit,
and/or execution cluster--and in the case of a separate memory
access pipeline, certain embodiments are implemented in which only
the execution cluster of this pipeline has the memory access
unit(s) 2964). It should also be understood that where separate
pipelines are used, one or more of these pipelines may be
out-of-order issue/execution and the rest in-order.
[0241] The set of memory access units 2964 is coupled to the memory
unit 2970, which includes a data TLB unit 2972 coupled to a data
cache unit 2974 coupled to a level 2 (L2) cache unit 2976. In one
exemplary embodiment, the memory access units 2964 may include a
load unit, a store address unit, and a store data unit, each of
which is coupled to the data TLB unit 2972 in the memory unit 2970.
The instruction cache unit 2934 is further coupled to a level 2
(L2) cache unit 2976 in the memory unit 2970. The L2 cache unit
2976 is coupled to one or more other levels of cache and eventually
to a main memory.
[0242] By way of example, the exemplary register renaming,
out-of-order issue/execution core architecture may implement the
pipeline 2900 as follows: 1) the instruction fetch 2938 performs
the fetch and length decoding stages 2902 and 2904; 2) the decode
unit 2940 performs the decode stage 2906; 3) the rename/allocator
unit 2952 performs the allocation stage 2908 and renaming stage
2910; 4) the scheduler unit(s) 2956 performs the schedule stage
2912; 5) the physical register file(s) unit(s) 2958 and the memory
unit 2970 perform the register read/memory read stage 2914; the
execution cluster 2960 perform the execute stage 2916; 6) the
memory unit 2970 and the physical register file(s) unit(s) 2958
perform the write back/memory write stage 2918; 7) various units
may be involved in the exception handling stage 2922; and 8) the
retirement unit 2954 and the physical register file(s) unit(s) 2958
perform the commit stage 2924.
[0243] The core 2990 may support one or more instructions sets
(e.g., the x86 instruction set (with some extensions that have been
added with newer versions); the MIPS instruction set of MIPS
Technologies of Sunnyvale, Calif.; the ARM instruction set (with
optional additional extensions such as NEON) of ARM Holdings of
Sunnyvale, Calif.), including the instruction(s) described herein.
In one embodiment, the core 2990 includes logic to support a packed
data instruction set extension (e.g., AVX1, AVX2), thereby allowing
the operations used by many multimedia applications to be performed
using packed data.
[0244] It should be understood that the core may support
multithreading (executing two or more parallel sets of operations
or threads), and may do so in a variety of ways including time
sliced multithreading, simultaneous multithreading (where a single
physical core provides a logical core for each of the threads that
physical core is simultaneously multithreading), or a combination
thereof (e.g., time sliced fetching and decoding and simultaneous
multithreading thereafter such as in the Intel.RTM. Hyperthreading
technology).
[0245] While register renaming is described in the context of
out-of-order execution, it should be understood that register
renaming may be used in an in-order architecture. While the
illustrated embodiment of the processor also includes separate
instruction and data cache units 2934/2974 and a shared L2 cache
unit 2976, alternative embodiments may have a single internal cache
for both instructions and data, such as, for example, a Level 1
(L1) internal cache, or multiple levels of internal cache. In some
embodiments, the system may include a combination of an internal
cache and an external cache that is external to the core and/or the
processor. Alternatively, all of the cache may be external to the
core and/or the processor.
[0246] Specific Exemplary In-Order Core Architecture
[0247] FIGS. 30A-B illustrate a block diagram of a more specific
exemplary in-order core architecture, which core would be one of
several logic blocks (including other cores of the same type and/or
different types) in a chip. The logic blocks communicate through a
high-bandwidth interconnect network (e.g., a ring network) with
some fixed function logic, memory I/O interfaces, and other
necessary I/O logic, depending on the application.
[0248] FIG. 30A is a block diagram of a single processor core,
along with its connection to the on-die interconnect network 3002
and with its local subset of the Level 2 (L2) cache 3004, according
to embodiments of the invention. In one embodiment, an instruction
decoder 3000 supports the x86 instruction set with a packed data
instruction set extension. An L1 cache 3006 allows low-latency
accesses to cache memory into the scalar and vector units. While in
one embodiment (to simplify the design), a scalar unit 3008 and a
vector unit 3010 use separate register sets (respectively, scalar
registers 3012 and vector registers 3014) and data transferred
between them is written to memory and then read back in from a
level 1 (L1) cache 3006, alternative embodiments of the invention
may use a different approach (e.g., use a single register set or
include a communication path that allow data to be transferred
between the two register files without being written and read
back).
[0249] The local subset of the L2 cache 3004 is part of a global L2
cache that is divided into separate local subsets, one per
processor core. Each processor core has a direct access path to its
own local subset of the L2 cache 3004. Data read by a processor
core is stored in its L2 cache subset 3004 and can be accessed
quickly, in parallel with other processor cores accessing their own
local L2 cache subsets. Data written by a processor core is stored
in its own L2 cache subset 3004 and is flushed from other subsets,
if necessary. The ring network ensures coherency for shared data.
The ring network is bi-directional to allow agents such as
processor cores, L2 caches and other logic blocks to communicate
with each other within the chip. Each ring data-path is 1024-bits
wide per direction in some embodiments.
[0250] FIG. 30B is an expanded view of part of the processor core
in FIG. 30A according to embodiments of the invention. FIG. 30B
includes an L1 data cache 3006A part of the L1 cache 3004, as well
as more detail regarding the vector unit 3010 and the vector
registers 3014. Specifically, the vector unit 3010 is a 31-wide
vector processing unit (VPU) (see the 16-wide ALU 3028), which
executes one or more of integer, single-precision float, and
double-precision float instructions. The VPU supports swizzling the
register inputs with swizzle unit 3020, numeric conversion with
numeric convert units 3022A-B, and replication with replication
unit 3024 on the memory input.
[0251] Processor with integrated memory controller and graphics
[0252] FIG. 31 is a block diagram of a processor 3100 that may have
more than one core, may have an integrated memory controller, and
may have integrated graphics according to embodiments of the
invention. The solid lined boxes in FIG. 31 illustrate a processor
3100 with a single core 3102A, a system agent 3110, a set of one or
more bus controller units 3116, while the optional addition of the
dashed lined boxes illustrates an alternative processor 3100 with
multiple cores 3102A-N, a set of one or more integrated memory
controller unit(s) 3114 in the system agent unit 3110, and special
purpose logic 3108.
[0253] Thus, different implementations of the processor 3100 may
include: 1) a CPU with the special purpose logic 3108 being
integrated graphics and/or scientific (throughput) logic (which may
include one or more cores), and the cores 3102A-N being one or more
general purpose cores (e.g., general purpose in-order cores,
general purpose out-of-order cores, a combination of the two); 2) a
coprocessor with the cores 3102A-N being a large number of special
purpose cores intended primarily for graphics and/or scientific
(throughput); and 3) a coprocessor with the cores 3102A-N being a
large number of general purpose in-order cores. Thus, the processor
3100 may be a general-purpose processor, coprocessor or
special-purpose processor, such as, for example, a network or
communication processor, compression engine, graphics processor,
GPGPU (general purpose graphics processing unit), a high-throughput
many integrated core (MIC) coprocessor (including 30 or more
cores), embedded processor, or the like. The processor may be
implemented on one or more chips. The processor 3100 may be a part
of and/or may be implemented on one or more substrates using any of
a number of process technologies, such as, for example, BiCMOS,
CMOS, or NMOS.
[0254] The memory hierarchy includes one or more levels of cache
within the cores 3104A-N, a set or one or more shared cache units
3106, and external memory (not shown) coupled to the set of
integrated memory controller units 3114. The set of shared cache
units 3106 may include one or more mid-level caches, such as level
2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a
last level cache (LLC), and/or combinations thereof. While in one
embodiment a ring based interconnect unit 3112 interconnects the
integrated graphics logic 3108, the set of shared cache units 3106,
and the system agent unit 3110/integrated memory controller unit(s)
3114, alternative embodiments may use any number of well-known
techniques for interconnecting such units. In one embodiment,
coherency is maintained between one or more cache units 3106 and
cores 3102-A-N.
[0255] In some embodiments, one or more of the cores 3102A-N are
capable of multi-threading. The system agent 3110 includes those
components coordinating and operating cores 3102A-N. The system
agent unit 3110 may include for example a power control unit (PCU)
and a display unit. The PCU may be or include logic and components
needed for regulating the power state of the cores 3102A-N and the
integrated graphics logic 3108. The display unit is for driving one
or more externally connected displays.
[0256] The cores 3102A-N may be homogenous or heterogeneous in
terms of architecture instruction set; that is, two or more of the
cores 3102A-N may be capable of execution the same instruction set,
while others may be capable of executing only a subset of that
instruction set or a different instruction set.
[0257] D. Exemplary Computer Architectures
[0258] FIGS. 32-35 are block diagrams of exemplary computer
architectures. Other system designs and configurations known in the
arts for laptops, desktops, handheld PCs, personal digital
assistants, engineering workstations, servers, network devices,
network hubs, switches, embedded processors, digital signal
processors (DSPs), graphics devices, video game devices, set-top
boxes, micro controllers, cell phones, portable media players, hand
held devices, and various other electronic devices, are also
suitable. In general, a huge variety of systems or electronic
devices capable of incorporating a processor and/or other execution
logic as disclosed herein are generally suitable.
[0259] Referring now to FIG. 32, shown is a block diagram of a
system 3200 in accordance with one embodiment of the present
invention. The system 3200 may include one or more processors 3210,
3215, which are coupled to a controller hub 3220. In one
embodiment, the controller hub 3220 includes a graphics memory
controller hub (GMCH) 3290 and an Input/Output Hub (IOH) 3250
(which may be on separate chips); the GMCH 3290 includes memory and
graphics controllers to which are coupled memory 3240 and a
coprocessor 3245; the IOH 3250 is couples input/output (I/O)
devices 3260 to the GMCH 3290. Alternatively, one or both of the
memory and graphics controllers are integrated within the processor
(as described herein), the memory 3240 and the coprocessor 3245 are
coupled directly to the processor 3210, and the controller hub 3220
in a single chip with the IOH 3250.
[0260] The optional nature of additional processors 3215 is denoted
in FIG. 32 with broken lines. Each processor 3210, 3215 may include
one or more of the processing cores described herein and may be
some version of the processor 3100.
[0261] The memory 3240 may be, for example, dynamic random access
memory (DRAM), phase change memory (PCM), or a combination of the
two. For at least one embodiment, the controller hub 3220
communicates with the processor(s) 3210, 3215 via a multi-drop bus,
such as a frontside bus (FSB), point-to-point interface, or similar
connection 3295.
[0262] In one embodiment, the coprocessor 3245 is a special-purpose
processor, such as, for example, a high-throughput MIC processor, a
network or communication processor, compression engine, graphics
processor, GPGPU, embedded processor, or the like. In one
embodiment, controller hub 3220 may include an integrated graphics
accelerator.
[0263] There can be a variety of differences between the physical
resources 3210, 32155 in terms of a spectrum of metrics of merit
including architectural, microarchitectural, thermal, power
consumption characteristics, and the like.
[0264] In one embodiment, the processor 3210 executes instructions
that control data processing operations of a general type. Embedded
within the instructions may be coprocessor instructions. The
processor 3210 recognizes these coprocessor instructions as being
of a type that should be executed by the attached coprocessor 3245.
Accordingly, the processor 3210 issues these coprocessor
instructions (or control signals representing coprocessor
instructions) on a coprocessor bus or other interconnect, to
coprocessor 3245. Coprocessor(s) 3245 accept and execute the
received coprocessor instructions.
[0265] Referring now to FIG. 33, shown is a block diagram of a
first more specific exemplary system 3300 in accordance with an
embodiment of the present invention. As shown in FIG. 33,
multiprocessor system 3300 is a point-to-point interconnect system,
and includes a first processor 3370 and a second processor 3380
coupled via a point-to-point interconnect 3350. Each of processors
3370 and 3380 may be some version of the processor 3100. In one
embodiment of the invention, processors 3370 and 3380 are
respectively processors 3210 and 3215, while coprocessor 3338 is
coprocessor 3245. In another embodiment, processors 3370 and 3380
are respectively processor 3210 coprocessor 3245.
[0266] Processors 3370 and 3380 are shown including integrated
memory controller (IMC) units 3372 and 3382, respectively.
Processor 3370 also includes as part of its bus controller units
point-to-point (P-P) interfaces 3376 and 3378; similarly, second
processor 3380 includes P-P interfaces 3386 and 3388. Processors
3370, 3380 may exchange information via a point-to-point (P-P)
interface 3350 using P-P interface circuits 3378, 3388. As shown in
FIG. 33, IMCs 3372 and 3382 couple the processors to respective
memories, namely a memory 3332 and a memory 3334, which may be
portions of main memory locally attached to the respective
processors.
[0267] Processors 3370, 3380 may each exchange information with a
chipset 3390 via individual P-P interfaces 3352, 3354 using point
to point interface circuits 3376, 3394, 3386, 3398. Chipset 3390
may optionally exchange information with the coprocessor 3338 via a
high-performance interface 3392. In one embodiment, the coprocessor
3338 is a special-purpose processor, such as, for example, a
high-throughput MIC processor, a network or communication
processor, compression engine, graphics processor, GPGPU, embedded
processor, or the like.
[0268] A shared cache (not shown) may be included in either
processor or outside of both processors, yet connected with the
processors via P-P interconnect, such that either or both
processors' local cache information may be stored in the shared
cache if a processor is placed into a low power mode.
[0269] Chipset 3390 may be coupled to a first bus 3316 via an
interface 3396. In one embodiment, first bus 3316 may be a
Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI
Express bus or another I/O interconnect bus, although the scope of
the present invention is not so limited.
[0270] As shown in FIG. 33, various I/O devices 3314 may be coupled
to first bus 3316, along with a bus bridge 3318 which couples first
bus 3316 to a second bus 3320. In one embodiment, one or more
additional processor(s) 3315, such as coprocessors, high-throughput
MIC processors, GPGPU's, accelerators (such as, e.g., graphics
accelerators or digital signal processing (DSP) units), field
programmable gate arrays, or any other processor, are coupled to
first bus 3316. In one embodiment, second bus 3320 may be a low pin
count (LPC) bus. Various devices may be coupled to a second bus
3320 including, for example, a keyboard and/or mouse 3322,
communication devices 3327 and a storage unit 3328 such as a disk
drive or other mass storage device which may include
instructions/code and data 3330, in one embodiment. Further, an
audio I/O 3324 may be coupled to the second bus 3316. Note that
other architectures are possible. For example, instead of the
point-to-point architecture of FIG. 33, a system may implement a
multi-drop bus or other such architecture.
[0271] Referring now to FIG. 34, shown is a block diagram of a
second more specific exemplary system 3400 in accordance with an
embodiment of the present invention. Like elements in FIGS. 33 and
34 bear like reference numerals, and certain aspects of FIG. 33
have been omitted from FIG. 34 in order to avoid obscuring other
aspects of FIG. 34.
[0272] FIG. 34 illustrates that the processors 3370, 3380 may
include integrated memory and I/O control logic ("CL") 3472 and
3482, respectively. Thus, the CL 3472, 3482 include integrated
memory controller units and include I/O control logic. FIG. 34
illustrates that not only are the memories 3332, 3334 coupled to
the CL 3472, 3482, but also that I/O devices 3414 are also coupled
to the control logic 3372, 3382. Legacy I/O devices 3415 are
coupled to the chipset 3390.
[0273] Referring now to FIG. 35, shown is a block diagram of a SoC
3500 in accordance with an embodiment of the present invention.
Similar elements in FIG. 31 bear like reference numerals. Also,
dashed lined boxes are optional features on more advanced SoCs. In
FIG. 35, an interconnect unit(s) 3502 is coupled to: an application
processor 3510 which includes a set of one or more cores 352A-N,
cache units 3104A-N, and shared cache unit(s) 3106; a system agent
unit 3110; a bus controller unit(s) 3116; an integrated memory
controller unit(s) 3114; a set or one or more coprocessors 3520
which may include integrated graphics logic, an image processor, an
audio processor, and a video processor; an static random access
memory (SRAM) unit 3530; a direct memory access (DMA) unit 3532;
and a display unit 3540 for coupling to one or more external
displays. In one embodiment, the coprocessor(s) 3520 include a
special-purpose processor, such as, for example, a network or
communication processor, compression engine, GPGPU, a
high-throughput MIC processor, embedded processor, or the like.
[0274] Embodiments of the mechanisms disclosed herein may be
implemented in hardware, software, firmware, or a combination of
such implementation approaches. Embodiments of the invention may be
implemented as computer programs or program code executing on
programmable systems comprising at least one processor, a storage
system (including volatile and non-volatile memory and/or storage
elements), at least one input device, and at least one output
device.
[0275] Program code, such as code 3330 illustrated in FIG. 33, may
be applied to input instructions to perform the functions described
herein and generate output information. The output information may
be applied to one or more output devices, in known fashion. For
purposes of this application, a processing system includes any
system that has a processor, such as, for example; a digital signal
processor (DSP), a microcontroller, an application specific
integrated circuit (ASIC), or a microprocessor.
[0276] The program code may be implemented in a high level
procedural or object oriented programming language to communicate
with a processing system. The program code may also be implemented
in assembly or machine language, if desired. In fact, the
mechanisms described herein are not limited in scope to any
particular programming language. In any case, the language may be a
compiled or interpreted language.
[0277] One or more aspects of at least one embodiment may be
implemented by representative instructions stored on a
machine-readable medium which represents various logic within the
processor, which when read by a machine causes the machine to
fabricate logic to perform the techniques described herein. Such
representations, known as "IP cores" may be stored on a tangible,
machine readable medium and supplied to various customers or
manufacturing facilities to load into the fabrication machines that
actually make the logic or processor.
[0278] Such machine-readable storage media may include, without
limitation, non-transitory, tangible arrangements of articles
manufactured or formed by a machine or device, including storage
media such as hard disks, any other type of disk including floppy
disks, optical disks, compact disk read-only memories (CD-ROMs),
compact disk rewritable's (CD-RWs), and magneto-optical disks,
semiconductor devices such as read-only memories (ROMs), random
access memories (RAMs) such as dynamic random access memories
(DRAMs), static random access memories (SRAMs), erasable
programmable read-only memories (EPROMs), flash memories,
electrically erasable programmable read-only memories (EEPROMs),
phase change memory (PCM), magnetic or optical cards, or any other
type of media suitable for storing electronic instructions.
[0279] Accordingly, embodiments of the invention also include
non-transitory, tangible machine-readable media containing
instructions or containing design data, such as Hardware
Description Language (HDL), which defines structures, circuits,
apparatuses, processors and/or system features described herein.
Such embodiments may also be referred to as program products.
[0280] E. Emulation (including binary translation, code morphing,
etc.)
[0281] In some cases, an instruction converter may be used to
convert an instruction from a source instruction set to a target
instruction set. For example, the instruction converter may
translate (e.g., using static binary translation, dynamic binary
translation including dynamic compilation), morph, emulate, or
otherwise convert an instruction to one or more other instructions
to be processed by the core. The instruction converter may be
implemented in software, hardware, firmware, or a combination
thereof. The instruction converter may be on processor, off
processor, or part on and part off processor.
[0282] FIG. 36 is a block diagram contrasting the use of a software
instruction converter to convert binary instructions in a source
instruction set to binary instructions in a target instruction set
according to embodiments of the invention. In the illustrated
embodiment, the instruction converter is a software instruction
converter, although alternatively the instruction converter may be
implemented in software, firmware, hardware, or various
combinations thereof. FIG. 36 shows a program in a high level
language 3602 may be compiled using an first compiler 3604 to
generate a first binary code (e.g., x86) 3606 that may be natively
executed by a processor with at least one first instruction set
core 3616. In some embodiments, the processor with at least one
first instruction set core 3616 represents any processor that can
perform substantially the same functions as an Intel processor with
at least one x86 instruction set core by compatibly executing or
otherwise processing (1) a substantial portion of the instruction
set of the Intel x86 instruction set core or (2) object code
versions of applications or other software targeted to run on an
Intel processor with at least one x86 instruction set core, in
order to achieve substantially the same result as an Intel
processor with at least one x86 instruction set core. The first
compiler 3604 represents a compiler that is operable to generate
binary code of the first instruction set 3606 (e.g., object code)
that can, with or without additional linkage processing, be
executed on the processor with at least one first instruction set
core 3616. Similarly, FIG. 36 shows the program in the high level
language 3602 may be compiled using an alternative instruction set
compiler 3608 to generate alternative instruction set binary code
3610 that may be natively executed by a processor without at least
one first instruction set core 3614 (e.g., a processor with cores
that execute the MIPS instruction set of MIPS Technologies of
Sunnyvale, Calif. and/or that execute the ARM instruction set of
ARM Holdings of Sunnyvale, Calif.). The instruction converter 3612
is used to convert the first binary code 3606 into code that may be
natively executed by the processor without an first instruction set
core 3614. This converted code is not likely to be the same as the
alternative instruction set binary code 3610 because an instruction
converter capable of this is difficult to make; however, the
converted code will accomplish the general operation and be made up
of instructions from the alternative instruction set. Thus, the
instruction converter 3612 represents software, firmware, hardware,
or a combination thereof that, through emulation, simulation or any
other process, allows a processor or other electronic device that
does not have a first instruction set processor or core to execute
the first binary code 3606.
* * * * *