U.S. patent application number 17/578125 was filed with the patent office on 2022-09-08 for method and apparatus for efficient loop processing in a graphics hardware front end.
The applicant listed for this patent is Intel Corporation. Invention is credited to Michael APODACA, Peter DOYLE, Hema Chand NALLURI, Balaji VEMBU.
Application Number | 20220284539 17/578125 |
Document ID | / |
Family ID | 1000006351385 |
Filed Date | 2022-09-08 |
United States Patent
Application |
20220284539 |
Kind Code |
A1 |
NALLURI; Hema Chand ; et
al. |
September 8, 2022 |
METHOD AND APPARATUS FOR EFFICIENT LOOP PROCESSING IN A GRAPHICS
HARDWARE FRONT END
Abstract
Various embodiments enable loop processing in a command
processing block of the graphics hardware. Such hardware may
include a processor including a command buffer, and a graphics
command parser. The graphics command parser to load graphics
commands from the command buffer, parse a first graphics command,
store a loop count value associated with the first graphics
command, parse a second graphics command and store a loop wrap
address based on the second graphics command. The graphics command
parser may execute a command sequence identified by the second
graphics command, parse a third graphics command, the third
graphics command identifying an end of the command sequence, set a
new loop count value, and iteratively execute the command sequence
using the loop wrap address based on the new loop count value.
Inventors: |
NALLURI; Hema Chand;
(Hyderabad, IN) ; VEMBU; Balaji; (Folsom, CA)
; DOYLE; Peter; (El Dorado Hills, CA) ; APODACA;
Michael; (Folsom, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Intel Corporation |
Santa Clara |
CA |
US |
|
|
Family ID: |
1000006351385 |
Appl. No.: |
17/578125 |
Filed: |
January 18, 2022 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
15690201 |
Aug 29, 2017 |
11232531 |
|
|
17578125 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06T 2200/28 20130101;
G06T 15/005 20130101; G06T 1/20 20130101 |
International
Class: |
G06T 1/20 20060101
G06T001/20; G06T 15/00 20060101 G06T015/00 |
Claims
1. (canceled)
2. An apparatus comprising: a memory; and a graphics processing
unit to execution graphics commands loaded from the memory, the
execution comprising: parsing a first graphics command from the
graphics commands, the first graphics command identifying a loop
wrap address; executing a command sequence based on the first
graphics command; parsing a second graphics command, the second
graphics command identifying an end of the command sequence;
setting a loop count value upon the second graphics command being
parsed; iteratively executing the command sequence using the loop
wrap address based on the loop count value.
3. The apparatus of claim 2, wherein the loop wrap address is to be
stored in a hardware stack.
4. The apparatus of claim 3, wherein the loop count value is stored
in the hardware stack.
5. The apparatus of claim 3, wherein one or more entries including
the loop wrap address and loop count value in the hardware stack
are cached in an on-die storage of the apparatus.
6. The apparatus of claim 3, wherein the command sequence includes
at least one nested loop, and wherein the hardware stack stores
another loop wrap address for the at least one nested loop.
7. The apparatus of claim 6, wherein the another loop wrap address
for the at least one nested loop is stored in an entry on top of an
corresponding entry for the loop wrap address in the hardware
stack.
8. The apparatus of claim 2, wherein the loop count value prior to
the second graphics command being parsed is stored in the memory,
and wherein the stored loop count value is based on parsing another
graphics command loaded from the memory prior to parsing the first
graphics command.
9. The apparatus of claim 8, wherein setting the loop count value
comprises decrementing the stored loop count value.
10. The apparatus of claim 2, wherein at least one command in the
command sequence includes indirect data, and wherein the indirect
data for the at least one command is determined based on a loop
variable.
11. A method comprising: loading graphics commands from a memory of
an apparatus; executing the graphics commands loaded from the
memory, the execution comprising: parsing a first graphics command
from the graphics commands, the first graphics command identifying
a loop wrap address; executing a command sequence based on the
first graphics command; parsing a second graphics command, the
second graphics command identifying an end of the command sequence;
setting a loop count value upon the second graphics command being
parsed; iteratively executing the command sequence using the loop
wrap address based on the loop count value.
12. The method of claim 11, wherein the loop wrap address is to be
stored in a hardware stack.
13. The method of claim 12, wherein the loop count value is stored
in the hardware stack.
14. The method of claim 12, wherein one or more entries including
the loop wrap address and loop count value in the hardware stack
are cached in an on-die storage of the apparatus.
15. The method of claim 12, wherein the command sequence includes
at least one nested loop, and wherein the hardware stack stores
another loop wrap address for the at least one nested loop.
16. The method of claim 15, wherein the another loop wrap address
for the at least one nested loop is stored in an entry on top of an
corresponding entry for the loop wrap address in the hardware
stack.
17. The method of claim 12, wherein the loop count value prior to
the second graphics command being parsed is stored in the memory,
and wherein the stored loop count value is based on parsing another
graphics command loaded from the memory prior to parsing the first
graphics command.
18. The method of claim 12, wherein at least one command in the
command sequence includes indirect data, and wherein the indirect
data for the at least one command is determined based on a loop
variable.
19. A non-transitory machine-readable storage medium storing
instructions, which when executed by a machine, are capable of
causing the machine to perform: loading graphics commands from a
memory of an apparatus; executing the graphics commands loaded from
the memory, the execution comprising: parsing a first graphics
command from the graphics commands, the first graphics command
identifying a loop wrap address; executing a command sequence based
on the first graphics command; parsing a second graphics command,
the second graphics command identifying an end of the command
sequence; setting a loop count value upon the second graphics
command being parsed; iteratively executing the command sequence
using the loop wrap address based on the loop count value.
20. The non-transitory machine-readable storage medium of claim 19,
wherein the loop wrap address is to be stored in a hardware
stack.
21. The non-transitory machine-readable storage medium of claim 20,
wherein the loop count value is stored in the hardware stack.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of application Ser. No.
15/690,201, filed Aug. 29, 2017, which is hereby incorporated by
reference.
TECHNICAL FIELD
[0002] This invention relates generally to the field of graphics
processors. More particularly, the invention relates to an
apparatus and method for efficient loop processing in a graphics
hardware front end.
BACKGROUND ART
[0003] Graphics processors are increasingly used to execute general
purpose instructions. However, typical graphics engine command
processors (e.g., command streamers in the hardware front end) do
not provide sufficient control flow or modification of graphics
processing data on the fly. As a result, certain compute or control
flows have to be offloaded to graphics software executed by a CPU,
before the workload can be dispatched to the GPU. This leads to
serialization of CPU-GPU, which increases latency and overhead in
the system.
[0004] For example, a typical hardware front end (HWFE) cannot
efficiently execute a batch of commands iteratively in a loop
(e.g., graphics processor command streamers do not support an
explicit loop construct). Moreover, the typical HWFE does not
include a mechanism for commands (State, Memory and MMIO modifying
commands) to modify their accesses (command contents: addresses,
data, etc.) as the loop executes, which is needed, e.g., when loops
are used to access (read/modify) data structures. These hardware
shortcomings are traditionally addressed using software first to
unroll the loops and then patching the commands with required data
before submitting them to a GPU for execution. However, this
creates additional overhead for software and also serializes the
command buffer submission process, reducing performance.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] A better understanding of the present invention can be
obtained from the following detailed description in conjunction
with the following drawings, in which:
[0006] FIG. 1 is a block diagram of a processing system, according
to an embodiment;
[0007] FIG. 2 is a block diagram of an embodiment of a processor
having one or more processor cores, an integrated memory
controller, and an integrated graphics processor;
[0008] FIG. 3 is a block diagram of a graphics processor, which may
be a discrete graphics processing unit, or may be a graphics
processor integrated with a plurality of processing cores;
[0009] FIG. 4 is a block diagram of an embodiment of a graphics
processing engine for a graphics processor;
[0010] FIG. 5 is a block diagram of another embodiment of a
graphics processor;
[0011] FIGS. 6A-6B illustrate thread execution logic including an
array of processing elements employed in a graphics processor;
[0012] FIG. 7 is a block diagram illustrating a graphics processor
instruction formats;
[0013] FIG. 8 is a block diagram of another embodiment of a
graphics processor;
[0014] FIG. 9A is a block diagram illustrating a graphics processor
command format according to an embodiment;
[0015] FIG. 9B is a block diagram illustrating a graphics processor
command sequence according to an embodiment;
[0016] FIG. 10 illustrates exemplary graphics software architecture
for a data processing system according to an embodiment;
[0017] FIG. 11A is a block diagram illustrating an IP core
development system that may be used to manufacture an integrated
circuit to perform operations according to an embodiment;
[0018] FIG. 11B illustrates a cross-section side view of an
integrated circuit package assembly, according to some
embodiments;
[0019] FIG. 12 is a block diagram illustrating an exemplary system
on a chip integrated circuit that may be fabricated using one or
more IP cores, according to an embodiment;
[0020] FIGS. 13A-13B are block diagrams illustrating exemplary
graphics processors for use within an SoC, according to
embodiments;
[0021] FIGS. 14A-14B illustrate additional exemplary graphics
processor logic according to embodiments;
[0022] FIG. 15 illustrates one embodiment of an architecture for
implementing embodiments;
[0023] FIG. 16 illustrates a graphics command parser in accordance
with one embodiment;
[0024] FIG. 17 illustrates an example of a loop in a command buffer
in accordance with one embodiment;
[0025] FIG. 18 illustrates the use of loop variables in command
processing, in accordance with an embodiment;
[0026] FIG. 19 illustrates a method of loop processing in
accordance with one embodiment;
[0027] FIG. 20 illustrates an example of nested loops in a command
buffer in accordance with one embodiment; and
[0028] FIG. 21 illustrates a method of nested loop processing in
accordance with one embodiment.
DETAILED DESCRIPTION
[0029] In the following description, for the purposes of
explanation, numerous specific details are set forth in order to
provide a thorough understanding of the embodiments of the
invention described below. It will be apparent, however, to one
skilled in the art that the embodiments of the invention may be
practiced without some of these specific details. In other
instances, well-known structures and devices are shown in block
diagram form to avoid obscuring the underlying principles of the
embodiments of the invention.
[0030] Exemplary Graphics Processor Architectures and Data
Types
[0031] System Overview
[0032] FIG. 1 is a block diagram of a processing system 100,
according to an embodiment. In various embodiments the system 100
includes one or more processors 102 and one or more graphics
processors 108, and may be a single processor desktop system, a
multiprocessor workstation system, or a server system having a
large number of processors 102 or processor cores 107. In one
embodiment, the system 100 is a processing platform incorporated
within a system-on-a-chip (SoC) integrated circuit for use in
mobile, handheld, or embedded devices.
[0033] In one embodiment the system 100 can include, or be
incorporated within a server-based gaming platform, a game console,
including a game and media console, a mobile gaming console, a
handheld game console, or an online game console. In some
embodiments the system 100 is a mobile phone, smart phone, tablet
computing device or mobile Internet device. The processing system
100 can also include, couple with, or be integrated within a
wearable device, such as a smart watch wearable device, smart
eyewear device, augmented reality device, or virtual reality
device. In some embodiments, the processing system 100 is a
television or set top box device having one or more processors 102
and a graphical interface generated by one or more graphics
processors 108.
[0034] In some embodiments, the one or more processors 102 each
include one or more processor cores 107 to process instructions
which, when executed, perform operations for system and user
software. In some embodiments, each of the one or more processor
cores 107 is configured to process a specific instruction set 109.
In some embodiments, instruction set 109 may facilitate Complex
Instruction Set Computing (CISC), Reduced Instruction Set Computing
(RISC), or computing via a Very Long Instruction Word (VLIW).
Multiple processor cores 107 may each process a different
instruction set 109, which may include instructions to facilitate
the emulation of other instruction sets. Processor core 107 may
also include other processing devices, such a Digital Signal
Processor (DSP).
[0035] In some embodiments, the processor 102 includes cache memory
104. Depending on the architecture, the processor 102 can have a
single internal cache or multiple levels of internal cache. In some
embodiments, the cache memory is shared among various components of
the processor 102. In some embodiments, the processor 102 also uses
an external cache (e.g., a Level-3 (L3) cache or Last Level Cache
(LLC)) (not shown), which may be shared among processor cores 107
using known cache coherency techniques. A register file 106 is
additionally included in processor 102 which may include different
types of registers for storing different types of data (e.g.,
integer registers, floating point registers, status registers, and
an instruction pointer register). Some registers may be
general-purpose registers, while other registers may be specific to
the design of the processor 102.
[0036] In some embodiments, one or more processor(s) 102 are
coupled with one or more interface bus(es) 110 to transmit
communication signals such as address, data, or control signals
between processor 102 and other components in the system 100. The
interface bus 110, in one embodiment, can be a processor bus, such
as a version of the Direct Media Interface (DMI) bus. However,
processor busses are not limited to the DMI bus, and may include
one or more Peripheral Component Interconnect buses (e.g., PCI, PCI
Express), memory busses, or other types of interface busses. In one
embodiment the processor(s) 102 include an integrated memory
controller 116 and a platform controller hub 130. The memory
controller 116 facilitates communication between a memory device
and other components of the system 100, while the platform
controller hub (PCH) 130 provides connections to I/O devices via a
local I/O bus.
[0037] The memory device 120 can be a dynamic random access memory
(DRAM) device, a static random access memory (SRAM) device, flash
memory device, phase-change memory device, or some other memory
device having suitable performance to serve as process memory. In
one embodiment the memory device 120 can operate as system memory
for the system 100, to store data 122 and instructions 121 for use
when the one or more processors 102 executes an application or
process. Memory controller 116 also couples with an optional
external graphics processor 112, which may communicate with the one
or more graphics processors 108 in processors 102 to perform
graphics and media operations. In some embodiments a display device
111 can connect to the processor(s) 102. The display device 111 can
be one or more of an internal display device, as in a mobile
electronic device or a laptop device or an external display device
attached via a display interface (e.g., DisplayPort, etc.). In one
embodiment the display device 111 can be a head mounted display
(HMD) such as a stereoscopic display device for use in virtual
reality (VR) applications or augmented reality (AR)
applications.
[0038] In some embodiments the platform controller hub 130 enables
peripherals to connect to memory device 120 and processor 102 via a
high-speed I/O bus. The I/O peripherals include, but are not
limited to, an audio controller 146, a network controller 134, a
firmware interface 128, a wireless transceiver 126, touch sensors
125, a data storage device 124 (e.g., hard disk drive, flash
memory, etc.). The data storage device 124 can connect via a
storage interface (e.g., SATA) or via a peripheral bus, such as a
Peripheral Component Interconnect bus (e.g., PCI, PCI Express). The
touch sensors 125 can include touch screen sensors, pressure
sensors, or fingerprint sensors. The wireless transceiver 126 can
be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile
network transceiver such as a 3G, 4G, or Long Term Evolution (LTE)
transceiver. The firmware interface 128 enables communication with
system firmware, and can be, for example, a unified extensible
firmware interface (UEFI). The network controller 134 can enable a
network connection to a wired network. In some embodiments, a
high-performance network controller (not shown) couples with the
interface bus 110. The audio controller 146, in one embodiment, is
a multi-channel high definition audio controller. In one embodiment
the system 100 incudes an optional legacy I/O controller 140 for
coupling legacy (e.g., Personal System 2 (PS/2)) devices to the
system. The platform controller hub 130 can also connect to one or
more Universal Serial Bus (USB) controllers 142 connect input
devices, such as keyboard and mouse 143 combinations, a camera 144,
or other USB input devices.
[0039] It will be appreciated that the system 100 shown is
exemplary and not limiting, as other types of data processing
systems that are differently configured may also be used. For
example, an instance of the memory controller 116 and platform
controller hub 130 may be integrated into a discreet external
graphics processor, such as the external graphics processor 112. In
one embodiment the platform controller hub 130 and/or memory
controller 160 may be external to the one or more processor(s) 102.
For example, the system 100 can include an external memory
controller 116 and platform controller hub 130, which may be
configured as a memory controller hub and peripheral controller hub
within a system chipset that is in communication with the
processor(s) 102.
[0040] FIG. 2 is a block diagram of an embodiment of a processor
200 having one or more processor cores 202A-202N, an integrated
memory controller 214, and an integrated graphics processor 208.
Those elements of FIG. 2 having the same reference numbers (or
names) as the elements of any other figure herein can operate or
function in any manner similar to that described elsewhere herein,
but are not limited to such. Processor 200 can include additional
cores up to and including additional core 202N represented by the
dashed lined boxes. Each of processor cores 202A-202N includes one
or more internal cache units 204A-204N. In some embodiments each
processor core also has access to one or more shared cached units
206.
[0041] The internal cache units 204A-204N and shared cache units
206 represent a cache memory hierarchy within the processor 200.
The cache memory hierarchy may include at least one level of
instruction and data cache within each processor core and one or
more levels of shared mid-level cache, such as a Level 2 (L2),
Level 3 (L3), Level 4 (L4), or other levels of cache, where the
highest level of cache before external memory is classified as the
LLC. In some embodiments, cache coherency logic maintains coherency
between the various cache units 206 and 204A-204N.
[0042] In some embodiments, processor 200 may also include a set of
one or more bus controller units 216 and a system agent core 210.
The one or more bus controller units 216 manage a set of peripheral
buses, such as one or more PCI or PCI express busses. System agent
core 210 provides management functionality for the various
processor components. In some embodiments, system agent core 210
includes one or more integrated memory controllers 214 to manage
access to various external memory devices (not shown).
[0043] In some embodiments, one or more of the processor cores
202A-202N include support for simultaneous multi-threading. In such
embodiment, the system agent core 210 includes components for
coordinating and operating cores 202A-202N during multi-threaded
processing. System agent core 210 may additionally include a power
control unit (PCU), which includes logic and components to regulate
the power state of processor cores 202A-202N and graphics processor
208.
[0044] In some embodiments, processor 200 additionally includes
graphics processor 208 to execute graphics processing operations.
In some embodiments, the graphics processor 208 couples with the
set of shared cache units 206, and the system agent core 210,
including the one or more integrated memory controllers 214. In
some embodiments, the system agent core 210 also includes a display
controller 211 to drive graphics processor output to one or more
coupled displays. In some embodiments, display controller 211 may
also be a separate module coupled with the graphics processor via
at least one interconnect, or may be integrated within the graphics
processor 208.
[0045] In some embodiments, a ring based interconnect unit 212 is
used to couple the internal components of the processor 200.
However, an alternative interconnect unit may be used, such as a
point-to-point interconnect, a switched interconnect, or other
techniques, including techniques well known in the art. In some
embodiments, graphics processor 208 couples with the ring
interconnect 212 via an I/O link 213.
[0046] The exemplary I/O link 213 represents at least one of
multiple varieties of I/O interconnects, including an on package
I/O interconnect which facilitates communication between various
processor components and a high-performance embedded memory module
218, such as an eDRAM module. In some embodiments, each of the
processor cores 202A-202N and graphics processor 208 use embedded
memory modules 218 as a shared Last Level Cache.
[0047] In some embodiments, processor cores 202A-202N are
homogenous cores executing the same instruction set architecture.
In another embodiment, processor cores 202A-202N are heterogeneous
in terms of instruction set architecture (ISA), where one or more
of processor cores 202A-202N execute a first instruction set, while
at least one of the other cores executes a subset of the first
instruction set or a different instruction set. In one embodiment
processor cores 202A-202N are heterogeneous in terms of
microarchitecture, where one or more cores having a relatively
higher power consumption couple with one or more power cores having
a lower power consumption. Additionally, processor 200 can be
implemented on one or more chips or as an SoC integrated circuit
having the illustrated components, in addition to other
components.
[0048] FIG. 3 is a block diagram of a graphics processor 300, which
may be a discrete graphics processing unit, or may be a graphics
processor integrated with a plurality of processing cores. In some
embodiments, the graphics processor communicates via a memory
mapped I/O interface to registers on the graphics processor and
with commands placed into the processor memory. In some
embodiments, graphics processor 300 includes a memory interface 314
to access memory. Memory interface 314 can be an interface to local
memory, one or more internal caches, one or more shared external
caches, and/or to system memory.
[0049] In some embodiments, graphics processor 300 also includes a
display controller 302 to drive display output data to a display
device 320. Display controller 302 includes hardware for one or
more overlay planes for the display and composition of multiple
layers of video or user interface elements. The display device 320
can be an internal or external display device. In one embodiment
the display device 320 is a head mounted display device, such as a
virtual reality (VR) display device or an augmented reality (AR)
display device. In some embodiments, graphics processor 300
includes a video codec engine 306 to encode, decode, or transcode
media to, from, or between one or more media encoding formats,
including, but not limited to Moving Picture Experts Group (MPEG)
formats such as MPEG-2, Advanced Video Coding (AVC) formats such as
H.264/MPEG-4 AVC, as well as the Society of Motion Picture &
Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic
Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG)
formats.
[0050] In some embodiments, graphics processor 300 includes a block
image transfer (BLIT) engine 304 to perform two-dimensional (2D)
rasterizer operations including, for example, bit-boundary block
transfers. However, in one embodiment, 2D graphics operations are
performed using one or more components of graphics processing
engine (GPE) 310. In some embodiments, GPE 310 is a compute engine
for performing graphics operations, including three-dimensional
(3D) graphics operations and media operations.
[0051] In some embodiments, GPE 310 includes a 3D pipeline 312 for
performing 3D operations, such as rendering three-dimensional
images and scenes using processing functions that act upon 3D
primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline
312 includes programmable and fixed function elements that perform
various tasks within the element and/or spawn execution threads to
a 3D/Media sub-system 315. While 3D pipeline 312 can be used to
perform media operations, an embodiment of GPE 310 also includes a
media pipeline 316 that is specifically used to perform media
operations, such as video post-processing and image
enhancement.
[0052] In some embodiments, media pipeline 316 includes fixed
function or programmable logic units to perform one or more
specialized media operations, such as video decode acceleration,
video de-interlacing, and video encode acceleration in place of, or
on behalf of video codec engine 306. In some embodiments, media
pipeline 316 additionally includes a thread spawning unit to spawn
threads for execution on 3D/Media sub-system 315. The spawned
threads perform computations for the media operations on one or
more graphics execution units included in 3D/Media sub-system
315.
[0053] In some embodiments, 3D/Media subsystem 315 includes logic
for executing threads spawned by 3D pipeline 312 and media pipeline
316. In one embodiment, the pipelines send thread execution
requests to 3D/Media subsystem 315, which includes thread dispatch
logic for arbitrating and dispatching the various requests to
available thread execution resources. The execution resources
include an array of graphics execution units to process the 3D and
media threads. In some embodiments, 3D/Media subsystem 315 includes
one or more internal caches for thread instructions and data. In
some embodiments, the subsystem also includes shared memory,
including registers and addressable memory, to share data between
threads and to store output data.
[0054] Graphics Processing Engine
[0055] FIG. 4 is a block diagram of a graphics processing engine
410 of a graphics processor in accordance with some embodiments. In
one embodiment, the graphics processing engine (GPE) 410 is a
version of the GPE 310 shown in FIG. 3. Elements of FIG. 4 having
the same reference numbers (or names) as the elements of any other
figure herein can operate or function in any manner similar to that
described elsewhere herein, but are not limited to such. For
example, the 3D pipeline 312 and media pipeline 316 of FIG. 3 are
illustrated. The media pipeline 316 is optional in some embodiments
of the GPE 410 and may not be explicitly included within the GPE
410. For example and in at least one embodiment, a separate media
and/or image processor is coupled to the GPE 410.
[0056] In some embodiments, GPE 410 couples with or includes a
command streamer 403, which provides a command stream to the 3D
pipeline 312 and/or media pipelines 316. In some embodiments,
command streamer 403 is coupled with memory, which can be system
memory, or one or more of internal cache memory and shared cache
memory. In some embodiments, command streamer 403 receives commands
from the memory and sends the commands to 3D pipeline 312 and/or
media pipeline 316. The commands are directives fetched from a ring
buffer, which stores commands for the 3D pipeline 312 and media
pipeline 316. In one embodiment, the ring buffer can additionally
include batch command buffers storing batches of multiple commands.
The commands for the 3D pipeline 312 can also include references to
data stored in memory, such as but not limited to vertex and
geometry data for the 3D pipeline 312 and/or image data and memory
objects for the media pipeline 316. The 3D pipeline 312 and media
pipeline 316 process the commands and data by performing operations
via logic within the respective pipelines or by dispatching one or
more execution threads to a graphics core array 414. In one
embodiment the graphics core array 414 include one or more blocks
of graphics cores (e.g., graphics core(s) 415A, graphics core(s)
415B), each block including one or more graphics cores. Each
graphics core includes a set of graphics execution resources that
includes general-purpose and graphics specific execution logic to
perform graphics and compute operations, as well as fixed function
texture processing and/or machine learning and artificial
intelligence acceleration logic.
[0057] In various embodiments the 3D pipeline 312 includes fixed
function and programmable logic to process one or more shader
programs, such as vertex shaders, geometry shaders, pixel shaders,
fragment shaders, compute shaders, or other shader programs, by
processing the instructions and dispatching execution threads to
the graphics core array 414. The graphics core array 414 provides a
unified block of execution resources for use in processing these
shader programs. Multi-purpose execution logic (e.g., execution
units) within the graphics core(s) 415A-414B of the graphic core
array 414 includes support for various 3D API shader languages and
can execute multiple simultaneous execution threads associated with
multiple shaders.
[0058] In some embodiments the graphics core array 414 also
includes execution logic to perform media functions, such as video
and/or image processing. In one embodiment, the execution units
additionally include general-purpose logic that is programmable to
perform parallel general-purpose computational operations, in
addition to graphics processing operations. The general-purpose
logic can perform processing operations in parallel or in
conjunction with general-purpose logic within the processor core(s)
107 of FIG. 1 or core 202A-202N as in FIG. 2.
[0059] Output data generated by threads executing on the graphics
core array 414 can output data to memory in a unified return buffer
(URB) 418. The URB 418 can store data for multiple threads. In some
embodiments the URB 418 may be used to send data between different
threads executing on the graphics core array 414. In some
embodiments the URB 418 may additionally be used for
synchronization between threads on the graphics core array and
fixed function logic within the shared function logic 420.
[0060] In some embodiments, graphics core array 414 is scalable,
such that the array includes a variable number of graphics cores,
each having a variable number of execution units based on the
target power and performance level of GPE 410. In one embodiment
the execution resources are dynamically scalable, such that
execution resources may be enabled or disabled as needed.
[0061] The graphics core array 414 couples with shared function
logic 420 that includes multiple resources that are shared between
the graphics cores in the graphics core array. The shared functions
within the shared function logic 420 are hardware logic units that
provide specialized supplemental functionality to the graphics core
array 414. In various embodiments, shared function logic 420
includes but is not limited to sampler 421, math 422, and
inter-thread communication (ITC) 423 logic. Additionally, some
embodiments implement one or more cache(s) 425 within the shared
function logic 420.
[0062] A shared function is implemented where the demand for a
given specialized function is insufficient for inclusion within the
graphics core array 414. Instead a single instantiation of that
specialized function is implemented as a stand-alone entity in the
shared function logic 420 and shared among the execution resources
within the graphics core array 414. The precise set of functions
that are shared between the graphics core array 414 and included
within the graphics core array 414 varies across embodiments. In
some embodiments, specific shared functions within the shared
function logic 420 that are used extensively by the graphics core
array 414 may be included within shared function logic 416 within
the graphics core array 414. In various embodiments, the shared
function logic 416 within the graphics core array 414 can include
some or all logic within the shared function logic 420. In one
embodiment, all logic elements within the shared function logic 420
may be duplicated within the shared function logic 416 of the
graphics core array 414. In one embodiment the shared function
logic 420 is excluded in favor of the shared function logic 416
within the graphics core array 414.
[0063] FIG. 5 is a block diagram of hardware logic of a graphics
processor core 500, according to some embodiments described herein.
Elements of FIG. 5 having the same reference numbers (or names) as
the elements of any other figure herein can operate or function in
any manner similar to that described elsewhere herein, but are not
limited to such. The illustrated graphics processor core 500, in
some embodiments, is included within the graphics core array 414 of
FIG. 4. The graphics processor core 500, sometimes referred to as a
core slice, can be one or multiple graphics cores within a modular
graphics processor. The graphics processor core 500 is exemplary of
one graphics core slice, and a graphics processor as described
herein may include multiple graphics core slices based on target
power and performance envelopes. Each graphics core 500 can include
a fixed function block 530 coupled with multiple sub-cores
501A-501F, also referred to as sub-slices, that include modular
blocks of general-purpose and fixed function logic.
[0064] In some embodiments the fixed function block 530 includes a
geometry/fixed function pipeline 536 that can be shared by all
sub-cores in the graphics processor 500, for example, in lower
performance and/or lower power graphics processor implementations.
In various embodiments, the geometry/fixed function pipeline 536
includes a 3D fixed function pipeline (e.g., 3D pipeline 312 as in
FIG. 3 and FIG. 4) a video front-end unit, a thread spawner and
thread dispatcher, and a unified return buffer manager, which
manages unified return buffers, such as the unified return buffer
418 of FIG. 4.
[0065] In one embodiment the fixed function block 530 also includes
a graphics SoC interface 537, a graphics microcontroller 538, and a
media pipeline 539. The graphics SoC interface 537 provides an
interface between the graphics core 500 and other processor cores
within a system on a chip integrated circuit. The graphics
microcontroller 538 is a programmable sub-processor that is
configurable to manage various functions of the graphics processor
500, including thread dispatch, scheduling, and pre-emption. The
media pipeline 539 (e.g., media pipeline 316 of FIG. 3 and FIG. 4)
includes logic to facilitate the decoding, encoding,
pre-processing, and/or post-processing of multimedia data,
including image and video data. The media pipeline 539 implement
media operations via requests to compute or sampling logic within
the sub-cores 501-501F.
[0066] In one embodiment the SoC interface 537 enables the graphics
core 500 to communicate with general-purpose application processor
cores (e.g., CPUs) and/or other components within an SoC, including
memory hierarchy elements such as a shared last level cache memory,
the system RAM, and/or embedded on-chip or on-package DRAM. The SoC
interface 537 can also enable communication with fixed function
devices within the SoC, such as camera imaging pipelines, and
enables the use of and/or implements global memory atomics that may
be shared between the graphics core 500 and CPUs within the SoC.
The SoC interface 537 can also implement power management controls
for the graphics core 500 and enable an interface between a clock
domain of the graphic core 500 and other clock domains within the
SoC. In one embodiment the SoC interface 537 enables receipt of
command buffers from a command streamer and global thread
dispatcher that are configured to provide commands and instructions
to each of one or more graphics cores within a graphics processor.
The commands and instructions can be dispatched to the media
pipeline 539, when media operations are to be performed, or a
geometry and fixed function pipeline (e.g., geometry and fixed
function pipeline 536, geometry and fixed function pipeline 514)
when graphics processing operations are to be performed.
[0067] The graphics microcontroller 538 can be configured to
perform various scheduling and management tasks for the graphics
core 500. In one embodiment the graphics microcontroller 538 can
perform graphics and/or compute workload scheduling on the various
graphics parallel engines within execution unit (EU) arrays
502A-502F, 504A-504F within the sub-cores 501A-501F. In this
scheduling model, host software executing on a CPU core of an SoC
including the graphics core 500 can submit workloads one of
multiple graphic processor doorbells, which invokes a scheduling
operation on the appropriate graphics engine. Scheduling operations
include determining which workload to run next, submitting a
workload to a command streamer, pre-empting existing workloads
running on an engine, monitoring progress of a workload, and
notifying host software when a workload is complete. In one
embodiment the graphics microcontroller 538 can also facilitate
low-power or idle states for the graphics core 500, providing the
graphics core 500 with the ability to save and restore registers
within the graphics core 500 across low-power state transitions
independently from the operating system and/or graphics driver
software on the system.
[0068] The graphics core 500 may have greater than or fewer than
the illustrated sub-cores 501A-501F, up to N modular sub-cores. For
each set of N sub-cores, the graphics core 500 can also include
shared function logic 510, shared and/or cache memory 512, a
geometry/fixed function pipeline 514, as well as additional fixed
function logic 516 to accelerate various graphics and compute
processing operations. The shared function logic 510 can include
logic units associated with the shared function logic 420 of FIG. 4
(e.g., sampler, math, and/or inter-thread communication logic) that
can be shared by each N sub-cores within the graphics core 500. The
shared and/or cache memory 512 can be a last-level cache for the
set of N sub-cores 501A-501F within the graphics core 500, and can
also serve as shared memory that is accessible by multiple
sub-cores. The geometry/fixed function pipeline 514 can be included
instead of the geometry/fixed function pipeline 536 within the
fixed function block 530 and can include the same or similar logic
units.
[0069] In one embodiment the graphics core 500 includes additional
fixed function logic 516 that can include various fixed function
acceleration logic for use by the graphics core 500. In one
embodiment the additional fixed function logic 516 includes an
additional geometry pipeline for use in position only shading. In
position-only shading, two geometry pipelines exist, the full
geometry pipeline within the geometry/fixed function pipeline 516,
536, and a cull pipeline, which is an additional geometry pipeline
which may be included within the additional fixed function logic
516. In one embodiment the cull pipeline is a trimmed down version
of the full geometry pipeline. The full pipeline and the cull
pipeline can execute different instances of the same application,
each instance having a separate context. Position only shading can
hide long cull runs of discarded triangles, enabling shading to be
completed earlier in some instances. For example and in one
embodiment the cull pipeline logic within the additional fixed
function logic 516 can execute position shaders in parallel with
the main application and generally generates critical results
faster than the full pipeline, as the cull pipeline fetches and
shades only the position attribute of the vertices, without
performing rasterization and rendering of the pixels to the frame
buffer. The cull pipeline can use the generated critical results to
compute visibility information for all the triangles without regard
to whether those triangles are culled. The full pipeline (which in
this instance may be referred to as a replay pipeline) can consume
the visibility information to skip the culled triangles to shade
only the visible triangles that are finally passed to the
rasterization phase.
[0070] In one embodiment the additional fixed function logic 516
can also include machine-learning acceleration logic, such as fixed
function matrix multiplication logic, for implementations including
optimizations for machine learning training or inferencing.
[0071] Within each graphics sub-core 501A-501F includes a set of
execution resources that may be used to perform graphics, media,
and compute operations in response to requests by graphics
pipeline, media pipeline, or shader programs. The graphics
sub-cores 501A-501F include multiple EU arrays 502A-502F,
504A-504F, thread dispatch and inter-thread communication (TD/IC)
logic 503A-503F, a 3D (e.g., texture) sampler 505A-505F, a media
sampler 506A-506F, a shader processor 507A-507F, and shared local
memory (SLM) 508A-508F. The EU arrays 502A-502F, 504A-504F each
include multiple execution units, which are general-purpose
graphics processing units capable of performing floating-point and
integer/fixed-point logic operations in service of a graphics,
media, or compute operation, including graphics, media, or compute
shader programs. The TD/IC logic 503A-503F performs local thread
dispatch and thread control operations for the execution units
within a sub-core and facilitate communication between threads
executing on the execution units of the sub-core. The 3D sampler
505A-505F can read texture or other 3D graphics related data into
memory. The 3D sampler can read texture data differently based on a
configured sample state and the texture format associated with a
given texture. The media sampler 506A-506F can perform similar read
operations based on the type and format associated with media data.
In one embodiment, each graphics sub-core 501A-501F can alternately
include a unified 3D and media sampler. Threads executing on the
execution units within each of the sub-cores 501A-501F can make use
of shared local memory 508A-508F within each sub-core, to enable
threads executing within a thread group to execute using a common
pool of on-chip memory.
[0072] Execution Units
[0073] FIGS. 6A-6B illustrate thread execution logic 600 including
an array of processing elements employed in a graphics processor
core according to embodiments described herein. Elements of FIGS.
6A-6B having the same reference numbers (or names) as the elements
of any other figure herein can operate or function in any manner
similar to that described elsewhere herein, but are not limited to
such. FIG. 6A illustrates an overview of thread execution logic
600, which can include a variant of the hardware logic illustrated
with each sub-core 501A-501F of FIG. 5. FIG. 6B illustrates
exemplary internal details of an execution unit.
[0074] As illustrated in FIG. 6A, in some embodiments thread
execution logic 600 includes a shader processor 602, a thread
dispatcher 604, instruction cache 606, a scalable execution unit
array including a plurality of execution units 608A-608N, a sampler
610, a data cache 612, and a data port 614. In one embodiment the
scalable execution unit array can dynamically scale by enabling or
disabling one or more execution units (e.g., any of execution unit
608A, 608B, 608C, 608D, through 608N-1 and 608N) based on the
computational requirements of a workload. In one embodiment the
included components are interconnected via an interconnect fabric
that links to each of the components. In some embodiments, thread
execution logic 600 includes one or more connections to memory,
such as system memory or cache memory, through one or more of
instruction cache 606, data port 614, sampler 610, and execution
units 608A-608N. In some embodiments, each execution unit (e.g.
608A) is a stand-alone programmable general-purpose computational
unit that is capable of executing multiple simultaneous hardware
threads while processing multiple data elements in parallel for
each thread. In various embodiments, the array of execution units
608A-608N is scalable to include any number individual execution
units.
[0075] In some embodiments, the execution units 608A-608N are
primarily used to execute shader programs. A shader processor 602
can process the various shader programs and dispatch execution
threads associated with the shader programs via a thread dispatcher
604. In one embodiment the thread dispatcher includes logic to
arbitrate thread initiation requests from the graphics and media
pipelines and instantiate the requested threads on one or more
execution unit in the execution units 608A-608N. For example, a
geometry pipeline can dispatch vertex, tessellation, or geometry
shaders to the thread execution logic for processing. In some
embodiments, thread dispatcher 604 can also process runtime thread
spawning requests from the executing shader programs.
[0076] In some embodiments, the execution units 608A-608N support
an instruction set that includes native support for many standard
3D graphics shader instructions, such that shader programs from
graphics libraries (e.g., Direct 3D and OpenGL) are executed with a
minimal translation. The execution units support vertex and
geometry processing (e.g., vertex programs, geometry programs,
vertex shaders), pixel processing (e.g., pixel shaders, fragment
shaders) and general-purpose processing (e.g., compute and media
shaders). Each of the execution units 608A-608N is capable of
multi-issue single instruction multiple data (SIMD) execution and
multi-threaded operation enables an efficient execution environment
in the face of higher latency memory accesses. Each hardware thread
within each execution unit has a dedicated high-bandwidth register
file and associated independent thread-state. Execution is
multi-issue per clock to pipelines capable of integer, single and
double precision floating point operations, SIMD branch capability,
logical operations, transcendental operations, and other
miscellaneous operations. While waiting for data from memory or one
of the shared functions, dependency logic within the execution
units 608A-608N causes a waiting thread to sleep until the
requested data has been returned. While the waiting thread is
sleeping, hardware resources may be devoted to processing other
threads. For example, during a delay associated with a vertex
shader operation, an execution unit can perform operations for a
pixel shader, fragment shader, or another type of shader program,
including a different vertex shader.
[0077] Each execution unit in execution units 608A-608N operates on
arrays of data elements. The number of data elements is the
"execution size," or the number of channels for the instruction. An
execution channel is a logical unit of execution for data element
access, masking, and flow control within instructions. The number
of channels may be independent of the number of physical Arithmetic
Logic Units (ALUs) or Floating Point Units (FPUs) for a particular
graphics processor. In some embodiments, execution units 608A-608N
support integer and floating-point data types.
[0078] The execution unit instruction set includes SIMD
instructions. The various data elements can be stored as a packed
data type in a register and the execution unit will process the
various elements based on the data size of the elements. For
example, when operating on a 256-bit wide vector, the 256 bits of
the vector are stored in a register and the execution unit operates
on the vector as four separate 64-bit packed data elements
(Quad-Word (QW) size data elements), eight separate 32-bit packed
data elements (Double Word (DW) size data elements), sixteen
separate 16-bit packed data elements (Word (W) size data elements),
or thirty-two separate 8-bit data elements (byte (B) size data
elements). However, different vector widths and register sizes are
possible.
[0079] In one embodiment one or more execution units can be
combined into a fused execution unit 609A-609N having thread
control logic (607A-607N) that is common to the fused EUs. Multiple
EUs can be fused into an EU group. Each EU in the fused EU group
can be configured to execute a separate SIMD hardware thread. The
number of EUs in a fused EU group can vary according to
embodiments. Additionally, various SIMD widths can be performed
per-EU, including but not limited to SIMD8, SIMD16, and SIMD32.
Each fused graphics execution unit 609A-609N includes at least two
execution units. For example, fused execution unit 609A includes a
first EU 608A, second EU 608B, and thread control logic 607A that
is common to the first EU 608A and the second EU 608B. The thread
control logic 607A controls threads executed on the fused graphics
execution unit 609A, allowing each EU within the fused execution
units 609A-609N to execute using a common instruction pointer
register.
[0080] One or more internal instruction caches (e.g., 606) are
included in the thread execution logic 600 to cache thread
instructions for the execution units. In some embodiments, one or
more data caches (e.g., 612) are included to cache thread data
during thread execution. In some embodiments, a sampler 610 is
included to provide texture sampling for 3D operations and media
sampling for media operations. In some embodiments, sampler 610
includes specialized texture or media sampling functionality to
process texture or media data during the sampling process before
providing the sampled data to an execution unit.
[0081] During execution, the graphics and media pipelines send
thread initiation requests to thread execution logic 600 via thread
spawning and dispatch logic. Once a group of geometric objects has
been processed and rasterized into pixel data, pixel processor
logic (e.g., pixel shader logic, fragment shader logic, etc.)
within the shader processor 602 is invoked to further compute
output information and cause results to be written to output
surfaces (e.g., color buffers, depth buffers, stencil buffers,
etc.). In some embodiments, a pixel shader or fragment shader
calculates the values of the various vertex attributes that are to
be interpolated across the rasterized object. In some embodiments,
pixel processor logic within the shader processor 602 then executes
an application programming interface (API)-supplied pixel or
fragment shader program. To execute the shader program, the shader
processor 602 dispatches threads to an execution unit (e.g., 608A)
via thread dispatcher 604. In some embodiments, shader processor
602 uses texture sampling logic in the sampler 610 to access
texture data in texture maps stored in memory. Arithmetic
operations on the texture data and the input geometry data compute
pixel color data for each geometric fragment, or discards one or
more pixels from further processing.
[0082] In some embodiments, the data port 614 provides a memory
access mechanism for the thread execution logic 600 to output
processed data to memory for further processing on a graphics
processor output pipeline. In some embodiments, the data port 614
includes or couples to one or more cache memories (e.g., data cache
612) to cache data for memory access via the data port.
[0083] As illustrated in FIG. 6B, a graphics execution unit 608 can
include an instruction fetch unit 637, a general register file
array (GRF) 624, an architectural register file array (ARF) 626, a
thread arbiter 622, a send unit 630, a branch unit 632, a set of
SIMD floating point units (FPUs) 634, and in one embodiment a set
of dedicated integer SIMD ALUs 635. The GRF 624 and ARF 626
includes the set of general register files and architecture
register files associated with each simultaneous hardware thread
that may be active in the graphics execution unit 608. In one
embodiment, per thread architectural state is maintained in the ARF
626, while data used during thread execution is stored in the GRF
624. The execution state of each thread, including the instruction
pointers for each thread, can be held in thread-specific registers
in the ARF 626.
[0084] In one embodiment the graphics execution unit 608 has an
architecture that is a combination of Simultaneous Multi-Threading
(SMT) and fine-grained Interleaved Multi-Threading (IMT). The
architecture has a modular configuration that can be fine tuned at
design time based on a target number of simultaneous threads and
number of registers per execution unit, where execution unit
resources are divided across logic used to execute multiple
simultaneous threads.
[0085] In one embodiment, the graphics execution unit 608 can
co-issue multiple instructions, which may each be different
instructions. The thread arbiter 622 of the graphics execution unit
thread 608 can dispatch the instructions to one of the send unit
630, branch unit 642, or SIMD FPU(s) 634 for execution. Each
execution thread can access 128 general-purpose registers within
the GRF 624, where each register can store 32 bytes, accessible as
a SIMD 8-element vector of 32-bit data elements. In one embodiment,
each execution unit thread has access to 4 Kbytes within the GRF
624, although embodiments are not so limited, and greater or fewer
register resources may be provided in other embodiments. In one
embodiment up to seven threads can execute simultaneously, although
the number of threads per execution unit can also vary according to
embodiments. In an embodiment in which seven threads may access 4
Kbytes, the GRF 624 can store a total of 28 Kbytes. Flexible
addressing modes can permit registers to be addressed together to
build effectively wider registers or to represent strided
rectangular block data structures.
[0086] In one embodiment, memory operations, sampler operations,
and other longer-latency system communications are dispatched via
"send" instructions that are executed by the message passing send
unit 630. In one embodiment, branch instructions are dispatched to
a dedicated branch unit 632 to facilitate SIMD divergence and
eventual convergence.
[0087] In one embodiment the graphics execution unit 608 includes
one or more SIMD floating point units (FPU(s)) 634 to perform
floating-point operations. In one embodiment, the FPU(s) 634 also
support integer computation. In one embodiment the FPU(s) 634 can
SIMD execute up to M number of 32-bit floating-point (or integer)
operations, or SIMD execute up to 2M 16-bit integer or 16-bit
floating-point operations. In one embodiment, at least one of the
FPU(s) provides extended math capability to support high-throughput
transcendental math functions and double precision 64-bit
floating-point. In some embodiments, a set of 8-bit integer SIMD
ALUs 635 are also present, and may be specifically optimized to
perform operations associated with machine learning
computations.
[0088] In one embodiment, arrays of multiple instances of the
graphics execution unit 608 can be instantiated in a graphics
sub-core grouping (e.g., a sub-slice). For scalability, product
architects can chose the exact number of execution units per
sub-core grouping. In one embodiment the execution unit 608 can
execute instructions across a plurality of execution channels. In a
further embodiment, each thread executed on the graphics execution
unit 608 is executed on a different channel.
[0089] FIG. 7 is a block diagram illustrating a graphics processor
instruction formats 700 according to some embodiments. In one or
more embodiment, the graphics processor execution units support an
instruction set having instructions in multiple formats. The solid
lined boxes illustrate the components that are generally included
in an execution unit instruction, while the dashed lines include
components that are optional or that are only included in a sub-set
of the instructions. In some embodiments, instruction format 700
described and illustrated are macro-instructions, in that they are
instructions supplied to the execution unit, as opposed to
micro-operations resulting from instruction decode once the
instruction is processed.
[0090] In some embodiments, the graphics processor execution units
natively support instructions in a 128-bit instruction format 710.
A 64-bit compacted instruction format 730 is available for some
instructions based on the selected instruction, instruction
options, and number of operands. The native 128-bit instruction
format 710 provides access to all instruction options, while some
options and operations are restricted in the 64-bit format 730. The
native instructions available in the 64-bit format 730 vary by
embodiment. In some embodiments, the instruction is compacted in
part using a set of index values in an index field 713. The
execution unit hardware references a set of compaction tables based
on the index values and uses the compaction table outputs to
reconstruct a native instruction in the 128-bit instruction format
710.
[0091] For each format, instruction opcode 712 defines the
operation that the execution unit is to perform. The execution
units execute each instruction in parallel across the multiple data
elements of each operand. For example, in response to an add
instruction the execution unit performs a simultaneous add
operation across each color channel representing a texture element
or picture element. By default, the execution unit performs each
instruction across all data channels of the operands. In some
embodiments, instruction control field 714 enables control over
certain execution options, such as channels selection (e.g.,
predication) and data channel order (e.g., swizzle). For
instructions in the 128-bit instruction format 710 an exec-size
field 716 limits the number of data channels that will be executed
in parallel. In some embodiments, exec-size field 716 is not
available for use in the 64-bit compact instruction format 730.
[0092] Some execution unit instructions have up to three operands
including two source operands, src0 720, src1 722, and one
destination 718. In some embodiments, the execution units support
dual destination instructions, where one of the destinations is
implied. Data manipulation instructions can have a third source
operand (e.g., SRC2 724), where the instruction opcode 712
determines the number of source operands. An instruction's last
source operand can be an immediate (e.g., hard-coded) value passed
with the instruction.
[0093] In some embodiments, the 128-bit instruction format 710
includes an access/address mode field 726 specifying, for example,
whether direct register addressing mode or indirect register
addressing mode is used. When direct register addressing mode is
used, the register address of one or more operands is directly
provided by bits in the instruction.
[0094] In some embodiments, the 128-bit instruction format 710
includes an access/address mode field 726, which specifies an
address mode and/or an access mode for the instruction. In one
embodiment the access mode is used to define a data access
alignment for the instruction. Some embodiments support access
modes including a 16-byte aligned access mode and a 1-byte aligned
access mode, where the byte alignment of the access mode determines
the access alignment of the instruction operands. For example, when
in a first mode, the instruction may use byte-aligned addressing
for source and destination operands and when in a second mode, the
instruction may use 16-byte-aligned addressing for all source and
destination operands.
[0095] In one embodiment, the address mode portion of the
access/address mode field 726 determines whether the instruction is
to use direct or indirect addressing. When direct register
addressing mode is used bits in the instruction directly provide
the register address of one or more operands. When indirect
register addressing mode is used, the register address of one or
more operands may be computed based on an address register value
and an address immediate field in the instruction.
[0096] In some embodiments instructions are grouped based on opcode
712 bit-fields to simplify Opcode decode 740. For an 8-bit opcode,
bits 4, 5, and 6 allow the execution unit to determine the type of
opcode. The precise opcode grouping shown is merely an example. In
some embodiments, a move and logic opcode group 742 includes data
movement and logic instructions (e.g., move (mov), compare (cmp)).
In some embodiments, move and logic group 742 shares the five most
significant bits (MSB), where move (mov) instructions are in the
form of 0000xxxxb and logic instructions are in the form of
0001xxxxb. A flow control instruction group 744 (e.g., call, jump
(jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20).
A miscellaneous instruction group 746 includes a mix of
instructions, including synchronization instructions (e.g., wait,
send) in the form of 0011xxxxb (e.g., 0x30). A parallel math
instruction group 748 includes component-wise arithmetic
instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb
(e.g., 0x40). The parallel math group 748 performs the arithmetic
operations in parallel across data channels. The vector math group
750 includes arithmetic instructions (e.g., dp4) in the form of
0101xxxxb (e.g., 0x50). The vector math group performs arithmetic
such as dot product calculations on vector operands.
[0097] Graphics Pipeline
[0098] FIG. 8 is a block diagram of another embodiment of a
graphics processor 800. Elements of FIG. 8 having the same
reference numbers (or names) as the elements of any other figure
herein can operate or function in any manner similar to that
described elsewhere herein, but are not limited to such.
[0099] In some embodiments, graphics processor 800 includes a
geometry pipeline 820, a media pipeline 830, a display engine 840,
thread execution logic 850, and a render output pipeline 870. In
some embodiments, graphics processor 800 is a graphics processor
within a multi-core processing system that includes one or more
general-purpose processing cores. The graphics processor is
controlled by register writes to one or more control registers (not
shown) or via commands issued to graphics processor 800 via a ring
interconnect 802. In some embodiments, ring interconnect 802
couples graphics processor 800 to other processing components, such
as other graphics processors or general-purpose processors.
Commands from ring interconnect 802 are interpreted by a command
streamer 803, which supplies instructions to individual components
of the geometry pipeline 820 or the media pipeline 830.
[0100] In some embodiments, command streamer 803 directs the
operation of a vertex fetcher 805 that reads vertex data from
memory and executes vertex-processing commands provided by command
streamer 803. In some embodiments, vertex fetcher 805 provides
vertex data to a vertex shader 807, which performs coordinate space
transformation and lighting operations to each vertex. In some
embodiments, vertex fetcher 805 and vertex shader 807 execute
vertex-processing instructions by dispatching execution threads to
execution units 852A-852B via a thread dispatcher 831.
[0101] In some embodiments, execution units 852A-852B are an array
of vector processors having an instruction set for performing
graphics and media operations. In some embodiments, execution units
852A-852B have an attached L1 cache 851 that is specific for each
array or shared between the arrays. The cache can be configured as
a data cache, an instruction cache, or a single cache that is
partitioned to contain data and instructions in different
partitions.
[0102] In some embodiments, geometry pipeline 820 includes
tessellation components to perform hardware-accelerated
tessellation of 3D objects. In some embodiments, a programmable
hull shader 811 configures the tessellation operations. A
programmable domain shader 817 provides back-end evaluation of
tessellation output. A tessellator 813 operates at the direction of
hull shader 811 and contains special purpose logic to generate a
set of detailed geometric objects based on a coarse geometric model
that is provided as input to geometry pipeline 820. In some
embodiments, if tessellation is not used, tessellation components
(e.g., hull shader 811, tessellator 813, and domain shader 817) can
be bypassed.
[0103] In some embodiments, complete geometric objects can be
processed by a geometry shader 819 via one or more threads
dispatched to execution units 852A-852B, or can proceed directly to
the clipper 829. In some embodiments, the geometry shader operates
on entire geometric objects, rather than vertices or patches of
vertices as in previous stages of the graphics pipeline. If the
tessellation is disabled the geometry shader 819 receives input
from the vertex shader 807. In some embodiments, geometry shader
819 is programmable by a geometry shader program to perform
geometry tessellation if the tessellation units are disabled.
[0104] Before rasterization, a clipper 829 processes vertex data.
The clipper 829 may be a fixed function clipper or a programmable
clipper having clipping and geometry shader functions. In some
embodiments, a rasterizer and depth test component 873 in the
render output pipeline 870 dispatches pixel shaders to convert the
geometric objects into per pixel representations. In some
embodiments, pixel shader logic is included in thread execution
logic 850. In some embodiments, an application can bypass the
rasterizer and depth test component 873 and access un-rasterized
vertex data via a stream out unit 823.
[0105] The graphics processor 800 has an interconnect bus,
interconnect fabric, or some other interconnect mechanism that
allows data and message passing amongst the major components of the
processor. In some embodiments, execution units 852A-852B and
associated logic units (e.g., L1 cache 851, sampler 854, texture
cache 858, etc.) interconnect via a data port 856 to perform memory
access and communicate with render output pipeline components of
the processor. In some embodiments, sampler 854, caches 851, 858
and execution units 852A-852B each have separate memory access
paths. In one embodiment the texture cache 858 can also be
configured as a sampler cache.
[0106] In some embodiments, render output pipeline 870 contains a
rasterizer and depth test component 873 that converts vertex-based
objects into an associated pixel-based representation. In some
embodiments, the rasterizer logic includes a windower/masker unit
to perform fixed function triangle and line rasterization. An
associated render cache 878 and depth cache 879 are also available
in some embodiments. A pixel operations component 877 performs
pixel-based operations on the data, though in some instances, pixel
operations associated with 2D operations (e.g. bit block image
transfers with blending) are performed by the 2D engine 841, or
substituted at display time by the display controller 843 using
overlay display planes. In some embodiments, a shared L3 cache 875
is available to all graphics components, allowing the sharing of
data without the use of main system memory.
[0107] In some embodiments, graphics processor media pipeline 830
includes a media engine 837 and a video front-end 834. In some
embodiments, video front-end 834 receives pipeline commands from
the command streamer 803. In some embodiments, media pipeline 830
includes a separate command streamer. In some embodiments, video
front-end 834 processes media commands before sending the command
to the media engine 837. In some embodiments, media engine 837
includes thread spawning functionality to spawn threads for
dispatch to thread execution logic 850 via thread dispatcher
831.
[0108] In some embodiments, graphics processor 800 includes a
display engine 840. In some embodiments, display engine 840 is
external to processor 800 and couples with the graphics processor
via the ring interconnect 802, or some other interconnect bus or
fabric. In some embodiments, display engine 840 includes a 2D
engine 841 and a display controller 843. In some embodiments,
display engine 840 contains special purpose logic capable of
operating independently of the 3D pipeline. In some embodiments,
display controller 843 couples with a display device (not shown),
which may be a system integrated display device, as in a laptop
computer, or an external display device attached via a display
device connector.
[0109] In some embodiments, the geometry pipeline 820 and media
pipeline 830 are configurable to perform operations based on
multiple graphics and media programming interfaces and are not
specific to any one application programming interface (API). In
some embodiments, driver software for the graphics processor
translates API calls that are specific to a particular graphics or
media library into commands that can be processed by the graphics
processor. In some embodiments, support is provided for the Open
Graphics Library (OpenGL), Open Computing Language (OpenCL), and/or
Vulkan graphics and compute API, all from the Khronos Group. In
some embodiments, support may also be provided for the Direct3D
library from the Microsoft Corporation. In some embodiments, a
combination of these libraries may be supported. Support may also
be provided for the Open Source Computer Vision Library (OpenCV). A
future API with a compatible 3D pipeline would also be supported if
a mapping can be made from the pipeline of the future API to the
pipeline of the graphics processor.
[0110] Graphics Pipeline Programming
[0111] FIG. 9A is a block diagram illustrating a graphics processor
command format 900 according to some embodiments. FIG. 9B is a
block diagram illustrating a graphics processor command sequence
910 according to an embodiment. The solid lined boxes in FIG. 9A
illustrate the components that are generally included in a graphics
command while the dashed lines include components that are optional
or that are only included in a sub-set of the graphics commands.
The exemplary graphics processor command format 900 of FIG. 9A
includes data fields to identify a client 902, a command operation
code (opcode) 904, and data 906 for the command A sub-opcode 905
and a command size 908 are also included in some commands.
[0112] In some embodiments, client 902 specifies the client unit of
the graphics device that processes the command data. In some
embodiments, a graphics processor command parser examines the
client field of each command to condition the further processing of
the command and route the command data to the appropriate client
unit. In some embodiments, the graphics processor client units
include a memory interface unit, a render unit, a 2D unit, a 3D
unit, and a media unit. Each client unit has a corresponding
processing pipeline that processes the commands Once the command is
received by the client unit, the client unit reads the opcode 904
and, if present, sub-opcode 905 to determine the operation to
perform. The client unit performs the command using information in
data field 906. For some commands an explicit command size 908 is
expected to specify the size of the command In some embodiments,
the command parser automatically determines the size of at least
some of the commands based on the command opcode. In some
embodiments commands are aligned via multiples of a double
word.
[0113] The flow diagram in FIG. 9B illustrates an exemplary
graphics processor command sequence 910. In some embodiments,
software or firmware of a data processing system that features an
embodiment of a graphics processor uses a version of the command
sequence shown to set up, execute, and terminate a set of graphics
operations. A sample command sequence is shown and described for
purposes of example only as embodiments are not limited to these
specific commands or to this command sequence. Moreover, the
commands may be issued as batch of commands in a command sequence,
such that the graphics processor will process the sequence of
commands in at least partially concurrence.
[0114] In some embodiments, the graphics processor command sequence
910 may begin with a pipeline flush command 912 to cause any active
graphics pipeline to complete the currently pending commands for
the pipeline. In some embodiments, the 3D pipeline 922 and the
media pipeline 924 do not operate concurrently. The pipeline flush
is performed to cause the active graphics pipeline to complete any
pending commands In response to a pipeline flush, the command
parser for the graphics processor will pause command processing
until the active drawing engines complete pending operations and
the relevant read caches are invalidated. Optionally, any data in
the render cache that is marked `dirty` can be flushed to memory.
In some embodiments, pipeline flush command 912 can be used for
pipeline synchronization or before placing the graphics processor
into a low power state.
[0115] In some embodiments, a pipeline select command 913 is used
when a command sequence requires the graphics processor to
explicitly switch between pipelines. In some embodiments, a
pipeline select command 913 is required only once within an
execution context before issuing pipeline commands unless the
context is to issue commands for both pipelines. In some
embodiments, a pipeline flush command 912 is required immediately
before a pipeline switch via the pipeline select command 913.
[0116] In some embodiments, a pipeline control command 914
configures a graphics pipeline for operation and is used to program
the 3D pipeline 922 and the media pipeline 924. In some
embodiments, pipeline control command 914 configures the pipeline
state for the active pipeline. In one embodiment, the pipeline
control command 914 is used for pipeline synchronization and to
clear data from one or more cache memories within the active
pipeline before processing a batch of commands.
[0117] In some embodiments, return buffer state commands 916 are
used to configure a set of return buffers for the respective
pipelines to write data. Some pipeline operations require the
allocation, selection, or configuration of one or more return
buffers into which the operations write intermediate data during
processing. In some embodiments, the graphics processor also uses
one or more return buffers to store output data and to perform
cross thread communication. In some embodiments, the return buffer
state 916 includes selecting the size and number of return buffers
to use for a set of pipeline operations.
[0118] The remaining commands in the command sequence differ based
on the active pipeline for operations. Based on a pipeline
determination 920, the command sequence is tailored to the 3D
pipeline 922 beginning with the 3D pipeline state 930 or the media
pipeline 924 beginning at the media pipeline state 940.
[0119] The commands to configure the 3D pipeline state 930 include
3D state setting commands for vertex buffer state, vertex element
state, constant color state, depth buffer state, and other state
variables that are to be configured before 3D primitive commands
are processed. The values of these commands are determined at least
in part based on the particular 3D API in use. In some embodiments,
3D pipeline state 930 commands are also able to selectively disable
or bypass certain pipeline elements if those elements will not be
used.
[0120] In some embodiments, 3D primitive 932 command is used to
submit 3D primitives to be processed by the 3D pipeline. Commands
and associated parameters that are passed to the graphics processor
via the 3D primitive 932 command are forwarded to the vertex fetch
function in the graphics pipeline. The vertex fetch function uses
the 3D primitive 932 command data to generate vertex data
structures. The vertex data structures are stored in one or more
return buffers. In some embodiments, 3D primitive 932 command is
used to perform vertex operations on 3D primitives via vertex
shaders. To process vertex shaders, 3D pipeline 922 dispatches
shader execution threads to graphics processor execution units.
[0121] In some embodiments, 3D pipeline 922 is triggered via an
execute 934 command or event. In some embodiments, a register write
triggers command execution. In some embodiments execution is
triggered via a `go` or `kick` command in the command sequence. In
one embodiment, command execution is triggered using a pipeline
synchronization command to flush the command sequence through the
graphics pipeline. The 3D pipeline will perform geometry processing
for the 3D primitives. Once operations are complete, the resulting
geometric objects are rasterized and the pixel engine colors the
resulting pixels. Additional commands to control pixel shading and
pixel back end operations may also be included for those
operations.
[0122] In some embodiments, the graphics processor command sequence
910 follows the media pipeline 924 path when performing media
operations. In general, the specific use and manner of programming
for the media pipeline 924 depends on the media or compute
operations to be performed. Specific media decode operations may be
offloaded to the media pipeline during media decode. In some
embodiments, the media pipeline can also be bypassed and media
decode can be performed in whole or in part using resources
provided by one or more general-purpose processing cores. In one
embodiment, the media pipeline also includes elements for
general-purpose graphics processor unit (GPGPU) operations, where
the graphics processor is used to perform SIMD vector operations
using computational shader programs that are not explicitly related
to the rendering of graphics primitives.
[0123] In some embodiments, media pipeline 924 is configured in a
similar manner as the 3D pipeline 922. A set of commands to
configure the media pipeline state 940 are dispatched or placed
into a command queue before the media object commands 942. In some
embodiments, commands for the media pipeline state 940 include data
to configure the media pipeline elements that will be used to
process the media objects. This includes data to configure the
video decode and video encode logic within the media pipeline, such
as encode or decode format. In some embodiments, commands for the
media pipeline state 940 also support the use of one or more
pointers to "indirect" state elements that contain a batch of state
settings.
[0124] In some embodiments, media object commands 942 supply
pointers to media objects for processing by the media pipeline. The
media objects include memory buffers containing video data to be
processed. In some embodiments, all media pipeline states must be
valid before issuing a media object command 942. Once the pipeline
state is configured and media object commands 942 are queued, the
media pipeline 924 is triggered via an execute command 944 or an
equivalent execute event (e.g., register write). Output from media
pipeline 924 may then be post processed by operations provided by
the 3D pipeline 922 or the media pipeline 924. In some embodiments,
GPGPU operations are configured and executed in a similar manner as
media operations.
[0125] Graphics Software Architecture
[0126] FIG. 10 illustrates exemplary graphics software architecture
for a data processing system 1000 according to some embodiments. In
some embodiments, software architecture includes a 3D graphics
application 1010, an operating system 1020, and at least one
processor 1030. In some embodiments, processor 1030 includes a
graphics processor 1032 and one or more general-purpose processor
core(s) 1034. The graphics application 1010 and operating system
1020 each execute in the system memory 1050 of the data processing
system.
[0127] In some embodiments, 3D graphics application 1010 contains
one or more shader programs including shader instructions 1012. The
shader language instructions may be in a high-level shader
language, such as the High Level Shader Language (HLSL) or the
OpenGL Shader Language (GLSL). The application also includes
executable instructions 1014 in a machine language suitable for
execution by the general-purpose processor core 1034. The
application also includes graphics objects 1016 defined by vertex
data.
[0128] In some embodiments, operating system 1020 is a
Microsoft.RTM. Windows.RTM. operating system from the Microsoft
Corporation, a proprietary UNIX-like operating system, or an open
source UNIX-like operating system using a variant of the Linux
kernel. The operating system 1020 can support a graphics API 1022
such as the Direct3D API, the OpenGL API, or the Vulkan API. When
the Direct3D API is in use, the operating system 1020 uses a
front-end shader compiler 1024 to compile any shader instructions
1012 in HLSL into a lower-level shader language. The compilation
may be a just-in-time (JIT) compilation or the application can
perform shader pre-compilation. In some embodiments, high-level
shaders are compiled into low-level shaders during the compilation
of the 3D graphics application 1010. In some embodiments, the
shader instructions 1012 are provided in an intermediate form, such
as a version of the Standard Portable Intermediate Representation
(SPIR) used by the Vulkan API.
[0129] In some embodiments, user mode graphics driver 1026 contains
a back-end shader compiler 1027 to convert the shader instructions
1012 into a hardware specific representation. When the OpenGL API
is in use, shader instructions 1012 in the GLSL high-level language
are passed to a user mode graphics driver 1026 for compilation. In
some embodiments, user mode graphics driver 1026 uses operating
system kernel mode functions 1028 to communicate with a kernel mode
graphics driver 1029. In some embodiments, kernel mode graphics
driver 1029 communicates with graphics processor 1032 to dispatch
commands and instructions.
[0130] IP Core Implementations
[0131] One or more aspects of at least one embodiment may be
implemented by representative code stored on a machine-readable
medium which represents and/or defines logic within an integrated
circuit such as a processor. For example, the machine-readable
medium may include instructions which represent various logic
within the processor. When read by a machine, the instructions may
cause the machine to fabricate the logic to perform the techniques
described herein. Such representations, known as "IP cores," are
reusable units of logic for an integrated circuit that may be
stored on a tangible, machine-readable medium as a hardware model
that describes the structure of the integrated circuit. The
hardware model may be supplied to various customers or
manufacturing facilities, which load the hardware model on
fabrication machines that manufacture the integrated circuit. The
integrated circuit may be fabricated such that the circuit performs
operations described in association with any of the embodiments
described herein.
[0132] FIG. 11A is a block diagram illustrating an IP core
development system 1100 that may be used to manufacture an
integrated circuit to perform operations according to an
embodiment. The IP core development system 1100 may be used to
generate modular, re-usable designs that can be incorporated into a
larger design or used to construct an entire integrated circuit
(e.g., an SOC integrated circuit). A design facility 1130 can
generate a software simulation 1110 of an IP core design in a
high-level programming language (e.g., C/C++). The software
simulation 1110 can be used to design, test, and verify the
behavior of the IP core using a simulation model 1112. The
simulation model 1112 may include functional, behavioral, and/or
timing simulations. A register transfer level (RTL) design 1115 can
then be created or synthesized from the simulation model 1112. The
RTL design 1115 is an abstraction of the behavior of the integrated
circuit that models the flow of digital signals between hardware
registers, including the associated logic performed using the
modeled digital signals. In addition to an RTL design 1115,
lower-level designs at the logic level or transistor level may also
be created, designed, or synthesized. Thus, the particular details
of the initial design and simulation may vary.
[0133] The RTL design 1115 or equivalent may be further synthesized
by the design facility into a hardware model 1120, which may be in
a hardware description language (HDL), or some other representation
of physical design data. The HDL may be further simulated or tested
to verify the IP core design. The IP core design can be stored for
delivery to a 3.sup.rd party fabrication facility 1165 using
non-volatile memory 1140 (e.g., hard disk, flash memory, or any
non-volatile storage medium). Alternatively, the IP core design may
be transmitted (e.g., via the Internet) over a wired connection
1150 or wireless connection 1160. The fabrication facility 1165 may
then fabricate an integrated circuit that is based at least in part
on the IP core design. The fabricated integrated circuit can be
configured to perform operations in accordance with at least one
embodiment described herein.
[0134] FIG. 11B illustrates a cross-section side view of an
integrated circuit package assembly 1170, according to some
embodiments described herein. The integrated circuit package
assembly 1170 illustrates an implementation of one or more
processor or accelerator devices as described herein. The package
assembly 1170 includes multiple units of hardware logic 1172, 1174
connected to a substrate 1180. The logic 1172, 1174 may be
implemented at least partly in configurable logic or
fixed-functionality logic hardware, and can include one or more
portions of any of the processor core(s), graphics processor(s), or
other accelerator devices described herein. Each unit of logic
1172, 1174 can be implemented within a semiconductor die and
coupled with the substrate 1180 via an interconnect structure 1173.
The interconnect structure 1173 may be configured to route
electrical signals between the logic 1172, 1174 and the substrate
1180, and can include interconnects such as, but not limited to
bumps or pillars. In some embodiments, the interconnect structure
1173 may be configured to route electrical signals such as, for
example, input/output (I/O) signals and/or power or ground signals
associated with the operation of the logic 1172, 1174. In some
embodiments, the substrate 1180 is an epoxy-based laminate
substrate. The package substrate 1180 may include other suitable
types of substrates in other embodiments. The package assembly 1170
can be connected to other electrical devices via a package
interconnect 1183. The package interconnect 1183 may be coupled to
a surface of the substrate 1180 to route electrical signals to
other electrical devices, such as a motherboard, other chipset, or
multi-chip module.
[0135] In some embodiments, the units of logic 1172, 1174 are
electrically coupled with a bridge 1182 that is configured to route
electrical signals between the logic 1172, 1174. The bridge 1182
may be a dense interconnect structure that provides a route for
electrical signals. The bridge 1182 may include a bridge substrate
composed of glass or a suitable semiconductor material. Electrical
routing features can be formed on the bridge substrate to provide a
chip-to-chip connection between the logic 1172, 1174.
[0136] Although two units of logic 1172, 1174 and a bridge 1182 are
illustrated, embodiments described herein may include more or fewer
logic units on one or more dies. The one or more dies may be
connected by zero or more bridges, as the bridge 1182 may be
excluded when the logic is included on a single die. Alternatively,
multiple dies or units of logic can be connected by one or more
bridges. Additionally, multiple logic units, dies, and bridges can
be connected together in other possible configurations, including
three-dimensional configurations.
[0137] Exemplary System on a Chip Integrated Circuit
[0138] FIGS. 12-14 illustrated exemplary integrated circuits and
associated graphics processors that may be fabricated using one or
more IP cores, according to various embodiments described herein.
In addition to what is illustrated, other logic and circuits may be
included, including additional graphics processors/cores,
peripheral interface controllers, or general-purpose processor
cores.
[0139] FIG. 12 is a block diagram illustrating an exemplary system
on a chip integrated circuit 1200 that may be fabricated using one
or more IP cores, according to an embodiment. Exemplary integrated
circuit 1200 includes one or more application processor(s) 1205
(e.g., CPUs), at least one graphics processor 1210, and may
additionally include an image processor 1215 and/or a video
processor 1220, any of which may be a modular IP core from the same
or multiple different design facilities. Integrated circuit 1200
includes peripheral or bus logic including a USB controller 1225,
UART controller 1230, an SPI/SDIO controller 1235, and an
I.sup.2S/I.sup.2C controller 1240. Additionally, the integrated
circuit can include a display device 1245 coupled to one or more of
a high-definition multimedia interface (HDMI) controller 1250 and a
mobile industry processor interface (MIPI) display interface 1255.
Storage may be provided by a flash memory subsystem 1260 including
flash memory and a flash memory controller. Memory interface may be
provided via a memory controller 1265 for access to SDRAM or SRAM
memory devices. Some integrated circuits additionally include an
embedded security engine 1270.
[0140] FIGS. 13A-13B are block diagrams illustrating exemplary
graphics processors for use within an SoC, according to embodiments
described herein. FIG. 13A illustrates an exemplary graphics
processor 1310 of a system on a chip integrated circuit that may be
fabricated using one or more IP cores, according to an embodiment.
FIG. 13B illustrates an additional exemplary graphics processor
1340 of a system on a chip integrated circuit that may be
fabricated using one or more IP cores, according to an embodiment.
Graphics processor 1310 of FIG. 13A is an example of a low power
graphics processor core. Graphics processor 1340 of FIG. 13B is an
example of a higher performance graphics processor core. Each of
the graphics processors 1310, 1340 can be variants of the graphics
processor 1210 of FIG. 12.
[0141] As shown in FIG. 13A, graphics processor 1310 includes a
vertex processor 1305 and one or more fragment processor(s)
1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D, through 1315N-1, and
1315N). Graphics processor 1310 can execute different shader
programs via separate logic, such that the vertex processor 1305 is
optimized to execute operations for vertex shader programs, while
the one or more fragment processor(s) 1315A-1315N execute fragment
(e.g., pixel) shading operations for fragment or pixel shader
programs. The vertex processor 1305 performs the vertex processing
stage of the 3D graphics pipeline and generates primitives and
vertex data. The fragment processor(s) 1315A-1315N use the
primitive and vertex data generated by the vertex processor 1305 to
produce a framebuffer that is displayed on a display device. In one
embodiment, the fragment processor(s) 1315A-1315N are optimized to
execute fragment shader programs as provided for in the OpenGL API,
which may be used to perform similar operations as a pixel shader
program as provided for in the Direct 3D API.
[0142] Graphics processor 1310 additionally includes one or more
memory management units (MMUs) 1320A-1320B, cache(s) 1325A-1325B,
and circuit interconnect(s) 1330A-1330B. The one or more MMU(s)
1320A-1320B provide for virtual to physical address mapping for the
graphics processor 1310, including for the vertex processor 1305
and/or fragment processor(s) 1315A-1315N, which may reference
vertex or image/texture data stored in memory, in addition to
vertex or image/texture data stored in the one or more cache(s)
1325A-1325B. In one embodiment the one or more MMU(s) 1320A-1320B
may be synchronized with other MMUs within the system, including
one or more MMUs associated with the one or more application
processor(s) 1205, image processor 1215, and/or video processor
1220 of FIG. 12, such that each processor 1205-1220 can participate
in a shared or unified virtual memory system. The one or more
circuit interconnect(s) 1330A-1330B enable graphics processor 1310
to interface with other IP cores within the SoC, either via an
internal bus of the SoC or via a direct connection, according to
embodiments.
[0143] As shown FIG. 13B, graphics processor 1340 includes the one
or more MMU(s) 1320A-1320B, caches 1325A-1325B, and circuit
interconnects 1330A-1330B of the graphics processor 1310 of FIG.
13A. Graphics processor 1340 includes one or more shader core(s)
1355A-1355N (e.g., 1455A, 1355B, 1355C, 1355D, 1355E, 1355F,
through 1355N-1, and 1355N), which provides for a unified shader
core architecture in which a single core or type or core can
execute all types of programmable shader code, including shader
program code to implement vertex shaders, fragment shaders, and/or
compute shaders. The exact number of shader cores present can vary
among embodiments and implementations. Additionally, graphics
processor 1340 includes an inter-core task manager 1345, which acts
as a thread dispatcher to dispatch execution threads to one or more
shader cores 1355A-1355N and a tiling unit 1358 to accelerate
tiling operations for tile-based rendering, in which rendering
operations for a scene are subdivided in image space, for example
to exploit local spatial coherence within a scene or to optimize
use of internal caches.
[0144] FIGS. 14A-14B illustrate additional exemplary graphics
processor logic according to embodiments described herein. FIG. 14A
illustrates a graphics core 1400 that may be included within the
graphics processor 1210 of FIG. 12, and may be a unified shader
core 1355A-1355N as in FIG. 13B. FIG. 14B illustrates a
highly-parallel general-purpose graphics processing unit 1430
suitable for deployment on a multi-chip module.
[0145] As shown in FIG. 14A, the graphics core 1400 includes a
shared instruction cache 1402, a texture unit 1418, and a
cache/shared memory 1420 that are common to the execution resources
within the graphics core 1400. The graphics core 1400 can include
multiple slices 1401A-1401N or partition for each core, and a
graphics processor can include multiple instances of the graphics
core 1400. The slices 1401A-1401N can include support logic
including a local instruction cache 1404A-1404N, a thread scheduler
1406A-1406N, a thread dispatcher 1408A-1408N, and a set of
registers 1410A. To perform logic operations, the slices
1401A-1401N can include a set of additional function units (AFUs
1412A-1412N), floating-point units (FPU 1414A-1414N), integer
arithmetic logic units (ALUs 1416-1416N), address computational
units (ACU 1413A-1413N), double-precision floating-point units
(DPFPU 1415A-1415N), and matrix processing units (MPU
1417A-1417N).
[0146] Some of the computational units operate at a specific
precision. For example, the FPUs 1414A-1414N can perform
single-precision (32-bit) and half-precision (16-bit) floating
point operations, while the DPFPUs 1415A-1415N perform double
precision (64-bit) floating point operations. The ALUs 1416A-1416N
can perform variable precision integer operations at 8-bit, 16-bit,
and 32-bit precision, and can be configured for mixed precision
operations. The MPUs 1417A-1417N can also be configured for mixed
precision matrix operations, including half-precision floating
point and 8-bit integer operations. The MPUs 1417-1417N can perform
a variety of matrix operations to accelerate machine learning
application frameworks, including enabling support for accelerated
general matrix to matrix multiplication (GEMM). The AFUs
1412A-1412N can perform additional logic operations not supported
by the floating-point or integer units, including trigonometric
operations (e.g., Sine, Cosine, etc.).
[0147] As shown in FIG. 14B, a general-purpose processing unit
(GPGPU) 1430 can be configured to enable highly-parallel compute
operations to be performed by an array of graphics processing
units. Additionally, the GPGPU 1430 can be linked directly to other
instances of the GPGPU to create a multi-GPU cluster to improve
training speed for particularly deep neural networks. The GPGPU
1430 includes a host interface 1432 to enable a connection with a
host processor. In one embodiment the host interface 1432 is a PCI
Express interface. However, the host interface can also be a vendor
specific communications interface or communications fabric. The
GPGPU 1430 receives commands from the host processor and uses a
global scheduler 1434 to distribute execution threads associated
with those commands to a set of compute clusters 1436A-1436H. The
compute clusters 1436A-1436H share a cache memory 1438. The cache
memory 1438 can serve as a higher-level cache for cache memories
within the compute clusters 1436A-1436H.
[0148] The GPGPU 1430 includes memory 1434A-1434B coupled with the
compute clusters 1436A-1436H via a set of memory controllers
1442A-1442B. In various embodiments, the memory 1434A-1434B can
include various types of memory devices including dynamic random
access memory (DRAM) or graphics random access memory, such as
synchronous graphics random access memory (SGRAM), including
graphics double data rate (GDDR) memory.
[0149] In one embodiment the compute clusters 1436A-1436H each
include a set of graphics cores, such as the graphics core 1400 of
FIG. 14A, which can include multiple types of integer and floating
point logic units that can perform computational operations at a
range of precisions including suited for machine learning
computations. For example and in one embodiment at least a subset
of the floating point units in each of the compute clusters
1436A-1436H can be configured to perform 16-bit or 32-bit floating
point operations, while a different subset of the floating point
units can be configured to perform 64-bit floating point
operations.
[0150] Multiple instances of the GPGPU 1430 can be configured to
operate as a compute cluster. The communication mechanism used by
the compute cluster for synchronization and data exchange varies
across embodiments. In one embodiment the multiple instances of the
GPGPU 1430 communicate over the host interface 1432. In one
embodiment the GPGPU 1430 includes an I/O hub 1439 that couples the
GPGPU 1430 with a GPU link 1440 that enables a direct connection to
other instances of the GPGPU. In one embodiment the GPU link 1440
is coupled to a dedicated GPU-to-GPU bridge that enables
communication and synchronization between multiple instances of the
GPGPU 1430. In one embodiment the GPU link 1440 couples with a high
speed interconnect to transmit and receive data to other GPGPUs or
parallel processors. In one embodiment the multiple instances of
the GPGPU 1430 are located in separate data processing systems and
communicate via a network device that is accessible via the host
interface 1432. In one embodiment the GPU link 1440 can be
configured to enable a connection to a host processor in addition
to or as an alternative to the host interface 1432.
[0151] While the illustrated configuration of the GPGPU 1430 can be
configured to train neural networks, one embodiment provides
alternate configuration of the GPGPU 1430 that can be configured
for deployment within a high performance or low power inferencing
platform. In an inferencing configuration the GPGPU 1430 includes
fewer of the compute clusters 1436A-1436H relative to the training
configuration. Additionally, the memory technology associated with
the memory 1434A-1434B may differ between inferencing and training
configurations, with higher bandwidth memory technologies devoted
to training configurations. In one embodiment the inferencing
configuration of the GPGPU 1430 can support inferencing specific
instructions. For example, an inferencing configuration can provide
support for one or more 8-bit integer dot product instructions,
which are commonly used during inferencing operations for deployed
neural networks.
[0152] Method and Apparatus for Efficient Loop Processing in a
Graphics Hardware Front End
[0153] In accordance with various embodiments, the limitations of
current systems are addressed by enabling loop processing in a
command processing block of the graphics hardware. This block may
be responsible for processing the hardware specific commands
(produced by the Application though API calls) and feeding the
graphics pipeline. Typically, graphics command parsers do not
provide an explicit command/mechanism to implement loops optimally
in a command sequence. Instead, software is required to un-roll the
loop in the command sequence. This adds overhead (e.g., on a CPU or
GPGPU) and also leads to larger command buffers. Additionally,
unrolling loops in software also adds an additional latency due to
serialization of software processing followed by graphics engine
execution. Other techniques, such as using software implemented
chained command buffers (e.g., where one command buffer calls
another recursively to form a loop), lead to additional
inefficiencies, such as memory latency incurred on a loop wrap as
there is no command buffer caching in a graphics command parser.
Further, for short command sequences, this memory latency may
dominate sequence execution.
[0154] Embodiments provide explicit support of loops and support
for commands with indirect data based on loop functionality in a
graphics command parser. A graphics command parsers may be extended
to support a loop construct, in accordance with various
embodiments. By adding explicit loop support to the graphics
command parser, the graphics command parser can more easily support
evolving APIs and usage models that increasingly utilize more
complex command processing from GPUs.
[0155] Additional details of implementations of various embodiments
are discussed in more detail below.
[0156] FIG. 15 illustrates one embodiment of a computing device
1500 for implementing embodiments. Computing device 1500 (e.g.,
mobile computing device) may be the same as system 100 of FIG. 1
and accordingly, for brevity and ease of understanding, many of the
details stated above with reference to FIGS. 1-14 are not further
discussed or repeated hereafter. Computing device 1500 may include
a mobile computing device (e.g., smartphone, tablet computer,
laptops, game consoles, portable workstations, etc.) serving as a
host machine for hosting a graphics command parsing mechanism
("parsing mechanism" or simply "graphics command parser") 1510 for
hardware loop command processing. Graphics command parser 1510 may
include any number and type of components to perform various tasks
relating to hardware loop command processing, as discussed herein.
It is to be noted that throughout this document, terms like
"graphics domain" may be referenced interchangeably with "graphics
processing unit" or simply "GPU" and similarly, "CPU domain" or
"host domain" may be referenced interchangeably with "computer
processing unit" or simply "CPU". In some embodiments, graphics
processing unit 1514 may store data associated with hardware loop
command processing in one or more dedicated registers or other
structures. This data may include loop wrap addresses 1518, loop
counts 1520, and/or a nested loop stack 1522. Although this data is
shown as being maintained by GPU 1514, in various embodiments data
may be stored to and/or accessed from memory 1508.
[0157] Computing device 1500 may include any number and type of
communication devices, such as large computing systems, such as
server computers, desktop computers, etc., and may further include
set-top boxes (e.g., Internet-based cable television set-top boxes,
etc.), global positioning system (GPS)-based devices, etc.
Computing device 1500 may include mobile computing devices serving
as communication devices, such as cellular phones including
smartphones, personal digital assistants (PDAs), tablet computers,
laptop computers, e-readers, smart televisions, television
platforms, wearable devices (e.g., glasses, watches, bracelets,
smartcards, jewelry, clothing items, etc.), media players, etc. For
example, in one embodiment, computing device 1500 may include a
mobile computing device employing an integrated circuit ("IC"),
such as system on a chip ("SoC" or "SOC"), integrating various
hardware and/or software components of computing device 1500 on a
single chip.
[0158] As illustrated, in one embodiment, in addition to employing
graphics command parser 1510, computing device 1500 may further
include any number and type of hardware components and/or software
components, such as (but not limited to) GPU 1514 (having driver
logic), CPU 1512, memory 1508, network devices, drivers, or the
like, as well as input/output (I/O) sources 1504, such as
touchscreens, touch panels, touch pads, virtual or regular
keyboards, virtual or regular mice, ports, connectors, etc.
Computing device 1500 may include operating system (OS) 1506
serving as an interface between hardware and/or physical resources
of the computer device 1500 and a user. It is contemplated that CPU
1512 may include one or processors, such as processor(s) 102 of
FIG. 1, while GPU 1514 may include one or more graphics processors,
such as graphics processor(s) 108 of FIG. 1.
[0159] It is to be noted that terms like "node", "computing node",
"server", "server device", "cloud computer", "cloud server", "cloud
server computer", "machine", "host machine", "device", "computing
device", "computer", "computing system", and the like, may be used
interchangeably throughout this document. It is to be further noted
that terms like "application", "software application", "program",
"software program", "package", "software package", and the like,
may be used interchangeably throughout this document. Also, terms
like "job", "input", "request", "message", and the like, may be
used interchangeably throughout this document.
[0160] It is contemplated and as further described with reference
to FIGS. 1-14, some processes of the graphics pipeline as described
above are implemented in software, while the rest are implemented
in hardware. A graphics pipeline may be implemented in a graphics
coprocessor design, where CPU 1512 is designed to work with GPU
1514 which may be included in or co-located with CPU 1512. In one
embodiment, GPU 1514 may employ any number and type of conventional
software and hardware logic to perform the conventional functions
relating to graphics rendering as well as novel software and
hardware logic to execute any number and type of instructions, such
as instructions 121 of FIG. 1.
[0161] As aforementioned, memory 1508 may include a random access
memory (RAM) comprising application database having object
information. A memory controller hub, such as memory controller hub
116 of FIG. 1, may access data in the RAM and forward it to GPU
1514 for graphics pipeline processing. RAM may include double data
rate RAM (DDR RAM), extended data output RAM (EDO RAM), etc. CPU
1512 interacts with a hardware graphics pipeline, as illustrated
with reference to FIG. 3, to share graphics pipelining
functionality. Processed data is stored in a buffer in the hardware
graphics pipeline, and state information is stored in memory 1508.
The resulting image is then transferred to I/O sources 1504, such
as a display component, such as display device 320 of FIG. 3, for
displaying of the image. It is contemplated that the display device
may be of various types, such as Cathode Ray Tube (CRT), Thin Film
Transistor (TFT), Liquid Crystal Display (LCD), Organic Light
Emitting Diode (OLED) array, etc., to display information to a
user.
[0162] Memory 1508 may comprise a pre-allocated region of a buffer
(e.g., frame buffer); however, it should be understood by one of
ordinary skill in the art that the embodiments are not so limited,
and that any memory accessible to the lower graphics pipeline may
be used. Computing device 1500 may further include input/output
(I/O) control hub (ICH) 130 as referenced in FIG. 1, one or more
I/O sources/devices 1504, etc.
[0163] CPU 1512 may include one or more processors to execute
instructions in order to perform whatever software routines the
computing system implements. The instructions frequently involve
some sort of operation performed upon data. Both data and
instructions may be stored in system memory 1508 and any associated
cache. Cache is typically designed to have shorter latency times
than system memory 1508; for example, cache might be integrated
onto the same silicon chip(s) as the processor(s) and/or
constructed with faster static RAM (SRAM) cells whilst the system
memory 1508 might be constructed with slower dynamic RAM (DRAM)
cells. By tending to store more frequently used instructions and
data in the cache as opposed to the system memory 1508, the overall
performance efficiency of computing device 1500 improves. It is
contemplated that in some embodiments, GPU 1514 may exist as part
of CPU 1512 (such as part of a physical CPU package) in which case,
memory 1508 may be shared by CPU 1512 and GPU 1514 or kept
separated.
[0164] System memory 1508 may be made available to other components
within the computing device 1500. For example, any data (e.g.,
input graphics data) received from various interfaces to the
computing device 1500 (e.g., keyboard and mouse, printer port,
Local Area Network (LAN) port, modem port, etc.) or retrieved from
an internal storage element of the computer device 1500 (e.g., hard
disk drive) are often temporarily queued into system memory 1508
prior to their being operated upon by the one or more processor(s)
in the implementation of a software program. Similarly, data that a
software program determines should be sent from the computing
device 1500 to an outside entity through one of the computing
system interfaces, or stored into an internal storage element, is
often temporarily queued in system memory 1508 prior to its being
transmitted or stored.
[0165] Further, for example, an ICH, such as ICH 130 of FIG. 1, may
be used for ensuring that such data is properly passed between the
system memory 1508 and its appropriate corresponding computing
system interface (and internal storage device if the computing
system is so designed) and may have bi-directional point-to-point
links between itself and the observed 110 sources/devices 1504.
Similarly, an MCH, such as MCH 116 of FIG. 1, may be used for
managing the various contending requests for system memory 1508
accesses amongst CPU 1512 and GPU 1514, interfaces and internal
storage elements that may proximately arise in time with respect to
one another.
[0166] I/O sources 1504 may include one or more I/O devices that
are implemented for transferring data to and/or from computing
device 1500 (e.g., a networking adapter); or, for a large scale
non-volatile storage within computing device 1500 (e.g., hard disk
drive). User input device, including alphanumeric and other keys,
may be used to communicate information and command selections to
GPU 1514. Another type of user input device is cursor control, such
as a mouse, a trackball, a touchscreen, a touchpad, or cursor
direction keys to communicate direction information and command
selections to GPU 1514 and to control cursor movement on the
display device. Camera and microphone arrays of computer device
1500 may be employed to observe gestures, record audio and video
and to receive and transmit visual and audio commands.
[0167] Computing device 1500 may further include network
interface(s) to provide access to a network, such as a LAN, a wide
area network (WAN), a metropolitan area network (MAN), a personal
area network (PAN), Bluetooth, a cloud network, a mobile network
(e.g., 3.sup.rd Generation (3G), etc.), an intranet, the Internet,
etc. Network interface(s) may include, for example, a wireless
network interface having antenna, which may represent one or more
antenna(e). Network interface(s) may also include, for example, a
wired network interface to communicate with remote devices via
network cable, which may be, for example, an Ethernet cable, a
coaxial cable, a fiber optic cable, a serial cable, or a parallel
cable.
[0168] Network interface(s) may provide access to a LAN, for
example, by conforming to IEEE 802.11b and/or IEEE 802.11g
standards, and/or the wireless network interface may provide access
to a personal area network, for example, by conforming to Bluetooth
standards. Other wireless network interfaces and/or protocols,
including previous and subsequent versions of the standards, may
also be supported. In addition to, or instead of, communication via
the wireless LAN standards, network interface(s) may provide
wireless communication using, for example, Time Division, Multiple
Access (TDMA) protocols, Global Systems for Mobile Communications
(GSM) protocols, Code Division, Multiple Access (CDMA) protocols,
and/or any other type of wireless communications protocols.
[0169] Network interface(s) may include one or more communication
interfaces, such as a modem, a network interface card, or other
well-known interface devices, such as those used for coupling to
the Ethernet, token ring, or other types of physical wired or
wireless attachments for purposes of providing a communication link
to support a LAN or a WAN, for example. In this manner, the
computer system may also be coupled to a number of peripheral
devices, clients, control surfaces, consoles, or servers via a
conventional network infrastructure, including an Intranet or the
Internet, for example.
[0170] It is to be appreciated that a lesser or more equipped
system than the example described above may be preferred for
certain implementations. Therefore, the configuration of computing
device 1500 may vary from implementation to implementation
depending upon numerous factors, such as price constraints,
performance requirements, technological improvements, or other
circumstances. Examples of the electronic device or computer system
1500 may include (without limitation) a mobile device, a personal
digital assistant, a mobile computing device, a smartphone, a
cellular telephone, a handset, a one-way pager, a two-way pager, a
messaging device, a computer, a personal computer (PC), a desktop
computer, a laptop computer, a notebook computer, a handheld
computer, a tablet computer, a server, a server array or server
farm, a web server, a network server, an Internet server, a work
station, a mini-computer, a main frame computer, a supercomputer, a
network appliance, a web appliance, a distributed computing system,
multiprocessor systems, processor-based systems, consumer
electronics, programmable consumer electronics, television, digital
television, set top box, wireless access point, base station,
subscriber station, mobile subscriber center, radio network
controller, router, hub, gateway, bridge, switch, machine, or
combinations thereof.
[0171] Embodiments may be implemented as any or a combination of:
one or more microchips or integrated circuits interconnected using
a parentboard, hardwired logic, software stored by a memory device
and executed by a microprocessor, firmware, an application specific
integrated circuit (ASIC), and/or a field programmable gate array
(FPGA). The term "logic" may include, by way of example, software
or hardware and/or combinations of software and hardware.
[0172] Embodiments may be provided, for example, as a computer
program product which may include one or more machine-readable
media having stored thereon machine-executable instructions that,
when executed by one or more machines such as a computer, network
of computers, or other electronic devices, may result in the one or
more machines carrying out operations in accordance with
embodiments described herein. A machine-readable medium may
include, but is not limited to, floppy diskettes, optical disks,
CD-ROMs (Compact Disc-Read Only Memories), and magneto-optical
disks, ROMs, RAMs, EPROMs (Erasable Programmable Read Only
Memories), EEPROMs (Electrically Erasable Programmable Read Only
Memories), magnetic or optical cards, flash memory, or other type
of media/machine-readable medium suitable for storing
machine-executable instructions.
[0173] Moreover, embodiments may be downloaded as a computer
program product, wherein the program may be transferred from a
remote computer (e.g., a server) to a requesting computer (e.g., a
client) by way of one or more data signals embodied in and/or
modulated by a carrier wave or other propagation medium via a
communication link (e.g., a modem and/or network connection).
[0174] FIG. 16 illustrates a graphics command parser 1510 in
accordance with one embodiment. In one embodiment, graphics command
parser 1510 may include any number and type of components to
perform various tasks relating to facilitating hardware loop
command processing at computing devices, such as computing device
1500 of FIG. 15. For example and in one embodiment, graphics
command parser 1510 may include (but not limited to): loop count
logic 1600; loop begin/loop end logic 1602; loop wrap address logic
1604; nested loop stack logic 1606; fetching and encoding/decoding
logic 1607; execution logic 1609; and communication/compatibility
logic 1611.
[0175] It is contemplated that various general purpose operations
can be performed quickly at GPUs, such as GPU 1514 of FIG. 15,
which can reduce the burden of performing such operations on CPUs,
such as CPU 1512 of FIG. 15. However, it is further contemplated
that command buffers and command steamers of GPUs are not designed
to efficiently conduct transfer of commands between GPUs and CPUs
and thus, a GPU often uses memory storage and cache resources that
are separate from the CPU. It is further known that General Purpose
Graphics Processing Unit (GPGPU) may employ driver software that is
capable of dispatching workloads to GPU using command buffers by
programming commands in a ring buffer, such as programming a
MI-BATCH_BUFFER_START command in a ring buffer. Typically, the
GPGPU driver waits for a previously dispatched command buffer
execution to be completed before its output can be evaluated and
any determination can be made as to whether a subsequent dependent
command buffer is to be executed or skipped.
[0176] In one embodiment, graphics command parser 1510 may include
loop count logic 1600 which may be used to load the initial loop
count and set the loop count on each iteration, as discussed
further with respect at least to FIG. 17 and FIG. 20. For example,
loop count logic 1600 may store a loop count for each loop/nested
loop in a command sequence. As the loop command sequence is
executed the loop count for the corresponding buffer may be
decremented. Further, in some embodiments, a loop count may be
updated dynamically based on an output of the command sequence. For
example, the sequence of commands may be executed iteratively in a
loop until a desired (e.g., quality or error margin) output is
achieved. The output of the command sequence may be compared to the
desired output value and, if it is within a margin of error, the
loop may not be repeated and the loop count may be decremented to
end the loop (e.g., set the loop count to zero). However, if the
output is greater than the margin of error the loop count may be
maintained or incremented (e.g., set the loop count to a value
equal to or greater than one).
[0177] In some embodiments, loop begin/loop end logic 1602, as
discussed further below, may identify LOOP_BEGIN and LOOP_END
commands which tag the start and end of a command sequence to be
executed in loop without referring to an address or offset.
Traditional loops are implemented in software as
"Jumps/Conditional-Jumps", in which a compiler or other software
would replace "LOOP_END" with a "JUMP" instruction with an address
corresponding to the "LOOP_BEGIN" instruction. However, in
accordance with various embodiments, loops may be implemented in
hardware such that the loop wrap address logic 1604 can derive a
LOOP_BEGIN location address as it parses the command sequence,
which avoids compiling of the command buffers. Evaluating the
location of the address can be difficult for a compiler or other
software when the "LOOP_BEGIN" and "LOOP_END" addresses are spanned
across multiple chained/nested batch buffers. Using this
address-free implementation of the LOOP provides an infrastructure
that is not impacted if the command buffers are moved around in
memory (page swapping) or when address translation page tables are
changed. The loop begin/loop end logic 1602 identifies the Loop
commands and can caches the memory requests made for the
instructions inside the loop. In some embodiments, dedicated
registers (e.g., loop variables) are implemented which
automatically compute (increment or decrement) on every iteration
of a loop (e.g., on a loop wrap) without expending additional
instructions.
[0178] In some embodiments, graphics commands that access memory
for load and store operations support computation of memory
addresses based on loop variables. For example,
MI_LOAD_REGISTER_MEM (LRM) command loads data from memory to an
MMIO register, both the memory address and the MMIO address are
inline to the command Using one or more loop variable values, the
LRM command can iteratively increment or decrement the addresses
used on each loop iteration. For example, a first loop variable may
be added to the memory address and a second loop variable may be
added to the MMIO address on each loop iterations. This enables
commands, such as the LRM command, to progressively make a forward
or reverse traverse in a data structure to fetch/store data as the
loop is executed.
[0179] In one embodiment, nested loop stack logic 1606 may
manipulate a nested loop stack, including its stack pointer, such
as stack 2030 and stack pointer 2032 of FIG. 20, to perform any
number of processes, such as some of the processes of FIG. 21, to
facilitate processing of nested loops. For example, as will be
further described with reference to FIG. 21, nested loop stack
logic 1606 may be used to perform any number of processes relating
to the stack, such as pushing to stack (e.g., block 2114), POPing
stack to update (e.g., block 2130), checking to determine whether
the stack is empty or full (e.g., block 2126), etc.
[0180] Further, in one embodiment, graphics command parser 1510
further includes fetching and encoding/decoding logic 1608 and
execution logic 1610 to perform additional processes as further
described with reference to FIG. 19 and FIG. 21, such as fetching
and encoding/decoding logic 1608 may be used for fetching commands
from addresses (e.g., at least blocks 1802, 1822, 2002, 2024),
decoding commands, etc. Similarly, execution logic 1610 may be used
to perform any number of execution processes, such as executing
commands (e.g., at least block 1826, 2034), etc.
[0181] In one embodiment, graphics command parser 1510 may be
hosted by a computing device, such as computing device 1500 of FIG.
15, wherein the computing device may include any number and type of
other components in communication with graphics command parser
1510, such as (without limitation): I/O sources 1508 having
capturing/sensing components (e.g., cameras, etc.) and output
components (e.g., display device, display screen, telepresence
display areas, telepresence projectors, telepresence
micro-projectors, etc.); etc. This computing device may be in
communication with one or more repositories or databases to store
and maintain any amount and type of data (e.g., real-time data,
historical contents, metadata, resources, policies, criteria, rules
and regulations, upgrades, etc.). Similarly, as aforementioned,
computing device may be in communication with any number and type
of other computing devices over a network or communications medium,
such as Cloud network, the Internet, intranet, Internet of Things
("IoT"), proximity network, Bluetooth, etc. It is contemplated that
embodiments are not limited to any particular number or type of
communication medium or networks.
[0182] In some embodiments, computing device 1500 may further
include capturing/sensing components having any number and type of
capturing/sensing devices, such as one or more sending and/or
capturing devices (e.g., cameras (e.g., three-dimension (3D)
cameras, etc.), microphones, vibration components, tactile
components, conductance elements, biometric sensors, chemical
detectors, signal detectors, electroencephalography, functional
near-infrared spectroscopy, wave detectors, force sensors (e.g.,
accelerometers), illuminators, etc.) that may be used for capturing
any amount and type of visual data, such as images (e.g., photos,
videos, movies, audio/video streams, etc.), and non-visual data,
such as audio streams (e.g., sound, noise, vibration, ultrasound,
etc.), radio waves (e.g., wireless signals, such as wireless
signals having data, metadata, signs, etc.), chemical changes or
properties (e.g., humidity, body temperature, etc.), biometric
readings (e.g., figure prints, etc.), brainwaves, brain
circulation, environmental/weather conditions, maps, etc. It is
contemplated that "sensor" and "detector" may be referenced
interchangeably throughout this document. It is further
contemplated that one or more capturing/sensing components may
further include one or more supporting or supplemental devices for
capturing and/or sensing of data, such as illuminators (e.g.,
infrared (IR) illuminator), light fixtures, generators, sound
blockers, etc.
[0183] It is further contemplated that in one embodiment,
capturing/sensing components may further include any number and
type of sensing devices or sensors (e.g., linear accelerometer) for
sensing or detecting any number and type of contexts (e.g.,
estimating horizon, linear acceleration, etc., relating to a mobile
computing device, etc.). For example, capturing/sensing components
may include any number and type of sensors, such as (without
limitations): accelerometers (e.g., linear accelerometer to measure
linear acceleration, etc.); inertial devices (e.g., inertial
accelerometers, inertial gyroscopes, micro-electro-mechanical
systems (MEMS) gyroscopes, inertial navigators, etc.); gravity
gradiometers to study and measure variations in gravitation
acceleration due to gravity, etc.
[0184] For example, capturing/sensing components may further
include (without limitations): audio/visual devices (e.g., cameras,
microphones, speakers, etc.); context-aware sensors (e.g.,
temperature sensors, facial expression and feature measurement
sensors working with one or more cameras of audio/visual devices,
environment sensors (such as to sense background colors, lights,
etc.), biometric sensors (such as to detect fingerprints, etc.),
calendar maintenance and reading device), etc.; global positioning
system (GPS) sensors; resource requestor; and trusted execution
environment (TEE) logic. TEE logic may be employed separately or be
part of resource requestor and/or an I/O subsystem, etc.
Capturing/sensing components may further include voice recognition
devices, photo recognition devices, facial and other body
recognition components, voice-to-text conversion components,
etc.
[0185] Computing device may further include one or more output
components in communication with one or more capturing/sensing
components to facilitate displaying of true 3D virtual images
floating in mid-air, 2D images, playing or visualization of sounds,
displaying visualization of fingerprints, presenting visualization
of touch, smell, and/or other sense-related experiences, etc. For
example, output components may include one or more display or
telepresence projectors to project a realistic and true 3D virtual
image that is capable of floating in the air and while having the
depth of a real-life image. Further, for example and in one
embodiment, output components may include (without limitation) one
or more of light sources, display devices and/or screens (e.g.,
two-dimension (2D) displays, 3D displays, etc.), audio speakers,
tactile components, conductance elements, bone conducting speakers,
olfactory or smell visual and/or non/visual presentation devices,
haptic or touch visual and/or non-visual presentation devices,
animation display devices, biometric display devices, X-ray display
devices, etc.
[0186] Communication/compatibility logic 1610 may be used to
facilitate dynamic communication and compatibility between
computing device 1500 of FIG. 15 and any number and type of other
computing devices (such as mobile computing device, desktop
computer, server computing device, etc.), processing devices (such
as central processing unit (CPU), graphics processing unit (GPU),
etc.), image capturing devices (such as camera), display elements
(such as display component, display device, display screen, etc.),
user/context-awareness components and/or
identification/verification sensors/devices (such as biometric
sensor/detector, scanner, etc.), memory or storage devices,
databases and/or data sources (such as data storage device, hard
drive, solid-state drive, hard disk, memory card or device, memory
circuit, etc.), networks (e.g., cloud network, the Internet,
intranet, cellular network, proximity networks, such as Bluetooth,
Bluetooth low energy (BLE), Bluetooth Smart, Wi-Fi proximity, Radio
Frequency Identification (RFID), Near Field Communication (NFC),
Body Area Network (BAN), etc.), wireless or wired communications
and relevant protocols (e.g., Wi-Fi.RTM., WiMAX, Ethernet, etc.),
connectivity and location management techniques, software
applications/websites, (e.g., social and/or business networking
websites, such as Facebook.RTM., LinkedIn.RTM., Google+.RTM.,
Twitter.RTM., etc., business applications, games and other
entertainment applications, etc.), programming languages, etc.,
while ensuring compatibility with changing technologies,
parameters, protocols, standards, etc.
[0187] Throughout this document, terms like "logic", "component",
"module", "framework", "engine", and the like, may be referenced
interchangeably and include, by way of example, software, hardware,
and/or any combination of software and hardware, such as firmware.
Further, any use of a particular brand, word, term, phrase, name,
and/or acronym, such as "GPU", "GPU domain", "CPU", "CPU domain",
"GPGPU", "command buffer", "batch buffer", "instruction", "stack",
"stack pointer", etc., should not be read to limit embodiments to
software or devices that carry that label in products or in
literature external to this document.
[0188] It is contemplated that any number and type of components
may be added to and/or removed from graphics command parser 1510 to
facilitate various embodiments including adding, removing, and/or
enhancing certain features. For brevity, clarity, and ease of
understanding of graphics command parser 1510, many of the standard
and/or known components, such as those of a computing device, are
not shown or discussed here. It is contemplated that embodiments,
as described herein, are not limited to any particular technology,
topology, system, architecture, and/or standard and are dynamic
enough to adopt and adapt to any future changes.
[0189] FIG. 17 illustrates an example of a loop in a command buffer
1700 in accordance with one embodiment. With the evolution of
graphics APIs, command sequences to be executed by a graphics
processor are getting more complex. This may include certain
command sequences that are to be executed multiple times (e.g.,
where the multiple count may be known a priori or may be computed
in real time). As discussed, this functionality may be supported by
adding a "LOOP" construct in graphics command parser. Through
loops, a section of commands in a command buffer can be identified
to be executed iteratively. As shown in FIG. 17, command buffer
1700 may include a buffer address 1702 and a corresponding command
1704.
[0190] In some embodiments, a Loop Construct is implemented by
bracketing (marking the beginning and ending) the desired section
of commands with a LOOP_BEGIN command 1706 indicating the start of
the command sequence 1708 and LOOP_END command 1710 as the end of
the command sequence to be executed in a loop. The graphics command
parser can execute the command sequence 1708 marked by the
LOOP_BEGIN and LOOP_END iteratively until a loop count expires. In
some embodiments, a loop count value can be stored in an MMIO
register which can be loaded from memory/MMIO/Immediate data prior
to executing LOOP_BEGIN command. The loop count can be modified by
the commands (e.g., MI) executed inside the looped command sequence
1708 allowing the loop count to dynamically modify itself. In some
embodiments, rather than executing the loop a known number of times
(e.g., as determined by the loop count), the loop can run
iteratively until a required/desired output of the loop is
achieved. In some embodiments, a LOOP_EXIT construct (e.g., loop
exit command) can be supported which, when executed, quits the
LOOP. This command may support conditional execution as well. By
supporting these loop commands, the graphics command parser of the
graphics engine can provide control structures, including:
[0191] 1. DO-WHILE Loop
[0192] 2. WHILE Loop
[0193] 3. FOR Loop
[0194] 4. EXIT
[0195] Unlike typical command buffers, which are not cached as they
do not follow the principle of locality, a graphics command parser
in accordance with an embodiment can implicitly make the command
fetches (from memory) for the commands inside the loop cacheable.
This provides the benefits of an instruction cache.
[0196] FIG. 18 illustrates the use of loop variables in command
processing, in accordance with an embodiment. In some embodiments,
dedicated MMIO registers may be supported to be used as variables
inside the loop. For example, as shown in FIG. 18, a command 1800
may include operands 1802, 1804. As shown, each operand may be
passed to adders 1806, 1808 which may also receive an input of a
loop variable 1810, 1812. This enables the value of the operands to
be incremented by the loop variable values. These registers can be
configured to automatically increment/decrement by a programmable
value on every loop wrap, avoiding additional instructions in the
command buffer to increment or decrement register variable on a
loop wrap resulting in compacted command buffers. Although adders
are shown in FIG. 18, in various embodiments, these registers can
also be modified through MI_MATH and other MI (Memory/MMIO
modifiers) commands as part of the loop command sequence to provide
more complex functionality using these variables. In some
embodiments, commands that may be programmed inside a loop can be
enhanced to support indirect data (e.g., earlier inline data) which
can be referenced as a function of the loop variables. For example,
an address field of a command for a memory request may be an offset
from a loop variable. In some embodiments, muxes 1814, 1816 can be
used to determine whether the initial operand value or the
incremented operand values output by adders 1806, 1808 are used
based on command fields 1818, 1820. As discussed, although adders
are shown in FIG. 18, this is for simplicity of explanation and one
of ordinary skill would recognize that alternative or additional
operations may be performed using the loop variables 1810, 1812 to
support indirect data.
[0197] FIG. 19 illustrates a method of loop processing in
accordance with one embodiment. As discussed, a Loop Construct can
be implemented by marking the beginning and ending of the desired
command sequence in a graphics command buffer to be executed in a
loop by explicitly programming LOOP_BEGIN and LOOP_END commands
respectively. A loop count value can be programmed to a LOOP_COUNT
register prior to programming LOOP_BEGIN command, LOOP_COUNT can
also be explicitly mentioned inline to the command. For example, a
bit field may be included in the LOOP_BEGIN command which indicates
if the LOOP_COUNT is inline or indirect.
[0198] As shown in FIG. 19 a command parser can load 1900 a command
buffer fetch address. The command parser can then get 1902 a
graphics command from the command buffer. At 1904, the command
parser can parse the command to determine whether the command
includes a load loop count command. If so, the command parser can
store 1906 the loop count value and the next graphics command can
be retrieved 1902. If the command is not a load loop count command
at 1904 (e.g., if the loop count command has already been
processed), the command parser can then determine at 1908 if the
command is a loop begin command. If so, the command parser can
activate 1910 loop logic and initialize a counter with the loop
count value. Additionally, the command parser can store 1912 the
address of the instruction following LOOP_BEGIN command as a Loop
Wrap address on parsing the LOOP_BEGIN command Processing may then
return to block 1902 to get the next graphics command from the
command buffer.
[0199] With the LOOP_BEGIN command having been identified and
processed, the next instruction in the command buffer is the first
instruction of the command sequence. If this command is not a load
loop count command, then processing will proceed from block 1904 to
block 1908. If this command is not a loop begin command, then
processing will proceed to block 1914. If the command parser
determines that this command is not a loop end command, then
processing will proceed to 1916 to determine whether the end of the
command buffer has been reached. If not, then the command is
executed 1918, and processing returns to 1902 to get the next
command. This loop will continue executing commands from the
command sequence until the loop end command is identified at 1914.
When the loop end command is identified, processing may proceed to
1920 and the counter that was previously stored with the loop count
value can be set. In some embodiments, set counter 1920 may
function to decrement the counter by an integer value. The value by
which the counter is decremented may be set by an earlier graphics
command (e.g., prior to or as a part of the command sequence). As
discussed, in some embodiments, the loop count value may be
determined dynamically based on an output of the command sequence.
In such an embodiment, set counter 1920 may set the counter value
to an integer value corresponding to the output value of the
command sequence (e.g., may increase, decrease, or maintain the
current counter value). If the counter value at 1922 equals zero or
less, then disable loop logic 1924 may be executed to end the loop
and processing may return to 1902 to get the next graphics command.
If the end of the command buffer has been reached at 1916, then
processing may end. If the counter value at 1922 does not equal
zero, processing may proceed to fetching 1926 the previously stored
loop wrap address and processing may return to 1902 to get the
first command from the command sequence (e.g., the command at the
loop wrap address). The command sequence may continue to execute as
described until the loop count equals zero and loop processing
ends.
[0200] FIG. 20 illustrates an example of nested loops in a command
buffer 2000 in accordance with one embodiment. As discussed, nested
loops may be supported by adding additional "LOOP" construct in
graphics command parser. As shown in FIG. 20, command buffer 2000
may include a buffer address 2002 and a corresponding command 2004.
A first loop begin command 2006 starts a first loop 2008. A first
loop wrap address 2010 can be stored for the first loop. In some
embodiments, a first loop count 2011 can be loaded prior to the
start of the first loop 2008. To add a nested loop, another loop
begin command 2012 can be included in the command sequence of the
first loop. Loop begin command 2012 starts nested loop 2014. Loop
2014 may be associated with its own loop count value 2015 and a
second loop wrap address 2016 can be stored. Loops may be further
nested similarly, by adding additional loop begin commands. For
example, a third loop 2020 is shown, which begins with command 2018
and includes its own loop count value set at 2019.
[0201] Like the single loop example discussed above, each loop may
be associated with a loop end command. For example, the third
nested loop 2020 ends with loop end command 2024, the second nested
loop 2014 ends with loop end command 2026, and the first loop 2008
ends with loop end command 2028. During processing, each loop may
be processed in turn. For example, the third nested loop 2020 may
be processed 15 times (e.g., its loop count value 2019) each time
second nested loop 2014 executes. The second nested loop 2014 may
executed three times (its loop count value 2015) each time the
first loop 2008 executes, which may execute five times (its loop
count value 2011).
[0202] In various embodiments, a hardware stack 2030 may be used to
track which loop's loop wrap address and loop count are being set.
For example, when a nested loop begin command is identified (such
as commands 2012 and 2018) the stack can be pushed with the loop
count value and loop wrap address for the nested loop. In some
embodiments the stack 2030 can be setup by programming a Stack
Pointer and max stack size. The stack can be a hardware based stack
with memory backed up. That is, one or more recent entries (e.g.,
entries on top of the stack) of the stack can be cached on an
on-die storage and spill fills can be done to memory as the stack
grows or shrinks. Likewise, when the nested loop has been
processed, the stack can be popped to return to the loop count
value and loop wrap address for the outer loop. In some
embodiments, the stack pointer can be made available on an MMIO
interface to be referenced and modified by MI commands. This
enables PUSH and POP of hardware state on to/from the stack. An
example of nested loop processing is discussed in further detail
below.
[0203] FIG. 21 illustrates a method of nested loop processing in
accordance with one embodiment. As shown in FIG. 21 a command
parser can load 2100 a command buffer fetch address. The command
parser can then get 2102 a graphics command from the command
buffer. At 2104, the command parser can determine whether the
command includes a load loop count command. If so, the command
parser can store 2106 the loop count value and the next graphics
command can be retrieved 2102. If the command is not a load loop
count command at 2104 (e.g., if the loop count command has already
been processed), the command parser can then determine at 2108 if
the command is a loop begin command. If so, the command parser can
determine 2110 whether a loop is active. If not, then the command
parser can activate 2112 loop logic. At 2116, the loop wrap address
can be stored and a counter can be initialized with the loop count
value. Processing may then return to block 2102 to process the next
graphics command.
[0204] If a loop is active, then the counter value and loop wrap
address can be pushed 2114 to a nested loop stack. After pushing
the stack, at 2116, the loop wrap address can be stored and a
counter can be initialized with the loop count value. In either
branch, the command parser can store the address of the instruction
following the LOOP_BEGIN command as a Loop Wrap address on parsing
the LOOP_BEGIN command for that loop. Processing may then return to
block 2102 to process the next graphics command.
[0205] With the LOOP_BEGIN command having been identified and
processed, the next instruction in the command buffer is the first
instruction of the command sequence for that loop. If this command
is not a load loop count command, then processing will proceed from
block 2104 to block 2108. If this command is not another loop begin
command, then processing will proceed to block 2118. If the command
parser determines that this command is not a loop end command, then
processing will proceed to 2132 to determine whether the end of the
command buffer has been reached. If not, then the command is
executed 2134, and processing returns to 1802 to get the next
command. This loop can continue executing commands from the command
sequence (including any additional nested loops) until the loop end
command is identified at 2118.
[0206] When the loop end command is identified, processing may
proceed to 2120 and the counter that was previously stored with the
loop count value can be set. In some embodiments, set counter 2120
may function to decrement the counter by an integer value. The
value by which the counter is decremented may be set by an earlier
graphics command (e.g., prior to or as a part of the command
sequence). As discussed, in some embodiments, the loop count value
may be determined dynamically based on an output of the command
sequence. In such an embodiment, set counter 2120 may set the
counter value to an integer value corresponding to the output value
of the command sequence (e.g., may increase, decrease, or maintain
the current counter value). If the counter value at 2122 does not
equal zero, processing may proceed to fetching 2126 the previously
loop wrap address stored to the current position of the stack
pointer and processing may return to 2102 to get the first command
from the command sequence (e.g., the command at the loop wrap
address) for the current loop. If the counter value at 2122 equals
zero or less, then the command processor can determine 2126 whether
the stack is empty. If the stack is empty, then the command
processor can disable loop logic 2128 to end the loop and
processing may return to 2102 to get the next graphics command. If
the end of the command buffer has been reached at 2132, then
processing may end. If the stack is not empty, then the command
parser can pop the stack 2130 to restore the previous (e.g., outer
loop) loop count and loop wrap address values. Processing may then
return to block 2124 where the loop wrap address from the new stack
pointer location is used to load the command buffer from that
address.
[0207] In some embodiments, a loop counter variable for a loop
execution can be MMIO (memory mapped I/O) mapped. The loop counter
can be modified by the commands executed from the loop to
dynamically control the loop count. In some embodiments, the loop
counter may be decremented by an integer value each time a loop is
completed (e.g., a default value of 1 may used for decrementing the
counter unless another value is specified). Additionally, the loop
construct can support a new command LOOP_EXIT to terminate the loop
sequence prematurely and jump to the command sequence following the
outer most LOOP_END command In some embodiments, the LOOP_EXIT
command with existing predication logic in hardware may provide the
capabilities to support CONDITIONAL_LOOP_EXIT. Predication logic
can be used to conditionally execute any command programmed in the
command buffer.
[0208] A LOOP_BEGIN command provides an additional option of
specifying the command buffer address of the corresponding LOOP_END
command. The command buffer address of the LOOP_END command may be
used by HW to optimize the following flows. For example, on
LOOP_EXIT, the command parser can directly jump to the outermost
LOOP_END command address instead of parsing the intervening command
sequence to reach the LOOP_END command In some embodiments, with a
"Loop Count" value programmed to zero (e.g., none of the commands
in the loop must be executed), the command parser can directly jump
to the LOOP_END command instead of parsing the intervening command
sequence to reach the LOOP_END command.
[0209] As discussed, in various embodiments, loop variables can be
used to support indirect data in commands executed by the loops. A
loop index can be made available for ALU operations in the graphics
command parser. The loop index with the loop variables can be used
as indirect data in the commands programmed inside the loop. This
provides support for various features, such as Draw Indirect and
Tile Based Rendering.
[0210] For example, Multi Draw Indirect requires multiple
3DPRIMITIVES to be rendered based on a count and requires each
3DPRIMTIVE to be rendered with the parameters provided. Executing a
MI_LOAD_REGISTER_MEM (LRM) command and a 3DPRIMTIVE command in a
loop that supports indirect data, enables the 3DPRIMITIVES to be
rendered based on the loop count. For example, the LRM can fetch
data from a first element in a multi draw array (e.g., elelemtn-0)
and populate the indirect registers. When the 3DPRIMITVE command is
executed, the inline content of the command can be replaced with
the values from the indirect registers resulting in rendering
3DPRIMITVE based on the parameters in element-0 of the array. On a
loop wrap the loop variable increments by the pitch of the elements
in the array and on executing the LRM, it fetches data from the
next element in the array (e.g., element-1). On executing
3DPRIMTIVE, it is rendered with parameters from element-1 in the
array. As loop continues to execute, the 3DPRIMITVES are rendered
based on the parameters fetched from subsequent elements in the
array.
[0211] In another example, in tile based rendering, a command
buffer may be rendered multiple times, based on a tile count, with
some parameters changing with each rendering (e.g., a different
tile may be selected on each iteration). Loops and commands
supporting indirect data provide an efficient way to perform tile
based rendering. Without a loop construct, the tile based rendering
sequence may require significant unrolling in software of the
command sequence. For example:
Select Tile-0
Execute Batch Buffer-0
Select Tile-1
Execute Batch Buffer-0
[0212] . . .
Select Tile-N
Execute Batch Buffer-0
[0213] However, in accordance with various embodiments, the same
sequence may be efficiently executed using the above described loop
construct, where the loop count is set to the number of tiles to be
rendered. For example:
LOOP_BEGIN (Count==N)
Select Tile=N
Execute Batch Buffer-0
LOOP_END
[0214] In embodiments, the terms "engine," "manager," "module," or
"logic" may be implemented in hardware, firmware, software, or any
combination thereof. For example, these terms may refer to, be part
of, or include an application specific integrated circuit (ASIC),
an electronic circuit, a processor (shared, dedicated, or group),
and/or memory (shared, dedicated, or group) that execute one or
more software or firmware programs, a combinational logic circuit,
and/or other suitable components that provide the described
functionality.
[0215] 1. A processor comprising: a command buffer; and
[0216] a graphics command parser to: load graphics commands from
the command buffer; parse a first graphics command; store a loop
count value associated with the first graphics command; parse a
second graphics command; store a loop wrap address based on the
second graphics command; execute a command sequence identified by
the second graphics command; parse a third graphics command, the
third graphics command identifying an end of the command sequence;
set a new loop count value; and iteratively execute the command
sequence using the loop wrap address based on the new loop count
value.
[0217] 2. The processor as in example 1, wherein to set the new
loop count value, the graphics command parser decrements the loop
count value.
[0218] 3. The processor as in example 1, wherein to set the new
loop count value, the graphics command parser sets the new loop
count value to an integer value based on an output value of the
command sequence.
[0219] 4. The processor as in example 1, wherein at least one
command in the command sequence includes indirect data, and wherein
the graphics command parser determines the indirect data for the at
least one command based on a loop variable.
[0220] 5. The processor as in example 4, wherein a set of general
purpose registers are assigned for the command sequence to maintain
the loop variable, the loop count value, and the loop wrap address,
and wherein values stored in the set of general purpose registers
are updated based on execution of the command sequence.
[0221] 6. The processor as in example 4, wherein the first graphics
command is a load loop count command, the second graphics command
is a loop begin command, and the third graphics command is a loop
end command.
[0222] 7. The processor as in example 1, wherein the command
sequence includes at least one nested loop, and wherein the
graphics command parser: determines a nested loop count value and a
nested loop wrap address associated with the at least one nested
loop; and pushes the nested loop count value and the nested loop
wrap address to a loop stack.
[0223] 8. The processor as in example 7, wherein the graphics
command parser is further to: parse a loop end command in the at
least one nested loop; determine a new nested loop count value
equals zero; and pop the loop stack.
[0224] 9. The processor as in example 8, wherein the graphics
command parser is further to: parse a loop end command in the
command sequence; determine the loop stack is empty; and end
execution of the command sequence.
[0225] 10. The processor as in example 8, wherein the graphics
command parser is further to: determine a command in the command
sequence is a loop exit command; execute the loop exit command; and
jump to a graphics command following the command sequence.
[0226] 11. The processor as in example 1, wherein only the command
sequence from the command buffer is cached.
[0227] 12. A system comprising: a memory; and a graphics processor
to process graphics commands responsive to execution of an
application, the graphics processor including a graphics command
parser to: load graphics commands from a command buffer; parse a
first graphics command; store a loop count value associated with
the first graphics command; parse a second graphics command; store
a loop wrap address based on the second graphics command; execute a
command sequence identified by the second graphics command; parse a
third graphics command, the third graphics command identifying an
end of the command sequence; set a new loop count value; and
iteratively execute the command sequence using the loop wrap
address based on the new loop count value.
[0228] 13. The system as in example 12, wherein to set the new loop
count value, the graphics command parser decrements the loop count
value.
[0229] 14. The system as in example 12, wherein to set the new loop
count value, the graphics command parser sets the new loop count
value to an integer value based on an output value of the command
sequence.
[0230] 15. The system as in example 12, wherein at least one
command in the command sequence includes indirect data, and wherein
the graphics command parser determines the indirect data for the at
least one command based on a loop variable.
[0231] 16. The system as in example 15, wherein the first graphics
command is a load loop count command, the second graphics command
is a loop begin command, and the third graphics command is a loop
end command.
[0232] 17. The system as in example 12, wherein the command
sequence includes at least one nested loop, and wherein the
graphics command parser is further to: determine a nested loop
count value and a nested loop wrap address associated with the at
least one nested loop; and push the nested loop count value and the
nested loop wrap address to a loop stack.
[0233] 18. The system as in example 17, wherein the graphics
command parser is further to: parse a loop end command in the at
least one nested loop; determine a new nested loop count value
equals zero; and pop the loop stack.
[0234] 19. The system as in example 18, wherein the graphics
command parser is further to: parse a loop end command in the
command sequence; determine the loop stack is empty; and end
execution of the command sequence.
[0235] 20. A graphics command parser, comprising: fetching logic to
load graphics commands responsive to execution of an application;
loop begin/loop end logic to identify a command sequence; loop wrap
address logic to determine a loop wrap address for the command
sequence; loop count logic to determine an initial loop count value
and to set a subsequent loop count value on each loop iteration;
and execution logic to iteratively execute the command sequence
using the loop wrap address based on the initial loop count value
and subsequent loop count value.
[0236] 21. The graphics command parser as in example 20 wherein the
loop begin/loop end logic further identifies at least one nested
loop in the command sequence, the loop wrap address logic further
determines a nested loop wrap address associated with the at least
one nested loop, and the loop count logic further determines a
nested loop count value associated with the at least one nested
loop.
[0237] 22. The graphics command parser as in example 21 further
comprising:
[0238] nested loop stack logic to push the nested loop count value
and the nested loop wrap address to a loop stack.
[0239] 23. The graphics command parser as in example 22 wherein the
loop count logic further determines a new nested loop count value
equals zero and the nested loop stack logic further pops the loop
stack.
[0240] Embodiments of the invention may include various steps,
which have been described above. The steps may be embodied in
machine-executable instructions which may be used to cause a
general-purpose or special-purpose processor to perform the steps.
Alternatively, these steps may be performed by specific hardware
components that contain hardwired logic for performing the steps,
or by any combination of programmed computer components and custom
hardware components.
[0241] As described herein, instructions may refer to specific
configurations of hardware such as application specific integrated
circuits (ASICs) configured to perform certain operations or having
a predetermined functionality or software instructions stored in
memory embodied in a non-transitory computer readable medium. Thus,
the techniques shown in the figures can be implemented using code
and data stored and executed on one or more electronic devices
(e.g., an end station, a network element, etc.). Such electronic
devices store and communicate (internally and/or with other
electronic devices over a network) code and data using computer
machine-readable media, such as non-transitory computer
machine-readable storage media (e.g., magnetic disks; optical
disks; random access memory; read only memory; flash memory
devices; phase-change memory) and transitory computer
machine-readable communication media (e.g., electrical, optical,
acoustical or other form of propagated signals--such as carrier
waves, infrared signals, digital signals, etc.).
[0242] In addition, such electronic devices typically include a set
of one or more processors coupled to one or more other components,
such as one or more storage devices (non-transitory
machine-readable storage media), user input/output devices (e.g., a
keyboard, a touchscreen, and/or a display), and network
connections. The coupling of the set of processors and other
components is typically through one or more busses and bridges
(also termed as bus controllers). The storage device and signals
carrying the network traffic respectively represent one or more
machine-readable storage media and machine-readable communication
media. Thus, the storage device of a given electronic device
typically stores code and/or data for execution on the set of one
or more processors of that electronic device. Of course, one or
more parts of an embodiment of the invention may be implemented
using different combinations of software, firmware, and/or
hardware. Throughout this detailed description, for the purposes of
explanation, numerous specific details were set forth in order to
provide a thorough understanding of the present invention. It will
be apparent, however, to one skilled in the art that the invention
may be practiced without some of these specific details. In certain
instances, well known structures and functions were not described
in elaborate detail in order to avoid obscuring the subject matter
of the present invention. Accordingly, the scope and spirit of the
invention should be judged in terms of the claims which follow.
* * * * *