U.S. patent application number 17/740453 was filed with the patent office on 2022-08-25 for semiconductor device.
This patent application is currently assigned to Samsung Electronics Co., Ltd.. The applicant listed for this patent is Samsung Electronics Co., Ltd.. Invention is credited to Sanghoon BAEK, Seung Young LEE.
Application Number | 20220270969 17/740453 |
Document ID | / |
Family ID | 1000006320688 |
Filed Date | 2022-08-25 |
United States Patent
Application |
20220270969 |
Kind Code |
A1 |
BAEK; Sanghoon ; et
al. |
August 25, 2022 |
SEMICONDUCTOR DEVICE
Abstract
A semiconductor device is provided. The semiconductor device
includes a first-direction plurality of wirings extending in a
first direction, and a second-direction plurality of wiring
extending in a second direction intersecting the first direction.
The first-direction plurality of wirings that extend in the first
direction includes gate wirings spaced apart from each other in the
second direction by a gate pitch, first wirings above the gate
wirings spaced apart from each other in the second direction by a
first pitch, second wirings above the first wirings spaced apart
from each other in the second direction by a second pitch, and
third wirings above the second wirings spaced apart from each other
in the second direction by a third pitch. A ratio between the gate
pitch and the second pitch is 6:5.
Inventors: |
BAEK; Sanghoon; (Seoul,
KR) ; LEE; Seung Young; (Seoul, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Samsung Electronics Co., Ltd. |
Suwon-si |
|
KR |
|
|
Assignee: |
Samsung Electronics Co.,
Ltd.
Suwon-si
KR
|
Family ID: |
1000006320688 |
Appl. No.: |
17/740453 |
Filed: |
May 10, 2022 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
16910748 |
Jun 24, 2020 |
|
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17740453 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 23/5283
20130101 |
International
Class: |
H01L 23/528 20060101
H01L023/528 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 4, 2019 |
KR |
10-2019-0159496 |
Claims
1. A method of designing a semiconductor device, the method
comprising: performing a simulation a number of times, the
simulation including, holding a gate pitch of a plurality of gate
wiring patterns constant, varying a first pitch of first wiring
patterns of a plurality of first-direction wiring patterns that
extend in a first direction, varying a second pitch of second
wiring patterns of the plurality of first-direction wiring patterns
that extend in the first direction, and varying a third pitch of
third wiring patterns of the plurality of first-direction wiring
patterns that extend in the first direction; for each of the number
of times, calculating a calculated least common multiple of the
gate pitch, the first pitch, the second pitch, and the third pitch;
determining a determined least common multiple from among the
calculated least common multiples; and designing a plurality of
layers based on the determined least common multiple.
2. The method of claim 1, further comprising: performing an optical
proximity correction on the plurality of layers; and manufacturing
a plurality of photomasks based on the optical proximity correction
of each of the plurality of layers.
3. A method of fabricating a semiconductor device comprising: using
the plurality of photomasks of claim 2 in a plurality of exposure
and etching processes.
4. The method of claim 3, wherein the using the plurality of
photomasks comprises: performing a gate exposure and etch process
on a substrate to form a plurality of gate wiring lines using a
gate photomask that includes the plurality of gate wiring patterns;
subsequently, performing a first exposure and etch process on the
substrate to form a plurality of first wiring lines using a first
photomask that includes the plurality of first wiring patterns;
subsequently, performing a second exposure and etch process on the
substrate to form a plurality of second wiring lines using a second
photomask that includes the plurality of second wiring patterns;
and subsequently, performing a third exposure and etch process on
the substrate to form a plurality of third wiring lines using a
third photomask that includes the plurality of third wiring
patterns.
5. The method of claim 4, further comprising, after the performing
the gate exposure and etch process and before the performing the
first exposure and etch process: performing a fourth exposure and
etch process to form a first power line, a plurality of fourth
wiring lines, and a second power line, wherein the first power
line, the plurality of fourth wiring lines, and the second power
line extending in a second direction crossing the first direction,
the first power line, the plurality of fourth wiring lines, and the
second power line at a same level of the semiconductor device.
6. A method of fabricating a semiconductor device, the method
including: performing a high-level design of the semiconductor
device to generate a netlist of the semiconductor device; designing
a plurality of first-direction layouts of the semiconductor device
based on the netlist; performing optical proximity corrections on
the plurality of first-direction layouts; generating a plurality of
photomasks based on the optical proximity correction; and
fabricating the semiconductor device based on the plurality of
photomasks, wherein the designing the plurality of first-direction
layouts includes repeating a simulation a number of times, the
simulation including, holding a first pitch of a first one of the
plurality of first-direction layouts constant, varying other
pitches of other ones of the plurality of first-direction layouts,
and calculating a least common multiple of the first pitch and each
of the other pitches.
7. The method of claim 6, wherein the first pitch corresponds to a
gate pitch.
8. The method of claim 6, further comprising: designing a plurality
of second-direction layouts of the semiconductor device based on
the netlist, wherein the designing the plurality of
second-direction layouts includes repeating a second simulation a
number of times, the second simulation including, holding a second
pitch of a second one of the plurality of second-direction layouts
constant, varying other pitches of other ones of the plurality of
second-direction layouts, and calculating a second least common
multiple of the second pitch and each of the other pitches.
Description
[0001] This application is a divisional application of U.S.
application Ser. No. 16/910,748, filed on Jun. 24, 2020, which
claims priority under 35 U.S.C. 119 from Korean Patent Application
No. 10-2019-0159496 filed on Dec. 4, 2019 in the Korean
Intellectual Property Office, the disclosure of each of which is
incorporated herein by reference in its entirety.
BACKGROUND
[0002] Example embodiments relate, in general, to a semiconductor
device.
[0003] Due to characteristics such as miniaturization,
multi-functionality and/or low manufacturing cost, semiconductor
devices have been spotlighted as an important factor in the
electronics industry. The semiconductor devices may be classified
into a semiconductor memory device that stores (logical) data, a
semiconductor logical device that performs arithmetic processing on
logical data, a hybrid semiconductor device that includes a storage
element and a logical element, and/or the like.
[0004] As the electronics industry is highly developed, demands
and/or desires for improved characteristics of semiconductor
devices gradually increase. For example, demands for high
reliability, high speed, and/or multi-function of the semiconductor
devices gradually increase. In order to satisfy such required
characteristics, structures in the semiconductor device become
gradually complicated and highly integrated.
[0005] As the structures are complicated, layout of the wirings in
the semiconductor device becomes important. One reason may be that,
when wirings are efficiently placed, many wirings may be placed in
a limited area.
SUMMARY
[0006] Aspects of the example embodiments provide a semiconductor
device having an improved wiring density.
[0007] However, aspects of example embodiments are not restricted
to the one set forth herein. The above and other aspects of some
example embodiments will become more apparent to one of ordinary
skill in the art to which some example embodiments pertains by
referencing the detailed description of some example embodiments
given below.
[0008] According to some example embodiments, there is provided a
semiconductor device comprising a first-direction plurality of
wirings extending in a first direction, and a second-direction
plurality of wiring extending in a second direction intersecting
the first direction. The first-direction plurality of wirings that
extend in the first direction includes gate wirings spaced apart
from each other in the second direction by a gate pitch, first
wirings above the gate wirings spaced apart from each other in the
second direction by a first pitch, second wirings above the first
wirings spaced apart from each other in the second direction by a
second pitch, and third wirings above the second wirings spaced
apart from each other in the second direction by a third pitch. A
ratio between the gate pitch and the second pitch is 6:5.
[0009] According to some example embodiments, there is provided a
semiconductor device comprising a first-direction plurality of
wirings extending in a first direction, and a second-direction
plurality of wirings extending in a second direction intersecting
the first direction. The second-direction plurality of wirings that
extend in the second direction includes fourth wirings spaced apart
from each other in the first direction by a fourth pitch, fifth
wirings above the fourth wirings spaced apart from each other in
the first direction by a fifth pitch, sixth wirings above the fifth
wirings spaced apart from each other in the first direction by a
sixth pitch, and seventh wirings above the sixth wirings spaced
apart from each other in the first direction by a seventh pitch. A
ratio between the fourth pitch and the fifth pitch is 5:4.
[0010] According to some example embodiments, there is provided a
semiconductor device comprising a first-direction plurality of
wirings extending in a first direction, and a second-direction
plurality of wirings extending in a second direction that
intersects the first direction. The first-direction plurality of
wirings includes gate wirings spaced apart from each other in the
second direction by a gate pitch, and first wirings above the gate
wirings spaced apart from each other in the second direction by a
first pitch. The second direction plurality of wirings includes
fourth wirings above the gate wirings and below the first wirings
and spaced apart from each other in the first direction by a fourth
pitch, and fifth wirings above the first wirings and spaced apart
from each other in the first direction by a fifth pitch. A ratio
between the gate pitch and the first pitch is 6:4, and a ratio
between the fourth pitch and the fifth pitch is 5:4.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The above and other aspects and features of the present
invention will become more apparent by describing in detail
exemplary embodiments thereof with reference to the attached
drawings, in which:
[0012] FIG. 1 is a wiring layout of a semiconductor device
according to some example embodiments;
[0013] FIG. 2 is a layout separately showing wirings extending in a
Y direction among the wirings of FIG. 1;
[0014] FIG. 3 is a cross-sectional view taken along a line P-P' of
FIG. 1;
[0015] FIG. 4 is a layout separately showing a gate wiring of FIG.
2;
[0016] FIG. 5 is a layout separately showing a M2 wiring of FIG.
2;
[0017] FIG. 6 is a layout separately showing a M4 wiring of FIG.
2;
[0018] FIG. 7 is a layout separately showing a D6 wiring of FIG.
2;
[0019] FIG. 8 is a layout separately showing wirings extending in a
X direction among the wirings of FIG. 1;
[0020] FIG. 9 is a cross-sectional view taken along a line Q-Q' of
FIG. 8;
[0021] FIG. 10 is a layout separately showing a M1 wiring of FIG.
8;
[0022] FIG. 11 is a layout separately showing a M3 wiring of FIG.
8;
[0023] FIG. 12 is a layout separately showing a M5 wiring of FIG.
8;
[0024] FIG. 13 is a layout separately showing a D7 wiring of FIG.
8;
[0025] FIGS. 14 and 15 are diagrams showing a process of
determining a wiring pitch of a semiconductor device according to
some example embodiments;
[0026] FIG. 16 is a layout for explaining a semiconductor device
according to some example embodiments;
[0027] FIG. 17 is a cross-sectional view taken along a line A-A of
FIG. 16;
[0028] FIG. 18 is a cross-sectional view taken along a line B-B of
FIG. 16;
[0029] FIG. 19 is a cross-sectional view taken along a line C-C of
FIG. 16;
[0030] FIG. 20 is a cross-sectional view taken along a line D-D of
FIG. 16;
[0031] FIG. 21 is a cross-sectional view taken along a line E-E of
FIG. 16;
[0032] FIGS. 22 and 23 are cross-sectional views showing a
semiconductor device according to some example embodiments;
[0033] FIG. 24 is a block diagram of a computer system for
executing a layout design of the semiconductor device according to
some example embodiments; and
[0034] FIG. 25 is a flowchart for explaining a layout design method
and a manufacturing method of the semiconductor device according to
some example embodiments.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0035] Some example embodiments will be described below with
reference to the attached drawings.
[0036] FIG. 1 is a wiring layout of a semiconductor device
according to some embodiments.
[0037] Referring to FIG. 1, a semiconductor device 1 may include a
plurality of wirings PC, M2, M4 and D6 that each extend in a first
direction (e.g., a Y direction, hereinafter Y), and a plurality of
wirings M1, M3, M5 and D7 that each extend in a second direction
(e.g., a X direction, hereinafter X). The first direction Y and the
second direction X may intersect with one another. For example, the
first direction Y may be perpendicular to the second direction
X.
[0038] Although it is not shown in detail in FIG. 1, such a
plurality of wirings PC, M2, M4, D6, M1, M3, M5 and D7 may be used
to provide, for example, a voltage and/or a signal to a functional
component, such as a bipolar and/or MOSFET N-type and/or P-type
transistor and/or a capacitor placed in the semiconductor device 1.
Accordingly, the plurality of wirings PC, M2, M4, D6, M1, M3, M5
and D7 may be placed between the plurality of functional components
and a plurality of conductive contacts and/or vias associated with
the transistors/capacitors/etc.
[0039] In the semiconductor device 1 according to some example
embodiments, the wirings PC, M2, M4 and D6 extending in the first
direction Y may be placed such that pitches of each of the wirings
PC, M2, M4 and D6 have a constant relationship with each other. In
addition, the plurality of wirings M1, M3, M5 and D7 extending in
the second direction X may be placed such that pitches of each of
the wiring M1, M3, M5 and D7 have a constant relationship with each
other. Herein, pitches may refer to center-to-center distances of
neighboring wirings.
[0040] Hereinafter, the relationship between the wirings PC, M2, M4
and D6 extending in the first direction Y will be described first
with reference to FIGS. 2 to 7.
[0041] FIG. 2 is a layout separately showing wirings extending in
the Y direction among the wirings of FIG. 1. FIG. 3 is a
cross-sectional view taken along a line P-P' of FIG. 2. FIG. 4 is a
layout separately showing the gate wirings of FIG. 2. FIG. 5 is a
layout separately showing an M2 wiring of FIG. 2. FIG. 6 is a
layout separately showing an M4 wiring of FIG. 2. FIG. 7 is a
layout separately showing a D6 wiring of FIG. 2.
[0042] Referring to FIGS. 2 to 7, the wirings PC, M2, M4 and D6
extending in the first direction Y may include a gate wiring PC, a
first wiring M2, a second wiring, M4 and a third wiring D6.
[0043] The gate wiring PC may be placed below the first wiring M2.
The gate wiring PC may be placed on/above the substrate 100, and
the first wiring M2 may be placed on the gate wiring PC. In FIGS. 2
to 7, although other components (e.g., transistors, vias,
conductive contacts and/or the like) placed in the semiconductor
device are not shown to more easily explain the relationship
between the wirings PC, M2, M4 and D6, for example, the gate wiring
PC may be electrically connected to a gate electrode of a
transistor and/or used as a gate electrode of the transistor. Each
of the wirings PC, M2, M4, and D6 may include a conductivity
material. For example, the gate wiring PC may include a conductive
material such as doped and/or undoped polysilicon and/or a metal
such as tungsten. The wirings M2, M4, and D6 may include material
such as aluminum and/or copper.
[0044] A width of the first wiring M2 placed above the gate wiring
PC may be greater than a width of the gate wiring PC.
[0045] The second wiring M4 may be placed on the first wiring M2.
In some example embodiments, although the width of the second
wiring M4 may be substantially the same as the width of the first
wiring M2, example embodiments are not limited thereto, and the
width of the first wiring M2 may be greater than and/or less than
the width of the second wiring M4.
[0046] The third wiring D6 may be placed on the second wiring M4.
In some example embodiments, although the width of the third wiring
D6 may be wider than the widths of the gate wiring PC, the first
wiring M2, and the second wiring M4, example embodiments are not
limited thereto.
[0047] The gate wiring PC, the first wiring M2, the second wiring
M4, and the third wiring D6 may be insulated from each other by the
interlayer insulating film 10. The interlayer insulating film 10
may include a plurality of layers, and may include an insulator
such as a silicon-oxide insulator; however, example embodiments are
not limited thereto.
[0048] Referring to FIG. 4, the gate wirings PC may be spaced apart
from each other by a gate pitch GP and extend in the first
direction Y. The gate wirings PC may be spaced apart from each
other by the gate pitch GP in the second direction X and extend in
the first direction Y side by side. For example, a center of each
of the gate wirings PC may be spaced apart from each other in the
second direction X by the gate pitch GP. Alternatively or
additionally, a left edge (resp. a right edge) of each of the gate
wirings PC may be spaced apart from a left edge (resp. right edge)
of a neighboring gate wiring PC by the gate pitch GP.
[0049] Referring to FIG. 5, the first wirings M2 may be spaced
apart from each other by a first pitch P2 and extend in the first
direction Y. The first wirings M2 may be spaced apart from each
other by the first pitch P2 in the second direction X and extend in
the first direction Y side by side. For example, a center of each
of the first wirings M2 may be spaced apart from each other in the
second direction X by the first pitch P2. Alternatively or
additionally, a left edge (resp. a right edge) of each of the first
wirings M2 may be spaced apart from a left edge (resp. right edge)
of a neighboring first wiring M2 by the first pitch P2.
[0050] Referring to FIG. 6, the second wirings M4 may be spaced
apart from each other by a second pitch P4 and extend in the first
direction Y. The second wirings M4 may be spaced apart from each
other by the second pitch P4 in the second direction X and extend
in the first direction Y side by side. For example, a center of
each of the second wirings M4 may be spaced apart from each other
in the second direction X by the second pitch P4. Alternatively or
additionally, a left edge (resp. a right edge) of each of the
second wirings M4 may be spaced apart from a left edge (resp. right
edge) of a neighboring second wiring M4 by the second pitch P4.
[0051] Referring to FIG. 7, the third wirings D6 may be spaced
apart from each other by a third pitch P6 and may extend in the
first direction Y. The third wirings D6 may be spaced apart from
each other by the third pitch P6 in the second direction X and
extend in the first direction Y side by side. For example, a center
of each of the third wirings D6 may be spaced apart from each other
in the second direction by the third pitch P6. Alternatively or
additionally, a left edge (resp. a right edge) of each of the third
wirings D4 may be spaced apart from a left edge (resp. right edge)
of a neighboring third wiring D4 by the third pitch P6
[0052] In some example embodiment, a ratio, e.g. a gear ratio,
between the gate pitch GP of the gate wiring PC and the first pitch
P2 of the first wiring M2 satisfies 6:4. For example, the gate
pitch GP is greater than the first pitch P2. Here, the ratio of 6:4
is a numerical value excluding a process error generated in a
fabrication/manufacturing process of the gate wiring PC and the
first wiring M2. Therefore, although the ratio may be slightly
changed to 6.01:4, 6:3.99, etc. depending on the actual
manufacturing process of the gate wiring PC and the first wiring
M2, such numerical values may be considered that the ratio is
designed and manufactured to 6:4 in accordance with the technical
idea of example embodiments.
[0053] All of the ratios described below should be understood as
numerical values that may not necessarily reflect small differences
in fabrication/process conditions that may occur in the actual
fabrication/manufacturing processes.
[0054] Further, in some example embodiments, a ratio, e.g. a gear
ratio between the gate pitch GP of the gate wiring PC, the first
pitch P2 of the first wiring M2, and the second pitch P4 of the
second wiring M4 is/satisfies 6:4:5. The second pitch P4 may be
greater than the first pitch P2, and may be less than the gate
pitch GP.
[0055] Further, in some example embodiments, a ratio, e.g. a gear
ratio between the gate pitch GP of the gate wiring PC, the first
pitch P2 of the first wiring M2, the second pitch P4 of the second
wiring M4 and the third pitch P6 of the third wiring D6
is/satisfies 6:4:5:9. The third pitch P6 may be greater than the
gate pitch GP, the first pitch P2, and the second pitch P4.
[0056] In some example embodiments, a ratio, e.g. a gear ratio
between the gate pitch GP of the gate wiring PC and the second
pitch P4 of the second wiring M4 satisfies 6:5.
[0057] In some example embodiments, a ratio, e.g. a gear ratio
between the gate pitch GP of the gate wiring PC, the second pitch
P4 of the second wiring M4, and the third pitch P6 of the third
wiring D6 is/satisfies 6:5:9.
[0058] In some example embodiments, a ratio, e.g. a gear ratio
between the gate pitch GP of the gate wiring PC and the third pitch
P6 of the third wiring D6 satisfies 6:9.
[0059] In some example embodiments, a ratio, e.g. a gear ratio
between the first pitch P2 of the first wiring M2 and the second
pitch P4 of the second wiring M4 satisfies 4:5.
[0060] In some example embodiments, a ratio, e.g. a gear ratio
between the first pitch P2 of the first wiring M2, the second pitch
P4 of the second wiring M4, and the third pitch P6 of the third
wiring D6 satisfies 4:5:9.
[0061] In some example embodiments, a ratio, e.g. a gear ratio
between the second pitch P4 of the second wiring M4 and the third
pitch P6 of the third wiring D6 satisfies 5:9.
[0062] On the other hand, any combination of ratios not described
above in which the ratio between the gate pitch GP of the gate
wiring PC, the first pitch P2 of the first wiring M2, the second
pitch P4 of the second wiring M4 and the third pitch P6 of the
third wiring D6 satisfies 6:4:5:9 may also be implemented according
to example embodiments.
[0063] The relationship between the wirings M1, M3, M5 and D7
extending in the second direction X will be described below with
reference to FIGS. 8 to 13.
[0064] FIG. 8 is a layout separately showing wirings extending in
the X direction among the wirings of FIG. 1. FIG. 9 is a
cross-sectional view taken along a line Q-Q' of FIG. 8. FIG. 10 is
a layout separately showing the M1 wiring of FIG. 8. FIG. 11 is a
layout separately showing the M3 wiring of FIG. 8. FIG. 12 is a
layout separately showing the M5 wiring of FIG. 8. FIG. 13 is a
layout separately showing the D7 wiring of FIG. 8.
[0065] Referring to FIGS. 8 to 13, the wirings M1, M3, M5 and D7
extending in the second direction X may include a fourth wiring M1,
a fifth wiring M3, a sixth wiring M5 and a seventh wiring D7.
[0066] Although the fourth wiring M1 differs in an extending
direction from the gate wiring PC, the fourth wiring M1 may be
placed on/above the gate wiring PC. There may be a contact and/or a
via (not shown) connecting at least one of the fourth wiring M1 to
at least one of the gate wiring PC; however, example embodiments
are not limited thereto. FIG. 9 also conceptually shows the wirings
PC, M2, M4 and D6 extending in the first direction Y to explain a
height relationship between the wirings M1, M3, M5 and D7 extending
in the second direction X and the wirings PC, M2, M4 and D6
extending in the first direction Y.
[0067] Similarly, although FIGS. 8 to 13 do not show other
components (e.g., transistors, vias, conductive contacts, etc.)
placed in the semiconductor device to more easily explain the
relationship between the wirings M1, M3, M5 and D7, for example,
the fourth wiring M1 may be used as a wiring which electrically
connects a drain of a first transistor and a source of a second
transistor to each other.
[0068] The fifth wiring M3 may be placed on the fourth wiring M1.
Further, although the fifth wiring M3 differs in the extending
direction from the first wiring M2, the fifth wiring M3 may be
placed on the first wiring M2. There may be a contact and/or a via
(not shown) connecting at least one of the fifth wiring M3 to at
least one of the first wiring M2; however, example embodiments are
not limited thereto. In some example embodiments, although the
width of the fifth wiring M3 may be narrower than the width of the
fourth wiring M1, example embodiments are not limited thereto.
[0069] The sixth wiring M5 may be placed on the fifth wiring M3.
Further, the sixth wiring M5 differs in the extending direction
from the second wiring M4, the sixth wiring M5 may be placed on the
second wiring M4. There may be a contact and/or a via (not shown)
connecting at least one of the sixth wiring M5 to at least one of
the second wiring M4; however, example embodiments are not limited
thereto. In some example embodiments, although the width of the
sixth wiring M5 may be wider than the widths of the fourth wiring
M1 and the fifth wiring M3, example embodiments are not limited
thereto.
[0070] The seventh wiring D7 may be placed on the sixth wiring M5.
Further, although the seventh wiring D7 differs in the extending
direction from the third wiring D6, the seventh wiring D7 may be
placed on the third wiring D6. There may be a contact and/or a via
(not shown) connecting at least one of the seventh wiring D7 to at
least one of the third wiring D6; however, example embodiments are
not limited thereto. In some embodiments, although the width of the
seventh wiring D7 may be wider than the widths of the fourth wiring
M1, the fifth wiring M3, and the sixth wiring M5, the embodiments
are not limited thereto.
[0071] The fourth wiring M1, the fifth wiring M3, the sixth wiring
M5, and the seventh wiring D7 may be insulated from each other by
the interlayer insulating film 10. Further, the fourth wiring M1,
the fifth wiring M3, the sixth wiring M5, and the seventh wiring D7
may be insulated from the gate wiring PC, the first wiring M2, the
second wiring M4, and the third wiring D6 by the interlayer
insulating film 10. In some example embodiments, there may be
vias/contacts (not shown) connecting each wiring PC, M1, M2, M3,
M4, M5, D6, and D7 to each other.
[0072] Referring to FIG. 10, the fourth wirings M1 may be spaced
apart from each other by a fourth pitch P1 and may extend in the
second direction X. The fourth wirings M1 may be spaced apart from
each other by the fourth pitch P1 in the first direction and may
extend in the second direction X side by side. For example, a
center of each of the fourth wirings M1 may be spaced apart from
each other in the first direction Y by the fourth pitch P1.
Alternatively or additionally, a top edge (resp. a bottom edge) of
each of the fourth wirings M1 may be spaced apart from a top edge
(resp. bottom edge) of a neighboring fourth wiring M1 by the fourth
pitch P1.
[0073] Referring to FIG. 11, the fifth wirings M3 may be spaced
apart from each other by a fifth pitch P3 and may extend in the
second direction X. The fifth wiring M3 may be spaced apart from
each other by the fifth pitch P3 in the first direction Y and may
extend in the second direction X side by side. For example, a
center of each of the fifth wirings M3 may be spaced apart from
each other in the first direction Y by the fifth pitch P3.
Alternatively or additionally, a top edge (resp. a bottom edge) of
each of the fifth wirings M3 may be spaced apart from a top edge
(resp. bottom edge) of a neighboring fifth wiring M3 by the fifth
pitch P3.
[0074] Referring to FIG. 12, the sixth wirings M5 may be spaced
apart from each other by a sixth pitch P5 and may extend in the
second direction X. The sixth wiring M5 may be spaced apart from
each other by the sixth pitch P5 in the first direction Y and may
extend in the second direction X side by side. For example, a
center of each of the sixth wirings M5 may be spaced apart from
each other in the first direction Y by the sixth pitch P5.
Alternatively or additionally, a top edge (resp. a bottom edge) of
each of the sixth wirings M5 may be spaced apart from a top edge
(resp. bottom edge) of a neighboring sixth wiring M5 by the sixth
pitch P5.
[0075] Referring to FIG. 13, the seventh wirings D7 may be spaced
apart from each other by a seventh pitch P7 and may extend in the
second direction X. The seventh wiring D7 may be spaced apart from
each other by the seventh pitch P7 in the first direction Y and may
extend in the second direction X side by side. For example, a
center of each of the seventh wirings D7 may be spaced apart from
each other in the first direction Y by the seventh pitch P6.
Alternatively or additionally, a top edge (resp. a bottom edge) of
each of the seventh wirings D7 may be spaced apart from a top edge
(resp. bottom edge) of a neighboring seventh wiring D7 by the
seventh pitch P7.
[0076] In some example embodiments, a ratio between the fourth
pitch P4 of the fourth wiring M1 and the fifth pitch P3 of the
fifth wiring M3 satisfies 5:4. The fourth pitch P4 may be greater
than the fifth pitch P3.
[0077] Further, in some example embodiments, a ratio between the
fourth pitch P4 of the fourth wiring M1, the fifth pitch P3 of the
fifth wiring M3, and the sixth pitch P5 of the sixth wiring M5
is/satisfies 5:4:6. The sixth pitch P5 may be greater than the
fourth pitch P4, and the fifth pitch P3.
[0078] Further, in some example embodiments, a ratio between the
fourth pitch P4 of the fourth wiring M1, the fifth pitch P3 of the
fifth wiring M3, the sixth pitch P5 of the sixth wiring M5 and the
seventh pitch P7 of the seventh wiring D7 is/satisfies
5:4:6:10.
[0079] In some example embodiments, a ratio between the fourth
pitch P4 of the fourth wiring M1 and the sixth pitch P5 of the
sixth wiring M5 is/satisfies 5:6.
[0080] In some example embodiments, a ratio between the fourth
pitch P4 of the fourth wiring M1, the sixth pitch P5 of the sixth
wiring M5, and the seventh pitch P7 of the seventh wiring D7
is/satisfies 5:6:10.
[0081] In some example embodiments, a ratio between the fourth
pitch P4 of the fourth wiring M1 and the seventh pitch P7 of the
seventh wiring D7 is/satisfies 5:10.
[0082] In some example embodiment, a ratio between the fifth pitch
P3 of the fifth wiring M3 and the sixth pitch P5 of the sixth
wiring M5 is/satisfies 4:6.
[0083] Further, in some example embodiment, a ratio between the
fifth pitch P3 of the fifth wiring M3, the sixth pitch P5 of the
sixth wiring M5, and the seventh pitch P7 of the seventh wiring D7
is/satisfies 4:6:10.
[0084] In some example embodiments, a ratio between the sixth pitch
P5 of the sixth wiring M5 and the seventh pitch P7 of the seventh
wiring D7 is/satisfies 6:10.
[0085] On the other hand, the ratios of any combination not
described above in which the ratio between the fourth pitch P4 of
the fourth wiring M1, the fifth pitch P3 of the fifth wiring M3,
the sixth pitch P5 of the sixth wiring M5, and the seventh pitch P7
of the seventh wiring D7 satisfies 5:4:6:10 can also be implemented
under example embodiments.
[0086] FIGS. 14 and 15 are diagrams showing a process of
determining a wiring pitch of the semiconductor device according to
some example embodiments.
[0087] Referring to FIG. 14, in order to determine a good, e.g. an
optimal, ratio between the gate pitch GP of the gate wiring PC, the
first pitch P2 of the first wiring M2, the second pitch P4 of the
second wiring M4, and the third pitch P6 of the third wiring D6
extending in the first direction Y, a simulation may be performed n
times (n is a very large natural number), while changing first to
third pitches P2, P4, and P6.
[0088] Specifically, least common multiples (LCM) M1 to Mn may be
obtained for each case, while changing the first pitch P2 of the
first wiring M2 from a1 to an, changing the second pitch P4 of the
second wiring M4 from b1 to bn, and changing the third pitch P6 of
the third wiring D6 from c1 to cn.
[0089] A case having the smallest least common multiple among the
least common multiples (LCM) M1 to Mn calculated for each case
corresponds to a case in which a large number, e.g. the most,
wirings may be placed within a predetermined (or, alternatively,
variably determined) limited area. At this time, a ratio between
the gate pitch GP of the gate wiring PC, the first pitch P2 of the
first wiring M2, the second pitch P4 of the second wiring M4, and
the third pitch P6 of the third wiring D6 satisfies 6:4:5:9.
[0090] Similarly, referring to FIG. 15, in order to obtain an
improved, e.g. the optimal, ratio between the fourth pitch P4 of
the fourth wiring M1, the fifth pitch P3 of the fifth wiring M3,
the sixth pitch P5 of the sixth wiring M5 and the seventh pitch P7
of the seventh wiring D7 extending in the second direction X,
simulation may be performed n times, while changing the fifth to
seventh pitches P3, P5 and P7.
[0091] Specifically, the least common multiples (LCM) L1 to Ln were
obtained for each case, while changing the fifth pitch P3 of the
fifth wiring M3 from d1 to dn, changing the sixth pitch P5 of the
sixth wiring M5 from e1 to en, and changing the seventh pitch P7 of
the seventh wiring D7 from f1 to fn.
[0092] A case having the smallest least common multiple among the
least common multiples (LCM) L1 to Ln calculated for each case is a
case in which the most wirings may be placed within a limited area.
At this time, the ratio between the fourth pitch P4 of the fourth
wiring M1, the fifth pitch P3 of the fifth wiring M3, the sixth
pitch P5 of the sixth wiring M5, and the seventh pitch P7 of the
seventh wiring D7 satisfies 5:4:6:10.
[0093] For example, when the wirings PC, M2, M4 and D6 extending in
the first direction Y are placed in the semiconductor device such
that the ratio between the gate pitch GP of the gate wiring PC, the
first pitch P2 of the first wiring M2, the second pitch P4 of the
second wiring M4, and the third pitch P6 of the third wiring D6
satisfies 6:4:5:9, since as many wirings as possible may be
provided within a limited area, the wiring density of the
semiconductor device may be improved. The wiring density of the
semiconductor device may be improved even in a case wherein a ratio
between pitches of lower wiring such as gate pitch GP to pitches of
wirings above such as first pitch P2 does not monotonically
vary.
[0094] Further, when the wirings M1, M3, M5 and D7 extending in the
second direction X are placed in the semiconductor device such that
the ratio between the fourth pitch P4 of the fourth wiring M1, the
fifth pitch P3 of the fifth wiring M3, the sixth pitch P5 of the
sixth wiring M5, and the seventh pitch P7 of the seventh wiring D7
satisfies 5:4:6:10, since as many wirings as possible may be placed
within a limited area, the wiring density of the semiconductor
device can be improved.
[0095] Although other components placed in the semiconductor device
are not shown and explained to intensively explain only the
relationship between the wirings above, a practical implementation
example of the gate wiring PC and the fourth wiring M1 described
above will be described below. However, example embodiments are not
limited thereto.
[0096] On the other hand, in the following drawings, although a
fin-type transistor FinFET including a fin-type pattern-shaped
channel region is shown as an example of a semiconductor device,
example embodiments are not limited thereto. The semiconductor
device according to some embodiments may include a tunneling
transistor (FET), a transistor including a nanowire, a transistor
including a nanosheet or a three-dimensional (3D) transistor. In
addition, the semiconductor device according to some embodiments
may include a bipolar junction transistor, a lateral double
diffusion transistor (LDMOS), and/or the like.
[0097] FIG. 16 is a layout for explaining the semiconductor device
according to some embodiments. FIG. 17 is a cross-sectional view
taken along a line A-A of FIG. 16. FIG. 18 is a cross-sectional
view taken along a line B-B of FIG. 16. FIG. 19 is a
cross-sectional view taken along a line C-C of FIG. 16. FIG. 20 is
a cross-sectional view taken along a line D-D of FIG. 16. FIG. 21
is a cross-sectional view taken along a line E-E of FIG. 16.
[0098] Referring to FIGS. 16 to 21, the semiconductor device
according to some example embodiments may be formed on a substrate
100.
[0099] The substrate 100 may be or include bulk silicon or
silicon-on-insulator (SOI). Alternatively or additionally, the
substrate 100 may be or include a silicon substrate or may include,
but is not limited to, other materials, for example, silicon
germanium, silicon germanium on insulator (SGOI), indium
antimonide, lead telluride, indium arsenide, phosphide, indium,
gallium arsenide and/or gallium antimonide.
[0100] The substrate 100 may include a first active region AR1 and
a second active region AR2. For convenience of description,
hereinafter the first active region AR1 will be described as a PFET
region and the second active region AR2 will be described as an
NFET region; however, example embodiments are not limited
thereto.
[0101] In some example embodiments, the first active region AR1 and
the second active region AR2 may be separated by an element
separation film 12. For example, as shown in FIGS. 19 to 21, the
element separation film 12 extends in the second direction X and
may separate the first active region AR1 and the second active
region AR2.
[0102] A plurality of active patterns F1 to F4 may be formed on the
substrate 100. For example, first and second active patterns F1 and
F2 may be formed on the first active region AR1, and third and
fourth active patterns F3 and F4 may be formed on the second active
region AR2. In some example embodiments, each of the active
patterns F1 to F4 may include a fin-type pattern protruding from an
upper surface of the substrate 100.
[0103] The first to fourth active patterns F1 to F4 may be spaced
apart from each other and may extend side by side. For example,
each of the first to fourth active patterns F1 to F4 may extend in
the second direction X. Further, the first to fourth active
patterns F1 to F4 may be sequentially arranged along the first
direction Y. In some example embodiments, the first to fourth
active patterns F1 to F4 may be formed over the first to third cell
regions CR1 to CR3, respectively.
[0104] In some example embodiments, the first cell separation film
11a and the second cell separation film 11b may intersect the first
to fourth active patterns F1 to F4. The first cell separation film
11a and the second cell separation film 11b may define first to
third cell regions CR3 across the first to fourth active patterns
F1 to F4. For example, as shown in FIGS. 17 and 18, the first cell
separation film 11a may define the first cell region CR1 and the
second cell region CR2 across the first active pattern F1. Further,
the second cell separation film 11b may define a first cell region
CR1 and a third cell region CR3 across the first active pattern
F1.
[0105] The field insulating film 105 may be formed on the substrate
100. In some example embodiments, the field insulating film 105 may
surround some of the side surfaces of the first to fourth active
patterns F1 to F4. For example, as shown in FIG. 19, some of the
first to fourth active patterns F1 to F4 may protrude upward from
the field insulating film 105.
[0106] The field insulating film 105 may include, for example, but
not limited to, at least one of silicon oxide (SiO.sub.2), silicon
nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride
(SiOCN) or a combination thereof.
[0107] The gate electrodes G1 to G3 may intersect the first to
fourth active patterns F1 to F4, respectively. In some example
embodiments, the gate electrodes G1 to G3 may correspond to the
gate wirings (PC of FIG. 4) described above. Also, in some example
embodiments, although it is not shown in detail, the gate wiring
(PC of FIG. 4) described above may correspond to wirings
electrically connected to the gate electrodes G1 to G3.
[0108] The gate electrodes G1 to G3 may each include a gate
conductive film 130. The gate conductive film 130 may include, for
example, but is not limited to, at least one of Ti, Ta, W, Al, Co,
or a combination thereof. The gate conductive film 130 may include,
for example, doped or undoped single-crystal or polysilicon or
doped or undoped single-crystal or polysilicon-germanium other than
metal.
[0109] Although the gate conductive film 130 is shown as a single
film in the drawings, example embodiments not limited thereto.
Unlike the shown example, the gate conductive film 130 may be
formed by stacking a plurality of conductive materials. For
example, the gate conductive film 130 may include a work function
adjusting film for adjusting a work function, and/or a filling
conductive film which fills a space formed by the work function
adjusting film. The work function adjusting film may include, for
example, at least one of TiN, TaN, TiC, TaC, TiAlC, or a
combination thereof. The filling conductive film may include, for
example, W and/or Al.
[0110] The gate conductive film 130 may be formed through, for
example, but is not limited to, a replacement process.
[0111] In some example embodiments, a first dummy gate electrode
DG1 and a second dummy gate electrode DG2 each intersecting the
first to fourth active patterns F1 to F4 may be formed. The first
dummy gate electrode DG1 may extend in the first direction Y
between the first cell region CR1 and the second cell region CR2,
and the second dummy gate electrode DG2 may extend in the first
direction Y between the first cell region CR1 and the third cell
region CR3.
[0112] In some example embodiments, the first dummy gate electrode
DG1 may be formed on the first cell separation film 11a, and the
second dummy gate electrode DG2 may be formed on the second
separation film 11b. In some example embodiments, the first dummy
gate electrode DG1 and the second dummy gate electrode DG2 may be
omitted. For example, the first cell separation film 11a and the
second cell separation film 11b may be formed to fill a region
occupied by the first dummy gate electrode DG1 and the second dummy
gate electrode DG2.
[0113] A gate dielectric film 120 may be interposed between the
first to fourth active patterns F1 to F4 and the gate conductive
film 130. For example, the gate dielectric film 120 may extend
along the side wall and the bottom surface of the gate conductive
film 130. However, example embodiments are not limited thereto, and
the gate dielectric film 120 may extend only along the bottom
surface of the gate conductive film 130.
[0114] In some example embodiments, a part of the gate dielectric
film 120 may be interposed between the field dielectric film 105
and the gate conductive film 130. For example, as shown in FIG. 19,
the gate dielectric film 120 may extend along the upper surface of
the field insulating film 105.
[0115] The gate dielectric film 120 may include, for example, at
least one of silicon oxide, silicon oxynitride, silicon nitride, or
a high-k material having a higher dielectric constant than silicon
oxide. The high-k material may include, for example, but is not
limited to, hafnium oxide.
[0116] The gate spacer 140 may be formed on the substrate 100 and
the field insulating film 105. Further, the gate spacer 140 may
extend along both sides of the gate conductive film 130.
Accordingly, the gate spacer 140 may intersect the first to fourth
active patterns F1 to F4. For example, the gate spacer 140 may
extend in the first direction Y.
[0117] The gate spacer 140 may include, for example, but is not
limited to, at least one of silicon oxide, silicon nitride, silicon
oxynitride, or combinations thereof.
[0118] A gate capping pattern 150 may cover the upper surface of
the gate conductive film 130. For example, the gate capping pattern
150 may extend along the upper surface of the gate conductive film
130. In addition, the gate capping pattern 150 may extend in the
first direction Y.
[0119] A first source/drain region 160 may be formed on the first
active region AR1. For example, the first source/drain region 160
may be formed in the first and second active patterns F1 and F2 on
both sides of the gate conductive film 130. However, the first
source/drain region 160 may be insulated from the gate conductive
film 130. For example, the first source/drain region 160 may be
spaced apart from the gate conductive film 130 by the gate spacer
140.
[0120] A second source/drain region 260 may be formed on the second
active region AR2. For example, the second source/drain region 260
may be formed in the third and fourth active patterns F3 and F4 on
both sides of the gate conductive film 130. However, the second
source/drain region 260 may be insulated from the gate conductive
film 130. For example, the second source/drain region 260 may be
spaced apart from the gate conductive film 130 by the gate spacer
140.
[0121] Each of the first source/drain region 160 and the second
source/drain region 260 may include an epitaxial layer, e.g. a
doped or undoped heterogeneous or homogenous epitaxial layer,
formed in each of the first to fourth active patterns F1 to F4.
[0122] When the semiconductor device formed in the first active
region AR1 is a PFET, the first source/drain region 160 may include
a p-type impurity and/or an impurity for preventing or reducing the
amount of diffusion of the p-type impurity. For example, the first
source/drain region 160 may include at least one of a group-III
element such as B, In, Ga, and Al, or a combination thereof, and
may include a group-IV element such as C, Ge, and/or Sn, however,
example embodiments are not limited thereto.
[0123] When the semiconductor device formed in the second active
region AR2 is an NFET, the second source/drain region 260 may
include an n-type impurity and/or an impurity for preventing or
reducing the amount of diffusion of the n-type impurity. For
example, the second source/drain region 260 may include at least
one of a group-V element such as P, Sb, zAs or a combination
thereof, and may include a group-IV element such as C, Ge, and/or
Sn; however, example embodiments are not limited thereto.
[0124] Although each of the first source/drain region 160 and the
second source/drain region 260 is shown as a single film example
embodiments not limited thereto. For example, the first
source/drain region 160 and the second source/drain region 260 may
be formed of multi-films each containing concentrations of
impurities different from each other.
[0125] A plurality of interlayer insulating films 110, 210, 310 and
410 may be formed on the substrate 100. For example, first to
fourth interlayer insulating films 110, 210, 310 and 410
sequentially stacked may be formed on the substrate 100.
[0126] In some example embodiments, the first interlayer insulating
film 110 and the second interlayer insulating film 210 may be
formed to cover the field insulating film 105, the first
source/drain region 160, the second source/drain region 260, the
gate spacer 140 and the gate capping pattern 150. For example, the
first interlayer insulating film 110 may cover the upper surface of
the field insulating film 105, the upper surface of the first
source/drain region 160, the upper surface of the second
source/drain region 260, and the side surface of the gate spacer
140. Further, for example, the second interlayer insulating film
210 may cover the upper surface of the gate capping pattern 150 and
the upper surface of the first interlayer insulating film 110.
[0127] The first to fourth interlayer insulating films 110, 210,
310 and 410 may include, for example, at least one of silicon
oxide, silicon nitride, silicon oxynitride, and/or a low-k material
having a lower dielectric constant than silicon oxide.
[0128] Further, in some example embodiments, a plurality of
source/drain contacts CA11 to CA33 may penetrate the first
interlayer insulating film 110 and the second interlayer insulating
film 210 and may be connected to the first source/drain region 160
and/or the second source/drain region 260. For example, the second,
fourth and eighth source/drain contacts CA12, CA22 and CA32 may be
connected to the first source/drain region 160. Also, for example,
the third, sixth, and ninth source/drain contacts CA13, CA23 and
CA33 may be connected to the second source/drain region 260. In
some example embodiments, the first, fourth, and seventh
source/drain contacts CA11, CA21 and CA31 may be connected to both
the first source/drain region 160 and the second source/drain
region 260. The plurality of contacts CA11 to CA33 may be or
include doped polysilicon and/or a metal such as tungsten; however,
example embodiments are not limited thereto.
[0129] In some example embodiments, a plurality of source/drain
vias VA11 to VA33 may penetrate the third interlayer insulating
film 310 and may be connected to the source/drain contacts CA11 to
CA33. The source/drain vias VA11 to VA33 may include a metal such
as tungsten; however, example embodiments are not limited
thereto.
[0130] In some example embodiments, a plurality of gate vias VB1 to
VB3 may penetrate the gate capping pattern 150, the second
interlayer insulating film 210, and the third interlayer insulating
film 310 and may be connected to the gate electrodes G1 to G3. The
gate vias VB1 to VB3 may include doped polysilicon and/or a metal
such as tungsten; however, example embodiments are not limited
thereto.
[0131] In some example embodiments, the plurality of wiring
patterns M1 may be placed at the same level as each other. When
used herein, the expression "placed at the same level" means
formation at the same height on the basis of the upper surface of
the substrate 100. Further, when used herein, the term "same" is
meant to include not only completely the same thing, but also a
slight difference that may occur due to a margin in a process or
the like.
[0132] In some example embodiments, the plurality of wiring
patterns M1 may correspond to the fourth wiring pattern (M1 of FIG.
10) described above.
[0133] For example, as shown in FIGS. 16 and 17, a first connection
wiring CW1 is formed in the fourth interlayer insulating film 410,
and may be connected to the fourth source/drain via VA21 and the
first gate via VB1. Further, a second wiring OW is formed in the
fourth interlayer insulating film 410 and may be connected to the
seventh source/drain via VA31.
[0134] For example, as shown in FIGS. 16 and 18, a first wiring 1 W
is formed in the fourth interlayer insulating film 410 and may be
connected to the second gate via VB2. Further, a second connection
wiring CW2 is formed in the fourth interlayer insulating film 410
and may be connected to the first source/drain via VA11 and the
third gate via VB3.
[0135] Further, in some example embodiments, the plurality of
wiring patterns M1 may be formed by the same
fabrication/manufacturing process.
[0136] In some example embodiments, the plurality of wiring
patterns M1 may be placed at the same level as the first power
supply wiring VDD and/or the second power supply wiring VSS.
[0137] For example, as shown in FIGS. 16 and 21, the first power
supply wiring VDD is formed in the fourth interlayer insulating
film 410, and may be connected to the second, fifth, and eighth
source/drain vias VA12, VA22 and VA32. Further, the second power
supply wiring VSS is formed in the fourth interlayer insulating
film 410, and may be connected to the third, sixth, and ninth
source/drain vias VA13, VA23 and VA33.
[0138] Further, in some example embodiments, the plurality of
wiring patterns M1 may be formed at the same level as the first
power supply wiring VDD and/or the second power supply wiring
VSS.
[0139] Thus, it may be possible to provide a semiconductor device
in which the power loss and the PnR resource loss are reduced, e.g.
by reducing the use of the additional upper wiring.
[0140] In some example embodiments, the source/drain contacts CA11
to CA33 may include a first barrier film 190 and a first filling
film 192, respectively. The first barrier film 190 may extend along
an upper surface of the first source/drain region 160, an upper
surface of the second source/drain region 260, a side surface of
the first interlayer insulating film 110, and a side surface of the
second interlayer insulating film 210. The first filling film 192
may fill a space formed by the first barrier film 190.
[0141] In some example embodiments, the source/drain vias VA11 to
VA33 may include a second barrier film 290 and a second filling
film 292, respectively. The second barrier film 290 may extend
along the upper surfaces of the source/drain contact CA11 to CA33
and the side surface of the third interlayer insulating film 310.
The second filling film 292 may fill the space formed by the second
barrier film 290.
[0142] In some example embodiments, the gate vias VB1 to VB3 may
include a third barrier film 390 and a third filling film 392,
respectively. The third barrier film 390 may extend along on the
upper surfaces of the gate electrodes, the side surface of the gate
capping pattern 150, the side surface of the second interlayer
insulating film 210 and the side surface of the third interlayer
insulating film 310. The third filling film 392 may fill the space
formed by the third barrier film 390.
[0143] In some example embodiments, the first power supply wiring
VDD, the second power supply wiring VSS, and the plurality of
wiring patterns M1 may include a fourth barrier film 490 and a
fourth filling film 492, respectively. The fourth barrier film 490
may extend along the upper surfaces of the source/drain vias VA11
to VA33, the upper surfaces of the gate vias VB1 to VB3, the upper
surface of the third interlayer insulating film 310, and the side
surface of the fourth interlayer insulating film 410. The fourth
filling film 492 may fill the space formed by the fourth barrier
film 490.
[0144] The first to fourth barrier films 490 may include a metal or
a metal nitride for preventing or reducing the amount of diffusion
of the first to fourth filling films 492. For example, the first to
fourth barrier films 490 may include, but is not limited to, at
least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel
(Ni), cobalt (Co), platinum (Pt), an alloy thereof, or a nitride
thereof.
[0145] The first to fourth filling films 492 may include, but is
not limited to, at least one of aluminum (Al), copper (Cu),
tungsten (W), molybdenum (Mo), cobalt (Co), or an alloy
thereof.
[0146] The source/drain vias VA11 to VA33, the gate vias VB1 to
VB3, the first power supply wiring VDD, the second power supply
wiring VSS and the wiring patterns M1 may be formed by, for
example, but is not limited to, a single damascene process. For
example, the source/drain vias VA11 to VA33, the gate vias VB1 to
VB3, the first power supply wiring VDD, the second power supply
wiring VSS and the wiring patterns M1 may be formed by, for
example, a dual damascene process or another wiring process.
[0147] Another example embodiment of the gate wiring PC and the
fourth wiring M1 described above will be described below with
reference to FIGS. 22 and 23. First, repeated parts of the contents
described above with reference to FIGS. 16 to 21 will be briefly
described or omitted.
[0148] FIGS. 22 and 23 are cross-sectional views for explaining a
semiconductor device according to some embodiments.
[0149] FIG. 22 is a cross-sectional view taken along a line A-A of
FIG. 16, and FIG. 23 is a cross-sectional view taken along a line
C-C of FIG. 16.
[0150] Referring to FIGS. 22 and 23, in the semiconductor device
according to some embodiments, the first to fourth active patterns
F1 to F4 each include a plurality of wire patterns 114, 116 and
118.
[0151] For example, the first to fourth active patterns F1 to F4
may include first to third wire patterns 114, 116 and 118 which are
sequentially stacked on the substrate 100 and are spaced apart from
each other. For example, the first wire pattern 114 may be spaced
apart from the substrate 100 in a third direction Z, the second
wire pattern 116 may be spaced apart from the first wire pattern
114 in the third direction Z, and the third wire pattern 118 may be
spaced apart from the second wire pattern 116 in the third
direction Z.
[0152] Each of the first to third wire patterns 114, 116 and 118
may extend in the second direction X. Further, the first to third
wire patterns 114, 116 and 118 may penetrate the first to third
gate electrodes G1 to G3, respectively. Therefore, as shown in FIG.
22, the first to third gate electrodes G1 to G3 may surround the
outer surfaces of the first to third wire patterns 114, 116 and
118, respectively.
[0153] Although the cross sections of the first to third wire
patterns 114, 116 and 118 are shown as a rectangular shape in FIG.
23, example embodiments are not limited thereto. For example, the
cross sections of the first to third wire patterns 114, 116 and 118
may be other polygonal shape or a circular shape, respectively.
[0154] In some example embodiments, the first to fourth active
patterns F1 to F4 may each further include a fin type pattern 112
protruding from the upper surface of the substrate 100 and
extending in the second direction X. The fin type pattern 112 may
be placed, for example, below the first wire pattern 114.
[0155] FIG. 24 is a block diagram of a computer system for
executing a layout design of a semiconductor device according to
some embodiments.
[0156] Referring to FIG. 24, the computer system may include a CPU
11, a working memory 30, an I/O device 50, and an auxiliary storage
70. Here, the shown computer system may be provided as a dedicated
device for layout design of the semiconductor device according to
some example embodiments. In some example embodiments, the computer
system may include various design and verification simulation
programs.
[0157] The CPU 11 may execute computer-readable instructions such
as software (an application program, an operating system, a device
driver and/or the like) to be executed on the computer system. When
executed by the CPU 11, the computer-readable instructions may
cause the CPU to perform various functions. The CPU 11 may execute
then operating system loaded into the working memory 30. The CPU 11
may execute various applications (an application program) to be
driven on the basis of the operating system. For example, the CPU
11 may execute a layout design tool 32, a placement and routing
tool 34 and/or an OPC tool 36 loaded into the working memory
30.
[0158] The operating system and/or the application programs may be
loaded into the working memory 30. An operating system image (not
shown) stored in the auxiliary storage 70 when the computer system
starts up may be loaded into the working memory 30 on the basis of
a booting sequence. The operating system may support all I/O
operations of the computer system.
[0159] A layout design tool 32 for layout design of the
semiconductor device according to some embodiments may be loaded
from the auxiliary storage 70 into the working memory 30.
Subsequently, the placement and routing tool 34 for placing the
designed standard cells, rearranging the internal wiring patterns
in the placed standard cells, and routing the placed standard cells
may be loaded into the working memory 30 from the auxiliary storage
70.
[0160] When an internal wiring pattern in a standard cell thus
placed is placed and/or rearranged, the ratio between the pitches
of the wiring patterns described above may be applied.
[0161] Specifically, the wiring patterns may be placed or
rearranged in the standard cells such that the ratio between the
gate pitch GP of the gate wiring PC, the first pitch P2 of the
first wiring M2, the second pitch P4 of the second wiring M4 and
the third pitch P6 of the third wiring D6 extending in the first
direction Y satisfies 6:4:5:9. Further, the wiring patterns may be
placed or rearranged in the standard cells such that the ratio
between the fourth pitch P4 of the fourth wiring M1, the fifth
pitch P3 of the fifth wiring M3, the sixth pitch P5 of the sixth
wiring M5 and the seventh pitch P7 of the seventh wiring D7
extending in the second direction X satisfies 5:4:6:10.
[0162] Subsequently, an OPC tool 36 for performing optical
proximity correction (OPC) on the designed layout data may be
loaded from the auxiliary storage 70 to the working memory 30.
[0163] The I/O device 50 may control user input and output from
user interface devices. For example, the I/O device 50 includes a
keyboard and a monitor, and may receive input of information from a
user. The user may receive input of information on the
semiconductor region or data paths that require adjusted operating
characteristics, using the I/O device 50. Also, the processing
course or the processing result of the OPC tool 36 may be displayed
through the I/O device 50.
[0164] The auxiliary storage 70 may be provided as a storage medium
of a computer system. The auxiliary storage 70 may store
application programs, an operating system image, and various
data.
[0165] A system interconnector 90 may be or include a system bus
for providing a network inside the computer system. The CPU 11, the
working memory 30, the I/O device 50, and the auxiliary storage 70
are electrically connected through the system interconnector 90,
and data may be exchanged each other.
[0166] FIG. 25 is a flowchart for explaining a layout design method
and a manufacturing method of the semiconductor device according to
some embodiments.
[0167] Referring to FIG. 25, a high level design of a semiconductor
integrated circuit may be executed using the computer system
described with reference to FIG. 24 (S10). The high level design
may mean description of the integrated circuit to be designed in a
parent language of a computer language. For example, a parent
language such as a C language may be used for the high level
design. Circuits designed by the high level design may be more
specifically expressed by register transfer level (RTL) coding or
simulation. Subsequently, code generated by the register transfer
level coding is converted into a Netlist, and may be synthesized by
the entire semiconductor element. A synthesized schematic circuit
is verified by a simulation tool, and an adjustment course may be
accompanied depending on the verification result.
[0168] Subsequently, a layout design for implementing a logically
completed semiconductor integrated circuit on a silicon substrate
may be performed (S20). For example, the layout design may be
performed with reference to the schematic circuit synthesized by
the high level design or the Netlist corresponding thereto. The
layout design may include a routing procedure for placing and
connecting various standard cells provided from a cell library in
accordance with a specified design rule.
[0169] The layout may be or include a procedure for actually
defining the form or size of a pattern for forming a transistor and
metal wirings to be formed on the silicon substrate. For example,
in order to actually form an inverter circuit on the silicon
substrate, layout patterns as a PFET, an NFET, a P-WELL, an N-WELL,
a gate electrode, and wiring patterns to be placed thereon may be
appropriately placed, e.g. designed for placement on reticles used
in fabrication of the semiconductor device.
[0170] When the layout patterns are placed in this way, the ratio
between the pitches of the wiring patterns described above may be
applied.
[0171] Specifically, the layout patterns may be placed so that the
ratio between the gate pitch GP of the gate wiring PC, the first
pitch P2 of the first wiring M2, the second pitch P4 of the second
wiring M4, and the third pitch P6 of the third wiring D6 extending
in the first direction Y satisfies 6:4:5:9. Further, the layout
patterns may be placed so that the ratio between the fourth pitch
P4 of the fourth wiring M1, the fifth pitch P3 of the fifth wiring
M3, the sixth pitch P5 of the sixth wiring M5 and the seventh pitch
P7 of the seventh wiring D7 extending in the second direction X
satisfies 5:4:6:10.
[0172] Subsequently, routing on the selected and placed standard
cells may be performed. Specifically, upper wirings (routing
patterns) may be placed on the placed standard cells. By executing
the routing, the placed standard cells may be interconnected
according to the design.
[0173] After routing, the layout may be verified whether there is a
portion which violates the design rules. Items to be verified may
include a DRC (Design Rule Check), an ERC (Electrical Rule Check),
a LVS (Layout vs Schematic), and/or the like.
[0174] Subsequently, an optical proximity correction (OPC)
procedure may be performed (S30). The layout patterns provided
through a layout design may be implemented on a silicon substrate,
using a photolithography process. At this time, the optical
proximity correction may be a technique for correcting a distortion
phenomenon that may occur in a photolithography process.
[0175] Subsequently, a photomask may be manufactured on the basis
of the layout changed by the optical proximity correction (S40).
The photomask may be manufactured, for example, in a manner of
drawing the layout patterns, using a chromium film applied on a
glass substrate.
[0176] Subsequently, a semiconductor element may be manufactured
using the generated photomask (S50). In the
fabrication/manufacturing process of the semiconductor element
using a photomask, various types of exposure and etching processes
may be repeated. The form of the patterns formed at the time of
layout design may be continuously formed on the silicon substrate
through such processes.
[0177] In concluding the detailed description, those skilled in the
art will appreciate that many variations and modifications may be
made to the preferred embodiments without substantially departing
from the principles of example embodiments. Therefore, the
disclosed example embodiments are used in a generic and descriptive
sense only and not for purposes of limitation.
* * * * *