U.S. patent application number 17/736515 was filed with the patent office on 2022-08-18 for display panel.
The applicant listed for this patent is LG Display Co., Ltd.. Invention is credited to JungSun BEAK, Seongjoo LEE, Sunmi LEE.
Application Number | 20220262868 17/736515 |
Document ID | / |
Family ID | 1000006307962 |
Filed Date | 2022-08-18 |
United States Patent
Application |
20220262868 |
Kind Code |
A1 |
BEAK; JungSun ; et
al. |
August 18, 2022 |
Display Panel
Abstract
The present disclosure relates to a display panel. More
specifically, the display panel is configured to surround an
opening area, includes a reflective electrode including an inclined
surface, and therefore provides increased luminous efficiency.
Inventors: |
BEAK; JungSun; (Paju-si,
KR) ; LEE; Seongjoo; (Paju-si, KR) ; LEE;
Sunmi; (Paju-si, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
LG Display Co., Ltd. |
Seoul |
|
KR |
|
|
Family ID: |
1000006307962 |
Appl. No.: |
17/736515 |
Filed: |
May 4, 2022 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
16548680 |
Aug 22, 2019 |
11355565 |
|
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17736515 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 51/5225 20130101;
H01L 2251/558 20130101; H01L 27/3246 20130101; H01L 27/326
20130101; H01L 51/5209 20130101 |
International
Class: |
H01L 27/32 20060101
H01L027/32; H01L 51/52 20060101 H01L051/52 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 17, 2018 |
KR |
10-2018-0163602 |
Claims
1. An organic light emitting display panel comprising: a substrate
including an active area and a non-active area, the non-active area
including a pad area; a transistor in the active area of the
substrate, the transistor comprising a first node, a second node,
and a third node; an insulating film disposed over the transistor
in the active area of the substrate, the insulating film including
at least one hole; a sub-pixel electrically connected to the
transistor, the sub-pixel including a plurality of light emitting
areas and a plurality of separation areas in the active area of the
substrate; and a plurality of pad electrodes disposed in the pad
area, the plurality of pad electrodes comprising a first pad
electrode and a second pad electrode, wherein the plurality of pad
electrodes in the pad area are disposed on a same layer with each
of the first node, the second node, and the third node in the
active area.
2. The organic light emitting display panel according to claim 1,
wherein the sub-pixel comprises a first electrode, an organic
emitting layer, and a second electrode on the insulating film.
3. The organic light emitting display panel according to claim 2,
further comprising a bank layer disposed on the insulating film and
partially on the first electrode, the bank layer having a first
inclined surface and a second inclined surface disposed in a
concavity of the insulating film.
4. The organic light emitting display panel according to claim 1,
wherein the second node or the third node of the transistor and the
first electrode are electrically connected in the at least one hole
of the insulating film.
5. The organic light emitting display panel according to claim 1,
further comprising an auxiliary electrode disposed in a separation
area from the plurality of separation areas, the auxiliary
electrode on a same layer with the first pad electrode in the pad
area, and the first node in the active area.
6. The organic light emitting display panel according to claim 5,
wherein the auxiliary electrode contacts the second electrode in
the at least one hole of the insulating film.
7. The organic light emitting display panel according to claim 1,
wherein each of the first pad electrode and the second pad
electrode in the pad area are disposed on the same layer with each
of the first node and the second node or the third node in the
active area, respectively.
8. The organic light emitting display panel according to claim 7,
further comprising an interlayer insulating film on the substrate,
the interlayer insulating film disposed on the first pad electrode
without covering a portion of a top surface of the first pad
electrode.
9. The organic light emitting display panel according to claim 8,
wherein the second pad electrode is disposed on the interlayer
insulating film and contacts the first pad electrode in the pad
area.
10. The organic light emitting display panel according to claim 1,
further comprising a gate insulating film disposed on the first
node in the active area and on the first pad electrode in the pad
area.
11. The organic light emitting display panel according to claim 10,
further comprising an activation layer disposed on the substrate in
the active area, the activation layer disposed between the
substrate and the gate insulating film.
12. The organic light emitting display panel according to claim 3,
wherein the bank layer comprises a third inclined surface, a fourth
inclined surface, and a fifth inclined surface in a separation area
from the plurality of separation areas.
13. The organic light emitting display panel according to claim 12,
wherein the third inclined surface and the fourth inclined surface
of the bank layer is in a first hole of the insulating film, and
the fifth inclined surface of the bank layer in in line with an
inclined surface of the insulating film in a second hole of the
insulating film.
14. The organic light emitting display panel according to claim 13,
wherein the second electrode is disposed on the fifth inclined
surface of the bank layer and the inclined surface of the
insulating film in the second hole of the insulating film.
15. The organic light emitting display panel according to claim 12,
wherein the first electrode contacts the first inclined surface of
the bank layer in the at least one of the plurality of light
emitting areas, and contacts the third inclined surface and the
fourth inclined surface of the bank layer in at least one of the
plurality of separation areas.
16. The organic light emitting display panel according to claim 1,
wherein the first electrode is disposed in the plurality of light
emitting areas and the plurality of separation areas.
17. The organic light emitting display panel according to claim 8,
wherein the interlayer insulating film is disposed on the first
node of the transistor in the active area, the interlayer
insulating film covering a top surface of the first node.
18. The organic light emitting display panel according to claim 1,
further comprising a storage capacitor disposed on the substrate in
the active area, the storage capacitor comprising a first storage
capacitor and a second storage capacitor, wherein each of the first
pad electrode and the second pad electrode in the pad area are
disposed on a same layer with each of the first storage capacitor
and the second storage capacitor in the active area,
respectively.
19. The organic light emitting display panel according to claim 18,
further comprising a passivation layer covering the storage
capacitor in the active area.
20. The organic light emitting display panel according to claim 19,
wherein the plurality of the pad electrodes in the pad area are not
covered by the passivation layer.
21. The organic light emitting display panel according to claim 19,
wherein the passivation layer partially covers the second node or
the third node of the transistor of the sub-pixel.
22. The organic light emitting display panel according to claim 6,
further comprising a passivation layer disposed on the transistor
of the sub-pixel, the passivation layer partially covering the
auxiliary electrode.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of U.S. patent
application Ser. No. 16/548,680 filed on Aug. 22, 2019 which claims
the priority benefit of Republic of Korea Patent Application No.
10-2018-0163602, filed on Dec. 17, 2018 in the Korean Intellectual
Property Office, each of which is incorporated herein by reference
in its entirety.
BACKGROUND
Field of the Disclosure
[0002] The present disclosure relates to a display device and a
display device including the same.
Description of the Background
[0003] As the advent of information society, there have been
growing needs for various display panels for using in display
devices, lighting devices, or the like. Among various display
panels and display devices including the display panels, there is
an increasing demand for organic light emitting display panels
which are advantageous in a reduction in overall weight and
thickness because the organic light emitting display panels does
not require an additional light source.
[0004] However, when the organic light emitting display panel
including an organic light emitting layer emitting light is
operated, a light extraction efficiency of the organic light
emitting display panel may be decreased and corresponding luminance
efficiency may be lowered because some of the light emitted from
the organic light emitting layer cannot be emitted outside the
organic light emitting display panel, and becomes trapped inside
the organic light emitting display device.
SUMMARY
[0005] Embodiments relate to a display panel comprising an overcoat
layer, a first electrode, a bank layer, an organic light emitting
layer, a second electrode and a transistor. The overcoat layer has
a first flat area having a first thickness, a second flat area
having a second thickness thicker than the first thickness, and an
inclined area between the first flat area and the second flat area.
The first electrode is on the first flat area, the inclined area
and at least a part of the second flat area of the overcoat layer.
The first electrode is reflective of light and has an inclined
surface on the inclined area of the overcoat layer. The bank layer
covers a portion of the first flat area of the overcoat layer, the
inclined area of the overcoat layer, and at least a portion of the
second flat area of the overcoat layer. The organic light emitting
layer is on the first electrode. The second electrode is on the
organic light emitting layer and the bank layer. At least part of a
transistor overlaps the first flat area of the overcoat layer. The
transistor has at least a terminal connected to the first electrode
through a contact hole under the bank layer and located outside the
first flat area.
[0006] In one or more embodiments, a thickness of the bank layer in
the first area in a direction parallel to a surface of a substrate
is less than or equal to 3.2.mu.m.
[0007] In one or more embodiments, the thickness of the bank layer
in the first area is larger than or equal to 0.1 .mu.m.
[0008] In one or more embodiments, a difference between the first
thickness and the second thickness is larger than or equal to 0.7
.mu.m.
[0009] In one or more embodiments, a difference between the first
thickness and the second thickness is less than or equal to 10
.mu.m.
[0010] In one or more embodiments, the first area has a polygonal
shape.
[0011] In one or more embodiments, the polygonal shape is an
octagonal shape.
[0012] In one or more embodiments, the bank layer is transparent to
visible light.
[0013] In one or more embodiments, the first electrode comprises a
conductive metal oxide layer and a reflective metal layer on the
conductive metal oxide layer.
[0014] In one or more embodiments, the bank layer contacts a
portion of the first electrode that is not covered by the bank in
the first area.
[0015] In one or more embodiments, the organic light emitting layer
extends from the first area to the second area via the inclined
area, the bank layer between the organic light emitting layer and
the first electrode in the inclined area and the second area.
[0016] In one or more embodiments, a portion of the bank layer is
on the inclined portion of the inclined surface of the first
electrode, a portion of the organic light emitting layer on the
portion of the bank layer is thinner than another portion of the
organic light emitting layer contacting the first electrode in the
first area.
[0017] Embodiments also relate to a display panel including an
overcoat layer on a substrate, a first electrode on the overcoat
layer, a bank layer covering a portion of the first electrode but
exposing at least another portion of the first electrode, an
organic light emitting layer on the first electrode, and a second
electrode on the organic light emitting layer and the bank layer.
The first electrode is reflective of light and has an inclined
surface. A first portion of light is emitted from the organic light
emitting layer through a flat area of the second electrode. A
second portion of light is emitted from the organic light emitting
layer and reflected by the inclined area separated from the first
portion of light.
[0018] In one or more embodiments, the portion of the first
electrode contacts a transistor via a contact hole under the bank
layer.
[0019] In one or more embodiments, the overcoat layer has a first
thickness at a portion under the organic light emitting layer and
has a second thickness that is thicker than the first thickness at
another portion not under the organic light emitting layer.
[0020] In one or more embodiments, the first portion of light from
a sub-pixel forms a main area on a viewing plane and the second
portion of light from the sub-pixel forms a supplemental area
surrounding the main area in the viewing plane.
[0021] In one or more embodiments, the supplemental areas is formed
for sub- pixels of only one or two colors.
[0022] In one or more embodiments, the supplemental area is
discontinuous.
[0023] In one or more embodiments, the supplemental area has a
shape of a closed curve.
[0024] In one or more embodiments, at least one of brightness,
shape and color coordinate of the supplemental area for the
sub-pixel is different for another sub-pixels of a different
color.
[0025] In one or more embodiments, the display panel further
comprises auxiliary electrodes connected to a subset of sub-pixels,
wherein the auxiliary electrodes are outside an area where the
organic light emitting layer is present.
[0026] In one or more embodiments, the display panel further
comprises a storage capacitor at least a part of which overlaps the
inclined surface.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] FIG. 1 is a block diagram schematically illustrating a
display device according to embodiments of the present
disclosure.
[0028] FIG. 2 is a view schematically illustrating a system
implementation of the display device according to embodiments of
the present disclosure.
[0029] FIG. 3 is a view illustrating a structure of a subpixel in
case the display panel is configured with an organic light emitting
diode (OLED) panel, according to embodiments of the present
disclosure.
[0030] FIG. 4 is a cross-sectional view illustrating the display
device according to embodiments of the present disclosure.
[0031] FIG. 5 is a view illustrating light emitted from an organic
light emitting layer of the display panel reflected from a second
inclined surface, according to embodiments of the present
disclosure.
[0032] FIG. 6 is an expanded cross-sectional view illustrating a
part of the display device according to embodiments of the present
disclosure.
[0033] FIG. 7A is a view illustrating the display panel including
an opening area and a non-opening area, according to embodiments of
the present disclosure.
[0034] FIG. 7B is a view illustrating an image of the display panel
including a first light emitting area, and a second light emitting
area capture from a viewing plane, according to embodiments of the
present disclosure.
[0035] FIG. 8 is a cross-sectional view illustrating the display
device according to embodiments of the present disclosure.
[0036] FIG. 9 is a cross-sectional view illustrating a part of the
display device according to embodiments of the present
disclosure.
DETAILED DESCRIPTION
[0037] Hereinafter, the present preferred embodiments of the
disclosure will be described in detail with reference to the
accompanying drawings. In denoting elements of the drawings by
reference numerals, the same elements will be referenced by the
same reference numerals although the elements are illustrated in
different drawings. Further, in the following description of the
disclosure, detailed description of known functions and
configurations incorporated herein may be omitted when it may make
the subject matter of the disclosure rather unclear.
[0038] Terms, such as first, second, A, B, (a), or (b) may be used
herein to describe elements of the disclosure. Each of the terms is
not used to define essence, order, sequence, or number of an
element, but is used merely to distinguish the corresponding
element from another element. When it is mentioned that an element
is "connected" or "coupled" to another element, it should be
interpreted that another element may be "interposed" between the
elements or the elements may be "connected" or "coupled" to each
other via another element as well as that one element is directly
connected or coupled to another element. When it is described that
an element is "located", "disposed", "arranged", "formed", or the
like over another element, it should be interpreted that not only
the element is directly contacted on the another element, but
further another element may be "interposed" between the element and
the another element.
[0039] That is, it is noted that a connection or a coupling between
an element and another element may be described in such a manner
that the element is located, disposed, or formed over the another
element, as an equivalent meaning.
[0040] FIG. 1 is a block diagram schematically illustrating a
configuration of a display device according to embodiments of the
present disclosure. The display device according to embodiments of
the present disclosure may be a display device with a display
panel, or may further include or be included in a lighting
device/apparatus/system, a luminescence device/apparatus/system, or
the like. Hereinafter, for convenience of description and ease of
the understanding, discussions are conducted based on the display
device with the display panel. However, the following description
may be applicable to identically or similarly to various
devices/apparatuses/systems with functionalities for displaying
images, such as, the lighting device/apparatus/system, the
luminescence device/apparatus/system, or the like.
[0041] In accordance with embodiments of the present disclosure,
the display device may include a panel PNL for displaying images or
emitting light, and a driving circuit (or driver) for driving the
panel PNL.
[0042] The panel PNL may include a plurality of data lines DL and a
plurality of gate lines, and include a plurality of subpixels SP
that is defined by the plurality of data lines DL and the plurality
of gate lines GL and that is arranged in a matrix form.
[0043] The plurality of data lines DL and the plurality of gate
lines GL may cross each other and be arranged in the panel PNL. For
example, the plurality of gate lines GL may be arranged in a first
direction or on one of a row or a column, and the plurality of data
lines DL may be arranged in a second direction or on the other of
the row or the column. Hereinafter, for convenience of description
and ease of the understanding, discussions are conducted on an
example of the plurality of gate lines GL arranged on a row and the
plurality of data lines DL arranged on a column.
[0044] Depending on a structure or arrangements of subpixels, one
or more types of signal line may be disposed other than the
plurality of data lines DL and the plurality of gate lines GL. For
example, the display panel may further include at least one driving
voltage line, at least one reference voltage line, at least one
common voltage line, or the like.
[0045] The panel PNL may be various types of panel, such as a
liquid crystal display LCD panel, an organic light emitting diode
OLED panel, or the like.
[0046] For example, one or more different types of signal line may
be disposed in the panel PNL depending on a structure of subpixels,
a type of panel (e.g., LCD panel, OLED panel, or the like), or the
like. In the present disclosure, the signal line may denote a term
including an electrode to which a signal is applied.
[0047] The panel PNL may include an active area A/A for displaying
an image and a non-active area N/A for not displaying an image.
Here, the non-active area N/A may be referred to as a bezel area or
an edge area of the panel or the display device.
[0048] A plurality of subpixels SP is arranged in the active area
A/A for displaying images.
[0049] At least one pad, such as conductive trace, electrically
connected to a data driver DDR is disposed in the non-active area
N/A, and a plurality of data link lines may be disposed in the
non-active area N/A for electrically connecting the pad to the
plurality of data lines DL. In this case, the plurality of data
link lines may be a part of the plurality of data lines DL
extending to the non-active area N/A, or be separate patterns
electrically connected to the plurality of data lines DL.
[0050] In addition, the non-active area N/A further may include
gate-driving-related lines for delivering a voltage (signal) needed
for driving at least one gate of at least one transistor for
driving at least one subpixel from the pad electrically connected
to the data driver DDR to a gate driver GDR. For example, the
gate-driving-related lines may include clock lines for delivering
clock signals, gate voltage lines for delivering gate voltages
(VGH, VGL), gate driving control signal lines for delivering
various control signals needed for generating scan signals, or the
like. The gate-driving-related lines are arranged in the non-
active area N/A, unlike gate lines GL arranged in the active area
A/A.
[0051] The driving circuit may include the data driver DDR for
driving the plurality of data lines DL, the gate driver GDR for
driving the plurality of gate lines GL, and a controller CTR for
controlling the data driver DDR and the gate driver GDR.
[0052] The data driver DDR may drive the plurality of data lines DL
by outputting data voltages to the plurality of data lines DL.
[0053] The gate driver GDR may drive the plurality of gate lines GL
by outputting scan signals to the plurality of gate lines GL.
[0054] The controller CTR may provide various control signals DCS,
GCS needed for driving and/or operating the data driver DDR and the
gate driver GDR, and control the driving and/or operating of the
data driver DDR and the gate driver GDR. In addition, the
controller CTR may provide image data DATA to the data driver
DDR.
[0055] The controller CTR starts scanning operation according to
timing processed in each frame, converts image data input from
other devices or image providing sources to a data signal form used
in the data driver DDR and then outputs resulting image data from
the converting, and controls the driving of at least one data line
at a pre-configured time aligned with the scanning operation.
[0056] In order to control the data driver DDR and the gate driver
GDR, the controller CTR receives a timing signal, such as, a
vertical synchronous signal Vsync, a horizontal synchronous signal
Hsync, an input data enable DE signal, a clock signal CLK, or the
like, from other devices or image providing sources, such as, a
host system, and generates various control signals and outputs the
generated signals to the data driver DDR and the gate driver
GDR.
[0057] For example, to control the gate driver GDR, the controller
CTR outputs various gate control signals GCS including a gate start
pulse GSP, a gate shift clock GSC, a gate output enable signal GOE,
or the like.
[0058] In addition, to control data driver(DDR), the controller CTR
outputs various data control signals DCS including a source start
pulse SSP, a source sampling clock SSC, a source output enable
signal SOE, or the like.
[0059] The controller CTR may be a timing controller used in the
typical display technology or a control apparatus/device capable of
additionally performing other control functionalities in addition
to the typical function of the timing controller.
[0060] The controller CTR may be implemented as a separate unit
from the data driver DDR, or integrated with the data driver DDR
and implemented as an integrated circuit.
[0061] The data driver DDR receives image data DATA form the
controller CTR, and provides data voltages to the plurality of data
lines DL. Thus it is possible for the data driver DDR to drive the
plurality of data lines DL. Herein, the data driver DDR may also be
referred to as a "source driver."
[0062] The data driver DDR may transmit various signals to and/or
receive them from the controller CTR through various
interfaces.
[0063] The gate driver GDR sequentially drives the plurality of
gate lines GL by sequentially providing scan signals to a plurality
of gate lines GL. Herein, the gate driver GDR may also be referred
to as a "scan driver."
[0064] According to controlling of the controller CTR, the gate
driver GDR sequentially provide a scan signal, such as an
on-voltage or an off-voltage to the plurality of gate lines GL.
[0065] When a specific gate line is asserted by a scan signal from
the gate driver GDR, the data driver DDR converts image data
received from the controller into analog data voltages and provides
the resulted analog data voltages to the plurality of data lines
DL.
[0066] The data driver DDR may be located on, but not limited to,
only one side (e.g., top side or bottom side) of the panel PNL, or
in some embodiments, be located on, but not limited to, two sides
(e.g., top side and bottom side) of the panel PNL according to
driving schemes, panel design schemes, or the like.
[0067] The gate driver GDR may be located on, but not limited to,
only one side (e.g., left side or right side) of the panel PNL, or
in some embodiments, be located on, but not limited to, two sides
(e.g., left side and right side) of the panel PNL according to
driving schemes, panel design schemes, or the like.
[0068] The data driver DDR may be implemented by including one or
more source driver integrated circuits SDIC.
[0069] Each source driver integrated circuits SDIC may include a
shift register, a latch circuit, a digital to analog converter DAC,
an output buffer, or the like. In some embodiments, the data driver
DDR may further include one or more analog to digital converters
ADC.
[0070] Each source driver integrated circuit SDIC may be connected
to the pad, such as a bonding pad, of the panel PNL in a tape
automated bonding TAB type or a chip on glass COG type, or be
directly disposed on the panel PNL. In some embodiments, each
source driver integrated circuit SDIC may be integrated and
disposed on the panel PNL. In addition, each source driver
integrated circuit SDIC may be implemented in a chip on film type.
In this case, each source driver integrated circuit SDIC may be
mounted on a circuit film and electrically connected to the data
lines DL arranged in the panel PNL through the circuit film.
[0071] The gate driver GDR may include a plurality of gate driving
circuits GDC. Herein, the plurality of gate driving circuits GDC
each may correspond to the respective plurality of gate lines
GL.
[0072] Each gate driving circuit GDC may include a shift register,
a level shifter, and the like.
[0073] Each gate driving circuit GDC may be connected to the pad,
such as a bonding pad, of the panel PNL in a tape automated bonding
TAB type or a chip on glass COG type. In addition, each gate
driving circuit GDC may be implemented in a chip on film type. In
this case, each gate driving circuit GDC may be mounted on a
circuit film and electrically connected to the gate lines GL
arranged in the panel PNL through the circuit film. In addition,
each gate driving circuit GDC may be integrated into the panel PNL
in a gate in panel GIP type. That is, each gate driving circuit GDC
may be directly formed in the panel PNL.
[0074] FIG. 3 is a view illustrating a structure of a subpixel
arranged in an organic light emitting diode OLED panel, according
to embodiments of the present disclosure. Referring to FIG. 3, each
subpixel SP may be implemented by electronic elements arranged in
the OLED panel 110 including, but not limited to, an organic light
emitting diode OLED, a driving transistor DRT for driving the
organic light emitting diode OLED, a switching transistor O-SWT
electrically connected between a first node N1 of the driving
transistor DRT and a corresponding data line DL, a storage
capacitor Cst electrically connected between the first node N1 and
a second node N2 of the driving transistor DRT, or the like.
[0075] The organic light emitting diode OLED may include an anode
electrode, an organic light emitting layer, a cathode electrode,
and the like.
[0076] FIG. 2 is a view schematically illustrating a system
implementation of the display device according to embodiments of
the present disclosure. Referring to FIG. 2, in a display device
according to embodiments of the present disclosure, a data driver
DDR may be implemented in the chip on film COF type of various
types, such as, TAB, COG, COF, GIP, or the like. Also, a gate
driver GDR may be implemented in the gate in panel GIP type of
various types, such as, TAB, COG, COF, GIP, or the like.
[0077] The data driver DDR may be implemented as one or more source
driver integrated circuits SDIC. FIG. 2 shows an embodiment in
which the data driver DDR is implemented as a plurality of source
driving integrated circuits SDIC.
[0078] In case the data driver DDR is implemented in the COF type,
each source driving integrated circuit SDIC served as the data
driver DDR may be mounted on a source side circuit film SF.
[0079] One side of the source side circuit film SF may be
electrically connected to the pad, such as an array of pads,
disposed in the non-active area N/A.
[0080] One or more lines electrically connecting between the source
driving integrated circuit SDIC and the panel PNL may be arranged
on the source side circuit film SF.
[0081] For circuit connections between the plurality of source
driving integrated circuits SDIC and other units or electronic
elements, the display device may include one or more source printed
circuit board SPCB, and a control printed circuit board CPCB for
mounting several units used for controlling the display device and
other elements/units/devices.
[0082] The other side of the source side circuit film SF in which
the source driving integrated circuit SDIC is mounted may be
connected to the one or more source printed circuit board SPCB.
[0083] That is, the one side and the other side of the source side
circuit film SF contained of the source driving integrated circuit
SDIC may be electrically connected to the non-active area N/A of
the panel PNL and the one or more source printed circuit board
SPCB, respectively.
[0084] The controller CTR for controlling the data driver DDR, the
gate driver GDR, or the like may be disposed on the control printed
circuit board CPCB.
[0085] In addition, the control printed circuit board CPCB may
further include a power management integrated circuit PMIC that
provides various voltages or currents or controls various voltages
or currents to be provided, to the panel PNL, the data driver DDR,
the gate driver GDR, and the like.
[0086] The source printed circuit board SPCB and the control
printed circuit board CPCB may be connected to each other in a
circuit through at least one connection unit CBL. Here, connection
unit CBL may be a flexible printed circuit FPC, a flexible flat
cable, or the like.
[0087] One or more source printed circuit board SPCB and the
control printed circuit board CPCB may be integrated into one
printed circuit board.
[0088] In case the gate driver GDR is implemented in the gate in
panel GIP type, a plurality of gate driving circuits GDC included
in the gate driver GDR may be directly formed in the non-active
area N/A of the panel PNL.
[0089] Each of the plurality of gate driving circuits GDC may
output scan signals to corresponding gate lines arranged in the
active area A/A of the panel PNL.
[0090] The plurality of gate driving circuits GDC arranged in the
panel PNL may receive various signals (a clock signal, a high level
gate voltage VGH, a low level gate voltage VGL, a start signal VST,
a reset signal RST, or the like) needed for generating the scan
signals through gate-driving-related lines disposed in the
non-active area N/A.
[0091] The gate-driving-related lines disposed in the non-active
area N/A may be electrically connected to the source side circuit
film SF disposed closest to a plurality of gate driving circuits
GDC.
[0092] FIG. 3 is a view illustrating a structure of a subpixel
arranged in an organic light emitting diode OLED panel, according
to embodiments of the present disclosure. Referring to FIG. 3, each
subpixel SP in the OLED panel 110 may be implemented by electronic
elements including, but not limited to, an organic light emitting
diode OLED, a driving transistor DRT for driving the organic light
emitting diode OLED, a switching transistor O-SWT electrically
connected between a first node N1 of the driving transistor DRT and
a corresponding data line DL, a storage capacitor Cst electrically
connected between the first node N1 and a second node N2 of the
driving transistor DRT, or the like.
[0093] The organic light emitting diode OLED may include an anode
electrode, an organic light emitting layer, a cathode electrode,
and the like.
[0094] Referring to FIG. 3, an anode electrode (also referred to as
a pixel electrode) of the organic light emitting diode OLED may be
electrically connected to a second node N2 of a driving transistor
DRT. A low voltage EVSS may be applied to a cathode electrode (also
referred to as a common electrode) of the organic light emitting
diode OLED.
[0095] Herein, the low voltage EVSS may be a ground voltage or a
voltage higher or lower than the ground voltage. In addition, a
value of the low voltage EVSS may be varied depending on a driving
state. For example, values of low voltage EVSS when image driving
is performed and when sensing driving is performed may be
differently set from each other.
[0096] The driving transistor DRT drives the organic light emitting
diode OLED by providing driving currents to the organic light
emitting diode OLED.
[0097] The driving transistor DRT may include a first node N1, a
second node N2 a third node N3, and the like.
[0098] The first node N1 of the driving transistor DRT may be a
gate node, and may be electrically connected to a source node or a
drain node of the switching transistor O-SWT. The second node N2 of
the driving transistor DRT may be a source node or a drain node,
and electrically connected to the anode electrode (or cathode
electrode) of the organic light emitting diode OLED. The third node
N3 of the driving transistor DRT may be the drain node or the
source node. A driving voltage EVDD may be applied to the third
node N3 that may be electrically connected to a driving voltage
line DVL providing the driving voltage EVDD.
[0099] The storage capacitor Cst may be electrically connected
between the first node N1 and the second node N2 of the driving
transistor DRT and may maintain a data voltage Vdata corresponding
to an image signal voltage or a corresponding voltage for one frame
time (or a pre-configured time).
[0100] The drain node or the source node of the switching
transistor O- SWT is electrically connected to a corresponding data
line, and the source node or the drain node of the switching
transistor O-SWT is electrically connected to the first node N1 of
the driving transistor DRT, and the gate node of the switching
transistor O-SWT is electrically connected to a corresponding gate
line, and thereby can receive scan signal SCAN.
[0101] On-off operation of the switching transistor O-SWT may be
controlled by a scan signal SCAN input to the gate node of the
switching transistor O-SWT through a corresponding gate line.
[0102] The switching transistor O-SWT may be turned on by the scan
signal SCAN, may transfer a data voltage Vdata provided from a
corresponding data line DL to the first node N1 of the driving
transistor DRT.
[0103] Meanwhile, the storage capacitor Cst may be an external
capacitor configured to be located outside of the driving
transistor DRT other than an internal capacitor, that is, a
parasitic capacitor (e.g., Cgs, Cgd), that presents between the
first node N1 and the second node N2 of the driving transistor
DRT.
[0104] Each of the driving transistor DRT and the switching
transistor O- SWT may be an n-type transistor or a p-type
transistor.
[0105] As shown in FIG. 3, two transistors (2T) and one capacitor
(1C) type of subpixel structure is discussed for convenience of
discussion, but the embodiments are not limited thereto. In some
embodiments, the subpixel may further include one or more
transistors and/or one or more capacitors. In some embodiments, a
plurality of subpixels may have an identical structure, or one or
more of the plurality of subpixels may have different structure
from others.
[0106] FIG. 4 is a cross-sectional view illustrating the display
device according to embodiments of the present disclosure.
Referring to FIG. 4, the display panel according to embodiments of
the present disclosure may include a substrate SUB, an overcoat
layer OC located over the substrate, an anode electrode ANO located
on the overcoat layer, a bank layer BNK located on a reflective
electrode, an organic light emitting layer EL located on the
reflective electrode, and a cathode electrode CAT located on the
organic light emitting layer and the bank layer.
[0107] The overcoat layer OC may be referred to as a planarization
layer for enabling one or more pixels to be arranged over an array
of transistors. The overcoat layer may include a first area A1
(also referred to as a "first flat area" herein), a second area A2
and an inclined area SA. A part of the second area A2 adjacent to
the inclined area SA and having a top flat surface is referred to
as a "second flat area" herein.
[0108] The second area A2 may be thicker than the first area A1.
The second area A2 may be an area surrounding the first area. The
inclined area SA may be located between the first area and the
second area, and may include a first inclined surface S1 connecting
between the first area and the second area.
[0109] In defining a thickness of each area of the overcoat layer,
the thickness of each area means the thickness of the overcoat
layer disposed over the substrate of the transistor. The thickness
of each area may be defined as the thickness of the overcoat layer
measured between a passivation layer PAS disposed directly under
the overcoat layer OC and the anode electrode ANO disposed directly
on the overcoat layer OC, in each area. In particular, the
thickness of each area may be defined as the thickest thickness of
the overcoat layer measured in each area except for a portion in
which a contact hole, or the like is introduced.
[0110] As shown in FIG. 4, the thickness of the first area T1 may
be smaller than that of the second area T2. Therefore, the first
area A1 may form a concave portion of the overcoat layer and the
second area A2 may form a convex portion of the overcoat layer.
[0111] The overcoat layer including the first area A1, the second
area A2 and the inclined area SA may be formed through a
photolithography process using a half-tone mask
[0112] A shape of the first area A1 may be, but not limited to, a
polygonal shape such as a circle or a square, a pentagon, and an
octagon. The second area A2 may surround the first area A1, and may
form a side wall surrounding the side portion of the first area A1
having the shape described above.
[0113] Both the first area A1 and the second area A2 may be
connected to the inclined area SA formed by a difference between
thickness of the first area A1 and the thickness of the second area
A2. The inclined area SA may include the first inclined surface
S1.
[0114] Accordingly, the overcoat layer may have a shape such that
the second area A2 having the convex portion surrounds around the
first area A1 having the concave portion, and the first area A1 and
the second area A2 are connected to each other by the inclined area
S1 having a pre-configured degree and height.
[0115] The anode electrode ANO may be located on the overcoat layer
OC and formed along the surface of the overcoat layer.
[0116] This forming of the anode electrode ANO along the surface of
the overcoat layer OC may mean that the reflective electrode is
formed on the overcoat layer with a thickness that is considered to
be uniform when a thickness variation due to a tolerable process
deviation is taken into account.
[0117] As described above, the overcoat layer may have a shape such
that the second area A2 having the convex portion surrounds around
the first area A1 having the concave portion, and the first area A1
and the second area A2 are connected to each other by the inclined
surface S1 having a pre-configured degree and height. In case the
reflective electrode is formed along the surface of the overcoat
layer as described above, the reflective electrode has a similar
shape to the overcoat layer. Thus, the reflective electrode may
have a shape such that the inclined surface Si having a
pre-configured angle and height surrounds the concave portion of
the reflective electrode.
[0118] Accordingly, in case the anode electrode ANO is formed along
the surface of the overcoat layer OC, the reflective electrode may
include the second inclined surface S2 located on the first
inclined surface S1.
[0119] This locating of the second inclined surface S2 on the first
inclined surface S1 may mean that since the anode electrode ANO is
formed along the surface of the overcoat OC, the second inclined
surface S2 is formed along the first inclined surface S1.
[0120] The anode electrode ANO may be electrically connected to a
drain electrode D or a source electrode S of a transistor TR
through a contact hole.
[0121] The anode electrode may be an electrode including the
reflective electrode. The anode electrode may include a conductive
metal oxide layer including indium tin oxide ITO and a reflective
metal layer including silver. For example, the anode electrode may
include a first indium tin oxide ITO layer located on the overcoat
layer, the reflective metal layer including silver located on the
first indium tin oxide ITO layer, and a second indium tin oxide ITO
layer located on the reflective metal layer.
[0122] The bank layer BNK may be located on the anode electrode
ANO, and at the same time, may be located on the second area A2,
the inclined area SA and the first area A1 connected to the
inclined area SA. The bank layer BNK may further include a third
inclined surface S3 formed along the second inclined surface
S2.
[0123] The bank layer BNK includes the third inclined surface S3
formed along the second inclined surface S2 of the reflective
electrode formed along the first inclined surface Si of the
overcoat layer OC. Therefore, the bank layer may be formed on the
second area A2 forming the convex portion of the overcoat layer and
the first inclined area Si of the overcoat layer, resulting in the
first area A1 forming the concave portion of the overcoat layer
being surrounded by the bank layer.
[0124] The organic light emitting layer EL may be located on a
portion of the anode electrode which is not covered by the bank
layer, and may be located on the first area A1.
[0125] The cathode electrode CAT may be located on the organic
light emitting layer EL and the bank layer BNK. The display panel
may be a top emission type in which light emitted from the organic
light emitting layer is emitted through the cathode electrode CAT.
Accordingly, the cathode electrode CAT may be a transparent
electrode with excellent transmittance to light in the visible
light region, and the bank layer BNK may perform a function as a
layer for distinguishing between an opening area OPN and a
non-opening area NOP of the display panel.
[0126] As described above, the display panel in the present
disclosure may include two areas that are the opening area OPN and
the non-opening area NOP caused by the configuration of the bank
layer BNK. The opening area OPN may correspond to an area that is
not covered by the bank layer, and the non-opening area NOP may
correspond to an area that is covered by the bank layer.
[0127] The correspondence of an area to another area may mean a
relationship in which an area and another area are considered to be
the same, taking into account tolerance that may occur in the
manufacturing process of a product.
[0128] As described above, the anode electrode ANO, the bank layer
BNK, the organic light emitting layer EL and the cathode electrode
CAT are located over the overcoat layer OC, and therefore light
emitting may be performed in the first area A1 of the overcoat
layer in which the anode electrode ANO, the organic light emitting
layer EL and the cathode electrode CAT are sequentially stacked. In
addition, a portion of the first area A1 of the overcoat layer in
which the anode electrode ANO, the organic light emitting layer EL
and the cathode electrode CAT are disposed in order is the opening
area OPN that is not covered by the bank layer BNK, and therefore
light emitting may be performed in the organic light emitting layer
EL by the anode electrode ANO exposed to the opening area OPN of
the bank layer BNK and electric field formed by the cathode
electrode CAT.
[0129] On the other hand, light is not emitted from organic light
emitting layer EL in an area in which the bank layer BNK is present
between the organic light emitting layer EL and the anode electrode
ANO due to the bank layer BNK.
[0130] In accordance with embodiments of the present disclosure,
the display panel may include a buffer layer BUF, an interlayer
insulating film INF, a passivation layer PAS, a transistor TR, a
storage capacitor C1, C2, an auxiliary electrode (AE, or may be
referred to as an auxiliary line), and pad area.
[0131] The buffer layer BUF may be disposed on the substrate SUB,
and the transistor TR and the storage capacitor C1, C2, and the
like may be disposed over the buffer layer BUF.
[0132] The interlayer insulating film INF may be located on a gate
electrode GATE of the transistor TR, an active layer ACT, a first
storage capacitor C1 of the storage capacitor, and a first pad
electrode P1 of the pad area.
[0133] The passivation layer PAS may be disposed to protect an
electric circuit element, such as the auxiliary electrode AE, the
storage capacitor C1, C2, the transistor TR, and the like.
[0134] The transistor TR may include the activation layer ACT, a
gate insulating film GI, a gate electrode GATE, a source electrode
S and a drain electrode D. Hereinafter, discussions are conducted
on a transistor according to embodiments of the present disclosure.
Typical implementations performed in the field of the present
disclosure may be used to describe a location relationship between
respective elements of the transistor in the present
disclosure.
[0135] The activation layer ACT may be disposed on the buffer layer
BUF.
[0136] The gate insulating film GI is disposed on the activation
layer ACT, and the gate electrode GATE is disposed on the gate
insulating film GI. Therefore, the gate insulating film GI may be
located between the activation layer ACT and the gate electrode
GATE.
[0137] Each of the source electrode S and the drain electrode D may
be disposed on respective portions of the activation layer ACT, and
spaced apart from each other. The drain electrode D may be
connected to the first electrode ANO through a contact hole CH. By
placing the contact hole CH in the second area A2, which is outside
the first area A1 on which the first electrode ANO comes into
contact with the organic light emitting layer (EL), the presence of
the contact hole CH does not negatively affect the flatness of the
first electrode ANO. Hence, the light emission quality of the
subpixels are maintained consistent and reliably compared to cases
where the contact hole CH is located in the first area A1. At least
a portion of the bank layer BNK is inserted into the contact hole
CH on the first electrode ANO. A depth T3 of the bank layer BNK
from the top of the bank layer BNK to the bottom of the contact
hole CH is larger than the thickness T1 of the overcoat layer OC
and the thickness T2 of the overcoat layer OC.
[0138] The transistor TR may function as a driving transistor DRT
included in the panel, and drive the OLED included in the panel. By
placing at least a portion of the transistor TR in the first area
A1 instead of placing the transistor TR only in the second area A2
(as illustrated in FIG. 4), space in the second area A2 may become
available to accommodate other circuit components such as other
transistors, wires and capacitors in the second area A2. Therefore,
such placement of the transistor TR may facilitate increase in the
density of the subpixels.
[0139] As shown in FIG. 4, the storage capacitor C1, C2 may be
disposed in the active area A/A. The storage capacitor C1, C2 may
include a first storage capacitor electrode C1 disposed in an
identical layer to the gate electrode GATE and a second storage
capacitor electrode C2 disposed in an identical layer to the source
electrode S and the drain electrode D, but the structure of the
storage capacitor C1, C2 of the present disclosure is not limited
thereto. The storage capacitor C1, C2 is placed at least partially
placed in the first area A1. This is advantageous, among other
reasons, because space is made in the second area A2 to accommodate
other circuit components in the second area A2, and thereby
facilitate the increase of the density of subpixels.
[0140] In addition, as shown in FIG. 4, the auxiliary electrode AE
contacted to the anode electrode ANO may be further disposed in the
active area A/A.
[0141] Specifically, the auxiliary electrode AE may be disposed on
the interlayer insulating film INF. The passivation layer PAS, an
overcoat layer OC and the bank layer BNK may have a hole that does
not cover the auxiliary electrode AE. The cathode CAT may contact
the auxiliary electrode AE through the hole of the passivation
layer PAS, overcoat layer OC and the bank layer BNK.
[0142] For example, in case the organic light emitting display
panel is a display panel having a large size, voltage drop due to
the resistance of the anode electrode ANO may occur, resulting in a
luminance difference between the outer edge and the center of the
panel. However, in the organic light emitting display panel
according to the present disclosure, it is possible to overcome
voltage drop occurring through the auxiliary electrode AE contacted
to the anode electrode ANO. Thus, in case the organic light
emitting display panel according to embodiments of the present
disclosure is a panel having a large size, it is possible to
prevent the panel from the occurrence of the luminance
difference.
[0143] FIG. 4 shows that one auxiliary electrode AE is disposed in
one subpixel SP, but present disclosure is not limit thereto. For
example, one auxiliary electrode AE may be disposed per a plurality
of subpixels SP basis. In one or more embodiments, the auxiliary
electrode AE may be connected to subpixel SP only at the edges of
the display panel.
[0144] As another example, in case the organic light emitting
display panel according to embodiments of the present disclosure is
not a panel having a large size, the panel may not include the
auxiliary electrode AE.
[0145] In addition, the display panel according to embodiments of
the present disclosure may include a pad area disposed in the
non-active area. A plurality of pad electrodes P1 and P2 may be
disposed in the pad area. For example, a first pad electrode P1 may
be disposed on a plurality of insulating films BUF and GI disposed
in the pad area. The interlayer insulating film INF that does not
cover a portion of a top surface of the first pad electrode P1 may
be disposed on the first pad electrode P1. A second pad electrode
P2 contacted to the first pad electrode P1 may be disposed on the
first pad electrode P1 and the interlayer insulating film INF.
[0146] FIG. 4 also illustrates a viewing plane VP at which the
light emitted from the display panel is captured. The viewing plane
may be located at a distance from the display panel. An example of
the image representing light emitted from the display panel is
illustrated in FIG. 7B.
[0147] Although not shown in FIG. 4, various circuit films, or the
like may be electrically connected to the second pad electrode
P2.
[0148] A viewing plane VP is illustrated in FIG. 4. The viewing
plane VP is a plane onto which the light from the display is
projected. The light projected onto the viewing plane VP is
illustrated in FIG. 7B.
[0149] FIG. 5 is a view illustrating that light emitted from an
organic light emitting layer of the display panel reflected from a
second inclined surface, according to embodiments of the present
disclosure. Referring to FIG. 5, light emitted from the organic
light emitting layer EL is emitted in various directions without
directionality. In particular, some of the light emitted from the
organic light emitting layer EL may undergo total reflection and
travel toward third inclined surface S3 of the bank layer BNK,
while traveling from a layer (not shown) with a high refractive
index to a layer (not shown) with a low refractive index.
[0150] The bank layer BNK is formed from a material that is
transparent to visible light wavelength band. Accordingly, light
emitted toward the third inclined surface S3 of the bank layer BNK
may go through the third inclined surface S3 of the bank layer BNK,
and then reach the second inclined surface S2 of the anode
electrode ANO.
[0151] Light having reached the second inclined surface S2 of the
anode electrode ANO is reflected from the second inclined surface
S2, and then may travel toward the third inclined surface S3 of the
bank layer BNK and exit the display panel. Accordingly, as
described above, in the display panel according to embodiments of
the present disclosure, the second inclined surface S2 of the
reflective electrode formed on the first inclined surface S1
enables light emitted from the organic light emitting layer EL to
travel toward an upper portion of the display panel, resulting in
improvement in the luminous efficiency of the display panel.
[0152] FIG. 6 is an expanded cross-sectional view of the first
inclined surface S1, the second inclined surface S2 and the third
inclined surface S3 of the display device according to embodiments
of the present disclosure. Referring to FIG. 6, an angle between
the first area A1 and the first inclined surface S1 is represented
as .theta. (hereinafter, referred to as ".theta."), a horizontal
distance between the second inclined surface S2 and the third
inclined surface S3 is represented as d (hereinafter, referred to
as "d"), and a vertical height of the inclined area SA is
represented as h (hereinafter, referred to as "h"). According to
embodiments of the present disclosure, it is possible to provide a
display panel with increased luminous efficiency by adjusting the
.theta. and the d, or the .theta., the d and the h.
[0153] The angle .theta. between the first area A1 and the first
inclined surface S1 may be larger than or equal to 27.degree. or
45.degree.. There is no restriction to the upper limit of the
.theta. range. In this case, when the .theta. has a larger value,
the possibility that cracks and breaks occur in the anode electrode
ANO formed on the overcoat layer is increased. Accordingly, the
upper limit may be preferably less than or equal to 80.degree. or
85.degree..
[0154] By keeping .theta. within this range, it is possible for the
second inclined surface S2 to effectively reflect the light emitted
from the organic light emitting layer. Thus, it is possible to
provide a display panel with increased luminous efficiency.
[0155] The horizontal distance d between the second inclined
surface S2 and the third inclined surface S3 may be defined as a
distance from the second inclined surface S2 to the third inclined
surface S3, measured in parallel direction to the first area A1 of
the overcoat layer. Distance d may be may be less than or equal to
3.2 .mu.m, 2.6 .mu.m or 2.0 .mu.m. The smaller the d is, the
greater the opening area OPN of the display panel expands. In this
case, traveling paths of light reflected from the second inclined
surface S2 may be reduced, and thus, luminous efficiency may be
increased. To this end, there is no restriction to the lower limit
of the d. The lower limit of the d may be preferably larger than or
equal to 0.1 .mu.m, 0.3 .mu.m, or 0.5 .mu.m. By adjusting the d
range within this range, it is possible to expand an opening area
and provide a display panel with increased luminous efficiency.
[0156] The vertical height h of the inclined area SA may denote a
difference between the thickness T1' of the first area A1 portion
and the thickness T2' of the second area A2 portion, which are
connected by the inclined area SA. The vertical height h may be
preferably larger than or equal to 0.7 .mu.m, 1.2 .mu.m, 1.4 .mu.m,
or 2 .mu.m. The larger the h is, the greater the luminous
efficiency increases because light emitted from the organic light
emitting layer EL by the second inclined surface S2 is reflected
effectively. To this end, there is no restriction to the upper
limit of the h. The upper limit may be preferably less than or
equal to 10 .mu.m, or 5 .mu.m.
[0157] As described above, by adjusting d, .theta. and h, the
display panel according to the present disclosure provides
increased luminous efficiency and may include the first light
emitting area and the second light emitting area when organic light
emitting layer emits light.
[0158] FIGS. 7A and 7B are views showing an opening area, a
non-opening area, a first light emitting area, and a second light
emitting area included in the display panel, according to
embodiments of the present disclosure. FIG. 7A shows a
photomicrograp of the display panel inclining the opening area OPN
and the non-opening area NOP having a specific shape. FIG. 7B is a
view illustrating an image of the display panel including a first
light emitting area, and a second light emitting area captured from
the viewing plane VP.
[0159] The display panel according to the present disclosure may
include a first light emitting area LEA1 (also referred to as a
"main light emitting area") and a second non-light emitting area
NEA2, in which visible light is emitted when the organic light
emitting layer emits light, and a first non-light emitting area
NEA1 and a second non-light emitting area NEA2.
[0160] The first light emitting area LEA1 may have a shape
corresponding to the shape of the opening area OPN. The
correspondence of a shape of an element to a shape of another
element may mean that i) a shape of an element is an identical
shape to another element, ii) two elements have an identical shape,
but have different sizes from each other, or iii) a shape of an
element may be formed by transferring the shape of another element.
Accordingly, the shape of the first light emitting area LEA1 may
mean that the shape of the opening area OPN is substantially
transferred by light emitted from the organic light emitting layer
EL located in the opening area OPN.
[0161] There is no restriction to the shape of the opening area
OPN. The shape of the opening area OPN may preferably be, but not
limited to, a polygonal shape such as a circle or a square, a
pentagon, and an octagon. Referring to FIG. 7A, the opening area
OPN has an octagonal shape.
[0162] The first light emitting area LEA1 may have a shape
corresponding to the opening area OPN. Referring to FIG. 7B, the
first light emitting area LEA1 has a shape corresponding to the
shape of opening area OPN as shown in FIG. 7A.
[0163] The second light emitting area LEA2 ((also referred to as a
"supplemental light emitting area") may not overlap with or
separated from the first light emitting area LEA1 and may surround
the first light emitting area LEA1. The second light emitting area
LEA2 may have a shape corresponding to an edge shape of the first
light emitting area LEA1. As shown in FIG. 7B, the second light
emitting area LEA2 has a shape identical to the edge of the first
light emitting area LEA1, but has different size from the first
light emitting area LEA1. Therefore, it is possible to express that
the second light emitting area LEA2 has a shape corresponding to
the edge shape of the first light emitting area LEA1. The second
light emitting area LEA2 may be a closed curve having an identical
shape to the edge of the first light emitting area LEA1. As another
example, the second light emitting area LEA2 may have a shape in
which a portion of the closed curve is disconnected.
[0164] A plurality of subpixels may be distinguished by the first
non-light emitting area NEA1. Referring to FIG. 7B, each of a
plurality of second light emitting area LEA2 may be spaced apart
from another by the first non-light emitting area NEA1. That is,
the first non-light emitting area NEA1 may be an area between the
second light emitting areas LEA2 in the non-opening area NOP.
[0165] That is, the first non-light emitting area NEA1 may be
substantially an area from which light is not emitted. That is, the
first non-light emitting area NEA1 may correspond to a portion in
which the second light emitting area LEA2 is not formed in the
non-opening area NOP.
[0166] The second non-light emitting area NEA2 may distinguish the
first light emitting area LEA1 and the second light emitting area
LEA2 formed by the subpixel and may be an area from which light is
not substantially emitted.
[0167] The shape of the second non-light emitting area NEA2 may be
determined depending on the shapes of the first light emitting area
LEA1 and the second light emitting area LEA2. For example, in case
the first light emitting area LEA1 has an octagonal shape, and the
second light emitting area LEA2 has a closed curve with the
octagonal shape, the second non-light emitting area NOP2 may have
the octagonal shape by the first light emitting area LEA1 and the
second light emitting area LEA2.
[0168] Although the second non-light emitting area NEA2 is
described using the term of non-light emitting, it is possible for
some light to be detected in the photograph because the second
non-light emitting area NEA2 is located between the light emitting
areas LEA1 and LEA2. In particular, it is possible for light with
colors similar to a wavelength band of visible light emitted in the
subpixel to be detected. Accordingly, the second non-light emitting
area NEA2 may be an area from which light is not emitted at all.
Alternatively, it should be understood that the second non-light
emitting area NEA2 may be an area from which light weaker than what
is emitted from the two light emitting areas is observed.
[0169] As described above, the second light emitting area LEA2 may
be implemented by adjusting a range of .theta., d, or h.
Accordingly, the display panel according to embodiments of the
present disclosure may have increased luminous efficiency and
include the first light emitting area LEA1 and the second light
emitting area LEA2, by adjusting a range of the .theta., the d, or
the h.
[0170] It is estimated that the second light emitting area LEA2 is
formed by light traveling through paths described with reference to
FIG. 5. The display panel according to embodiments of the present
disclosure includes, as well as the first light emitting area LEA1,
but the second light emitting area LEA2 formed by light reflected
from the second inclined surface S2. Therefore, the display panel
may have increased luminous efficiency.
[0171] The second light emitting area may be located in such a way
that the second light emitting area surrounds the first light
emitting area. This is estimated from, as a main reason, that the
second light emitting area LEA2 is formed by light reflected from
the second inclined surface S2 of the anode electrode ANO formed in
the first inclined surface Si located in the inclined area SA
surrounding the first area A1.
[0172] In addition, the second light emitting area LEA2 may be
located in the non-opening area NOP. As another embodiment, the
overcoat layer may not include the inclined area, other than the
display panel according to embodiments described above. In this
case, among light emitted from the organic light emitting layer,
only some of light traveling toward the opening area exits the
display panel, and light traveling toward the non-opening area in
which the bank layer is formed may be trapped within the display
panel. Thus, in such display panels, light emitting area is
observed in only the opening area.
[0173] However, as shown in FIG. 5, in the display panel according
to embodiments of the present disclosure, among light emitted from
the organic light emitting layer EL, light traveling toward the
non-opening area is reflected from the second inclined surface S2
and goes out of the display panel, and therefore second light
emitting area (LEA2) may be formed in the non-opening area NOP in
which the bank layer is disposed, by the reflected light.
[0174] As shown in FIG. 5, the light from the first light emitting
area LEA1 and the light from the second light emitting area LEA2
travel different paths and goes through different layers, and
therefore may have different color coordinates. Accordingly, a
color coordinate of visible light emitted from the first light
emitting area may be different from a color coordinate of visible
light emitted from the second light emitting area adjacent to the
first light emitting area. As shown in FIG. 7B, a plurality of the
first light emitting areas and the second light emitting areas may
be formed according to the number of subpixels included in the
display panel. Thus, it should be understood that the second light
emitting area adjacent to the first light emitting area is a light
emitting area included in an identical subpixel area, and denotes
the second light emitting area adjacent to the first light emitting
area of a plurality of the second light emitting area.
[0175] FIG. 8 is a cross-sectional view illustrating the display
device according to embodiments of the present disclosure.
Referring to FIG. 8, the organic light emitting layer EL may be
located on a portion of the anode electrode ANO that is not covered
by the bank layer BNK and the bank layer BNK, and the cathode
electrode CAT may be located on the organic light emitting layer
EL.
[0176] Table 1 below shows data on the luminous efficiency measured
in Comparative examples and Embodiments.
[0177] Display panels used for the Embodiments have a structure as
shown in FIG. 8. Each display panel in the Embodiments have
identical configurations to others, except for being configured
with the .theta., the d and the h described in the Table 1. A
display panel in the Comparative example has identical
configurations to display panels in the Embodiments except for not
including the first inclined surface to third inclined surface.
TABLE-US-00001 TABLE 1 luminous .theta.(.degree.) h(.mu.m) d(.mu.m)
efficiency(Cd/A) Comparative -- -- -- 55.5 example 1 Embodiment 1
42 2 2.3 62.2 Embodiment 2 34 2 3.2 58.0 Embodiment 3 40 2 4.4 59.4
Embodiment 4 44 2 5.2 59.0
[0178] In the Table 1, in case of Comparative example 1, there are
no values of the .theta., the h and the d because the first
inclined surface to the third inclined surface are not included. It
can be seen that luminous efficiency in the Embodiments 1 to 4
increases more than that in Comparative examples, and in
particular, luminous efficiency in the Embodiments 1 and 2 with the
d less than or equal to 3.2 .mu.m increase more than that in the
Embodiments 3 and 4. In particular, it can be observed that the
Embodiment 1 in which the d less than or equal to 2.3 .mu.m shows
the most increased luminous efficiency.
[0179] In case the organic light emitting layer EL is disposed in,
as well as the opening area OPN in which the bank layer BNK is not
disposed, but the non-opening area NOP in which the bank layer BNK
is disposed, it is possible to maximize the area of the organic
light emitting layer EL in which light emitting is performed. In
case the organic light emitting layer EL is disposed in only the
opening area OPN, due to limitations in process, the organic light
emitting layer EL may not be formed in an edge portion of the
opening area OPN or may be incompletely formed. However as
described above, in case the organic light emitting layer EL is
disposed on the bank layer BNK, it is possible to overcome some
problems with limitations in process.
[0180] Table 2 below shows data related to whether the second light
emitting area is included according to the .theta., the d and the
h.
TABLE-US-00002 TABLE 2 Whether the second light emitting area
.theta.(.degree.) h(.mu.m) d(.mu.m) is disposed Comparative 8.0
0.60 2.0 X example 2 Comparative 25.0 1.70 2.0 X example 3
Comparative 25.8 1.70 2.0 X example 4 Embodiment 5 45.0 1.40 2.0 O
Embodiment 6 60.0 2.00 2.0 O Embodiment 7 60.0 2.04 2.0 O
[0181] The Comparative examples 2 and 3 and the Embodiments 4 to 7
are based on the display panel as shown in FIG. 4 and have
identical configurations except for different .theta.s and hs as
described in Table 2.
[0182] Referring to Table 2, it can be seen that, in case the
display panel is configured with a larger .theta. and a larger h,
the second light emitting area is formed because the second
inclined surface of the reflective electrode can effectively
reflect light emitted from the organic light emitting layer.
[0183] In case the organic light emitting layer EL is formed as
shown in FIG. 8, a first light emitting layer emitting a first
color and a second light emitting layer emitting a second color may
be disposed on the anode electrode ANO and the bank layer BNK. In
this case, each of the first light emitting layer emitting the
first color and the second light emitting layer emitting the second
color is disposed in a different opening area OPN distinguished by
the bank layer BNK, it is possible to omit to use a large mask and
to simplify a related process.
[0184] FIG. 9 is a cross-sectional view illustrating a part of the
display device according to embodiments of the present disclosure.
Referring to FIG. 9, the thickness t1 of the organic light emitting
layer EL disposed on the anode electrode ANO is larger than the
thickness t2 of the organic light emitting layer EL disposed on the
third inclined surface S3 of the bank layer BNK.
[0185] The difference in the thicknesses of the organic light
emitting layer may be caused by the third inclined surface S3 of
the bank layer BNK. The organic light emitting layer EL may be
formed by a thermal evaporation process, which is a physical vapor
deposition technique. In case the thermal evaporation process is
used on the inclined surface, such as third inclined surface S3,
the thickness of the deposited layer may be reduced due to
characteristics of the thermal deposition process.
[0186] In case a portion of the organic light emitting layer is
thinned, the density of carriers may be increased at an electrode
adjacent to an organic light emitting layer with a thin thickness
and result in the organic light emitting layer being deteriorated.
However, it is possible to prevent such problems in the display
panel according to embodiments of the present disclosure, as shown
in FIG. 9, because the bank layer BNK is located between the
reflective electrode EL and the organic light emitting layer EL, in
a portion in which the organic light emitting layer EL has the
thinned thickness t2.
[0187] Although a preferred embodiment of the present disclosure
has been described for illustrative purposes, those skilled in the
art will appreciate that various modifications, additions and
substitutions are possible, without departing from the scope and
spirit of the invention as disclosed in the accompanying claims.
Although the exemplary embodiments have been described for
illustrative purposes, a person skilled in the art will appreciate
that various modifications and applications are possible without
departing from the essential characteristics of the present
disclosure. For example, the specific components of the exemplary
embodiments may be variously modified. The various embodiments
described above can be combined to provide further embodiments.
These and other changes can be made to the embodiments in light of
the above-detailed description. In general, in the following
claims, the terms used should not be construed to limit the claims
to the specific embodiments disclosed in the specification and the
claims, but should be construed to include all possible embodiments
along with the full scope of equivalents to which such claims are
entitled. Accordingly, the claims are not limited by the
disclosure.
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