U.S. patent application number 17/660854 was filed with the patent office on 2022-08-11 for process for fabricating silicon nanostructures.
The applicant listed for this patent is Advanced Silicon Group Technologies, LLC. Invention is credited to Marcie R. Black, Brent A. Buchine, Faris Modawar.
Application Number | 20220254883 17/660854 |
Document ID | / |
Family ID | 1000006290877 |
Filed Date | 2022-08-11 |
United States Patent
Application |
20220254883 |
Kind Code |
A1 |
Buchine; Brent A. ; et
al. |
August 11, 2022 |
PROCESS FOR FABRICATING SILICON NANOSTRUCTURES
Abstract
A process for etching a substrate comprising polycrystalline
silicon to form silicon nanostructures includes depositing metal on
top of the substrate and contacting the metallized substrate with
an etchant aqueous solution comprising about 2 to about 49 weight
percent HF and an oxidizing agent.
Inventors: |
Buchine; Brent A.; (Austin,
TX) ; Black; Marcie R.; (Lincoln, MA) ;
Modawar; Faris; (Orem, UT) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Advanced Silicon Group Technologies, LLC |
Lincoln |
MA |
US |
|
|
Family ID: |
1000006290877 |
Appl. No.: |
17/660854 |
Filed: |
April 27, 2022 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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16871436 |
May 11, 2020 |
11355584 |
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17660854 |
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16054457 |
Aug 3, 2018 |
10692971 |
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16871436 |
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15826005 |
Nov 29, 2017 |
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16054457 |
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14924273 |
Oct 27, 2015 |
9859366 |
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15826005 |
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14444361 |
Jul 28, 2014 |
9202868 |
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14924273 |
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13305649 |
Nov 28, 2011 |
8791449 |
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14444361 |
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12423623 |
Apr 14, 2009 |
8143143 |
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13305649 |
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61141082 |
Dec 29, 2008 |
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61044573 |
Apr 14, 2008 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 31/02363 20130101;
H01M 4/0492 20130101; B01J 20/28007 20130101; H01L 21/3086
20130101; H01L 29/16 20130101; B82Y 30/00 20130101; H01L 31/028
20130101; H01M 4/386 20130101; Y10S 977/762 20130101; H01L 21/02282
20130101; H01L 21/02175 20130101; H01L 29/0669 20130101; H01M
2004/027 20130101; H01L 21/02603 20130101; H01L 21/02488 20130101;
H01M 10/0525 20130101; H01L 21/02164 20130101; B82Y 20/00 20130101;
H01L 21/2855 20130101; H01L 21/0234 20130101; H01M 4/134 20130101;
H01L 21/02118 20130101; B01J 20/10 20130101; H01L 21/02244
20130101; C23C 14/34 20130101; H01M 4/661 20130101; H01L 21/02513
20130101; H01M 4/1395 20130101; H01L 21/28568 20130101; H01M 4/366
20130101; H01L 29/04 20130101; H01L 31/0352 20130101; H01L 21/30604
20130101; H01L 21/32134 20130101; H01L 31/0236 20130101; Y02E 10/50
20130101; H01L 21/02532 20130101; H01L 29/0676 20130101; H01L
21/02307 20130101 |
International
Class: |
H01L 29/06 20060101
H01L029/06; B01J 20/10 20060101 B01J020/10; B01J 20/28 20060101
B01J020/28; B82Y 20/00 20060101 B82Y020/00; B82Y 30/00 20060101
B82Y030/00; H01L 21/306 20060101 H01L021/306; H01L 21/308 20060101
H01L021/308; H01L 31/0236 20060101 H01L031/0236; H01M 4/134
20060101 H01M004/134; H01M 4/36 20060101 H01M004/36; H01M 4/38
20060101 H01M004/38; H01L 29/16 20060101 H01L029/16; C23C 14/34
20060101 C23C014/34; H01L 21/02 20060101 H01L021/02; H01L 21/285
20060101 H01L021/285; H01L 21/3213 20060101 H01L021/3213; H01L
29/04 20060101 H01L029/04; H01L 31/028 20060101 H01L031/028; H01L
31/0352 20060101 H01L031/0352; H01M 4/04 20060101 H01M004/04 |
Claims
1. A nanowire array comprising polycrystalline silicon, wherein the
nanowires of the nanowire array have their lengthwise directions
disposed at a non-zero angle to a polycrystalline silicon
substrate, wherein the array is formed by etching the
polycrystalline silicon substrate, wherein the nanowires in the
nanowire array have diameters below 150 nm, and wherein the
nanowire array is incorporated into a solar cell.
2. The nanowire array of claim 1, wherein the nanowires in the
nanowire array have diameters less than 125 nm.
3. The nanowire array of claim 1, wherein the nanowires in the
nanowire array have diameters less than 100 nm.
4. The nanowire array of claim 1, wherein nanowires in the nanowire
array have diameters less than 70 nm.
5. The nanowire array of claim 1, wherein the nanowires in the
nanowire array have diameters less than 50 nm.
6. The nanowire array of claim 1, wherein the polysilicon nanowires
are at an angle from the substrate which is different from
perpendicular
7. A nanowire array comprising polycrystalline silicon, the
nanowires of the array having lengthwise directions disposed at one
or more non-zero angles to a substrate composed primarily of
polycrystalline silicon, the nanowires having bases in electrical
and physical contact with the substrate and having tips free of
electrical communication with any electrical contacts other than
through the bases, the array having been formed by etching the
substrate, the nanowire array being incorporated into a solar cell,
the nanowires in the nanowire array having diameters less than 150
nm.
8. The nanowire array of claim 7, wherein the nanowires in the
nanowire array have diameters less than 125 nm.
9. The nanowire array of claim 8, wherein the nanowires in the
nanowire array have diameters less than 100 nm.
10. The nanowire array of claim 9, wherein nanowires in the
nanowire array have diameters less than 70 nm.
11. The nanowire array of claim 10, wherein the nanowires in the
nanowire array have diameters less than 50 nm.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority under 35 U.S.C. .sctn. 120
as a continuation of U.S. patent application Ser. No. 16/871,436,
filed May 11, 2020, titled "PROCESS FOR FABRICATING SILICON
NANOSTRUCTURES," which is a continuation of U.S. patent application
Ser. No. 16/054,457, filed Aug. 3, 2018, titled "PROCESS FOR
FABRICATING SILICON NANOSTRUCTURES," now U.S. Pat. No. 10,692,971,
which is a continuation of U.S. patent application Ser. No.
15/826,005, filed Nov. 29, 2017, titled "PROCESS FOR FABRICATING
SILICON NANOSTRUCTURES," which is a division of U.S. patent
application Ser. No. 14/924,273, filed Oct. 27, 2015, titled
"PROCESS FOR FABRICATING SILICON NANOSTRUCTURES," now U.S. Pat. No.
9,859,366, which is a continuation of U.S. patent application Ser.
No. 14/444,361, filed Jul. 28, 2014, titled "PROCESS FOR
FABRICATING NANOWIRE ARRAYS," now U.S. Pat. No. 9,202,868, which is
a continuation of U.S. patent application Ser. No. 13,305,649,
filed Nov. 28, 2011, titled "NANOSTRUCTURED SILICON FOR BATTERY
ANODES," now U.S. Pat. No. 8,791,449, which is a continuation of
U.S. patent application Ser. No. 12/423,623, filed Apr. 14, 2009,
titled "PROCESS FOR FABRICATING NANOWIRE ARRAYS," now U.S. Pat. No.
8,143,143, which claims priority to U.S. Provisional Applications
Nos. 61/044,573, filed Apr. 14, 2008, and 61/141,082, filed Dec.
29, 2008. These applications are incorporated by reference
herein.
TECHNICAL FIELD
[0002] This application pertains to the field of
nanotechnology.
BACKGROUND OF THE INVENTION
[0003] The ability to structure and pattern silicon is important
for many applications. There has been particular interest in
patterning silicon to make nanostructures. Relevant information
regarding silicon fabrication processes known to those of skill in
the art can be found, for example, in Sami Franssila, Introduction
to Microfabrication (John Wiley & Sons, 2004), and the
references cited there.
[0004] Semiconductor nanowires have become the focal point of
research over the last decade due to their interesting physical,
chemical and biological properties. There is particular interest
surrounding silicon nanowires, as silicon is one of the most
abundant materials in the earth's crust and has become a
cornerstone for many of the electronic, optoelectronic,
electro-chemical and electro-mechanical devices upon which designs
are based.
[0005] Today, many nanosystems are not utilized commercially due to
the large cost associated with fabrication, and limitations in the
scalability of nanowire synthesis. Nanowires have been grown bottom
up using molecular beam epitaxy (MBE), metal-organic chemical vapor
deposition (MOCVD), and physical vapor deposition (PVD). They have
also been fabricated top-down using techniques like reactive ion
etching (RIE) and inductively coupled plasma (ICP). These systems
require high temperature and/or low pressure which is largely
responsible for the high cost. A push towards solution based
techniques that can be operated in ambient conditions is important
given their low cost, simplicity of design and ease of
utilization.
[0006] Recent work has demonstrated the fabrication of silicon
nanowires using a solution made up of a metal salt and a strong
acid (typically AgNO.sub.3 and HF). (See reference (a).) By
controlling the concentrations of each component in solution,
silicon can be etched normal to the plane of the wafer forming
vertically aligned silicon nanowires with an average diameter of
150 nm and a diameter range from 20-300 nm. Through the realization
that silver is precipitating out of solution and catalyzing the
silicon etch, the technique has been modified to incorporate the
addition of H.sub.2O.sub.2 into the chemical bath and Ag metal
directly deposited onto silicon. Polystyrene spheres of uniform
dimensions were dispersed prior to the deposition of the Ag in
order to use them as an etch mask and define the nanowire. (See
reference (e).) As a result, ordered arrays of silicon nanowires
with a homogeneous diameter and length were demonstrated.
[0007] The ultimate diameter achieved with this technique has been
limited. The ability to achieve sub-100 nm dimensions is of value
to a variety of electronic, optoelectronic, electrochemical and
electromechanical applications. For example, it is within the
sub-100 nm range that silicon begins to demonstrate novel
properties distinguishable from the properties of bulk silicon. In
addition, an increase in surface area at the low nanometer scale is
of value.
SUMMARY OF THE INVENTION
[0008] A process is provided for etching a silicon-containing
substrate to form nanowire arrays. In this process, one deposits
nanoparticles and a metal film onto the substrate in such a way
that the metal is present and touches silicon where etching is
desired and is blocked from touching silicon or not present
elsewhere. One submerges the metallized substrate into an etchant
aqueous solution comprising HF and an oxidizing agent. In this way
arrays of nanowires with controlled diameter and length are
produced.
BRIEF DESCRIPTION OF THE FIGURES
[0009] FIG. 1 depicts the result of using an embodiment of the
invention to obtain nanowires with diameters that ranged from 12-70
nm.
[0010] FIG. 2 depicts the result of using the alternative
embodiment described below in part B to obtain nanowires.
[0011] FIG. 3 depicts schematically a setup for practicing
processes of the invention, using oxygen as an oxidizer.
[0012] FIG. 4 depicts the result of using metal enhanced etching of
silicon to obtain microstructuring on a silicon wafer.
Unintentional wires were formed inside the trenches.
DETAILED DESCRIPTION OF THE INVENTION
[0013] In an aspect of the invention, a process is provided for
etching a silicon-containing substrate to form nanostructures. In
this process, one deposits and patterns a metal film onto the
substrate in such a way that the metal is present and touches
silicon where etching is desired and is blocked from touching
silicon or not present elsewhere. One submerges the metallized
substrate into an etchant aqueous solution comprising about 4 to
about 49 weight percent HF and an oxidizing agent.
[0014] In a process as described above, to achieve sub-100 nm
nanowires, one may use sub-100 nm nanoparticles to block the silver
from the silicon. The nanoparticles may be made of a variety of
substances, for example silicon dioxide, iron oxide, or
polymers.
A. First Exemplary Process
[0015] An exemplary process utilizes the spinning of SiO.sub.2
nanoparticles well dispersed in an isopropanol solution (5 wt %
SiO.sub.2 in IPA) that ranged in particle size from 12-30 nm at
4000 RPM. Subsequent to spin-coating, the samples were heated at
elevated temperatures resulting in solvent evaporation. Once the
samples were dry, 40 nm of Ag was sputter deposited on top in order
to coat the SiO.sub.2 nanoparticles as well as the bare silicon
spaces in between. The samples were dipped into an
HF/H.sub.2O.sub.2 solution for a period of 10 minutes. The etching
reaction commenced at the Ag/Si interface and the nanoparticles
acted as a barrier by which to mask and define the nanostructure.
The dimensions of the nanoparticles, which are selected per the
desired application, influence the dimensions and the shape of the
resulting one-dimensional nanostructure. Some agglomeration
occurred between the SiO.sub.2 nanoparticles resulting in wire
dimensions on the order of a single agglomerate. By selecting the
concentration of particles in solution as well as the method for
depositing/spin coating the particles, it is possible to limit
agglomeration resulting in nanowires that ranged from 12-70 nm. A
result is depicted in FIG. 1.
B. First Alternative
[0016] In a variant on the process described above, one uses iron
oxide nanoparticles (5-10 nm) with surfaces that have been
pretreated with oleic acid and dispersed in chloroform. This
surface treatment was done in order to prevent agglomeration and
maintain a stable nanoparticle suspension. In this situation it was
not necessary to spin coat. Deposition of the nanoparticles onto
the silicon substrate was achieved by applying a few drops of the
solution to the surface under static conditions (no spinning) Rapid
evaporation at room temperature resulted in a monodispersed layer
of the iron oxide particles on the silicon substrate with little to
no agglomeration. Without wishing to be bound by theory, it is
believed that the monodispersed layer resulted at least in part
from the pre-tailored surface tension properties and the high vapor
pressure of the solvent.
[0017] In this alternative process, Ag was sputter deposited on the
surface and the substrate to coat the iron oxide particles and the
spaces in between. The sample was dipped into a similar
HF/H.sub.2O.sub.2 solution in order to begin the etching reaction
and form the nanowires. An example of the result is seen in FIG. 2.
There is some bundling that occurs due to the drying process,
making it difficult to determine precisely the actual nanowire
dimension. However, all of the measurable structures had a diameter
less than 30 nm.
C. Second Alternative
[0018] In a further variation of the process, other oxidizers may
be used in place of H.sub.2O.sub.2 in the H.sub.2O.sub.2-HF etchant
solution. An oxidizing agent (also called an oxidant or oxidizer)
is a substance that readily transfers oxygen atoms or tends to gain
electrons in a redox chemical reaction. One such oxidizer is pure
oxygen, which may be introduced by bubbling oxygen through the HF.
Other oxidizers include: ozone, chlorine, iodine, ammonium
perchlorate, ammonium permanganate, barium peroxide, bromine,
calcium chlorate, calcium hypochlorite, chlorine trifluoride,
chromic acid, chromium trioxide (chromic anhydride), peroxides such
as hydrogen peroxide, magnesium peroxide, dibenzoyl peroxide and
sodium peroxide, dinitrogen trioxide, fluorine, perchloric acid,
potassium bromate, potassium chlorate, potassium peroxide, propyl
nitrate, sodium chlorate, sodium chlorite, and sodium
perchlorate.
[0019] It may be desirable to use a less reactive alternative
oxidizer in place of H.sub.2O.sub.2. Comparative reactivity towards
the metal deposited (e.g., silver), silicon, or silicon dioxide may
be of interest in the selection of an oxidizer. Reactivity may be
measured, for example, by the extent to which the reaction goes
forward in a particular period of time, or by determining a
reaction rate as discussed in books on physical chemistry and
chemical kinetics. (See, e.g., Peter W. Atkins & Julio de
Paula, Atkins' Physical Chemistry (8th ed. 2006), especially
chapters 22 and 23.) Measurements may be made in conditions such as
temperature and pressure similar to those of the etching
process.
[0020] An exemplary process would be as follows:
[0021] Silicon material with a resistivity of greater than 20
ohm-cm is selected having a surface with (100), (110), (111) or any
orientation available. Amorphous and/or microcrystalline material
will also result in vertically oriented nanowires if one carries
out the following process.
[0022] The substrate is pre-cleaned using a series of solvents by
sonicating for three minutes each in acetone, methanol and then
isopropyl alcohol. The substrate is then rinsed in a dump-tank of
flowing deionized water (DI) for 3 minutes to remove any residue
remaining from the solvent clean. The silicon is placed into a
Piranha solution made up of 3 parts 96% H.sub.2SO.sub.4 and 1 part
30 wt % H.sub.2O.sub.2 for 15 minutes in order to remove any
additional organics and create a hydrophilic surface. The substrate
is then removed from the bath and placed into a dump dank of
flowing DI water again for 3 minutes to remove any residual acids.
The substrate is removed and blown dry with nitrogen gas.
[0023] A colloidal suspension of 10 nm iron oxide nanoparticles in
chloroform is made by diluting product #SOR-10-0050 from
OceanNanotech to a concentration of 1 mg/mL. The silicon wafer is
coated with the iron oxide by dipping the silicon into the
colloidal suspension and then removing the substrate so that the
surface normal is perpendicular to the vertical direction of motion
allowing the chloroform to sheet of the surface. The combination of
the hydrophilic surface and the nature of the oleic acid
functionalized iron oxide nanoparticles, results in a natural
self-assembly that limits agglomeration and gives some reasonable
spacing to the particles. The samples are then baked on an
80.degree. C. hot plate for 2 minutes and cleaned using an in-situ
O.sub.2 plasma prior to metal deposition.
[0024] In addition to iron oxide nanoparticles, 100 nm polystyrene
spheres have also been used successfully in this process. In this
situation, a hydrophilic surface is created on the silicon
substrate as described above. The polystyrene spheres (purchased
from Duke Scientific Corporation) are diluted to a concentration of
1% and spun onto the substrate at 500 RPM for 5 seconds followed by
a ramp to 2000 RPM for 40 seconds. The polystyrene spheres create a
single monolayer on the surface. An O.sub.2 plasma is used to
reduce the size and spacing in the polystyrene spheres inside a
plasma stripper prior to inserting the sample into the metal
deposition tool (30 W, 200 mTorr). The sample heats up during the
plasma clean, which can change the properties (or melt) the
polystyrene making it difficult to continue the shrinking process.
To resolve this, the polystyrene is etched using short 1 minute
intervals, removing the substrate from the tool and allowing it to
cool to room temperature prior to the next 1 minute etch.
Preferably the shrinking process is done in-situ (inside the metal
deposition tool) prior to metal deposition with Ar or O.sub.2.
[0025] Silver (Ag) is deposited via physical vapor deposition
inside a sputterer, thermal evaporator or e-beam evaporator. It is
desirable that a continuous film results, where there are no breaks
or cracks that would cause a portion of the film to become isolated
from the remainder. As HF concentration is altered, the optimal
film thickness may need to be varied.
[0026] Once the chip is coated with the appropriate film of Ag, the
HF solution is seasoned before commencing the etching reaction. The
concentration of HF can vary from full strength (about 49 wt %) all
the way down to very nominal concentrations. Initial observations
have shown that the length of the resulting nanostructure increases
as HF concentration is reduced. Concentrations as low as 2 wt % and
below may be used. For example, a solution of 8 wt % HF may be
used.
[0027] O.sub.2 gas is flowed into the bath to create a vigorous
bubbling for a period of 10 minutes. Once the bath is seasoned, the
samples are submerged. At the completion of the etch, the samples
are removed and put into a dump-tank of flowing DI water and blown
dry with N.sub.2. At this point the remaining Ag on the surface can
be removed with a silver etchant, for example the etchant supplied
by Transene Corporation.
[0028] FIG. 3 depicts a setup for the use of oxygen gas as an
oxidizer. There is a container holding HF etchant 40. In the
container there is a silver/silicon substrate 42. There is an
oxygen source 44 which produces oxygen bubbles such as 46 and 48.
The oxygen source inlet may be placed at, above, or below the level
of the substrate. With this less aggressive oxidizer, all wires
were formed by the intentional nanoparticle mask that was spun on
top of the surface. No defects formed in the metal film during
etching were apparent.
[0029] An advantage of the processes which use alternative
oxidizers is that they are able to eliminate unintentional
nanowires ("grass") formed in some variants of the processes
described above, while still producing the desirable sub-100 nm
nanowires while using a thin continuous layer of metal for
catalyzed etching of silicon. FIG. 4 depicts unintentional
nanowires. Avoidance of these unintentional nanowires both saves an
etching step which would be used to eliminate them and also avoids
the rounding of nanostructure corners and edges which would result
from such an etching step.
[0030] While not wishing to be bound by theory, it is believed that
some of the alternative oxidizers used in these processes of the
invention do not attack the metal, or attack it to a much lesser
degree than H.sub.2O.sub.2. This may be a reason why processes with
alternative oxidizers avoid the formation of unintentional
nanowires. For this reason it may be desirable to use oxidizers
known to react less readily or at a lower rate with the metal than
H.sub.2O.sub.2 does.
[0031] In order to avoid unintentional wires, it is desirable that
the metal film be free of small unintentional holes and be
deposited on a clean silicon surface free of oxide.
[0032] A further advantage of the processes of the invention is
that they are extendable to specified crystallographic directions.
With at least some processes of the invention, irrespective of the
crystal orientation of the silicon surface, the nanowires will be
etched at least approximately perpendicular to that surface. In
order to achieve this, it is desirable that the metal film has no
breaks or cracks that would cause a portion of the film to become
isolated from the remainder. It is also desirable that the metal
film has sufficient adhesion and is deposited on a clean silicon
surface. Desirable angles between nanowire axes and a vector normal
to the substrate may be, for example, less than about 0.25 degrees,
about 0.5 degrees, about 1 degree, or about 2 degrees.
[0033] With processes of the invention, it is possible to make
wires which have a noticeable taper that results in the wire
diameter increasing slightly as the etch progresses. The taper has
been found to increase with HF concentration. For some
applications, the taper may not be desirable. For photovoltaic
applications, however, a taper may be beneficial. For example, with
a slight taper, free carriers in the nanowire will bounce off the
edges of the wire and thus tend propagate downward to the
substrate. If the p-n junction of the photovoltaic cell is in the
substrate rather than in the nanowires, this increased diffusion
towards the substrate may be expected to increase the cell
efficiency. Desirable taper angles might be, for example, no more
than about 0.5 degrees, about 1 degree, about 2 degrees, or about 4
degrees, or in a range between about 0.5 degrees and about 1
degree, about 2 degrees, or about 4 degrees.
[0034] Using processes of the invention it is possible to achieve
nanowire diameters which are on average (e.g., have a mean or
median) below about 150 nm, below about 125 nm, below about 100 nm,
below about 70 nm, or below about 50 nm. Small nanowires are
important in certain applications, such as where the small size
changes the band structure of the silicon. It may be desired, for
example, that a majority, or at least about 75%, or about 90%, or
about 95% of the nanowires have diameters less than a selected
dimension such as those indicated above.
D. Applications
[0035] Processes of the invention may be applied to structuring
silicon for optoelectronic devices (see reference (i)). They may be
employed in devices that utilize the photoelectric or photovoltaic
effect, for example solar cells (see, e.g., references (j) and
(k)), photodetectors, photodiodes (see reference (a)),
phototransistors, photomultipliers and integrated optical circuits.
Silicon nanowire arrays or individual nanowires fabricated via this
process can be utilized within each of these applications.
[0036] Processes of the invention may be employed to produce
devices made out of or comprising polycrystalline silicon. The
invention encompasses processes which can be used with any
crystalline orientation of silicon. Such processes can be used to
texture the surface of and/or form nanowires in polysilicon.
Polysilicon is a cheaper material than crystalline silicon, but it
is typically more difficult to texture and structure than single
crystal silicon due to the random orientation of the grains. The
processes of the invention can likewise be used to form nanowires
in amorphous silicon.
[0037] Arrays of silicon nanowires can be used in applications
where the silicon will be subjected to stress or strain where the
nanostructure is able to absorb and relax this stress or strain.
For example, nanowires can act as an interfacial layer between bulk
silicon and another material grown on top which is not
lattice-matched to it.
[0038] Processes of the invention are also applicable to lithium
ion battery technology. Silicon has been seen as a desirable
candidate for the anode material in lithium ion batteries due to
its low discharge potential and high charge capacity. Its
application in the past has been limited due to the large change in
volume associated with ion insertion and ion extraction. The large
amounts of stress and strain that builds in the silicon results in
degradation of the silicon layer resulting in a very short
performance lifetime. Nanowires have been pursued due to their
ability to withstand these stress and strains (see reference (1)).
The ability to form well ordered and aligned nanostructures with a
great deal of control over the resulting diameter and void spacing
between them provided by processes of the invention would be
advantageous in making a lithium ion battery anode. In addition,
the fact that porous silicon (nanopores or micropores) can also be
fabricated via processes of this invention would enable the
fabrication of another anode geometry capable of withstanding the
stresses and strains of ion insertion/extraction for lithium ion
battery applications.
[0039] It would additionally be possible to form a porous template
or silicon nanowire arrays out of a specific type of silicon (say
n-type) and utilize an alternate technique like the vapor, liquid,
solid (VLS) process to fill the pores with p-type silicon nanowires
resulting in a novel n/p junction configuration which could be
utilized in a wide variety of optoelectronic (LED, photovoltaic)
and electronic (transistor) applications. (For some general
information about the VLS process see reference (p).) This process
is especially favorable since the Ag particles that catalyze the
etching of the silicon substrate to form the template could also be
used to catalyze the wire growth (e.g., in VLS or VSS) at the base
of the pore to synthesize the wire. In addition, the Ag particles
could serve as electrical contacts for the device. A wide variety
of materials other than silicon can be formed inside the template
as well. A few examples are Bi, Ge, GaN, ZnO, and GaAs.
[0040] Processes of the invention may be used to create
nanostructures which make silicon into an intermediate band
photovoltaic material (IBPV). (See reference (n).) Silicon has an
excellent band structure for IBPV, provided that the strength of
particular electronic transitions can be enhanced. One way to do
this is to form a dense array of silicon nanowires with specific
control over the wire diameter, doping and crystallographic
orientation, as described in reference (i). Processes of the
invention may be used for manufacturing such nanowire arrays.
[0041] The following references are of interest in relation to this
application: (a) K. Peng, Z. Huang, and J. Zhu, Adv. Mater. 16 (1)
(2004) 73-76; (b) T. Qiu, X. L. Wu, X. Yang, G. S. Huang, and Z. Y.
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[0042] All patents, patent applications, and publications mentioned
herein are hereby incorporated by reference in their entireties.
However, where a patent, patent application, or publication
containing express definitions is incorporated by reference, those
express definitions should be understood to apply to the
incorporated patent, patent application, or publication in which
they are found, and not to the remainder of the text of this
application, in particular the claims of this application.
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