U.S. patent application number 17/669953 was filed with the patent office on 2022-05-26 for high voltage esd protection apparatus.
The applicant listed for this patent is Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Yi-Feng Chang, Jam-Wem Lee.
Application Number | 20220165725 17/669953 |
Document ID | / |
Family ID | 1000006138507 |
Filed Date | 2022-05-26 |
United States Patent
Application |
20220165725 |
Kind Code |
A1 |
Chang; Yi-Feng ; et
al. |
May 26, 2022 |
High Voltage ESD Protection Apparatus
Abstract
A device comprises a high voltage n well and a high voltage p
well over a buried layer, a first low voltage n well over the high
voltage n well, wherein a bottom portion of the first low voltage n
well is surrounded by the high voltage n well, an N+ region over
the first low voltage n well, a second low voltage n well and a low
voltage p well over the high voltage p well, a first P+ region over
the second low voltage n well and a second P+ region over the low
voltage p well.
Inventors: |
Chang; Yi-Feng; (Xinbei,
TW) ; Lee; Jam-Wem; (Hsinchu, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Co., Ltd. |
Hsinchu |
|
TW |
|
|
Family ID: |
1000006138507 |
Appl. No.: |
17/669953 |
Filed: |
February 11, 2022 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
16227726 |
Dec 20, 2018 |
11282830 |
|
|
17669953 |
|
|
|
|
15165832 |
May 26, 2016 |
10163891 |
|
|
16227726 |
|
|
|
|
13243688 |
Sep 23, 2011 |
9356012 |
|
|
15165832 |
|
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/7302 20130101;
H01L 27/067 20130101; H01L 29/0808 20130101; H01L 27/0259 20130101;
H01L 29/0821 20130101; H01L 29/8611 20130101; H01L 27/0255
20130101; H01L 29/735 20130101; H01L 29/0649 20130101; H01L 29/1008
20130101; H01L 29/872 20130101 |
International
Class: |
H01L 27/02 20060101
H01L027/02; H01L 29/73 20060101 H01L029/73; H01L 29/735 20060101
H01L029/735; H01L 29/861 20060101 H01L029/861; H01L 29/872 20060101
H01L029/872; H01L 27/06 20060101 H01L027/06; H01L 29/06 20060101
H01L029/06; H01L 29/08 20060101 H01L029/08; H01L 29/10 20060101
H01L029/10 |
Claims
1. A semiconductor device comprising: a substrate; a transistor in
the substrate, comprising: a collector comprising an n-type region;
a base comprising a first p-type region; and an emitter comprising
an N well; a first P well in the substrate and under the first
p-type region; a second P well in the substrate, wherein the first
P well and the N well extend into the second P well; a first
isolation region in the substrate between the n-type region and the
first p-type region; a second isolation region in the substrate
between the n-type region and the N well; and a PN junction
connected in series with the transistor, wherein the PN junction
comprises the N well and a second p-type region over the N
well.
2. The semiconductor device of claim 1, wherein the second p-type
region is a p-type metal contact.
3. The semiconductor device of claim 2, wherein a lower surface of
the p-type metal contact facing the substrate contacts and extends
along an upper surface of the N well.
4. The semiconductor device of claim 1, wherein the n-type region,
the first p-type region, the N well, the first isolation region,
and the second isolation region have a coplanar upper surface.
5. The semiconductor device of claim 4, wherein the first isolation
region extends continuously from the first p-type region to the
n-type region, and wherein the second isolation region extends
continuously from the n-type region to the N well.
6. The semiconductor device of claim 5, wherein the first isolation
region and the second isolation region extend deeper into the
substrate than the n-type region and the first p-type region,
wherein the N well extends deeper into the substrate than the first
isolation region and the second isolation region.
7. The semiconductor device of claim 1, wherein the first P well
contacts and extends along a lower surface of the first p-type
region.
8. The semiconductor device of claim 7, wherein the first P well
further contacts and extends along a sidewall of the first
isolation region and a first portion of a bottom surface of the
first isolation region.
9. The semiconductor device of claim 8, wherein the second P well
contacts and extends along a second portion of the bottom surface
of the first isolation region.
10. The semiconductor device of claim 1, wherein the N well
contacts and extends along a sidewall of the second isolation
region and a first portion of a bottom surface of the second
isolation region, wherein the second P well contacts and extends
along a second portion of the bottom surface of the second
isolation region.
11. The semiconductor device of claim 10, wherein the second P well
contacts and extends along a lower surface of the n-type region,
wherein there is a depletion region at the lower surface of the
n-type region.
12. A semiconductor device comprising: a substrate; a diode having
a PN junction, the diode comprising a metal contact and an N well,
wherein the N well is in the substrate, and the metal contact is
over the N well; a transistor in the substrate and connected in
series with the diode, wherein the transistor comprises an emitter,
a collector, and a base, wherein the collector comprises an n-type
region, the base comprises a p-type region, and the emitter
comprises the N well; a first P well in the substrate and under the
p-type region; and a second P well in the substrate, wherein the
second P well extends along a lower surface of the n-type region,
and at least partially surrounds the first P well and the N
well.
13. The semiconductor device of claim 12, wherein the metal contact
is a p-type metal contact.
14. The semiconductor device of claim 12, wherein the n-type region
is in the substrate and laterally between the N well and the p-type
region.
15. The semiconductor device of claim 14, further comprises: a
first isolation region in the substrate and extending continuously
from the p-type region to the n-type region; and a second isolation
region in the substrate and extending continuously from the n-type
region to the N well.
16. The semiconductor device of claim 15, wherein the first P well
contacts and extends along the p-type region and a first portion of
a bottom surface of the first isolation region, wherein the N well
contacts and extends along a first portion of a bottom surface of
the second isolation region, wherein the second P well contacts and
extends along a second portion of the bottom surface of the first
isolation region and a second portion of the bottom surface of the
second isolation region.
17. A semiconductor device comprising: a substrate; a transistor in
the substrate, the transistor comprising: a base; an emitter; and a
collector, wherein the collector is disposed in the substrate
laterally between the base and the emitter; a first isolation
region in the substrate between the base and the collector; a
second isolation region in the substrate between the emitter and
the collector; a third isolation region in the substrate, wherein
the emitter is between the second isolation region and the third
isolation region; and a diode connected in series with the
transistor, the diode comprising a metal contact forming a PN
junction with the emitter of the transistor, wherein the metal
contact overlies the emitter and extends continuously from the
second isolation region to the third isolation region.
18. The semiconductor device of claim 17, wherein the base is a
first doped semiconductor region in the substrate, the collector is
a second doped semiconductor region in the substrate, and the
emitter is a first well region in the substrate.
19. The semiconductor device of claim 18, further comprising: a
second well region in the substrate under the first doped
semiconductor region; and a third well region in the substrate,
wherein the first well region and the second well region extend
into the third well region, wherein the first well region has a
first dopant of a first type, the first type being n-type or
p-type, wherein the second well region and the third well region
has a second dopant of a second type different from the first type,
the second type being p-type or n-type.
20. The semiconductor device of claim 19, wherein the first well
region covers a first portion of a lower surface of the second
isolation region, and the second well region covers a first portion
of a lower surface of the first isolation region, wherein the third
well region covers a second portion of the lower surface of the
first isolation region and a second portion of the lower surface of
the second isolation region.
Description
PRIORITY CLAIM AND CROSS-REFERENCE
[0001] This application is a continuation of U.S. patent
application Ser. No. 16/227,726, filed on Dec. 20, 2018, which is a
continuation of U.S. patent application Ser. No. 15/165,832, filed
on May 26, 2016, now U.S. Pat. No. 10,163,891 issued on Dec. 25,
2018, which is a divisional of U.S. patent application Ser. No.
13/243,688, filed on Sep. 23, 2011, now U.S. Pat. No. 9,356,012
issued on May 31, 2016, which applications are incorporated herein
by reference.
BACKGROUND
[0002] Electrostatic discharge (ESD) is a rapid discharge that
flows between two objects due to the build-up of static charge. ESD
may destroy semiconductor devices because the rapid discharge can
produce a relatively large current. In order to reduce the
semiconductor failures due to ESD, ESD protection circuits have
been developed to provide a current discharge path. When an ESD
event occurs, the discharge current is conducted through the
discharge path without going through the internal circuits to be
protected.
[0003] In the semiconductor technology, ESD protection solutions
such as NMOS transistors, Silicon-Controlled Rectifiers (SCRs) and
RC triggered PMOS transistors are widely used. Each ESD protection
device may comprise a detection circuit and an ESD current
discharge path. For example, an RC triggered ESD protection circuit
may comprise a discharge transistor, a driver and an ESD spike
detection circuit. The ESD spike detection circuit may include a
resistance element and a capacitance element connected in series to
form an RC detection circuit. The node between the resistance
element and the capacitance element is coupled to the gate of the
discharge transistor via the driver. The time constant formed by
the resistance element and the capacitance element is so chosen
that the discharge transistor is turned off when the ESD protection
device operates in a normal power up mode. On the other hand, the
discharge transistor is turned on when an ESD spike occurs at a
power bus to which the ESD protection circuit is coupled. The
turn-on of the discharge transistor may provide a bypass of the ESD
current from the power bus to ground so as to clamp the voltage of
the power bus to a level below the maximum rating voltage to which
the internal circuit is specified, so that it helps to prevent the
large voltage spike from damaging the internal circuits being
protected.
[0004] Similarly, a PNP transistor can be used as an ESD protection
device. More particularly, the emitter of the PNP transistor is
coupled to an input/output (I/O) pad of an integrated circuit and
the collector of the PNP transistor is coupled to ground. When an
ESD event occurs, an external voltage across the I/O pad and ground
increases beyond the reverse-bias breakdown voltage of the PNP
transistor. As a result, a conductive path is established between
the emitter and the collector of the PNP transistor. Such a
conductive path allows the large amount of ESD energy to be
discharged in a relatively short amount of time. As a consequence,
the internal circuit components of the integrated circuit can be
protected from being damaged by the ESD event.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] For a more complete understanding of the present invention,
and the advantages thereof, reference is now made to the following
descriptions taken in conjunction with the accompanying drawings,
in which:
[0006] FIG. 1 illustrates a simplified cross-sectional view of an
ESD protection structure in accordance with an embodiment;
[0007] FIG. 2 illustrates an equivalent circuit diagram of the ESD
protection structure illustrated in FIG. 1;
[0008] FIG. 3 illustrates breakdown voltage curves of a
conventional ESD protection circuit such as a PNP transistor and
the ESD protection circuit in FIG. 2;
[0009] FIG. 4 illustrates a simplified cross-sectional view of an
ESD protection structure in accordance with another embodiment;
[0010] FIG. 5 illustrates an equivalent circuit diagram of the ESD
protection structure illustrated in FIG. 4;
[0011] FIG. 6 illustrates a simplified cross-sectional view of an
ESD protection structure in accordance with yet another
embodiment;
[0012] FIG. 7 illustrates an equivalent circuit diagram of the ESD
protection structure illustrated in FIG. 6;
[0013] FIG. 8 illustrates a simplified cross-sectional view of an
ESD protection structure in accordance with yet another
embodiment;
[0014] FIG. 9 illustrates an equivalent circuit diagram of the ESD
protection structure illustrated in FIG. 8;
[0015] FIG. 10 illustrates a simplified cross-sectional view of an
ESD protection structure in accordance with yet another
embodiment;
[0016] FIG. 11 illustrates an equivalent circuit diagram of the ESD
protection structure illustrated in FIG. 10;
[0017] FIG. 12 illustrates an integrated circuit level ESD
protection diagram in accordance with an embodiment; and
[0018] FIG. 13 illustrates a further ESD protection scheme by
employing a plurality of ESD protection circuits in series
connection between an I/O pad and a VSS pad.
[0019] Corresponding numerals and symbols in the different figures
generally refer to corresponding parts unless otherwise indicated.
The figures are drawn to clearly illustrate the relevant aspects of
the various embodiments and are not necessarily drawn to scale.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
[0020] The making and using of the presently preferred embodiments
are discussed in detail below. It should be appreciated, however,
that the present invention provides many applicable inventive
concepts that can be embodied in a wide variety of specific
contexts. The specific embodiments discussed are merely
illustrative of specific ways to make and use the invention, and do
not limit the scope of the invention.
[0021] The present invention will be described with respect to
preferred embodiments in a specific context, an NPN transistor
based electrostatic discharge (ESD) protection device. The
invention may also be applied, however, to a variety of ESD
protection devices.
[0022] FIG. 1 illustrates a simplified cross-sectional view of an
ESD protection structure in accordance with an embodiment. The ESD
protection structure 100 includes a first P+ region 102, a second
P+ region 108, a first N+ region 106, a first isolation region 142,
a second isolation region 144, a third isolation region 146 and a
fourth isolation region 148. The ESD protection structure 100
further comprises a shallow p-type well 112 and shallow n-type well
114 and 116. For simplicity, throughout the description, the
shallow p-type well 112 and the shallow n-type well 114 and 116 are
alternatively referred to as a SHP region 112, a first SHN region
114 and a second SHN region 116 respectively. In one embodiment,
the SHP region 112, the first SHN region 114 and the second SHN
region 116 have a depth of about 1 .mu.m.
[0023] The ESD protection structure 100 further comprises a first
high voltage P well (HVPW) region 122, a high voltage N well (HVNW)
region 124 and a second HVPW region 126. As shown in FIG. 1, both
the first HVPW region 122 and the HVNW region 124 are formed on an
N+ buried layer (NBL) 132. The NBL 132 is commonly used in the art,
and hence is not discussed in further detail. Both the SHP region
112 and the first SHN region 114 are formed in the HVPW 122. More
particularly, as shown in FIG. 1, an upper portion of the SHP
region 112 and an upper portion of the first SHN region 114 are
separated by the second isolation region 144. A bottom portion of
the SHP region 112 and a bottom portion of the first SHN region 114
are enclosed by the HVPW region 122. Likewise, the second SHP
region 116 has an upper portion formed between the third isolation
region 146 and the fourth isolation region 148 and a bottom portion
enclosed by the HVNW region 124.
[0024] The first P+ region 102 is formed on the SHP region 112. The
first P+ region 102 is separated from the first SHN region 114 by
the second isolation region 144. The N+ region 106 is formed on the
second SHN region 116. The second P+ region 108 is formed on the
second HVPW 126. As shown in FIG. 1, the N+ region 106 is separated
from the first SHN region 114 by the third isolation region 146. In
addition, the N+ region 106 is separated from the second P+ region
108 by the fourth isolation region 148.
[0025] In FIG. 1, there may be a p-type metal contact 152 formed on
the first SHN region 114. As a result, the p-type metal contact 152
and the first SHN region 114 form a diode junction. Such a diode
junction helps to increase the breakdown voltage of the ESD
protection device 100. The detailed explanation of the p-type metal
contact 152 will be described below with respect to FIG. 2 and FIG.
3. In accordance with an embodiment, the p-type metal contact 152
comprises cobalt silicide (CoSi2). It should be noted that while
FIG. 1 illustrates a p-type metal contact 152 formed on the first
SHN 114, one skilled in the art will recognize that other metal
contacts are necessary for the first P+ region 102 and the N+
region 106. Indeed, the metal contacts on the first P+ region 102
and the N+ region 106 are semiconductor contacts that form low
resistance connections between the ESD protection device 100 and
external terminals (not shown).
[0026] The SHP region 112, the first SHN region 114 and the second
SHN region 116 are fabricated in a low voltage CMOS process. In
accordance with an embodiment, the SHP region 112, the first SHN
region 114 and the second SHN region 116 are fabricated in a 5V
CMOS process. It should further be noted that while the SHP region
112, the first SHN region 114 and the second SHN region 116 appear
to be similar in FIG. 1, one person skilled in the art will
recognize that it is merely an example. The SHP region 112, the
first SHN region 114 and the second SHN region 116 may have unequal
dimensions or doping concentrations.
[0027] In accordance with an embodiment, the first P+ region 102,
the second P+ region 108 and the N+ region 106 are highly doped.
The first P+ region 102, the second P+ region 108 and the N+ region
106 have a doping density of between about 10.sup.20/cm.sup.3 and
10.sup.21/cm.sup.3. In addition, the SHP region 112, the first SHN
region 114 and the second SHN region 116 are heavily doped regions.
The SHP region 112 has a doping density of between about
10.sup.17/cm.sup.3 and 10.sup.18/cm.sup.3. The first SHN region 114
and the second SHN region 116 have a doping density of between
about 10.sup.17/cm.sup.3 and 10.sup.18/cm.sup.3. Furthermore, in
accordance with an embodiment, the first HVPW region 122 has a
doping density of about 10.sup.17/cm.sup.3. Likewise, the HVPW
region 124 and the second HVPW region 126 have a doping density of
10.sup.17/cm.sup.3.
[0028] It should be noted that the doping technique used in the
previous example is selected purely for demonstration purposes and
is not intended to limit the various embodiments to any particular
doping technique. One skilled in the art will recognize that
alternate embodiment could be employed (such as employing the
diffusion technique).
[0029] The isolation regions 142, 144, 146 and 148 are used to
isolate active regions so as to prevent leakage current from
flowing between adjacent active regions. The isolation region
(e.g., the first isolation region 142) can be formed by various
ways (e.g., thermally grown, deposited) and materials (e.g.,
silicon oxide, silicon nitride). In accordance with an embodiment,
the isolation regions (e.g., the first isolation region 142) may be
fabricated by a surface trench isolation (STI) technique.
[0030] In accordance with an embodiment, the ESD protection
structure 100 may comprise two depletion regions. A first depletion
region is formed between the HVNW region 124 and the first HVPW
region 122. One skilled in the art will recognize that the first
depletion region can provide a breakdown voltage when the first
depletion region is reverse biased during an ESD event. The
detailed operation of the breakdown voltage of the ESD protection
structure 100 will be described below with respect to FIG. 2 and
FIG. 3. In addition, a second depletion region is formed between
the p-type metal contact 152 and the first SHN region 114. Since
the second depletion region is connected in series with the first
depletion region, the second depletion region may provide
additional breakdown voltage protection.
[0031] In FIG. 1, the ESD protection structure 100 may provide an
on-chip ESD protection solution. For ESD protection applications,
the N+ region 106 is typically coupled to an input/output (I/O) pad
and the p-type metal contact 152 is typically coupled to a VSS pad,
which is typically grounded or coupled to a power supply. An
advantageous feature of the described embodiment is that the second
depletion region formed by the p-type metal contact 152 and the
first SHN region 114 provides extra ESD protection headroom as well
as reliable protection.
[0032] FIG. 2 illustrates an equivalent circuit diagram of the ESD
protection structure illustrated in FIG. 1. The equivalent circuit
of the ESD protection structure 100 illustrated in FIG. 1 includes
a diode 210 and an NPN transistor 220. Referring again to FIG. 1,
the p-type metal contact 152 is formed on the first SHN region 114.
The junction between the p-type metal contact 152 and the first SHN
region 114 forms the diode 210 as shown in FIG. 2. The diode 210
has a cathode and an anode. The cathode is located in the first SHN
region 114. The anode is located in the p-type metal contact 152.
In accordance with an embodiment, the diode 210 has a typical
breakdown voltage of 10V. However, as one of ordinary skill in the
art will recognize that the diode 210 and its associated
semiconductor structure is merely exemplary and is not intended to
limit various embodiments in any fashion. By selecting different
diffusion parameters, any suitable breakdown voltage rating may be
utilized in the ESD protection circuit described above.
[0033] The NPN transistor 220 has an emitter 212, a base 216 and a
collector 214. The emitter 212, the base 216 and the collector 214
are formed by the first SHN region 114, the first P+ region 102 and
the N+ region 106 respectively. The emitter 212 is electrically
coupled to the cathode of the diode 210. The base 216 is either
coupled to the emitter 212 or floating. In sum, a simplified
circuit diagram 200 depicts that the corresponding circuit of the
ESD protection structure 100 is formed by a series connection of
the diode 210 and the NPN transistor 220.
[0034] However, it should be recognized that while FIG. 2
illustrates the ESD protection circuit with one diode and one NPN
transistor (e.g., diode 210 and NPN transistor 220), the ESD
protection circuit could accommodate any numbers of diodes and NPN
transistors. Furthermore, it is understood that the ESD protection
circuit may be implemented using a plurality of diodes or NPN
transistors in series connection. On the other hand, other
configurations of a plurality of diodes and NPN transistors such as
parallel-connected diodes coupled to parallel-connected NPN
transistors are also within the contemplated scope of this
embodiment.
[0035] As known in the art, the NPN transistor 220 has a breakdown
voltage. When a large voltage spike is applied between the
collector 214 and the emitter 212, the NPN transistor 220 may
experience an avalanche breakdown in which a large current is
allowed to flow from the collector 214 to the emitter 212. The
current path from the collector 214 to the emitter 212 may provide
a bypass of the ESD current and clamp the voltage between the
collector 214 and the emitter 212 to a level below the maximum
rating voltage of the internal circuit, so that it helps to prevent
the large voltage spike from damaging the internal circuits being
protected. Similarly, the diode 210 has a breakdown voltage (e.g.,
10V) when a voltage is applied between the cathode and the anode of
the diode 210. In sum, the ESD protection circuit 200 has a
breakdown voltage equivalent to the NPN transistor's 220 breakdown
voltage plus the diode's 210 breakdown voltage.
[0036] The ESD protection circuit 200 is typically placed at an I/O
pad and a VSS of a device to be protected (not shown but
illustrated in FIG. 12). The first N+ region 106 is typically
coupled to the I/O pad and the p-type metal contact 152 is
typically coupled to the VSS, which is typically grounded. If an
ESD event occurs, a voltage spike is applied between the first N+
region 106 and the p-type metal contact 152. Firstly, both the
diode 210 and the NPN transistor 220 experience the voltage spike,
which may exceed the breakdown voltages of the diode 210 and the
NPN transistor 220. In response to the voltage spike, the NPN
transistor 220 may enter an avalanche conduction mode.
Consequently, the NPN transistor 220 may provide a current path so
that the ESD discharge current can flow from the collector 214 to
the emitter 212.
[0037] Furthermore, the diode 210 allows the ESD current to flow
from the cathode to the anode when the voltage across the cathode
and the anode exceeds the breakdown voltage of the diode 210 (e.g.,
10y). In addition, the diode 210 may clamp the voltage between the
cathode and the anode to its breakdown voltage (e.g., 10y). The
conduction of both the diode 210 and the NPN transistor 220 clamps
the voltage between the collector 214 and the anode of the diode
210 to a lower level so that the internal circuits coupled to the
collector 214 can be protected.
[0038] It should be noted that both the diode 210 and the NPN
transistor 220 may turn on nearly simultaneously. However, for
convenience the description above uses a slightly earlier turn-on
of the NPN transistor 220 as an example to describe the breakdown
mechanism. It is understood that the turn-on sequence between the
diode 210 and the NPN transistor 220 plays no role in this
embodiment. The breakdowns of two series-connected elements (e.g.,
diode 210 and NPN transistor 220) in the ESD protection circuit 200
may be performed in any arbitrary sequence. However, the
specifically discussed example above is preferred.
[0039] FIG. 3 illustrates the breakdown voltage curves of a
conventional ESD protection circuit such as a PNP transistor and
the ESD protection circuit 200 in FIG. 2. The horizontal axis of
FIG. 3 represents the ESD voltage across an ESD protection circuit
(e.g., the ESD protection circuit 200). The vertical axis of FIG. 3
represents the ESD current flowing through the ESD protection
circuit. A curve 302 illustrates the current flowing through a
conventional ESD protection circuit as a voltage spike is applied.
As shown in FIG. 3, the trigger voltage as well as the breakdown
voltage for a conventional ESD protection circuit is around 30V. On
the curve 302, before the applied voltage reaches the trigger
voltage, the ESD current is approximately equal to zero. Once the
applied ESD voltage exceeds the trigger voltage, the ESD current
increases in proportion to the applied ESD voltage. In this
embodiment, the peak ESD current of the conventional ESD protection
circuit is up to about 3 A with a breakdown voltage approximately
30V.
[0040] The curve 304 represents the I-V relationship for the ESD
protection circuit 200 during an ESD event. As shown in FIG. 3, the
trigger voltage as well as the breakdown voltage of the ESD
protection circuit 200 is about 40V. After a resulting breakdown,
the curve 304 is about in parallel with the curve 302 but having a
voltage gap, which is about 10V as illustrated in FIG. 3. An
advantageous feature of the described embodiment is that the diode
210 helps to provide a higher ESD breakdown voltage.
[0041] FIG. 4 illustrates a simplified cross-sectional view of an
ESD protection structure in accordance with another embodiment.
FIG. 4 is similar to FIG. 1, and hence is not discussed in detail
to avoid unnecessary repetition. In comparison with FIG. 1, a third
P+ region 404 is formed on the first SHN region 114. As a result, a
second depletion region is formed by the third P+ region 404 and
the first SHN region 114. Similar to the second depletion region
formed by a p-type metal contact 152 and the first SHN region 114
in FIG. 1, the second depletion region in FIG. 4 can provide
addition breakdown voltage protection. FIG. 5 illustrates an
equivalent circuit diagram of the ESD protection structure 400
illustrated in FIG. 4. As shown in FIG. 5, the equivalent circuit
diagram of the ESD protection structure 400 is similar to that
shown in FIG. 2, and hence is not discussed in further detail to
avoid unnecessary repetition.
[0042] FIG. 6 illustrates a simplified cross-sectional view of an
ESD protection structure in accordance with yet another embodiment.
The structure configuration of FIG. 6 is similar to FIG. 1 except
that FIG. 6 comprises a PNP transistor rather than an NPN
transistor. In comparison with FIG. 1, each p-type region is
replaced by its corresponding n-type region. Likewise, each n-type
region is replaced by its corresponding p-type region. The
operation principles of the PNP transistor based ESD protection
structure 600 is similar to its NPN transistor based counterpart
shown in FIG. 1, and hence are not discussed in detail to avoid
repetition.
[0043] It should be noted that in FIG. 6 the metal contact 652 is
an n-type metal contact. In accordance with an embodiment, the
n-type metal contact 652 may be formed of Titanium Nitride (TiN).
As shown in FIG. 6, the n-type metal contact 652 is formed on the
first SHP region 614. As a result, a second depletion region is
formed by the n-type metal contact 652 and the first SHP region
614. Similar to the second depletion region formed by a p-type
metal contact 152 and the first SHN region 114 in FIG. 1, the
second depletion region in FIG. 6 can provide extra headroom during
an ESD event.
[0044] FIG. 7 illustrates an equivalent circuit diagram of the ESD
protection structure 600 illustrated in FIG. 6. As shown in FIG. 7,
the equivalent circuit diagram of the ESD protection structure 600
comprises a diode 710 connected in series with a PNP transistor
720. During an ESD event, the operation principle of the equivalent
circuit diagram 700 is similar to that of the equivalent circuit
diagram 200 shown in FIG. 2, and hence is not discussed in detail
herein.
[0045] FIG. 8 illustrates a simplified cross-sectional view of an
ESD protection structure 800 in accordance with yet another
embodiment. The ESD protection structure 100 includes a P+ region
806, an N+ region 802, a SHP region 816, a SHN region 812 and an
HVPW region 822. Both the SHP region 816 and the SHN region 812 are
formed in the HVPW 822. More particularly, as shown in FIG. 8, an
upper portion of the SHP region 816 is formed between the third
isolation region 146 and the fourth isolation region 148. An upper
portion of the SHN region 812 is formed between the first isolation
region 142 and the second isolation region 144. A bottom portion of
the SHP region 816 and a bottom portion of the SHN region 812 are
enclosed by the HVPW 822. The P+ region 806 is formed on the SHP
region 816. The N+ region 802 is formed on the HVPW region 822. The
N+ region 802 is separated from the SHN region 812 by the second
isolation region 144. The N+ region 802 is separated from the P+
region 806 by the third isolation region 146.
[0046] In FIG. 8, there may be a p-type metal contact 852 formed on
the SHN region 812. As a result, the p-type metal contact 852 and
the SHN region 812 form a diode junction. Such a diode junction
helps to increase the breakdown voltage of the ESD protection
device 800. In accordance with an embodiment, the p-type metal
contact 852 comprises CoSi2. The SHP region 816 and the SHN region
812 are similar to the SHP region and the SHN region in FIG. 1, and
hence are not discussed in further detail herein.
[0047] In accordance with an embodiment, the ESD protection
structure 800 may comprises two depletion regions. A first
depletion region is formed between the N+ region 802 and the HVPW
region 822. One skilled in the art will recognize that the first
depletion region can provide a breakdown voltage when the first
depletion region is reverse biased during an ESD event. In
addition, a second depletion region is formed between the p-type
metal contact 852 and the SHN region 812. Since the second
depletion region is connected in series with the first depletion
region, the second depletion region may provide additional
breakdown voltage during an ESD event.
[0048] FIG. 9 illustrates an equivalent circuit diagram of the ESD
protection structure 800 illustrated in FIG. 8. As shown in FIG. 9,
the equivalent circuit diagram of the ESD protection structure 900
comprises a diode 910 connected in series with an NPN transistor
920. During an ESD event, the operation principle of the equivalent
circuit diagram 900 is similar to that of the equivalent circuit
diagram 200 shown in FIG. 2, and hence is not discussed in detail
herein.
[0049] FIG. 10 illustrates a simplified cross-sectional view of an
ESD protection structure in accordance with yet another embodiment.
The structure configuration of FIG. 10 is similar to FIG. 8 except
that FIG. 10 comprises a PNP transistor rather than an NPN
resistor. In comparison with FIG. 8, each p-type region is replaced
by its corresponding n-type region. Likewise, each n-type region is
replaced by its corresponding p-type region. The operation
principles of the PNP transistor based ESD protection structure
1000 is similar to its NPN transistor based counterpart 800 shown
in FIG. 8, and hence are not discussed in further detail
herein.
[0050] It should be noted that in FIG. 10 the metal contact 1052 is
an n-type metal contact. In accordance with an embodiment, the
metal contact 1052 may be formed of TiN. As shown in FIG. 10, the
n-type metal contact 1052 is formed on the SHP region 1012. As a
result, a second depletion region is formed by the n-type metal
contact 1052 and the SHP region 1012. Similar to the second
depletion region formed by a p-type metal contact 852 and the SHN
region 812 in FIG. 8, the second depletion region in FIG. 10 can
provide extra headroom during an ESD event.
[0051] FIG. 11 illustrates an equivalent circuit diagram of the ESD
protection structure 1000 illustrated in FIG. 10. As shown in FIG.
11, the equivalent circuit diagram of the ESD protection structure
1100 comprises a diode 1110 connected in series with a PNP
transistor 1120. During an ESD event, the operation principle of
the equivalent circuit diagram 1100 is similar to that of the
equivalent circuit diagram 200 shown in FIG. 2, and hence is not
discussed in detail herein.
[0052] FIG. 12 illustrates an integrated circuit level ESD
protection diagram in accordance with embodiment. An integrated
circuit chip 1200 has a VDD pad 1208, an I/O pad 1206 and a VSS pad
1204. Internal circuits 1202 are coupled to the VDD pad 1208 and
VSS pad 1204. The internal circuits 1202 further include an input
coupled to the I/O pad 1206. The ESD protection circuit 200 is
coupled between the I/O pad 1206 and the VSS pad 1204. It should be
noted that the ESD protection circuit 200 is provided for
illustrative purpose only. The ESD protection circuit between the
I/O pad 1206 and the VSS pad 1204 may comprise any variations of
the ESD protection circuits 200 shown in FIG. 2. For example, the
ESD protection circuit may be any of the ESD protection circuits
500, 700, 900 and 1100 shown in FIG. 5, FIG. 7, FIG. 9 and FIG. 11
respectively.
[0053] When an ESD event occurs between the I/O pad 1206 and the
VSS pad 1204, the ESD protection circuit 200 conducts the ESD
current, and the turn-on of an ESD protection circuit (e.g., the
ESD protection circuit 200) clamps the voltage between the I/O pad
1206 and the VSS pad 1204 below the maximum voltage to which the
internal circuits 1202 are specified, so that the internal circuits
1202 coupled between the I/O pad 1206 and the VSS pad 1204 are
protected. An advantageous feature of the described circuit level
ESD protection is the ESD protection circuit provides a bypass for
ESD current to flow so that the various circuit components of the
internal circuit 1202 are protected.
[0054] It should be noted that the ESD protection circuit 200 may
be coupled between the VDD pad 1208 and the VSS pad 1204 as
indicated by the dashed line in FIG. 12. When an ESD event occurs
between the VDD pad 1208 and the VSS pad 1204, the conduction of
the ESD protection circuit clamps the voltage between the VDD pad
1208 and the VSS pad 1204, so that the internal circuits such as
internal circuits 1202 are protected. In short, the connection of
the ESD device 200 in FIG. 12 is merely an example, which should
not unduly limit the scope of the claims. One skilled in the art
will recognize many variations, alternatives, and modifications.
For example, the ESD protection circuit 200 may comprise a
plurality of NPN transistors connected in series.
[0055] FIG. 13 illustrates a further ESD protection scheme by
employing a plurality of ESD protection circuits in series
connection between an I/O pad and a VSS pad. Similar to FIG. 12,
FIG. 13 includes an integrated circuit 1200, a VDD pad 1208, an I/O
pad 1206, a VSS pad 1204 and internal circuits 1202. However, FIG.
13 further includes a series connection of ESD protection circuits
electrically coupled to the I/O pad 1206 and the VSS pad 1204. In
high voltage applications, a single ESD protection circuit such as
the ESD protection circuit 200 shown in FIG. 13 may not provide a
reliable ESD protection. By contrast, a plurality of ESD protection
circuits 200 connected in series may provide an adjustable ESD
protection breakdown voltage as well as an adjustable ESD
protection current. As shown in FIG. 13, the ESD protection
circuits 200 connected in series are substantially identical. It
should be noted that "substantially identical" means the same
design but could be different from each other due to fabrication
process variations.
[0056] In FIG. 13, if an ESD event occurs, a voltage spike is
applied between the I/O pad 1206 and the VSS pad 1204. The
series-connected ESD protection circuits may turn on nearly
simultaneously. Each ESD protection circuit provides an ESD
protection breakdown voltage. The sum of all series-connected ESD
protection circuits' breakdown voltages clamps the I/O pad's
voltage 1206 to a level below the maximum rating voltage of the
internal circuits 1202, so that the internal circuits 1202 are
protected.
[0057] As described above with respect to FIG. 12, placing an ESD
device (e.g., ESD protection device 200) between the I/O pad 1206
and the VSS pad 1204 in FIG. 13 is merely an example. One skilled
in the art will recognize many variations, alternatives, and
modifications, such as connecting the ESD device between the VDD
pad 1208 and the VSS pad 1204 as indicated by the dashed line in
FIG. 13.
[0058] Although embodiments of the present invention and its
advantages have been described in detail, it should be understood
that various changes, substitutions and alterations can be made
herein without departing from the spirit and scope of the invention
as defined by the appended claims.
[0059] Moreover, the scope of the present application is not
intended to be limited to the particular embodiments of the
process, machine, manufacture, composition of matter, means,
methods and steps described in the specification. As one of
ordinary skill in the art will readily appreciate from the
disclosure of the present invention, processes, machines,
manufacture, compositions of matter, means, methods, or steps,
presently existing or later to be developed, that perform
substantially the same function or achieve substantially the same
result as the corresponding embodiments described herein may be
utilized according to the present invention. Accordingly, the
appended claims are intended to include within their scope such
processes, machines, manufacture, compositions of matter, means,
methods, or steps.
* * * * *