U.S. patent application number 17/433347 was filed with the patent office on 2022-05-26 for packaging substrate and semiconductor apparatus comprising same.
This patent application is currently assigned to ABSOLICS INC.. The applicant listed for this patent is ABSOLICS INC.. Invention is credited to Byungkyu JANG, Jincheol KIM, Sungjin KIM, Youngho RHO.
Application Number | 20220165650 17/433347 |
Document ID | / |
Family ID | |
Filed Date | 2022-05-26 |
United States Patent
Application |
20220165650 |
Kind Code |
A1 |
KIM; Sungjin ; et
al. |
May 26, 2022 |
PACKAGING SUBSTRATE AND SEMICONDUCTOR APPARATUS COMPRISING SAME
Abstract
The embodiment relates to a packaging substrate and a
semiconductor apparatus, including an element unit including a
semiconductor element; and a packaging substrate electrically
connected to the element unit; and it applies a glass substrate as
a core of the packaging substrate, thereby can significantly
improve electrical properties such as a signal transmission rate by
connecting the semiconductor element and a motherboard to be closer
to each other so that electrical signals are transmitted through as
short a path as possible. Therefore, it can significantly improve
electrical properties such a signal transmission rate,
substantially prevent generating of parasitic element, and simplify
a process of treatment for an insulating layer, and thus provides a
packaging substrate applicable to a high-speed circuit.
Inventors: |
KIM; Sungjin; (SUWANEE,
GA) ; RHO; Youngho; (Daejeon, KR) ; KIM;
Jincheol; (Hwaseong-si, KR) ; JANG; Byungkyu;
(Suwon-si, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
ABSOLICS INC. |
Covington |
GA |
US |
|
|
Assignee: |
ABSOLICS INC.
Covington
GA
|
Appl. No.: |
17/433347 |
Filed: |
March 6, 2020 |
PCT Filed: |
March 6, 2020 |
PCT NO: |
PCT/KR2020/003175 |
371 Date: |
August 24, 2021 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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62814941 |
Mar 7, 2019 |
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62816965 |
Mar 12, 2019 |
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International
Class: |
H01L 23/498 20060101
H01L023/498; H01L 23/15 20060101 H01L023/15 |
Claims
1. A semiconductor apparatus comprising: a semiconductor element
unit where one or more semiconductor elements are disposed; a
packaging substrate electrically connected to the semiconductor
element; and a motherboard electrically connected to the packaging
substrate, transmitting electrical signals of the semiconductor
element and external, and connecting each other; wherein a
packaging substrate comprises a core layer, and an upper layer
disposed on the core layer, wherein the core layer comprises a
glass substrate and a core via, the glass substrate is with a first
surface and a second surface facing each other, the core via
penetrating through the glass substrate in a thickness direction is
disposed in a plural number, the core layer comprises a core
distribution layer disposed on a surface of the glass substrate or
the core via, the core distribution layer comprises an electrically
conductive layer at least a part of which electrically connect an
electrically conductive layer of the first surface and an
electrically conductive layer of the second surface through the
core via, and the upper layer is disposed on the first surface and
comprises an electrically conductive layer which electrically
connect the core distribution layer and semiconductor element unit
of external; wherein the core via comprises a first surface opening
part diameter, a second surface opening part diameter, and a
minimum inner diameter, wherein the first surface opening part
diameter is a diameter at an opening part in contact with the first
surface, the second surface opening part diameter is a diameter at
an opening part in contact with the second surface, and the minimum
inner diameter is a diameter at the narrowest area disposed between
the first surface opening part and the second surface opening part,
and wherein at a position of the minimum inner diameter, a
thickness of the electrically conductive layer is 90% or more, when
a distance from an inner diameter surface of the core via to a
surface of an electrically conductive layer of the core via is 100%
as total.
2. The semiconductor apparatus of claim 1, wherein at an opening
part where a larger one between the first surface opening part
diameter and the second surface opening part diameter is disposed,
a thickness of the electrically conductive layer is 90% or more,
when a distance from an inner diameter surface of the core via to a
surface of an electrically conductive layer of the core via
distribution pattern is 100% as total.
3. The semiconductor apparatus of claim 1, further comprising: an
upper insulating layer and an upper distribution pattern, wherein
the upper insulating layer is an insulating layer disposed on the
first surface, the upper distribution pattern is an electrically
conductive layer at least a part of which is electrically connected
to the core distribution layer, the upper distribution pattern is
built in the upper insulating layer, the upper distribution pattern
is at least partially comprising a fine pattern, and the fine
pattern has a width and an interval of less than 4 .mu.m,
respectively.
4. The semiconductor apparatus of claim 1, wherein the packaging
substrate has a resistance value of about
27.5.times.10.sup.-6.OMEGA. or less, based on a cut one of the
packaging substrate into 100 .mu.m.times.100 .mu.m as an upper
surface size.
5. A packaging substrate comprising: a core layer, and an upper
layer disposed on the core layer, wherein the core layer comprises
a glass substrate and a core via, the glass substrate is with a
first surface and a second surface facing each other, the core via
penetrating through the glass substrate in a thickness direction is
disposed in a plural number, the core layer comprises a core
distribution layer disposed on a surface of the glass substrate or
the core via, the core distribution layer comprises an electrically
conductive layer at least a part of which electrically connect an
electrically conductive layer of the first surface and an
electrically conductive layer of the second surface through the
core via, and the upper layer is disposed on the first surface and
comprises an electrically conductive layer which electrically
connect the core distribution layer and semiconductor element unit
of external; wherein the core via comprises a first surface opening
part diameter, a second surface opening part diameter, and a
minimum inner diameter, wherein the first surface opening part
diameter is a diameter at an opening part in contact with the first
surface, the second surface opening part diameter is a diameter at
an opening part in contact with the second surface, and the minimum
inner diameter is a diameter at the narrowest area disposed between
the first surface opening part and the second surface opening part,
and wherein at a position of the minimum inner diameter, a
thickness of the electrically conductive layer is 90% or more, when
a distance from an inner diameter surface of the core via to a
surface of an electrically conductive layer of the core via is 100%
as total.
6. A semiconductor apparatus comprising: a semiconductor element
unit where one or more semiconductor elements are disposed; a
packaging substrate electrically connected to the semiconductor
element; and a motherboard electrically connected to the packaging
substrate, transmitting electrical signals of the semiconductor
element and external, and connecting each other; wherein a
packaging substrate comprises a core layer, and an upper layer
disposed on the core layer, wherein the core layer comprises a
glass substrate and a core via, the glass substrate is with a first
surface and a second surface facing each other, the core via
penetrating through the glass substrate in a thickness direction is
disposed in a plural number, the core layer comprises a core
distribution layer disposed on a surface of the glass substrate or
the core via, the core distribution layer comprises an electrically
conductive layer at least a part of which electrically connect an
electrically conductive layer of the first surface and an
electrically conductive layer of the second surface through the
core via, and the upper layer is disposed on the first surface and
comprises an electrically conductive layer which electrically
connect the core distribution layer and semiconductor element unit
of external; wherein the core distribution layer comprises a first
surface core pattern, a second surface core pattern, and a core via
pattern, wherein the first surface core pattern is an electrically
conductive layer disposed on at least a part of the first surface,
the second surface core pattern is an electrically conductive layer
disposed on at least a part of the second surface, and the core via
pattern is an electrically conductive layer electrically connecting
the first surface core pattern and the second surface core pattern
through the core via, and wherein the core via pattern has an
average distance of 1 .mu.m or less, between one surface of the
core via pattern close to an inner diameter surface of the core
via; and the inner diameter surface of the core via.
7. The semiconductor apparatus of claim 6, wherein the core via has
a first surface opening part diameter, a second surface opening
part diameter and a minimum inner diameter, wherein the first
surface opening part diameter is a diameter at an opening part in
contact with the first surface, the second surface opening part
diameter is a diameter at an opening part in contact with the
second surface, and the minimum inner diameter is a diameter at the
narrowest area disposed between the first surface opening part and
the second surface opening part, and wherein at a position of the
minimum inner diameter, a thickness of the electrically conductive
layer is 90% or more, when a distance from an inner diameter
surface of the core via to a surface of an electrically conductive
layer of the core via is 100% as total.
8. The semiconductor apparatus of claim 7, wherein the packaging
substrate has a resistance value of about
27.5.times.10.sup.-6.OMEGA. or less, based on a cut one of the
packaging substrate into 100 .mu.m.times.100 .mu.m as an upper
surface size.
9. The semiconductor apparatus of claim 6, further comprising: an
upper insulating layer and an upper distribution pattern, wherein
the upper insulating layer is an insulating layer disposed on the
first surface, the upper distribution pattern is an electrically
conductive layer at least a part of which is electrically connected
to the core distribution layer, the upper distribution pattern is
built in the upper insulating layer, the upper distribution pattern
is at least partially including a fine pattern, and the fine
pattern has a width and an interval of less than 4 .mu.m,
respectively.
10. A packaging substrate comprising: a core layer, and an upper
layer disposed on the core layer, wherein the core layer comprises
a glass substrate and a core via, the glass substrate is with a
first surface and a second surface facing each other, the core via
penetrating through the glass substrate in a thickness direction is
disposed in a plural number, the core layer comprises a core
distribution layer disposed on a surface of the glass substrate or
the core via, the core distribution layer comprises an electrically
conductive layer at least a part of which electrically connect an
electrically conductive layer of the first surface and an
electrically conductive layer of the second surface through the
core via, and the upper layer is disposed on the first surface and
comprises an electrically conductive layer which electrically
connect the core distribution layer and semiconductor element unit
of external; wherein the core distribution layer comprises a first
surface core pattern, a second surface core pattern, and a core via
pattern, wherein the first surface core pattern is an electrically
conductive layer disposed on at least a part of the first surface,
the second surface core pattern is an electrically conductive layer
disposed on at least a part of the second surface, and the core via
pattern is an electrically conductive layer electrically connecting
the first surface core pattern and the second surface core pattern
through the core via, and wherein the core via pattern has an
average distance of 1 .mu.m or less, between one surface of the
core via pattern close to an inner diameter surface of the core
via; and the inner diameter surface of the core via.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims priority to U.S. Provisional Patent
Application No. 62/814,941, filed on Mar. 7, 2019, and US
Provisional Patent Application No. 62/816,965, filed on Mar. 12,
2019, and all the benefits accruing therefrom under the priority,
the content of which in their entireties are herein incorporated by
reference.
FIELD
[0002] The embodiments relate to packaging substrate, and
semiconductor apparatus comprising same.
RELATED ART
[0003] In the manufacturing of electronic components, the
implementation of a circuit on a semiconductor wafer is referred to
as a Front-End Process (FE), and the assembly of a wafer such that
it can be actually used in a product is referred to as a Back-End
Process (BE). A packaging process is included in the Back-End
process.
[0004] Four key technologies of the semiconductor industry that
enable the rapid development of electronic products in recent years
include semiconductor technology, semiconductor packaging
technology, manufacturing process technology, and software
technology. Semiconductor technology has been developed in various
forms such as line width of a nanometer unit, which is smaller than
a micrometer unit, 10 million or more cells, high-speed operation,
and much heat dissipation, but technology of packaging it
completely is not supported yet. Thus, the electrical performance
of semiconductors may be determined by the packaging technology and
the resulting electrical connection rather than the performance of
the semiconductor itself.
[0005] Ceramic or resin is used as the material of a packaging
substrate. In the case of a ceramic substrate such as Si substrate,
it is not easy to mount a high-performance and high-frequency
semiconductor element thereon due to a high resistance or high
dielectric constant. In the case of a resin substrate, it is
possible to mount a high-performance and high-frequency
semiconductor element thereon, but there is a distinct limitation
to the reduction of pitches of wirings.
[0006] Recently, research is being conducted to apply silicon or
glass to a high-end packaging substrate. By forming a through-via
on a silicon or glass substrate and applying a conductive material
into the through-via, it is possible to shorten a length of
conductive lines between an element and a motherboard, and have
excellent electric characteristics.
[0007] As related art documents, there are [0008] Korean Patent
Publication No. 10-2019-0008103, [0009] Korean Patent Publication
No. 10-2016-0114710, [0010] Korean Patent No. 10-1468680, and the
like.
DISCLOSURE
Technical Problem
[0011] The objective of the embodiment is to provide a more
integrated packaging substrate and a semiconductor apparatus
comprising same, by applying a glass substrate.
Technical Solution
[0012] To achieve the above objective, a semiconductor apparatus
according to one embodiment includes:
[0013] a semiconductor element unit where one or more semiconductor
elements are disposed; a packaging substrate electrically connected
to the semiconductor element; and a motherboard electrically
connected to the packaging substrate, transmitting electrical
signals of the semiconductor element and external, and connecting
each other;
[0014] wherein a packaging substrate includes a core layer, and an
upper layer disposed on the core layer,
[0015] the core layer includes a glass substrate and a core
via,
[0016] the glass substrate is with a first surface and a second
surface facing each other,
[0017] the core via penetrating through the glass substrate in a
thickness direction is disposed in a plural number,
[0018] the core layer includes a core distribution layer disposed
on a surface of the glass substrate or the core via,
[0019] the core distribution layer includes an electrically
conductive layer at least a part of which electrically connect an
electrically conductive layer of the first surface and an
electrically conductive layer of the second surface through the
core via, and
[0020] the upper layer is disposed on the first surface and
includes an electrically conductive layer which electrically
connect the core distribution layer and semiconductor element unit
of external;
[0021] wherein the core via has a first surface opening part
diameter which is a diameter at an opening part in contact with the
first surface, a second surface opening part diameter which is a
diameter at an opening part in contact with the second surface, and
a minimum inner diameter which is a diameter at the narrowest area
disposed between the first surface opening part and the second
surface opening part, and
[0022] wherein at a position of the minimum inner diameter, a
thickness of the electrically conductive layer is 90% or more, when
a distance from an inner diameter surface of the core via to a
surface of an electrically conductive layer of the core via is 100%
as total.
[0023] In one embodiment, at an opening part where a larger one
between the first surface opening part diameter and the second
surface opening part diameter is disposed, a thickness of the
electrically conductive layer may be 90% or more, when a distance
from an inner diameter surface of the core via to a surface of an
electrically conductive layer of the core distribution layer is
100% as total.
[0024] In one embodiment, an upper insulating layer and an upper
distribution pattern may be included,
[0025] wherein the upper insulating layer may be disposed on the
first surface,
[0026] the upper distribution pattern may be an electrically
conductive layer at least a part of which is electrically connected
to the core distribution layer, and built in the upper insulating
layer,
[0027] the upper distribution pattern may be at least partially
including a fine pattern, and
[0028] the fine pattern may have a width and an interval of less
than 4 .mu.m, respectively.
[0029] In one embodiment, the packaging substrate may have a
resistance value of about 27.5.times.10.sup.-6.OMEGA. or less,
based on a cut one of the packaging substrate into 100
.mu.m.times.100 .mu.m as an upper surface size.
[0030] To achieve the above objective, a packaging substrate
according to one embodiment includes:
[0031] a core layer, and an upper layer disposed on the core
layer,
[0032] wherein the core layer includes a glass substrate and a core
via,
[0033] the glass substrate is with a first surface and a second
surface facing each other,
[0034] the core via penetrating through the glass substrate in a
thickness direction is disposed in a plural number,
[0035] the core layer includes a core distribution layer disposed
on a surface of the glass substrate or the core via,
[0036] the core distribution layer includes an electrically
conductive layer at least a part of which electrically connect an
electrically conductive layer of the first surface and the second
surface through the core via, and
[0037] the upper layer is disposed on the first surface and
includes an electrically conductive layer which electrically
connect the core distribution layer and semiconductor element unit
of external;
[0038] wherein the core via has a first surface opening part
diameter which is a diameter at an opening part in contact with the
first surface, a second surface opening part diameter which is a
diameter at an opening part in contact with the second surface, and
a minimum inner diameter which is a diameter at the narrowest area
disposed between the first surface opening part and the second
surface opening part, and
[0039] wherein a thickness of a thinner one among electrically
conductive layers of the core distribution layer, may be the same
as or thicker than a width of a thinner one among electrically
conductive layers of the upper layer.
[0040] To achieve the above objective, a semiconductor element
according to another embodiment includes:
[0041] a semiconductor element unit where one or more semiconductor
elements are disposed; a packaging substrate electrically connected
to the semiconductor element; and a motherboard electrically
connected to the packaging substrate, transmitting electrical
signals of the semiconductor element and external, and connecting
each other;
[0042] wherein a packaging substrate includes a core layer, and an
upper layer disposed on the core layer,
[0043] the core layer includes a glass substrate and a core
via,
[0044] the glass substrate is with a first surface and a second
surface facing each other,
[0045] the core via penetrating through the glass substrate in a
thickness direction is disposed in a plural number,
[0046] the core layer includes a core distribution layer disposed
on a surface of the glass substrate or the core via,
[0047] the core distribution layer includes an electrically
conductive layer at least a part of which electrically connect an
electrically conductive layer of the first surface and the second
surface through the core via, and
[0048] the upper layer is disposed on the first surface and
includes an electrically conductive layer which electrically
connect the core distribution layer and semiconductor element unit
of external;
[0049] wherein the core distribution layer includes a first surface
core pattern which is an electrically conductive layer disposed on
at least a part of the first surface, a second surface core pattern
which is an electrically conductive layer disposed on at least a
part of the second surface, and a core via pattern which is an
electrically conductive layer electrically connecting the first
surface core pattern and the second surface core pattern through
the core via,
[0050] wherein the core via has a first surface opening part
diameter which is a diameter at an opening part in contact with the
first surface, a second surface opening part diameter which is a
diameter at an opening part in contact with the second surface, and
a minimum inner diameter which is a diameter at the narrowest area
disposed between the first surface opening part and the second
surface opening part, and
[0051] wherein the core via pattern may have an average distance of
1 .mu.m or less, between one surface of the core via pattern close
to an inner diameter surface of the core via; and the inner
diameter surface of the core via.
[0052] In one embodiment, at a position of the minimum inner
diameter, a thickness of the electrically conductive layer may be
90% or more, when a distance from an inner diameter surface of the
core via to a surface of the electrically conductive layer of the
core via is 100% as total.
[0053] In one embodiment, the packaging substrate may have a
resistance value of about 27.5.times.10.sup.-6.OMEGA. or less,
based on an upper surface of the one being cut into the size of 100
.mu.m.times.100 .mu.m.
[0054] In one embodiment, an upper insulating layer and an upper
distribution pattern may be included,
[0055] wherein the upper insulating layer may be disposed on the
first surface,
[0056] the upper distribution pattern may be an electrically
conductive layer at least a part of which is electrically connected
to the core distribution layer, and built in the upper insulating
layer,
[0057] the upper distribution layer may be at least partially
including a fine pattern, and
[0058] the fine pattern may have a width and an interval of less
than 4 .mu.m, respectively.
[0059] To achieve the above objective, a packaging substrate
according to another embodiment includes:
[0060] a core layer, and an upper layer disposed on the core
layer,
[0061] wherein the core layer includes a glass substrate and a core
via,
[0062] the glass substrate is with a first surface and a second
surface facing each other,
[0063] the core via penetrating through the glass substrate in a
thickness direction is disposed in a plural number,
[0064] the core layer includes a core distribution layer disposed
on a surface of the glass substrate or the core via,
[0065] the core distribution layer includes an electrically
conductive layer at least a part of which electrically connect an
electrically conductive layer of the first surface and the second
surface through the core via, and
[0066] the upper layer is disposed on the first surface and
includes an electrically conductive layer which electrically
connect the core distribution layer and semiconductor element unit
of external;
[0067] wherein the core distribution layer includes a first surface
core pattern which is an electrically conductive layer disposed on
at least a part of the first surface, a second surface core pattern
which is an electrically conductive layer disposed on at least a
part of the second surface, and a core via pattern which is an
electrically conductive layer electrically connecting the first
surface core pattern and the second surface core pattern through
the core via,
[0068] wherein the core via has a first surface opening part
diameter which is a diameter at an opening part in contact with the
first surface, a second surface opening part diameter which is a
diameter at an opening part in contact with the second surface, and
a minimum inner diameter which is a diameter at the narrowest area
disposed between the first surface opening part and the second
surface opening part, and
[0069] wherein the core via pattern may have an average distance of
1 .mu.m or less, between one surface of the core via pattern close
to an inner diameter surface of the core via; and the inner
diameter surface of the core via.
Effects
[0070] Packaging substrate and semiconductor apparatus comprising
same of the embodiment can significantly improve electrical
properties such as a signal transmission rate by connecting the
semiconductor element and a motherboard to be closer to each other
so that electrical signals are transmitted through as short a path
as possible.
[0071] Also, since a glass substrate applied as a core of substrate
is an insulator itself, there is a lower possibility of generating
parasitic element compared to a conventional silicon core, and thus
it is possible to simplify a process of treatment for an insulating
layer and it is also applicable to a high-speed circuit.
[0072] In addition, unlike silicon being manufactured in the form
of a round wafer shape, the glass substrate is manufactured in the
form of a large panel, and thus mass production is relatively easy
and economic efficiency can be further improved.
BRIEF DESCRIPTION OF THE DRAWINGS
[0073] FIG. 1 is a conceptual view for illustrating a cross section
of a semiconductor apparatus according to one embodiment.
[0074] FIG. 2 is a conceptual view for illustrating a cross section
of a packaging substrate according to another embodiment.
[0075] FIGS. 3 (a) and (b) are conceptual views for illustrating a
cross section of a core via applied to the embodiment,
respectively.
[0076] FIG. 4 is a conceptual view for illustrating a shape of a
core distribution pattern formed on a glass substrate and a
thickness of an electrically conductive layer by a cross sections
thereof.
[0077] FIG. 5 and FIG. 6 are detailed conceptual views for
illustrating a part of cross sections of a packaging substrate
according to the embodiment, respectively.
[0078] FIGS. 7 to 9 are flowcharts for illustrating a process of
manufacturing a packaging substrate according to the embodiment by
using cross sections thereof.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS
[0079] Hereinafter, examples will be described in detail with
reference to the accompanying drawings so that they can be easily
practiced by those skilled in the art to which the embodiment
pertains. However, the embodiment may be embodied in many different
forms and is not to be construed as being limited to the
embodiments set forth herein. Like reference numerals designate
like elements throughout the specification.
[0080] Throughout the present specification, the phrase
"combination(s) thereof" included in a Markush-type expression
denotes one or more mixtures or combinations selected from the
group consisting of components stated in the Markush-type
expression, that is, denotes that one or more components selected
from the group consisting of the components are included.
[0081] Throughout the present specification, terms such as "first,"
"second," "A," or "B" are used to distinguish the same terms from
each other. The singular forms "a," "an," and "the" include the
plural form unless the context clearly dictates otherwise.
[0082] Throughout the present specification, the term "X-based" may
mean that a compound includes a compound corresponding to X, or a
derivative of X.
[0083] Throughout the present specification, "B being disposed on
A" means that B is disposed in direct contact with A or disposed
over A with another layer or structure interposed therebetween and
thus should not be interpreted as being limited to B being disposed
in direct contact with A.
[0084] Throughout the present specification, "B being connected to
A" means that B is connected to A directly or through another
element therebetween, and thus should not be interpreted as being
limited to B being directly connected to A, unless otherwise
noted.
[0085] Throughout the present specification, a singular form is
contextually interpreted as including a plural form as well as a
singular form unless specially stated otherwise.
[0086] The inventors have recognized that, in the process of
developing a semiconductor apparatus capable of exhibiting high
performance with a more integrated and thinner thickness, not only
the apparatus itself but also the packaging process is an important
factor for improving its performance. And while researching this,
inventors have confirmed that, by applying a glass core in a single
layer and controlling the shape of a through-via, an electrically
conductive layer formed thereon, etc., it is possible to make a
packaging substrate thinner and to improve the electrical
properties of the semiconductor apparatus, unlike a conventional
interposer and organic substrate in which two or more layers of
cores are applied on a motherboard as a packaging substrate, and
thereby completed the invention.
[0087] FIG. 1 is a conceptual view for illustrating a cross section
of a semiconductor apparatus according to one embodiment, FIG. 2 is
a conceptual view for illustrating a cross section of a packaging
substrate according to another embodiment, FIGS. 3 (a) and (b) are
conceptual views for illustrating a cross section of a core via
applied to the embodiment, respectively, FIG. 4 is a conceptual
view for illustrating a shape of a core distribution pattern formed
on a glass substrate and a thickness of an electrically conductive
layer by a cross sections thereof, and FIG. 5 and FIG. 6 are
detailed conceptual views for illustrating a part of cross sections
of a packaging substrate according to the embodiment, respectively.
Hereinafter, the embodiment will be described in more detail with
reference to FIGS. 1 to 5.
[0088] To achieve the above objective, a semiconductor apparatus
100 according to the embodiment includes a semiconductor element
unit 30 where one or more semiconductor elements 32, 34, and 36 are
disposed; a packaging substrate 20 electrically connected to the
semiconductor element; and a motherboard 10 electrically connected
to the packaging substrate, transmitting electrical signals of the
semiconductor element and external, and connecting each other.
[0089] The packaging substrate 20 according to another embodiment
includes a core layer 22 and an upper layer 26.
[0090] The semiconductor element unit 30 refers to the elements
mounted on a semiconductor apparatus and is mounted on the
packaging substrate 20 through a connecting electrode or the like.
In detail, for example, a computation element (a first element 32
and a second element 34) such as a central processing unit (CPU)
and a graphics processing unit (GPU), a memory element (a third
element 36) such as a memory chip, or the like may be applied as
the semiconductor element unit 30, but any semiconductor element
capable of being mounted on a semiconductor apparatus may be
applicable without limitation.
[0091] A motherboard such as a printed circuit board and a printed
wiring board may be applied as the motherboard 10.
[0092] The packaging substrate 20 includes a core layer 22 and an
upper layer 26 disposed on one surface of the core layer.
[0093] The packaging substrate 20 may further include a lower layer
29 disposed under the core layer, optionally.
[0094] The core layer 22 includes a glass substrate 21; a plurality
of core via 23 penetrating through the glass substrate 21 in a
thickness direction; and a core distribution layer 24 disposed on a
surface of the glass substrate or a surface of the core via, and
where an electrically conductive layer at least a part of which
electrically connect an electrically conductive layer of the first
surface and an electrically conductive layer of the second surface
through the core via, is disposed.
[0095] The glass substrate 21 has a first surface 213 and a second
surface 214 facing each other, and the two surfaces are
substantially parallel to each other and have a substantially
uniform thickness throughout the glass substrate.
[0096] A core via 23 penetrating through the first surface and the
second surface is disposed at the glass substrate 21.
[0097] Conventionally, a silicon substrate and an organic substrate
were applied to the packaging substrate of the semiconductor
apparatus, in a shape of being stacked. In case of a silicon
substrate, when it is applied to a high-speed circuit, a parasitic
element effect may occur due to its semiconductor property, and
there is an advantage of relatively large power loss. Also, in case
of an organic substrate, it requires a larger area to form a more
complicated distribution pattern, but this does not correspond to
the miniaturization trend of electronic devices. In order to form a
complicated distribution pattern within a predetermined size, it is
necessary to make patterns finer substantially, but there has been
a practical limit to the miniaturization of the patterns due to a
material property of the polymer, etc., applied to an organic
substrate.
[0098] In the embodiment, the glass substrate 21 is applied as a
supporting body for the core layer 22 to solve these problems.
Also, by applying a glass substrate and the core via 23 formed to
penetrating through the glass substrate, it is possible to provide
a packaging substrate 20 having a shortened electrical flow length,
a smaller size, a faster response, and a lower loss property.
[0099] As the glass substrate 21, a glass substrate applied to
semiconductor can be applied. For example, a borosilicate glass
substrate, a non-alkali glass substrate, or the like may be
applicable, but not limited thereto.
[0100] The glass substrate 21 may have a thickness of 1,000 .mu.m
or less, 100 to 1,000 .mu.m, or 100 to 700 .mu.m. More
specifically, the glass substrate 21 may have a thickness of 100 to
500 .mu.m. Although applying a thinner packaging substrate is
advantageous in that electrical signal transmission can be made
more efficient, but the packaging substrate also should serve as a
supporting body of packaging, so it is preferable to apply the
glass substrate 21 having the above thickness. Here, the thickness
of the glass substrate may be the thickness of the glass substrate
itself except for the thickness of an electrically conductive layer
on the glass substrate.
[0101] The core via 23 may be formed by removing a predetermined
region of the glass substrate 21. In detail, it may be formed by
etching a glass plate physically and/or chemically.
[0102] In detail, the core via 23 may be formed by applying a
method of forming a defect (flaw) on the surface of the glass
substrate by means of a laser or the like and then chemical
etching, laser etching, or the like, but not limited thereto.
[0103] The core via 23 includes a first opening part 233 in contact
with the first surface; a second opening part 234 in contact with
the second surface; and a minimum inner diameter part 235 having
the smallest inner diameter in the entire core via connecting the
first opening part and the second opening part.
[0104] A diameter CV1 of the first opening part and a diameter CV2
of the second opening part may substantially differ, or a diameter
CV1 of the first opening part and a diameter CV2 of the second
opening part may be substantially equal.
[0105] The minimum inner diameter part may be disposed in the first
opening part or the second opening part. In this case, a core via
may be a cylindrical-type or a (truncated) trigonal-pyramid-type.
In this case, a diameter CV3 of the minimum inner diameter part
corresponds to a diameter of the smaller one between the first
opening part and the second opening part.
[0106] The minimum inner diameter part may be disposed between the
first opening part and the second opening part. In this case, the
core via may be a barrel-type core via. In this case, the diameter
CV3 of the minimum inner diameter part may be smaller than a larger
one between a diameter of the first opening part and a diameter of
the second opening part.
[0107] The core distribution layer 24 includes a core distribution
pattern 241, which is an electrically conductive layer electrically
connecting the first surface and the second surface of the glass
substrate through a through-via, and a core insulating layer 223
surrounding the core distribution pattern.
[0108] The core layer 22 has an electrically conductive layer
formed therein through a core via and thus serves as an electrical
passage crossing the glass substrate 21, connects an upper and a
lower part of the glass substrate with a relatively short distance,
and thereby may have properties of faster electrical signal
transmission and lower loss.
[0109] The core distribution pattern 241 is a pattern that
electrically connect the first surface 213 and the second surface
214 of the glass substrate through a core via 23, and,
specifically, it includes a first surface distribution pattern
241a, which is an electrically conductive layer disposed on at
least a part of the first surface 213, a second surface
distribution pattern 241c, which is an electrically conductive
layer disposed on at least a part of the second surface 214, and a
core via distribution pattern 241b, which is an electrically
conductive layer electrically connecting the first surface
distribution pattern and the second surface distribution pattern to
each other through the core via 23. As the electrically conductive
layers, for example, a copper plating layer may be applicable, but
not limited thereto.
[0110] The core via 23 includes a first opening part 233 in contact
with the first surface; a second opening part 234 in contact with
the second surface; and a minimum inner diameter part 235 which is
an area with the narrowest inner diameter in the entire core via
connecting the first opening part and the second opening part.
[0111] The glass substrate 21 serves as an intermediate role or an
intermediary role, connecting a semiconductor element unit 30 and a
motherboard 10 to an upper and a lower part thereof, respectively,
and the core via 23 serves as a transmitting passage for electrical
signals thereof, thereby facilitating signal transmission.
[0112] A thickness of an electrically conductive layer measured at
a larger one between the first surface opening part diameter and
the second surface opening part diameter may be equal to or thicker
than a thickness of an electrically conductive layer formed on a
part with a minimum inner diameter in a core via.
[0113] The core distribution layer 24 is an electrically conductive
layer formed on a glass substrate, and may satisfy that a cross-cut
adhesion test value according to ASTM D3359 is 4 B or greater, and
specifically may satisfy that the cross-cut adhesion test value is
5 B or greater. Also, an electrically conductive layer which is a
core distribution layer 24, may have an adhesive strength of 3 N/cm
or more and a bonding strength of 4.5 N/cm or more with respect to
the glass substrate 21. When such a degree of bonding strength is
satisfied, it has a sufficient bonding strength between a substrate
and an electrically conductive layer, to be applied as a packaging
substrate.
[0114] An upper layer 26 is disposed on the first surface 213.
[0115] The upper layer 26 may include an upper distribution layer
25 and an upper surface connecting layer 27 disposed on the upper
distribution layer 25, and the uppermost surface of the upper layer
26 may be protected by a cover layer 60 having an opening part
formed thereon, which is capable of being in direct contact with a
connecting electrode of the semiconductor element unit.
[0116] The upper distribution layer 25 includes an upper insulating
layer 253 disposed on the first surface; and an upper distribution
pattern 251 that has a predetermined pattern and is an electrically
conductive layer at least a part of which is electrically connected
to the core distribution layer 24, and built in the upper insulting
layer.
[0117] Anything applied as an insulating layer to a semiconductor
element or a packaging substrate, is applicable to the upper
insulating layer 253, for example, an epoxy-based resin comprising
a filler may be applied, but not limited thereto.
[0118] The insulating layer may be formed by a method of forming
and hardening a coating layer, or by a method of laminating an
insulating film which is being filmed in a state of non-hardened or
semi-hardened to a core layer and hardening it. In this time, when
a method of pressure sensitive lamination and the like is applied,
the insulator is embedded even in the space inside a core via, and
thus efficient process proceeding can be made. Also, even though
plural-layered insulating layers are applied with being stacked,
substantial distinction between the layers may be difficult, so
that a plurality of insulating layer are collectively referred to
as an upper insulating layer. Also, the core insulating layer 223
and the upper insulating layer 253 may be applied with the same
insulating material, and in this case, the boundary therebetween
may not be substantially distinguished.
[0119] The upper distribution pattern 251 refers to an electrically
conductive layer disposed in the upper insulating layer 253 in a
predetermined form. For example, it may be formed by a method of a
build-up layer method. In detail, the upper distribution pattern
251 where electrically conductive layer is vertically or
horizontally formed in a desired pattern, may be formed by
repeating a process of: forming an insulating layer, removing an
unnecessary part of the insulating layer and then forming an
electrically conductive layer through a method of copper plating
and the like, removing an unnecessary part of the electrically
conductive layer and then forming an insulating layer on this
electrically conductive layer again, and removing an unnecessary
part again and then forming an electrically conductive layer
through a method of plating and the like.
[0120] Since the upper distribution pattern 251 is disposed between
the core layer 22 and the semiconductor element unit 30, it is
formed to at least partially includes a fine pattern so that the
transmission of electrical signals with the semiconductor element
unit 30 may proceed smoothly and a desired complicated pattern may
be sufficiently accommodated. In this case, the fine pattern may
have a width and an interval of about less than 4 um, 3.5 .mu.m or
less, 3 .mu.m or less, 2.5 .mu.m or less, or 1 to 2.3 .mu.m,
respectively (Hereinafter, the description of the fine pattern is
the same).
[0121] In order to form the upper distribution pattern 251 to
include a fine pattern, at least two or more methods are applied in
the present disclosure.
[0122] One of them, is to apply a glass substrate 21, as a glass
substrate 21 of a packaging substrate. The glass substrate 21 can
have a considerably flat surface property with a surface roughness
(Ra) of 10 angstroms or less, and thereby minimizing the influence
of surface morphology of a supporting substrate on formation of the
fine pattern.
[0123] The other one, is based on the property of the insulating
layer. In case of the insulating layer, a filler component is often
applied in addition to resin, and inorganic particles such as
silica particles may be applicable as the filler. When the
inorganic particles are applied to the insulating layer as the
filler, the size of the inorganic particles can affect whether to
form the fine pattern, and therefore, the insulating layer in the
present disclosure applies particle fillers with an average
diameter of about 150 nm or less, and in detail, including particle
fillers with an average diameter of 1 to 100 nm. Such a
characteristic can minimize the influence of the insulating layer
itself on the formation of an electrically conductive layer with a
width of several micrometer-unit, while maintaining necessary
properties for the insulating layer at a certain level or more, and
can also help to form a fine pattern with good adhesion onto the
surface, due to the fine surface morphology.
[0124] The upper surface connecting layer 27 includes an upper
surface connecting pattern 272 disposed in the upper insulating
layer 253, and at least a part of which is electrically connected
to the upper distribution pattern 251, and an upper surface
connecting electrode 271, electrically connecting the semiconductor
element unit 30 and the upper surface connecting pattern 272. The
upper surface connecting pattern 272 may be disposed on one surface
of the upper insulating layer 253 or may be embedded with at least
a part of which is being exposed on the upper insulating layer. For
example, when the upper surface connecting pattern is disposed on
one side of the upper insulating layer, the upper insulating layer
may be formed by a method of plating and the like, and when the
upper surface connecting pattern is embedded with at least a part
of which is being exposed on the upper insulating layer, it may be
the one which is formed by forming a copper plating layer and the
like, and then a part of an insulating layer or electrically
conductive layer is removed by a method of surface polishing,
surface etching and the like.
[0125] The upper surface connecting pattern 272 may at least
partially include a fine pattern like the above-described upper
distribution pattern 251. The upper surface connecting pattern 272
including the fine pattern like this may enable a larger number of
elements to be electrically connected to one another even in a
narrow area, facilitate electrical signal connection between
elements or with the external, and more integrated packaging is
possible.
[0126] The upper surface connecting electrode 271 may be connected
to the semiconductor element unit 30 directly through a terminal
and the like or via an element connecting unit 51 such as a solder
ball.
[0127] The packaging substrate 20 is also connected to the
motherboard 10. The motherboard 10 may be directly connected to the
second surface distribution pattern 241c, which is a core
distribution layer disposed on at least a part of the second
surface 214 of the core layer 22, through a motherboard terminal or
may be electrically connected via a board connecting unit such as a
solder ball. Also, the second surface distribution pattern 241c may
be connected to the motherboard 10 via the lower layer 29 disposed
under the core layer 22.
[0128] The lower layer 29 includes a lower distribution layer 291
and a lower surface connecting layer 292.
[0129] The lower distribution layer 291 includes i) a lower
insulating layer 291b at least a part of which is in contact with
the second surface 214; and ii) a lower distribution pattern 291a
being embedded in the lower insulating layer and having a
predetermined pattern, and at least a part of which is electrically
connected to the core distribution layer.
[0130] The lower surface connecting layer 292 includes i) a lower
surface connecting electrode 292a electrically connected to the
lower surface connecting pattern and may further include ii) a
lower surface connecting pattern 292b at least a part of which is
electrically connected to the lower distribution pattern, and at
least a part of which is exposed to one surface of the lower
insulating layer.
[0131] The lower surface connecting pattern 292b, which is a part
connected to the motherboard 10, may be formed as a non-fine
pattern wider than the fine pattern, unlike the upper surface
connecting pattern 272, for more efficient transmitting of
electrical signals.
[0132] Not applying a substantially additional different substrate
other than the glass substrate 21 to the packaging substrate 20
disposed between the semiconductor element unit 30 and the
motherboard 10, is one feature of the present disclosure.
[0133] Conventionally, an interposer and an organic substrate were
applied with being stacked between connection of the element and
the motherboard. It is considered that such a multi-stage form has
been applied in at least two reasons. One reason is that there is a
scale problem in directly bonding the fine pattern of the element
to the motherboard, and the other reason is that problem of wiring
damage may occur due to a difference in thermal expansion
coefficient during the bonding process or during the driving
process of the semiconductor apparatus. The embodiment has solved
these problems by applying the glass substrate with a thermal
expansion coefficient similar to that of the semiconductor element,
and by forming a fine pattern with a fine scale enough to mount the
elements on the first surface of the glass substrate and its upper
layer.
[0134] In the embodiment of an electrically conductive layer
composing the core via distribution pattern 214b, a thickness of
the electrically conductive layer may be about 90% or more, about
93% to about 100%, or about 95% to about 100%, when a distance from
an inner diameter surface of the core via 22 to a surface of the
core via distribution pattern 214b is 100% as total. More
specifically, in an electrically conductive layer composing the
core via distribution pattern 214b, a thickness of the electrically
conductive layer may be about 97% to 100%, or about 96% to about
100%, when a distance from an inner diameter surface of the core
via 22 to a surface of the core via distribution pattern 214b is
100% as total.
[0135] Specifically, at a position of a minimum inner diameter, a
thickness Tcv3 of the electrically conductive layer may be about
90% or more, about 93% to about 100%, about 95% to about 100%, or
about 95.5% to about 99%, when a distance Dt3 from an inner
diameter surface of the core via 22 to a surface of the core via
distribution pattern 214b is 100% as total.
[0136] Specifically, at an opening part where a larger one between
the first surface opening part diameter and the second surface
opening part diameter is disposed, a thickness Tcv2 of the
electrically conductive layer may be about 90% or more, about 93%
to about 100%, about 95% to about 100%, or about 98% to about
99.9%, when a distance Dt2 (Assuming the second surface opening
part diameter is a larger one) from an inner diameter surface of
the core via 22 to a surface of the core via distribution pattern
214b is 100% as total.
[0137] When a thickness of the core via distribution pattern which
is an electrically conductive layer, is formed substantially
thickly inside the core via like this, more smooth electrical
conductivity can be obtained, and a process of connecting
electrical signals to a motherboard from a highly integrated
element can be made more efficient.
[0138] Also, one feature of the embodiment is that an electrically
conductive layer formed on inner diameter surface of core via, is
positioned close to a surface of a glass substrate (inner diameter
surface of core via).
[0139] Specifically, the core via pattern may have an average
distance of about 1 .mu.m or less, about 0.9 .mu.m, or about 0.01
.mu.m to about 0.9 .mu.m, between i) one surface of the core via
pattern close to an inner diameter surface of the core via; and ii)
the inner diameter surface of the core via.
[0140] An inorganic material or an organic-inorganic composite
material which improves adhesion between the core via pattern and
the glass surface or serves as a seed during a plating process, may
be disposed in a space corresponding to the above distance. The
organic-inorganic composite material may have a layered structure
of being continuously observed in the cross section, and in this
case an average thickness of the layered structure may correspond
to the average distance. The organic-inorganic composite material
may have a spotty structure of not being continuously observed in
the cross section, and in which the shapes of particles are being
located with an interval regularly or irregularly. When the
organic-inorganic composite material has the spotty structure, the
distance refers to an average value.
[0141] At the minimum inner diameter part, the core via pattern may
have a distance F3 of about 1 .mu.m or less, about 0.7 .mu.m or
less, or about 0.01 .mu.m to about 0.7 .mu.m, between i) one
surface of the core via pattern close to an inner diameter surface
of the core via; and ii) the inner diameter surface of the core
via. An organic layer, an organic-inorganic composite layer, an
adhesive layer, and the like with a thickness of about 1 .mu.m or
more, may not be substantially formed separately between an inner
diameter surface and an electrically conductive layer, in the
distance F3.
[0142] At the first opening part, the core via pattern may have a
distance (not shown) of about 1 .mu.m or less, about 0.9 .mu.m or
less, or about 0.01 .mu.m to about 0.9 .mu.m, between i) one
surface of the core via pattern close to an inner diameter surface
of the core via; and ii) the inner diameter surface of the core
via. An adhesive layer and the like with a thickness of about 1
.mu.m or more, may not be substantially formed separately between
an inner diameter surface and an electrically conductive layer, in
the above distance.
[0143] At the second opening part, the core via pattern may have a
distance F2 of about 1 .mu.m or less, about 0.9 .mu.m or less, or
about 0.01 .mu.m to about 0.9 .mu.m, between i) one surface of the
core via pattern close to an inner diameter surface of the core
via; and ii) the inner diameter surface of the core via. An
adhesive layer and the like with a thickness of about 1 .mu.m or
more, may not be substantially formed separately between an inner
diameter surface and an electrically conductive layer, in the
distance F2.
[0144] The distance (not shown) at the first opening part, the
distance F2 at the second opening part, and the distance F3 at the
minimum inner diameter part respectively refer to a distance
measured at an extension line of the first surface of the glass
substrate, a distance measured at an extension line of the second
surface of the glass substrate, and a distance measured at a
virtual line substantially parallel to the first surface or the
second surface of the glass at the minimum inner diameter part.
[0145] Within the core via, when a core via distribution pattern,
which is an electrically conductive layer, is formed close to an
inner diameter surface like this, a substantially thick
electrically conductive layer can be manufactured under the same
conditions, a more facilitated electrical conductivity as desired
can be achieved, and a process of connecting electrical signals
from a highly integrated element to a motherboard can be made more
efficient.
[0146] The semiconductor apparatus 100 having a considerably thin
packaging substrate 20 may make the overall thickness of the
semiconductor apparatus thinner, and it is also possible to dispose
a desired electrical connecting pattern even in a narrower area by
applying the fine pattern. In detail, the packaging substrate may
have a thickness of about 2000 .mu.m or less, about 1500 .mu.m or
less, or about 900 .mu.m. Also, the packaging substrate 20 may have
a thickness of about 120 .mu.m or more, or about 150 .mu.m or more.
Due to the above-described characteristics, the packaging substrate
can stably connect the element and the motherboard electrically and
structurally even with a relatively thin thickness, thereby
contributing to miniaturization and thinning of the semiconductor
apparatus.
[0147] The packaging substrate 20 may have a resistance value of
about 2.6.times.10.sup.-6.OMEGA. or more, about
3.6.times.10.sup.-6.OMEGA. or more, or about
20.6.times.10.sup.-6.OMEGA. or more, based on a cut one of the
packaging substrate 20 into 100 .mu.m.times.100 .mu.m as an upper
surface size. The packaging substrate may have a resistance value
of about 27.5.times.10.sup.-6.OMEGA. or less, about
25.8.times.10.sup.-6.OMEGA. or less, or about
24.1.times.10.sup.-6.OMEGA. or less. For example, the resistance
value is a measured resistance between an electrically conductive
layer of an upper layer, and an electrically conductive layer of a
lower layer, of the cut one of the packaging substrate into the
constant size described above. And it is a resistance value
measured by connecting the electrically conductive layer of the
upper layer, and the electrically conductive layer of the lower
layer to each other, by core via pattern. The resistance value may
be measured by methods described at below experimental examples.
Packaging substrate satisfying the above resistance value is
possible to easily transmit electrical signals to external.
[0148] FIGS. 7 to 9 are flowcharts for illustrating a process of
manufacturing a packaging substrate by cross sections thereof
according to the embodiment. A method of manufacturing the
packaging substrate according to another embodiment will be
described below with reference to FIGS. 7 to 9.
[0149] The method of manufacturing the packaging substrate of the
embodiment includes a preparation step of forming a defect at
predetermined positions of a first surface and a second surface of
a glass substrate; an etching step of preparing a glass substrate
with a core via formed thereon by applying an etchant to the glass
substrate where the defect is formed; a core layer forming step of
plating the surface of the glass substrate with the core via formed
thereon, to form a core distribution layer which is an electrically
conductive layer, and thereby forming a core layer; and an upper
layer forming step of forming an upper distribution layer, which is
an electrically conductive layer surrounded by an insulting layer
on one side of the core layer, and thereby manufacturing the
packaging substrate described above.
[0150] The core layer forming step may include a pretreatment
process of preparing a pretreated glass substrate by forming an
organic-inorganic composite primer layer containing a nanoparticle
with amine-group on a surface of the glass substrate where the core
via is formed; and a plating process of plating a metal layer on
the glass substrate which is pretreated.
[0151] The core layer forming step may include a pretreatment
process of preparing a pretreated glass substrate by forming a
metal-containing primer layer through sputtering on a surface of
the glass substrate where the core via is formed; and a plating
process of plating a metal layer on the glass substrate which is
pretreated.
[0152] An insulating layer forming step may be further included
between the core layer forming step and the upper layer forming
step.
[0153] The insulating layer forming step may be a step of
positioning an insulating film on the core layer and performing
pressure sensitive lamination to form a core insulating layer.
[0154] The method of manufacturing the packaging substrate will be
described in more detail.
[0155] 1) Preparation Step (Glass Defect Forming Process): A glass
substrate 21a having flat first surface and second surface was
prepared, and a defect (groove) 21b was formed at a predetermined
position on the surface of the glass substrate to form a core via.
As the glass substrate, a glass substrate applied to a substrate
for electronic apparatus, etc., for example, non-alkalic glass
substrate, etc. is applicable, but not limited thereto. As a
commercial product, product manufactured by manufacturers such as
CORNING, SCHOTT, AGC may be applied. For formation of the defect
(groove), a method of mechanical etching, laser irradiation, and
the like can be applied.
[0156] 2) Etching Step (Core Via Forming Step): On the glass
substrate 21a where the defect (groove) 21b is formed, a core via
23 is formed through a physical or chemical etching process. During
the etching process, the glass substrate forms vias in the parts
with defect, and at the same time, the surface of the glass
substrate 21a may be simultaneously etched. A masking film may be
applied to prevent the etching of the glass surface, but the
defective glass substrate itself may be etched in consideration of
the inconvenience, etc. of the process of applying and removing the
masking film, and in this case, a thickness of the glass substrate
having the core via may be slightly thinner than the thickness of
the first glass substrate.
[0157] 3-1) Core Layer Forming Step: An electrically conductive
layer 21d is formed on the glass substrate. As for the electrically
conductive layer, a metal layer containing copper metal may be
applied representatively, but not limited thereto.
[0158] A surface of the glass (including a surface of a glass
substrate and a surface of a core via) and a surface of the copper
metal have different properties, so the adhesion strength is rather
poor. In the embodiment, the adhesion strength between the glass
surface and the metal is improved by two methods, a dry method and
a wet method.
[0159] The dry method is a method applying sputtering, that is, a
method of forming a seed layer 21c inside the core via and on the
glass surface through metal sputtering. For the formation of the
seed layer, different kinds of metals such as titanium, chromium,
and nickel may be sputtered with copper, etc., and in this case, it
is considered that the adhesiveness of glass-metal is improved by
surface morphology of glass, an anchor effect which is an
interaction between metal particles, and the like.
[0160] The wet method is a method applying primer treatment, that
is, a method of forming a primer layer 21c by performing
pre-treatment with a compound having a functional group such as
amine. After pre-treatment by using a silane coupling agent
depending on the degree of intended adhesion strength, primer
treatment may be done with a compound or particles having an amine
functional group. As mentioned above, a supporting body substrate
of the embodiment needs to be of high performance enough to form a
fine pattern, and it should be maintained after the primer
treatment. Therefore, when such a primer includes a nanoparticle,
it is desirable to apply a nanoparticle with an average diameter of
150 nm or less, for example, a nanoparticle is desirable to be
applied to a particle with amine functional group. The primer layer
may be formed by applying an adhesive strength improving agent
manufactured in CZ series by MEC Inc, for example.
[0161] In the seed layer/primer layer 21c, an electrically
conductive layer may selectively form a metal layer in the state of
removing a part where the formation of an electrically conductive
layer is unnecessary, or not removing. Also, in the seed
layer/primer layer 21c, a part where the formation of an
electrically conductive layer is necessary, or a part where it is
unnecessary, may be selectively processed to be an activated state
or an inactivated state for metal plating. The processing to be an
activated state or an inactivated state may be performed, for
example, by using light irradiation treatment such as laser light
of a certain wavelength, etc., chemical treatment, and the like. A
copper plating method, etc. applied to manufacturing a
semiconductor element may be applied to form the metal layer, but
not limited thereto.
[0162] During the metal plating, a thickness of an electrically
conductive layer formed, may be controlled by regulating several
variables such as the concentration of plating solution, plating
time, and type of additive to be applied.
[0163] When a part of the core distribution layer is unnecessary,
it may be removed, and an etched layer 21e of a core distribution
layer may be formed by performing metal plating to form an
electrically conductive layer as a predetermined pattern, after the
seed layer is partially removed or processed to be inactivated.
[0164] 3-2) Insulating Layer Forming Step: An insulating layer
forming step in which an empty space of a core via is filled with
an insulating layer after the core distribution layer, which is an
electrically conductive layer, is formed, may be performed. In this
case, the one manufactured in a film type may be applied to the
applied insulating layer, and for example, a method such as
pressure sensitive laminating the film-type insulating layer may be
applied. When proceeding the pressure sensitive laminating like
this, the insulating layer may be sufficiently subsided to the
empty space inside the core via to form a core insulating layer
without void formation.
[0165] 4) Upper Layer Forming Step: It is a step of forming an
upper distribution layer including an upper insulating layer and an
upper distribution pattern on a core layer. The upper distribution
layer may be formed by a method of coating a resin composition
forming an insulating layer 23a, or laminating an insulating film.
For simplicity, applying a method of laminating an insulating film
is desirable. The laminating of the insulating film may be
proceeded by a process of laminating and then hardening, and in
this case, if a method of the pressure sensitive lamination is
applied, the insulating resin may be sufficiently subsided even
into a layer where an electrically conductive layer is not formed
inside the core via. The upper insulating layer is also in direct
contact with a glass substrate at least in part thereof, and thus
the one with a sufficient adhesive force is applied. Specifically,
it is desirable that the glass substrate and the upper insulating
layer have characteristics that satisfy an adhesion strength test
value of 4 B or more according to ASTM D3359.
[0166] The upper distribution pattern may be formed by repeating a
process of forming the insulating layer 23a, forming an
electrically conductive layer 23c to have a predetermined pattern,
and forming an etched layer 23d of the electrically conductive
layer by etching the unnecessary part, and in the case of an
electrically conductive layer formed to neighbor with having an
insulating layer disposed therebetween, it may be formed by a
method of performing a plating process after forming a blind via
23b in the insulating layer. For formation of the blind via, a dry
etching method such as laser etching and plasma etching, and a wet
etching method using a masking layer and an etching solution may be
applied.
[0167] 5) Upper Surface Connecting Layer and Cover Layer Forming
Step: Upper surface connecting pattern and upper surface connecting
electrode may be performed by a process similar to forming the
upper distribution layer. Specifically, it may be formed by a
method such as forming an etched layer 23f of an insulating layer
23e on the insulating layer 23e, and then forming an electrically
conductive layer 23g again thereon, and then forming an etched
layer 23h of the electrically conductive layer, but a method of
selectively forming only an electrically conductive layer without
applying a method of etching, may be also applied. A cover layer
may be formed to have an opening part (not shown) at a position
corresponding to the upper surface connecting electrode such that
the upper surface connecting electrode to be exposed and directly
connected to an element connecting unit, a terminal of an element,
or the like.
[0168] 6) Lower Surface Connecting Layer and Cover Layer Forming
Step: A lower distribution layer and/or a lower surface connecting
layer, and optionally a cover layer (not shown) may be formed in a
manner similar to the the upper surface connecting layer and the
cover layer forming step, described above.
[0169] Hereinafter, the embodiment will be described in more detail
through specific examples. The following examples are only examples
to help the understanding of the embodiment, and the scope of the
embodiment is not limited thereto.
Example 1--Manufacturing of a Packaging Substrate
[0170] 1) Preparation Step (Glass Defect Forming Process): A glass
substrate 21a with a flat first surface and a flat second surface
was prepared, and defects (grooves, 21b) were formed on the glass
surface at a predetermined position for forming a core via. In this
case, the number of defects were allowed to form in the number of
225 per 1 cm.sup.2. As the glass, borosilicate glass (from CORNING)
was applied. A method of mechanical etching and laser irradiation
were applied to the formation of the defect (groove).
[0171] 2) Etching Step (Core Via Forming Step): The core via 23 was
formed on the glass substrate 21a where the defects (grooves, 21b)
were formed, through a physical or chemical etching process. In
this case, the core via were formed to have a first opening part in
contact with the first surface; a second opening part in contact
with the second surface; and a minimum inner diameter part, which
is the area whose diameter is the narrowest in the entire core via
connecting the first opening part and the second opening part.
[0172] 3-1) Core Layer Forming Step: An electrically conductive
layer 21d was formed on a glass substrate. As the electrically
conductive layer, a metal layer containing copper metal was
applied. By two methods of a dry method and a wet method, an
adhesive strength between a surface of the glass substrate and a
metal layer was improved. The dry method is a method applying
sputtering, that is, a method of forming a seed layer 21c inside
the core via and on the glass surface through metal sputtering. For
the formation of the seed layer, one or more different kinds of
metals from titanium, chromium, and nickel were sputtered with
copper, etc. The wet method is a method applying primer treatment,
that is, a method of forming a primer layer 21c by performing
pre-treatment with a compound having a functional group such as
amine After pre-treatment by using a silane coupling agent, primer
treatment was done with a compound or particles having an amine
functional group. A nanoparticle with an average diameter of 150 nm
or less was applied to this primer, and a nanoparticle was applied
to a particle with amine functional group. The primer layer was
formed by applying an adhesive strength improving agent
manufactured in CZ series by MEC Inc.
[0173] In the seed layer/primer layer 21c, a part where the
formation of an electrically conductive layer is necessary, or a
part where it is unnecessary, was selectively processed to be an
activated state or an inactivated state for metal plating. Light
irradiation treatment such as laser light of a certain wavelength,
etc., chemical treatment, and the like were applied to the
processing to be an activated state or an inactivated state. A
copper plating method applied to manufacturing a semiconductor
element was applied to form the metal layer.
[0174] An etched layer 21e of a core distribution layer was formed
by performing metal plating to form an electrically conductive
layer as a predetermined pattern, after the seed layer is partially
removed or processed to be inactivated. At a position of the
minimum inner diameter of the core via, the electrically conductive
layer was allowed to have a thickness of 97%, when a distance from
an inner diameter surface of the core via to a surface of the
electrically conductive layer is total 100%. Also, at an opening
part where has a larger diameter between the first opening part and
the second opening part, the electrically conductive layer was
allowed to have a thickness of 97%, when a distance from an inner
diameter surface of the core via to a surface of the electrically
conductive layer is total 100%. Furthermore, an average distance
between one surface of the electrically conductive layer near to an
inner diameter surface of the core via and the inner diameter
surface of the core via, was allowed to be 0.5 .mu.m.
[0175] 3-2) Insulation Layer Forming step: After forming the core
distribution layer, which is an electrically conductive layer, an
insulating layer forming step of filling the empty space with an
insulating layer was performed. At this time, the one manufactured
in the form of a film was applied to the applied insulating layer,
and a method of pressure sensitive lamination of the insulating
layer in the form of a film was applied.
[0176] 4) Upper Layer Forming Step: A step of forming an upper
distribution layer including an upper insulating layer and an upper
distribution pattern on the core layer was performed. A method of
laminating an insulating film as the upper insulating layer was
performed, and a process of lamination and hardening of the
insulating was performed. The upper insulating layer is also at
least partially in direct contact with the glass substrate, and
thus the one with a sufficient adhesive force was applied to.
Specifically, the one having properties that satisfy an adhesion
test value of 4 B or more according to ASTM D3359, were applied to
the glass substrate and the upper insulating layer
[0177] The upper distribution pattern was formed by repeating the
process of forming the insulating layer 23a, forming an
electrically conductive layer 23c in a predetermined pattern, and
etching unnecessary parts to form an etching layer 23d of an
electrically conductive layer. In the case of an electrically
conductive layer formed adjacent to each other with an insulating
layer disposed therebetween, it was formed by a method of forming a
blind via 23b in the insulating layer and then performing a plating
process. For the formation of the blind via, a dry etching method
such as laser etching and plasma etching, and a wet etching method
using a masking layer and an etchant were applied to manufacture a
packaging substrate.
[0178] 5) Upper Surface Connecting Layer and Cover Layer Forming
Step: A method of forming an etched layer 23f of an insulating
layer 23e on the insulating layer, and then forming an electrically
conductive layer 23g again thereon, and then forming an etched
layer 23h of the electrically conductive layer, was proceeded. A
cover layer was formed to have an opening part (not shown) at a
position corresponding to the upper surface connecting electrode
such that the upper surface connecting electrode to be exposed and
directly connected to an element connecting unit, a terminal of an
element, or the like.
[0179] 6) Lower Surface Connecting Layer and Cover Layer Forming
Step: A lower distribution layer and/or a lower surface connecting
layer, and optionally a cover layer (not shown) was formed in a
manner similar to the the upper surface connecting layer and the
cover layer forming step, described above.
[0180] A packaging substrate 20 manufactured by the above methods
comprises:
[0181] a core layer including a glass substrate 21 with a first
surface and a second surface facing each other, a plurality of core
via 23 penetrating through the glass substrate in a thickness
direction, and a core distribution layer 24 disposed on a surface
of the glass substrate or the core via, and where an electrically
conductive layer at least a part of which electrically connect an
electrically conductive layer of the first surface and an
electrically conductive layer of the second surface through the
core via, is disposed; and
[0182] an upper layer 26 disposed on the first surface and includes
an electrically conductive layer which electrically connect the
core distribution layer and semiconductor element unit of
external;
[0183] wherein the upper layer includes an upper distribution layer
25 and an upper surface connecting layer 27 disposed on the upper
distribution layer,
[0184] the upper distribution layer includes an upper insulating
layer 253 disposed on the first surface; and an upper distribution
pattern 251 that has a predetermined pattern and is an electrically
conductive layer at least a part of which is electrically connected
to the core distribution layer 24, and built in the upper insulting
layer,
[0185] the core via includes a first opening part 233 in contact
with the first surface; a second opening part 234 in contact with
the second surface; and a minimum inner diameter part 235 having
the smallest inner diameter in the entire core via connecting the
first opening part and the second opening part,
[0186] wherein a thickness Tcv3 of an electrically conductive layer
of the core distribution layer is 97%, when a distance Dt3 from an
inner diameter surface of the core via to a surface of an
electrically conductive layer of the core distribution layer is
100% as total,
[0187] wherein at an opening part where a larger diameter between
the first surface opening part and the second surface opening part
is disposed, a thickness Tcv2 of an electrically conductive layer
of the core distribution layer is 97%, when a distance Dt2 from an
inner diameter surface of the core via to a surface of an
electrically conductive layer of the core distribution layer is
100% as total, and
[0188] wherein an average distance F3, between one surface of an
electrically conductive layer of the core distribution layer close
to an inner diameter surface of the core via and the inner diameter
surface of the core, via is 0.5 .mu.m.
Example 2--Manufacturing of a Packaging Substrate
[0189] In a packaging substrate of Example 1, a packaging substrate
was manufactured by the same process with Example 1, except for
changing a thickness Tcv3 of an electrically conductive layer of
the core distribution layer to 95%, when a distance Dt3 from an
inner diameter surface of the core via to a surface of an
electrically conductive layer of the core distribution layer is
100% as total,
[0190] a thickness Tcv2 of an electrically conductive layer of the
core distribution layer to 95%, at an opening part where a larger
diameter between the first surface opening part and the second
surface opening part is disposed, when a distance Dt2 from an inner
diameter surface of the core via to a surface of an electrically
conductive layer of the core via distribution layer is 100% as
total, and
[0191] an average distance F3 to 0.75 .mu.m, between one surface of
an electrically conductive layer of the core distribution layer
close to an inner diameter surface of the core via, and the inner
diameter surface of the core via.
Example 3--Manufacturing of a Packaging Substrate
[0192] In a packaging substrate of Example 1, a packaging substrate
was manufactured by the same process with Example 1, except for
changing a thickness Tcv3 of an electrically conductive layer of
the core distribution layer to 93%, when a distance Dt3 from an
inner diameter surface of the core via to a surface of an
electrically conductive layer of the core distribution layer is
100% as total,
[0193] a thickness Tcv2 of an electrically conductive layer of the
core distribution layer to 93%, at an opening part where a larger
diameter between the first surface opening part and the second
surface opening part is disposed, when a distance Dt2 from an inner
diameter surface of the core via to a surface of an electrically
conductive layer of the core via distribution layer is 100% as
total, and
[0194] an average distance F3 to 1 .mu.m, between one surface of an
electrically conductive layer of the core distribution layer close
to an inner diameter surface of the core via, and the inner
diameter surface of the core via.
Example 4--Manufacturing of a Packaging Substrate
[0195] In a packaging substrate of Example 1, a packaging substrate
was manufactured by the same process with Example 1, except for
changing a thickness Tcv3 of an electrically conductive layer of
the core distribution layer to 92%, when a distance Dt3 from an
inner diameter surface of the core via to a surface of an
electrically conductive layer of the core distribution layer is
100% as total,
[0196] a thickness Tcv2 of an electrically conductive layer of the
core distribution layer to 92%, at an opening part where a larger
diameter between the first surface opening part and the second
surface opening part is disposed, when a distance Dt2 from an inner
diameter surface of the core via to a surface of an electrically
conductive layer of the core via distribution layer is 100% as
total, and
[0197] an average distance F3 to 1.2 .mu.m, between one surface of
an electrically conductive layer of the core distribution layer
close to an inner diameter surface of the core via, and the inner
diameter surface of the core via.
Example 5--Manufacturing of a Packaging Substrate
[0198] A packaging substrate was manufactured by the same process
with Example 1, except for changing a thickness Tcv3 of an
electrically conductive layer of the core distribution layer to
87%, when a distance Dt3 from an inner diameter surface of the core
via to a surface of an electrically conductive layer of the core
distribution layer is 100% as total,
[0199] a thickness Tcv2 of an electrically conductive layer of the
core distribution layer to 87%, at an opening part where a larger
diameter between the first surface opening part and the second
surface opening part is disposed, when a distance Dt2 from an inner
diameter surface of the core via to a surface of an electrically
conductive layer of the core via distribution layer is 100% as
total, and
[0200] an average distance F3 to 2 .mu.m, between one surface of an
electrically conductive layer of the core distribution layer close
to an inner diameter surface of the core via, and the inner
diameter surface of the core via, in the Example 1.
Experimental Example--Measurement of Electrical Properties
[0201] A packaging substrate of the Examples 1 to 5 was cut into
the size of 100 .mu.m.times.100 .mu.m based on an upper surface,
and a resistance value among electrical properties were measured by
resistivity meter. And the results are shown in Table 1.
TABLE-US-00001 TABLE 1 Example 1 Example 2 Example 3 Example 4
Example 5 Tcv3/Dt3 0.97 0.95 0.93 0.92 0.87 Tcv2/Dt2 0.97 0.95 0.93
0.92 0.87 F3 0.5 .mu.m 0.75 .mu.m 1 .mu.m 1.2 .mu.m 2 .mu.m Bulk
25.8 .times. 10.sup.-6 24.5 .times. 10.sup.-6 24.1 .times.
10.sup.-6 23.7 .times. 10.sup.-6 22.4 .times. 10.sup.-6 resistance
value (.OMEGA.)
[0202] Referring to Table 1, a packaging substrate of Examples 1 to
3 in which a thickness Tcv3 of an electrically conductive layer of
the core distribution layer is 90% or more, when a distance Dt3
from an inner diameter surface of the core via to a surface of an
electrically conductive layer of the core distribution layer is
100% as total, a thickness Tcv2 of an electrically conductive layer
of the core distribution layer is 90% or more, at an opening part
where a larger diameter between the first surface opening part and
the second surface opening part is disposed, when a distance Dt2
from an inner diameter surface of the core via to a surface of an
electrically conductive layer of the core via distribution layer is
100% as total, and an average distance F3 is 1 .mu.m or less,
between one surface of an electrically conductive layer of the core
distribution layer close to an inner diameter surface of the core
via, and the inner diameter surface of the core via, showed
resistance values of 24.1.times.10.sup.-6.OMEGA. to
25.8.times.10.sup.-6.OMEGA., which are good resistance values. It
is considered that a packaging substrate with these characteristics
is possible to sufficiently easily transmit electrical signals to
the element respectively disposed at above or below it.
[0203] A packaging substrate of the embodiment does not form a
parasitic element which a glass substrate has, and with excellent
characteristics such as being capable of serving as a supporting
substrate which is thin and having sufficient strength, it forms an
electrically conductive layer with an appropriate ratio of the
thickness of the glass substrate, and thereby utilizes that
excellent properties such as inducing efficient transmitting of
signals.
[0204] A glass substrate is evaluated to have poor bonding
properties with an electrically conductive layer such as a copper
layer, and in order to form an electrically conductive layer with a
sufficient thickness by a method of plating, etc., a seed layer, a
primer layer or the like is needed to be formed between a glass
surface and an electrically conductive layer. However, when forming
such seed layer or primer layer too thick, it may be difficult to
form an electrically conductive layer enough within the determined
diameter of core via, and it may adversely affect the upper and
lower electrical signal transmission rate of the packaging
substrate.
[0205] Considering these characteristics, and for efficient
electrical signal transmission, it is considered that applying a
thickness of a seed layer or a primer layer as thin as possible
while satisfying specific ratio, the Tcv3/Dt3 ratio and the
Tcv2/Dt2 ratio of 0.90 or more, and F3 of 1.0 .mu.m or less, is
desirable.
[0206] Although the desirable examples of the embodiment have been
described above, the scope of the embodiment is not limited
thereto, and various modifications and alterations made by those
skilled in the art using the basic concept of the embodiment
defined in the following claims also fall within the scope of the
embodiment.
TABLE-US-00002 DESCRIPTION OF FIG. NUMBERS 100: Semiconductor
apparatus 10: Motherboard 30: Semiconductor element unit 32: First
semiconductor element 34: Second semiconductor element 36: Third
semiconductor element 20: Packaging substrate 22: Core layer 223:
Core insulating layer 21, 21a: Glass substrate 213: First surface
214: Second surface 23: Core via 233: First opening part 234:
Second opening part 235: Minimum inner diameter part 24: Core
distribution layer 241: Core distribution pattern 241a: First
surface distribution pattern 241b: Core via distribution pattern
241c: Second surface distribution pattern 26: Upper layer 25: Upper
distribution layer 251: Upper distribution pattern 252: Blind via
253: Upper insulating layer 27: Upper surface connecting layer 271:
Upper surface connecting electrode 272: Upper surface connecting
pattern 29: Lower layer 291: Lower distribution layer 291a: Lower
distribution pattern 291b: Lower insulating layer 292: Lower
surface connecting pattern 292a: Lower surface connecting electrode
292b: Lower surface connecting pattern 50: Connecting part 51:
Element connecting part 52: Board connecting part 60: Cover layer
21b: Glass defect 21c: Seed layer, Primer layer 21d: Core
distribution layer 21e: Etched layer of Core distribution layer
23a: Insulating layer 23b: Etched layer of Insulating layer 23c:
Electrically conductive layer 23d: Etched layer of Electrically
conductive layer 23e: Insulating layer 23f: Etched layer of
Insulating layer 23g: Electrically conductive layer 23h: Etched
layer of Electrically conductive layer
* * * * *