U.S. patent application number 17/569678 was filed with the patent office on 2022-04-28 for semiconductor structure and manufacture method thereof.
The applicant listed for this patent is Silergy Semiconductor Technology (Hangzhou) LTD. Invention is credited to Chuan Peng.
Application Number | 20220130762 17/569678 |
Document ID | / |
Family ID | |
Filed Date | 2022-04-28 |
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United States Patent
Application |
20220130762 |
Kind Code |
A1 |
Peng; Chuan |
April 28, 2022 |
SEMICONDUCTOR STRUCTURE AND MANUFACTURE METHOD THEREOF
Abstract
A method of making a semiconductor structure can include: (i)
forming a plurality of oxide layers on a semiconductor substrate;
(ii) forming a plurality of conductor layers on the plurality of
oxide layers; (iii) forming plurality of thickening layers on the
plurality of conductor layers; (iv) patterning the plurality of
conductor layers and the plurality of thickening layers to form a
hard mask; and (v) implanting ion using the hard mask to form a
plurality of doped regions.
Inventors: |
Peng; Chuan; (Hangzhou,
CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Silergy Semiconductor Technology (Hangzhou) LTD |
Hangzhou |
|
CN |
|
|
Appl. No.: |
17/569678 |
Filed: |
January 6, 2022 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15211036 |
Jul 15, 2016 |
11251130 |
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17569678 |
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International
Class: |
H01L 23/535 20060101
H01L023/535; H01L 29/786 20060101 H01L029/786; H01L 21/28 20060101
H01L021/28 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 16, 2015 |
CN |
201510420281.0 |
Claims
1.-18. (canceled)
19. A method of making a semiconductor structure, the method
comprising: a) forming a first oxide layer on a first region of a
semiconductor substrate and forming a second oxide layer on a
second region of a semiconductor substrate; b) forming a first gate
structure on the first region of the semiconductor substrate, and
forming a second gate structure on the second region of the
semiconductor substrate, wherein the forming the first and second
gate structures comprises forming a polysilicon layer on the first
and second oxide layers, forming a thickening layer on the
polysilicon layer, and patterning the thickening layer to form a
patterned thickening layer located only in the first region, and to
expose the polysilicon layer in the second region using a mask
layer; and c) forming a plurality of doped regions by implanting
ions into the semiconductor substrate using the first gate
structure as a first hard mask on the first region and the second
gate structure as a second hard mask on the second region.
20. The method of claim 19, further comprising: a) etching the
patterned thickening layer in the first region and patterning the
polysilicon layer remaining in the first region to respectively
form an etched thickening layer and a first conductor layer,
wherein the first hard mask comprises the first conductor layer;
and b) patterning the polysilicon layer in the second region to
form a second conductor layer, wherein the second hard mask
comprises the second conductor layer.
21. The method of claim 20, wherein the first conductor layer is
configured as a first gate conductor, and wherein the second
conductor layer is configured as a second gate conductor.
22. The method of claim 20, wherein the etched thickening layer
comprises a metal silicide layer.
23. The method of claim 20, wherein the first conductor layer and
the etched thickening layer form a composite gate conductor.
24. The method of claim 22, wherein the thickening layer further
comprises an antireflection layer on the metal silicide layer.
25. The method of claim 21, wherein the forming the first and
second gate conductors comprises: c) etching the thickening layer
in the second region to expose the polysilicon layer in the second
region; d) etching the polysilicon layer in the second region on a
predetermined portion of the second oxide layer to form the second
gate conductor; and e) etching the thickening layer and the
polysilicon layer in the first region on a predetermined portion of
the first oxide layer to form the first gate conductor.
26. The method of claim 19, further comprising doping a portion of
the polysilicon layer to regulate a work function.
27. The method of claim 20, wherein the second conductor layer and
the second oxide layer combined is thinner than the thickening
layer, the first conductor layer, and the first oxide layer
combined.
28. The method of claim 19, wherein the formation of the first
oxide layer and second oxide layer comprises: a) forming a first
oxide layer of a first thickness on a semiconductor substrate; b)
forming a first region mask to cover a first region of the
semiconductor substrate, and to expose a second region of the
semiconductor substrate; c) etching the first oxide layer on the
second region of the semiconductor substrate; d) removing the first
region mask; and e) employing an oxidation process to grow a second
oxide layer of a second thickness on the second region, resulting
in the thickness of the first oxide layer being increased to a
third thickness, wherein the second thickness is less than the
first thickness.
29. A semiconductor structure, comprising: a) a semiconductor
substrate; b) a first oxide layer and a second oxide layer on the
semiconductor substrate; c) a first semiconductor device in a first
region of the semiconductor substrate, wherein the first
semiconductor device comprises the first oxide layer and a first
gate conductor on the first oxide layer, and wherein the first gate
conductor comprises a conductor layer; and d) a second
semiconductor device in a second region of the semiconductor
substrate, wherein the second semiconductor device comprises the
second oxide layer and a second gate conductor on the second oxide
layer, and wherein the second gate conductor comprises a conductor
layer and a silicide layer.
30. The semiconductor structure of claim 29, wherein the conductor
layer comprises a polysilicon layer, and the silicide layer
comprises a metal silicide layer.
31. The semiconductor structure of claim 29, further comprising an
antireflection layer on the metal silicide layer.
32. The semiconductor structure of claim 29, wherein the first gate
conductor is doped.
33. The semiconductor structure of claim 31, wherein the
antireflection layer comprises an oxide layer.
34. The semiconductor structure of claim 29, wherein the first
semiconductor device comprises first doped regions located in the
semiconductor substrate and at two side of the first gate
conductor, and the second semiconductor device comprises second
doped regions located in the semiconductor substrate and at the
first gate conductor.
35. The semiconductor structure of claim 34, further comprising
shallow trench isolation between the first doped regions and second
doped regions.
Description
RELATED APPLICATIONS
[0001] This application claims the benefit of Chinese Patent
Application No. 201510420281.0, filed on Jul. 16, 2015, which is
incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
[0002] The present invention generally relates to the field of
semiconductor devices and manufacturing methods, and more
particularly to semiconductor structures and associated
manufacturing methods.
BACKGROUND
[0003] The development of semiconductor technology allows for
improvements in integration density and functionality of integrated
dice. Semiconductor devices of different structures and electrical
characteristics can be integrated into one integrated die or
integrated circuit. For example, two different types (e.g., N-type
and P-type) of metal oxide semiconductor effect transistors
(MOSFET) can be formed on a common semiconductor substrate for CMOS
devices. CMOS devices are widely employed in devices today, such as
in logic circuits with low power consumption. Also, control dice of
power converters can be formed by CMOS processes, resulting in
relatively low power losses, higher integration, and faster
speeds.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIGS. 1A-1H are cross-sectional diagrams of a first example
method of making a semiconductor structure that includes gate
oxides of different thicknesses, in accordance with embodiments of
the present invention.
[0005] FIG. 2 is a cross-sectional diagram of an example
semiconductor structure that includes gate oxides of different
thicknesses, in accordance with embodiments of the present
invention.
[0006] FIGS. 3A-3B are cross-sectional diagrams of a second example
method of making a semiconductor structure that includes gate
oxides of different thicknesses, in accordance with embodiments of
the present invention.
[0007] FIGS. 4A-4C are cross-sectional diagrams of a third example
method of making a semiconductor structure including gate oxide of
different thicknesses, in accordance with embodiments of the
present invention.
DETAILED DESCRIPTION
[0008] Reference may now be made in detail to particular
embodiments of the invention, examples of which are illustrated in
the accompanying drawings. While the invention may be described in
conjunction with the preferred embodiments, it may be understood
that they are not intended to limit the invention to these
embodiments. On the contrary, the invention is intended to cover
alternatives, modifications and equivalents that may be included
within the spirit and scope of the invention as defined by the
appended claims. Furthermore, in the following detailed description
of the present invention, numerous specific details are set forth
in order to provide a thorough understanding of the present
invention. However, it may be readily apparent to one skilled in
the art that the present invention may be practiced without these
specific details. In other instances, well-known methods,
procedures, processes, components, structures, and circuits have
not been described in detail so as not to unnecessarily obscure
aspects of the present invention.
[0009] Semiconductor devices are generally manufactured using two
complex manufacturing processes: front-end manufacturing and
back-end manufacturing. Front-end manufacturing may involve the
formation of a plurality of die on the surface of a semiconductor
wafer. Each die on the wafer may contain active and passive
electrical components, which are electrically connected to form
functional electrical circuits. Active electrical components, such
as transistors and diodes, have the ability to control the flow of
electrical current. Passive electrical components, such as
capacitors, inductors, resistors, and transformers, create a
relationship between voltage and current necessary to perform
electrical circuit functions.
[0010] Passive and active components can be formed over the surface
of the semiconductor wafer by a series of process steps including
doping, deposition, photolithography, etching, and planarization.
Doping introduces impurities into the semiconductor material by
techniques such as ion implantation or thermal diffusion. The
doping process modifies the electrical conductivity of
semiconductor material in active devices, transforming the
semiconductor material into an insulator, conductor, or dynamically
changing the semiconductor material conductivity in response to an
electric field or base current. Transistors contain regions of
varying types and degrees of doping arranged as necessary to enable
the transistor to promote or restrict the flow of electrical
current upon the application of the electric field or base
current.
[0011] Active and passive components are formed by layers of
materials with different electrical properties. The layers can be
formed by a variety of deposition techniques determined in part by
the type of material being deposited. For example, thin film
deposition may involve chemical vapor deposition (CVD), physical
vapor deposition (PVD), electrolytic plating, and electroless
plating processes. Each layer is generally patterned to form
portions of active components, passive components, or electrical
connections between components.
[0012] The layers can be patterned using photolithography, which
involves the deposition of light sensitive material, e.g.,
photoresist, over the layer to be patterned. A pattern is
transferred from a photomask to the photoresist using light. The
portion of the photoresist pattern subjected to light is removed
using a solvent, exposing portions of the underlying layer to be
patterned. The remainder of the photoresist may be removed, leaving
behind a patterned layer. Alternatively, some types of materials
can be patterned by directly depositing the material into the areas
or voids formed by a previous deposition/etch process using
techniques such as electroless and electrolytic plating.
[0013] Depositing a thin film of material over an existing pattern
can exaggerate the underlying pattern and create a non-uniformly
flat surface. A uniformly flat surface may be used to produce
smaller and more densely packed active and passive components.
Planarization can be used to remove material from the surface of
the wafer and produce a uniformly flat surface. Planarization can
involve polishing the surface of the wafer with a polishing pad. An
abrasive material and corrosive chemical are added to the surface
of the wafer during polishing. The combined mechanical action of
the abrasive and corrosive action of the chemical removes any
irregular topography, resulting in a uniformly flat surface.
[0014] Back-end manufacturing refers to cutting or singulating the
finished wafer into the individual die and then packaging the die
for structural support and environmental isolation. To singulate
the die, the wafer is scored and broken along non-functional
regions of the wafer called saw streets or scribes. The wafer may
be singulated using a laser cutting tool or saw blade. After
singulation, the individual die are mounted to a package substrate
that includes pins or contact pads for interconnection with other
system components. Contact pads formed over the semiconductor die
can then be connected to contact pads within the package. The
electrical connections can be made with solder bumps, stud bumps,
conductive paste, or wire bonds, as a few examples. An encapsulant
or other molding material may be deposited over the package to
provide physical support and electrical isolation. The finished
package can then be inserted into an electrical system and the
functionality of the semiconductor device is made available to the
other system components.
[0015] Only one type of transistor gate structure may be included
in integrated die due to limitations of typical semiconductor
processes. The gate structure can be a polysilicon gate, or
composite gate formed by silicide layer and polysilicon. For
example, a polysilicon gate with less thickness may be formed by
processes less than 0.25 um, and a composite gate with greater
thicknesses can be formed by processes larger than 0.35 um. A
polysilicon gate may have a reduced line width, and a composite
gate can have lower connection resistance. An integrated die
including both polysilicon and composite gates may thus realize
both advantages. However, it is difficult for processes to form the
two different gates in one integrated die. Because the thickness of
a polysilicon gate is generally lower, the dopant may penetrate the
hard mask when implanting ion if the polysilicon gate is configured
as the hard mask. Therefore, the hard mask may not restrict the
scope of the doped region, which can induce semiconductor device
failure.
[0016] In one embodiment, a method of making a semiconductor
structure can include: (i) forming a plurality of oxide layers on a
semiconductor substrate; (ii) forming a plurality of conductor
layers on the plurality of oxide layers; (iii) forming plurality of
thickening layers on the plurality of conductor layers; (iv)
patterning the plurality of conductor layers and the plurality of
thickening layers to form a hard mask; and (v) implanting ion using
the hard mask to form a plurality of doped regions.
[0017] Referring now to FIGS. 1A-1H, shown are cross-sectional
diagrams of a first example method of making a semiconductor
structure that includes gate oxides of different thicknesses, in
accordance with embodiments of the present invention. In this
particular example, only the steps to form the stacked gate
structure of a semiconductor structure are described, while the
steps to form other parts of the semiconductor structure are
understood. Initially, semiconductor substrate 101 can be formed of
any suitable type(s) of semiconductor materials (e.g., silicon,
germanium, SiGe, SOI, SiC, GaAs, any compound semiconductors of
III/V groups, etc.).
[0018] Oxide layer 102 can be formed on semiconductor substrate 101
by an oxidation process (e.g., chemical oxidation, thermal
oxidation, or the combination of both), as shown in FIG. 1A. For
example, the thickness of oxide layer 102 can be from about 20
.ANG. to about 100 .ANG., such as about 55 .ANG.. In one example,
thermal oxidation can be executed for a time interval from about 20
s to about 120 s at a temperature between about 600.degree. C. and
about 900.degree. C. to form oxide layer 102. In another example,
chemical oxidation can be executed in a water solution including O3
to form oxide layer 102. A photoresist layer can be formed on a
surface of oxide layer 102. The photoresist layer can then be
etched by a lithography process to form mask layer PR1 to cover a
"first" region of semiconductor substrate 101, and to expose a
"second" region of semiconductor substrate 101.
[0019] Through the opening of mask layer PR1, the exposed portion
of oxide layer 102 on semiconductor substrate 101 can be etched by
a wet etching process using an etchant. Due to the selectivity of
the etchant, the etching process may be completed when the surface
of semiconductor substrate 101 is exposed. As such, oxide layer 102
on the first region of semiconductor substrate 101 may remain as
shown in FIG. 1B. After the etching process, mask layer PR1 can be
removed by dissolving in solvent or an ashing process. Oxide layer
103 can be formed on the second region of semiconductor substrate
101, such as by the above oxidation processes, and as shown in FIG.
1C. The thickness of oxide layer 103 can be less than that of oxide
layer 102. For example, the thickness of oxide layer 103 can be
between about 10 .ANG. and about 50 .ANG., such as about 30
.ANG..
[0020] For example, thermal oxidation process can be utilized in
this step. The first region of semiconductor substrate 101 can be
covered by oxide layer 102. When oxide layer 103 is growing by a
thermal oxidation process, oxygen atoms can reach the surface of
semiconductor substrate 101, penetrating oxide layer 102 to oxidize
the surface of semiconductor substrate 101 underneath oxide layer
102. Therefore, oxide layer 102 may again grow in order to increase
its thickness. As the thickness of the oxide layer increases, the
growth speed is reduced, so the growth speed of oxide layer 102 is
less than that of oxide layer 103.
[0021] In one example, when the thickness of oxide layer 102 is
about 55 .ANG. and the thickness of oxide layer 103 is about 30
.ANG., due to the additional growth of oxide layer 102, the
thickness of oxide layer 102 may increase to about 70 .ANG. from
about 55 .ANG.. As shown in FIG. 1D, polysilicon layer 104 can be
formed on oxide layers 102 and 103 by a deposition process (e.g.,
EBM, CVD, ALD, sputtering process, etc.). The thickness of
polysilicon layer 104 can be between about 1000 .ANG. and about
3000 .ANG., such as about 2000 .ANG..
[0022] A metal layer may be formed on polysilicon layer 104, such
as by above deposition processes, which may then be siliconized in
order to generate metal silicide layer 105. For example, metal
silicide layer 105 can be formed by Wsix, the thickness of which
can be between about 1000 .ANG. and about 3000 .ANG., such as about
1500 .ANG.. In one example, a tungsten (W) metal layer with a
thickness between about 5 nm and about 12 nm can be deposited, and
then the W metal layer may be heat treated for a time interval
between about 1 s and about 10 s at temperature of between about
300.degree. C. and about 500.degree. C. Therefore, a chemical
reaction may be carried out between the surface of polysilicon
layer 104 and the W metal, in order to generate Wsix. The remaining
W metal that has not been chemically reacted may be removed by a
wet etching process.
[0023] Antireflection layer 106 can be formed on metal silicide
layer 105, such as by the above deposition processes, as shown in
FIG. 1D. In one example, antireflection layer 106 can be made by an
oxide (e.g., silicon oxide) with a thickness of about 1000 .ANG..
In other examples, antireflection layer 106 may be excluded. In
some cases, the relatively strong light reflectivity of metal
silicide layer 105 may adversely affect the alignment in the
photolithography process. However, the reflection from metal
silicide layer 105 may be decreased when the surface of metal
silicide layer 105 is covered by antireflection layer 106.
[0024] As shown in FIG. 1E, a photoresist layer can be formed on
the surface of antireflection layer 106. Mask layer PR2 can be
formed by etching the photoresist layer by a lithography process.
The first region of semiconductor substrate 101 can be covered by
mask layer PR2, and the second region of semiconductor substrate
may be exposed. In one example, mask layer PR2 may be aligned with
mask layer PR1. Therefore, both of mask layers PR1 and PR2 can be
formed by a same mold. In another example, mask layer PR2 may be
formed using a different mold than that of mask layer PR1. Mask
layer PR2 can cover a portion of the first region, and may expose a
portion of the second region. For example, a compound gate may be
formed in the first region, and a polysilicon gate can be formed in
the second region.
[0025] Through the opening of mask layer PR2, by a wet etching
process using an etchant, the exposed portion of antireflection
layer 106 and the exposed portion of metal silicide layer 105 from
top to bottom can be etched until the surface of polysilicon layer
104 is exposed due to the selectivity of the etchant. As shown in
FIG. 1E, the portion of antireflection layer 106 and metal silicide
layer 105 on the first region of semiconductor substrate 101 can
remain. Mask layer PR2 can be removed by dissolving in solvent or
ashing process.
[0026] A photoresist layer may be formed on the surface of the
semiconductor structure of FIG. 1E. As shown in FIG. 1F, mask layer
PR3 can be formed by etching the photoresist layer by a lithography
process. Only one portion of the second region of semiconductor
substrate 101 can be covered by mask layer PR3, and the remaining
portion of the second region of semiconductor substrate 101 can be
exposed through the openings of mask layer PR3.
[0027] Through the openings of mask layer PR3, a wet etching
process using an etchant may be employed. On the first region of
semiconductor substrate 101, antireflection layer 106 can be
configured as a hard mask. The exposed portion of polysilicon layer
104 can be etched selectively until the surface of oxide layer 103
is exposed due to the selectivity of the etchant. The remaining
portion of polysilicon layer 104 on the second region of
semiconductor substrate 101 may form gate conductor 107, as shown
in FIG. 1F. After the etching process, mask layer PR3 can be
removed by dissolving in solvent or ashing process.
[0028] A photoresist layer can be formed on the top surface of the
semiconductor structure as shown in FIG. 1F. In FIG. 1G, mask layer
PR4 may be formed by etching the photoresist layer to cover a
portion of the second region of semiconductor substrate 101 and
gate conductor 107 on the second region. The remaining portions of
the first and second regions of semiconductor substrate 101 may be
exposed through the openings of mask layer PR4. Through the
openings of mask layer PR4, a wet etching process can occur using
an etchant.
[0029] From top to bottom, the exposed portion of antireflection
layer 106, portion of metal silicide layer 105, and portion of
polysilicon layer 104 can be etched until the surface of oxide
layers 102 and 103 are exposed due to the selectivity of the
etchant. The remaining portion of polysilicon layer 104 on the
first region of semiconductor substrate 101 can be configured as
gate conductor 108, as shown in FIG. 1G. Due to the protection of
mask layer PR4, gate conductor 107 on the second region may remain
during selective removal of polysilicon layer 104 on the first
region. After the etching process, mask layer PR4 can be removed,
such as by dissolving in solvent or ashing process.
[0030] As shown in FIG. 1H, by a regular ion implanting process,
doped regions may be formed in semiconductor substrate 101 to be
configured as body 111 of semiconductor device, and body 112 of
semiconductor device 112. On the first region of semiconductor
substrate 101, antireflection layer 106 together with metal
silicide layer 105 can be configured as a thickening layer. Both
the thickening layer and gate conductor 108 can be configured as a
hard mask layer.
[0031] On the second region of semiconductor substrate 101, gate
conductor 107 can be configured as a hard mask. In some cases,
prior to the ion implanting process, a photoresist mask formed by
etching a photoresist layer can be configured as an additional
mask, in order to limit the scope of the doped region together with
hard mask. The doped regions may be aligned with the hard mask.
Therefore, even though the thickness of gate conductor is smaller,
the thickening layer on the gate conductor can be configured as a
shield together with the conductor layer.
[0032] N-type dopants (e.g., P, As, etc.) can be implanted to form
N-type semiconductor layers or regions, and P-type dopants (e.g.,
B, etc.) can be implanted to form P-type semiconductor layers or
regions. By controlling the ion implantation parameters, such as
implantation energy and dosage, targeted depth and doping
concentrations can be achieved. After the formation of body regions
111 and 112, source and drain regions may be respectively formed in
body regions 111 and 112. When forming source and drain regions,
ions can be implanted given that the above hard mask and additional
etchant resist are configured as a mask to form self-aligned doped
regions.
[0033] In cases when body regions are not utilized, the source and
drain regions of the semiconductor device can be directly formed in
the step as shown in FIG. 1H. Therefore, the doped regions formed
by employing the hard masks can be body regions and/or source and
drain regions. Because the doped depth of body regions is greater
than that of source and drain regions, the ion implantation energy
for body regions may be larger, and dopants can penetrate the oxide
layer more easily. Thus, during the process of ion implantation,
the above hard mask provide an improved shield. In addition, an
insulating interlayer, through-hole conductor penetrating the
insulating interlayer, and connection structure connecting to the
through-hole conductor, may also be included to form the full
structure of the semiconductor device.
[0034] In accordance with the example above, oxide layer 102 can be
on the semiconductor substrate. The portion of the oxide layer 102
on the first region of the semiconductor substrate may remain, and
the portion of oxide layer 102 on the second region of
semiconductor substrate can be removed by etching mask PR1. Then,
oxide layer 103 with a different thickness may be formed on the
second region of the semiconductor substrate. Gate oxides with
different thicknesses on the first and second regions of the
semiconductor substrate may thus be formed by one mask (e.g., PR1)
in order to decrease the number of masks and associated cost of the
semiconductor device.
[0035] In one example, oxide layer 103 can be by thermal growth
process, where oxide layer 102 grows again towards the bottom to
increase its thickness. Due to characteristics of the thermal
growth process, this increased thickness of oxide layer 102 is
greater than that of oxide layer 103. Therefore, a gate oxide with
a greater thickness can be achieved on the first region of the
semiconductor substrate, and a gate oxide with a lesser thickness
is achieved on the second region of the semiconductor
substrate.
[0036] In one example, the antireflection layer can be configured
as an additional hard mask in the gate conductor patterning step to
decrease the amount of masks and alignment accuracy requirement of
the photolithography. A compound gate conductor that includes a
polysilicon layer and metal silicide can be formed in the first
region of the semiconductor structure, and a single layer gate
conductor that includes a polysilicon layer can be formed in the
second region of the semiconductor structure. In other examples,
the gate conductor in the first and second regions of the
semiconductor structure can be same, such as where both are formed
by a polysilicon layer.
[0037] In one example, both the antireflection layer and metal
silicide layer can be configured as a thickening layer to from hard
mask together with the gate conductor in the step of forming doped
region in order to generate the body region of the semiconductor
device. For those examples without the antireflection layer, the
metal silicide layer as thickening layer together with the gate
conductor can be configured as the hard mask. In another
alternative example, a nitride layer (e.g., SiNx) can be directly
formed on the gate conductor configured as thickening layer. In the
step of forming the doped region, the nitride layer and gate
conductor 108 can be configured as hard mask. After forming the
doped region, the thickening layer can be removed, or may remain as
a portion of the semiconductor device.
[0038] In one embodiment, a semiconductor structure can include:
(i) a semiconductor substrate; (ii) a plurality of oxide layers on
the semiconductor substrate; (iii) a first semiconductor device in
a first region of the semiconductor substrate, where the first
semiconductor device comprises a first oxide layer and a first gate
conductor on the first oxide layer, and where the first gate
conductor comprises a conductor layer; and (iv) a second
semiconductor device in a second region of the semiconductor
substrate, where the second semiconductor device comprises a second
oxide layer and a second gate conductor on the second oxide layer,
and where the second gate conductor comprises a conductor layer and
a silicide layer.
[0039] Referring now to FIG. 2, shown is a cross-sectional diagram
of an example semiconductor structure that includes gate oxides of
different thicknesses, in accordance with embodiments of the
present invention. Semiconductor structure 100 can include
semiconductor substrate 101, semiconductor device T1 in the first
region of semiconductor substrate 101, and semiconductor device T2
in the second region of semiconductor substrate 101. Semiconductor
device T1 can include oxide layer 102 in the first region of
semiconductor substrate 101, polysilicon layer 108, metal silicide
layer 105, and antireflection layer 106 stacked in sequence on
oxide layer 102. Semiconductor device T2 can include oxide layer
103 in the second region of semiconductor substrate 101, and
polysilicon layer 107 stacked on second oxide layer 103.
[0040] The thickness of oxide layer 102 may be greater than that of
oxide layer 103. Also, the lateral boundaries of oxide layers 102
and 103 may be overlapped. As shown in FIG. 2, the top surface of
oxide layer 102 can be higher than that of oxide layer 103, and the
bottom surface of oxide layer 102 may not be lower than that of
oxide layer 103. In this particular example, a compound gate
conductor that includes a polysilicon layer and metal silicide may
be formed in the first region of the semiconductor structure, and a
single layer gate conductor that includes a polysilicon layer can
be formed in the second region of the semiconductor structure. In
other examples, the gate conductor in the first and second regions
of the semiconductor structure can be same, such as whereby both
are formed by a polysilicon layer.
[0041] The gate conductor can be formed including stacked layers,
as described above. Also, those skilled in the art will recognize
that before the formation of oxide layer 102, wells of different
dopants can be formed in the semiconductor substrate. The
semiconductor structure can also include an insulating interlayer,
a through-hole conductor penetrating the insulating interlayer, and
a connection structure connecting to the through-hole conductor to
form the complete structure of semiconductor devices T1 and T2.
[0042] Referring now to FIGS. 3A-3B, shown are cross-sectional
diagrams of a second example method of making a semiconductor
structure that includes gate oxides of different thicknesses, in
accordance with embodiments of the present invention. For clarity,
only the steps of forming the gate conductor are described, and the
formation steps of other parts of the semiconductor structure are
omitted here. Thus, the steps of FIGS. 3A and 3B can occur after
the steps of FIGS. 1A-1D. Photoresist may be grown on the surface
of antireflection layer 106, and mask PR5 can be formed by etching
the photoresist by a photolithography process. A portion of a first
region of semiconductor substrate 101 may be covered by mask PR5,
and the remaining portion of the first region and the entire second
region can be exposed. In this example, mask PR5 may be different
from mask PR1.
[0043] Exposed portions of antireflection layer 106 and metal
silicide layer 105 may be etched from top to bottom though the
opening of mask PR5 by a wet etching process using an etchant until
the surface of polysilicon layer 104 is exposed due to the
selectivity of the etchant. As shown in FIG. 3A, antireflection
layer 106 and metal silicide layer 105 in the first region of
semiconductor substrate 101 may remain. After etching, mask PR5 can
be removed by dissolving in a solvent or by an ashing process.
Then, photoresist can grow on the surface of the semiconductor
structure of FIG. 3A, which can be etched by photolithographic to
form mask PR6, as shown in FIG. 3B. A portion of the second region
of semiconductor substrate 101 may be covered by mask PR6, and the
remaining portion of the second region can be exposed through the
opening of mask PR6.
[0044] Antireflection layer 106 can be configured as additional
hard mask. The exposed portion of polysilicon layer 104 may be
removed by a wet etching process using an etchant through the
opening of mask PR6 until the surface of oxide layers 102 and 103
is exposed due to the selectivity of etchant. The remaining portion
of polysilicon layer 104 in the first region of semiconductor
substrate 101 can be configured as gate conductor 107, as shown in
FIG. 3B. After etching, mask PR6 may be removed, such as by
dissolving in a solvent, or by an ashing process.
[0045] The mask formed by the photoresist and antireflection layer
may be configured as a hard mask, and the polysilicon layer can be
patterned to form gate conductors 107 and 108. As compared with the
above examples, the number of masks can be decreased, and the masks
need not be aligned accurately, in order to decrease the
manufacture cost and to improve the reliability and yield rate.
[0046] Referring now to FIGS. 4A-4C, shown are cross-sectional
diagrams of another example method of making a semiconductor
structure including gate oxide of different thicknesses, in
accordance with embodiments of the present invention. For clarity,
only the steps of forming gate conductor may be described here, and
the formation steps of other portions of the semiconductor
structure are omitted.
[0047] Different from the step of FIG. 1A, prior to the formation
of oxide layer 102, shallow trench isolation (STI) 112 may be
formed in semiconductor substrate 101, in order to restrict the
active regions of semiconductor devices T1 and T2. For example,
semiconductor substrate 101 may be etched to form trenches. Then,
insulation material can be filled in the trenches by a deposition
process. Insulation material outside of the trenches can be
removed, such as by a chemical mechanical planarization (CMP)
process, to form STI 112. As shown in FIG. 4A, oxide layer 102 can
be formed on semiconductor substrate 101 by an oxidation process
(e.g., chemical oxidation, thermal oxidation, or a combination of
both).
[0048] Polysilicon layer 104 may be formed on oxide layers 102 and
103, such as by a deposition process, as shown in FIG. 4B.
Photoresist can be formed on the surface of the semiconductor
structure. Mask PR7 can be formed by etching the photoresist by a
photolithography process. The exposed portion of polysilicon layer
104 through the opening of mask PR7 can be configured to form gate
conductors of NMOS devices in the first and second regions.
[0049] As shown in FIG. 4C, an ion implantation process can occur.
Dopants may enter polysilicon layer 104 through the openings of
mask PR7. After the ion implantation process, mask PR7 can be
removed, such as by dissolving in a solvent or by an ashing
process. The threshold voltage of the MOSFET can mainly be
determined by the difference of work functions between the gate
conductor and channel material. For an N-type MOSFET, the work
function can be changed by doping polysilicon layer 104 in order to
regulate the threshold voltage. Because the active regions of the
semiconductor devices T1 and T2 are restricted by STI 112, the
reliability of the semiconductor devices may be improved. In
addition, multiple types of semiconductor devices can be integrated
into a single semiconductor die because the threshold voltage can
be regulated by doping the polysilicon layer.
[0050] The embodiments were chosen and described in order to best
explain the principles of the invention and its practical
applications, to thereby enable others skilled in the art to best
utilize the invention and various embodiments with modifications as
are suited to particular use(s) contemplated. It is intended that
the scope of the invention be defined by the claims appended hereto
and their equivalents.
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