U.S. patent application number 17/559730 was filed with the patent office on 2022-04-14 for methods and apparatus for data enhanced automated model generation.
The applicant listed for this patent is Intel Corporation. Invention is credited to Anahita Bhiwandiwalla, Abhijit Davare, Nilesh Jain, Chaunte W. Lacewell, Juan Pablo Munoz, Eriko Nurvitadhi, Rajesh Poornachandran.
Application Number | 20220114451 17/559730 |
Document ID | / |
Family ID | |
Filed Date | 2022-04-14 |
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United States Patent
Application |
20220114451 |
Kind Code |
A1 |
Lacewell; Chaunte W. ; et
al. |
April 14, 2022 |
METHODS AND APPARATUS FOR DATA ENHANCED AUTOMATED MODEL
GENERATION
Abstract
Methods, apparatus, systems, and articles of manufacture for
data enhanced automated model generation are disclosed. Example
instructions, when executed, cause at least one processor to access
a request to generate a machine learning model to perform a
selected task, generate task knowledge based on a previously
generated machine learning model, create a search space based on
the task knowledge, and generate a machine learning model using
neural architecture search, the neural architecture search
beginning based on the search space.
Inventors: |
Lacewell; Chaunte W.;
(Hillsboro, OR) ; Munoz; Juan Pablo; (Folsom,
CA) ; Poornachandran; Rajesh; (Portland, OR) ;
Jain; Nilesh; (Portland, OR) ; Bhiwandiwalla;
Anahita; (Santa Clara, CA) ; Nurvitadhi; Eriko;
(Hillsboro, OR) ; Davare; Abhijit; (Hillsboro,
OR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Intel Corporation |
Santa Clara |
CA |
US |
|
|
Appl. No.: |
17/559730 |
Filed: |
December 22, 2021 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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63222938 |
Jul 16, 2021 |
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International
Class: |
G06N 3/08 20060101
G06N003/08; G06N 3/063 20060101 G06N003/063; G06N 3/04 20060101
G06N003/04 |
Claims
1. An apparatus for data enhanced automated model generation, the
apparatus comprising: interface circuitry to access a request to
generate a machine learning model; and processor circuitry
including one or more of: at least one of a central processing
unit, a graphic processing unit, or a digital signal processor, the
at least one of the central processing unit, the graphic processing
unit, or the digital signal processor having control circuitry to
control data movement within the processor circuitry, arithmetic
and logic circuitry to perform one or more first operations
corresponding to instructions, and one or more registers to store a
result of the one or more first operations, the instructions in the
apparatus; a Field Programmable Gate Array (FPGA), the FPGA
including logic gate circuitry, a plurality of configurable
interconnections, and storage circuitry, the logic gate circuitry
and interconnections to perform one or more second operations, the
storage circuitry to store a result of the one or more second
operations; or Application Specific Integrate Circuitry (ASIC)
including logic gate circuitry to perform one or more third
operations; the processor circuitry to perform at least one of the
first operations, the second operations, or the third operations to
instantiate: task data orchestration circuitry to generate task
knowledge based on a previously generated machine learning model;
search space management circuitry to create a search space based on
the task knowledge; and neural architecture search circuitry to
generate the machine learning model using neural architecture
search, the neural architecture search circuitry to begin an
architecture search based on the search space.
2. The apparatus of claim 1, wherein the processor circuitry is to,
during generation of the machine learning model, insert a plurality
of anchor points into the machine learning model, the anchor points
to be used for collection of a performance statistic concerning
execution of the machine learning model.
3. The apparatus of claim 2, wherein the performance statistic
includes at least one of power efficiency or energy efficiency.
4. The apparatus of claim 2, wherein the processor circuitry is
further to collect the performance statistic based on the anchor
points.
5. The apparatus of claim 4, wherein, to generate the task
knowledge, the processor circuitry is further to rank features of
the previously generated machine learning model.
6. The apparatus of claim 1, wherein to create the search space,
the processor circuitry is to select a prior architecture based on
performance of the prior architecture on a selected hardware.
7. At least one non-transitory computer readable storage medium
comprising instructions that, when executed, cause at least one
processor to at least: access a request to generate a machine
learning model to perform a selected task; generate task knowledge
based on a previously generated machine learning model; create a
search space based on the task knowledge; and generate a machine
learning model using neural architecture search, the neural
architecture search beginning based on the search space.
8. The at least one non-transitory computer readable storage medium
of claim 7, wherein the instructions, when executed, further cause
the at least one processor to insert a plurality of anchor points
into the machine learning model, the anchor points to be used when
collecting a performance statistic concerning execution of the
machine learning model.
9. The at least one non-transitory computer readable storage medium
of claim 8, wherein the instructions, when executed, further cause
the at least one processor to collect the performance statistic
based on the anchor points.
10. The at least one non-transitory computer readable storage
medium of claim 9, wherein the instructions, when executed, further
cause the at least one processor to rank features of the previously
generated machine learning model to generate the task
knowledge.
11. The at least one non-transitory computer readable storage
medium of claim 7, wherein the instructions, when executed, further
cause the at least one processor select a prior architecture based
on performance of the prior architecture on a selected hardware to
create the search space.
12. A method for data enhanced automated model generation, the
method comprising: accessing a request to generate a machine
learning model to perform a selected task; generating task
knowledge based on a previously generated machine learning model;
creating a search space based on the task knowledge; and generating
a machine learning model using neural architecture search, the
neural architecture search beginning based on the search space.
13. The method of claim 12, further including, during generation of
the machine learning model, inserting a plurality of anchor points
into the machine learning model, the anchor points to be used when
collecting a performance statistic concerning execution of the
machine learning model.
14. The method of claim 13, further including collecting the
performance statistic based on the anchor points.
15. The method of claim 14, wherein the generation of the task
knowledge includes ranking features of the previously generated
machine learning model.
16. The method of claim 12, wherein the creation of the search
space includes selecting a prior architecture based on performance
of the prior architecture on a selected hardware.
17. An apparatus for data enhanced automated model generation, the
apparatus comprising: means for accessing a request to generate a
machine learning model to perform a selected task; means for
generating task knowledge based on a previously generated machine
learning model; means for creating a search space based on the task
knowledge; and means for generating a machine learning model using
neural architecture search, the neural architecture search
beginning based on the search space.
18. The apparatus of claim 17, further means for inserting, during
generation of the machine learning model, a plurality of anchor
points into the machine learning model, the anchor points to be
used when collecting a performance statistic concerning execution
of the machine learning model.
19. The apparatus of claim 18, further including means for
collecting the performance statistic based on the anchor
points.
20. The apparatus of claim 19, wherein the means for generating is
further to rank features of the previously generated machine
learning model.
21. The apparatus of claim 17, wherein the means for creating is to
select a prior architecture based on performance of the prior
architecture on a selected hardware.
Description
RELATED APPLICATIONS
[0001] This application claims priority to U.S. Provisional Patent
Application No. 63/222,938, which was filed on Jul. 16, 2021. U.S.
Provisional Patent Application No. 63/222,938 is hereby
incorporated by reference in its entirety.
FIELD OF THE DISCLOSURE
[0002] This disclosure relates generally to machine learning and,
more particularly, to methods and apparatus for data enhanced
automated model generation.
BACKGROUND
[0003] Machine learning is an important enabling technology for the
revolution currently underway in artificial intelligence, driving
truly remarkable advances in fields such as object detection, image
classification, speech recognition, natural language processing,
and many more. Models are created using machine learning that, when
utilized, enable an output to be generated based on an input.
Neural architecture search enables various architectures to be
searched when creating a machine learning model.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 is a block diagram of an example system implemented
in accordance with the teachings of this disclosure for data
enhanced automated model generation.
[0005] FIG. 2 is a block diagram of an example process flow
utilizing the example system of FIG. 1.
[0006] FIG. 3 is a flowchart representative of example machine
readable instructions and/or example operations that may be
executed by example processor circuitry to implement the example
knowledge builder circuitry and the example model builder circuitry
of FIG. 1.
[0007] FIG. 4 is a flowchart representative of example machine
readable instructions and/or example operations that may be
executed by example processor circuitry to implement the example
target hardware of FIG. 1.
[0008] FIG. 5 is a block diagram of an example processing platform
including processor circuitry structured to execute the example
machine readable instructions and/or the example operations of FIG.
3 to implement the example knowledge builder circuitry and the
example model builder circuitry of FIG. 2.
[0009] FIG. 6 is a block diagram of an example implementation of
the processor circuitry of FIG. 4.
[0010] FIG. 7 is a block diagram of another example implementation
of the processor circuitry of FIG. 4.
[0011] FIG. 8 is a block diagram of an example software
distribution platform (e.g., one or more servers) to distribute
software (e.g., software corresponding to the example machine
readable instructions of FIGS. 3 and/or 4) to client devices
associated with end users and/or consumers (e.g., for license,
sale, and/or use), retailers (e.g., for sale, re-sale, license,
and/or sub-license), and/or original equipment manufacturers (OEMs)
(e.g., for inclusion in products to be distributed to, for example,
retailers and/or to other end users such as direct buy
customers).
[0012] In general, the same reference numbers will be used
throughout the drawing(s) and accompanying written description to
refer to the same or like parts. The figures are not to scale.
[0013] As used in this patent, stating that any part (e.g., a
layer, film, area, region, or plate) is in any way on (e.g.,
positioned on, located on, disposed on, or formed on, etc.) another
part, indicates that the referenced part is either in contact with
the other part, or that the referenced part is above the other part
with one or more intermediate part(s) located therebetween.
[0014] Unless specifically stated otherwise, descriptors such as
"first," "second," "third," etc., are used herein without imputing
or otherwise indicating any meaning of priority, physical order,
arrangement in a list, and/or ordering in any way, but are merely
used as labels and/or arbitrary names to distinguish elements for
ease of understanding the disclosed examples. In some examples, the
descriptor "first" may be used to refer to an element in the
detailed description, while the same element may be referred to in
a claim with a different descriptor such as "second" or "third." In
such instances, it should be understood that such descriptors are
used merely for identifying those elements distinctly that might,
for example, otherwise share a same name.
[0015] As used herein "substantially real time" refers to
occurrence in a near instantaneous manner recognizing there may be
real world delays for computing time, transmission, etc. Thus,
unless otherwise specified, "substantially real time" refers to
real time+/-1 second.
[0016] As used herein, the phrase "in communication," including
variations thereof, encompasses direct communication and/or
indirect communication through one or more intermediary components,
and does not require direct physical (e.g., wired) communication
and/or constant communication, but rather additionally includes
selective communication at periodic intervals, scheduled intervals,
aperiodic intervals, and/or one-time events.
[0017] As used herein, "processor circuitry" is defined to include
(i) one or more special purpose electrical circuits structured to
perform specific operation(s) and including one or more
semiconductor-based logic devices (e.g., electrical hardware
implemented by one or more transistors), and/or (ii) one or more
general purpose semiconductor-based electrical circuits programmed
with instructions to perform specific operations and including one
or more semiconductor-based logic devices (e.g., electrical
hardware implemented by one or more transistors). Examples of
processor circuitry include programmed microprocessors, Field
Programmable Gate Arrays (FPGAs) that may instantiate instructions,
Central Processor Units (CPUs), Graphics Processor Units (GPUs),
Digital Signal Processors (DSPs), XPUs, or microcontrollers and
integrated circuits such as Application Specific Integrated
Circuits (ASICs). For example, an XPU may be implemented by a
heterogeneous computing system including multiple types of
processor circuitry (e.g., one or more FPGAs, one or more CPUs, one
or more GPUs, one or more DSPs, etc., and/or a combination thereof)
and application programming interface(s) (API(s)) that may assign
computing task(s) to whichever one(s) of the multiple types of the
processing circuitry is/are best suited to execute the computing
task(s).
DETAILED DESCRIPTION
[0018] Neural Architecture Search (NAS) is an approach for
exploring different machine learning algorithms for solving machine
learning tasks. NAS algorithms take significant amount resources
(e.g., compute resources, temporal resources, energy resources,
etc.) to identify acceptable architectures. Most of these resources
are expended by examining non-optimal architecture configurations
during an exploration stage. Existing NAS algorithms do not provide
clear explanations of the decisions for selecting a particular
architecture, and such algorithms do not benefit from collected
data regarding previous findings (e.g., sequence of operations,
FLOPs, etc.) or target hardware capabilities. This information is
typically discarded and does not benefit future applications of the
NAS algorithm.
[0019] Due to the complexity of the task, NAS solutions tend to
forget any insights from one run to the next. The initial
conditions/configurations in previous solutions are independent of
any other configurations used previously.
[0020] Existing NAS approaches do not reuse prior execution data
related to models identified via NAS. That is, existing approaches
do not benefit from collected knowledge about the task that the
model will perform (e.g., detection, segmentation, etc.). When
performing NAS, existing approaches start from scratch every time,
when looking for better models. Many existing NAS approaches also
require significant reconfiguration when moving to different tasks,
and such approaches do not generalize the neural network
architecture search process.
[0021] Example approaches disclosed herein analyze state-of-the-art
and emerging workloads and collect historical information about the
models including performance, sequence of operations, size,
floating point operations per second (FLOPS), etc. for each
operation.
[0022] In examples disclosed herein, a user provides a task (object
recognition, segmentation, etc.) and objective (accuracy, latency,
mix, etc.), and the NAS system selects starting
hyperparameters/configuration information which include the best
configuration for the task, objective, and, in some examples, the
target hardware on which the model is to be executed.
[0023] Collected execution and/or performance information provides
insights and guides the initial conditions on the search for an
architecture that satisfies the requirements. The system also
collects target hardware information, making the system
hardware-aware and allowing the system to refine for the specific
target hardware(s). For example, the system can avoid dilated
7.times.7 convolution kernels if kernel does not perform well
(e.g., latency on the selected target hardware exceeds a threshold
amount of latency).
[0024] Example approaches disclosed herein provide the user with
the generated model and the reasoning behind the choices made when
selecting operations. The decisions are based on the collected
historical data and the task knowledge obtained from the knowledge
builder (KB). Providing the reasoning for decisions can result in
insights for future HW improvements (e.g., optimize specific
kernels, memory BW, etc.)
[0025] FIG. 1 is a block diagram of an example system implemented
in accordance with the teachings of this disclosure for data
enhanced automated model generation. The example system 100 of FIG.
1 includes knowledge builder circuitry 105 that receives a user
input 110, and model builder circuitry 115 that builds and provides
a model to target hardware 120.
[0026] The example system of FIG. 1 presents an end-to-end solution
that receives information from the user (objective, task, target
HW), analyzes this information using a knowledge base and builds
suggestions for the search space and initial configuration for the
NAS approach. The approach is agnostic to the NAS approach to be
used, enabling a user to decide on the state-of-the-art approach
that will receive the suggested configuration.
[0027] The example user input 110 includes information including,
for example, an objective of a machine learning model, a task to be
performed by the machine learning model, and, optionally, one or
more characteristics of a target hardware on which the machine
learning model is to be executed. The task (object recognition,
segmentation, etc.) will include input layer requirements, output
layer requirements, and data requirements. The system of FIG. 1 is
flexible enough that the user can provide information used to
influence the model generation (e.g., by specifying whether the
current task is similar to another task, and/or by specifying
additional layers (not yet in the knowledge base, or associated
with a different task) to include in the search space).
[0028] The knowledge builder circuitry 105 of FIG. 1 may be
instantiated (e.g., creating an instance of, bring into being for
any length of time, materialize, implement, etc.) by processor
circuitry such as a central processing unit executing instructions.
Additionally or alternatively, the knowledge builder circuitry 105
of FIG. 1 may be instantiated (e.g., creating an instance of, bring
into being for any length of time, materialize, implement, etc.) by
an ASIC or an FPGA structured to perform operations corresponding
to the instructions. It should be understood that some or all of
the circuitry of FIG. 1 may, thus, be instantiated at the same or
different times (and/or by different hardware circuitry). Some or
all of the circuitry may be instantiated, for example, in one or
more threads executing concurrently on hardware and/or in series on
hardware. Moreover, in some examples, some or all of the circuitry
of FIG. 1 may be implemented by one or more virtual machines and/or
containers executing on the microprocessor.
[0029] The example knowledge builder circuitry 105 of the
illustrated example of FIG. 1 includes request accessor circuitry
130, hardware data orchestration circuitry 135, task data
orchestration circuitry 140, and a knowledge datastore 145. The
example knowledge builder circuitry 105 archives information for
models and hardware into the knowledge datastore 145. If the
hardware is not known in the knowledge datastore 145, the user is
able to cause the system to execute on the target hardware 120 to
extract performance metrics. A report of such performance metrics
is obtained and added to the knowledge datastore 145 to build task
knowledge. If the task is not in the knowledge datastore 145, the
task data orchestration circuitry 140 creates task knowledge for
the new tasks. FIG. 2 illustrates the process for creating or
updating the knowledge datastore 145.
[0030] In examples disclosed herein, the knowledge datastore 145 of
the knowledge builder circuitry 105 can be pre-populated with
state-of-the-art (SOTA) or custom models and hardware
configurations. In addition, the knowledge datastore 145 can be
updated at any time based on, for example, statistics collected by
the target hardware 120. In examples disclosed herein, the
knowledge datastore 145 separates the models by tasks. To build the
task knowledge, model information is retrieved from the knowledge
datastore 145 the specific task and features are extracted from the
models. In cases of a new or custom task, similar tasks/models are
retrieved based on the user input. These features include, but are
not limited to, the framework used to train the model, the HW specs
and any information for mapping model (latencies, etc.) including
HW telemetry, the performance objective, sequence of operations,
number of FLOPs, dataset used, number of layers, etc. These
features are then ranked by hardware features, objective, etc. The
extracted and ranked features are then considered task knowledge
which is then archived in the knowledge datastore 145 for future
use.
[0031] The example request accessor circuitry 130 of the
illustrated example of FIG. 1 receives a request for generation of
a model to perform a selected task. In examples disclosed herein,
the user input 110 received by the request accessor circuitry 130
includes information including, for example, an objective of a
machine learning model, a task to be performed by the machine
learning model, and, in some examples, one or more characteristics
of a target hardware on which the machine learning model is to be
executed. The request may be formatted as, for example, a request
received at a web server, a request formatted in a structured data
format (e.g., a JavaScript object notation (JSON) format, an
extensible markup language (XML) format, etc.). The example request
accessor circuitry 130 accesses hardware data orchestration
information via the hardware data orchestration circuitry 135 and
task data orchestration information via the task data orchestration
circuitry 140. The accessed information (if available) and the
request are provided to the search space management circuitry 160
of the model builder circuitry 115.
[0032] In some examples, the apparatus includes means for accessing
a request. For example, the means for accessing may be implemented
by the request accessor circuitry 130. In some examples, the
request accessor circuitry 130 may be instantiated by processor
circuitry such as the example processor circuitry 512 of FIG. 5.
For instance, the request accessor circuitry 130 may be
instantiated by the example general purpose processor circuitry 600
of FIG. 6 executing machine executable instructions such as that
implemented by at least block 310 of FIG. 3. In some examples, the
request accessor circuitry 130 may be instantiated by hardware
logic circuitry, which may be implemented by an ASIC or the FPGA
circuitry 700 of FIG. 7 structured to perform operations
corresponding to the machine readable instructions. Additionally or
alternatively, the request accessor circuitry 130 may be
instantiated by any other combination of hardware, software, and/or
firmware. For example, the request accessor circuitry 130 may be
implemented by at least one or more hardware circuits (e.g.,
processor circuitry, discrete and/or integrated analog and/or
digital circuitry, an FPGA, an Application Specific Integrated
Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a
logic circuit, etc.) structured to execute some or all of the
machine readable instructions and/or to perform some or all of the
operations corresponding to the machine readable instructions
without executing software or firmware, but other structures are
likewise appropriate.
[0033] The example hardware data orchestration circuitry 135 of the
illustrated example of FIG. 1 determines whether any prior
knowledge is present in the knowledge datastore 145 for the
selected hardware (e.g., the selected hardware identified in a
request accessed by the request accessor circuitry 130). If no
prior knowledge is known for the selected hardware, the example
hardware data orchestration circuitry 135 adds an identification of
the selected hardware to the knowledge datastore 145. The
identification of the hardware enables subsequent performance
metrics associated with the selected hardware to be stored in the
knowledge datastore 145 in an organized fashion. In some examples,
the identification of the selected hardware may be omitted prior to
model creation and may, instead, be performed when performance
metrics are provided to the knowledge datastore by the execution
performance statistic collection circuitry 185.
[0034] The example task data orchestration circuitry 140 of the
illustrated example of FIG. 1 determines whether any task
information is available for the selected task. If no prior
knowledge is available for the selected task, the example task data
orchestration circuitry 140 adds an identification of the selected
task to the knowledge datastore 145. The identification of the
selected task enables subsequent performance metrics associated
with the selected task to be stored in the knowledge datastore 145
in an organized fashion. In some examples, the identification of
the selected task may be omitted prior to model creation and may,
instead, be performed when performance metrics are provided to the
knowledge datastore by the execution performance statistic
collection circuitry 185.
[0035] In some examples, the apparatus includes means for
generating task knowledge. For example, the means for generating
task knowledge may be implemented by the example task data
orchestration circuitry 140. In some examples, the example task
data orchestration circuitry 140 may be instantiated by processor
circuitry such as the example processor circuitry 512 of FIG. 5.
For instance, the example task data orchestration circuitry 140 may
be instantiated by the example general purpose processor circuitry
600 of FIG. 6 executing machine executable instructions such as
that implemented by at least blocks 320, 335, 325 of FIG. 3. In
some examples, the example task data orchestration circuitry 140
may be instantiated by hardware logic circuitry, which may be
implemented by an ASIC or the FPGA circuitry 700 of FIG. 7
structured to perform operations corresponding to the machine
readable instructions. Additionally or alternatively, the example
task data orchestration circuitry 140 may be instantiated by any
other combination of hardware, software, and/or firmware. For
example, the example task data orchestration circuitry 140 may be
implemented by at least one or more hardware circuits (e.g.,
processor circuitry, discrete and/or integrated analog and/or
digital circuitry, an FPGA, an Application Specific Integrated
Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a
logic circuit, etc.) structured to execute some or all of the
machine readable instructions and/or to perform some or all of the
operations corresponding to the machine readable instructions
without executing software or firmware, but other structures are
likewise appropriate.
[0036] The example knowledge datastore 145 of the illustrated
example of FIG. 1 is implemented by any memory, storage device
and/or storage disc for storing data such as, for example, flash
memory, magnetic media, optical media, solid state memory, hard
drive(s), thumb drive(s), etc. Furthermore, the data stored in the
example knowledge datastore 145 may be in any data format such as,
for example, binary data, comma delimited data, tab delimited data,
structured query language (SQL) structures, etc. While, in the
illustrated example, the knowledge datastore 145 is illustrated as
a single device, the example knowledge datastore 145 and/or any
other data storage devices described herein may be implemented by
any number and/or type(s) of memories. In the illustrated example
of FIG. 1, the example knowledge datastore 145 stores hardware
and/or task knowledge.
[0037] The model builder circuitry 115 of FIG. 1 may be
instantiated (e.g., creating an instance of, bring into being for
any length of time, materialize, implement, etc.) by processor
circuitry such as a central processing unit executing instructions.
Additionally or alternatively, the model builder circuitry 115 of
FIG. 1 may be instantiated (e.g., creating an instance of, bring
into being for any length of time, materialize, implement, etc.) by
an ASIC or an FPGA structured to perform operations corresponding
to the instructions. As noted above, it should be understood that
some or all of the circuitry of FIG. 1 may, thus, be instantiated
at the same or different times (and/or by different hardware
circuitry). Some or all of the circuitry may be instantiated, for
example, in one or more threads executing concurrently on hardware
and/or in series on hardware. Moreover, in some examples, some or
all of the circuitry of FIG. 1 may be implemented by one or more
virtual machines and/or containers executing on the
microprocessor.
[0038] The example model builder circuitry 115 of the illustrated
example of FIG. 1 includes search space management circuitry 160,
anchor point inserter circuitry 165, neural architecture search
circuitry 170, and model outputter circuitry 175. The model builder
circuitry 115 is responsible for extracting the insights in the
knowledge datastore and executing neural architecture search to
identify an optimal model. First, the example search space
management circuitry 160 creates a search space. This search space
includes the operations provided by the task knowledge from the
knowledge datastore, variants of those operations, and additional
layers if the user specifies. The neural architecture search
circuitry 170 performs a search that is initiated with the
configuration identified by the search space management circuitry
160 for the objective, task, HW, etc. Anchor points are inserted in
the chosen NAS algorithm by the anchor point inserter circuitry 165
to capture the decisions made during this process. The task
knowledge is incorporated in the training loop of the neural
architecture search circuitry 170 to inform decisions and guide the
search. During training, historical decisions, confidence levels,
and the knowledge datastore-based recommendations obtained from the
task knowledge are used to guide the neural architecture
search.
[0039] In some examples, the apparatus includes means for creating
a search space. For example, the means for creating may be
implemented by the example search space management circuitry 160.
In some examples, the example search space management circuitry 160
may be instantiated by processor circuitry such as the example
processor circuitry 512 of FIG. 5. For instance, the example search
space management circuitry 160 may be instantiated by the example
general purpose processor circuitry 500 of FIG. 5 executing machine
executable instructions such as that implemented by at least blocks
327, 340 of FIG. 3. In some examples, the example search space
management circuitry 160 may be instantiated by hardware logic
circuitry, which may be implemented by an ASIC or the FPGA
circuitry 700 of FIG. 7 structured to perform operations
corresponding to the machine readable instructions. Additionally or
alternatively, the example search space management circuitry 160
may be instantiated by any other combination of hardware, software,
and/or firmware. For example, the example search space management
circuitry 160 may be implemented by at least one or more hardware
circuits (e.g., processor circuitry, discrete and/or integrated
analog and/or digital circuitry, an FPGA, an Application Specific
Integrated Circuit (ASIC), a comparator, an operational-amplifier
(op-amp), a logic circuit, etc.) structured to execute some or all
of the machine readable instructions and/or to perform some or all
of the operations corresponding to the machine readable
instructions without executing software or firmware, but other
structures are likewise appropriate.
[0040] In some examples, the apparatus includes means for
generating a machine learning model. For example, the means for
generating may be implemented by the example neural architecture
search circuitry 170. In some examples, the example neural
architecture search circuitry 170 may be instantiated by processor
circuitry such as the example processor circuitry 512 of FIG. 5.
For instance, the example neural architecture search circuitry 170
may be instantiated by the example general purpose processor
circuitry 600 of FIG. 6 executing machine executable instructions
such as that implemented by at least blocks 330, 350 of FIG. 3. In
some examples, the example neural architecture search circuitry 170
may be instantiated by hardware logic circuitry, which may be
implemented by an ASIC or the FPGA circuitry 700 of FIG. 7
structured to perform operations corresponding to the machine
readable instructions. Additionally or alternatively, the example
neural architecture search circuitry 170 may be instantiated by any
other combination of hardware, software, and/or firmware. For
example, the example neural architecture search circuitry 170 may
be implemented by at least one or more hardware circuits (e.g.,
processor circuitry, discrete and/or integrated analog and/or
digital circuitry, an FPGA, an Application Specific Integrated
Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a
logic circuit, etc.) structured to execute some or all of the
machine readable instructions and/or to perform some or all of the
operations corresponding to the machine readable instructions
without executing software or firmware, but other structures are
likewise appropriate.
[0041] In some examples, the apparatus includes means for
inserting. For example, the means for inserting may be implemented
by the example anchor point inserter circuitry 165. In some
examples, the example anchor point inserter circuitry 165 may be
instantiated by processor circuitry such as the example processor
circuitry 512 of FIG. 5. For instance, the example anchor point
inserter circuitry 165 may be instantiated by the example general
purpose processor circuitry 600 of FIG. 6 executing machine
executable instructions such as that implemented by at least block
360 of FIG. 3. In some examples, the example anchor point inserter
circuitry 165 may be instantiated by hardware logic circuitry,
which may be implemented by an ASIC or the FPGA circuitry 700 of
FIG. 7 structured to perform operations corresponding to the
machine readable instructions. Additionally or alternatively, the
example anchor point inserter circuitry 165 may be instantiated by
any other combination of hardware, software, and/or firmware. For
example, the example anchor point inserter circuitry 165 may be
implemented by at least one or more hardware circuits (e.g.,
processor circuitry, discrete and/or integrated analog and/or
digital circuitry, an FPGA, an Application Specific Integrated
Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a
logic circuit, etc.) structured to execute some or all of the
machine readable instructions and/or to perform some or all of the
operations corresponding to the machine readable instructions
without executing software or firmware, but other structures are
likewise appropriate.
[0042] After generation of the model, the example model outputter
circuitry 175 provides a model for execution. In some examples, the
decisions and/or rationales selected during the neural architecture
search are made available in association with the generated
model.
[0043] The target hardware 120 of FIG. 1 may be instantiated (e.g.,
creating an instance of, bring into being for any length of time,
materialize, implement, etc.) by processor circuitry such as a
central processing unit executing instructions. Additionally or
alternatively, the target hardware 120 of FIG. 1 may be
instantiated (e.g., creating an instance of, bring into being for
any length of time, materialize, implement, etc.) by an ASIC or an
FPGA structured to perform operations corresponding to the
instructions. As noted above, it should be understood that some or
all of the circuitry of FIG. 1 may, thus, be instantiated at the
same or different times (and/or by different hardware circuitry).
Some or all of the circuitry may be instantiated, for example, in
one or more threads executing concurrently on hardware and/or in
series on hardware. Moreover, in some examples, some or all of the
circuitry of FIG. 1 may be implemented by one or more virtual
machines and/or containers executing on the microprocessor.
[0044] The example target hardware 120 of the illustrated example
of FIG. 1 includes model execution circuitry 180 and execution
performance statistic collection circuitry 185. The example model
execution circuitry 180 of the illustrated example of FIG. 1
executes the model provided by the model outputter circuitry
175.
[0045] The example execution performance statistic collection
circuitry 185 of the illustrated example of FIG. 1, during
execution of the model by the model execution circuitry 180,
collects model execution statistics using the inserted anchor
points. The collected execution statistics are provided to the
knowledge datastore 145. In examples disclosed herein, the
collected execution statistics include information about the anchor
points. Including information about the anchor points enables
statistics specific to particular features to be utilized when
generating task knowledge.
[0046] FIG. 2 is a block diagram of an example process flow
utilizing the example system of FIG. 1. The example process begins
when a user submits a request for generation of a model to perform
a selected task. (Blocks 210). The requested model is generated
using neural architecture search and prior knowledge of models
associated with the selected task. (Block 220). The generated
models are provided to the target hardware for execution and
collection of performance statistics. (Blocks 230). Execution
features are extracted from the models. (Block 240). The extracted
features are ranked based on collected performance metrics. (Block
250). The extracted features and their associated performance
metrics are added to the knowledge datastore 145. (Block 260). This
added knowledge may then subsequently be used for future generation
of models. (Block 220).
[0047] While an example manner of implementing the example
knowledge builder circuitry 105 and/or the example model builder
circuitry 115 is illustrated in FIG. 1, one or more of the
elements, processes, and/or devices illustrated in FIG. 1 may be
combined, divided, re-arranged, omitted, eliminated, and/or
implemented in any other way. Further, the example request accessor
circuitry 130, the example hardware data orchestration circuitry
135, the example task data orchestration circuitry 140, and/or
more, generally, example knowledge builder circuitry 105 of FIG. 1,
and/or the example search space management circuitry 160, the
example anchor point inserter circuitry 165, the example neural
architecture search circuitry 170, the example model outputter
circuitry 175, and/or, more generally, the example model builder
circuitry 115 of FIG. 1, may be implemented by hardware alone or by
hardware in combination with software and/or firmware. Thus, for
example, any of the example request accessor circuitry 130, the
example hardware data orchestration circuitry 135, the example task
data orchestration circuitry 140, and/or more, generally, example
knowledge builder circuitry 105 of FIG. 1, and/or the example
search space management circuitry 160, the example anchor point
inserter circuitry 165, the example neural architecture search
circuitry 170, the example model outputter circuitry 175, and/or,
more generally, the example model builder circuitry 115 of FIG. 1,
could be implemented by processor circuitry, analog circuit(s),
digital circuit(s), logic circuit(s), programmable processor(s),
programmable microcontroller(s), graphics processing unit(s)
(GPU(s)), digital signal processor(s) (DSP(s)), application
specific integrated circuit(s) (ASIC(s)), programmable logic
device(s) (PLD(s)), and/or field programmable logic device(s)
(FPLD(s)) such as Field Programmable Gate Arrays (FPGAs). Further
still, the example request accessor circuitry 130, the example
hardware data orchestration circuitry 135, the example task data
orchestration circuitry 140, and/or more, generally, example
knowledge builder circuitry 105 of FIG. 1, and/or the example
search space management circuitry 160, the example anchor point
inserter circuitry 165, the example neural architecture search
circuitry 170, the example model outputter circuitry 175, and/or,
more generally, the example model builder circuitry 115 of FIG. 1
may include one or more elements, processes, and/or devices in
addition to, or instead of, those illustrated in FIG. 1, and/or may
include more than one of any or all of the illustrated elements,
processes and devices.
[0048] A flowchart representative of example hardware logic
circuitry, machine readable instructions, hardware implemented
state machines, and/or any combination thereof for implementing the
knowledge builder circuitry 105 and/or the example model builder
circuitry 115 of FIG. 1 is shown in FIG. 3. The machine readable
instructions may be one or more executable programs or portion(s)
of an executable program for execution by processor circuitry, such
as the processor circuitry 512 shown in the example processor
platform 500 discussed below in connection with FIG. 5 and/or the
example processor circuitry discussed below in connection with
FIGS. 5 and/or 6.
[0049] A flowchart representative of example hardware logic
circuitry, machine readable instructions, hardware implemented
state machines, and/or any combination thereof for implementing the
target hardware 120 of FIG. 1 is shown in FIG. 4. The machine
readable instructions may be one or more executable programs or
portion(s) of an executable program for execution by processor
circuitry, such as the processor circuitry 512 shown in the example
processor platform 500 discussed below in connection with FIG. 5
and/or the example processor circuitry discussed below in
connection with FIGS. 5 and/or 6.
[0050] The programs of FIGS. 3 and/or 4 may be embodied in software
stored on one or more non-transitory computer readable storage
media such as a compact disk (CD), a floppy disk, a hard disk drive
(HDD), a solid-state drive (SSD), a digital versatile disk (DVD), a
Blu-ray disk, a volatile memory (e.g., Random Access Memory (RAM)
of any type, etc.), or a non-volatile memory (e.g., electrically
erasable programmable read-only memory (EEPROM), FLASH memory, an
HDD, an SSD, etc.) associated with processor circuitry located in
one or more hardware devices, but the entire program and/or parts
thereof could alternatively be executed by one or more hardware
devices other than the processor circuitry and/or embodied in
firmware or dedicated hardware. The machine readable instructions
may be distributed across multiple hardware devices and/or executed
by two or more hardware devices (e.g., a server and a client
hardware device). For example, the client hardware device may be
implemented by an endpoint client hardware device (e.g., a hardware
device associated with a user) or an intermediate client hardware
device (e.g., a radio access network (RAN)) gateway that may
facilitate communication between a server and an endpoint client
hardware device). Similarly, the non-transitory computer readable
storage media may include one or more mediums located in one or
more hardware devices. Further, although the example program is
described with reference to the flowchart illustrated in FIG. 3,
many other methods of implementing the example knowledge builder
circuitry 105 and/or the example model builder circuitry 115 may
alternatively be used. For example, the order of execution of the
blocks may be changed, and/or some of the blocks described may be
changed, eliminated, or combined. Additionally or alternatively,
any or all of the blocks may be implemented by one or more hardware
circuits (e.g., processor circuitry, discrete and/or integrated
analog and/or digital circuitry, an FPGA, an ASIC, a comparator, an
operational-amplifier (op-amp), a logic circuit, etc.) structured
to perform the corresponding operation without executing software
or firmware. The processor circuitry may be distributed in
different network locations and/or local to one or more hardware
devices (e.g., a single-core processor (e.g., a single core central
processor unit (CPU)), a multi-core processor (e.g., a multi-core
CPU), etc.) in a single machine, multiple processors distributed
across multiple servers of a server rack, multiple processors
distributed across one or more server racks, a CPU and/or a FPGA
located in the same package (e.g., the same integrated circuit (IC)
package or in two or more separate housings, etc.).
[0051] The machine readable instructions described herein may be
stored in one or more of a compressed format, an encrypted format,
a fragmented format, a compiled format, an executable format, a
packaged format, etc. Machine readable instructions as described
herein may be stored as data or a data structure (e.g., as portions
of instructions, code, representations of code, etc.) that may be
utilized to create, manufacture, and/or produce machine executable
instructions. For example, the machine readable instructions may be
fragmented and stored on one or more storage devices and/or
computing devices (e.g., servers) located at the same or different
locations of a network or collection of networks (e.g., in the
cloud, in edge devices, etc.). The machine readable instructions
may require one or more of installation, modification, adaptation,
updating, combining, supplementing, configuring, decryption,
decompression, unpacking, distribution, reassignment, compilation,
etc., in order to make them directly readable, interpretable,
and/or executable by a computing device and/or other machine. For
example, the machine readable instructions may be stored in
multiple parts, which are individually compressed, encrypted,
and/or stored on separate computing devices, wherein the parts when
decrypted, decompressed, and/or combined form a set of machine
executable instructions that implement one or more operations that
may together form a program such as that described herein.
[0052] In another example, the machine readable instructions may be
stored in a state in which they may be read by processor circuitry,
but require addition of a library (e.g., a dynamic link library
(DLL)), a software development kit (SDK), an application
programming interface (API), etc., in order to execute the machine
readable instructions on a particular computing device or other
device. In another example, the machine readable instructions may
need to be configured (e.g., settings stored, data input, network
addresses recorded, etc.) before the machine readable instructions
and/or the corresponding program(s) can be executed in whole or in
part. Thus, machine readable media, as used herein, may include
machine readable instructions and/or program(s) regardless of the
particular format or state of the machine readable instructions
and/or program(s) when stored or otherwise at rest or in
transit.
[0053] The machine readable instructions described herein can be
represented by any past, present, or future instruction language,
scripting language, programming language, etc. For example, the
machine readable instructions may be represented using any of the
following languages: C, C++, Java, C#, Perl, Python, JavaScript,
HyperText Markup Language (HTML), Structured Query Language (SQL),
Swift, etc.
[0054] As mentioned above, the example operations of FIGS. 3 and/or
4 may be implemented using executable instructions (e.g., computer
and/or machine readable instructions) stored on one or more
non-transitory computer and/or machine readable media such as
optical storage devices, magnetic storage devices, an HDD, a flash
memory, a read-only memory (ROM), a CD, a DVD, a cache, a RAM of
any type, a register, and/or any other storage device or storage
disk in which information is stored for any duration (e.g., for
extended time periods, permanently, for brief instances, for
temporarily buffering, and/or for caching of the information). As
used herein, the terms non-transitory computer readable medium and
non-transitory computer readable storage medium are expressly
defined to include any type of computer readable storage device
and/or storage disk and to exclude propagating signals and to
exclude transmission media.
[0055] "Including" and "comprising" (and all forms and tenses
thereof) are used herein to be open ended terms. Thus, whenever a
claim employs any form of "include" or "comprise" (e.g., comprises,
includes, comprising, including, having, etc.) as a preamble or
within a claim recitation of any kind, it is to be understood that
additional elements, terms, etc., may be present without falling
outside the scope of the corresponding claim or recitation. As used
herein, when the phrase "at least" is used as the transition term
in, for example, a preamble of a claim, it is open-ended in the
same manner as the term "comprising" and "including" are open
ended. The term "and/or" when used, for example, in a form such as
A, B, and/or C refers to any combination or subset of A, B, C such
as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with
C, (6) B with C, or (7) A with B and with C. As used herein in the
context of describing structures, components, items, objects and/or
things, the phrase "at least one of A and B" is intended to refer
to implementations including any of (1) at least one A, (2) at
least one B, or (3) at least one A and at least one B. Similarly,
as used herein in the context of describing structures, components,
items, objects and/or things, the phrase "at least one of A or B"
is intended to refer to implementations including any of (1) at
least one A, (2) at least one B, or (3) at least one A and at least
one B. As used herein in the context of describing the performance
or execution of processes, instructions, actions, activities and/or
steps, the phrase "at least one of A and B" is intended to refer to
implementations including any of (1) at least one A, (2) at least
one B, or (3) at least one A and at least one B. Similarly, as used
herein in the context of describing the performance or execution of
processes, instructions, actions, activities and/or steps, the
phrase "at least one of A or B" is intended to refer to
implementations including any of (1) at least one A, (2) at least
one B, or (3) at least one A and at least one B.
[0056] As used herein, singular references (e.g., "a", "an",
"first", "second", etc.) do not exclude a plurality. The term "a"
or "an" object, as used herein, refers to one or more of that
object. The terms "a" (or "an"), "one or more", and "at least one"
are used interchangeably herein. Furthermore, although individually
listed, a plurality of means, elements or method actions may be
implemented by, e.g., the same entity or object. Additionally,
although individual features may be included in different examples
or claims, these may possibly be combined, and the inclusion in
different examples or claims does not imply that a combination of
features is not feasible and/or advantageous.
[0057] FIG. 3 is a flowchart representative of example machine
readable instructions and/or example operations 300 that may be
executed and/or instantiated by processor circuitry to implement
the example knowledge builder circuitry and the example model
builder circuitry of FIG. 1. The machine readable instructions
and/or the operations 300 of FIG. 3 begin at block 310, at which
the request accessor circuitry 130 receives a request for
generation of a model to perform a selected task. (Block 310). In
examples disclosed herein, the user input 110 received by the
request accessor circuitry 130 includes information including, for
example, an objective of a machine learning model, a task to be
performed by the machine learning model, and, in some examples, one
or more characteristics of a target hardware on which the machine
learning model is to be executed. The request may be formatted as,
for example, a request received at a web server, a request
formatted in a structured data format (e.g., a JavaScript object
notation (JSON) format, an extensible markup language (XML) format,
etc.). The example request accessor circuitry 130 accesses hardware
data orchestration information via the hardware data orchestration
circuitry 135 and task data orchestration information via the task
data orchestration circuitry 140. The accessed information (if
available) and the request are provided to the search space
management circuitry 160 of the model builder circuitry 115.
[0058] The example hardware data orchestration circuitry 135
determines whether any prior knowledge is present in the knowledge
datastore 145 for the selected hardware. (Block 312). If no prior
knowledge is known for the selected hardware (e.g., block 312
returns a result of NO), the example hardware data orchestration
circuitry 135 adds an identification of the selected hardware to
the knowledge datastore 145. (Block 314). The identification of the
hardware enables subsequent performance metrics associated with the
selected hardware to be stored in the knowledge datastore 145 in an
organized fashion. In some examples, the identification of the
selected hardware may be omitted prior to model creation and may,
instead, be performed when performance metrics are provided to the
knowledge datastore by the execution performance statistic
collection circuitry 185.
[0059] The example task data orchestration circuitry 140 determines
whether any task information is available for the selected task.
(Block 320). If no prior knowledge is available for the selected
task (e.g., block 320 returns a result of NO), the example task
data orchestration circuitry 140 adds an identification of the
selected task to the knowledge datastore 145. (Block 325). The
identification of the selected task enables subsequent performance
metrics associated with the selected task to be stored in the
knowledge datastore 145 in an organized fashion. In some examples,
the identification of the selected task may be omitted prior to
model creation and may, instead, be performed when performance
metrics are provided to the knowledge datastore by the execution
performance statistic collection circuitry 185. The example search
space management circuitry 160 creates a search space based on user
selection of available building blocks or building blocks from
existing state-of-the-art architecture(s) for the task. (Block
327). In this manner, the search space is created, but is not based
on specific prior task knowledge (as is described in connection
with block 340, below). In some examples, the ability to perform
user selection of available building blocks (and/or whether to use
state-of-the-art architecture(s) for the task) may be configurable
by policy.
[0060] The example NAS search circuitry 170 performs neural
architecture search to generate a model using the search space.
(Block 330). In the illustrated example of FIG. 3, the NAS search
circuitry 170 starts from an uninitialized state. That is, no prior
knowledge of performance of various tasks and/or hardware on which
the tasks are to be executed is used when performing the neural
architecture search of block 330.
[0061] Returning to block 320, if the task data orchestration
circuitry 140 determines that prior knowledge is present for the
selected task (e.g., block 320 returns a result of YES), the
example task data orchestration circuitry 140 builds task
knowledge. (Block 335). To build the task knowledge, model
information is retrieved by the task data orchestration circuitry
140 from the knowledge datastore 145 for the specific task and
features are extracted from the models. In cases of a new or custom
task, similar tasks/models are retrieved based on the user input.
These features include, but are not limited to, the framework used
to train the model, the hardware specification and/or any
information for mapping model (latencies, etc.) including hardware
telemetry, the performance objective, sequence of operations,
number of FLOPs, dataset used, number of layers, etc. These
features are then ranked by hardware, objective, etc. The
respective features extracted and ranked from the model(s) is
collectively identified as the task knowledge which is then used to
create the search space. In some examples, such task knowledge is
archived in the knowledge datastore 145 to allow for efficient
retrieval should a same task be later requested.
[0062] The example search space management circuitry 160 creates a
search space from the prior task knowledge. (Block 340). The search
space may be created by, for example, ranking and selecting a prior
architecture that had an acceptable level of performance on the
target hardware (and/or hardware similar to the target hardware).
In some examples, performance statistics stored in the knowledge
datastore 145 associated with different architectures and tasks are
compared to select an architecture meeting a threshold performance
statistic. In some examples, the performance statistic upon which
the selection is based may be dependent upon the user input 110
which may indicate, for example, whether power consumption
statistics are to be prioritized over processing speed
statistics.
[0063] In some examples, the selection of the prioritization (e.g.,
prioritization of functionality, performance, power optimization,
etc.) may be guided by a policy. For example, a policy may be
provided by a policy-providing entity to control behavior of the
training operations and/or search space management. In some
examples, the policy controls other details about the creation
and/or training of the model including, for example, different
levels of neural network sparsity (e.g., 50%, 90%, etc.), different
levels of precision (e.g., thirty-two bit floating point values,
sixteen-bit floating point values, eight bit integer values,
etc.)
[0064] In some examples, the policy-providing entity may be a user
of the system of FIG. 1. However, the policy-providing entity may
be any other entity that guides functionality of the system of FIG.
1 including, for example, a system administrator, a manufacturer, a
device provider, etc. In some examples, the policy-providing entity
may be separate from the user. In this manner, the user is able to
input requests for training and/or creation of a machine learning
model, while allowing the parameters under which the training
and/or creation of the machine learning model to be based on the
policy created by the policy-providing entity.
[0065] In some examples the policy is provisioned to the system of
FIG. 1 by the policy-providing entity via a platform Trusted
Execution Environment (TEE). However, the policy may be provided to
the system of FIG. 1 in any other manner.
[0066] The example NAS search circuitry 170 generates a model using
neural architecture search, based on the search space created by
the search space management circuitry 160. (Block 350). In this
manner, the neural architecture search performed by the NAS search
circuitry 170 at block 350 starts from an initialized state based
on the prior task knowledge (e.g., starting from an architecture
which previously met a performance threshold).
[0067] The example anchor point inserter circuitry 165 then inserts
anchor points into the generated model. (Block 360). Anchor points
provide locations at which performance statistics are to be
measured by the execution performance statistic collection
circuitry 185. Moreover, the anchor points provide locations by
which additional information about the model and/or the
objectives/tasks of the model may be captured. In examples
disclosed herein, anchor points are inserted intermediate
respective layers of the generated model. In some examples, anchor
points are added to the model prior to the first layer and after
the last layer of the model. In some other examples, anchor points
are added adjacent (e.g., before and after) particular types of
layers (e.g., a convolution layer).
[0068] The example model outputter circuitry 175 provides the
generated model to the target hardware 120 for execution by the
model execution circuitry 180. (Block 370). In examples disclosed
herein, the model may first be stored at a storage location (e.g.,
a server) before being provided to the model execution circuitry
180. In some examples, the model execution circuitry 180 may
retrieve the model from the storage location or directly from the
model outputter circuitry 175. The process of the illustrated
example of FIG. 3 then terminates, but by may be re-executed upon,
for example, receipt of subsequent user input 110.
[0069] FIG. 4 is a flowchart representative of example machine
readable instructions and/or example operations 400 that may be
executed and/or instantiated by processor circuitry to implement
the example target hardware 120 of FIG. 1. The machine readable
instructions and/or the operations 400 of FIG. 4 begin at block
410, at which the model execution circuitry 180 begin execution of
a model received from the model outputter circuitry 175. (Block
410). During execution of the model, the example execution
performance statistic collection circuitry 185 collects model
execution statistics using the inserted anchor points. (Block 420).
The collected execution statistics are provided to the knowledge
datastore 145. (Block 430). In examples disclosed herein, the
collected execution statistics include information about the anchor
points. Including information about the anchor points enables
statistics specific to particular features to be utilized when
generating task knowledge.
[0070] FIG. 5 is a block diagram of an example processor platform
500 structured to execute and/or instantiate the machine readable
instructions and/or the operations of FIGS. 3 and/or 4 to implement
the system 100 of FIG. 1. The processor platform 500 can be, for
example, a server, a personal computer, a workstation, a
self-learning machine (e.g., a neural network), a mobile device
(e.g., a cell phone, a smart phone, a tablet such as an iPad.TM.),
a personal digital assistant (PDA), an Internet appliance, a DVD
player, a CD player, a digital video recorder, a Blu-ray player, a
gaming console, a personal video recorder, a set top box, a headset
(e.g., an augmented reality (AR) headset, a virtual reality (VR)
headset, etc.) or other wearable device, or any other type of
computing device.
[0071] The processor platform 500 of the illustrated example
includes processor circuitry 512. The processor circuitry 512 of
the illustrated example is hardware. For example, the processor
circuitry 512 can be implemented by one or more integrated
circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs,
and/or microcontrollers from any desired family or manufacturer.
The processor circuitry 512 may be implemented by one or more
semiconductor based (e.g., silicon based) devices. In this example,
the processor circuitry 512 implements the knowledge builder
circuitry 105 and the model builder circuitry 115. In some
examples, the knowledge builder circuitry 105 and the model builder
circuitry 115 may be implemented on separate processor
platforms.
[0072] The processor circuitry 512 of the illustrated example
includes a local memory 513 (e.g., a cache, registers, etc.). The
processor circuitry 512 of the illustrated example is in
communication with a main memory including a volatile memory 514
and a non-volatile memory 516 by a bus 518. The volatile memory 514
may be implemented by Synchronous Dynamic Random Access Memory
(SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS.RTM. Dynamic
Random Access Memory (RDRAM.RTM.), and/or any other type of RAM
device. The non-volatile memory 516 may be implemented by flash
memory and/or any other desired type of memory device. Access to
the main memory 514, 516 of the illustrated example is controlled
by a memory controller 517.
[0073] The processor platform 500 of the illustrated example also
includes interface circuitry 520. The interface circuitry 520 may
be implemented by hardware in accordance with any type of interface
standard, such as an Ethernet interface, a universal serial bus
(USB) interface, a Bluetooth.RTM. interface, a near field
communication (NFC) interface, a Peripheral Component Interconnect
(PCI) interface, and/or a Peripheral Component Interconnect Express
(PCIe) interface.
[0074] In the illustrated example, one or more input devices 522
are connected to the interface circuitry 520. The input device(s)
522 permit(s) a user to enter data and/or commands into the
processor circuitry 512. The input device(s) 522 can be implemented
by, for example, an audio sensor, a microphone, a camera (still or
video), a keyboard, a button, a mouse, a touchscreen, a track-pad,
a trackball, an isopoint device, and/or a voice recognition
system.
[0075] One or more output devices 524 are also connected to the
interface circuitry 520 of the illustrated example. The output
device(s) 524 can be implemented, for example, by display devices
(e.g., a light emitting diode (LED), an organic light emitting
diode (OLED), a liquid crystal display (LCD), a cathode ray tube
(CRT) display, an in-place switching (IPS) display, a touchscreen,
etc.), a tactile output device, a printer, and/or speaker. The
interface circuitry 520 of the illustrated example, thus, typically
includes a graphics driver card, a graphics driver chip, and/or
graphics processor circuitry such as a GPU.
[0076] The interface circuitry 520 of the illustrated example also
includes a communication device such as a transmitter, a receiver,
a transceiver, a modem, a residential gateway, a wireless access
point, and/or a network interface to facilitate exchange of data
with external machines (e.g., computing devices of any kind) by a
network 526. The communication can be by, for example, an Ethernet
connection, a digital subscriber line (DSL) connection, a telephone
line connection, a coaxial cable system, a satellite system, a
line-of-site wireless system, a cellular telephone system, an
optical connection, etc.
[0077] The processor platform 500 of the illustrated example also
includes one or more mass storage devices 528 to store software
and/or data. Examples of such mass storage devices 528 include
magnetic storage devices, optical storage devices, floppy disk
drives, HDDs, CDs, Blu-ray disk drives, redundant array of
independent disks (RAID) systems, solid state storage devices such
as flash memory devices and/or SSDs, and DVD drives.
[0078] The machine executable instructions 532, which may be
implemented by the machine readable instructions of FIGS. 3 and/or
4, may be stored in the mass storage device 528, in the volatile
memory 514, in the non-volatile memory 516, and/or on a removable
non-transitory computer readable storage medium such as a CD or
DVD.
[0079] FIG. 5 is a block diagram of an example implementation of
the processor circuitry 512 of FIG. 5. In this example, the
processor circuitry 512 of FIG. 5 is implemented by a general
purpose microprocessor 600. The general purpose microprocessor
circuitry 600 executes some or all of the machine readable
instructions of the flowchart of FIG. 3 to effectively instantiate
the knowledge builder circuitry 105 and/or the example model
builder circuitry 115 of FIG. 1 as logic circuits to perform the
operations corresponding to those machine readable instructions. In
some such examples, the circuitry of FIG. 1 is instantiated by the
hardware circuits of the microprocessor 600 in combination with the
instructions. For example, the microprocessor 600 may implement
multi-core hardware circuitry such as a CPU, a DSP, a GPU, an XPU,
etc. Although it may include any number of example cores 602 (e.g.,
1 core), the microprocessor 600 of this example is a multi-core
semiconductor device including N cores. The cores 602 of the
microprocessor 600 may operate independently or may cooperate to
execute machine readable instructions. For example, machine code
corresponding to a firmware program, an embedded software program,
or a software program may be executed by one of the cores 602 or
may be executed by multiple ones of the cores 602 at the same or
different times. In some examples, the machine code corresponding
to the firmware program, the embedded software program, or the
software program is split into threads and executed in parallel by
two or more of the cores 602. The software program may correspond
to a portion or all of the machine readable instructions and/or
operations represented by the flowchart of FIG. 3.
[0080] The cores 602 may communicate by a first example bus 604. In
some examples, the first bus 604 may implement a communication bus
to effectuate communication associated with one(s) of the cores
602. For example, the first bus 604 may implement at least one of
an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral
Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or
alternatively, the first bus 604 may implement any other type of
computing or electrical bus. The cores 602 may obtain data,
instructions, and/or signals from one or more external devices by
example interface circuitry 606. The cores 602 may output data,
instructions, and/or signals to the one or more external devices by
the interface circuitry 606. Although the cores 602 of this example
include example local memory 620 (e.g., Level 1 (L1) cache that may
be split into an L1 data cache and an L1 instruction cache), the
microprocessor 600 also includes example shared memory 610 that may
be shared by the cores (e.g., Level 2 (L2_cache)) for high-speed
access to data and/or instructions. Data and/or instructions may be
transferred (e.g., shared) by writing to and/or reading from the
shared memory 610. The local memory 620 of each of the cores 602
and the shared memory 610 may be part of a hierarchy of storage
devices including multiple levels of cache memory and the main
memory (e.g., the main memory 514, 516 of FIG. 5). Typically,
higher levels of memory in the hierarchy exhibit lower access time
and have smaller storage capacity than lower levels of memory.
Changes in the various levels of the cache hierarchy are managed
(e.g., coordinated) by a cache coherency policy.
[0081] Each core 602 may be referred to as a CPU, DSP, GPU, etc.,
or any other type of hardware circuitry. Each core 602 includes
control unit circuitry 614, arithmetic and logic (AL) circuitry
(sometimes referred to as an ALU) 616, a plurality of registers
618, the L1 cache 620, and a second example bus 622. Other
structures may be present. For example, each core 602 may include
vector unit circuitry, single instruction multiple data (SIMD) unit
circuitry, load/store unit (LSU) circuitry, branch/jump unit
circuitry, floating-point unit (FPU) circuitry, etc. The control
unit circuitry 614 includes semiconductor-based circuits structured
to control (e.g., coordinate) data movement within the
corresponding core 602. The AL circuitry 616 includes
semiconductor-based circuits structured to perform one or more
mathematic and/or logic operations on the data within the
corresponding core 602. The AL circuitry 616 of some examples
performs integer based operations. In other examples, the AL
circuitry 616 also performs floating point operations. In yet other
examples, the AL circuitry 616 may include first AL circuitry that
performs integer based operations and second AL circuitry that
performs floating point operations. In some examples, the AL
circuitry 616 may be referred to as an Arithmetic Logic Unit (ALU).
The registers 618 are semiconductor-based structures to store data
and/or instructions such as results of one or more of the
operations performed by the AL circuitry 616 of the corresponding
core 602. For example, the registers 618 may include vector
register(s), SIMD register(s), general purpose register(s), flag
register(s), segment register(s), machine specific register(s),
instruction pointer register(s), control register(s), debug
register(s), memory management register(s), machine check
register(s), etc. The registers 618 may be arranged in a bank as
shown in FIG. 5. Alternatively, the registers 618 may be organized
in any other arrangement, format, or structure including
distributed throughout the core 602 to shorten access time. The
second bus 622 may implement at least one of an I2C bus, a SPI bus,
a PCI bus, or a PCIe bus
[0082] Each core 602 and/or, more generally, the microprocessor 600
may include additional and/or alternate structures to those shown
and described above. For example, one or more clock circuits, one
or more power supplies, one or more power gates, one or more cache
home agents (CHAs), one or more converged/common mesh stops (CMSs),
one or more shifters (e.g., barrel shifter(s)) and/or other
circuitry may be present. The microprocessor 600 is a semiconductor
device fabricated to include many transistors interconnected to
implement the structures described above in one or more integrated
circuits (ICs) contained in one or more packages. The processor
circuitry may include and/or cooperate with one or more
accelerators. In some examples, accelerators are implemented by
logic circuitry to perform certain tasks more quickly and/or
efficiently than can be done by a general purpose processor.
Examples of accelerators include ASICs and FPGAs such as those
discussed herein. A GPU or other programmable device can also be an
accelerator. Accelerators may be on-board the processor circuitry,
in the same chip package as the processor circuitry and/or in one
or more separate packages from the processor circuitry.
[0083] FIG. 7 is a block diagram of another example implementation
of the processor circuitry 512 of FIG. 5. In this example, the
processor circuitry 512 is implemented by FPGA circuitry 700. The
FPGA circuitry 700 can be used, for example, to perform operations
that could otherwise be performed by the example microprocessor 600
of FIG. 6 executing corresponding machine readable instructions.
However, once configured, the FPGA circuitry 700 instantiates the
machine readable instructions in hardware and, thus, can often
execute the operations faster than they could be performed by a
general purpose microprocessor executing the corresponding
software.
[0084] More specifically, in contrast to the microprocessor 600 of
FIG. 6 described above (which is a general purpose device that may
be programmed to execute some or all of the machine readable
instructions represented by the flowchart of FIG. 3 but whose
interconnections and logic circuitry are fixed once fabricated),
the FPGA circuitry 700 of the example of FIG. 7 includes
interconnections and logic circuitry that may be configured and/or
interconnected in different ways after fabrication to instantiate,
for example, some or all of the machine readable instructions
represented by the flowchart of FIG. 3. In particular, the FPGA 700
may be thought of as an array of logic gates, interconnections, and
switches. The switches can be programmed to change how the logic
gates are interconnected by the interconnections, effectively
forming one or more dedicated logic circuits (unless and until the
FPGA circuitry 700 is reprogrammed). The configured logic circuits
enable the logic gates to cooperate in different ways to perform
different operations on data received by input circuitry. Those
operations may correspond to some or all of the software
represented by the flowchart of FIG. 3. As such, the FPGA circuitry
700 may be structured to effectively instantiate some or all of the
machine readable instructions of the flowchart of FIG. 3 as
dedicated logic circuits to perform the operations corresponding to
those software instructions in a dedicated manner analogous to an
ASIC. Therefore, the FPGA circuitry 700 may perform the operations
corresponding to the some or all of the machine readable
instructions of FIG. 3 faster than the general purpose
microprocessor can execute the same.
[0085] In the example of FIG. 6, the FPGA circuitry 700 is
structured to be programmed (and/or reprogrammed one or more times)
by an end user by a hardware description language (HDL) such as
Verilog. The FPGA circuitry 700 of FIG. 7, includes example
input/output (I/O) circuitry 702 to obtain and/or output data
to/from example configuration circuitry 704 and/or external
hardware (e.g., external hardware circuitry) 706. For example, the
configuration circuitry 704 may implement interface circuitry that
may obtain machine readable instructions to configure the FPGA
circuitry 700, or portion(s) thereof. In some such examples, the
configuration circuitry 704 may obtain the machine readable
instructions from a user, a machine (e.g., hardware circuitry
(e.g., programmed or dedicated circuitry) that may implement an
Artificial Intelligence/Machine Learning (AI/ML) model to generate
the instructions), etc. In some examples, the external hardware 706
may implement the microprocessor 600 of FIG. 6. The FPGA circuitry
700 also includes an array of example logic gate circuitry 708, a
plurality of example configurable interconnections 710, and example
storage circuitry 712. The logic gate circuitry 708 and
interconnections 710 are configurable to instantiate one or more
operations that may correspond to at least some of the machine
readable instructions of FIG. 3 and/or other desired operations.
The logic gate circuitry 708 shown in FIG. 7 is fabricated in
groups or blocks. Each block includes semiconductor-based
electrical structures that may be configured into logic circuits.
In some examples, the electrical structures include logic gates
(e.g., And gates, Or gates, Nor gates, etc.) that provide basic
building blocks for logic circuits. Electrically controllable
switches (e.g., transistors) are present within each of the logic
gate circuitry 708 to enable configuration of the electrical
structures and/or the logic gates to form circuits to perform
desired operations. The logic gate circuitry 708 may include other
electrical structures such as look-up tables (LUTs), registers
(e.g., flip-flops or latches), multiplexers, etc.
[0086] The interconnections 710 of the illustrated example are
conductive pathways, traces, vias, or the like that may include
electrically controllable switches (e.g., transistors) whose state
can be changed by programming (e.g., using an HDL instruction
language) to activate or deactivate one or more connections between
one or more of the logic gate circuitry 708 to program desired
logic circuits.
[0087] The storage circuitry 712 of the illustrated example is
structured to store result(s) of the one or more of the operations
performed by corresponding logic gates. The storage circuitry 712
may be implemented by registers or the like. In the illustrated
example, the storage circuitry 712 is distributed amongst the logic
gate circuitry 708 to facilitate access and increase execution
speed.
[0088] The example FPGA circuitry 700 of FIG. 7 also includes
example Dedicated Operations Circuitry 714. In this example, the
Dedicated Operations Circuitry 714 includes special purpose
circuitry 716 that may be invoked to implement commonly used
functions to avoid the need to program those functions in the
field. Examples of such special purpose circuitry 716 include
memory (e.g., DRAM) controller circuitry, PCIe controller
circuitry, clock circuitry, transceiver circuitry, memory, and
multiplier-accumulator circuitry. Other types of special purpose
circuitry may be present. In some examples, the FPGA circuitry 700
may also include example general purpose programmable circuitry 718
such as an example CPU 720 and/or an example DSP 722. Other general
purpose programmable circuitry 718 may additionally or
alternatively be present such as a GPU, an XPU, etc., that can be
programmed to perform other operations.
[0089] Although FIGS. 6 and 7 illustrate two example
implementations of the processor circuitry 512 of FIG. 5, many
other approaches are contemplated. For example, as mentioned above,
modern FPGA circuitry may include an on-board CPU, such as one or
more of the example CPU 720 of FIG. 7. Therefore, the processor
circuitry 512 of FIG. 5 may additionally be implemented by
combining the example microprocessor 600 of FIG. 6 and the example
FPGA circuitry 700 of FIG. 7. In some such hybrid examples, a first
portion of the machine readable instructions represented by the
flowchart of FIG. 3 may be executed by one or more of the cores 502
of FIG. 5, a second portion of the machine readable instructions
represented by the flowchart of FIG. 3 may be executed by the FPGA
circuitry 700 of FIG. 7, and/or a third portion of the machine
readable instructions represented by the flowchart of FIG. 3 may be
executed by an ASIC. It should be understood that some or all of
the circuitry of FIG. 1 may, thus, be instantiated at the same or
different times. Some or all of the circuitry may be instantiated,
for example, in one or more threads executing concurrently and/or
in series. Moreover, in some examples, some or all of the circuitry
of FIG. 1 may be implemented within one or more virtual machines
and/or containers executing on the microprocessor.
[0090] In some examples, the processor circuitry 512 of FIG. 5 may
be in one or more packages. For example, the processor circuitry
600 of FIG. 6 and/or the FPGA circuitry 700 of FIG. 7 may be in one
or more packages. In some examples, an XPU may be implemented by
the processor circuitry 512 of FIG. 5, which may be in one or more
packages. For example, the XPU may include a CPU in one package, a
DSP in another package, a GPU in yet another package, and an FPGA
in still yet another package.
[0091] A block diagram illustrating an example software
distribution platform 805 to distribute software such as the
example machine readable instructions 532 of FIG. 5 to hardware
devices owned and/or operated by third parties is illustrated in
FIG. 8. The example software distribution platform 805 may be
implemented by any computer server, data facility, cloud service,
etc., capable of storing and transmitting software to other
computing devices. The third parties may be customers of the entity
owning and/or operating the software distribution platform 805. For
example, the entity that owns and/or operates the software
distribution platform 805 may be a developer, a seller, and/or a
licensor of software such as the example machine readable
instructions 532 of FIG. 5. The third parties may be consumers,
users, retailers, OEMs, etc., who purchase and/or license the
software for use and/or re-sale and/or sub-licensing. In the
illustrated example, the software distribution platform 805
includes one or more servers and one or more storage devices. The
storage devices store the machine readable instructions 532, which
may correspond to the example machine readable instructions 300,
400 of FIGS. 3 and/or 4, as described above. The one or more
servers of the example software distribution platform 805 are in
communication with a network 810, which may correspond to any one
or more of the Internet and/or any of the example networks 526
described above. In some examples, the one or more servers are
responsive to requests to transmit the software to a requesting
party as part of a commercial transaction. Payment for the
delivery, sale, and/or license of the software may be handled by
the one or more servers of the software distribution platform
and/or by a third party payment entity. The servers enable
purchasers and/or licensors to download the machine readable
instructions 532 from the software distribution platform 805. For
example, the software, which may correspond to the example machine
readable instructions 532 of FIG. 5, may be downloaded to the
example processor platform 500, which is to execute the machine
readable instructions 532 to implement the example knowledge
builder circuitry 105, the example model builder circuitry 115,
and/or the example target hardware 120 of FIG. 1. In some examples,
one or more servers of the software distribution platform 805
periodically offer, transmit, and/or force updates to the software
(e.g., the example machine readable instructions 532 of FIG. 5) to
ensure improvements, patches, updates, etc., are distributed and
applied to the software at the end user devices.
[0092] From the foregoing, it will be appreciated that example
systems, methods, apparatus, and articles of manufacture have been
disclosed that enable neural architecture search to be performed
based on prior knowledge of models created to perform particular
tasks. Disclosed systems, methods, apparatus, and articles of
manufacture improve the efficiency of using a computing device by
avoiding re-discovery of models that would otherwise be initially
discovered by neural architecture search, but that do not function
well for the intended task. By starting from based on prior
knowledge, higher performing models can be identified more quickly.
This reduces resource consumption not only on the target hardware
(e.g., more efficient models can be developed), but also reduces
resource consumption on systems that generate models (e.g., higher
performing models can be discovered more quickly/efficiently).
Disclosed systems, methods, apparatus, and articles of manufacture
are accordingly directed to one or more improvement(s) in the
operation of a machine such as a computer or other electronic
and/or mechanical device.
[0093] Example methods, apparatus, systems, and articles of
manufacture for data enhanced automated model generation are
disclosed herein. Further examples and combinations thereof include
the following:
[0094] Example 1 includes an apparatus for data enhanced automated
model generation, the apparatus comprising interface circuitry to
access a request to generate a machine learning model, and
processor circuitry including one or more of at least one of a
central processing unit, a graphic processing unit, or a digital
signal processor, the at least one of the central processing unit,
the graphic processing unit, or the digital signal processor having
control circuitry to control data movement within the processor
circuitry, arithmetic and logic circuitry to perform one or more
first operations corresponding to instructions, and one or more
registers to store a result of the one or more first operations,
the instructions in the apparatus, a Field Programmable Gate Array
(FPGA), the FPGA including logic gate circuitry, a plurality of
configurable interconnections, and storage circuitry, the logic
gate circuitry and interconnections to perform one or more second
operations, the storage circuitry to store a result of the one or
more second operations, or Application Specific Integrate Circuitry
(ASIC) including logic gate circuitry to perform one or more third
operations, the processor circuitry to perform at least one of the
first operations, the second operations, or the third operations to
instantiate task data orchestration circuitry to generate task
knowledge based on a previously generated machine learning model,
search space management circuitry to create a search space based on
the task knowledge, and neural architecture search circuitry to
generate the machine learning model using neural architecture
search, the neural architecture search circuitry to begin an
architecture search based on the search space.
[0095] Example 2 includes the apparatus of example 1, wherein the
processor circuitry is to, during generation of the machine
learning model, insert a plurality of anchor points into the
machine learning model, the anchor points to be used for collection
of a performance statistic concerning execution of the machine
learning model.
[0096] Example 3 includes the apparatus of example 2, wherein the
performance statistic includes at least one of power efficiency or
energy efficiency.
[0097] Example 4 includes the apparatus of example 2, wherein the
processor circuitry is further to collect the performance statistic
based on the anchor points.
[0098] Example 5 includes the apparatus of example 4, wherein, to
generate the task knowledge, the processor circuitry is further to
rank features of the previously generated machine learning
model.
[0099] Example 6 includes the apparatus of example 1, wherein to
create the search space, the processor circuitry is to select a
prior architecture based on performance of the prior architecture
on a selected hardware.
[0100] Example 7 includes At least one non-transitory computer
readable storage medium comprising instructions that, when
executed, cause at least one processor to at least access a request
to generate a machine learning model to perform a selected task,
generate task knowledge based on a previously generated machine
learning model, create a search space based on the task knowledge,
and generate a machine learning model using neural architecture
search, the neural architecture search beginning based on the
search space.
[0101] Example 8 includes the at least one non-transitory computer
readable storage medium of example 7, wherein the instructions,
when executed, further cause the at least one processor to insert a
plurality of anchor points into the machine learning model, the
anchor points to be used when collecting a performance statistic
concerning execution of the machine learning model.
[0102] Example 9 includes the at least one non-transitory computer
readable storage medium of example 8, wherein the instructions,
when executed, further cause the at least one processor to collect
the performance statistic based on the anchor points.
[0103] Example 10 includes the at least one non-transitory computer
readable storage medium of example 9, wherein the instructions,
when executed, further cause the at least one processor to rank
features of the previously generated machine learning model to
generate the task knowledge.
[0104] Example 11 includes the at least one non-transitory computer
readable storage medium of example 7, wherein the instructions,
when executed, further cause the at least one processor select a
prior architecture based on performance of the prior architecture
on a selected hardware to create the search space.
[0105] Example 12 includes a method for data enhanced automated
model generation, the method comprising accessing a request to
generate a machine learning model to perform a selected task,
generating task knowledge based on a previously generated machine
learning model, creating a search space based on the task
knowledge, and generating a machine learning model using neural
architecture search, the neural architecture search beginning based
on the search space.
[0106] Example 13 includes the method of example 12, further
including, during generation of the machine learning model,
inserting a plurality of anchor points into the machine learning
model, the anchor points to be used when collecting a performance
statistic concerning execution of the machine learning model.
[0107] Example 14 includes the method of example 13, further
including collecting the performance statistic based on the anchor
points.
[0108] Example 15 includes the method of example 14, wherein the
generation of the task knowledge includes ranking features of the
previously generated machine learning model.
[0109] Example 16 includes the method of example 12, wherein the
creation of the search space includes selecting a prior
architecture based on performance of the prior architecture on a
selected hardware.
[0110] Example 17 includes an apparatus for data enhanced automated
model generation, the apparatus comprising means for accessing a
request to generate a machine learning model to perform a selected
task, means for generating task knowledge based on a previously
generated machine learning model, means for creating a search space
based on the task knowledge, and means for generating a machine
learning model using neural architecture search, the neural
architecture search beginning based on the search space.
[0111] Example 18 includes the apparatus of example 17, further
means for inserting, during generation of the machine learning
model, a plurality of anchor points into the machine learning
model, the anchor points to be used when collecting a performance
statistic concerning execution of the machine learning model.
[0112] Example 19 includes the apparatus of example 18, further
including means for collecting the performance statistic based on
the anchor points.
[0113] Example 20 includes the apparatus of example 19, wherein the
means for generating is further to rank features of the previously
generated machine learning model.
[0114] Example 21 includes the apparatus of example 17, wherein the
means for creating is to select a prior architecture based on
performance of the prior architecture on a selected hardware.
[0115] The following claims are hereby incorporated into this
Detailed Description by this reference. Although certain example
systems, methods, apparatus, and articles of manufacture have been
disclosed herein, the scope of coverage of this patent is not
limited thereto. On the contrary, this patent covers all systems,
methods, apparatus, and articles of manufacture fairly falling
within the scope of the claims of this patent.
* * * * *