U.S. patent application number 17/520977 was filed with the patent office on 2022-02-24 for semiconductor device.
The applicant listed for this patent is Semiconductor Energy Laboratory Co., Ltd.. Invention is credited to Kiyoshi KATO, Jun KOYAMA, Shunpei YAMAZAKI.
Application Number | 20220059531 17/520977 |
Document ID | / |
Family ID | |
Filed Date | 2022-02-24 |
United States Patent
Application |
20220059531 |
Kind Code |
A1 |
YAMAZAKI; Shunpei ; et
al. |
February 24, 2022 |
SEMICONDUCTOR DEVICE
Abstract
It is an object to provide a semiconductor having a novel
structure. In the semiconductor device, a plurality of memory
elements are connected in series and each of the plurality of
memory elements includes first to third transistors thus forming a
memory circuit. A source or a drain of a first transistor which
includes an oxide semiconductor layer is in electrical contact with
a gate of one of a second and a third transistor. The extremely low
off current of a first transistor containing the oxide
semiconductor layer allows storing, for long periods of time,
electrical charges in the gate electrode of one of the second and
the third transistor, whereby a substantially permanent memory
effect can be obtained. The second and the third transistors which
do not contain an oxide semiconductor layer allow high-speed
operations when using the memory circuit.
Inventors: |
YAMAZAKI; Shunpei;
(Setagaya, JP) ; KOYAMA; Jun; (Sagamihara, JP)
; KATO; Kiyoshi; (Atsugi, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Semiconductor Energy Laboratory Co., Ltd. |
Atsugi-shi |
|
JP |
|
|
Appl. No.: |
17/520977 |
Filed: |
November 8, 2021 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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13939223 |
Jul 11, 2013 |
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17520977 |
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12912190 |
Oct 26, 2010 |
8860108 |
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13939223 |
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International
Class: |
H01L 27/088 20060101
H01L027/088; G11C 11/405 20060101 G11C011/405; G11C 11/404 20060101
G11C011/404; G11C 16/02 20060101 G11C016/02; H01L 27/02 20060101
H01L027/02; H01L 27/115 20060101 H01L027/115; H01L 27/11517
20060101 H01L027/11517; H01L 27/1156 20060101 H01L027/1156; H01L
27/12 20060101 H01L027/12; H01L 27/105 20060101 H01L027/105 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 30, 2009 |
JP |
2009-251275 |
Claims
1. (canceled)
2. A semiconductor device comprising: a first transistor comprising
silicon in a channel formation region; and a second transistor
comprising an oxide semiconductor layer in a channel formation
region, wherein a first insulating layer is over the gate electrode
of the first transistor, wherein a first conductive layer is over
the first insulating layer and electrically connected to one of a
source and a drain of the second transistor, wherein the oxide
semiconductor layer is over the first insulating layer and in
contact with a top surface of the first conductive layer, wherein a
second insulating layer is over the oxide semiconductor layer,
wherein a second conductive layer is over the second insulating
layer and electrically connected to the first conductive layer
through a first opening of the second insulating layer, wherein the
second conductive layer is electrically connected to the gate
electrode of the first transistor through an opening of the first
insulating layer and a second opening of the second insulating
layer, and wherein a third conductive layer is over the second
insulating layer and electrically connected to one of a source and
a drain of the first transistor.
3. The semiconductor device according to claim 2, wherein the
silicon is a single crystal silicon.
4. The semiconductor device according to claim 2, wherein the oxide
semiconductor layer and the second opening of the second insulating
layer do not overlap each other.
5. The semiconductor device according to claim 2, further
comprising a capacitor electrically connected to a gate electrode
of the first transistor.
Description
TECHNICAL FIELD
[0001] The invention disclosed herein relates to a semiconductor
device using a semiconductor element and a method for manufacturing
the semiconductor device.
BACKGROUND ART
[0002] Storage devices using semiconductor elements are broadly
classified into two categories: volatile memory devices that lose
stored data when power supply stops, and non-volatile memory
devices that retain stored data even when power is not
supplied.
[0003] A typical example of a volatile storage device is a DRAM
(dynamic random access memory). A DRAM stores data in such a manner
that a transistor included in a storage element is selected and
electric charge is stored in a capacitor.
[0004] When data is read from a DRAM, according to the
above-described principle, electric charge in a capacitor is lost;
thus, another writing operation is necessary every time data is
read. Moreover, a transistor included in a storage element has a
leakage current and electric charge flows into or out of the
capacitor even when the transistor is not selected, so that the
data holding time is short. For that reason, another writing
operation (refresh operation) is necessary at predetermined
intervals, and it is difficult to substantially reduce power
consumption. Furthermore, since stored data is lost when power
supply stops, an additional storage device using a magnetic
material or an optical material is needed in order to hold the data
for a long time.
[0005] Another example of a volatile storage device is an SRAM
(static random access memory). An SRAM stores data by using a
circuit such as a flip-flop and thus does not need refresh
operation. This means that an SRAM has an advantage over a DRAM.
However, cost per storage capacity is increased because a circuit
such as a flip-flop is used. Moreover, as in a DRAM, stored data in
an SRAM is lost when power supply stops.
[0006] A typical example of a non-volatile storage device is a
flash memory. A flash memory includes a floating gate between a
gate electrode and a channel formation region in a transistor and
stores data by holding electric charge in the floating gate.
Therefore, a flash memory has advantages in that the data holding
time is extremely long (almost permanent) and refresh operation
which is necessary in a volatile storage device is not needed
(e.g., see Patent Document 1).
[0007] However, a gate insulating layer included in a storage
element deteriorates by tunneling current generated in writing, so
that the storage element stops its function after a predetermined
number of writing operations. In order to reduce adverse effects of
this problem, a method in which the number of writing operations
for storage elements is equalized is employed, for example.
However, a complicated peripheral circuit is needed to apply this
method. Moreover, employing such a method does not solve the
fundamental problem of lifetime. In other words, a flash memory is
not suitable for applications in which data is frequently
rewritten.
[0008] In addition, high voltage is necessary for injecting
electric charge in the floating gate or for removing the electric
charge. Further, it takes a relatively long time to inject or
remove electric charge, and it is not easy to increase writing and
erasing speed.
REFERENCE
[0009] Patent Document 1: Japanese Published Patent Application No.
S57-105889
DISCLOSURE OF INVENTION
[0010] In view of the foregoing problems, an object of one
embodiment of the invention disclosed herein is to provide a
semiconductor device with a novel structure in which stored data
can be retained even when power is not supplied, and which does not
have a limitation on the number of writing.
[0011] One embodiment of the present invention is a semiconductor
device having a multilayered structure comprising a transistor
formed using an oxide semiconductor, and a transistor formed using
a material which is not an oxide semiconductor. As examples, the
following structures can be employed.
[0012] An embodiment of the present invention is a semiconductor
device including a first wiring (source line), a second wiring (bit
line), a third wiring (first signal line), a fourth wiring (second
signal line), and a fifth wiring (word line). A plurality of memory
elements are connected in series between the first wiring and the
second wiring. Each of the plurality of memory elements includes a
first transistor including a first gate electrode, a first source
electrode, and a first drain electrode, a second transistor
including a second gate electrode, a second source electrode, and a
second drain electrode, and a third transistor including a third
gate electrode, a third source electrode, and a third drain
electrode. The first transistor is provided over a substrate
including a semiconductor material. The second transistor includes
an oxide semiconductor layer. The first gate electrode and one of
the second source electrode and the second drain electrode are
electrically connected to each other. The first wiring (source
line), the first source electrode, and the third source electrode
are electrically connected to each other. The second wiring (bit
line), the first drain electrode, and the third drain electrode are
electrically connected to each other. The third wiring (first
signal line) and the other of the second source electrode and the
second drain electrode are electrically connected to each other.
The fourth wiring (second signal line) and the second gate
electrode are electrically connected to each other. The fifth
wiring (word line) and the third gate electrode are electrically
connected to each other.
[0013] In addition, another embodiment of the present invention is
a semiconductor device including a first wiring, a second wiring, a
third wiring, a fourth wiring, and a fifth wiring. A plurality of
memory elements are connected in series between the first wiring
and the second wiring. Each of the plurality of memory elements
including a first transistor including a first gate electrode, a
first source electrode, and a first drain electrode; a second
transistor including a second gate electrode, a second source
electrode, and a second drain electrode; and a capacitor. The first
transistor is provided over a substrate including a semiconductor
material. The second transistor includes an oxide semiconductor
layer. The first gate electrode, one of the second source electrode
and the second drain electrode, and one electrode of the capacitor
are electrically connected to each other. The first wiring and the
first source electrode are electrically connected to each other.
The second wiring and the first drain electrode are electrically
connected to each other. The third wiring and the other of the
second source electrode and the second drain electrode are
electrically connected to each other. The fourth wiring and the
second gate electrode are electrically connected to each other. The
fifth wiring and the other electrode of the capacitor are
electrically connected to each other.
[0014] In description above, the semiconductor device may include a
sixth wiring, a seventh wiring, a fourth transistor a gate
electrode of which is electrically connected to the sixth wiring,
and a fifth transistor a gate electrode of which is electrically
connected to the seven wiring. It is preferable that the second
wiring be electrically connected to the first drain electrode and
the third drain electrode through the fourth transistor, and the
first wiring be electrically connected to the first source
electrode and the third source electrode through the fifth
transistor.
[0015] In description above, the first transistor of the
semiconductor device includes a channel formation region provided
in the substrate including the semiconductor material, impurity
regions provided so as to sandwich the channel formation region, a
first gate insulating layer over the channel formation region, the
first gate electrode being located over the first gate insulating
layer, and the first source electrode and the first drain electrode
being electrically connected to the impurity regions.
[0016] In description above, the second transistor includes the
second gate electrode over the substrate including the
semiconductor material, a second gate insulating layer over the
second gate electrode, the oxide semiconductor layer over the
second gate insulating layer, and the second source electrode and
the second drain electrode electrically connected to the oxide
semiconductor layer.
[0017] In description above, the third transistor includes a
channel formation region provided in the substrate including the
semiconductor material, impurity regions provided so as to sandwich
the channel formation region, a third gate insulating layer over
the channel formation region, the third gate electrode over the
third gate insulating layer, and the third source electrode and the
third drain electrode electrically connected to the impurity
regions.
[0018] In description above, a single crystal semiconductor
substrate or an SOI substrate is preferably used as the substrate
including the semiconductor material. In particular, silicon is
preferably used as the semiconductor material.
[0019] In description above, the oxide semiconductor layer is
preferably formed using an In--Ga--Zn--O-based oxide semiconductor
material. More preferably, the oxide semiconductor layer includes a
crystal of In.sub.2Ga.sub.2ZnO.sub.7. Moreover, the concentration
of hydrogen in the oxide semiconductor layer is preferably
5.times.10.sup.19 atoms/cm.sup.3 or less. In addition, the
off-state current of the second transistor is preferably
1.times.10.sup.-13 A or less.
[0020] In any of the above structures, the second transistor can be
provided in a region overlapping with the first transistor.
[0021] Note that in this specification, the terms such as "over" or
"below" do not necessarily mean that a component is placed
"directly on" or "directly under" another component. For example,
the expression "a first gate electrode over a gate insulating
layer" does not exclude the case where a component is placed
between the gate insulating layer and the gate electrode. Moreover,
the terms such as "over" and "below" are only used for convenience
of description and can include the case where the relation of
components is reversed, unless otherwise specified.
[0022] In addition, in this specification, the term such as
"electrode" or "wiring" does not limit a function of a component.
For example, an "electrode" is sometimes used as part of a
"wiring", and vice versa. Furthermore, the term "electrode" or
"wiring" can include the case where a plurality of "electrodes" or
"wirings" are formed in an integrated manner.
[0023] Functions of a "source" and a "drain" are sometimes replaced
with each other when a transistor of opposite polarity is used or
when the direction of current flowing is changed in circuit
operation, for example. Therefore, the terms "source" and "drain"
can be replaced with each other in this specification.
[0024] Note that in this specification, the term "electrically
connected" includes the case where components are connected through
an object having any electric function. There is no particular
limitation on an object having any electric function as long as
electric signals can be transmitted and received between components
that are connected through the object.
[0025] Examples of an object having any electric function are a
resistor, an inductor, a capacitor, a switching element such as a
transistor, and an element with a variety of functions as well as
an electrode and a wiring.
[0026] In general, the term "SOT substrate" means a substrate where
a silicon semiconductor layer is provided on an insulating surface.
In this specification, the term "SOT substrate" also includes in
its category a substrate where a semiconductor layer formed using a
material which is not silicon is provided over an insulating
surface. That is, a semiconductor layer included in the "SOT
substrate" is not limited to a silicon semiconductor layer. A
substrate in the "SOT substrate" is not limited to a semiconductor
substrate such as a silicon wafer and can be a non-semiconductor
substrate such as a glass substrate, a quartz substrate, a sapphire
substrate, or a metal substrate. In other words, the "SOT
substrate" also includes in its category a conductive substrate
with an insulating surface, or an insulating substrate, provided
with a layer formed of a semiconductor material. In addition, in
this specification, the term "semiconductor substrate" means not
only a substrate formed using only a semiconductor material but
also all substrates including a semiconductor material. That is, in
this specification, the "SOT substrate" is also included in the
category of the "semiconductor substrate".
[0027] One embodiment of the present invention provides a
semiconductor device in which a transistor including a material
which is not an oxide semiconductor is placed in a lower portion
and a transistor including an oxide semiconductor is placed in an
upper portion.
[0028] Since the off-state current of a transistor including an
oxide semiconductor is extremely low, stored data can be stored for
an extremely long time by using the transistor. In other words,
power consumption can be adequately reduced because refresh
operation becomes unnecessary or the frequency of refresh operation
can be extremely low. Moreover, stored data can be stored for a
long time even when power is not supplied.
[0029] Further, a high voltage being not necessary to write data,
deterioration of the element does not become a problem.
Furthermore, data is written depending on the on state and the off
state of the transistor, whereby high-speed operation can be easily
realized. In addition, there is no need of operation for erasing
data.
[0030] Since a transistor including a material which is not an
oxide semiconductor can operate at high speed when compared to a
transistor using an oxide semiconductor, stored data can be read
out at high speed by using the transistor including a material
which is not an oxide semiconductor.
[0031] A semiconductor device with a novel feature can be realized
by including both the transistor including a material which is not
an oxide semiconductor and the transistor including an oxide
semiconductor.
BRIEF DESCRIPTION OF DRAWINGS
[0032] In the accompanying drawings:
[0033] FIG. 1 is a circuit diagram for illustrating a semiconductor
device;
[0034] FIGS. 2A and 2B are respectively a cross-sectional view and
a plan view for illustrating a semiconductor device;
[0035] FIGS. 3A to 3H are cross-sectional views illustrating steps
for manufacturing a semiconductor device;
[0036] FIGS. 4A to 4G are cross-sectional views illustrating steps
for manufacturing a semiconductor device;
[0037] FIGS. 5A to 5D are cross-sectional views illustrating steps
for manufacturing a semiconductor device;
[0038] FIG. 6 is a cross-sectional view for illustrating a
semiconductor device;
[0039] FIGS. 7A and 7B are cross-sectional views each illustrating
a semiconductor device;
[0040] FIGS. 8A and 8B are cross-sectional views each illustrating
a semiconductor device;
[0041] FIGS. 9A and 9B are cross-sectional views each illustrating
a semiconductor device;
[0042] FIG. 10 is a circuit diagram for illustrating a
semiconductor device;
[0043] FIG. 11 is a block circuit diagram for illustrating
operation of a semiconductor device;
[0044] FIG. 12 is a timing chart of writing operation for
illustrating a semiconductor device;
[0045] FIG. 13 is a circuit diagram for illustrating a
semiconductor device;
[0046] FIG. 14 is a block circuit diagram for illustrating a
semiconductor device;
[0047] FIG. 15 is a circuit diagram for illustrating a
semiconductor device;
[0048] FIG. 16 is a block circuit diagram for illustrating a
semiconductor device;
[0049] FIG. 17 is a graph illustrating a relation of potentials of
a node A and a fifth wiring;
[0050] FIG. 18 is a circuit diagram for illustrating a
semiconductor device;
[0051] FIG. 19 is a circuit diagram for illustrating a
semiconductor device;
[0052] FIG. 20 is a circuit diagram for illustrating a
semiconductor device;
[0053] FIGS. 21A to 21F each illustrate an electronic device;
[0054] FIG. 22 is a longitudinal cross-sectional view of an
inverted staggered transistor including an oxide semiconductor;
[0055] FIGS. 23A and 23B are energy band diagrams (schematic
diagrams) of a cross section A-A' in FIG. 22;
[0056] FIG. 24A illustrates a state in which a positive potential
(+V.sub.G) is applied to a gate (G1), and FIG. 24B illustrates a
state in which a negative potential (-V.sub.G) is applied to the
gate (G1); and
[0057] FIG. 25 illustrates a relation between vacuum level, work
function (.phi..sub.M) of a metal, and electron affinity (.chi.) of
an oxide semiconductor.
BEST MODE FOR CARRYING OUT THE INVENTION
[0058] Examples of embodiments of the present invention will be
described below with reference to the accompanying drawings. Note
that the present invention is not limited to the following
descriptions, and it is easily understood by those skilled in the
art that modes and details disclosed herein can be modified in
various ways without departing from the spirit and the scope of the
present invention. Therefore, the present invention is not to be
construed as being limited to the content of the embodiments
included herein.
[0059] Note that the position, the size, the range, or the like of
each structure illustrated in drawings and the like is not
accurately represented in some cases for easy understanding.
Therefore, embodiments of the present invention are not necessarily
limited to a specific position, size, range, or the like disclosed
in the drawings and the like.
[0060] In this specification, ordinal numbers such as "first",
"second", and "third" are used in order to avoid confusion among
components, and the terms do not mean limitation of the number of
components.
Embodiment 1
[0061] In this embodiment, a structure and a manufacturing method
of a semiconductor device according to one embodiment of the
invention disclosed herein will be described with reference to FIG.
1, FIGS. 2A and 2B, FIGS. 3A to 3H, FIGS. 4A to 4G, FIGS. 5A to 5D,
FIG. 6, FIGS. 7A and 7B, FIGS. 8A and 8B, and FIGS. 9A and 9B.
[0062] <Circuit Configuration of a Semiconductor Device>
[0063] FIG. 1 illustrates an example of a circuit configuration of
a semiconductor device. The semiconductor device includes a
transistor 160 formed using a material which is not an oxide
semiconductor, and a transistor 162 formed using an oxide
semiconductor.
[0064] Here, a gate electrode of the transistor 160 is electrically
connected to one of a source electrode and a drain electrode of the
transistor 162. A first wiring SL (a 1st line, also referred to as
a source line) is electrically connected to a source electrode of
the transistor 160. A second wiring BL (a 2nd line, also referred
to as a bit line) is electrically connected to a drain electrode of
the transistor 160. A third wiring S1 (a 3rd line, also referred to
as a first signal line) is electrically connected to the other of
the source electrode and the drain electrode of the transistor 162.
A fourth wiring S2 (a 4th line, also referred to as a second signal
line) is electrically connected to a gate electrode of the
transistor 162.
[0065] Since the transistor 160 including a material which is not
an oxide semiconductor can operate at higher speed in comparison
with the transistor including an oxide semiconductor, stored data
can be read at high speed by using the transistor 160. Moreover,
the transistor 162 including an oxide semiconductor has extremely
low off-state current. For that reason, a potential of the gate
electrode of the transistor 160 can be held for an extremely long
time by turning off the transistor 162.
[0066] Writing, holding, and reading of data can be performed in
the following manner, using the advantage that the potential of the
gate electrode can be held.
[0067] Firstly, writing and holding of data will be described.
First, a potential of the fourth wiring S2 is set to a potential at
which the transistor 162 is turned on, and the transistor 162 is
turned on. Thus, a potential of the third wiring S1 is supplied to
the gate electrode of the transistor 160 (writing). After that, the
potential of the fourth wiring S2 is set to a potential at which
the transistor 162 is turned off, and the transistor 162 is turned
off, whereby the potential of the gate electrode of the transistor
160 is held (holding).
[0068] Since the off-state current of the transistor 162 is
extremely low, the potential of the gate electrode of the
transistor 160 is held for a long time. For example, when the
potential of the gate electrode of the transistor 160 is a
potential at which the transistor 160 is turned on, the on state of
the transistor 160 is kept for a long time. Moreover, when the
potential of the gate electrode of the transistor 160 is a
potential at which the transistor 160 is turned off, the off state
of the transistor 160 is kept for a long time.
[0069] Secondly, reading of data will be described. When a
predetermined potential (a low potential) is supplied to the first
wiring SL in a state where the on state or the off state of the
transistor 160 is kept as described above, a potential of the
second wiring BL varies depending on the on state or the off state
of the transistor 160. For example, when the transistor 160 is on,
the potential of the second wiring BL becomes lower than the
potential of the first wiring SL. In contrast, when the transistor
160 is off, the potential of the second wiring BL is not
changed.
[0070] In such a manner, the potential of the second wiring and a
predetermined potential are compared with each other in a state
where data is held, whereby the data can be read.
[0071] Thirdly, rewriting of data will be described. Rewriting of
data is performed in a manner similar to that of the writing and
holding of data. That is, the potential of the fourth wiring S2 is
set to a potential at which the transistor 162 is turned on, and
the transistor 162 is turned on. Thus, a potential of the third
wiring S1 (a potential for new data) is supplied to the gate
electrode of the transistor 160. After that, the potential of the
fourth wiring S2 is set to a potential at which the transistor 162
is turned off, and the transistor 162 is turned off, whereby the
new data is stored.
[0072] In the semiconductor device according to the invention
disclosed herein, data can be directly rewritten by another writing
of data as described above. For that reason, erasing operation
which is necessary for a flash memory or the like is not needed, so
that a reduction in operation speed because of erasing operation
can be prevented. In other words, high-speed operation of the
semiconductor device can be realized.
[0073] Note that an n-channel transistor in which electrons are the
majority carriers is used in the above description; it is needless
to say that a p-channel transistor in which holes are the majority
carriers can be used instead of the n-channel transistor.
[0074] <Planar Structure and Cross-sectional Structure of
Semiconductor Device>
[0075] FIGS. 2A and 2B illustrate an example of a structure of the
semiconductor device. FIG. 2A illustrates a cross section of the
semiconductor device, and FIG. 2B illustrates a plan view of the
semiconductor device. Here, FIG. 2A corresponds to a cross section
along line A1-A2 and line B1-B2 in FIG. 2B. The semiconductor
device illustrated in FIGS. 2A and 2B includes the transistor 160
including a material which is not an oxide semiconductor in a lower
portion, and the transistor 162 including an oxide semiconductor in
an upper portion. Note that the transistors 160 and 162 are
n-channel transistors here; alternatively, a p-channel transistor
may be used. In particular, it is easy to use a p-channel
transistor as the transistor 160.
[0076] The transistor 160 includes a channel formation region 116
provided in a substrate 100 including a semiconductor material,
impurity regions 114 and heavily doped regions 120 (these regions
can be collectively referred to simply as impurity regions)
provided so as to sandwich the channel formation region 116, a gate
insulating layer 108 provided over the channel formation region
116, a gate electrode 110 provided over the gate insulating layer
108, and a source electrode or drain electrode (hereinafter
referred to as a source/drain electrode) 130a electrically
connected to a first impurity region 114 on one side of the channel
formation region 116 and a source/drain electrode 130b electrically
connected to a second impurity region 114 located on another side
of the channel formation region 116.
[0077] A sidewall insulating layer 118 is provided on a side
surface of the gate electrode 110. The sidewall insulating layer
118 are comprised between the heavily doped regions 120 formed in
regions of the substrate 100, when seen from above. A metal
compound region 124 is placed over the heavily doped regions 120.
An element insulation insulating layer 106 is provided over the
substrate 100 so as to surround the transistor 160. An interlayer
insulating layer 126 and an interlayer insulating layer 128 are
provided so as to cover the transistor 160. The source/drain
electrode 130a is electrically connected to a first metal compound
region 124 located on the one side of the channel formation region
116, and the source/drain electrode 130b is electrically connected
to a second metal compound region 124 located on the other side of
the channel formation region 116 through an opening formed in the
interlayer insulating layers 126 and 128. That is, the source/drain
electrode 130a is electrically connected to a first heavily doped
region 120 and to the first impurity region 114 which are on the
one side of the channel formation region 116 through the first
metal compound region 124 on the one side of the channel formation
region 116, and the source/drain 130b is electrically connected to
a second heavily doped region 120 and the to the second impurity
region 114 which are on the other side of the channel formation
region 116, through second the metal compound region 124. An
electrode 130c that is formed in a manner similar to that of the
source/drain electrodes 130a and 130b is electrically connected to
the gate electrode 110.
[0078] The transistor 162 including an oxide semiconductor includes
a gate electrode 136d provided over the interlayer insulating layer
128, a gate insulating layer 138 provided over the gate electrode
136d, an oxide semiconductor layer 140 provided over the gate
insulating layer 138, and a source/drain electrode 142a and a
source/drain electrode 142b that are provided over the oxide
semiconductor layer 140 and electrically connected to the oxide
semiconductor layer 140.
[0079] Here, the gate electrode 136d is provided so as to be
embedded in an insulating layer 132 formed over the interlayer
insulating layer 128. Like the gate electrode 136d, an electrode
136a, an electrode 136b, and an electrode 136c are formed in
contact with the source/drain electrode 130a and the source/drain
electrode 130b of the transistor 160, and the electrode 130c,
respectively.
[0080] A protective insulating layer 144 is provided over the
transistor 162 so as to be in contact with part of the oxide
semiconductor layer 140. An interlayer insulating layer 146 is
provided over the protective insulating layer 144. Openings that
reach the source/drain electrode 142a and the source/drain
electrode 142b are formed in the protective insulating layer 144
and the interlayer insulating layer 146. An electrode 150d and an
electrode 150e are formed in contact with the source/drain
electrode 142a and the source/drain electrode 142b, respectively,
through the respective openings. Like the electrodes 150d and 150e,
an electrode 150a, an electrode 150b, and an electrode 150c are
formed in contact with the electrode 136a, the electrode 136b, and
the electrode 136c, respectively, through openings provided in the
gate insulating layer 138, the protective insulating layer 144, and
the interlayer insulating layer 146.
[0081] Here, the oxide semiconductor layer 140 is preferably a
highly purified oxide semiconductor layer from which impurities
such as hydrogen are adequately removed. Specifically, the
concentration of hydrogen in the oxide semiconductor layer 140 is
5.times.10.sup.19 atoms/cm.sup.3 or less, preferably
5.times.10.sup.18 atms/cm.sup.3 or less, more preferably
5.times.10.sup.17 atoms/cm.sup.3 or less. Moreover, the oxide
semiconductor layer 140 which is highly purified by an adequate
reduction in hydrogen concentration has a carrier concentration
with a low value compared to a carrier concentration of a typical
silicon wafer (a silicon wafer to which an impurity element such as
phosphorus and boron is slightly added) (approximately
5.times.10.sup.14/cm.sup.3). The transistor 162 with excellent
off-state current characteristics can be obtained with the use of
such an oxide semiconductor that is highly purified by an adequate
reduction in hydrogen concentration and becomes intrinsic or
substantially intrinsic. For example, when the drain voltage Vd is
+1 V or +10 V and the gate voltage Vg is in the range of -5 V to
-20 V, the off-state current is 1.times.10.sup.-13 A or less. The
oxide semiconductor layer 140 which is highly purified by an
adequate reduction in hydrogen concentration is used so that the
off-state current of the transistor 162 is reduced, whereby a
semiconductor device with a novel structure can be realized. Note
that the concentration of hydrogen in the oxide semiconductor layer
140 is measured by secondary ion mass spectrometry (SIMS).
[0082] An insulating layer 152 is provided over the interlayer
insulating layer 146. An electrode 154a, an electrode 154b, an
electrode 154c, and an electrode 154d are provided so as to be
embedded in the insulating layer 152. The electrode 154a is in
contact with the electrode 150a. The electrode 154b is in contact
with the electrode 150b. The electrode 154c is in contact with the
electrode 150c and the electrode 150d. The electrode 154d is in
contact with the electrode 150e.
[0083] That is, in the semiconductor device illustrated in FIGS. 2A
and 2B, the gate electrode 110 of the transistor 160 and the
source/drain electrode 142a of the transistor 162 are electrically
connected through the electrodes 130c, 136c, 150c, 154c, and
150d.
[0084] <Method for Manufacturing Semiconductor Device>
[0085] Next, an example of a method for manufacturing the
semiconductor device will be described. First, a method for
manufacturing the transistor 160 in the lower portion will be
described below with reference to FIGS. 3A to 3D, and then a method
for manufacturing the transistor 162 in the upper portion will be
described with reference to FIGS. 4A to 4G and FIGS. 5A to 5D.
[0086] <Method for Manufacturing Lower Transistor>
[0087] First, the substrate 100 including a semiconductor material
is prepared (see FIG. 3A). As the substrate 100 including a
semiconductor material, a single crystal semiconductor substrate or
a polycrystalline semiconductor substrate made of silicon, silicon
carbide, or the like; a compound semiconductor substrate made of
silicon germanium or the like; an SOI substrate; or the like can be
used. Here, an example of using a single crystal silicon substrate
as the substrate 100 including a semiconductor material is
described.
[0088] A protective layer 102 serving as a mask for forming an
element insulation insulating layer is formed over the substrate
100 (see FIG. 3A). As the protective layer 102, an insulating layer
formed using silicon oxide, silicon nitride, silicon nitride oxide,
or the like can be used, for example. Note that before or after
this step, an impurity element imparting n-type conductivity or an
impurity element imparting p-type conductivity may be added to the
substrate 100 in order to control the threshold voltage of the
transistor. Phosphorus, arsenic, or the like can be used as the
impurity imparting n-type conductivity in the case where the
semiconductor material included in the substrate 100 is silicon.
Boron, aluminum, gallium, or the like can be used as the impurity
imparting p-type conductivity.
[0089] Next, part of the substrate 100 in a region that is not
covered with the protective layer 102 (i.e., in an exposed region)
is removed by etching, using the protective layer 102 as a mask.
Thus, an isolated semiconductor region 104 is formed (see FIG. 3B).
As the etching, dry etching is preferably performed, but wet
etching may be performed. An etching gas and an etchant can be
selected as appropriate depending on a material of a layer to be
etched.
[0090] Then, an insulating layer is formed so as to cover the
semiconductor region 104, and the insulating layer in a region
overlapping with the semiconductor region 104 is selectively
removed, so that element insulation insulating layers 106 are
formed (see FIG. 3B). The insulating layer is formed using silicon
oxide, silicon nitride, silicon nitride oxide, or the like. As a
method for removing the insulating layer, any of etching treatment
and polishing treatment such as CMP (Chemical Mechanical Polishing)
can be employed. Note that the protective layer 102 is removed
after the formation of the semiconductor region 104 or after the
formation of the element insulation insulating layers 106.
[0091] Next, an insulating layer is formed over the semiconductor
region 104, and a layer including a conductive material is formed
over the insulating layer.
[0092] Because the insulating layer serves as a gate insulating
layer later, the insulating layer preferably has a single-layer
structure or a layered structure using a film containing silicon
oxide, silicon nitride oxide, silicon nitride, hafnium oxide,
aluminum oxide, tantalum oxide, or the like formed by a CVD method,
a sputtering method, or the like. Alternatively, the insulating
layer may be formed in such a manner that a surface of the
semiconductor region 104 is oxidized or nitrided by high-density
plasma treatment or thermal oxidation treatment. The high-density
plasma treatment can be performed using, for example, a mixed gas
of a rare gas such as He, Ar, Kr, or Xe and a gas such as oxygen,
nitrogen oxide, ammonia, nitrogen, or hydrogen. There is no
particular limitation on the thickness of the insulating layer; the
insulating layer can have a thickness of 1 nm to 100 nm inclusive,
for example.
[0093] The layer including a conductive material can be formed
using a metal material such as aluminum, copper, titanium,
tantalum, or tungsten. The layer including a conductive material
may be formed using a semiconductor material such as
polycrystalline silicon containing a conductive material. There is
no particular limitation on the method for forming the layer
containing a conductive material, and a variety of film formation
methods such as an evaporation method, a CVD method, a sputtering
method, or a spin coating method can be employed. Note that this
embodiment shows an example of the case where the layer containing
a conductive material is formed using a metal material.
[0094] After that, the insulating layer and the layer including a
conductive material are selectively etched, so that the gate
insulating layer 108 and the gate electrode 110 are formed (see
FIG. 3C).
[0095] Next, an insulating layer 112 that covers the gate electrode
110 is formed (see FIG. 3C). Then, the impurity regions 114 with a
shallow junction depth in the substrate 100 are formed by adding
phosphorus (P), arsenic (As), or the like to the semiconductor
region 104 (see FIG. 3C). Note that phosphorus or arsenic is added
here in order to form an n-channel transistor; an impurity element
such as boron (B) or aluminum (Al) may be added in the case of
forming a p-channel transistor. With the formation of the impurity
regions 114, the channel formation region 116 is formed in the
semiconductor region 104 below the gate insulating layer 108 (see
FIG. 3C). Here, the concentration of the impurity added can be set
as appropriate; the concentration is preferably increased when the
size of a semiconductor element is extremely decreased. The step in
which the impurity regions 114 are formed after the formation of
the insulating layer 112 is employed here; alternatively, the
insulating layer 112 may be formed after the formation of the
impurity regions 114.
[0096] Next, the sidewall insulating layers 118 are formed (see
FIG. 3D). An insulating layer is formed so as to cover the
insulating layer 112 and then subjected to highly anisotropic
etching, whereby the sidewall insulating layers 118 can be formed
in a self-aligned manner. At this time, it is preferable to partly
etch the insulating layer 112 so that a top surface of the gate
electrode 110 and top surfaces of the impurity regions 114 are
exposed.
[0097] Then, an insulating layer is formed so as to cover the gate
electrode 110, the impurity regions 114, the sidewall insulating
layers 118, and the like. Next, phosphorus (P), arsenic (As), or
the like is added to regions where the insulating layer is in
contact with the impurity regions 114, so that the heavily doped
regions 120 are formed (see FIG. 3E). After that, the insulating
layer is removed, and a metal layer 122 is formed so as to cover
the gate electrode 110, the sidewall insulating layers 118, the
heavily doped regions 120, and the like (see FIG. 3E). A variety of
film formation methods such as a vacuum evaporation method, a
sputtering method, or a spin coating method can be employed for
forming the metal layer 122. The metal layer 122 is preferably
formed using a metal material that reacts with a semiconductor
material included in the semiconductor region 104 to be a
low-resistance metal compound. Examples of such a metal material
are titanium, tantalum, tungsten, nickel, cobalt, and platinum.
[0098] Next, heat treatment is performed so that the metal layer
122 reacts with the semiconductor material. Thus, the metal
compound regions 124 that are in contact with the heavily doped
regions 120 are formed (see FIG. 3F). Note that when the gate
electrode 110 is formed using polycrystalline silicon or the like,
a metal compound region is also formed in a region of the gate
electrode 110 in contact with the metal layer 122.
[0099] As the heat treatment, irradiation with a flash lamp can be
employed, for example. Although it is needless to say that another
heat treatment method may be used, a method by which heat treatment
for an extremely short time can be achieved is preferably used in
order to improve the controllability of chemical reaction in
formation of the metal compound. Note that the metal compound
regions are formed by reaction of the metal material and the
semiconductor material and have sufficiently high conductivity. The
formation of the metal compound regions can properly reduce the
electric resistance and improve element characteristics. Note that
the metal layer 122 is removed after the metal compound regions 124
are formed.
[0100] Then, the interlayer insulating layer 126 and the interlayer
insulating layer 128 are formed so as to cover the components
formed in the above steps (see FIG. 3G). The interlayer insulating
layers 126 and 128 can be formed using an inorganic insulating
material such as silicon oxide, silicon nitride oxide, silicon
nitride, hafnium oxide, aluminum oxide, or tantalum oxide.
Moreover, the interlayer insulating layers 126 and 128 can be
formed using an organic insulating material such as polyimide or
acrylic. Note that a two-layer structure of the interlayer
insulating layer 126 and the interlayer insulating layer 128 is
employed here; however, the structure of an interlayer insulating
layer is not limited to this structure. After the formation of the
interlayer insulating layer 128, a surface of the interlayer
insulating layer 128 is preferably planarized with CMP, etching, or
the like.
[0101] Then, openings that reach the metal compound regions 124 are
formed in the interlayer insulating layers, and the source/drain
electrode 130a and the source/drain electrode 130b are formed in
the openings (see FIG. 3H). The source/drain electrodes 130a and
130b can be formed in such a manner, for example, that a conductive
layer is formed in a region including the openings by a PVD
(Physical Vapor Deposition) method, a CVD (Chemical Vapor
Deposition) method, or the like and then part of the conductive
layer is removed by etching, CMP, or the like.
[0102] Note that in the case where the source/drain electrodes 130a
and 130b are formed by removing part of the conductive layer, the
process is preferably performed so that the surfaces are
planarized. For example, when a thin titanium film or a thin
titanium nitride film is formed in a region including the openings
and then a tungsten film is formed so as to fill the openings,
unnecessary parts of the tungsten film, the titanium film, the
titanium nitride film, or the like is removed and the planarity of
the surface can be improved by subsequent CMP. The surface
including the source/drain electrodes 130a and 130b is planarized
in such a manner that an electrode, a wiring, an insulating layer,
a semiconductor layer, and the like can be favorably formed in
later steps.
[0103] Note that only the source/drain electrodes 130a and 130b in
contact with the metal compound regions 124 are shown here;
however, an electrode that is in contact with the gate electrode
110 (e.g., the electrode 130c in FIG. 2A) and the like can also be
formed in this step. There is no particular limitation on a
material used for the source/drain electrodes 130a and 130b, and a
variety of conductive materials can be used. For example, a
conductive material such as molybdenum, titanium, chromium,
tantalum, tungsten, aluminum, copper, neodymium, or scandium can be
used.
[0104] Through the above steps, the transistor 160 using the
substrate 100 including a semiconductor material is formed. Note
that an electrode, a wiring, an insulating layer, or the like may
be further formed after the above step. When the wirings have a
multi-layer structure of a layered structure including an
interlayer insulating layer and a conductive layer, a highly
integrated semiconductor device can be provided.
[0105] <Method for Manufacturing Upper Transistor>
[0106] Next, steps for manufacturing the transistor 162 over the
interlayer insulating layer 128 will be described with reference to
FIGS. 4A to 4G and FIGS. 5A to 5D. Note that FIGS. 4A to 4G and
FIGS. 5A to 5D illustrate steps for manufacturing electrodes, the
transistor 162, and the like over the interlayer insulating layer
128; therefore, the transistor 160 and the like placed below the
transistor 162 are omitted.
[0107] First, the insulating layer 132 is formed over the
interlayer insulating layer 128, the source/drain electrodes 130a
and 130b, and the electrode 130c (see FIG. 4A). The insulating
layer 132 can be formed by a PVD method, a CVD method, or the like.
The insulating layer 132 can be formed using an inorganic
insulating material such as silicon oxide, silicon nitride oxide,
silicon nitride, hafnium oxide, aluminum oxide, or tantalum
oxide.
[0108] Next, openings that reach the source/drain electrodes 130a
and 130b and the electrode 130c are formed in the insulating layer
132. At this time, an opening is also formed in a region where the
gate electrode 136d is to be formed in a later step. Then, a
conductive layer 134 is formed so as to fill the openings (see FIG.
4B). The openings can be formed by a method such as etching using a
mask. The mask can be formed by a method such as light exposure
using a photomask. Either wet etching or dry etching may be used as
the etching; dry etching is preferably used in terms of
microfabrication. The conductive layer 134 can be formed by a film
formation method such as a PVD method or a CVD method. The
conductive layer 134 can be formed using a conductive material such
as molybdenum, titanium, chromium, tantalum, tungsten, aluminum,
copper, neodymium, or scandium or an alloy or a compound (e.g., a
nitride) of any of these materials, for example.
[0109] Specifically, it is possible to employ a method in which,
for example, a thin titanium film is formed in a region including
the openings by a PVD method and a thin titanium nitride film is
formed by a CVD method, and then, a tungsten film is formed so as
to fill the openings. Here, the titanium film formed by a PVD
method has a function of reducing an oxide film at the interface
with a lower electrode to decrease the contact resistance with
lower electrodes (here, the source/drain electrodes 130a and 130b,
the electrode 130c, and the like). The titanium nitride film formed
after the titanium film has a barrier function of preventing
diffusion of the conductive material. A copper film may be formed
by a plating method after the formation of the barrier film of
titanium, titanium nitride, or the like.
[0110] After the conductive layer 134 is formed, part of the
conductive layer 134 is removed by etching, CMP, or the like, so
that the insulating layer 132 is exposed and the electrodes 136a,
136b, and 136c and the gate electrode 136d are formed (see FIG.
4C). Note that when the electrodes 136a, 136b, and 136c and the
gate electrode 136d are formed by removing part of the conductive
layer 134, the process is preferably performed so that the surfaces
are planarized. The surfaces of the insulating layer 132, the
electrodes 136a, 136b, and 136c, and the gate electrode 136d are
planarized in such a manner that an electrode, a wiring, an
insulating layer, a semiconductor layer, and the like can be
favorably formed in later steps.
[0111] Next, the gate insulating layer 138 is formed so as to cover
the insulating layer 132, the electrodes 136a, 136b, and 136c, and
the gate electrode 136d (see FIG. 4D). The gate insulating layer
138 can be formed by a CVD method, a sputtering method, or the
like. The gate insulating layer 138 is preferably formed using
silicon oxide, silicon nitride, silicon oxynitride, silicon nitride
oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like.
Note that the gate insulating layer 138 may have a single-layer
structure or a layered structure. For example, the gate insulating
layer 138 made of silicon oxynitride can be formed by a plasma CVD
method using silane (SiH.sub.4), oxygen, and nitrogen as a source
gas. There is no particular limitation on the thickness of the gate
insulating layer 138; the gate insulating layer 138 can have a
thickness of 10 nm to 500 nm inclusive, for example. In the case of
employing a layered structure, for example, the gate insulating
layer 138 is preferably a stack of a first gate insulating layer
having a thickness of 50 nm to 200 nm inclusive, and a second gate
insulating layer with a thickness of 5 nm to 300 nm inclusive over
the first gate insulating layer.
[0112] Note that an oxide semiconductor that becomes intrinsic or
substantially intrinsic by removal of impurities (a highly purified
oxide semiconductor) is quite susceptible to the interface energy
levels and the charges trapped at the interface; therefore, when
such an oxide semiconductor is used for an oxide semiconductor
layer, the interface with the gate insulating layer is important.
In other words, the gate insulating layer 138 that is to be in
contact with a highly purified oxide semiconductor layer needs to
be of high quality.
[0113] For example, the gate insulating layer 138 is preferably
formed by a high-density plasma CVD method using a microwave (2.45
GHz) because the gate insulating layer 138 can be dense, have a
high withstand voltage and be of high quality. When a highly
purified oxide semiconductor layer and a high-quality gate
insulating layer are in close contact with each other, the density
of energy levels at the interface can be reduced and interface
characteristics can be favorable.
[0114] It is needless to say that, even when a highly purified
oxide semiconductor layer is used, another method such as a
sputtering method or a plasma CVD method can be employed as long as
a high-quality insulating layer can be formed as a gate insulating
layer. Moreover, it is possible to use an insulating layer whose
quality and characteristics of the interface with the oxide
semiconductor layer are improved by heat treatment performed after
the formation of the insulating layer. In any case, an insulating
layer that has adequate film quality as the gate insulating layer
138 and can reduce interface level density with an oxide
semiconductor layer to form a favorable interface is formed as the
gate insulating layer 138.
[0115] In a gate bias-temperature stress test (BT test) at
85.degree. C. with 2.times.10.sup.6 V/cm for 12 hours, if an
impurity is added to an oxide semiconductor, a bond between the
impurity and a main component of the oxide semiconductor is broken
by a high electric field (B: bias) and high temperature (T:
temperature), thus generating a dangling bond causing a shift of
the threshold voltage (Vth).
[0116] In contrast, by reducing to a minimum impurities of an oxide
semiconductor, particularly hydrogen and water, interface
characteristics between the oxide semiconductor and the gate
insulating layer are made favorable as described above, whereby a
transistor that is stable through the BT test can be obtained.
[0117] Next, an oxide semiconductor layer is formed over the gate
insulating layer 138 and processed by a method such as etching
using a mask, so that the island-shaped oxide semiconductor layer
140 is formed (see FIG. 4E).
[0118] As the oxide semiconductor layer, it is preferable to use an
In--Ga--Zn--O-based oxide semiconductor layer, an
In--Sn--Zn--O-based oxide semiconductor layer, an
In--Al--Zn--O-based oxide semiconductor layer, a
Sn--Ga--Zn--O-based oxide semiconductor layer, an
Al--Ga--Zn--O-based oxide semiconductor layer, a
Sn--Al--Zn--O-based oxide semiconductor layer, an In--Zn--O-based
oxide semiconductor layer, a Sn--Zn--O-based oxide semiconductor
layer, an Al--Zn--O-based oxide semiconductor layer, an In--O-based
oxide semiconductor layer, a Sn--O-based oxide semiconductor layer,
or a Zn--O-based oxide semiconductor layer, which is preferably
amorphous in particular. In this embodiment, as the oxide
semiconductor layer, an amorphous oxide semiconductor layer is
formed by a sputtering method using a target for depositing an
In--Ga--Zn--O-based oxide semiconductor. Note that since
crystallization of an amorphous oxide semiconductor layer can be
suppressed by adding silicon to the amorphous oxide semiconductor
layer, an oxide semiconductor layer may be formed by, for example,
using a target containing SiO.sub.2 of 2 wt % to 10 wt %
inclusive.
[0119] As a target used for forming an oxide semiconductor layer by
a sputtering method, a metal oxide target containing zinc oxide as
its main component can be used, for example. Moreover, a target for
depositing an oxide semiconductor containing In, Ga, and Zn (a
composition ratio of In.sub.2O.sub.3:Ga.sub.2O.sub.3:ZnO=1:1:1 [mol
%]) can be used, for example. Furthermore, as a target for
depositing an oxide semiconductor containing In, Ga, and Zn, a
target has a composition ratio of In:Ga:Zn=1:1:1 [mol %] or a
composition ratio of In:Ga:Zn=1:1:2 [mol %]) may also be used. The
filling rate of a target for depositing an oxide semiconductor is
90% to 100% inclusive, preferably 95% or more (e.g., 99.9%). A
dense oxide semiconductor layer is formed when using a target for
depositing an oxide semiconductor with a high filling rate.
[0120] The atmosphere in which the oxide semiconductor layer is
formed is preferably a rare gas (typically argon) atmosphere, an
oxygen atmosphere, or a mixed atmosphere containing a rare gas
(typically argon) and oxygen. Specifically, it is preferable to use
a gas of high purity, for example a gas from which concentrations
of impurities such as hydrogen, water, a hydroxyl group, or hydride
are reduced to a few ppm (preferably a few ppb).
[0121] During formation of the oxide semiconductor layer, the
substrate is held in a treatment chamber maintaining a reduced
pressure and the substrate temperature is set between 100.degree.
C. and 600.degree. C. inclusive, preferably between 200.degree. C.
and 400.degree. C. inclusive. The oxide semiconductor layer is
formed while the substrate is heated, so that the impurity
concentration of the oxide semiconductor layer can be reduced.
Moreover, damage due to sputtering is reduced. Then, a sputtering
gas from which hydrogen and water are removed is introduced into
the treatment chamber from which remaining moisture is being
removed, and the oxide semiconductor layer is formed using metal
oxide as a target. A sorption vacuum pump is preferably used in
order to remove moisture remaining in the treatment chamber. A
cryopump, an ion pump, or a titanium sublimation pump can be used.
An evacuation unit may be a turbo pump provided with a cold trap.
In the deposition chamber that is evacuated with the cryopump, a
hydrogen atom and a compound containing a hydrogen atom such as
water (H.sub.2O) (and preferably also a compound containing a
carbon atom), for example, are removed, whereby the impurity
concentration of the oxide semiconductor layer formed in the
deposition chamber can be reduced.
[0122] The oxide semiconductor layer can be formed under the
following conditions, for example: the distance between the
substrate and the target is 100 mm; the pressure is 0.6 Pa; the
direct-current (DC) power supply is 0.5 kW; and the atmosphere is
oxygen (the flow rate ratio of oxygen is 100%). Note that it is
preferable to use a pulse direct current (DC) power supply because
powder substances (also referred to as particles or dust) generated
in film deposition can be reduced and the thickness distribution is
uniform. The thickness of the oxide semiconductor layer is 2 nm to
200 nm inclusive, preferably 5 nm to 30 nm inclusive. Note that an
appropriate thickness differs depending on an oxide semiconductor
material, and the thickness is set as appropriate depending on the
material to be used.
[0123] Note that before the oxide semiconductor layer is formed by
a sputtering method, dust on a surface of the gate insulating layer
138 is preferably removed by reverse sputtering in which an argon
gas is introduced and plasma is generated. Here, the reverse
sputtering is a method by which ions collide with a surface to be
processed so that the surface is modified, in contrast to normal
sputtering by which ions collide with a sputtering target. An
example of a method for making ions collide with a surface to be
processed is a method in which high-frequency voltage is applied to
the surface in an argon atmosphere so that plasma is generated near
a substrate. Note that an atmosphere of nitrogen, helium, oxygen,
or the like may be used instead of an argon atmosphere.
[0124] As an etching method for the oxide semiconductor layer,
either dry etching or wet etching may be employed. It is needless
to say that dry etching and wet etching can be used in combination.
The etching conditions (e.g., an etching gas or an etching
solution, etching time, and temperature) are set as appropriate
depending on the material so that the oxide semiconductor layer can
be etched into a desired shape.
[0125] An example of an etching gas used for dry etching is a gas
containing chlorine (a chlorine-based gas such as chlorine
(Cl.sub.2), boron chloride (BCl.sub.3), silicon chloride
(SiCl.sub.4), or carbon tetrachloride (CCl.sub.4)). Moreover, a gas
containing fluorine (a fluorine-based gas such as carbon
tetrafluoride (CF.sub.4), sulfur fluoride (SF.sub.6), nitrogen
fluoride (NF.sub.3), or trifluoromethane (CHF.sub.3)), hydrogen
bromide (HBr), oxygen (O.sub.2), any of these gases to which a rare
gas such as helium (He) or argon (Ar) is added, or the like may be
used.
[0126] As the dry etching method, a parallel plate RIE (reactive
ion etching) method or an ICP (inductively coupled plasma) etching
method can be used. In order to etch the oxide semiconductor layer
into a desired shape, etching conditions (e.g., the amount of
electric power applied to a coiled electrode, the amount of
electric power applied to an electrode on the substrate side, and
the electrode temperature on the substrate side) are set as
appropriate.
[0127] As an etchant used for wet etching, a mixed solution of
phosphoric acid, acetic acid, and nitric acid, an ammonia peroxide
mixture, or the like can be used. As an etchant, ITO07N (produced
by KANTO CHEMICAL CO., INC.) may also be used.
[0128] Then, a first heat treatment is preferably performed on the
oxide semiconductor layer. The oxide semiconductor layer can be
dehydrated or dehydrogenated by the first heat treatment. The
temperature of the first heat treatment is 300.degree. C. or more
and 750.degree. C. or less, preferably 400.degree. C. or more and
less than the strain point of the substrate. For example, the
substrate is introduced into an electric furnace in which a
resistance heating element or the like is used and the oxide
semiconductor layer 140 is subjected to heat treatment at
450.degree. C. for one hour in a nitrogen atmosphere. The oxide
semiconductor layer 140 is not exposed to the air during the heat
treatment so that entry of water and hydrogen can be prevented.
[0129] The heat treatment apparatus is not limited to the electric
furnace and can be an apparatus for heating an object by thermal
radiation or thermal conduction from a medium such as a heated gas.
For example, a rapid thermal annealing (RTA) apparatus such as a
gas rapid thermal annealing (GRTA) apparatus or a lamp rapid
thermal annealing (LRTA) apparatus can be used. An LRTA apparatus
is an apparatus for heating an object to be processed by radiation
of light (an electromagnetic wave) emitted from a lamp such as a
halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc
lamp, a high pressure sodium lamp, or a high pressure mercury lamp.
A GRTA apparatus is an apparatus for performing heat treatment
using a high-temperature gas. As the gas, an inert gas that does
not react with an object by heat treatment, for example, nitrogen
or a rare gas such as argon is used.
[0130] For example, as the first heat treatment, a GRTA process may
be performed as follows. The substrate is put in an inert gas that
has been heated to a high temperature of 650.degree. C. to
700.degree. C., heated for several minutes, and taken out of the
inert gas. The GRTA process enables high-temperature heat treatment
for a short time. Moreover, the GRTA process can be employed even
when the temperature exceeds the strain point of the substrate
because due to the short time of the heat treatment.
[0131] Note that the first heat treatment is preferably performed
in an atmosphere that contains nitrogen or a rare gas (e.g.,
helium, neon, or argon) as its main component and does not contain
water, hydrogen, or the like. For example, the purity of nitrogen
or a rare gas such as helium, neon, or argon introduced into a heat
treatment apparatus is 6 N (99.9999%) or more, preferably 7 N
(99.99999%) or more (i.e., the impurity concentration is 1 ppm or
less, preferably 0.1 ppm or less).
[0132] Depending on the conditions of the first heat treatment or
the material of the oxide semiconductor layer, the oxide
semiconductor layer is sometimes crystallized to be
microcrystalline or polycrystalline. For example, the oxide
semiconductor layer sometimes becomes a microcrystalline oxide
semiconductor layer having a degree of crystallization of 90% or
more, or 80% or more. Further, depending on the conditions of the
first heat treatment or the material of the oxide semiconductor
layer, the oxide semiconductor layer may be an amorphous oxide
semiconductor layer containing no crystalline component.
[0133] Furthermore, in the oxide semiconductor layer, a
microcrystal (the grain size is 1 nm to 20 nm inclusive, typically
2 nm to 4 nm inclusive) is sometimes mixed in an amorphous oxide
semiconductor (e.g., at a surface of the oxide semiconductor
layer).
[0134] The electrical characteristics of the oxide semiconductor
layer can be changed by aligning microcrystals in an amorphous
semiconductor. For example, when the oxide semiconductor layer is
formed using a target for depositing In--Ga--Zn--O-based oxide
semiconductor, the electrical characteristics of the oxide
semiconductor layer can be changed by formation of a
microcrystalline portion in which crystal grains of
In.sub.2Ga.sub.2ZnO.sub.7 with electrical anisotropy are
aligned.
[0135] Specifically, for example, when the crystal grains are
arranged so that the c-axis of In.sub.2Ga.sub.2ZnO.sub.7 is
perpendicular to a surface of the oxide semiconductor layer, the
conductivity in the direction parallel to the surface of the oxide
semiconductor layer can be improved and insulating properties in
the direction perpendicular to the surface of the oxide
semiconductor layer can be improved. Furthermore, such a
microcrystalline portion has a function of suppressing entry of an
impurity such as water or hydrogen into the oxide semiconductor
layer.
[0136] Note that the oxide semiconductor layer including the
microcrystalline portion can be formed by heating the surface of
the oxide semiconductor layer by a GRTA process. Further, the oxide
semiconductor layer can be formed in a more preferred manner by
using a sputtering target in which the amount of Zn is smaller than
that of In or Ga.
[0137] The first heat treatment for the oxide semiconductor layer
140 can be performed on the oxide semiconductor layer that has not
yet been processed into the island-shaped oxide semiconductor layer
140. In that case, after the first heat treatment, the substrate is
taken out of the heating apparatus and a photolithography step is
performed.
[0138] Note that the above-described first heat treatment can be
referred to as dehydration treatment, dehydrogenation treatment, or
the like because of its effect of dehydration or dehydrogenation on
the oxide semiconductor layer 140. Such dehydration treatment or
dehydrogenation treatment can be performed, for example, after the
oxide semiconductor layer is formed, after a source electrode and a
drain electrode are stacked over the oxide semiconductor layer 140,
or after a protective insulating layer is formed over the source
and drain electrodes. Such dehydration treatment or dehydrogenation
treatment may be performed once or plural times.
[0139] Next, the source/drain electrode 142a and the source/drain
electrode 142b are formed in contact with the oxide semiconductor
layer 140 (see FIG. 4F). The source/drain electrodes 142a and 142b
can be formed in such a manner that a conductive layer is formed so
as to cover the oxide semiconductor layer 140 and then is
selectively etched.
[0140] The conductive layer can be formed by a PVD method such as a
sputtering method, or a CVD method such as a plasma CVD method. As
a material for the conductive layer, an element selected from
aluminum, chromium, copper, tantalum, titanium, molybdenum, or
tungsten; an alloy containing any of these elements as a component;
or the like can be used. Moreover, one or more materials selected
from manganese, magnesium, zirconium, beryllium, or thorium may be
used. Aluminum combined with one or more of elements selected from
titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or
scandium may be used. The conductive layer can have a single-layer
structure or a layered structure including two or more layers. For
example, the conductive layer can have a single-layer structure of
an aluminum film containing silicon, a two-layer structure in which
a titanium film is stacked over an aluminum film, or a three-layer
structure in which a titanium film, an aluminum film, and a
titanium film are stacked in this order.
[0141] Here, ultraviolet light, KrF laser light, or ArF laser light
is preferably used for light exposure in forming a mask used for
etching.
[0142] The channel length (L) of the transistor is determined by a
distance between a lower edge portion of the source/drain electrode
142a and a lower edge portion of the source/drain electrode 142b.
Note that for light exposure in the case where the channel length
(L) is less than 25 nm, light exposure for forming a mask is
performed with extreme ultraviolet rays whose wavelength is several
nanometers to several hundreds of nanometers, which is extremely
short. The resolution of light exposure with extreme ultraviolet
rays is high and the depth of focus is large. For these reasons,
the channel length (L) of the transistor to be formed later can be
in the range of 10 nm to 1000 nm, and the circuit can operate at
higher speed. Moreover, the off-state current is extremely low,
which prevents power consumption from increasing.
[0143] The materials and etching conditions of the conductive layer
and the oxide semiconductor layer 140 are adjusted as appropriate
so that the oxide semiconductor layer 140 is not removed in etching
of the conductive layer. Note that in some cases, the oxide
semiconductor layer 140 is partly etched in the etching step and
thus has a groove portion (a recessed portion) depending on the
materials and the etching conditions.
[0144] An oxide conductive layer may be formed between the oxide
semiconductor layer 140 and the source/drain electrode 142a and
between the oxide semiconductor layer 140 and the source/drain
electrode 142b. The oxide conductive layer and a metal layer for
forming the source/drain electrodes 142a and 142b can be
successively formed. The oxide conductive layer can function as a
source region and a drain region. The placement of such an oxide
conductive layer can reduce the electrical resistance of the source
region and the drain region, so that the transistor can operate at
high speed.
[0145] In order to reduce the number of masks to be used and reduce
the number of steps, an etching step may be performed with the use
of a resist mask formed using a multi-tone mask which is a
light-exposure mask through which light is transmitted so as to
have a plurality of intensities. A resist mask formed with the use
of a multi-tone mask has a plurality of thicknesses (has a
stair-like shape) and further can be changed in shape by ashing;
therefore, the resist mask can be used in a plurality of etching
steps for processing different patterns. That is, a resist mask
corresponding to at least two of different patterns can be formed
by using a multi-tone mask. Thus, the number of light-exposure
masks can be reduced and the number of corresponding
photolithography steps can also be reduced, whereby a process can
be simplified.
[0146] Note that plasma treatment is preferably performed with the
use of a gas such as N.sub.2O, N.sub.2, or Ar after the above step.
This plasma treatment removes water or the like adsorbed on an
exposed surface of the oxide semiconductor layer. Plasma treatment
may be performed using a mixed gas of oxygen and argon.
[0147] Next, the protective insulating layer 144 is formed in
contact with part of the oxide semiconductor layer 140 without
exposure to the air (see FIG. 4G).
[0148] The protective insulating layer 144 can be formed by a
method by which impurities such as water and hydrogen are prevented
from being mixed to the protective insulating layer 144, such as a
sputtering method, as appropriate. The protective insulating layer
144 has a thickness of 1 nm or more. The protective insulating
layer 144 can be formed using silicon oxide, silicon nitride,
silicon oxynitride, silicon nitride oxide, or the like. The
protective insulating layer 144 can have a single-layer structure
or a layered structure. The substrate temperature in forming the
protective insulating layer 144 is preferably room temperature or
more and 300.degree. C. or less. The atmosphere for forming the
protective insulating layer 144 is preferably a rare gas (typically
argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere
containing a rare gas (typically argon) and oxygen.
[0149] If hydrogen is contained in the protective insulating layer
144, the hydrogen may enter the oxide semiconductor layer or
extract oxygen in the oxide semiconductor layer, whereby the
resistance of the oxide semiconductor layer on the backchannel side
might be decreased and a parasitic channel might be formed.
Therefore, it is important not to use hydrogen in forming the
protective insulating layer 144 so that the oxide insulating layer
144 contains as few hydrogen as possible.
[0150] Moreover, the protective insulating layer 144 is preferably
formed while water left in the treatment chamber is removed, in
order that hydrogen, a hydroxyl group, or water is not contained in
the oxide semiconductor layer 140 and the protective insulating
layer 144.
[0151] A sorption vacuum pump is preferably used in order to remove
moisture remaining in the treatment chamber. A cryopump, an ion
pump, or a titanium sublimation pump can be used. An evacuation
unit may be a turbo pump provided with a cold trap. In the
deposition chamber that is evacuated with the cryopump, a hydrogen
atom and a compound containing a hydrogen atom, such as water
(H.sub.2O), are removed, for example; thus, the impurity
concentration of the protective insulating layer 144 formed in the
deposition chamber can be reduced.
[0152] As a sputtering gas used for forming the protective
insulating layer 144, it is preferable to use a high-purity gas
from which an impurity such as hydrogen, water, a hydroxyl group,
or hydride is reduced so that the concentration is a few ppm
(preferably a few ppb).
[0153] Next, a second heat treatment is preferably performed in an
inert gas atmosphere or an oxygen gas atmosphere (at 200.degree. C.
to 400.degree. C. inclusive, for example, at 250.degree. C. to
350.degree. C. inclusive). For example, the second heat treatment
is performed at 250.degree. C. for one hour in a nitrogen
atmosphere. The second heat treatment can reduce variation in
electric characteristics of the transistor.
[0154] Furthermore, heat treatment may be performed at 100.degree.
C. to 200.degree. C. for one hour to 30 hours in the air. This heat
treatment may be performed at a fixed heating temperature;
alternatively, the following change in the heating temperature may
be conducted plural times repeatedly: the heating temperature is
increased from room temperature to a temperature of 100.degree. C.
to 200.degree. C. inclusive and then decreased to room temperature.
This heat treatment may be performed under a reduced pressure
before the protective insulating layer is formed. The heat
treatment time can be shortened when performed under the reduced
pressure. This heat treatment may be performed instead of the
second heat treatment or may be performed before or after the
second heat treatment, for example.
[0155] Next, the interlayer insulating layer 146 is formed over the
protective insulating layer 144 (see FIG. 5A). The interlayer
insulating layer 146 can be formed by a PVD method, a CVD method,
or the like. The interlayer insulating layer 146 can be formed
using an inorganic insulating material such as silicon oxide,
silicon nitride oxide, silicon nitride, hafnium oxide, aluminum
oxide, or tantalum oxide. After the formation of the interlayer
insulating layer 146, a surface of the interlayer insulating layer
146 is preferably planarized with CMP, etching, or the like.
[0156] Next, openings that reach the electrodes 136a, 136b, and
136c and the source/drain electrodes 142a and 142b are formed in
the interlayer insulating layer 146, the protective insulating
layer 144, and the gate insulating layer 138. Then, a conductive
layer 148 is formed so as to fill the openings (see FIG. 5B). The
openings can be formed by a method such as etching using a mask.
The mask can be formed by a method such as light exposure using a
photomask. Either wet etching or dry etching may be used as the
etching; dry etching is preferably used in terms of
microfabrication. The conductive layer 148 can be formed by a film
formation method such as a PVD method or a CVD method. The
conductive layer 148 can be formed using a conductive material such
as molybdenum, titanium, chromium, tantalum, tungsten, aluminum,
copper, neodymium, or scandium or an alloy or a compound (e.g., a
nitride) of any of these materials, for example.
[0157] Specifically, it is possible to employ a method, for
example, in which a thin titanium film is formed in a region
including the openings by a PVD method and a thin titanium nitride
film is formed by a CVD method, and then, a tungsten film is formed
so as to fill the openings. Here, the titanium film formed by a PVD
method has a function of reducing an oxide film at the interface
with the interlayer insulating layer 146 to decrease the contact
resistance with lower electrodes (here, the electrodes 136a, 136b,
and 136c and the source/drain electrodes 142a and 142b). The
titanium nitride film formed after the formation of the titanium
film has a barrier function of preventing diffusion of the
conductive material. A copper film may be formed by a plating
method after the formation of the barrier film of titanium,
titanium nitride, or the like.
[0158] After the conductive layer 148 is formed, part of the
conductive layer 148 is removed by etching, CMP, or the like, so
that the interlayer insulating layer 146 is exposed and the
electrodes 150a, 150b, 150c, 150d, and 150e are formed (see FIG.
5C). Note that when the electrodes 150a, 150b, 150c, 150d, and 150e
are formed by removing part of the conductive layer 148, the
process is preferably performed so that the surfaces are
planarized. The surfaces of the interlayer insulating layer 146 and
the electrodes 150a, 150b, 150c, 150d, and 150e are planarized in
such a manner that an electrode, a wiring, an insulating layer, a
semiconductor layer, and the like can be favorably formed in later
steps.
[0159] Then, the insulating layer 152 is formed, and openings that
reach the electrodes 150a, 150b, 150c, 150d, and 150e are formed in
the insulating layer 152. After a conductive layer is formed so as
to fill the openings, part of the conductive layer is removed by
etching, CMP, or the like. Thus, the insulating layer 152 is
exposed and the electrodes 154a, 154b, 154c, and 154d are formed
(see FIG. 5D). This step is similar to the step of forming the
electrode 150a and the like; therefore, the detailed description is
not repeated.
[0160] In the case where the transistor 162 is formed by the
above-described method, the hydrogen concentration of the oxide
semiconductor layer 140 is 5.times.10.sup.19 atoms/cm.sup.3 or less
and the off-state current of the transistor 162 is
1.times.10.sup.-13 A or less. The transistor 162 with excellent
characteristics can be obtained by the application of the oxide
semiconductor layer 140 that is highly purified by a sufficient
reduction in hydrogen concentration as described above. Moreover,
it is possible to manufacture a semiconductor device that has
excellent characteristics and includes the transistor 160 formed
using a material which is not an oxide semiconductor in the lower
portion and the transistor 162 formed using an oxide semiconductor
in the upper portion.
[0161] Note that silicon carbide (e.g., 4H-SiC) is given as a
semiconductor material which can be compared with an oxide
semiconductor. An oxide semiconductor and 4H-SiC have some common
properties. The carrier density is one of them. The density of
intrinsic carriers in an oxide semiconductor at room temperature is
estimated to be approximately 10.sup.-7/cm.sup.3, while that in
4H-SiC, 6.7.times.10.sup.-11/cm.sup.3, an extremely small value
compared to other semiconductors. For example, when the intrinsic
carrier density of an oxide semiconductor is compared with the
intrinsic carrier density of silicon (approximately
1.4.times.10.sup.10/cm.sup.3), it can be understood well that the
intrinsisc carrier density of an oxide semiconductor is
significantly low.
[0162] Further, the energy band gap of an oxide semiconductor is
3.0 eV to 3.5 eV and the energy band gap of 4H-SiC is 3.26 eV.
Thus, an oxide semiconductor and silicon carbide are similar in
that they are both wide-gap semiconductors.
[0163] On the other hand, there is a major difference between an
oxide semiconductor and silicon carbide, the process temperature.
Since silicon carbide generally needs to be subjected to heat
treatment at 1500.degree. C. to 2000.degree. C., it is difficult to
form a stack of silicon carbide and a semiconductor element formed
using a semiconductor material which is not silicon carbide. This
is because a semiconductor substrate, the semiconductor element, or
the like is damaged at such high temperatures. Meanwhile, an oxide
semiconductor can be formed by heat treatment at 300.degree. C. to
500.degree. C. (lower than a glass transition temperature of some
glasses, up to about 700.degree. C. at most); therefore, it is
possible to form an integrated circuit with the use of a
semiconductor material which is not an oxide semiconductor and then
to form a semiconductor element including an oxide
semiconductor.
[0164] In addition, in contrast to silicon carbide, an oxide
semiconductor is advantageous because a low heat-resistant
substrate such as a glass substrate can be used. Moreover, an oxide
semiconductor does not need to be subjected to heat treatment at
high temperature, so that energy cost can be reduced as compared to
silicon carbide, which is another advantage.
[0165] Although a lot of researches on properties of an oxide
semiconductor have been conducted, they do not include the idea of
substantially reducing the density of localized energy levels
itself in an energy gap. According to an embodiment of the
disclosed invention, a highly purified oxide semiconductor is
formed by removing water or hydrogen that can be a cause of a
localized energy level. This is based on the idea of reducing
substantially a localized level itself in an energy gap. Such a
highly purified oxide semiconductor enables fabrication of
outstanding industrial products.
[0166] Further, it is also possible to form a more highly purified
(i-type) oxide semiconductor by supplying oxygen to dangling bonds
of metal atoms, the dangling bonds being generated by oxygen
vacancies, and thus reducing localized levels density due to the
oxygen vacancy. For example, an oxide film containing oxygen in
excess is formed in close contact with a channel formation region
and then oxygen is supplied to the channel formation region from
the oxide film, so that the localized levels density due to oxygen
vacancy can be reduced.
[0167] The origin of donors in an oxide semiconductor is attributed
to a shallow level of 0.1 eV to 0.2 eV under the conduction band
due to hydrogen in excess, a deep level due to shortage of oxygen,
or the like. Thorough removal of hydrogen and substantial supply of
oxygen for elimination of such defects would be a proper
technological thought.
[0168] An oxide semiconductor is generally considered as an n-type
semiconductor;
[0169] however, according to one embodiment of the invention
disclosed herein, an i-type semiconductor is realized by removing
impurities, particularly water and hydrogen. In this respect, it
can be said that one embodiment of the invention disclosed herein
includes a novel technical idea because it is different from usual
i-type semiconductors, such as silicon, in that they are obtained
by addition of an impurity.
[0170] <Electrical Conduction Mechanism of Transistor Including
Oxide Semiconductor>
[0171] An electrical conduction mechanism of a transistor including
an oxide semiconductor will be described with reference to FIG. 22,
FIGS. 23A and 23B, FIGS. 24A and 24B, and FIG. 25. Note that the
following description is just a consideration and does not
contradict the validity of the invention.
[0172] FIG. 22 is a longitudinal cross-sectional view of a
dual-gate transistor (thin film transistor) including an oxide
semiconductor. An oxide semiconductor layer (OS) is provided over a
gate electrode layer (GE) with a gate insulating layer (GI)
therebetween, and a source electrode (S) and a drain electrode (D)
are formed thereover.
[0173] FIGS. 23A and 23B are schematic diagrams of energy band
structures along A-A' in FIG. 22. FIG. 23B illustrates the case
where a positive voltage (V.sub.D>0) is applied to a drain and a
voltage is not applied to a gate (V.sub.G=0) (shown by dashed
lines) and the case where a positive voltage (V.sub.D>0) is
applied to the drain and a positive voltage (V.sub.G>0) is
applied to the gate (shown by solid lines). In the case where a
voltage is not applied to the gate, a carrier (electron) is not
injected to the oxide semiconductor side from an electrode because
of a high potential barrier, so that a current does not flow, which
means an off state. On the other hand, when a positive voltage is
applied to the gate, the potential barrier is lowered and thus a
current flows, which means an on state.
[0174] FIGS. 24A and 24B are energy band diagrams (schematic
diagrams) along B-B' in FIG. 22. FIG. 24A illustrates a state where
a positive voltage +V.sub.G (V.sub.G>0) is applied to the gate
(GE), that is, an on state where a carrier (electron) flows between
a source and a drain. FIG. 24B illustrates a state where a negative
voltage -V.sub.G (V.sub.G>0) is applied to the gate (GE), that
is, an off state (where a minority carrier does not flow).
[0175] FIG. 25 illustrates the relation between the vacuum level,
the work function of metal (.phi..sub.M), and the electron affinity
of an oxide semiconductor (.chi.).
[0176] Metal degenerates and the Fermi level exists in the
conduction band. Meanwhile, a conventional oxide semiconductor is
n-type, and the Fermi level (E) is distant from the intrinsic Fermi
level (E.sub.i) in the center of the band gap and is located near
the conduction band. It is known that hydrogen in an oxide
semiconductor partly becomes a donor and is one of the causes
leading to obtention of an n-type oxide semiconductor.
[0177] In contrast, an oxide semiconductor according to an
embodiment of the disclosed invention is an oxide semiconductor
that is made to be intrinsic (i-type) or to be close to intrinsic
in the following manner: hydrogen, which is a cause of obtaining an
n-type oxide semiconductor, is removed from the oxide semiconductor
by high purification, so that the oxide semiconductor includes as
few an element (impurity element) other than the main component of
the oxide semiconductor as possible. That is, a feature of an
embodiment of the present invention is that an oxide semiconductor
is made to be or be close to a highly-purified i-type (intrinsic)
semiconductor not by addition of an impurity element but by
elimination, as much as possible, of impurities such as hydrogen
and water. Thus, the Fermi level (E.sub.f) can be comparable with
the intrinsic Fermi level (E.sub.i).
[0178] The band gap (E.sub.g) and the electron affinity (.chi.) of
an oxide semiconductor are said to be 3.15 eV and 4.3 eV,
respectively. The work function of titanium (Ti) contained in a
source electrode or a drain electrode is substantially equal to the
electron affinity (.chi.) of an oxide semiconductor. In this case,
a Schottky barrier against an electron is not formed at the
interface between metal and an oxide semiconductor.
[0179] That is to say, in the case where the work function of metal
(.phi..sub.M) is equal to the electron affinity of an oxide
semiconductor (.chi.), such an energy band diagram (schematic
diagram) in FIG. 23A is shown when the metal and the oxide
semiconductor are in contact with each other.
[0180] In FIG. 23B, a black dot (.circle-solid.) indicates an
electron. When a positive potential is supplied to the drain, the
electron crosses over a barrier (of height h) to be injected into
the oxide semiconductor, and flows to the drain. The height of the
barrier (h) depends on a gate voltage and a drain voltage. When a
positive drain voltage is applied, the height of the barrier (h) is
lower than the height of the barrier in FIG. 23A where a voltage is
not applied, that is, half the band gap (E.sub.g).
[0181] At that time, as illustrated in FIG. 24A, the electron
travels in the vicinity of the interface between a gate insulating
layer and the highly-purified oxide semiconductor (the bottom
portion where the oxide semiconductor is stable in terms of
energy).
[0182] As illustrated in FIG. 24B, when a negative potential is
supplied to the gate electrode (GE), a hole which is a minority
carrier does not exist substantially. Thus, the current value is
substantially close to 0.
[0183] In such a manner, the oxide semiconductor layer becomes
intrinsic (an i-type semiconductor) or substantially intrinsic by
being highly purified so as to contain as few of an element other
than its main element (i.e., an impurity element) as possible.
Thus, characteristics of the interface between the oxide
semiconductor and the gate insulating layer become obvious. For
that reason, the gate insulating layer needs to form a favorable
interface with the oxide semiconductor. Specifically, it is
preferable to use the following insulating layer, for example: an
insulating layer formed by a CVD method using high-density plasma
generated with a power supply frequency in the range of the VHF
band to the microwave band, or an insulating layer formed by a
sputtering method.
[0184] When the interface between the oxide semiconductor and the
gate insulating layer is made favorable while the oxide
semiconductor is highly purified, in the case where the transistor
has a channel width W of 1.times.10.sup.4 .mu.m and a channel
length L of 3 .mu.m, for example, it is possible to realize an
off-state current of 1.times.10.sup.-13 A or less and a
subthreshold swing (S value) of 0.1 V/dec at room temperature (with
a 100-nm-thick gate insulating layer).
[0185] The oxide semiconductor is highly purified as described
above so as to contain an element other than its main element
(i.e., an impurity element) as little as possible, so that the thin
film transistor can operate in a favorable manner.
Modification Example
[0186] FIG. 6, FIGS. 7A and 7B, FIGS. 8A and 8B, and FIGS. 9A and
9B illustrate modification examples of structures of semiconductor
devices. The semiconductor devices in each of which the transistor
162 has a structure different from that described above will be
described below as modification examples. That is, the structure of
the transistor 160 is the same as the above.
[0187] FIG. 6 illustrates an example of a semiconductor device
including the transistor 162 in which the gate electrode 136d is
placed below the oxide semiconductor layer 140 and the source/drain
electrodes 142a and 142b are in contact with a bottom surface of
the oxide semiconductor layer 140. Note that the planar structure
can be changed as appropriate to correspond to the cross section;
therefore, only the cross section is shown here.
[0188] A big difference between the structure in FIG. 6 and the
structure in FIG. 2A is the position at which the oxide
semiconductor layer 140 is connected to the source/drain electrodes
142a and 142b. That is, a top surface of the oxide semiconductor
layer 140 is in contact with the source/drain electrodes 142a and
142b in the structure in FIG. 2A, whereas the bottom surface of the
oxide semiconductor layer 140 is in contact with the source/drain
electrodes 142a and 142b in the structure in FIG. 6. Moreover, the
difference in the contact position results in a different
arrangement of other electrodes, an insulating layer, and the like.
The details of each component are the same as those of FIGS. 2A and
2B.
[0189] Specifically, the semiconductor device illustrated in FIG. 6
includes the gate electrode 136d provided over the interlayer
insulating layer 128, the gate insulating layer 138 provided over
the gate electrode 136d, the source/drain electrodes 142a and 142b
provided over the gate insulating layer 138, and the oxide
semiconductor layer 140 in contact with top surfaces of the
source/drain electrodes 142a and 142b.
[0190] Here, the gate electrode 136d is provided so as to be
embedded in the insulating layer 132 formed over the interlayer
insulating layer 128. Like the gate electrode 136d, the electrode
136a, the electrode 136b, and the electrode 136c are formed in
contact with the source/drain electrode 130a, the source/drain
electrode 130b, and the electrode 130c, respectively.
[0191] The protective insulating layer 144 is provided over the
transistor 162 so as to be in contact with part of the oxide
semiconductor layer 140. The interlayer insulating layer 146 is
provided over the protective insulating layer 144. Openings that
reach the source/drain electrode 142a and the source/drain
electrode 142b are formed in the protective insulating layer 144
and the interlayer insulating layer 146. The electrode 150d and the
electrode 150e are formed in contact with the source/drain
electrode 142a and the source/drain electrode 142b, respectively,
through the respective openings. Like the electrodes 150d and 150e,
the electrodes 150a, 150b, and 150c are formed in contact with the
electrodes 136a, 136b, and 136c, respectively, through openings
provided in the gate insulating layer 138, the protective
insulating layer 144, and the interlayer insulating layer 146.
[0192] The insulating layer 152 is provided over the interlayer
insulating layer 146. The electrodes 154a, 154b, 154c, and 154d are
provided so as to be embedded in the insulating layer 152. The
electrode 154a is in contact with the electrode 150a. The electrode
154b is in contact with the electrode 150b. The electrode 154c is
in contact with the electrode 150c and the electrode 150d. The
electrode 154d is in contact with the electrode 150e.
[0193] FIGS. 7A and 7B each illustrate an example of a structure of
a semiconductor device in which the gate electrode 136d is placed
over the oxide semiconductor layer 140. FIG. 7A illustrates an
example of a structure in which the source/drain electrodes 142a
and 142b are in contact with a bottom surface of the oxide
semiconductor layer 140. FIG. 7B illustrates an example of a
structure in which the source/drain electrodes 142a and 142b are in
contact with a top surface of the oxide semiconductor layer
140.
[0194] A big difference between the structures in FIGS. 7A and 7B
and those in FIG. 2A and FIG. 6 is that the gate electrode 136d is
placed over the oxide semiconductor layer 140. Furthermore, a big
difference between the structure in FIG. 7A and the structure in
FIG. 7B is that the source/drain electrodes 142a and 142b are in
contact with either the bottom surface or the top surface of the
oxide semiconductor layer 140. Moreover, these differences result
in a different arrangement of other electrodes, an insulating
layer, and the like. The details of each component are the same as
those of FIGS. 2A and 2B, and the like.
[0195] Specifically, the semiconductor device illustrated in FIG.
7A includes the source/drain electrodes 142a and 142b provided over
the interlayer insulating layer 128, the oxide semiconductor layer
140 in contact with top surfaces of the source/drain electrodes
142a and 142b, the gate insulating layer 138 provided over the
oxide semiconductor layer 140, and the gate electrode 136d over the
gate insulating layer 138 in a region overlapping with the oxide
semiconductor layer 140.
[0196] The semiconductor device illustrated in FIG. 7B includes the
oxide semiconductor layer 140 provided over the interlayer
insulating layer 128, the source/drain electrodes 142a and 142b
provided to be in contact with a top surface of the oxide
semiconductor layer 140, the gate insulating layer 138 provided
over the oxide semiconductor layer 140 and the source/drain
electrodes 142a and 142b, and the gate electrode 136d over the gate
insulating layer 138 in a region overlapping with the oxide
semiconductor layer 140.
[0197] Note that in the structures in FIGS. 7A and 7B, a component
(e.g., the electrode 150a or the electrode 154a) can sometimes be
omitted from the structure in FIGS. 2A and 2B or the like. In this
case, a secondary effect such as simplification of a manufacturing
process can be obtained. It is needless to say that a nonessential
component can be omitted in the structures in FIGS. 2A and 2B and
the like.
[0198] FIGS. 8A and 8B each illustrate an example of the case where
the size of the element is relatively large and the gate electrode
136d is placed below the oxide semiconductor layer 140. In this
case, a demand for the planarity of a surface and the coverage is
relatively moderate, so that it is not necessary to form a wiring,
an electrode, and the like to be embedded in an insulating layer.
For example, the gate electrode 136d and the like can be formed by
patterning after formation of a conductive layer. Note that
although not illustrated here, the transistor 160 can be formed in
a similar manner.
[0199] A big difference between the structure in FIG. 8A and the
structure in FIG. 8B is that the source/drain electrodes 142a and
142b are in contact with either the bottom surface or the top
surface of the oxide semiconductor layer 140. Moreover, these
differences result in other electrodes, an insulating layer, and
the like being arranged in a different manner. The details of each
component are the same as those of FIGS. 2A and 2B, and the
like.
[0200] Specifically, the semiconductor device illustrated in FIG.
8A includes the gate electrode 136d provided over the interlayer
insulating layer 128, the gate insulating layer 138 provided over
the gate electrode 136d, the source/drain electrodes 142a and 142b
provided over the gate insulating layer 138, and the oxide
semiconductor layer 140 in contact with top surfaces of the
source/drain electrodes 142a and 142b.
[0201] The semiconductor device illustrated in FIG. 8B includes the
gate electrode 136d provided over the interlayer insulating layer
128, the gate insulating layer 138 provided over the gate electrode
136d, the oxide semiconductor layer 140 provided over the gate
insulating layer 138 overlapping with the gate electrode 136d, and
the source/drain electrodes 142a and 142b provided to be in contact
with a top surface of the oxide semiconductor layer 140.
[0202] Note that also in the structures in FIGS. 8A and 8B, a
component can sometimes be omitted from the structure in FIGS. 2A
and 2B or the like. Also in this case, a secondary effect such as
simplification of a manufacturing process can be obtained.
[0203] FIGS. 9A and 9B each illustrate an example of the case where
the size of the element is relatively large and the gate electrode
136d is placed over the oxide semiconductor layer 140. Also in this
case, a demand for the planarity of a surface and the coverage is
relatively moderate, so that it is not necessary to form a wiring,
an electrode, and the like to be embedded in an insulating layer.
For example, the gate electrode 136d and the like can be formed by
patterning after formation of a conductive layer. Note that
although not illustrated here, the transistor 160 can be formed in
a similar manner.
[0204] A big difference between the structure in FIG. 9A and the
structure in FIG. 9B is that the source/drain electrodes 142a and
142b are in contact with either the bottom surface or the top
surface of the oxide semiconductor layer 140. Moreover, this
difference results in other electrodes, an insulating layer, and
the like being arranged in a different manner. The details of each
component are the same as those of FIGS. 2A and 2B, and the
like.
[0205] Specifically, the semiconductor device illustrated in FIG.
9A includes the source/drain electrodes 142a and 142b provided over
the interlayer insulating layer 128, the oxide semiconductor layer
140 in contact with top surfaces of the source/drain electrodes
142a and 142b, the gate insulating layer 138 provided over the
source/drain electrodes 142a and 142b and the oxide semiconductor
layer 140, and the gate electrode 136d provided over the gate
insulating layer 138 in a region overlapping with the oxide
semiconductor layer 140.
[0206] The semiconductor device illustrated in FIG. 9B includes the
oxide semiconductor layer 140 provided over the interlayer
insulating layer 128, the source/drain electrodes 142a and 142b
provided to be in contact with a top surface of the oxide
semiconductor layer 140, the gate insulating layer 138 provided
over the source/drain electrodes 142a and 142b and the oxide
semiconductor layer 140, and the gate electrode 136d provided over
the gate insulating layer 138 in a region overlapping with the
oxide semiconductor layer 140.
[0207] Note that also in the structures in FIGS. 9A and 9B, a
component can sometimes be omitted from the structure in FIGS. 2A
and 2B or the like. Also in this case, a secondary effect such as
simplification of a manufacturing process can be obtained.
[0208] As described above, a semiconductor device with a novel
structure can be realized according to one embodiment of the
invention disclosed herein. In this embodiment, the examples in
each of which the semiconductor device is formed by stacking the
transistor 160 and the transistor 162 are described; however, the
structure of the semiconductor device is not limited to this
structure. Moreover, this embodiment shows the examples in each of
which the channel length direction of the transistor 160 is
perpendicular to that of the transistor 162; however, the
positional relation between the transistors 160 and 162 is not
limited to this example. In addition, the transistor 160 and the
transistor 162 may be provided to overlap with each other.
[0209] In this embodiment, the semiconductor device with a minimum
storage unit (one bit) is described for simplification; however,
the structure of the semiconductor device is not limited thereto. A
more advanced semiconductor device can be formed by connecting a
plurality of semiconductor devices as appropriate. For example, a
NAND-type or NOR-type semiconductor device can be formed by using a
plurality of the above-described semiconductor devices. The wiring
configuration is not limited to that in FIG. 1 and can be changed
as appropriate.
[0210] The semiconductor device according to this embodiment can
store data for an extremely long time because the transistor 162
has low off-state current. That is, refresh operation which is
necessary in a DRAM and the like is not needed, so that power
consumption can be suppressed. Moreover, the semiconductor device
according to this embodiment can be used as a substantially
non-volatile memory device.
[0211] Since writing or the like of data is performed with
switching operation of the transistor 162, high voltage is not
necessary and deterioration of the element does not become a
problem. Furthermore, data is written and erased depending on on
state and off state of the transistor, whereby high-speed operation
can be easily realized. In addition, it is possible to rewrite data
directly by controlling a potential input to the transistor.
Therefore, erasing operation which is necessary in a flash memory
and the like is not necessary in the present invention, so that a
reduction in operation speed because of erasing operation can be
prevented.
[0212] Since a transistor including a material which is not an
oxide semiconductor can operate at further high speed in comparison
with a transistor including an oxide semiconductor, stored data can
be read out at high speed by using the transistor including a
material which is not an oxide semiconductor.
[0213] The structures and methods described in this embodiment can
be combined as appropriate with any of the structures and methods
described in the other embodiments.
Embodiment 2
[0214] In this embodiment, a circuit configuration of a
semiconductor device according to one embodiment of the present
invention and an operation method thereof will be described.
[0215] FIG. 10 illustrates an example of a circuit diagram of a
memory element (hereinafter, also referred to as a memory cell)
included in the semiconductor device. A memory cell 200 illustrated
in FIG. 10 includes a third wiring S1 (a first signal line), a
fourth wiring S2 (a second signal line), a fifth wiring WL (a word
line), a transistor 201, a transistor 202, and a transistor 203.
The transistor 201 and the transistor 203 are formed using a
material which is not an oxide semiconductor and the transistor 202
is formed using an oxide semiconductor. Here, the transistor 201
and the transistor 203 are preferably formed to have a structure
similar to that of the transistor 160 in Embodiment 1. In addition,
the transistor 202 is preferably formed to have a structure similar
to that of the transistor 162 in Embodiment 1. Further, the memory
cell 200 is electrically connected to the first wiring SL (the
source line) and the second wiring BL (the bit line), preferably
through a transistor (including a transistor included in another
memory cell).
[0216] Here, a gate electrode of the transistor 201 is electrically
connected to one of a source electrode and a drain electrode of the
transistor 202. In addition, the first wiring SL is electrically
connected to a source electrode of the transistor 201 and a source
electrode of the transistor 203, and the second wiring BL is
electrically connected to a drain electrode of the transistor 201
and a drain electrode of the transistor 203. Moreover, the third
wiring S1, the fourth wiring S2, and the fifth wiring WL are
electrically connected to the other of the source electrode and the
drain electrode of the transistor 202, a gate electrode of the
transistor 202, and a gate electrode of the transistor 203,
respectively. Note that the first wiring SL may be electrically
connected to the source electrode of the transistor 201 and to a
source electrode of the transistor 203 through a transistor
(including a transistor in another memory cell). Furthermore, the
second wiring BL may be electrically connected to the drain
electrode of the transistor 201 and to the drain electrode of the
transistor 203 through a transistor (including a transistor in
another memory cell).
[0217] FIG. 11 illustrates a block circuit diagram of a
semiconductor device according to one embodiment of the present
invention, which includes m.times.n bits of memory capacitance.
Here, as an example, a NAND semiconductor device in which the
memory cells 200 are connected in series is shown.
[0218] The semiconductor device according to one embodiment of the
present invention includes m fifth wirings WL(1) to W(m), m fourth
wirings S2(1) to S2(m), n first wirings SL(1) to SL(n), n second
wirings BL(1) to BL(n), n third wirings S1(1) to S1(n), two sixth
wirings SEL(1) and SEL(2), a memory cell array 210 in which a
plurality of memory cells 200 (1, 1) to 200 (m, n) are provided in
matrix of m rows (horizontal) and n columns (vertical) (m and n are
natural numbers), transistors 215 (1, 1) to 215 (1, n) provided
respectively between the second wirings BL(1) to BL(n) and the
memory cells 200 (1, 1) to 200 (1, n) along the sixth wiring
SEL(1), transistors 215 (2, 1) to 215 (2, n) provided respectively
between the first wirings SL(1) to SL(n) and the memory cells 200
(m, 1) to 200 (m, n) along the sixth wiring SEL(2), and peripheral
circuits such as a driver circuit 211 of the second wiring and the
third wiring, a driver circuit 213 of the fourth wiring and the
fifth wiring, and a reading circuit 212. A refresh circuit or the
like may be provided as another peripheral circuit.
[0219] Each memory cell 200 (a specific example of which is the
memory cell 200 (i, j), where i is an integer of 1 or more and m or
less, and j is an integer of 1 or more and n or less) is connected
to the third wiring S1(j), the fourth wiring S2(i), and the fifth
wiring WL(i). Further, the drain electrodes of the transistors 201
and 203 included in the memory cell 200 (i.sub.1, j) (i.sub.1 is an
integer of 2 to m) are connected to the source electrodes of the
transistors 201 and 203 included in the memory cell 200 (i.sub.j-1,
j). In addition, the source electrodes of the transistors 201 and
203 included in the memory cell 200 (i.sub.2, j) (i.sub.2 is an
integer of 1 to m-1) are connected to the drain electrodes of the
transistors 201 and 203 included in the memory cell 200 (i.sub.2+1,
j). The drain electrodes of the transistors 201 and 203 included in
the memory cell 200 (1, j) are connected to a source electrode of
the transistor 215 (1, j). The source electrodes of the transistors
201 and 203 included in the memory cell 200 (m, j) are connected to
a drain electrode of the transistor 215 (2, j). The drain electrode
of the transistor 215 (1, j) is connected to the second wiring
BL(j). The source electrode of the transistor 215 (2, j) is
connected to the first wiring SL(j). A gate electrode of the
transistor 215 (1, j) is connected to the sixth wiring SEL(1). The
gate electrode of the transistor 215 (2, j) is connected to the
sixth wiring SEL(2).
[0220] Further, the second wirings BL(1) to BL(n) and the third
wirings S1(1) to S1(n) are connected to the driver circuit 211 of
the second wiring and the third wiring. The fifth wirings WL(1) to
WL(m), the fourth wirings S2(1) to S2(m), and the sixth wirings
SEL(1) and SEL(2) are connected to the driver circuit 213 of the
fourth wiring and the fifth wiring. In addition, the second wirings
BL(1) to BL(n) are also connected to the reading circuit 212. A
potential Vs is supplied to the first wirings SL(1) to SL(n). Note
that the first wirings SL(1) to SL(n) are not necessarily separated
and may be connected to each other.
[0221] The operation of the semiconductor device illustrated in
FIG. 11 will be described. In this structure, writing and reading
are performed by row.
[0222] When writing is performed on the memory cells 200 (i, 1) to
200 (i, n) in the i-th row, the fourth wiring S2(i) is supplied
with 2 V in order to turn on the transistors 202 of the selected
memory cells. On the other hand, the fourth wirings S2 except the
fourth wiring S2(i) are supplied with 0 V in order to turn off the
transistors 202 of the non-selected memory cells. Among the third
wirings S1(1) to S1(n), a wiring of a column through which data "1"
is written is supplied with 2 V while a column through which data
"0" is supplied with 0 V. Note that, to finish writing, the fourth
wiring S2(i) is supplied with 0 V before the potentials of the
third wirings S1(1) to S1(n) are changed, so that the transistors
202 of the selected memory cells are turned off. As for the other
wirings, for example, the potentials of the second wirings BL(1) to
BL(n), the potentials of the fifth wirings WL(1) to WL (m), the
potentials of the sixth wirings SEL(1) and SEL(2), and the
potential Vs of the first wirings SL(1) to SL(n) are set to 0. An
example of a timing chart of writing operation is illustrated in
FIG. 12.
[0223] As a result, the potential of a node (hereinafter, referred
to as a node A) connected to the gate electrode of the transistor
201 of the memory cell to which the data "1" has been written is
approximately 2 V, and the potential of the node A of the memory
cell to which the data "0" has been written is approximately 0 V.
The potential of the node A of the non-selected memory cell is not
changed. Here, the off-state current of the transistor 202 is
extremely small or substantially zero, so that the potential of the
gate electrode of the transistor 201 (node A) is held for a long
time.
[0224] When reading is performed on the memory cells 200 (i, 1) to
200 (i, n) in the i-th row, the sixth wirings SEL(1) and SEL(2) are
supplied with 2 V in order to turn on the transistors 215 (1, 1) to
215 (2, n). The potential Vs of the first wirings SL(1) to SL(n) is
set to 0. The reading circuit 212 connected to the second wirings
BL(1) to BL(n) is set to operate. The fourth wirings S2(1) to S2(m)
are supplied with 0 V in order to turn off the all of the
transistors 202 of the memory cells. The third wirings S1(1) to
S1(n) are supplied with 0 V.
[0225] Then, the fifth wiring WL(i) is supplied with 0 V, and the
fifth wirings WL except the fifth wiring WL(i) are supplied with 2
V. At this time, the transistors 203 of the memory cells in the
i-th row are turned off. The transistors 203 of the memory cells
which are not in the i-th row are turned on. As a result, the
resistance state of the column of memory cells is determined by
whether the state of the transistor 201 of the memory cells in the
i-th row is in an on state or an off state. In the memory cell
which has the data "0" in the i-th row, the transistor 201 is
turned off because the node A is supplied with approximately 0 V;
therefore, the resistance of the memory cell column is high
(hereinafter, also referred to as "the memory cell column is in a
high-resistance state"). On the other hand, in the memory cell
which has the data in the i-th row, the transistor 201 is turned on
because the node A is supplied with approximately 2 V; therefore,
the resistance of the memory cell column is low (hereinafter, also
referred to as "the memory cell column is in a low-resistance
state"). As a result, the reading circuit can read the data "0" and
"1" by difference of the resistance states of the memory cells.
[0226] Note that in writing, in the case where the semiconductor
device does not have a substrate potential such as the case where
thin film transistor is formed over an SOI substrate, it is
preferable that the fifth wirings WL(i+1) to WL(m) and the sixth
wiring SEL(2) be supplied with 2 V. Thus, at least one of the
source electrode and the drain electrode of the transistor 201 of
the memory cell in the i-th row can be supplied with approximately
0 V. Alternatively, the sixth wiring SEL(1) and the fifth wirings
WL(1) to WL(i-1) can be supplied with 2 V. On the other hand, in
the case where the semiconductor device has a substrate potential
such as the case where a transistor is formed over a single crystal
semiconductor substrate, the substrate potential may be set to be 0
V.
[0227] Note that the second wirings BL(1) to BL(n) are supplied
with 0 V in writing in the above description; however, the second
wirings BL(1) to BL(n) may be in a floating state or charged to
have a potential of 0 V or more in the case where the sixth wiring
SEL(1) is supplied with 0 V. The third wirings S1(1) to S1(n) are
supplied with 0 V in reading; however, the third wirings S1(1) to
S1(n) may be in a floating state or charged to have a potential of
0 V or more.
[0228] Note that the data "1" and the data "0" are defined for
convenience and can be reversed. In addition, the above operation
voltages are an example. An operation voltage may be determined so
that the transistor 201 is in an off state when the data "0" is set
to and in an on state when the data "1" is set to, so that the 202
is in an on state in writing and in an off state otherwise, or so
that the transistor 203 of the selected memory cell is in an off
state in reading, and the transistor 203 of the non-selected memory
cell is in an on state in reading. The power supply potential VDD
of the peripheral logic circuit may be used instead of 2 V. In
addition, the ground potential GND may be used instead of 0 V.
[0229] Next, another example of a circuit configuration of a
semiconductor device according to one embodiment of the present
invention and operation thereof will be described.
[0230] FIG. 13 illustrates an example of a memory cell circuit
included in a semiconductor device. A memory cell 220 in FIG. 13
includes the third wiring S1, the fourth wiring S2, the fifth
wiring WL, the transistor 201, the transistor 202, and the
transistor 203. The transistor 201 and the transistor 203 are
formed using a material which is not an oxide semiconductor and the
transistor 202 is formed using an oxide semiconductor. Here, the
transistor 201 and the transistor 203 are preferably formed to have
a structure similar to that of the transistor 160 in Embodiment 1.
In addition, the transistor 202 is preferably formed to have a
structure similar to that of the transistor 162 in Embodiment 1.
Further, it is preferable that the memory cell 220 be electrically
connected to the first wiring SL and the second wiring BL through a
transistor (including a transistor in another memory cell).
[0231] The memory cell circuit in FIG. 13 is different from the
memory cell circuit in FIG. 10 in the directions of the third
wiring S1 and the fourth wiring S2. In other words, the memory cell
circuit in FIG. 13 has a structure in which the fourth wiring S2
and the third wiring S1 are provided along the second wiring BL (in
a column direction) and the fifth wiring WL (in a row direction),
respectively.
[0232] FIG. 14 illustrates a block circuit diagram of a
semiconductor device according to one embodiment of the present
invention, which includes m.times.n bits of memory capacitance.
Here, as an example, a NAND semiconductor device in which the
memory cells 220 are connected in series is shown.
[0233] The semiconductor device according to one embodiment of the
present invention includes m fifth wirings WL, m third wirings S1,
n first wirings SL, n second wirings BL, n fourth wirings S1, two
sixth wirings SEL, a memory cell array 230 in which a plurality of
memory cells 220 (1, 1) to 220 (m, n) are provided in matrix of m
rows (horizontal) and n columns (vertical) (m and n are natural
numbers), transistors 235 (1, 1) to 235 (1, n) provided between the
second wirings BL(1) to BL(n) and the memory cells 220 (1, 1) to
220 (1, n) along the sixth wiring SEL(1), transistors 235 (2, 1) to
235 (2, n) provided between the first wirings SL(1) to SL(n) and
the memory cells 220 (m, 1) to 220 (m, n) along the sixth wiring
SEL(2), and peripheral circuits such as a driver circuit 231 of the
second wiring and the fourth wiring, a driver circuit 213 of the
third wiring and the fifth wiring, and a reading circuit 232. A
refresh circuit or the like may be provided as another peripheral
circuit.
[0234] The semiconductor device in FIG. 14 is different from the
semiconductor device in FIG. 11 in the directions of the third
wiring S1 and the fourth wiring S2. In other words, semiconductor
device in FIG. 14 has a structure in which the fourth wiring S2 and
the third wiring S1 are provided along the second wiring BL (in a
column direction) and the fifth wiring WL (in a row direction),
respectively.
[0235] Each memory cell 220 (a specific example of which is the
memory cell 220 (i, j), where i is an integer of 1 or more and m or
less, and j is an integer of 1 or more and n or less) is connected
to the third wiring S1(i), the fifth wiring WL(i), and the fourth
wiring S2(j). Further, the drain electrodes of the transistors 201
and 203 included in the memory cell 220 (i.sub.1, j) (i.sub.1 is an
integer of 2 to m) are connected to the source electrodes of the
transistors 201 and 203 included in the memory cell 220 (i.sub.1-1,
j). In addition, the source electrodes of the transistors 201 and
203 included in the memory cell 220 (i.sub.2, j) (i.sub.2 is an
integer of 1 to m-1) are connected to the drain electrodes of the
transistors 201 and 203 included in the memory cell 220 (i.sub.2+1,
j). The drain electrodes of the transistors 201 and 203 included in
the memory cell 200 (1, j) are connected to a source electrode of
the transistor 235 (1, j). The source electrodes of the transistors
201 and 203 included in the memory cell 220 (m, j) are connected to
a drain electrode of the transistor 235 (2, j). The drain electrode
of the transistor 235 (1, j) is connected to the second wiring
BL(j). The source electrode of the transistor 235 (2, j) is
connected to the first wiring SL(j). A gate electrode of the
transistor 235 (1, j) is connected to the sixth wiring SEL(1). The
gate electrode of the transistor 235 (2, j) is connected to the
sixth wiring SEL(2).
[0236] Further, the second wirings BL(1) to BL(n) and the fourth
wirings S2(1) to S2(n) are connected to the driver circuit 231 of
the second wiring and the fourth wiring. The fifth wirings WL(1) to
WL(m), the third wirings S1(1) to S1(m), and the sixth wirings
SEL(1) and SEL(2) are connected to the driver circuit 233 of the
third wiring and the fifth wiring. In addition, the second wirings
BL(1) to BL(n) are also connected to the reading circuit 232. The
potential Vs is supplied to the first wirings SL(1) to SL(n). Note
that the first wirings SL(1) to SL(n) are not necessarily separated
and may be connected to each other.
[0237] The operation of the semiconductor device illustrated in
FIG. 14 will be described. In this structure, writing is performed
by column and reading is performed by row.
[0238] When writing is performed on the memory cells 220 (1, j) to
220 (m, j) in the j-th column, the fourth wiring S2(j) is supplied
with 2 V in order to turn on the transistors 202 of the selected
memory cells. On the other hand, the fourth wirings S2 except the
fourth wiring S2(j) are supplied with 0 V in order to turn off the
transistors 202 of the non-selected memory cells. Among the third
wirings S1(1) to S1(n), a wiring of a row through which data "1" is
written is supplied with 2 V while a row through which data "0" is
written is supplied with 0 V. Note that, to finish writing, the
fourth wiring S2(j) is supplied with 0 V before the potentials of
the third wirings S1(1) to S1(m) are changed, so that the
transistors 202 of the selected memory cells are turned off. As for
the other wirings, for example, the potentials of the second
wirings BL(1) to BL(n), the potentials of the fifth wirings WL(1)
to WL (m), the potentials of the sixth wirings SEL(1) and SEL(2),
and the potential Vs of the first wirings SL(1) to SL(n) are set to
0.
[0239] As a result, the potential of a node (hereinafter, referred
to as a node A) connected to the gate electrode of the transistor
201 of the memory cell to which the data "1" has been written is
approximately 2 V, and the potential of the node A of the memory
cell to which the data "0" has been written is approximately 0 V.
The potential of the node A of the non-selected memory cell is not
changed. Here, the off-state current of the transistor 202 is
extremely small or substantially zero, so that the potential of the
gate electrode of the transistor 201 (node A) is held for a long
time.
[0240] When the memory cells 220 (i, 1) to 220 (i, n) in the i-th
row are read, the sixth wirings SEL(1) and SEL(2) are supplied with
2 V in order to turn on the transistors 235 (1, 1) to 235 (2, n).
The potential Vs of the first wirings SL(1) to SL(n) is set to 0.
The reading circuit 232 connected to the second wirings BL(1) to
BL(n) is set to operate. The fourth wirings S2(1) to S2(n) are
supplied with 0 V in order to turn off the all of the transistors
202 of the memory cells. The third wirings S1(1) to S1(m) are
supplied with 0 V.
[0241] Then, the fifth wiring WL(i) is supplied with 0 V, and the
fifth wirings WL except the fifth wiring WL(i) are supplied with 2
V. At this time, the transistors 203 of the memory cells in the
i-th row are turned off. The transistors 203 of the memory cells
which are not in the i-th row are turned on. As a result, the
resistant/resistance state of the columns of memory cells is
determined by the state of transistor 201 of the memory cells in
the i-th row, an on state or an off state. In the memory cells
which has the data "0" in the i-th row, the transistor 201 is
turned off because the node A is supplied with approximately 0 V;
therefore, the memory cell column is in a high-resistance state. On
the other hand, in the memory cells which has the data "1" in the
i-th row, the transistor 201 is turned on because the node A is
supplied with approximately 2 V; therefore, the memory cell column
is in a low-resistance state. As a result, the reading circuit 232
can read the data "0" and "1" by difference of the resistance
states of the memory cells.
[0242] Note that in writing, in the case where the semiconductor
device does not have a substrate potential such as the case where a
thin film transistor is formed over an SOI substrate, it is
preferable that the fifth wirings WL(1) to WL(m) and the sixth
wiring SEL(1) or SEL(2) be supplied with 2 V. Thus, at least one of
the source electrode and the drain electrode of the transistor 201
of the memory cell in the i-th row can be supplied with
approximately 0 V. On the other hand, in the case where the
semiconductor device has a substrate potential such as the case
where a transistor is formed over a single crystal semiconductor
substrate, the substrate potential may be set to be 0 V.
[0243] Note that the second wirings BL(1) to BL(n) are supplied
with 0 V in writing in the above description; however, the second
wirings BL(1) to BL(n) may be in a floating state or charged to
have a potential of 0 V or more in the case where the sixth wiring
SEL(1) is supplied with 0 V. The third wirings S1(1) to S1(n) are
supplied with 0 V in reading; however, the third wirings S1(1) to
S1(n) may be in a floating state or charged to have a potential of
0 V or more.
[0244] Note that the data "1" and the data "0" are defined for
convenience and can be reversed. In addition, the above operation
voltages are an example. An operation voltage may be determined so
that the transistor 201 is in an off state when the data "0" is set
to and in an on state when the data "1" is set to, so that the
transistor 202 is in an on state in writing and in an off state
otherwise, or so that the transistor 203 of the selected memory
cell is in an off state in reading, and the transistor 203 of the
non-selected memory cell is in an on state in reading. The power
supply potential VDD of the peripheral logic circuit may be used
instead of 2 V. In addition, the ground potential GND may be used
instead of 0 V.
[0245] The semiconductor device according to this embodiment can
store data for an extremely long time because the transistor 202
has low off-state current. That is, refresh operation which is
necessary in a DRAM and the like is not needed, so that power
consumption can be suppressed. Moreover, the semiconductor device
according to this embodiment can be used as a substantially
non-volatile memory device.
[0246] Since writing or the like of data is performed with
switching operation of the transistor 202, high voltage is not
necessary and deterioration of the element does not become a
problem. Furthermore, data is written and erased depending on on
state and off state of the transistor, whereby high-speed operation
can be easily realized. In addition, it is possible to rewriting
data directly by controlling a potential input to the transistor.
Therefore, erasing operation which is necessary in a flash memory
and the like is not necessary, so that a reduction in operation
speed because of erasing operation can be prevented.
[0247] Since a transistor including a material which is not an
oxide semiconductor can operate at sufficiently high speed, stored
data can be read out at high speed by using the transistor.
Embodiment 3
[0248] In this embodiment, an example of a circuit configuration of
a semiconductor device which is different from that in Embodiment 2
and operation thereof will be described.
[0249] FIG. 15 illustrates an example of a circuit diagram of a
memory cell included in the semiconductor device. A memory cell 240
illustrated in FIG. 15 includes the third wiring S1, the fourth
wiring S2, the fifth wiring WL, the transistor 201, the transistor
202, and a capacitor 204. The transistor 201 is formed using a
material which is not an oxide semiconductor and the transistor 202
is formed using an oxide semiconductor. Here, the transistor 201 is
preferably formed to have a structure similar to that of the
transistor 160 in Embodiment 1. In addition, the transistor 202 is
preferably formed to have a structure similar to that of the
transistor 162 in Embodiment 1. Further, it is preferable that the
memory cell 240 be electrically connected to the first wiring SL
and the second wiring BL through a transistor (including a
transistor in another memory cell).
[0250] Here, the gate electrode of the transistor 201, the one of
the source electrode and the drain electrode of the transistor 202,
and one electrode of the capacitor 204 are electrically connected
to each other. In addition, the first wiring SL is electrically
connected to the source electrode of the transistor 201, and the
second wiring BL is electrically connected to the drain electrode
of the transistor 201. Moreover, the third wiring S1, the fourth
wiring S2, and the fifth wiring WL are electrically connected to
the other of the source electrode and the drain electrode of the
transistor 202, the gate electrode of the transistor 202, and the
other electrode of the capacitor 204, respectively. Note that the
first wiring SL may be electrically connected to the source
electrode of the transistor 201 through a transistor (including a
transistor in another memory cell). Furthermore, the second wiring
BL may be electrically connected to the drain electrode of the
transistor 201 through a transistor (including a transistor in
another memory cell).
[0251] FIG. 16 illustrates a block circuit diagram of a
semiconductor device according to one embodiment of the present
invention, which includes m.times.n bits of memory capacitance.
Here, as an example, a NAND semiconductor device in which the
memory cells 240 are connected in series is shown.
[0252] The semiconductor device according to one embodiment of the
present invention includes m fifth wirings WL, m fourth wirings S2,
n first wirings SL, n second wirings BL, n third wirings S1, two
sixth wirings SEL(1) and SEL(2), a memory cell array 250 in which a
plurality of memory cells 240 (1, 1) to 240 (m, n) are provided in
matrix of m rows (horizontal) and n columns (vertical) (m and n are
natural numbers), transistors 255 (1, 1) to 255 (1, n) provided
between the second wirings BL(1) to BL(n) and the memory cells 240
(1, 1) to 240 (1, n) along the sixth wiring SEL(1), transistors 255
(2, 1) to 255 (2, n) provided between the first wirings SL(1) to
SL(n) and the memory cells 240 (m, 1) to 240 (m, n) along the sixth
wiring SEL(2), and peripheral circuits such as a driver circuit 251
of the second wiring and the third wiring, a driver circuit 253 of
the fourth wiring and the fifth wiring, and a reading circuit 252.
A refresh circuit or the like may be provided as another peripheral
circuit.
[0253] Each memory cell 240 (a specific example of which the memory
cell 240 (i, j), where i is an integer of 1 or more and m or less,
and j is an integer of 1 or more and n or less) is connected to the
third wiring S1(j), the fourth wiring S2(i), and the fifth wiring
WL(i). Further, the drain electrode of the transistor 201 included
in the memory cell 240 (i.sub.1, j) (i.sub.1 is an integer of 2 to
m) are connected to the source electrode of the transistor 201
included in the memory cell 240 (i.sub.1-1, j). In addition, the
source electrode of the transistor 201 included in the memory cell
240 (i.sub.2,1) (i.sub.2 is an integer of 1 to m-1) are connected
to the drain electrode of the transistor 201 included in the memory
cell 240 (i.sub.2+1, 1). The drain electrode of the transistor 201
included in the memory cell 240 (1, j) is connected to a source
electrode of the transistor 255 (1, j). The source electrode of the
transistor 201 included in the memory cell 240 (m, j) is connected
to a drain electrode of the transistor 255 (2, j). The drain
electrode of the transistor 255 (1, j) is connected to the second
wiring BL(j). The source electrode of the transistor 255 (2, j) is
connected to the first wiring SL(j).
[0254] Further, the second wirings BL(1) to BL(n) and the third
wirings S1(1) to S1(n) are connected to the driver circuit 251 of
the second wirings and the third wirings. The fifth wirings WL(1)
to WL(m), the fourth wirings S2(1) to S2(m), and the sixth wirings
SEL(1) and SEL(2) are connected to the driver circuit 253 of the
fourth wiring and the fifth wiring. In addition, the second wirings
BL(1) to BL(n) are also connected to the reading circuit 252. The
potential Vs is supplied to the first wirings SL(1) to SL(n). Note
that the first wirings SL(1) to SL(n) are not necessarily separated
and may be connected to each other.
[0255] The operation of the semiconductor device illustrated in
FIG. 16 will be described. In this structure, writing and reading
are performed by row.
[0256] When writing is performed on the memory cells 240 (i, 1) to
240 (i, n) in the i-th row, the fourth wiring S2(i) is supplied
with 2 V in order to turn on the transistors 202 of the memory
cells in the i-th row. On the other hand, the fourth wirings S2
except the fourth wiring S2(i) are supplied with 0 V in order to
turn off the transistors 202 of the memory cells which are not in
the i-th row. Among the third wirings S1(1) to S1(n), a wiring of a
column through which data "1" is written is supplied with 2 V while
a column through which data "0" is supplied with 0 V. Note that, to
finish writing, the fourth wiring S2(i) is supplied with 0 V before
the potentials of the third wirings S1(1) to S1(n) are changed, so
that the transistors 202 of the selected memory cells are turned
off. As for the other wirings, for example, the potentials of the
second wirings BL(1) to BL(n), the potentials of the fifth wirings
WL(1) to WL (m), the potentials of the sixth wirings SEL(1) and
SEL(2), and the potential Vs of the first wirings SL(1) to SL(n)
are set to 0.
[0257] As a result, the potential of a node (hereinafter, referred
to as a node A) connected to the gate electrode of the transistor
201 of the memory cell to which the data "1" has been written is
approximately 2 V, and the potential of the node A of the memory
cell to which the data "0" has been written is approximately 0 V.
The potential of the node A of the non-selected memory cell is not
changed. Here, the off-state current of the transistor 202 is
extremely small or substantially zero, so that the potential of the
gate electrode of the transistor 201 (node A) is held for a long
time.
[0258] When the memory cells 240 (i, 1) to 240 (i, n) in the i-th
row are read, the sixth wirings SEL(1) and SEL(2) are supplied with
2 V in order to turn on the transistors 255 (1, 1) to 255 (2, n).
The potential Vs of the first wirings SL(1) to SL(n) is set to 0.
The reading circuit 252 connected to the second wirings BL(1) to
BL(n) is set to operate. The fourth wirings S2(1) to S2(m) are
supplied with 0 V in order to turn off the all of the transistors
202 of the memory cells. The third wirings S1(1) to S1(n) are
supplied with 0 V.
[0259] Further, the fifth wiring WL (i) is supplied with 0 V and
the fifth wirings except the fifth wiring WL (i) are supplied with
2 V. The state of the transistor 201 in the case where the fifth
wiring WL (i) is supplied with 0 V and the fifth wirings except the
fifth wiring WL (i) are supplied with 2 V is described here. The
potential of the node A which determines the state of the
transistor 201 is decided depending on capacitance C1 between the
fifth wiring WL and the node A, and capacitance C2 between the gate
of the transistor 201 and the source or the drain of the transistor
201. FIG. 17 illustrates a relationship between the potential of
the fifth wiring WL and the potential of the node A. Here, as an
example, C1/C2>>1 is satisfied when the transistor is in an
off state and C1/C2=1 is satisfied when the transistor 201 is in an
on state. In addition, the threshold voltage of the transistor 201
is 0.5 V. According to FIG. 17, when the potential of the fifth
wiring WL is 0 V, the transistor 201 is turned off in a memory cell
having data "0" because the node A is at approximately 0 V, and the
transistor 201 is turned on in a memory cell having data "1"
because the node A has approximately 2 V. On the other hand, when
the potential of the fifth wiring WL is 2 V, the node A is at
approximately 1.25 V in the memory cell having data "0" and the
node A is at approximately 3 V in the memory cell having data "1",
so that the transistor 201 is turned on regardless of whether the
data of the memory cell is "0" or "1". Accordingly, in the case
where the fifth wiring WL(i) is supplied with 0 V and the fifth
wirings WL except the fifth wiring WL(i) are supplied with 2 V, a
memory cell column in which the memory cell in the i-th row has
data "0" is in a high resistance state and a memory cell column in
which the memory cell in the i-th row has data "1" is in a low
resistance state. The reading circuit 252 can read data "0" or "1"
by difference between the resistance states of a memory cells.
[0260] Note that the second wirings BL(1) to BL(n) are supplied
with 0 V in writing in the above description; however, the second
wirings BL(1) to BL(n) may be in a floating state or charged to
have a potential of 0 V or more in the case where the sixth wiring
SEL(1) is supplied with 0 V. The third wirings S1(1) to S1(n) are
supplied with 0 V in reading; however, the third wirings S1(1) to
S1(n) may be in a floating state or charged to have a potential of
0 V or more.
[0261] Note that the data "1" and the data "0" are defined for
convenience and can be reversed. In addition, the above operation
voltages are merely examples. An operation voltage may be
determined so that the transistor 202 is in an on state in writing
and in an off state otherwise, or so that the transistor 201 of the
selected memory cell having data "0" is in an off state in reading,
the transistor 201 of the selected memory cell having data "1" is
in an on state in reading, and the transistor 201 of the
non-selected memory cell is in an on state in reading. The power
supply potential VDD of the peripheral logic circuit may be used
instead of 2 V. In addition, the ground potential GND may be used
instead of 0 V.
[0262] Next, another example of a circuit configuration of a
semiconductor device according to one embodiment of the present
invention and operation thereof will be described.
[0263] FIG. 18 illustrates an example of a circuit diagram of a
memory cell circuit included in the semiconductor device. A memory
cell 260 illustrated in FIG. 18 includes the third wiring S1, the
fourth wiring S2, the fifth wiring WL, the transistor 201, the
transistor 202, and the capacitor 204. The transistor 201 is formed
using a material which is not an oxide semiconductor and the
transistor 202 is formed using an oxide semiconductor. Here, the
transistor 201 is preferably formed to have a structure similar to
that of the transistor 160 in Embodiment 1. In addition, the
transistor 202 is preferably formed to have a structure similar to
that of the transistor 162 in Embodiment 1. Further, it is
preferable that the memory cell 260 be electrically connected to
the first wiring SL and the second wiring BL through a transistor
(including a transistor in another memory cell).
[0264] The memory cell circuit in FIG. 18 is different from the
memory cell circuit in FIG. 15 in the directions of the third
wiring S1 and the fourth wiring S2. In other words, the memory cell
circuit in FIG. 18 has a structure in which the fourth wiring S2
and the third wiring S1 are provided along the second wiring BL (in
a column direction) and the fifth wiring WL (in a row direction),
respectively.
[0265] Further, a block circuit diagram of a semiconductor device
according to one embodiment of the present invention, which
includes m.times.n bits of memory capacitance, can be formed in
such a manner that the memory cell 260 in FIG. 18 is employed as
the memory cell of the block circuit diagram illustrated in FIG.
14. The driving voltage and timing of a driver circuit are set in
accordance with operation of the memory cell 260. Thus, writing by
column and reading by row can be performed as in the case of the
block circuit diagram in FIG. 14.
[0266] The semiconductor device according to this embodiment can
store data for an extremely long time because the transistor 202
has low off-state current. That is, refresh operation which is
necessary in a DRAM and the like is not needed, so that power
consumption can be suppressed. Moreover, the semiconductor device
according to this embodiment can be used as a substantially
non-volatile memory device.
[0267] Since writing or the like of data is performed with
switching operation of the transistor 202, high voltage is not
necessary and deterioration of the element does not become a
problem. Furthermore, data is written and erased depending on on
state and off state of the transistor, whereby high-speed operation
can be easily realized. In addition, it is possible to rewriting
data directly by controlling a potential input to the transistor.
Therefore, erasing operation which is necessary in a flash memory
and the like is not necessary, so that a reduction in operation
speed because of erasing operation can be prevented.
[0268] Since a transistor including a material which is not an
oxide semiconductor can operate at sufficiently high speed, stored
data can be read out at high speed by using the transistor.
Embodiment 4
[0269] In this embodiment, an example of a circuit configuration of
a semiconductor device which is different from that in Embodiment 2
or 3 and operation thereof will be described.
[0270] FIG. 19 illustrates an example of a circuit diagram of a
memory cell circuit included in a semiconductor device according to
one embodiment of the present invention.
[0271] A memory cell 280 in FIG. 19 includes a capacitor 205
between the node A and the first wiring SL in addition to the
elements included in the memory cell circuit in FIG. 10. The
capacitor 205 leads to improvement of a data storing
characteristics.
[0272] Operation of the memory cell circuit in FIG. 19 is similar
to that of the memory cell circuit in FIG. 10, so that detailed
description thereof is omitted.
Embodiment 5
[0273] An example of a reading circuit included in a semiconductor
device according to one embodiment of the present invention will be
described with reference to FIG. 20.
[0274] A reading circuit illustrated in FIG. 20 includes a
transistor 206 and a differential amplifier.
[0275] At the time of reading, a terminal A is connected to a
second wiring connected to a memory cell from which data is read.
Moreover, a voltage Vdd is applied to a drain electrode or a source
electrode of the transistor 206, a bias voltage Vbias is applied to
a gate electrode of the transistor 206, and a predetermined current
flows through the transistor 206.
[0276] A memory cell has a different resistance corresponding to
data "1" or data "0" stored therein. Specifically, when the
transistor 201 in a selected memory cell is on, the memory cell has
a low resistance; whereas when the transistor 201 in a selected
memory cell is off, the memory cell has a high resistance.
[0277] When the memory cell has a high resistance, the potential of
the terminal A is higher than a reference potential Vref and data
"1" is output from an output of the differential amplifier. On the
other hand, when the memory cell has a low resistance, the
potential of the terminal A is lower than the reference potential
Vref and data "0" is output from the output of the differential
amplifier.
[0278] In such a manner, the reading circuit can read data from the
memory cell. Note that the reading circuit in this embodiment is an
example, and a known circuit may be used. For example, the reading
circuit may include a precharge circuit. A second wiring for
reference may be connected instead of the reference potential Vref.
A latch-type sense amplifier may be used instead of the
differential amplifier.
[0279] The structures and methods described in this embodiment can
be combined as appropriate with any of the structures and methods
described in the other embodiments.
Embodiment 6
[0280] In this embodiment, examples of electronic devices each
including the semiconductor device according to any of the
above-described embodiments will be described with reference to
FIGS. 21A to 21F. The semiconductor device according to the above
embodiment can store data even when power is not supplied.
Moreover, degradation due to writing or erasing does not occur.
Furthermore, the semiconductor device can operate at high speed.
For these reasons, an electronic device with a novel structure can
be provided by using the semiconductor device. Note that the
semiconductor devices according to the above embodiment are
integrated and mounted on a circuit board or the like, and placed
inside an electronic device.
[0281] FIG. 21A illustrates a notebook personal computer including
the semiconductor device according to the above embodiment. The
notebook personal computer includes a main body 301, a housing 302,
a display portion 303, a keyboard 304, and the like. The
semiconductor device according to one embodiment of the present
invention is applied to a notebook personal computer, whereby the
notebook personal computer can store data even when power is not
supplied. Moreover, degradation due to writing or erasing does not
occur. Further, the notebook personal computer can operate at high
speed. For these reasons, it is appropriate to apply the
semiconductor device according to one embodiment of the present
invention to a notebook personal computer.
[0282] FIG. 21B illustrates a personal digital assistant (PDA)
including the semiconductor device according to the above
embodiment. A main body 311 is provided with a display portion 313,
an external interface 315, operation buttons 314, and the like. A
stylus 312 that is an accessory is used for operating the PDA. The
semiconductor device according to one embodiment of the present
invention is applied to a PDA, whereby the PDA can store data even
when power is not supplied.
[0283] Moreover, degradation due to writing or erasing does not
occur. Further, the PDA can operate at high speed. For these
reasons, it is appropriate to apply the semiconductor device
according to one embodiment of the present invention to a PDA.
[0284] FIG. 21C illustrates an e-book reader 320 as an example of
electronic paper including the semiconductor device according to
the above embodiment. The e-book reader 320 includes two housings:
a housing 321 and a housing 323. The housing 321 and the housing
323 are combined with a hinge 337 so that the e-book reader 320 can
be opened and closed with the hinge 337 as an axis. With such a
structure, the e-book reader 320 can be used like a paper book. The
semiconductor device according to one embodiment of the present
invention is applied to electronic paper, whereby the electronic
paper can hold data even when power is not supplied. Moreover,
degradation due to writing or erasing does not occur. Further, the
electronic paper can operate at high speed. For these reasons, it
is appropriate to apply the semiconductor device according to one
embodiment of the present invention to electronic paper.
[0285] A display portion 325 is incorporated in the housing 321 and
a display portion 327 is incorporated in the housing 323. The
display portion 325 and the display portion 327 may display one
image or different images. When the display portion 325 and the
display portion 327 display different images, for example, the
right display portion (the display portion 325 in FIG. 21C) can
display text and the left display portion (the display portion 327
in FIG. 21C) can display images.
[0286] FIG. 21C illustrates an example in which the housing 321 is
provided with an operation portion and the like. For example, the
housing 321 is provided with a power switch 331, operation keys
333, a speaker 335, and the like. Pages can be turned with the
operation key 333. Note that a keyboard, a pointing device, or the
like may also be provided on the surface of the housing, on which
the display portion is provided. Furthermore, an external
connection terminal (e.g., an earphone terminal, a USB terminal, or
a terminal that can be connected to various cables such as an AC
adapter and a USB cable), a recording medium insertion portion, and
the like may be provided on the back surface or the side surface of
the housing. Further, the e-book reader 320 may have a function of
an electronic dictionary.
[0287] The e-book reader 320 may send and receive data wirelessly.
Through wireless communication, desired book data or the like can
be purchased and downloaded from an electronic book server.
[0288] Note that electronic paper can be applied to devices in a
variety of fields as long as they display information. For example,
electronic paper can be used for posters, advertisement in vehicles
such as trains, display in a variety of cards such as credit cards,
and the like in addition to e-book readers.
[0289] FIG. 21D illustrates a mobile phone including the
semiconductor device according to the above embodiment. The mobile
phone includes two housings: a housing 340 and a housing 341. The
housing 341 is provided with a display panel 342, a speaker 343, a
microphone 344, a pointing device 346, a camera lens 347, an
external connection terminal 348, and the like. The housing 340 is
provided with a solar cell 349 for charging the mobile phone, an
external memory slot 350, and the like. In addition, an antenna is
incorporated in the housing 341. The semiconductor device according
to one embodiment of the present invention is applied to a mobile
phone, whereby the mobile phone can hold data even when power is
not supplied. Moreover, degradation due to writing or erasing does
not occur. Further, the mobile phone can operate at high speed. For
these reasons, it is appropriate to apply the semiconductor device
according to one embodiment of the present invention to a mobile
phone.
[0290] The display panel 342 has a touch panel function. A
plurality of operation keys 345 displayed as images are shown by
dashed lines in FIG. 21D. Note that the mobile phone includes a
booster circuit for boosting a voltage output from the solar cell
349 to a voltage necessary for each circuit. Moreover, the mobile
phone can include a contactless IC chip, a small recording device,
or the like in addition to the above structure.
[0291] The direction of display on the display panel 342 is changed
as appropriate depending on applications. Further, the camera lens
347 is provided on the same surface as the display panel 342, so
that the mobile phone can be used as a videophone. The speaker 343
and the microphone 344 can be used for videophone calls, recording
and playing sound, and the like as well as voice calls. Moreover,
the housings 340 and 341 in a state where they are developed as
illustrated in FIG. 21D can be slid so that one is lapped over the
other. Therefore, the size of the mobile phone can be reduced,
which makes the mobile phone suitable for being carried.
[0292] The external connection terminal 348 can be connected to a
variety of cables such as an AC adapter or a USB cable, so that the
mobile phone can be charged or can perform data communication.
Moreover, the mobile phone can store and move a larger amount of
data by inserting a recording medium into the external memory slot
350. Further, the mobile phone may have an infrared communication
function, a television reception function, or the like in addition
to the above functions.
[0293] FIG. 21E illustrates a digital camera including the
semiconductor device according to the above embodiment. The digital
camera includes a main body 361, a display portion (A) 367, an
eyepiece portion 363, an operation switch 364, a display portion
(B) 365, a battery 366, and the like. The semiconductor device
according to one embodiment of the present invention is applied to
a digital camera, whereby the digital camera can hold data even
when power is not supplied. Moreover, degradation due to writing or
erasing does not occur. Further, the digital camera can operate at
high speed. For these reasons, it is appropriate to apply the
semiconductor device according to one embodiment of the present
invention to a digital camera.
[0294] FIG. 21F illustrates a television set including the
semiconductor device according to the above embodiment. In a
television set 370, a display portion 373 is incorporated in a
housing 371. Images can be displayed on the display portion 373.
Here, the housing 371 is supported by a stand 375.
[0295] The television set 370 can be operated by an operation
switch of the housing 371 or a separate remote controller 380. With
operation keys 379 of the remote controller 380, channels and
volume can be controlled and images displayed on the display
portion 373 can be controlled. Moreover, the remote controller 380
may include a display portion 377 for displaying data output from
the remote controller 380. The semiconductor device according to
one embodiment of the present invention is applied to a television
set, whereby the television set can hold data even when power is
not supplied. Moreover, degradation due to writing or erasing does
not occur. Furthermore, the television set can operate at high
speed. For these reasons, it is appropriate to apply the
semiconductor device according to one embodiment of the present
invention to a television set.
[0296] Note that the television set 370 is preferably provided with
a receiver, a modem, and the like. A general television broadcast
can be received with the receiver. Moreover, when the television
set is connected to a communication network with or without wires
via the modem, one-way (from a sender to a receiver) or two-way
(between a sender and a receiver or between receivers) data
communication can be performed.
[0297] The structures and methods described in this embodiment can
be combined as appropriate with any of the structures and methods
described in the other embodiments.
[0298] This application is based on Japanese Patent Application
serial no. 2009-251275 filed with the Japan Patent Office on Oct.
30, 2009, the entire contents of which are hereby incorporated by
reference.
* * * * *