U.S. patent application number 16/872598 was filed with the patent office on 2021-11-18 for integrated assemblies and methods of forming integrated assemblies.
This patent application is currently assigned to Micron Technology, Inc.. The applicant listed for this patent is Micron Technology, Inc.. Invention is credited to John D. Hopkins, Nancy M. Lomeli, Lifang Xu.
Application Number | 20210358805 16/872598 |
Document ID | / |
Family ID | 1000004858223 |
Filed Date | 2021-11-18 |
United States Patent
Application |
20210358805 |
Kind Code |
A1 |
Hopkins; John D. ; et
al. |
November 18, 2021 |
Integrated Assemblies and Methods of Forming Integrated
Assemblies
Abstract
Some embodiments include an integrated assembly having a stack
of alternating first and second levels. The first levels contain
conductive material and the second levels contain insulative
material. At least some of the first and second levels are
configured as steps. Each of the steps has one of the second levels
over an associated one of the first levels. A layer is over the
steps and is spaced from the stack by an intervening insulative
region. Insulative material is over the layer. Conductive
interconnects extend through the insulative material, through the
layer, through the intervening insulative region and to the
conductive material within the first levels of the steps. Some
embodiments include methods of forming integrated assemblies.
Inventors: |
Hopkins; John D.; (Meridian,
ID) ; Xu; Lifang; (Boise, ID) ; Lomeli; Nancy
M.; (Boise, ID) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Micron Technology, Inc. |
Boise |
ID |
US |
|
|
Assignee: |
Micron Technology, Inc.
Boise
ID
|
Family ID: |
1000004858223 |
Appl. No.: |
16/872598 |
Filed: |
May 12, 2020 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/11573 20130101;
H01L 27/1157 20130101; H01L 27/11582 20130101; H01L 2221/1063
20130101; H01L 21/76829 20130101; H01L 21/76816 20130101; H01L
27/11524 20130101; H01L 21/76895 20130101; H01L 27/11556 20130101;
H01L 23/5283 20130101; H01L 23/5226 20130101; H01L 21/76805
20130101; H01L 21/76877 20130101; H01L 27/11529 20130101; H01L
21/76834 20130101; H01L 23/535 20130101 |
International
Class: |
H01L 21/768 20060101
H01L021/768; H01L 27/11524 20060101 H01L027/11524; H01L 27/11556
20060101 H01L027/11556; H01L 27/11529 20060101 H01L027/11529; H01L
27/1157 20060101 H01L027/1157; H01L 27/11582 20060101
H01L027/11582; H01L 27/11573 20060101 H01L027/11573; H01L 23/522
20060101 H01L023/522; H01L 23/528 20060101 H01L023/528; H01L 23/535
20060101 H01L023/535 |
Claims
1. A method of forming an integrated assembly, comprising: forming
a stack of alternating first and second levels; the first levels
comprising sacrificial material and the second levels comprising
insulative material; at least some of the first and second levels
being configured as steps; each of the steps comprising one of the
second levels over an associated one of the first levels, and
having an upper surface corresponding to an upper surface of said
one of the second levels; forming an etch-stop material over the
stack; forming fill material over the etch-stop material; removing
the sacrificial material and forming conductive layers within the
first levels; the conductive layers within the steps having upper
surfaces; forming openings to extend through the fill material to
the etch-stop material; removing portions of the etch-stop material
from under the fill material to form recesses; extending the
openings through the etch-stop material and to the upper surfaces
of the conductive layers within the steps; and forming conductive
interconnects within the openings and the extended openings.
2. The method of claim 1 wherein the conductive layers are
gate/routing layers of a memory array, and further comprising
coupling the conductive interconnects with driver circuitry.
3. The method of claim 1 further comprising forming a protective
liner over the stack, and forming the etch-stop material over the
protective liner.
4. The method of claim 3 wherein the protective liner comprises an
insulative oxide.
5. The method of claim 3 wherein the protective liner comprises one
or more of SiO, AlO, HfO, ZrO, and TaO; where the chemical formulas
indicate primary constituents rather than specific
stoichiometries.
6. The method of claim 1 wherein the fill material comprises
silicon dioxide.
7. The method of claim 1 wherein the etch-stop material is
insulative.
8. The method of claim 1 wherein the etch-stop material is
conductive.
9. The method of claim 1 wherein the etch-stop material comprises
aluminum oxide.
10. The method of claim 1 wherein the etch-stop material comprises
carbon-doped silicon nitride.
11. The method of claim 10 wherein the carbon-doped silicon nitride
comprises a carbon concentration within a range of from about 5 at
% to about 20 at %.
12. The method of claim 10 wherein the carbon-doped silicon nitride
comprises a carbon concentration within a range of from about 10 at
% to about 15 at %.
13. The method of claim 1 wherein the etch-stop material consists
essentially of silicon.
14. The method of claim 1 wherein the etch-stop material comprises
tungsten.
15. A method of forming an integrated assembly, comprising: forming
a stack of alternating first and second levels; the stack having a
first region within a memory array region, and having a second
region within a staircase region proximate the memory array region;
the first levels comprising sacrificial material and the second
levels comprising insulative material; at least some of the first
and second levels being configured as steps within the staircase
region; each of the steps comprising one of the second levels over
an associated one of the first levels, and having an upper surface
corresponding to an upper surface of said one of the second levels;
forming a protective liner over the second region of the stack;
forming an etch-stop material over the second region of the stack
and over the protective liner, material of the protective liner
comprising one of the following: the same material as the etch-stop
material; or a different material from the etch-stop material
wherein the material of the protective liner comprises AlO, HfO,
ZrO and TaO; forming a fill material over the steps, the fill
material being over the etch-stop material; removing the
sacrificial material and forming conductive material within the
first levels; the conductive material within the steps being
configured as conductive layers having upper surfaces; forming
openings to extend through the fill material to the etch-stop
material; extending the openings through the etch-stop material to
the protective liner with first etching conditions; extending the
openings through the protective liner and to the upper surfaces of
the conductive layers within the steps with additional etching
conditions; and forming conductive interconnects within the
openings and the extended openings.
16. The method of claim 15 wherein the first etching conditions
include isotropic etching conditions which remove portions of the
etch-stop material from under the fill material to form
recesses.
17. The method of claim 16 wherein the etch-stop material is a
conductive material; and further comprising forming insulative
spacers within the recesses prior to forming the conductive
interconnects.
18. The method of claim 15 wherein the first etching conditions
include first anisotropic etching conditions, and wherein the
additional etching conditions include second anisotropic etching
conditions.
19. The method of claim 15 wherein the sacrificial material
comprises silicon nitride.
20. The method of claim 15 further comprising forming a planarized
upper surface to extend across the stack and the first fill
material prior to forming the openings.
21. The method of claim 15 further comprising forming channel
material to extend through the stack within the memory array
region.
22. The method of claim 21 further comprising forming
charge-trapping material to be adjacent the channel material.
23. The method of claim 15 wherein dielectric blocking material is
formed within the first levels in addition to the conductive
material; and wherein the extending of the openings with the
additional etching conditions also includes extending the openings
through the dielectric-barrier material.
24-42. (canceled)
43. A method of forming an integrated assembly, comprising: forming
a stack of alternating first and second levels; the first levels
comprising sacrificial material and the second levels comprising
insulative material; at least some of the first and second levels
being configured as steps; each of the steps comprising one of the
second levels over an associated one of the first levels, and
having an upper surface corresponding to an upper surface of said
one of the second levels; forming an etch-stop material over the
stack; forming fill material over the etch-stop material; removing
the sacrificial material and forming conductive layers within the
first levels; the conductive layers within the steps having upper
surfaces; forming openings to extend through the fill material to
the etch-stop material; extending the openings through the
etch-stop material and to the upper surfaces of the conductive
layers within the steps; and forming conductive interconnects
within the openings and the extended openings; wherein the
etch-stop material comprises carbon-doped silicon nitride; and
wherein the carbon-doped silicon nitride comprises a carbon
concentration within a range of from about 5 at % to about 20 at
%.
44. A method of forming an integrated assembly, comprising: forming
a stack of alternating first and second levels; the first levels
comprising sacrificial material and the second levels comprising
insulative material; at least some of the first and second levels
being configured as steps; each of the steps comprising one of the
second levels over an associated one of the first levels, and
having an upper surface corresponding to an upper surface of said
one of the second levels; forming an etch-stop material over the
stack; forming fill material over the etch-stop material; removing
the sacrificial material and forming conductive layers within the
first levels; the conductive layers within the steps having upper
surfaces; forming openings to extend through the fill material to
the etch-stop material; extending the openings through the
etch-stop material and to the upper surfaces of the conductive
layers within the steps; and forming conductive interconnects
within the openings and the extended openings; wherein the
etch-stop material comprises carbon-doped silicon nitride; and
wherein the carbon-doped silicon nitride comprises a carbon
concentration within a range of from about 10 at % to about 15 at
%.
45. The method of claim 1 wherein the etch-stop material comprises
a range of one of the following thicknesses: a range from about 50
nm to about 250 nm; a range from about 20 nm to about 100 nm; and a
range from about 40 nm to about 60 nm.
46. The method of claim 1 wherein the removing of the portions of
the etch-stop material occurs during the forming of the openings to
extend through the fill material.
47. The method of claim 1 wherein the removing of the portions of
the etch-stop material occurs before the extending of the
openings.
48. The method of claim 1 further comprising forming insulative
spacers within the recesses.
49. The method of claim 15 wherein the material of the protective
liner comprises the same material as the etch-stop material.
50. The method of claim 49 wherein the same material is AlO.
51. A method of forming an integrated assembly, comprising: forming
a stack of alternating first and second levels; the stack having a
first region within a memory array region, and having a second
region within a staircase region proximate the memory array region;
the first levels comprising sacrificial material and the second
levels comprising insulative material; at least some of the first
and second levels being configured as steps within the staircase
region; each of the steps comprising one of the second levels over
an associated one of the first levels, and having an upper surface
corresponding to an upper surface of said one of the second levels;
forming a protective liner over the second region of the stack;
forming an etch-stop material over the second region of the stack
and over the protective liner; forming a fill material over the
steps, the fill material being over the etch-stop material;
removing the sacrificial material and forming conductive material
within the first levels; the conductive material within the steps
being configured as conductive layers having upper surfaces;
forming openings to extend through the fill material to the
etch-stop material; extending the openings through the etch-stop
material to the protective liner with first etching conditions;
extending the openings through the protective liner and to the
upper surfaces of the conductive layers within the steps with
additional etching conditions; forming conductive interconnects
within the openings and the extended openings; and wherein the
first etching conditions include isotropic etching conditions which
remove portions of the etch-stop material from under the fill
material to form recesses.
52. The method of claim 51 wherein the etch-stop material is a
conductive material; and further comprising forming insulative
spacers within the recesses prior to forming the conductive
interconnects.
53. A method of forming an integrated assembly, comprising: forming
a stack of alternating first and second levels; the stack having a
first region within a memory array region, and having a second
region within a staircase region proximate the memory array region;
the first levels comprising sacrificial material and the second
levels comprising insulative material; at least some of the first
and second levels being configured as steps within the staircase
region; each of the steps comprising one of the second levels over
an associated one of the first levels, and having an upper surface
corresponding to an upper surface of said one of the second levels;
forming a protective liner over the second region of the stack;
forming an etch-stop material over the second region of the stack
and over the protective liner; forming a fill material over the
steps, the fill material being over the etch-stop material;
removing the sacrificial material and forming conductive material
within the first levels; the conductive material within the steps
being configured as conductive layers having upper surfaces;
forming openings to extend through the fill material to the
etch-stop material; extending the openings through the etch-stop
material to the protective liner with first etching conditions;
extending the openings through the protective liner and to the
upper surfaces of the conductive layers within the steps with
additional etching conditions; forming conductive interconnects
within the openings and the extended openings; and wherein
dielectric blocking material is formed within the first levels in
addition to the conductive material; and wherein the extending of
the openings with the additional etching conditions also includes
extending the openings through the dielectric-barrier material.
Description
TECHNICAL FIELD
[0001] Integrated assemblies (e.g., memory arrangements), and
methods of forming integrated assemblies.
BACKGROUND
[0002] Memory provides data storage for electronic systems. Flash
memory is one type of memory, and has numerous uses in modern
computers and devices. For instance, modern personal computers may
have BIOS stored on a flash memory chip. As another example, it is
becoming increasingly common for computers and other devices to
utilize flash memory in solid state drives to replace conventional
hard drives. As yet another example, flash memory is popular in
wireless electronic devices because it enables manufacturers to
support new communication protocols as they become standardized,
and to provide the ability to remotely upgrade the devices for
enhanced features.
[0003] NAND may be a basic architecture of flash memory, and may be
configured to comprise vertically-stacked memory cells.
[0004] Before describing NAND specifically, it may be helpful to
more generally describe the relationship of a memory array within
an integrated arrangement. FIG. 1 shows a block diagram of a prior
art device 1000 which includes a memory array 1002 having a
plurality of memory cells 1003 arranged in rows and columns along
with access lines 1004 (e.g., wordlines to conduct signals WL0
through WLm) and first data lines 1006 (e.g., bitlines to conduct
signals BL0 through BLn). Access lines 1004 and first data lines
1006 may be used to transfer information to and from the memory
cells 1003. A row decoder 1007 and a column decoder 1008 decode
address signals A0 through AX on address lines 1009 to determine
which ones of the memory cells 1003 are to be accessed. A sense
amplifier circuit 1015 operates to determine the values of
information read from the memory cells 1003. An I/O circuit 1017
transfers values of information between the memory array 1002 and
input/output (I/O) lines 1005. Signals DQ0 through DQN on the I/O
lines 1005 can represent values of information read from or to be
written into the memory cells 1003. Other devices can communicate
with the device 1000 through the I/O lines 1005, the address lines
1009, or the control lines 1020. A memory control unit 1018 is used
to control memory operations to be performed on the memory cells
1003, and utilizes signals on the control lines 1020. The device
1000 can receive supply voltage signals Vcc and Vss on a first
supply line 1030 and a second supply line 1032, respectively. The
device 1000 includes a select circuit 1040 and an input/output
(I/O) circuit 1017. The select circuit 1040 can respond, via the
I/O circuit 1017, to signals CSEL1 through CSELn to select signals
on the first data lines 1006 and the second data lines 1013 that
can represent the values of information to be read from or to be
programmed into the memory cells 1003. The column decoder 1008 can
selectively activate the CSEL1 through CSELn signals based on the
A0 through AX address signals on the address lines 1009. The select
circuit 1040 can select the signals on the first data lines 1006
and the second data lines 1013 to provide communication between the
memory array 1002 and the I/O circuit 1017 during read and
programming operations.
[0005] The memory array 1002 of FIG. 1 may be a NAND memory array,
and FIG. 2 shows a schematic diagram of a three-dimensional NAND
memory device 200 which may be utilized for the memory array 1002
of FIG. 1. The device 200 comprises a plurality of strings of
charge-storage devices. In a first direction (Z-Z'), each string of
charge-storage devices may comprise, for example, thirty-two
charge-storage devices stacked over one another with each
charge-storage device corresponding to one of, for example,
thirty-two tiers (e.g., Tier0-Tier31). The charge-storage devices
of a respective string may share a common channel region, such as
one formed in a respective pillar of semiconductor material (e.g.,
polysilicon) about which the string of charge-storage devices is
formed. In a second direction (X-X'), each first group of, for
example, sixteen first groups of the plurality of strings may
comprise, for example, eight strings sharing a plurality (e.g.,
thirty-two) of access lines (i.e., "global control gate (CG)
lines", also known as wordlines, WLs). Each of the access lines may
couple the charge-storage devices within a tier. The charge-storage
devices coupled by the same access line (and thus corresponding to
the same tier) may be logically grouped into, for example, two
pages, such as P0/P32, P1/P33, P2/P34 and so on, when each
charge-storage device comprises a cell capable of storing two bits
of information. In a third direction (Y-Y'), each second group of,
for example, eight second groups of the plurality of strings, may
comprise sixteen strings coupled by a corresponding one of eight
data lines. The size of a memory block may comprise 1,024 pages and
total about 16 MB (e.g., 16 WLs.times.32 tiers.times.2 bits=1,024
pages/block, block size=1,024 pages 16 KB/page=16 MB). The number
of the strings, tiers, access lines, data lines, first groups,
second groups and/or pages may be greater or smaller than those
shown in FIG. 2.
[0006] FIG. 3 shows a cross-sectional view of a memory block 300 of
the 3D NAND memory device 200 of FIG. 2 in an X-X' direction,
including fifteen strings of charge-storage devices in one of the
sixteen first groups of strings described with respect to FIG. 2.
The plurality of strings of the memory block 300 may be grouped
into a plurality of subsets 310, 320, 330 (e.g., tile columns),
such as tile column.sub.I, tile column.sub.j and tile column.sub.K,
with each subset (e.g., tile column) comprising a "partial block"
of the memory block 300. A global drain-side select gate (SGD) line
340 may be coupled to the SGDs of the plurality of strings. For
example, the global SGD line 340 may be coupled to a plurality
(e.g., three) of sub-SGD lines 342, 344, 346 with each sub-SGD line
corresponding to a respective subset (e.g., tile column), via a
corresponding one of a plurality (e.g., three) of sub-SGD drivers
332, 334, 336. Each of the sub-SGD drivers 332, 334, 336 may
concurrently couple or cut off the SGDs of the strings of a
corresponding partial block (e.g., tile column) independently of
those of other partial blocks. A global source-side select gate
(SGS) line 360 may be coupled to the SGSs of the plurality of
strings. For example, the global SGS line 360 may be coupled to a
plurality of sub-SGS lines 362, 364, 366 with each sub-SGS line
corresponding to the respective subset (e.g., tile column), via a
corresponding one of a plurality of sub-SGS drivers 322, 324, 326.
Each of the sub-SGS drivers 322, 324, 326 may concurrently couple
or cut off the SGSs of the strings of a corresponding partial block
(e.g., tile column) independently of those of other partial blocks.
A global access line (e.g., a global CG line) 350 may couple the
charge-storage devices corresponding to the respective tier of each
of the plurality of strings. Each global CG line (e.g., the global
CG line 350) may be coupled to a plurality of sub-access lines
(e.g., sub-CG lines) 352, 354, 356 via a corresponding one of a
plurality of sub-string drivers 312, 314 and 316. Each of the
sub-string drivers may concurrently couple or cut off the
charge-storage devices corresponding to the respective partial
block and/or tier independently of those of other partial blocks
and/or other tiers. The charge-storage devices corresponding to the
respective subset (e.g., partial block) and the respective tier may
comprise a "partial tier" (e.g., a single "tile") of charge-storage
devices. The strings corresponding to the respective subset (e.g.,
partial block) may be coupled to a corresponding one of sub-sources
372, 374 and 376 (e.g., "tile source") with each sub-source being
coupled to a respective power source.
[0007] The NAND memory device 200 is alternatively described with
reference to a schematic illustration of FIG. 4.
[0008] The memory array 200 includes wordlines 202.sub.1 to
202.sub.N, and bitlines 228.sub.1 to 228.sub.M.
[0009] The memory array 200 also includes NAND strings 206.sub.1 to
206.sub.M. Each NAND string includes charge-storage transistors
208.sub.1 to 208.sub.N. The charge-storage transistors may use
floating gate material (e.g., polysilicon) to store charge, or may
use charge-trapping material (such as, for example, silicon
nitride, metallic nanodots, etc.) to store charge.
[0010] The charge-storage transistors 208 are located at
intersections of wordlines 202 and strings 206. The charge-storage
transistors 208 represent non-volatile memory cells for storage of
data. The charge-storage transistors 208 of each NAND string 206
are connected in series source-to-drain between a source-select
device (e.g., source-side select gate, SGS) 210 and a drain-select
device (e.g., drain-side select gate, SGD) 212. Each source-select
device 210 is located at an intersection of a string 206 and a
source-select line 214, while each drain-select device 212 is
located at an intersection of a string 206 and a drain-select line
215. The select devices 210 and 212 may be any suitable access
devices, and are generically illustrated with boxes in FIG. 4.
[0011] A source of each source-select device 210 is connected to a
common source line 216. The drain of each source-select device 210
is connected to the source of the first charge-storage transistor
208 of the corresponding NAND string 206. For example, the drain of
source-select device 210.sub.1 is connected to the source of
charge-storage transistor 208.sub.1 of the corresponding NAND
string 206.sub.1. The source-select devices 210 are connected to
source-select line 214.
[0012] The drain of each drain-select device 212 is connected to a
bitline (i.e., digit line) 228 at a drain contact. For example, the
drain of drain-select device 212.sub.1 is connected to the bitline
228.sub.1. The source of each drain-select device 212 is connected
to the drain of the last charge-storage transistor 208 of the
corresponding NAND string 206. For example, the source of
drain-select device 212.sub.1 is connected to the drain of
charge-storage transistor 208.sub.N of the corresponding NAND
string 206.sub.1.
[0013] The charge-storage transistors 208 include a source 230, a
drain 232, a charge-storage region 234, and a control gate 236. The
charge-storage transistors 208 have their control gates 236 coupled
to a wordline 202. A column of the charge-storage transistors 208
are those transistors within a NAND string 206 coupled to a given
bitline 228. A row of the charge-storage transistors 208 are those
transistors commonly coupled to a given wordline 202.
[0014] FIGS. 5 and 6 describe a general layout of a conventional
integrated assembly, with FIG. 5 showing a top down view of regions
of the assembly and FIG. 6 showing a cross-sectional side view of
the regions of the assembly.
[0015] Referring to FIG. 5, the assembly 10 includes a memory array
region 12 (Memory Array) proximate a staircase region 14
(Staircase).
[0016] The memory array region 12 includes channel material pillars
16 arranged in a tightly-packed pattern (e.g., a hexagonally-packed
pattern). The channel material pillars extend through conductive
tiers (described below with reference to FIG. 6). The staircase
region 14 includes interconnect regions 18 where electrical contact
is made to individual tiers. Each of the interconnect regions may
be utilized for establishing interconnects to a specific set of the
tiers. For instance, FIG. 5 shows that each of the interconnect
regions is utilized for establishing interconnects to eight of the
tiers, with one of the regions be utilized for coupling with tiers
1-8, and another of the regions being utilized for coupling with
tiers 9-16. Any suitable number of interconnect regions 18 may be
utilized, and such interconnect regions may be utilized for
coupling with any suitable number of conductive tiers.
[0017] FIG. 6 shows a cross-sectional side view of the regions 12
and 14. A stack 20 of alternating first and second levels 22 and 24
extends within the regions 12 and 14. The levels 22 comprise
conductive material 26, and the levels 24 comprise insulative
material 28. In the shown embodiment, a dielectric-barrier material
30 extends along the conductive material 26 of the levels 22.
[0018] The levels 22 may be considered to comprise conductive
tiers, with such tiers corresponding to the conductive material 26
within such levels. Any suitable number of conductive tiers may be
utilized; such as, for example, 8, 16, 32, 64, 128, 256, 512, 1024,
etc.
[0019] The channel material pillars 16 extend through the stack 20
within the memory array region 12. The channel material pillars
comprise channel material 32 (indicated with stippling). The
channel material is spaced from the stack 20 by intervening regions
34. Such regions include charge-blocking material 36,
charge-trapping material 38 and gate dielectric material 40.
[0020] In the illustrated embodiment, the channel material pillars
16 are configured as annular rings surrounding an insulative
material 33. Such may be considered to be a hollow channel
configuration, with the insulative material 33 being within
"hollows" of the channel material pillars 16. In other
applications, the channel material pillars 16 may be solid rather
than being hollow.
[0021] The staircase region 14 includes conductive interconnects 42
which extend to the conductive material 26 of the individual tiers
22. The conductive interconnects extend through an insulative fill
material 44.
[0022] A source structure 46 is shown to be under the stack 20 of
the memory array region 12. The source structure may or may not
also extend to under the stack 20 of the staircase region 14.
[0023] The channel material 32 is shown to be electrically coupled
with the source structure 46.
[0024] Memory cells 48 are along the conductive levels 22 within
the memory array region 12; with each of the memory cells including
portions of the channel material 32, gate dielectric material 40,
charge-trapping material 38, charge-blocking material 36 and
dielectric-barrier material 30. The memory cells also include
regions of the conductive material 26 of the conductive tiers 22.
The regions of the conductive material 26 within the memory cells
48 may be considered to be gate regions 50. Other regions of the
conductive material 26 may be considered to be routing regions
(wordline regions) 52 which couple the gate regions with other
circuitry. The routing regions 52 extend to the interconnects 42
within the staircase region 14.
[0025] A source-side select gate (SGS) 54 may be between the memory
cells 48 and the source structure 46.
[0026] The channel material 32 may be coupled to a bitline 54
through a drain-side select gate (SGD) 56.
[0027] A base 58 supports the structures of the memory array region
12 and the staircase region 14. The base 58 may be part of a
semiconductor die. The base 58 may comprise semiconductor material;
and may, for example, comprise, consist essentially of, or consist
of monocrystalline silicon. The base 58 may be referred to as a
semiconductor substrate. The term "semiconductor substrate" means
any construction comprising semiconductive material, including, but
not limited to, bulk semiconductive materials such as a
semiconductive wafer (either alone or in assemblies comprising
other materials), and semiconductive material layers (either alone
or in assemblies comprising other materials). The term "substrate"
refers to any supporting structure, including, but not limited to,
the semiconductor substrates described above. In some applications,
the base 58 may correspond to a semiconductor substrate containing
one or more materials associated with integrated circuit
fabrication. Such materials may include, for example, one or more
of refractory metal materials, barrier materials, diffusion
materials, insulator materials, etc.
[0028] Logic circuitries 60 and 62 are shown to be supported by the
base. Such logic circuitries may comprise, for example, CMOS. In
the illustrated application, the logic circuitry 60 comprises
sense-amplifier-circuitry (Sense Amplifier), and is electrically
coupled with the bitline 54; and the logic circuitry 62 comprises
wordline-driver-circuitry (Wordline Driver) and is electrically
coupled with the wordline levels (access levels) 22 through the
interconnects 42.
[0029] It can be difficult to form the interconnects 42 in the
staircase region 14. It can be particularly difficult to form
interconnects 42 to very deep tiers due to the high aspect ratios
of the deep openings used to reach the deep tiers. It would be
desirable to develop improved methods of forming the interconnects
42.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] FIG. 1 shows a block diagram of a prior art memory device
having a memory array with memory cells.
[0031] FIG. 2 shows a schematic diagram of the prior art memory
array of FIG. 1 in the form of a 3D NAND memory device.
[0032] FIG. 3 shows a cross-sectional view of the prior art 3D NAND
memory device of FIG. 2 in an X-X' direction.
[0033] FIG. 4 is a schematic diagram of a prior art NAND memory
array.
[0034] FIG. 5 is a diagrammatic top-down view of regions of a prior
art integrated assembly.
[0035] FIG. 6 is a diagrammatic cross-sectional side view of
regions of the prior art assembly of FIG. 5.
[0036] FIG. 7 is a diagrammatic cross-sectional side view of a
region of an example structure at an example process stage of an
example method.
[0037] FIG. 7A is a diagrammatic cross-sectional side view of
another region of the example structure of FIG. 7 at the same
example process stage as FIG. 7.
[0038] FIGS. 8-11 are diagrammatic cross-sectional side views of
the region of the example structure of FIG. 7 at sequential process
stages of an example method. The process stage of FIG. 8 may follow
that of FIG. 7.
[0039] FIG. 11A is a diagrammatic cross-sectional side view of the
region of FIG. 7A at an example process stage similar to that of
FIG. 11.
[0040] FIG. 12 is a diagrammatic cross-sectional side view of the
region of the example structure of FIG. 7 at a process stage of an
example method. The process stage of FIG. 12 may follow that of
FIG. 11.
[0041] FIG. 12A is a diagrammatic cross-sectional side view of the
region of FIG. 7A at an example process stage similar to that of
FIG. 12.
[0042] FIGS. 13-15 are diagrammatic cross-sectional side views of
the region of the example structure of FIG. 7 at sequential process
stages of an example method. The process stage of FIG. 13 may
follow that of FIG. 12.
[0043] FIGS. 16-19 are diagrammatic cross-sectional side views of
the region of the example structure of FIG. 7 at sequential process
stages of an example method. The process stage of FIG. 16 may
follow that of FIG. 13.
DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
[0044] Some embodiments include methods of forming interconnects to
specific steps within a staircase region of an integrated assembly.
Some embodiments include integrated assemblies having interconnects
electrically coupled with steps in a staircase region of an
integrated assembly. Example embodiments are described with
reference to FIGS. 7-19.
[0045] Referring to FIG. 7, a staircase region 14 of an integrated
assembly 10 is illustrated at an example process stage. The
staircase region includes a stack 20 of alternating first and
second levels 22 and 24. The first levels 22 comprise sacrificial
material 64, and the second levels 24 comprise insulative material
28.
[0046] The sacrificial material 64 may comprise any suitable
composition(s); and in some embodiments may comprise, consist
essentially of, or consist of silicon nitride.
[0047] The insulative material 28 may comprise any suitable
composition(s); and in some embodiments may comprise, consist
essentially of, or consist of silicon dioxide.
[0048] Some of the first and second levels 22/24 are configured as
steps 66. Each of the steps comprises one of the second levels 24
over an associated one of the first levels 22 (i.e., comprises the
insulative material 28 over the sacrificial material 64), and has
an upper surface 67.
[0049] The levels 22 and 24 may be of any suitable thicknesses; and
may be the same thickness as one another or different thicknesses
relative to one another. In some embodiments, the levels 22 and 24
may have vertical thicknesses within a range of from about 10
nanometers (nm) to about 400 nm.
[0050] The stack 20 may have any suitable number of the first and
second levels 22 and 24. For instance, in some embodiments the
stack 20 may have 8 of the first levels, 16 of the first levels, 32
of the first levels, 64 the first levels, 512 of the first levels,
1024 of the first levels, etc.; with such first levels ultimately
becoming conductive tiers analogous to those described above with
reference to FIG. 6
[0051] Only a lower region of the stack 20 is patterned into the
illustrated steps 66 of the illustrated interconnect region of
FIG.7. Other portions of the stack 20 may be patterned into steps
in other interconnect regions (analogous to the interconnect
regions 18 of FIG. 5).
[0052] FIG. 7A shows a memory array region 12 proximate the
staircase region 14 of FIG. 7, and at the same process stage as the
staircase region 14 of FIG. 7. The stack 20 extends across the
memory array region 12.
[0053] The portion of the stack 20 within the memory array region
12 may be referred to as a first portion (or first region) of the
stack, and the portion of the stack 20 within the staircase region
14 may be referred to as a second portion (or second region) of the
stack.
[0054] The source structure 46 (FIG. 6) and the base 58 (FIG. 6)
are not shown in FIGS. 7 and 7A to simplify the drawings. However,
it is to be understood that such structures may be present under
the stack 20 of FIGS. 7 and 7A.
[0055] Referring to FIG. 8, a protective liner 68 is formed over
the stack 20 within the staircase region 14. The protective liner
68 comprises a liner material 70. Such liner material may comprise
any suitable composition(s); and in some embodiments may comprise,
consist essentially of, or consist of one or more insulative
oxides. For instance, the liner material 70 may comprise, consist
essentially of, or consist of one or more of SiO, AlO, HfO, ZrO,
and TaO; where the chemical formulas indicate primary constituents
rather than specific stoichiometries.
[0056] The liner 68 may have any suitable thickness; and in some
embodiments may have a thickness within a range of from about 10 nm
to about 100 nm, within a range of from about 20 nm to about 50 nm,
etc.
[0057] Referring to FIG. 9, etch-stop material 72 is formed over
the protective liner 68. The etch-stop material forms an etch-stop
layer (structure) 74.
[0058] The etch-stop material 72 may comprise any suitable
composition(s), and may be insulative, semiconductive or
conductive. In some embodiments, the etch-stop material may
comprise, consist essentially of, or consist of one or more of
aluminum oxide, carbon-doped silicon nitride, silicon and tungsten.
If the etch-stop material comprises carbon-doped silicon nitride,
the carbon concentration may be within a range of from about 5
atomic percent (at %) to about 20 at %, within a range of from
about 10 at % to about 15 at %, etc. If the etch-stop stop material
comprises silicon, the silicon may be effectively undoped (i.e.,
may comprise less than or equal to about 10.sup.15 atoms/cm.sup.3
of conductivity-enhancing dopant therein). The silicon may be in
any suitable crystalline form, and in some embodiments may be
polycrystalline and/or amorphous.
[0059] The etch-stop layer 74 may have any suitable thickness; and
in some embodiments may have a thickness within a range of from
about 50 nm to about 250 nm, within a range of from about 20 nm to
about 100 nm, within a range of from about 40 nm to about 60 nm,
etc.
[0060] Referring to FIG. 10, a material 76 is formed over the
etch-stop material 72. The material 76 may be referred to as a fill
material. The material 76 is over the steps 66.
[0061] The material 76 may comprise any suitable composition(s);
and in some embodiments may comprise, consist essentially of, or
consist of silicon dioxide and/or doped silicate glass (e.g.,
borophosphosilicate glass, phosphosilicate glass, fluorosilicate
glass, etc.). In some embodiments the fill material 76 may comprise
a same composition as the protective material 70, and in other
embodiments the fill material 76 may comprise a different
composition than the protective material 70.
[0062] Referring to FIG. 11, a planarized surface 77 is formed to
extend across an upper surface of liner 68, and across the
materials 70, 72 and 76. The planarized surface 77 may be formed
utilizing any suitable processing, including, for example,
chemical-mechanical polishing (CMP). The planarized surface 77 may
be formed at any suitable level. In some embodiments, the
planarized surface 77 may be along the upper level 24 of stack 20
(i.e., along an upper surface of the material 28 of the upper level
24), rather than being along the upper surface of the liner 68.
[0063] FIG. 11A shows the memory array region 12 at a process stage
similar to that of FIG. 11 (and in some embodiments, the same as
that of FIG. 11). An opening 90 has been formed through the stack
20, and then the materials 32, 33, 36, 38 and 40 have been formed
within such opening. The material 68 of FIG. 11 may or may not
extend across the memory array region 12 of FIG. 11A, and in the
illustrated embodiment is not shown to be across the illustrated
portion of the memory array region.
[0064] The channel material 32 comprises semiconductor material;
and may comprise any suitable composition or combination of
compositions. For instance, the channel material 32 may comprise
one or more of silicon, germanium, III/V semiconductor materials
(e.g., gallium phosphide), semiconductor oxides, etc.; with the
term III/V semiconductor material referring to semiconductor
materials comprising elements selected from groups III and V of the
periodic table (with groups III and V being old nomenclature, and
now being referred to as groups 13 and 15). In some embodiments,
the channel material 32 may comprise, consist essentially of, or
consist of silicon.
[0065] The tunneling material (gate dielectric material) 40 may
comprise any suitable composition(s). In some embodiments, the
tunneling material 40 may comprise, for example, one or more of
silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide,
etc.
[0066] The charge-blocking material 36 may comprise any suitable
composition(s); and in some embodiments may comprise, consist
essentially of, or consist of silicon dioxide and/or one or more
high-k materials (e.g., aluminum oxide, zirconium oxide, hafnium
oxide, etc.); with the term "high-k" meaning a dielectric constant
greater than that of silicon dioxide.
[0067] The material 38 may be referred to as a charge-storage
material, and may comprise any suitable composition(s). In some
embodiments, the charge-storage material 38 may comprise
charge-trapping materials; such as, for example, silicon nitride,
silicon oxynitride, conductive nanodots, etc. For instance, in some
embodiments the charge-storage material 38 may comprise, consist
essentially of, or consist of silicon nitride.
[0068] The insulative material 33 may comprise any suitable
composition(s); and in some embodiments may comprise, consist
essentially of, or consist of silicon dioxide.
[0069] The channel material 82 is configured as a
channel-material-pillar 16 of the type described above with
reference to FIGS. 5 and 6. The illustrated channel-material-pillar
16 of FIG. 11A may be representative of a large number of
channel-material-pillars formed across the memory array region
12.
[0070] Referring to FIGS. 12 and 12A, the sacrificial material 64
(FIGS. 11 and 11A) is removed, and the conductive material 26 is
formed within the levels 22. Also, in the shown embodiment the
dielectric-barrier material 30 is formed along outer peripheral
surfaces of the conductive material 26.
[0071] The sacrificial material 64 (FIGS. 11 and 11A) may be
removed with an etch utilizing hot phosphoric acid. The protective
liner 68 may protect the etch-stop material 72 from being exposed
to such etch. If the etch-stop material 72 is resistant to the etch
utilized to remove the sacrificial material 64, the protective
liner 68 may be omitted.
[0072] The conductive material 26 may comprise any suitable
electrically conductive composition(s); such as, for example, one
or more of various metals (e.g., titanium, tungsten, cobalt,
nickel, platinum, ruthenium, etc.), metal-containing compositions
(e.g., metal silicide, metal nitride, metal carbide, etc.), and/or
conductively-doped semiconductor materials (e.g.,
conductively-doped silicon, conductively-doped germanium, etc.). In
some embodiments, the conductive material 26 may comprise a
tungsten core surrounded by a liner comprising titanium
nitride.
[0073] The dielectric-barrier material 30 may comprise any suitable
composition(s). In some embodiments, the dielectric-barrier
material 30 may comprise high-k material (for instance, one or more
of aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide,
etc.). In some embodiments, the dielectric-barrier material 30 may
comprise, consist essentially of, or consist of aluminum oxide.
[0074] The conductive material 26 within the steps 66 may be
considered to be configured as conductive layers 92, with each of
such conductive layers having an upper surface 93.
[0075] The configuration shown in the memory array region 12 of
FIG. 12A may comprise memory cells 48 analogous to those described
above with reference to FIG. 6. The conductive levels 22 may
comprise gate regions 50 and routing regions 52 analogous to those
described above with reference to FIG. 6. In some embodiments, the
conductive layers 92 may be referred to as gate/routing layers of a
memory array, with such layers extending into both the memory array
region 12 and the staircase region 14.
[0076] The process stage of FIG. 12A may be the same as that of
FIG. 12 in some embodiments. In such embodiments, the protective
liner 68 may or may not extend along an upper surface of the memory
array region 12 of FIG. 12A.
[0077] Referring to FIG. 13, openings 78 are formed to extend
through the fill material 76 to the etch-stop material 72. In the
illustrated embodiment, the openings 78 penetrate partially into
the etch-stop material. In other embodiments, the openings 78 may
stop at an upper surface of the etch-stop material. Each of the
openings 78 is aligned with one of the steps 66.
[0078] Referring to FIG. 14, the openings 78 are extended through
the etch-stop material 72, the protective material 70, the
insulative material 28 and the dielectric-barrier material 30 to
the upper surfaces 93 of the conductive layers 92 within the steps
66. In the illustrated embodiment, the openings 78 are extended
with one or more anisotropic etches through each of the materials
72, 70, 28 and 30 so that the openings have relatively straight
vertical sidewalls through the materials 72, 70, 28 and 30. In some
embodiments, the etch through the layer 74 to the protective liner
68 may be considered to comprise first etching conditions, and the
etch through the materials 70, 28 and 30 may be considered to
comprise additional etching conditions. The additional etching
conditions may or may not be the same as the first etching
conditions. The first etching conditions can be chosen for the
particular material 74. In some embodiments, the first etching
conditions may utilize one or both of hydrofluoric acid (HF) and
tetramethyl ammonium hydroxide (TMAH); and the layer 70 may
comprise silicon and/or carbon-doped silicon nitride. In some
embodiments, the additional etching conditions may utilize HF to
penetrate through oxide-containing materials 70, 28 and 30.
[0079] In some embodiments, the openings 78 may penetrate into the
conductive material 52 of the layers 92 rather than stopping at the
upper surfaces 93.
[0080] Although the replacement of the sacrificial material 64
(FIG. 11) is shown occurring at the process stage of FIG. 12, it is
to be understood that in other embodiments such replacement may
occur at any process stage prior to that of FIG. 14. It is desired
that the conductive layers 92 be present at the process stage of
FIG. 14 so that the openings 78 may stop on (or, in some
embodiments, may extend into) such conductive material.
[0081] Referring to FIG. 15, conductive material 96 is formed
within the openings 78 to form interconnects 42 analogous to those
described above with reference to FIG. 6.
[0082] The conductive material 96 may comprise any suitable
electrically conductive composition(s); such as, for example, one
or more of various metals (e.g., titanium, tungsten, cobalt,
nickel, platinum, ruthenium, etc.), metal-containing compositions
(e.g., metal silicide, metal nitride, metal carbide, etc.), and/or
conductively-doped semiconductor materials (e.g.,
conductively-doped silicon, conductively-doped germanium, etc.). In
some embodiments, the conductive material 96 may be a
metal-containing material, and may comprise one or more of
tungsten, titanium nitride, tungsten nitride, etc.
[0083] The conductive interconnects 42 of FIG. 15 may be coupled
with driver circuitry 62 analogous to that shown in FIG. 6.
[0084] A planarized surface 97 is shown extending across the
interconnects 42 and the fill material 76. The planarized surface
97 may be formed with any suitable methodology, including, for
example, CMP.
[0085] As discussed above, in some embodiments the etch-stop
material 72 may be electrically conductive (e.g., may comprise
tungsten). In such embodiments, it may be advantageous to
electrically isolate the etch stop material 72 from the
interconnects 42. FIGS. 16-19 show example process stages of an
example method for electrically isolating the etch-stop material
from the interconnects 42.
[0086] Referring to FIG. 16, the staircase region 14 is shown at a
process stage that may follow that of FIG. 13. Isotropic etching is
utilized to remove regions of the material 72 and form cavities 99
extending under the fill material 76. The isotropic etching of FIG.
16 may utilize any suitable etchant(s) and conditions. For
instance, in some embodiments the isotropic etching may utilize one
or more of HF, TMAH and hot phosphoric acid if the material 72
comprises silicon and/or carbon-doped silicon nitride.
[0087] Referring to FIG. 17, insulative spacer material 102 is
formed within the cavities 99 (FIG. 16) to form insulative spacers
100. The spacer material 102 may comprise any suitable insulative
composition(s); and in some embodiment may comprise, consist
essentially of, or consist of one or more of silicon dioxide,
silicon nitride, aluminum oxide, etc.
[0088] The spacers 100 may be formed with any suitable processing.
For instance, a liner of the spacer material 102 may be formed
within the openings 78 and cavities 99, and then excess spacer
material may be removed with an etch while leaving the spacers 100
remaining within the cavities 99 (FIG. 16).
[0089] Referring to FIG. 18, the openings 78 are extended through
the protective material 70, the insulative material 28 and the
dielectric-barrier material 30 to the upper surfaces 93 of the
conductive layers 92 within the steps 66. Such may be accomplished
with etching analogous to that described above with reference to
FIG. 14.
[0090] Referring to FIG. 19, conductive material 96 is formed
within the openings 78 (FIG. 18) to form interconnects 42 analogous
to those described above with reference to FIG. 6. The conductive
interconnects 42 are laterally spaced from the layer 74 (which may
be conductive material; such as, for example, tungsten) by the
insulative spacers 100.
[0091] The conductive interconnects 42 of FIG. 19 may be coupled
with driver circuitry 62 analogous to that shown in FIG. 6.
[0092] In the illustrated embodiments of FIGS. 15 and 19, the layer
74 is over the steps 66 and along a lower portion of the stack 20,
and is spaced from the stack 20 by an intervening insulative region
corresponding to the liner material 70.
[0093] The processing described herein may advantageously improve
formation of conductive interconnects (42) to the deep steps within
a staircase region by utilizing the etch-stop material (72) as a
landing pad for the openings (78) punched through the fill material
(76). The etch-stop material may be tailored to completely stop
both low and high aspect ratio openings (78) by tailoring the
thickness and/or composition of the etch-stop. In some
applications, the tailorability of the etch-stop material is
enhanced by having the etch-stop material float on (formed over)
the protective material (70).
[0094] In some embodiments, the etch-stop material (74) may be
chosen to be selectively removable relative to the insulative
material (28) of the insulative tiers (24), and relative to the
conductive material (26) of the conductive tiers (22).
[0095] In some embodiments, the processes described herein may
advantageously provide scaling capability and location flexibility
for staircase contact structures (interconnects).
[0096] The assemblies and structures discussed above may be
utilized within integrated circuits (with the term "integrated
circuit" meaning an electronic circuit supported by a semiconductor
substrate); and may be incorporated into electronic systems. Such
electronic systems may be used in, for example, memory modules,
device drivers, power modules, communication modems, processor
modules, and application-specific modules, and may include
multilayer, multichip modules. The electronic systems may be any of
a broad range of systems, such as, for example, cameras, wireless
devices, displays, chip sets, set top boxes, games, lighting,
vehicles, clocks, televisions, cell phones, personal computers,
automobiles, industrial control systems, aircraft, etc.
[0097] Unless specified otherwise, the various materials,
substances, compositions, etc. described herein may be formed with
any suitable methodologies, either now known or yet to be
developed, including, for example, atomic layer deposition (ALD),
chemical vapor deposition (CVD), physical vapor deposition (PVD),
etc.
[0098] The terms "dielectric" and "insulative" may be utilized to
describe materials having insulative electrical properties. The
terms are considered synonymous in this disclosure. The utilization
of the term "dielectric" in some instances, and the term
"insulative" (or "electrically insulative") in other instances, may
be to provide language variation within this disclosure to simplify
antecedent basis within the claims that follow, and is not utilized
to indicate any significant chemical or electrical differences.
[0099] The terms "electrically connected" and "electrically
coupled" may both be utilized in this disclosure. The terms are
considered synonymous. The utilization of one term in some
instances and the other in other instances may be to provide
language variation within this disclosure to simplify antecedent
basis within the claims that follow.
[0100] The particular orientation of the various embodiments in the
drawings is for illustrative purposes only, and the embodiments may
be rotated relative to the shown orientations in some applications.
The descriptions provided herein, and the claims that follow,
pertain to any structures that have the described relationships
between various features, regardless of whether the structures are
in the particular orientation of the drawings, or are rotated
relative to such orientation.
[0101] The cross-sectional views of the accompanying illustrations
only show features within the planes of the cross-sections, and do
not show materials behind the planes of the cross-sections, unless
indicated otherwise, in order to simplify the drawings.
[0102] When a structure is referred to above as being "on",
"adjacent" or "against" another structure, it can be directly on
the other structure or intervening structures may also be present.
In contrast, when a structure is referred to as being "directly
on", "directly adjacent" or "directly against" another structure,
there are no intervening structures present. The terms "directly
under", "directly over", etc., do not indicate direct physical
contact (unless expressly stated otherwise), but instead indicate
upright alignment.
[0103] Structures (e.g., layers, materials, etc.) may be referred
to as "extending vertically" to indicate that the structures
generally extend upwardly from an underlying base (e.g.,
substrate). The vertically-extending structures may extend
substantially orthogonally relative to an upper surface of the
base, or not.
[0104] Some embodiments include a method of forming an integrated
assembly. A stack of alternating first and second levels is formed.
The first levels include sacrificial material and the second levels
include insulative material. At least some of the first and second
levels are configured as steps. Each of the steps includes one of
the second levels over an associated one of the first levels, and
has an upper surface corresponding to an upper surface of said one
of the second levels. An etch-stop material is formed over the
stack. Fill material is formed over the etch-stop material. The
sacrificial material is removed, and conductive layers are formed
within the first levels. The conductive layers within the steps
have upper surfaces. Openings are formed to extend through the fill
material to the etch-stop material. The openings are extended
through the etch-stop material and to the upper surfaces of the
conductive layers within the steps. Conductive interconnects are
formed within the extended openings.
[0105] Some embodiments include a method of forming an integrated
assembly. A stack of alternating first and second levels is formed.
The stack has a first region within a memory array region, and has
a second region within a staircase region proximate the memory
array region. The first levels comprise sacrificial material and
the second levels comprise insulative material. At least some of
the first and second levels are configured as steps within the
staircase region. Each of the steps comprises one of the second
levels over an associated one of the first levels, and has an upper
surface corresponding to an upper surface of said one of the second
levels. A protective liner is formed over the second region of the
stack. An etch-stop material is formed over the second region of
the stack and over the protective liner. A fill material is formed
over the steps. The fill material is over the etch-stop material.
The sacrificial material is removed, and conductive material is
formed within the first levels. The conductive material within the
steps is configured as conductive layers having upper surfaces.
Openings are formed to extend through the fill material to the
etch-stop material. The openings are extended through the etch-stop
material to the protective liner with first etching conditions. The
openings are extended through the protective liner and to the upper
surfaces of the conductive layers within the steps with additional
etching conditions. Conductive interconnects are formed within the
extended openings.
[0106] Some embodiments include an integrated assembly having a
stack of alternating first and second levels. The first levels
contain conductive material and the second levels contain
insulative material. At least some of the first and second levels
are configured as steps. Each of the steps has one of the second
levels over an associated one of the first levels. A layer is over
the steps and is spaced from the stack by an intervening insulative
region. Insulative material is over the layer. Conductive
interconnects extend through the insulative material, through the
layer, through the intervening insulative region and to the
conductive material within the first levels of the steps.
[0107] In compliance with the statute, the subject matter disclosed
herein has been described in language more or less specific as to
structural and methodical features. It is to be understood,
however, that the claims are not limited to the specific features
shown and described, since the means herein disclosed comprise
example embodiments. The claims are thus to be afforded full scope
as literally worded, and to be appropriately interpreted in
accordance with the doctrine of equivalents.
* * * * *