U.S. patent application number 17/302099 was filed with the patent office on 2021-08-26 for selective-area growth of iii-v materials for integration with silicon photonics.
The applicant listed for this patent is Cisco Technology, Inc.. Invention is credited to Jock T. BOVINGTON, Vipulkumar K. PATEL, Dominic F. SIRIANI.
Application Number | 20210265806 17/302099 |
Document ID | / |
Family ID | 1000005570236 |
Filed Date | 2021-08-26 |
United States Patent
Application |
20210265806 |
Kind Code |
A1 |
SIRIANI; Dominic F. ; et
al. |
August 26, 2021 |
SELECTIVE-AREA GROWTH OF III-V MATERIALS FOR INTEGRATION WITH
SILICON PHOTONICS
Abstract
Embodiments provide for selective-area growth of III-V materials
for integration with silicon photonics. The resulting platform
includes a substrate; an insulator, extending a first distance from
the substrate, including a passive optical component at a second
distance from the substrate less than the first distance, and
defining a pit extending to the substrate; and a III-V component,
extending from the substrate within in the pit defined in the
insulator, the III-V component including a gain medium included at
the second distance from the substrate and optically coupled with
the passive optical component. The pit may define an Optical
Coupling Interface between the III-V component and the passive
optical component, or a slit defined between the III-V component
and the passive optical component may define the Optical Coupling
Interface.
Inventors: |
SIRIANI; Dominic F.;
(Lansdale, PA) ; BOVINGTON; Jock T.; (La Mesa,
CA) ; PATEL; Vipulkumar K.; (Breinigsville,
PA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Cisco Technology, Inc. |
San Jose |
CA |
US |
|
|
Family ID: |
1000005570236 |
Appl. No.: |
17/302099 |
Filed: |
April 23, 2021 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
16203463 |
Nov 28, 2018 |
11018473 |
|
|
17302099 |
|
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G02B 2006/12121
20130101; G02B 6/122 20130101; H01S 5/021 20130101; H01S 5/026
20130101; H01S 5/028 20130101; G02B 6/131 20130101; H01S 5/1028
20130101; H01S 5/343 20130101; H01S 5/1014 20130101; G02B 6/136
20130101; G02B 2006/12061 20130101 |
International
Class: |
H01S 5/026 20060101
H01S005/026; G02B 6/122 20060101 G02B006/122; H01S 5/343 20060101
H01S005/343; G02B 6/136 20060101 G02B006/136; H01S 5/10 20060101
H01S005/10; G02B 6/13 20060101 G02B006/13; H01S 5/028 20060101
H01S005/028; H01S 5/02 20060101 H01S005/02 |
Claims
1. A Silicon Photonic Platform, comprising: a silicon substrate; a
dielectric, extending a first distance from the silicon substrate,
including a passive optical component at a second distance from the
silicon substrate less than the first distance, and defining a pit
extending to the silicon substrate; and a III-V component,
extending from the silicon substrate within in the pit defined in
the dielectric, the III-V component including an active gain medium
included at the second distance from the silicon substrate and
optically coupled with the passive optical component.
2. The Silicon Photonic Platform of claim 1, wherein an Optical
Coupling Interface (OCI) between the passive optical component and
the active gain medium includes an optical coating.
3. The Silicon Photonic Platform of claim 1, wherein the dielectric
and the III-V component define a slot defining an airgap Optical
Coupling Interface (OCI) between the passive optical component and
the active gain medium.
4. The Silicon Photonic Platform of claim 1, wherein the active
gain medium defines one of a plurality of quantum dots or a
plurality of quantum wells that when exposed to a current generates
coherent light.
5. The Silicon Photonic Platform of claim 1, the III-V component
includes a first cladding layer formed on the silicon substrate,
and a second cladding layer formed on the active gain medium.
6. The Silicon Photonic Platform of claim 1, wherein the passive
optical component includes a silicon waveguide and at least one of:
a silicon nano-taper coupler; and a nitride prong coupler.
7. The Silicon Photonic Platform of claim 1, further comprising: a
contact pad formed on the III-V component.
8. The Silicon Photonic Platform of claim 1, wherein the dielectric
and the III-V component extend to a second height from the silicon
substrate.
9. The Silicon Photonic Platform of claim 1, wherein the silicon
substrate is an off-cut Silicon material, cut between 1.degree. and
10.degree. from a material matrix axis of the silicon
substrate.
10. The Silicon Photonic Platform of claim 1, further comprising a
carrier, including: a carrier substrate; a carrier dielectric
extending from the carrier substrate for a third distance to a
first surface and including a carrier waveguide at a fourth
distance from the first surface and defining a pocket; wherein the
silicon substrate is connected to the first surface; and wherein
the dielectric and the III-V component are located in the pocket to
align the passive optical component with the carrier waveguide such
that the second distance and the fourth distance are equal.
11. A device, comprising: a substrate; a first dielectric layer
formed on the substrate; a passive photonic layer formed on the
first dielectric layer, defining a silicon waveguide; a second
dielectric layer formed on the passive photonic layer; wherein the
first dielectric layer, the passive photonic layer, and the second
dielectric layer define a pit that defines an Optical Coupling
Interface (OCI) with the silicon waveguide; and wherein the OCI
includes an optical coating affecting a reflectivity of an
interface between the silicon waveguide and an active III-V
component formed on the substrate within the pit.
12. The device of claim 11, wherein the first dielectric layer and
the second dielectric layer are disposed on opposing sides of the
passive photonic layer.
13. The device of claim 11, the substrate is an off-cut Silicon
material, cut between 1.degree. and 10.degree. from a material
matrix axis of the substrate.
14. The device of claim 11, wherein the passive photonic layer
further includes one of: a silicon nano-taper coupler; or a nitride
prong coupler.
15. A photonic element, comprising: a passive photonic element
including a waveguide within a dielectric; and an active III-V
component formed in a pit defined in the passive photonic element,
wherein the active III-V component includes a III-V gain medium
that is aligned to butt couple with the waveguide.
16. The photonic element of claim 15, wherein the III-V gain medium
is separated from the waveguide by a slot defined between the
active III-V component and the passive photonic element that
defines an optical coupling interface (OCI) between the passive
photonic element and the active III-V component.
17. The photonic element of claim 16, wherein the slot includes an
optical coating configured to affect a reflectivity of the OCI.
18. The photonic element of claim 15, wherein: the passive photonic
element includes a second waveguide within the dielectric on an
opposite side relative to the pit of the waveguide; and wherein the
III-V gain medium is aligned to butt couple with the second
waveguide.
19. The photonic element of claim 15, further comprising: a
substrate on which the passive photonic element is formed at a
first time and on which the active III-V component is formed at a
second time, different from the first time.
20. The photonic element of claim 15, wherein the III-V gain medium
includes a plurality of quantum dots.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of co-pending U.S. patent
application Ser. No. 16/203,463, filed Nov. 28, 2018. The
aforementioned related patent application is herein incorporated by
reference in its entirety
TECHNICAL FIELD
[0002] Embodiments presented in this disclosure generally relate to
photonic integrated circuits. More specifically, embodiments
disclosed herein relate to the fabrication of active gain materials
for use with a silicon photonics platform.
BACKGROUND
[0003] Photonic Integrated Circuits (PICs) may include both active
(i.e., powered) components, such as laser emitters, laser
receivers, etc., and passive (i.e., not powered) components, such
as waveguides, optical couplers, etc., which may be used as lasers,
amplifiers, or the like. Many active components are made from III-V
materials (i.e., compounds that include at least one Group III
element (such as Boron, Aluminum, Gallium, Indium, or Thallium) and
at least one Group V element (such as Nitrogen, Phosphorus,
Arsenic, Antimony, or Bismuth)), and are mated to passive
components that include Silicon (such as a Silicon substrate or a
SiO.sub.2 Interlayer Dielectric). Heterogeneous processes may
include a coupon attachment of a III-V material to a Silicon
material or an epitaxy deposition of a III-V material to a Silicon
material.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] So that the manner in which the above-recited features of
the present disclosure can be understood in detail, a more
particular description of the disclosure, briefly summarized above,
may be had by reference to embodiments, some of which are
illustrated in the appended drawings. It is to be noted, however,
that the appended drawings illustrate typical embodiments and are
therefore not to be considered limiting; other equally effective
embodiments are contemplated.
[0005] FIG. 1 illustrates isometric cutaway views of integrating a
III-V component with a Silicon Photonic platform in various stages
of fabrication via selective area growth, according to embodiments
of the present disclosure.
[0006] FIG. 2 illustrates cutaway views of integrating a III-V
component with a Silicon Photonic platform in various stages of
fabrication via selective area growth, according to embodiments of
the present disclosure.
[0007] FIG. 3 is a flowchart of a method for fabricating a Silicon
Photonic platform with a III-V component integrated via selective
area growth, according to embodiments of the present
disclosure.
[0008] FIG. 4 illustrates cutaway views of integrating a III-V
component with a Silicon Photonic platform in various stages of
fabrication via selective area growth, according to embodiments of
the present disclosure.
[0009] FIG. 5 is a flowchart of a method for fabricating a Silicon
Photonic platform with a III-V component integrated via selective
area growth, according to embodiments of the present
disclosure.
[0010] FIG. 6 illustrates an optical assembly with an integrated
III-V component in a Silicon Photonic platform, according to
embodiments of the present disclosure.
[0011] FIG. 7 illustrates a second optical assembly using a first
optical assembly with an integrated III-V component in a Silicon
Photonic platform as a sub-assembly with a carrier, according to
embodiments of the present disclosure.
[0012] To facilitate understanding, identical reference numerals
have been used, where possible, to designate identical elements
that are common to the figures. It is contemplated that elements
disclosed in one embodiment may be beneficially used in other
embodiments without specific recitation.
DESCRIPTION OF EXAMPLE EMBODIMENTS
Overview
[0013] One embodiment presented in this disclosure provides a
method for selective-area growth of III-V materials for integration
with silicon photonics, the method comprising: fabricating a
photonic element on a substrate; forming an insulator on the
photonic element; etching a pit through the insulator to the
substrate, the pit defining an optical coupling interface (OCI) for
the photonic element; forming an optical coating on the OCI
affecting a reflectivity of the OCI; and forming a III-V component
in the pit, the III-V component butt coupling with the photonic
element via the OCI.
[0014] One embodiment presented in this disclosure provides a
method for selective-area growth of III-V materials for integration
with silicon photonics, the method comprising: fabricating a
photonic element, including a substrate; forming an insulator on
the photonic element; etching a pit through the insulator to the
substrate; forming a III-V component in the pit, the III-V
component butt coupling with the photonic element; and etching a
slot between the III-V component and the insulator, the slot
defining an optical coupling interface (OCI) between the photonic
element and the III-V component.
[0015] One embodiment presented in this disclosure provides a
Silicon Photonic Platform produced, including: a silicon substrate;
an insulator, extending a first distance from the substrate,
including a passive optical component at a second distance from the
substrate less than the first distance, and defining a pit
extending to the substrate; and a III-V component, extending from
the substrate within in the pit defined in the insulator, the III-V
component including a gain medium included at the second distance
from the substrate and optically coupled with the passive optical
component.
EXAMPLE EMBODIMENTS
[0016] A Selective-Area Growth (SAG) of III-V materials for
integration with Silicon Photonics (SiPh) is provided herein to
produce Photonic Integrated Circuits (PICs) with active and passive
components using both III-V and Silicon materials that are
integrated with one another. The III-V material used for active
components is selectively formed in regions of a SiPh platform
(e.g., Silicon On Insulator (SOI) wafers or Silicon Nitride (SiN)
waveguides) and butt couples with the SiPh waveguides. Various
Optical Coupling Interfaces (OCI) such as air voids or optical
coatings may be used in various embodiments between the active and
passive components of the PIC. The III-V material is selectively
formed (e.g., grown, bonded) in a cavity defined in the Si material
in contact with the substrate, which allows superior thermal
performance and a more efficient fabrication (avoiding material
waste and coupon bonding processes) over other heterogeneous PIC
fabrication processes, which can result in poor thermal performance
and material waste in creating the PIC compared to the processes
described herein.
[0017] FIG. 1 illustrates isometric cutaway views 100a-c
(generally, view 100) of integrating a III-V component 160 with a
SiPh platform 140 in various stages of fabrication via selective
area growth. The SiPh platform 140 includes a substrate 110, one or
more layers of an insulator 120, and a passive optical layer
130.
[0018] The substrate 110 provides a base from which the other
layers and components of the SiPh platform 140 are fabricated
(e.g., via epitaxial growth, vapor deposition, eutectic bonding,
etc.). In various embodiments, the substrate 110 is a Si wafer
(including Silicon Nitride (SiN) or Silicon Dioxide (SiO.sub.2)
matrices) or a wafer made from a III-V material, such as, for
example, Boron-Nitride (BN), Gallium-Nitride (GaN), GaAs (Gallium
Arsenide), or InP (Indium Phosphide) that are cut on-axis for the
material matrix thereof (i.e., using an on-cut III-V substrate
material). In embodiments using a Si wafer, the wafer may be an
on-axis or an off-axis cut for the crystalline structure of the Si
material, which varies the material lattice of the face of the
substrate 110 available for growth of additional layers of Si or
III-V materials. For example, an off-axis Si wafer (i.e., a
substrate 110 using an off-cut Si material may provide a lower
number defects when forming a III-V material thereon than an
on-axis Si wafer (i.e., a substrate 110 using an on-cut Si
material), but may require different processing techniques than
providing an on-axis Si wafer. In various embodiments using an
off-axis Si material, the off-cut is between 1 degree and 10
degrees from the material matrix axis, for example, an off-cut from
the material matrix axis of the substrate of 6 degrees.
[0019] The insulator 120 includes SiO.sub.2 or SiN materials, which
may be doped or processed to include various optical elements (such
as the passive optical layer 130) and physical elements, such as,
for example, alignment features, mating faces, and
Through-Silicon-Vias (TSV).
[0020] The passive optical layer 130 includes one or more photonic
elements secured in the insulator 120. A silicon waveguide (with
various splitters, modulators, routing, etc.) is one example of a
photonic element. Other examples of photonic elements include
butt-coupling structures, such as, a nitride prong coupler or a
silicon nano-taper (of the waveguide), evanescent coupling
structures, such as, adiabatic or directional couplers, and passive
alignment features.
[0021] View 100b shows a pit 150 defined in the SiPh platform 140
shown in view 100a that extends to the substrate 110. Although
illustrated as defining an area of a rectangular prism, the pit 150
may be defined in areas having different shapes in other
embodiments, such as, for example, a cylindrical area, a pyramidal
area, a trapezoidal area, etc. The area defining the pit 150
provides space for a III-V component 160 to be formed from the
substrate 110 to butt-couple with the other layers of the SiPh
platform 140. In various embodiments, the III-V component 160
includes an optical gain medium that is aligned with the coupling
features defined in the passive optical layer 130 at a first height
relative to the substrate 110. View 100c shows that the III-V
component 160 may form to a second height relative to the substrate
110 that the insulator 120 is also formed to, but in other
embodiments the III-V component 160 may be formed to a different
height than the insulator 120 relative to the substrate 110.
[0022] The pit 150 also defines an Optical Coupling Interface (OCI)
170 between the III-V component 160 and passive optical layer 130.
In various embodiments, the OCI 170 may include an optical layer
(e.g., 210 or 410) that is deposited or patterned either before or
after the III-V component 160 is selectively formed in the pit 150.
The optical layer may be a low-reflection or anti-reflection
coating, a highly-reflective coating, an airgap, or a coating to
impart a particular refractive index. Examples of OCI coatings
include, but are not limited to: SiN (Silicon Nitride),
Ta.sub.2O.sub.5 (Tantalum Pentoxide), TiO.sub.2 (Titanium Dioxide),
etc.
[0023] FIG. 2 illustrates cutaway views 200a-f (generally, view
200) of integrating a III-V component 160 with a SiPh platform 140
in various stages of fabrication via selective area growth. FIG. 2
may be understood in conjunction with the method 300 described in
relation to the flowchart of FIG. 3.
[0024] At block 310, a fabricator fabricates the SiPh platform 140
to include a substrate 110, an insulator 120, and a passive optical
layer 130. (First view 200a). In various embodiments, the
fabricator creates the substrate from a bulk material (e.g., SiN,
SiO.sub.2, GaAs, InP) having an axis-aligned crystalline structure.
In various embodiments, the fabricator cuts the bulk material into
a wafer of desired dimensions with respect to the axis of alignment
of the material matrix with cuts made in parallel and
perpendicularly to the axis (i.e., on-axis) or at an offset from
the axis (i.e., off-axis). The fabricator forms an insulator 120
from a first surface of the substrate 110, and forms various
photonic elements in a passive optical layer 130 in the insulator
120. In various embodiments, the fabricator controls the height at
which the photonic elements of the passive optical layer 130 so
that various photonic elements are formed at known heights relative
to the first surface of the substrate. The fabricator further
shapes the photonic elements in the optical layer 130 into desired
shapes and lengths via one or more etching processes, such applying
a nano-taper to an end of a waveguide. (Second view 200b).
[0025] At block 320, the fabricator applies additional insulator
120 to capture the photonic elements of the passive optical layer
130 in the insulator 120. (Third view 200c). The fabricator forms
the insulator 120 to a desired second height relative to the
insulator 120 to define a form factor for the SiPh platform
140.
[0026] At block 330, the fabricator etches a pit 150 in the SiPh
platform 140. (Fourth view 200d). The pit 150 may be defined in
various shapes, and exposes a surface that may form an OCI 170 or
over which an optical coating 210 may be grown to form an OCI 170.
In some embodiments, the fabricator physically etches the pit 150
into the SiPh platform 140, while in other embodiments, the
fabricator chemically etches the pit 150 into the SiPh platform 140
(e.g., applying a resist mask to portions of the SiPh platform 140
that are not to be etched out, and applying a caustic or reactive
chemical etchant to the SiPh platform). In various embodiments, the
fabricator etches the pit 150 to expose a first end of the photonic
elements of the passive optical layer 130 to the pit 150, or leaves
a portion of the insulator 120 of a desired thickness to separate
the first end of the photonic elements from the pit 150.
[0027] At block 340, the fabricator processes the OCI 170 for the
SiPh platform 140. (Fifth view 200e). In various embodiments, the
fabricator forms one or more optical layers on a face of the SiPh
platform 140 exposed by the pit 150. In some embodiments, the
fabricator physically or chemically etches the exposed face of the
pit 150 to provide a surface with a desired smoothness and distance
from the photonic elements of the SiPh platform 140 (e.g., a fine
etch or polish following a rough etch per block 330). For example,
the fabricator may form an optical coating to affect a reflectivity
or refractivity of the OCI 170.
[0028] At block 350, the fabricator forms a III-V component 160 in
the pit 150 via selective area growth. (Sixth view 200f). In
various embodiments, the fabricator applies a resist mask to the
insulator 120 (and/or the OCI 170) to ensure that III-V materials
are not formed on surfaces other than the exposed surface of the
substrate 110. In various embodiments, the III-V component 160 is
selectively formed in the pit 150 via epitaxial growth process,
including, but not limited to: Chemical Vapor Deposition (CVD),
Metal-Organic CVD (MOCVD), Molecular Beam Epitaxy (MBE),
Vapor-Phase Epitaxy (VPE), Liquid-Phase Epitaxy (LPE), Solid-Phase
Epitaxy (SPE), and Hydride Vapor Phase Epitaxy. The III-V material
may include, but is not limited to: GaAs, GaN, GaSb, InSb, InAs,
InP, etc.
[0029] The fabricator may form the III-V component 160 in stages
from the substrate 110 to include cladding layers 220 of a III-V
material surrounding an active gain medium 230. The active gain
medium 230 may include quantum dots or quantum wells or quantum
wires or bulk material to provide one or more of lasing or optical
amplification when current is applied across the active gain medium
230 or to produce a voltage difference when an external light
source is applied to the active gain medium 230 for optical
detection. The cladding layers 220 are formed to surround the
active gain medium 230 and provide a waveguide to amplify and
direct light produced by the active gain medium 230 outward in one
or more directions. In some embodiments, the III-V materials used
in the cladding layers 220 are different than the III-V materials
used in the active gain medium 230 or include different
dopants.
[0030] In various embodiments, the active gain medium 230 includes
a plurality of quantum dots or quantum wells that, when stimulated
by an applied electrical current, emit photons. Quantum dots and
quantum wells are nano-structures that exhibit various properties,
such as light generation, based on quantum mechanical effects.
Quantum wells are two-dimensional structures formed by a thin layer
of a first material surrounded by wider-bandgap material and that
allow electronic capture in one dimension (allowing planar
two-dimensional movement). In contrast, quantum dots act as
zero-dimensional entities, which enables three-dimensional capture
of excited electrons (not allowing movement). The quantum dots are
surrounded by the waveguides of the cladding layers 220 and are
made of materials that have narrower bandgaps than the material of
the cladding layers 220. As will be appreciated, the precise size,
shape, and material of the quantum dots or wells will affect the
color of coherent light produced by the laser.
[0031] The fabricator forms the III-V component 160 in the pit 150
to optically couple (via butt-coupling) with the photonic elements
in the passive optical layer 130. The active gain medium 230 is
formed at a predetermined height relative to the substrate 110 to
allow for alignment with earlier-fabricated photonic elements in
the passive optical layer 130. Additionally, the upper cladding
layer 220 is formed to a predetermined height relative to the
substrate 110 (e.g., the height of the insulator 120 surrounding
the pit 150) to define the form factor for the SiPh platform
140.
[0032] As will be appreciated, various processes may be applied to
etch the SiPh platform 140 into a desired shape or profile, add one
or more photonic elements, and/or process the SiPh platform 140
into a final assembly. Similarly, various wafer processes may be
performed on the SiPh platform 140 prior to or after bonding and/or
forming the other layers, such as, for example, the inclusion of
TSVs, alignment features, dicing a wafer into several dies for the
SiPh platform 140, etc.
[0033] FIG. 4 illustrates side views 400a-g (generally, view 400)
of integrating a III-V component 160 with a SiPh platform in
various stages of fabrication via selective area growth. FIG. 4 may
be understood in conjunction with the method 500 described in
relation to the flowchart of FIG. 5.
[0034] At block 510, a fabricator fabricates the SiPh platform 140
to include a substrate 110, an insulator 120, and a passive optical
layer 130. (First view 400a). In various embodiments, the
fabricator creates the substrate from a bulk material (e.g., SiN,
SiO.sub.2, GaAs, InP) having an axis-aligned crystalline structure.
In various embodiments, the fabricator cuts the bulk material into
a wafer of desired dimensions with respect to the axis of alignment
of the material matrix with cuts made in parallel and
perpendicularly to the axis (i.e., on-axis) or at an offset from
the axis (i.e., off-axis). The fabricator forms an insulator 120
from a first surface of the substrate 110, and forms various
photonic elements in a passive optical layer 130 in the insulator
120. In various embodiments, the fabricator controls the height at
which the photonic elements of the passive optical layer 130 so
that various photonic elements are formed at known heights relative
to the first surface of the substrate. The fabricator further
shapes the photonic elements in the optical layer 130 into desired
shapes and lengths via one or more etching processes, such applying
a nano-taper to an end of a waveguide. (Second view 400b).
[0035] At block 520, the fabricator applies additional insulator
120 to capture the photonic elements of the passive optical layer
130 in the insulator 120. (Third view 400c). The fabricator forms
the insulator 120 to a desired second height relative to the
insulator 120 to define a form factor for the SiPh platform
140.
[0036] At block 530, the fabricator etches a pit 150 in the SiPh
platform 140. (Fourth view 400d). The pit 150 may be defined in
various shapes, and exposes a surface that may form an OCI 170 or
over which an optical coating 210 may be grown to form an OCI 170.
In some embodiments, the fabricator physically etches the pit 150
into the SiPh platform 140, while in other embodiments, the
fabricator chemically etches the pit 150 into the SiPh platform 140
(e.g., applying a resist mask to portions of the SiPh platform 140
that are not to be etched out, and applying a caustic or reactive
chemical etchant to the SiPh platform). In various embodiments, the
fabricator etches the pit 150 to expose a first end of the photonic
elements of the passive optical layer 130 to the pit 150, or leaves
a portion of the insulator 120 of a desired thickness to separate
the first end of the photonic elements of from the pit 150.
[0037] At block 540, the fabricator forms a III-V component 160 in
the pit 150 via selective area growth. (Fifth view 400e). In
various embodiments, the fabricator applies a resist mask to the
insulator 120 to ensure that III-V materials are not formed on
surfaces other than the exposed surface of the substrate 110. In
various embodiments, the III-V component 160 is selectively formed
in the pit 150 via epitaxial growth process, including, but not
limited to: Chemical Vapor Deposition (CVD), Metal-Organic CVD
(MOCVD), Molecular Beam Epitaxy (MBE), Vapor-Phase Epitaxy (VPE),
Liquid-Phase Epitaxy (LPE), Solid-Phase Epitaxy (SPE), and Hydride
Vapor Phase Epitaxy. The III-V material may include, but is not
limited to: GaAs, GaN, GaSb, InSb, InAs, InP, etc.
[0038] The fabricator may form the III-V component 160 in stages
from the substrate 110 to include cladding layers 220 of a III-V
material surrounding an active gain medium 230. The active gain
medium 230 may include quantum dots or quantum wells or quantum
wires or bulk material to provide one or more of lasing or optical
amplification when current is applied across the active gain medium
230 or to produce a voltage difference when an external light
source is applied to the active gain medium 230 for optical
detection. The cladding layers 220 are formed to surround the
active gain medium 230 and provide a waveguide to amplify and
direct light produced by the active gain medium 230 outward in one
or more directions. In some embodiments, the III-V materials used
in the cladding layers 220 are different than the III-V materials
used in the active gain medium 230 or include different
dopants.
[0039] In various embodiments, the active gain medium 230 includes
a plurality of quantum dots or quantum wells that, when stimulated
by an applied electrical current, emit photons. Quantum dots and
quantum wells are nano-structures that exhibit various properties,
such as light generation, based on quantum mechanical effects.
Quantum wells are two-dimensional structures formed by a thin layer
of a first material surrounded by wider-bandgap material and that
allow electronic capture in one dimension (allowing planar
two-dimensional movement). In contrast, quantum dots act as
zero-dimensional entities, which enables three-dimensional capture
of excited electrons (not allowing movement). The quantum dots are
surrounded by the waveguides of the cladding layers 220 and are
made of materials that have narrower bandgaps than the material of
the cladding layers 220. As will be appreciated, the precise size,
shape, and material of the quantum dots or wells will affect the
color produced by the laser.
[0040] The fabricator forms the III-V component 160 in the pit 150
to optically couple (via butt-coupling) with the photonic elements
in the passive optical layer 130. The active gain medium 230 is
formed at a predetermined height relative to the substrate 110 to
allow for alignment with earlier-fabricated photonic elements in
the passive optical layer 130. Additionally, the upper cladding
layer 220 is formed to a predetermined height relative to the
substrate 110 (e.g., the height of the insulator 120 surrounding
the pit 150) to define the form factor for the SiPh platform
140.
[0041] At block 550, the fabricator etches a slot 410 between the
Si elements (e.g, the insulator 120 and the passive optical layer
130) and the III-V component 160. (Sixth view 400f). In various
embodiments, the fabricator uses a physical or a chemical etching
process to define the slot 410 by removing material from at least
one of the Si elements and the III-V component 160. For example,
the fabricator may etch the slot 410 by removing material only from
the Si elements, only from the III-V component 160, or both the Si
elements and the III-V component 160. In various embodiments using
a chemical etchant, the fabricator applies a resist mask to the
insulator 120 and the III-V component 160 to ensure that only
exposed materials are removed. Although the slot 410 is illustrated
as being formed from the top surface of the SiPh platform 140 to
the substrate 110, in some embodiments, the slot 410 may be more
shallow; exposing the interface between the passive optical layer
130 and the active gain medium 230, but leaving the substrate 110
unexposed.
[0042] At optional block 560, the fabricator fills the slot 410
with an optical coating 210. (Seventh view 400g). In various
embodiments, the fabricator forms one or more optical layers on a
face of the SiPh platform 140 exposed by the slot 410. For example,
the fabricator may form an optical coating 210 to affect a
reflectivity or refractivity of the OCI 170. In embodiments of
method 500 that omit optional block 560, the fabricator leaves the
slot 410 unfilled; providing an OCI 170 with an air-gap between the
active gain medium 230 and the photonic elements of the passive
optical layer 130 (i.e., an airgap OCI). In some embodiments, the
fabricator physically or chemically etches the exposed face of the
slot 410 to provide a surface with a desired smoothness and
distance from the photonic elements of the (e.g., a fine etch or
polish following a rough etch per block 550).
[0043] As will be appreciated, various processes may be applied to
etch the SiPh platform 140 into a desired shape or profile, add one
or more photonic elements, and/or process the SiPh platform 140
into a final assembly. Similarly, various wafer processes may be
performed on the SiPh platform 140 prior to or after bonding and/or
forming the other layers, such as, for example, the inclusion of
TSVs, alignment features, dicing a wafer into several dies for the
SiPh platform 140, etc.
[0044] FIG. 6 illustrates an optical assembly 600 with an
integrated III-V component 160 in a SiPh platform 140. The III-V
component 160 is selectively formed in the semiconductor layers of
the SiPh platform 140, which may constitute a final optical
assembly 600 in some embodiments. Any waveguides internal to the
passive optical layer 130 are aligned with the waveguides of the
III-V component 160. In various embodiments, different surface
treatments are applied to the OCI 170 to affect the reflectivity
and refractive index for light passing between the integrated III-V
component 160 and the passive optical layer 130.
[0045] The fabricator may incorporate various contact pads 610 to
the optical assembly 600 via metallization (e.g., via evaporation
or sputtering processes) so as to add TSVs, electrical leads, and
passive connection points so that other components can be
physically attached to and/or electrically connected to the optical
assembly 600. The contact pads 610 may include electrical leads
that pass through the dielectric and terminate in one or more pads
360 (e.g., TSVs). In some embodiments, the contact pads 610 are
positioned on opposite side of the III-V component 160 (and may
pass through the substrate 110) for a voltage to be applied across
the III-V component to generate or amplify an optical signal.
[0046] FIG. 7 illustrates a second optical assembly 700 using a
first optical assembly 600 with an integrated III-V component 160
in a SiPh platform 140 as a sub-assembly with a carrier 710. The
first optical assembly 600 is fabricated separately from the
carrier 710, and may be attached in a pocket 730 defined in the
carrier 710 via one or more a solder bonds or wire bonds. The
carrier 710 may include carrier contact pads 610b where the
assembly substrate 110a of the first optical assembly 600 is
attached, as well as carrier contact pads 610b on other portions of
the carrier 710 to allow other components to be physically attached
to and/or electrically connected to the second optical assembly
700.
[0047] The carrier 710 may be a pre-fabricated optical component
that includes a carrier substrate 110b (which may be formed from a
different material or a same material with a different axial cut
than the assembly substrate 110a of the first optical assembly
600), a carrier insulator 120b, and a carrier passive optical layer
130b. The waveguides in the carrier passive optical layer 130b of
the carrier 710 are aligned with the waveguides in the assembly
passive optical layer 130a of the first optical assembly 600 by a
pair of optical couplers; a first optical coupler 720a in the first
optical assembly 600 and a second optical coupler 720b in the
carrier 710. Although illustrated as nitride prong connectors, the
optical couplers 720a and 720b may also include silicon nano-taper
couplers, adiabatic evanescent couplers, and directional couplers
in various embodiments. The fabricator forms the relative heights
of the carrier insulator 120b and the carrier waveguide (or
connectors) in the carrier passive optical layer 130b to the
relative heights of the III-V component 160, assembly insulator
120a, and assembly passive optical layer 130a of the first optical
assembly 600. For example, with a first optical assembly 600 having
an assembly insulator 120a that extends a first distance from the
assembly substrate 110a and an assembly passive optical layer 130a
that extends a second distance from the assembly substrate 110a,
the carrier 710 may have a carrier insulator 120b that extends a
third distance from the carrier substrate 110b to a mounting
surface for the first optical assembly 600 that is at least as
great as the first distance (to accommodate the first optical
assembly 600 in the pocket 730). Similarly, the fabricator may form
the carrier passive optical layer 130b of the carrier 710 at a
fourth distance relative to the mounting surface of the carrier
insulator 120b that is the same as the second distance that the
assembly passive optical layer 130a extends from the assembly
substrate 110a of the first optical assembly 600 to align the
carrier passive optical layers 130b and the assembly optical layers
130a when the first optical assembly 600 is captured in the pocket
730. The assembly passive optical layer 130a of the first optical
assembly 600 thus creates an optical pathway for the III-V
component 160 to the carrier passive optical layer 130b of the
carrier 710.
[0048] In the current disclosure, reference is made to various
embodiments. However, the scope of the present disclosure is not
limited to specific described embodiments. Instead, any combination
of the described features and elements, whether related to
different embodiments or not, is contemplated to implement and
practice contemplated embodiments. Additionally, when elements of
the embodiments are described in the form of "at least one of A and
B," it will be understood that embodiments including element A
exclusively, including element B exclusively, and including element
A and B are each contemplated. Furthermore, although some
embodiments disclosed herein may achieve advantages over other
possible solutions or over the prior art, whether or not a
particular advantage is achieved by a given embodiment is not
limiting of the scope of the present disclosure. Thus, the aspects,
features, embodiments and advantages disclosed herein are merely
illustrative and are not considered elements or limitations of the
appended claims except where explicitly recited in a claim(s).
Likewise, reference to "the invention" shall not be construed as a
generalization of any inventive subject matter disclosed herein and
shall not be considered to be an element or limitation of the
appended claims except where explicitly recited in a claim(s).
[0049] In view of the foregoing, the scope of the present
disclosure is determined by the claims that follow.
* * * * *