U.S. patent application number 17/242870 was filed with the patent office on 2021-08-12 for memory device.
This patent application is currently assigned to TOSHIBA MEMORY CORPORATION. The applicant listed for this patent is TOSHIBA MEMORY CORPORATION. Invention is credited to Tatsuo IZUMI, Reiko KOMIYA, Takeshi NAGATOMO, Karin TAKAGI, Takaya YAMANAKA.
Application Number | 20210249440 17/242870 |
Document ID | / |
Family ID | 1000005550487 |
Filed Date | 2021-08-12 |
United States Patent
Application |
20210249440 |
Kind Code |
A1 |
KOMIYA; Reiko ; et
al. |
August 12, 2021 |
MEMORY DEVICE
Abstract
A memory device includes a conductive layer, a plurality of
first electrode layers, a first semiconductor layer extending
through the plurality of first electrode layers in a first
direction toward the plurality of first electrode layers from the
conductive layer, a first insulating film including a tunneling
insulator film, a charge-trapping film and a blocking insulator
film, a second electrode layer, and a semiconductor base. The
charge-trapping film is spaced along the first direction from the
semiconductor base, a distance in the first direction between the
charge-trapping film and the semiconductor base is larger than a
thickness of the blocking insulator film in a second direction
toward the plurality of first electrode layers from the first
semiconductor layer.
Inventors: |
KOMIYA; Reiko; (Nagoya,
JP) ; IZUMI; Tatsuo; (Yokkaichi, JP) ;
YAMANAKA; Takaya; (Yokkaichi, JP) ; NAGATOMO;
Takeshi; (Yokkaichi, JP) ; TAKAGI; Karin;
(Yokkaichi, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TOSHIBA MEMORY CORPORATION |
Minato-ku |
|
JP |
|
|
Assignee: |
TOSHIBA MEMORY CORPORATION
Minato-ku
JP
|
Family ID: |
1000005550487 |
Appl. No.: |
17/242870 |
Filed: |
April 28, 2021 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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16695749 |
Nov 26, 2019 |
11024646 |
|
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17242870 |
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16127634 |
Sep 11, 2018 |
10529735 |
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16695749 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/11582 20130101;
H01L 27/11524 20130101; H01L 27/1157 20130101; H01L 27/11556
20130101; G11C 7/18 20130101; G11C 8/14 20130101 |
International
Class: |
H01L 27/11582 20170101
H01L027/11582; G11C 7/18 20060101 G11C007/18; H01L 27/1157 20170101
H01L027/1157; G11C 8/14 20060101 G11C008/14 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 13, 2018 |
JP |
2018-045703 |
Claims
1. A manufacturing method of a nonvolatile semiconductor memory
device comprising: forming a conductive layer; forming first layers
and second layers alternately in a first direction above the
conductive layer, the first direction being perpendicular to a
surface of the conductive layer; forming a first hole in the first
layers and the second layers, the first hole extending in the first
direction; forming an insulating film in the first hole; forming an
sacrificial material in the first hole, the insulating film being
between the conductive layer and the sacrificial material; forming
third layers and fourth layers alternately in the first direction
above the first and second layers; forming a second hole in the
third layers and the fourth layers, the second hole extending in
the first direction to reach the sacrificial material; removing the
sacrificial material through the second hole; and forming a memory
layer in the first hole and the second hole.
2. The manufacturing method according to claim 1, further
comprising: forming a semiconductor layer on the memory layer in
the first hole and the second hole.
3. The manufacturing method according to claim 1, further
comprising: forming a semiconductor base on the conductive layer in
the first hole.
4. The manufacturing method according to claim 3, wherein the
insulating film is formed on the semiconductor base.
5. The manufacturing method according to claim 3, wherein the
insulating film is formed by oxidizing a portion of the
semiconductor base.
6. The manufacturing method according to claim 3, wherein the
semiconductor base includes the same material as a material of the
sacrificial material.
7. The manufacturing method according to claim 3, wherein the
semiconductor base and the sacrificial material each include
silicon.
8. The manufacturing method according to claim 1, further
comprising: forming a slit in the first layers, the second layers,
the third layers and the fourth layers, removing the first layers
and the third layers through the slit to form spaces; and forming
conductive materials in the spaces.
9. The manufacturing method according to claim 3, further
comprising: forming a slit in the first layers, the second layers,
the third layers and the fourth layers; removing the first layers
and the third layers through the slit to form spaces; and forming
conductive materials in the spaces.
10. The manufacturing method according to claim 9, further
comprising: forming a gate insulating film on a side surface of the
semiconductor base exposed after removing the first layers and the
third layers and before forming the conductive materials.
11. The manufacturing method according to claim 9, wherein the gate
insulating film is formed by oxidizing a portion of the
semiconductor base.
12. The manufacturing method according to claim 1, further
comprising: forming an inter-layer insulating layer above the first
layers and the second layers; and forming a connection hole in the
inter-layer insulating layer before forming the sacrificial
material, the connection hole having a larger diameter than a
diameter of the first hole.
13. The manufacturing method according to claim 1, wherein the
memory layer includes a blocking insulating layer, a charge trap
layer and a tunneling insulating layer.
14. A manufacturing method of a nonvolatile semiconductor memory
device comprising: forming a conductive layer; forming first layers
and second layers alternately in a first direction above the
conductive layer, the first direction being perpendicular to a
surface of the conductive layer; forming a first hole in the first
layers and the second layers, the first hole extending in the first
direction; forming a semiconductor base on the conductive layer in
the first hole forming an insulating film on the semiconductor base
in the first hole; forming an sacrificial material in the first
hole, the insulating film being between the conductive layer and
the sacrificial material; forming third layers and fourth layers
alternately in the first direction above the first and second
layers; forming a second hole in the third layers and the fourth
layers, the second hole extending in the first direction to reach
the sacrificial material; removing the sacrificial material through
the second hole; forming a memory layer in the first hole and the
second hole; and forming a semiconductor layer on the memory layer
in the first hole and the second hole.
15. The manufacturing method according to claim 14, wherein the
insulating film is formed by oxidizing a portion of the
semiconductor base.
16. The manufacturing method according to claim 14, wherein the
semiconductor base and the sacrificial material each include
silicon.
17. The manufacturing method according to claim 14, further
comprising: forming a slit in the first layers, the second layers,
the third layers and the fourth layers; removing the first layers
and the third layers through the slit to form spaces; and forming
conductive materials in the spaces.
18. The manufacturing method according to claim 14, further
comprising: forming a gate insulating film on a side surface of the
semiconductor base exposed after removing the first layers and the
third layers and before forming the conductive materials by
oxidizing a portion of the semiconductor base.
19. The manufacturing method according to claim 14, further
comprising: forming an inter-layer insulating layer above the first
layers and the second layers; and forming a connection hole in the
inter-layer insulating layer before forming the sacrificial
material, the connection hole having a larger diameter than a
diameter of the first hole.
20. The manufacturing method according to claim 14, wherein the
memory layer includes a blocking insulating layer, a charge trap
layer and a tunneling insulating layer.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 16/695,749, filed Nov. 26, 2019, which is a continuation of
U.S. application Ser. No. 16/127,634, filed Sep. 11, 2018 (now U.S.
Pat. No. 10,529,735), which is based upon and claims the benefit of
priority from Japanese Patent Application No. 2018-045703, filed on
Mar. 13, 2018; the entire contents of each of which are
incorporated herein by reference.
FIELD
[0002] Embodiments relate to a memory device.
BACKGROUND
[0003] A memory device that includes three-dimensionally arranged
memory cells is being developed. For example, a NAND nonvolatile
memory device includes multiple electrode layers and a
semiconductor layer having a columnar configuration piercing the
multiple electrode layers; and memory cells are provided between
the semiconductor layer and the electrode layers. In a memory
device having such a structure, the memory capacity can be
increased by increasing the number of electrode layers. However,
when the electrode layers are increased, the cell current that
flows through the semiconductor layer piercing the electrode layers
may decrease.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 is a perspective view schematically showing a memory
device 1 according to a first embodiment;
[0005] FIGS. 2A and 2B are schematic cross-sectional views showing
the memory device according to the first embodiment;
[0006] FIG. 3 is a partial cross-sectional view schematically
showing the memory device according to the first embodiment;
[0007] FIGS. 4A to 14B are schematic cross-sectional views showing
manufacturing processes of the memory device according to the first
embodiment;
[0008] FIG. 15 is a schematic cross-sectional view showing a memory
device according to a variation of the first embodiment;
[0009] FIG. 16 is a schematic cross-sectional view showing a memory
device according to a variation of the first embodiment;
[0010] FIG. 17 is a schematic cross-sectional view showing a memory
device according to a variation of the first embodiment;
[0011] FIG. 18A to FIG. 26B are schematic cross-sectional views
showing manufacturing processes of a memory device according to a
second embodiment;
[0012] FIG. 27 is a schematic cross-sectional view showing a memory
device 6 according to a third embodiment; and
[0013] FIG. 28A to FIG. 32B are schematic cross-sectional views
showing manufacturing processes of the memory device according to
the third embodiment.
DETAILED DESCRIPTION
[0014] According to one embodiment, a memory device includes a
conductive layer, a plurality of first electrode layers, a first
semiconductor layer, a first insulating film, a second electrode
layer and a semiconductor base. The plurality of first electrode
layers are stacked above the conductive layer. The first
semiconductor layer pierces the plurality of first electrode layers
in a first direction, wherein the first direction is from the
conductive layer toward the plurality of first electrode layers.
The first insulating film is provided to surround the first
semiconductor layer between the first semiconductor layer and the
plurality of first electrode layers. The first insulating film
includes a first film, a second film, and a third film provided in
order in a second direction, wherein the second direction is from
the first semiconductor layer toward one of the plurality of first
electrode layers. The second electrode layer is provided between
the conductive layer and the first electrode layer of the plurality
of first electrode layers most proximal to the conductive layer.
The semiconductor base is connected to the first semiconductor
layer, and is provided to pierce the second electrode layer in the
first direction between the conductive layer and the first
semiconductor layer. A spacing in the first direction between the
second film and a surface of the semiconductor base contacting the
first semiconductor layer is wider than a film thickness of the
third film in the second direction. A minimum width in the second
direction of an outer perimeter of a portion of the first
semiconductor layer surrounded with the first insulating film is
substantially the same as a first width in the second direction of
an outer perimeter of a portion of the first semiconductor layer
piercing the most proximal first electrode layer. A second width in
the second direction of an outer perimeter of the first
semiconductor layer positioned at a level between the semiconductor
base and the first insulating film is substantially the same as or
wider than the first width, and is narrower than a third width in
the second direction, wherein the third width is of an outer
perimeter of the first insulating film covering the portion of the
first semiconductor layer piercing the most proximal first
electrode layer.
[0015] Embodiments will now be described with reference to the
drawings. The same portions inside the drawings are marked with the
same numerals; a detailed description is omitted as appropriate;
and the different portions are described. The drawings are
schematic or conceptual; and the relationships between the
thicknesses and widths of portions, the proportions of sizes
between portions, etc., are not necessarily the same as the actual
values thereof. The dimensions and/or the proportions may be
illustrated differently between the drawings, even in the case
where the same portion is illustrated.
[0016] There are cases where the dispositions of the components are
described using the directions of XYZ axes shown in the drawings.
The X-axis, the Y-axis, and the Z-axis are orthogonal to each
other. Hereinbelow, the directions of the X-axis, the Y-axis, and
the Z-axis are described as an X-direction, a Y-direction, and a
Z-direction. Also, there are cases where the Z-direction is
described as upward and the direction opposite to the Z-direction
is described as downward.
First Embodiment
[0017] FIG. 1 is a perspective view schematically showing a memory
device 1 according to a first embodiment. The memory device 1 is,
for example, a NAND flash memory device and includes
three-dimensionally arranged memory cells. Insulating films that
electrically insulate between adjacent components are not
illustrated in FIG. 1.
[0018] As shown in FIG. 1, the memory device 1 includes a
conductive layer (hereinbelow, a source layer SL), a select gate
SGS, word lines WL1, word lines WL2, and a select gate SGD. The
select gate SGS, the word lines WL1 and WL2, and the select gate
SGD are stacked on the source layer SL. The source layer SL, the
select gate SGS, the word lines WL1 and WL2, and the select gate
SGD are electrically insulated from each other by not-illustrated
inter-layer insulating films. The number of stacks of the word
lines WL1 and WL2 is not limited to the example shown in FIG.
1.
[0019] The memory device 1 includes a memory cell region MCR and a
draw-out region HUR. Multiple columnar bodies PB are provided in
the memory cell region MCR. The columnar bodies PB each include
columnar portions PB1 and PB2 and a connection portion JP. A
semiconductor base SB is further provided between the source layer
SL and the columnar body PB.
[0020] The columnar portion PB1 extends in a Z-direction and
pierces the word lines WL1. The columnar portion PB2 extends in the
Z-direction and pierces the word lines WL2 and the select gate SGD.
The connection portion JP connects the columnar portion PB1 and the
columnar portion PB2. The columnar portion PB1 is connected to the
semiconductor base SB.
[0021] The semiconductor base SB extends in the Z-direction and
pierces the select gate SGS. The columnar body PB is connected to
the source layer SL via the semiconductor base SB. The columnar
body PB also is connected to a bit line BL via a connection plug
VB.
[0022] The draw-out region HUR includes end portions of the select
gate SGS, the word lines WL1 and WL2, and the select gate SGD. As
shown in FIG. 1, the end portions of the word lines WL2 and the
select gate SGD are provided in a staircase configuration; and the
end portions are connected respectively to contact plugs CC. The
contact plugs CC electrically connect between the word lines WL2
and gate interconnects GL and between the select gate SGD and the
gate interconnect GL via connection plugs VC. The end portions of
the select gate SGS and the word lines WL1 also are provided in a
staircase configuration at a not-illustrated portion and are
electrically connected to the gate interconnects GL via the contact
plugs CC and the connection plugs VC.
[0023] The draw-out region HUR further includes a columnar support
body SP. The columnar support body SP is provided at the vicinity
of the contact plugs CC, extends in the Z-direction, and pierces at
least one of the word line WL1 or WL2 or the select gate SGD. The
columnar support body SP includes a lower portion piercing the word
lines WL1, an upper portion piercing the word lines WL2 and the
select gate SGD, and the connection portion JP linking between the
lower portion and the upper portion.
[0024] FIGS. 2A and 2B are schematic cross-sectional views showing
the memory device 1 according to the first embodiment. FIG. 2A is a
schematic cross-sectional view of the columnar body PB; and FIG. 2B
is a schematic cross-sectional view of the columnar support body
SP.
[0025] As shown in FIG. 2A, the memory device 1 includes
inter-layer insulating films 13, 15, 23, 25, and 30. The
inter-layer insulating film 13 is provided between the source layer
SL and the select gate SGS. The inter-layer insulating films 15 are
provided between the word lines WL1 adjacent to each other in the
Z-direction and between the select gate SGS and the word line WL1.
The inter-layer insulating film 23 is provided between the word
line WL1 and the word line WL2; and the connection portion JP is
positioned inside the inter-layer insulating film 23.
[0026] The inter-layer insulating films 25 are provided between the
word lines WL2 adjacent to each other in the Z-direction. The
inter-layer insulating film 25 is further provided between the word
line WL2 and the inter-layer insulating film 30. The inter-layer
insulating film 30 covers the upper end of the columnar body
PB.
[0027] The columnar body PB includes a memory film MF, a
semiconductor layer SF, and an insulating core CA. The insulating
core CA extends in the Z-direction in the interior of the columnar
body PB. The semiconductor layer SF surrounds the insulating core
CA and extends in the Z-direction. The memory film MF is positioned
between the semiconductor layer SF and the word lines WL and
extends in the Z-direction along the semiconductor layer SF. The
memory film MF is positioned between the semiconductor layer SF and
the select gate SGD. Hereinbelow, the word line WL1 and the word
line WL2 are generally called the word line WL in the
description.
[0028] The semiconductor layer SF is connected to the semiconductor
base SB at the lower end of the semiconductor layer SF. The
semiconductor base SB is connected to the source layer SL at the
lower end of the semiconductor base SB and electrically connects
the semiconductor layer SF and the source layer SL. An insulating
film 31 is provided between the semiconductor base SB and the
select gate SGS. An insulating film 33 is provided between the
semiconductor base SB and the memory film MF.
[0029] The semiconductor layer SF is connected to the connection
plug VB at the upper end of the semiconductor layer SF. The
connection plug VB is provided inside the inter-layer insulating
film 30 and electrically connects the semiconductor layer SF to the
bit line BL provided on the inter-layer insulating film 30.
[0030] The memory device 1 includes a select transistor STS, memory
cells MC, and a select transistor STD. The select transistor STD is
provided at a portion where the semiconductor layer SF crosses the
select gate SGD. The memory cells MC are provided at portions where
the semiconductor layer SF crosses the word lines WL. The select
transistor STD includes a portion of the memory film MF as a gate
insulating film. The memory cells MC include portions of the memory
film MF as charge retaining portions.
[0031] The select transistor STS is provided at a portion where the
semiconductor base SB pierces the select gate SGS. The insulating
film 31 that is provided between the semiconductor base SB and the
select gate SGS functions as a gate insulating film of the select
transistor STS.
[0032] As shown in FIG. 2B, the columnar support body SP includes a
memory film MFS, a semiconductor layer SFS, and an insulating core
CAS. The columnar support body SP is formed using the same
processes as the columnar body PB and has a similar structure. The
material of the memory film MFS is the same as the material of the
memory film MF of the columnar body PB. The material of the
semiconductor layer SFS is the same as the material of the
semiconductor layer SF of the columnar body PB. The material of the
insulating core CAS is the same as the material of the insulating
core CA of the columnar body PB.
[0033] The columnar support body SP is formed to pierce the end
portions of the word lines WL and the select gate SGD formed in the
staircase configuration in the draw-out region HUR. Therefore, the
number of the word lines WL and the select gates SGD crossing the
columnar support body SP is different according to the position
where the columnar support body SP is provided. In other words, the
columnar support body SP is provided to pierce at least one word
line WL counting from the word line WL of the lowermost layer.
[0034] The upper portion of the columnar support body SP is
provided to pierce an insulating film 29 burying the end portions
of the word lines WL formed in the staircase configuration. The
upper end of the columnar support body SP is covered with the
inter-layer insulating film 30 provided on the insulating film 29
and is electrically insulated from the interconnects of the upper
layers (not illustrated).
[0035] FIG. 3 is a partial cross-sectional view schematically
showing the memory device 1 according to the first embodiment. FIG.
3 is a schematic cross-sectional view showing the structure of the
lower portion of the columnar body PB.
[0036] As shown in FIG. 3, the memory film MF includes a tunneling
insulating film TN, a charge trap film CT, and a blocking
insulating film BLK. The charge trap film CT is provided between
the tunneling insulating film TN and the blocking insulating film
BLK. The tunneling insulating film TN contacts the semiconductor
layer SF; and the blocking insulating film BLK contacts the word
lines WL1 and the inter-layer insulating films 15.
[0037] The tunneling insulating film TN is, for example, a silicon
oxide film; and the charge trap film CT is, for example, a silicon
nitride film. The blocking insulating film BLK is, for example, a
silicon oxide film. The blocking insulating film BLK also may
include an insulative metal oxide, e.g., aluminum oxide, etc.
[0038] The embodiment is not limited to the example; and, for
example, memory cells MC having floating gate structures may be
used. For example, instead of the charge trap film CT, the memory
film MF may include conductive films at the portions positioned
between the semiconductor layer SF and the word lines WL. The
conductive films are positioned between the tunneling insulating
film TN and the blocking insulating film BLK and are arranged to be
separated from each other in the Z-direction.
[0039] The semiconductor layer SF has a width W.sub.S1 in an
X-direction of the outer perimeter at a position crossing a word
line WLB1 of the lowermost layer, a width W.sub.S2 in the
X-direction of the outer perimeter at the lower end position of the
memory film MF, and a width W.sub.S3 in the X-direction of the
outer perimeter surrounded with the insulating film 33. In the case
where the horizontal cross section of the semiconductor layer SF is
substantially a circle, W.sub.S1, W.sub.S2, and W.sub.S3 are the
outer diameters of the semiconductor layer SF at the respective
positions.
[0040] Here, W.sub.S2 is the minimum width in the X-direction of
the semiconductor layer SF and is substantially the same as
W.sub.S1 in the embodiment. W.sub.S3 is substantially the same as
W.sub.S2 or wider than W.sub.S2.
[0041] Because the insulating film 33 is provided on the
semiconductor base SB, a spacing T.sub.1 between the lower end of
the charge trap film CT and the surface where the semiconductor
layer SF and the semiconductor base SB contact, i.e., the upper
surface of the semiconductor base SB, is wider than a film
thickness T.sub.BLK of the blocking insulating film BLK. The memory
film MF has a width W.sub.PB in the X-direction of the outer
perimeter at a position contacting the word line WLB1; and W.sub.S3
is narrower than W.sub.PB.
[0042] A method for manufacturing the memory device 1 according to
the first embodiment will now be described with reference to FIG.
4A to FIG. 14B. FIG. 4A to FIG. 14B are schematic cross-sectional
views showing manufacturing processes of the memory device 1.
Although FIG. 4A to FIG. 14B show the manufacturing processes of
the semiconductor base SB and the columnar body PB, it should be
noted that the columnar support body SP also is formed
simultaneously in the embodiment.
[0043] As shown in FIG. 4A, a memory hole MH1 is formed after
stacking the inter-layer insulating films 13, 15, and 21 and
sacrificial films 17 on the source layer SL. Also, the end portions
of the sacrificial films 17 are formed in a staircase configuration
at a portion used to form the draw-out region HUR (not
illustrated). The sacrificial films 17 are provided between the
inter-layer insulating film 13 and an inter-layer insulating film
15B, between the inter-layer insulating films 15 adjacent to each
other in the Z-direction, and between an inter-layer insulating
film 15T and the inter-layer insulating film 21. Here, the
inter-layer insulating film 15B is the lowermost inter-layer
insulating film 15 of the multiple inter-layer insulating films 15.
The inter-layer insulating film 15T is the uppermost inter-layer
insulating film 15 of the multiple inter-layer insulating films
15.
[0044] The memory hole MH1 has a depth reaching the source layer SL
from the upper surface of the inter-layer insulating film 21. For
example, the memory hole MH1 is formed by selectively removing the
inter-layer insulating films 13, 15, and 21 and the sacrificial
films 17 using anisotropic RIE (Reactive Ion Etching).
[0045] The source layer SL is, for example, a portion of a silicon
substrate, or a polysilicon layer provided on a silicon substrate
(not illustrated) with an inter-layer insulating film (not
illustrated) interposed. The inter-layer insulating films 13, 15,
and 21 are, for example, silicon oxide films. The sacrificial films
17 are, for example, silicon nitride films.
[0046] As shown in FIG. 4B, the semiconductor base SB is formed at
the bottom portion of the memory hole MH1. The semiconductor base
SB is, for example, silicon that is epitaxially grown on the source
layer SL exposed at the bottom surface of the memory hole MH1.
[0047] The semiconductor base SB is formed so that an upper surface
SBT of the semiconductor base SB is positioned at a level between a
sacrificial film 17A and a sacrificial film 17B. Here, the
sacrificial film 17B is the sacrificial film 17 of the lowermost
layer of the multiple sacrificial films 17. The sacrificial film
17A is the sacrificial film 17 adjacent to the sacrificial film 17B
in the Z-direction.
[0048] As shown in FIG. 4C, the insulating film 33 is formed on the
semiconductor base SB. The insulating film 33 is, for example, a
silicon oxide film and is formed by oxidizing a portion of the
semiconductor base SB. The insulating film 33 is formed so that the
upper surface SBT of the semiconductor base SB is positioned at a
level between the sacrificial film 17A and the sacrificial film
17B. When the semiconductor base SB is oxidized, there are also
cases where portions of the sacrificial films 17 exposed at the
inner wall of the memory hole MH1 also are oxidized; and, for
example, thin oxide films (not illustrated) are formed.
[0049] As shown in FIG. 5A, a sacrificial layer 35 that fills the
interior of the memory hole MH1 is formed. The sacrificial layer 35
is, for example, an amorphous silicon layer deposited using CVD
(Chemical Vapor Deposition).
[0050] As shown in FIG. 5B, etch-back of the sacrificial layer 35
is performed; and a space ES is formed on the sacrificial layer 35
filling the memory hole MH1. The space ES is formed to be
positioned at a level that is higher than a sacrificial film
17T.
[0051] As shown in FIG. 5C, the connection portion JP is formed by
enlarging the space ES in the horizontal direction. For example,
the connection portion JP is formed by etching the inter-layer
insulating film 21 using an isotropic etching method.
[0052] As shown in FIG. 6A, a sacrificial layer 37 that fills the
connection portion JP is formed. The sacrificial layer 37 is, for
example, an amorphous silicon layer deposited using CVD.
[0053] As shown in FIG. 6B, the surface of the inter-layer
insulating film 21 is exposed by removing a portion of the
sacrificial layer 37. For example, the surfaces of the inter-layer
insulating film 21 and the sacrificial layer 37 are planarized by
removing a portion of the sacrificial layer 37 by performing
etch-back of the sacrificial layer 37 or by using CMP (Chemical
Mechanical Polishing).
[0054] As shown in FIG. 7A, the inter-layer insulating films 25 and
sacrificial films 27 are stacked alternately on the inter-layer
insulating film 21 and the sacrificial layer 37. The inter-layer
insulating films 25 are, for example, silicon oxide films; and the
sacrificial films 27 are, for example, silicon nitride films. Here,
the inter-layer insulating film 21 and the inter-layer insulating
film 25 are formed as one body if both are silicon oxide films.
[0055] In the following drawings, the inter-layer insulating films
21 and 25 are described as being formed as one body as the
inter-layer insulating film 23.
[0056] As shown in FIG. 7B, a memory hole MH2 is formed to
communicate with the sacrificial layer 37 from the upper surface of
an inter-layer insulating film 25T. For example, the memory hole
MH2 is formed by selectively removing the inter-layer insulating
films 25 and the sacrificial films 27 by using anisotropic RIE. The
inter-layer insulating film 25T is the uppermost inter-layer
insulating film 25 of the multiple inter-layer insulating films
25.
[0057] As shown in FIG. 8A, the memory hole MH1 and the memory hole
MH2 are formed as one body as a memory hole MH. The memory hole MH
is formed by selectively removing the sacrificial layers 35 and 37
via the memory hole MH2. For example, the sacrificial layers 35 and
37 are removed using wet etching.
[0058] At this time, the insulating film 33 protects the
semiconductor base SB from the etchant of the sacrificial layers 35
and 37. Thereby, the etching of the semiconductor base SB and the
lowering of the position of the upper surface SBT of the
semiconductor base SB (referring to FIG. 4C) toward the select gate
SGS can be avoided (referring to FIG. 2B). However, it should be
noted that the formation of the insulating film 33 can be omitted
if the tolerance of the upper surface position of the semiconductor
base SB with respect to the select gate SGS is large.
[0059] In the embodiment, the memory hole MH that reaches the
insulating film 33 from the inter-layer insulating film 25T can be
formed easily by connecting the memory hole MH1 and the memory hole
MH2. For example, in the case where the aspect ratio (the depth
divided by the diameter of the bottom surface) of the memory hole
MH is large, it is difficult to form a memory hole MH having a
uniform diameter in the depth direction. In the embodiment, a
memory hole MH having the desired high aspect ratio can be realized
by connecting the memory hole MH1 and the memory hole MH2 which
have small aspect ratios. Further, the positional alignment of the
memory hole MH2 with respect to the memory hole MH1 is easy by
providing the connection portion JP which has an enlarged diameter
between the memory hole MH1 and the memory hole MH2.
[0060] As shown in FIG. 8B, the memory film MF and a semiconductor
layer SF1 are formed on the inner surface of the memory hole MH.
The memory film MF includes the blocking insulating film BLK, the
charge trap film CT, and the tunneling insulating film TN stacked
in order on the inner surface of the memory hole MH (referring to
FIG. 3). The semiconductor layer SF1 is, for example, an amorphous
silicon layer. The semiconductor layer SF1 is stacked on the memory
film MF; and the semiconductor layer SF1 is formed so that a space
remains in the interior of the memory hole MH.
[0061] As shown in FIG. 9A, portions of the memory film MF, the
semiconductor layer SF, and the insulating film 33 at the bottom
surface of the memory hole MH are selectively removed. For example,
the memory film MF, the semiconductor layer SF, and the insulating
film 33 are selectively removed using anisotropic RIE. Thereby, the
semiconductor base SB is exposed at the bottom surface of the
memory hole MH. The bottom surface of the memory hole MH is
positioned in the interior of the semiconductor base SB; and a
recess (a recess portion) is formed in the semiconductor base
SB.
[0062] As shown in FIG. 9B, the bottom portion of the memory hole
MH is enlarged in the horizontal direction by selectively removing
the lower end of the memory film MF and a portion of the insulating
film 33 exposed at the wall surface of the memory hole MH. For
example, the portions of the memory film MF and the insulating film
33 are removed using isotropic dry etching.
[0063] As shown in FIG. 10A, a width W.sub.MB in the X-direction of
the bottom portion of the memory hole MH is enlarged to be
substantially the same as or wider than the width W.sub.S1 in the
X-direction of the outer perimeter of the semiconductor layer SF1
at the level of the sacrificial film 17A.
[0064] As shown in FIG. 10B, a semiconductor layer SF2 is formed on
the inner surface of the memory hole MH. The semiconductor layer
SF2 is, for example, an amorphous silicon layer. The semiconductor
layer SF2 is formed on the semiconductor layer SF1 and contacts the
semiconductor base SB at the bottom surface of the memory hole MH.
The contact surface area between the semiconductor layer SF2 and
the semiconductor base SB is greater than the surface area of the
recess portion formed in the semiconductor base SB.
[0065] For example, the semiconductor layer SF2 contacts the
surface of the semiconductor base SB that is not damaged by the
anisotropic RIE at the enlarged bottom portion of the memory hole
MH. Thereby, the contact resistance between the semiconductor layer
SF (referring to FIG. 10B) and the semiconductor base SB can be
reduced.
[0066] As shown in FIG. 11A, the semiconductor layer SF is formed
in which the semiconductor layer SF1 and the semiconductor layer
SF2 are formed as one body. For example, the semiconductor layer SF
is formed by performing heat treatment to change the semiconductor
layers SF1 and SF2 which are amorphous silicon layers into a
polysilicon layer.
[0067] As shown in FIG. 11B, the insulating core CA that is filled
into the interior of the memory hole MH is formed. The insulating
core CA is, for example, silicon oxide deposited using CVD.
[0068] As shown in FIG. 12A, a slit ST that divides the inter-layer
insulating films 13, 15, and 23 and the sacrificial films 17 is
formed. For example, the slit ST is formed by selectively removing
the inter-layer insulating films 13, 15, and 23 and the sacrificial
films 17 by using anisotropic RIE. The slit ST extends in the
X-direction and has a depth reaching the source layer SL from the
upper surface of the inter-layer insulating film 25T (referring to
FIG. 9B). In other words, the slit ST also divides the
not-illustrated inter-layer insulating films 25 and the
not-illustrated sacrificial films 27.
[0069] As shown in FIG. 12B, the sacrificial films 17 are
selectively removed; and spaces 17S are formed between the
inter-layer insulating film 13 and the inter-layer insulating film
15, between the inter-layer insulating films 15 adjacent to each
other in the Z-direction, and between the inter-layer insulating
film 15 and the inter-layer insulating film 23. For example, the
sacrificial films 17 are removed by supplying an etchant via the
slit ST. At this time, the sacrificial films 17 are selectively
removed with respect to the inter-layer insulating films 13, 15,
and 23. The sacrificial films 27 also are selectively removed at a
not-illustrated portion.
[0070] The columnar body PB supports the inter-layer insulating
films 15, 23, and 25 in the memory cell region MCR and maintains
the space between the inter-layer insulating films. Also, the
columnar support body SP (referring to FIG. 3) supports the
inter-layer insulating films 15, 23, and 25 in the draw-out region
HUR and maintains the space between the inter-layer insulating
films.
[0071] As shown in FIG. 13A, the insulating film 31 is formed on
the side surface of the semiconductor base SB. The insulating film
31 is, for example, a silicon oxide film and is formed by oxidizing
a portion of the semiconductor base SB via a space 17BS. At this
time, a portion of the source layer SL exposed at the bottom
surface of the slit ST also is oxidized; and an insulating film 39
is formed. Here, the space 17BS is formed by removing the
sacrificial film 17B at the position most proximal to the source
layer SL; and a portion of the side surface of the semiconductor
base SB is exposed in the interior of the space 17BS.
[0072] As shown in FIG. 13B, a metal layer 43 is formed in the
interior of the spaces 17S (referring to FIG. 12B). The metal layer
43 includes, for example, tungsten (W) deposited using CVD. The
source gas of the metal layer 43 is supplied to the interiors of
the spaces 17S via the slit ST.
[0073] As shown in FIG. 14A, the word lines WL1 and the select gate
SGS are formed by removing the portion of the metal layer 43
deposited on the inner surface of the slit ST. The word lines WL2
and the select gate SGD also are formed at a not-illustrated
portion.
[0074] As shown in FIG. 14B, a source contact LI is formed in the
interior of the slit ST. The source contact LI is connected to the
source layer SL at the bottom surface of the slit ST. The source
contact LI is, for example, a metal such as tungsten (W), etc., and
electrically connects the source layer SL to an interconnect of the
upper layer (not illustrated).
[0075] The source contact LI is electrically insulated from the
word lines WL and the select gates SGS and SGD by an insulating
film 45. The insulating film 45 is, for example, a silicon oxide
film and is provided on the inner wall of the slit ST.
[0076] Continuing, the contact plugs CC and the interconnects of
the upper layers that are connected respectively to the word lines
WL and the select gates SGS and SGD (referring to FIG. 1) are
formed; and the memory device 1 is completed.
[0077] FIG. 15 is a schematic cross-sectional view showing a memory
device 2 according to a modification of the first embodiment. FIG.
15 is a schematic cross-sectional view of the lower portion of the
columnar body PB.
[0078] In the memory device 2 as shown in FIG. 15, a width W.sub.S4
in the X-direction of the outer perimeter of the lower end of the
semiconductor layer SF is provided to be narrower than the width
W.sub.S1 in the X-direction of the outer perimeter of the portion
crossing the word line WLB1. In other words, the memory film MF
includes a lower end MFB extending toward the insulating core CA;
and the entire width of the portion of the semiconductor layer SF
and the insulating core CA piercing the insulating film 33 also is
formed to be narrow. For example, such a structure is formed by
omitting the process of enlarging the bottom portion of the memory
hole MH in the horizontal direction shown in FIG. 9B.
[0079] In the memory device 2, for example, there are cases where
the current (hereinbelow, the cell current) that flows through the
semiconductor layer SF when reading data from the memory cells MC
is blocked by the insulating film 33 and the lower end MFB of the
memory film MF. Conversely, in the memory device 1 shown in FIG. 3,
the lower end MFB of the memory film MF is removed; and the portion
of the semiconductor layer SF piercing the insulating film 33 is
enlarged in the horizontal direction. Thereby, the channel
resistance between the semiconductor layer SF and the semiconductor
base SB is reduced; and the cell current can be increased.
[0080] FIG. 16 is a schematic cross-sectional view showing a memory
device 3 according to a modification of the first embodiment. FIG.
16 is a schematic cross-sectional view of the lower portion of the
columnar body PB.
[0081] In the memory device 3 as shown in FIG. 16, the lower
portion of the semiconductor layer SF positioned between the
semiconductor base SB and the memory film MF is provided to contact
the inter-layer insulating film 15. The width W.sub.S2 in the
X-direction of the outer perimeter of the semiconductor layer SF at
the lower end of the memory film MF (referring to FIG. 3) is
substantially the same as the width W.sub.S1 in the X-direction of
the outer perimeter of the portion of the semiconductor layer SF
crossing the word line WLB1. For example, such a structure is
formed by completely removing the insulating film 33 and the lower
end MFB of the memory film MF (referring to FIG. 15) in the process
of enlarging the bottom portion of the memory hole MH shown in FIG.
9B.
[0082] The width W.sub.S3 in the X-direction of the outer perimeter
of the semiconductor layer SF contacting the inter-layer insulating
film 15 is substantially the same as or wider than a width W.sub.MH
in the X-direction of the outer perimeter of the memory film MF at
the level of the word line WLB1. A spacing T.sub.2 between the
upper surface of the semiconductor base SB and the lower end of the
charge trap film CT is wider than a film thickness T.sub.MF of the
memory film MF. For example, in the case where the horizontal cross
section of the memory hole MH is substantially a circle, W.sub.MH
is the diameter of the memory hole MH.
[0083] In the memory device 3, the width W.sub.S3 of the outer
perimeter of the semiconductor layer SF at the lower end of the
memory film MF can be set to be substantially the same as the width
W.sub.S1 of the outer perimeter of the semiconductor layer SF at
the level of the word line WLB1; and the channel resistance between
the semiconductor layer SF and the semiconductor base SB can be
reduced and the cell current can be large by enlarging, in the
horizontal direction, the portion of the semiconductor layer SF
positioned between the memory film MF and the semiconductor base
SB.
[0084] FIG. 17 is a schematic cross-sectional view showing a memory
device 4 according to a modification of the first embodiment. FIG.
17 is a schematic cross-sectional view showing the lower portions
of the columnar body PB and the source contact LI.
[0085] In the memory device 4 as shown in FIG. 17, the
semiconductor base SB is not provided; and the semiconductor layer
SF is directly connected to the source layer SL. The width W.sub.S3
in the X-direction of the outer perimeter of the semiconductor
layer SF at the lower end of the memory film MF is set to be
substantially the same as the width W.sub.S1 in the X-direction of
the outer perimeter of the semiconductor layer SF at the level
crossing the select gate SGS; and the portion of the semiconductor
layer SF contacting the source layer SL is enlarged in the
horizontal direction. The lower end of the memory film MF is
positioned at a level between the source layer SL and the select
gate SGS.
[0086] For example, the memory device 4 can be formed by omitting
the formation of the semiconductor base SB and the formation of the
insulating film 33 shown in FIGS. 4B and 4C. Also, the lower end
MFB of the memory film MF (referring to FIG. 15) is removed
completely in the process of enlarging the bottom portion of the
memory hole MH shown in FIG. 9B. Thereby, for example, a maximum
width W.sub.S5 of the outer perimeter of the portion of the
semiconductor layer SF contacting the source layer SL is formed to
be substantially the same as or wider than the width W.sub.MH in
the X-direction of the outer perimeter of the memory film MF at the
level of the select gate SGS.
[0087] In the memory device 4 as well, the channel resistance at
the lower end of the semiconductor layer SF can be reduced. Also,
the contact resistance between the semiconductor layer SF and the
source layer SL can be reduced because a portion of the
semiconductor layer SF contacts a portion of the source layer SL
not damaged by the RIE. Thereby, a cell current I.sub.CEL that
flows in the source contact LI from the semiconductor layer SF via
the source layer SL can be increased.
[0088] In the embodiment as recited above, the bottom portion of
the memory hole MH is enlarged by partially removing the insulating
film 33 and the lower end MFB of the memory film MF. Thereby, the
resistance of the semiconductor layer SF provided in the interior
of the memory hole MH can be reduced. For example, even in the case
where the number of stacks of the word lines WL increases and the
entire channel length of the memory cells MC increases, it is
possible to prevent the decrease of the cell current by reducing
the channel resistance at the lower portion of the semiconductor
layer SF.
Second Embodiment
[0089] FIG. 18A to FIG. 26B are schematic cross-sectional views
showing manufacturing processes of a memory device 5 according to a
second embodiment (referring to FIGS. 26A and 26B). The drawings
are schematic cross-sectional views showing the manufacturing
processes of the columnar body PB and the columnar support body
SP.
[0090] As shown in FIG. 18A, the inter-layer insulating films 13,
15, and 21 and the sacrificial films 17 are stacked on the source
layer SL. The sacrificial films 17 are provided between the
inter-layer insulating film 13 and the inter-layer insulating film
15B, between the inter-layer insulating films 15 adjacent to each
other in the Z-direction, and between the inter-layer insulating
film 15T and the inter-layer insulating film 21.
[0091] As shown in FIG. 18B, a support hole HR is formed at a
portion used to form the draw-out region HUR. The support hole HR
has a depth reaching the source layer SL from the upper surface of
the inter-layer insulating film 21. Continuing, an insulating film
53 is formed by oxidizing the source layer SL exposed at the bottom
surface of the support hole HR. The insulating film 53 is, for
example, a silicon oxide film.
[0092] In this process, the end surfaces of the sacrificial films
17 exposed at the inner wall of the support hole HR also are
oxidized; and insulating films 55 are formed. The sacrificial films
17 are, for example, silicon nitride films; and the insulating
films 55 are, for example, silicon oxide films. For example, the
insulating film 53 may be deposited on the inner surface of the
support hole HR using CVD.
[0093] As shown in FIG. 19A, the memory hole MH1 is formed at a
portion used to form the memory cell region MCR. The memory hole
MH1 has a depth reaching the source layer SL from the upper surface
of the inter-layer insulating film 21.
[0094] For example, the memory hole MH1 is formed by selectively
removing the inter-layer insulating films 13, 15, and 21 and the
sacrificial films 17 by using a resist mask 57. As shown in FIG.
19B, the support hole HR is protected by the resist mask 57 during
the selective removal.
[0095] As shown in FIG. 20A, the semiconductor base SB is formed at
the bottom portion of the memory hole MH1. The semiconductor base
SB is epitaxially grown on the source layer SL exposed at the
bottom portion of the memory hole MH1. As shown in FIG. 20B, the
semiconductor base SB is not formed because the source layer SL is
not exposed in the interior of the support hole HR.
[0096] Further, the insulating film 33 is formed by oxidizing the
semiconductor base SB in the memory hole MH1. In the support hole
HR, the oxidization of the source layer SL and the sacrificial
films 17 progresses; and the film thicknesses of the insulating
films 53 and 55 become thick. Although the sacrificial films 17
that are exposed at the inner wall of the memory hole MH1 also are
oxidized in the oxidization, insulating films that are formed on
the end surfaces of the sacrificial films 17 inside the memory hole
MH1 are not illustrated in FIG. 20A and subsequent drawings.
[0097] As shown in FIG. 21A, the inter-layer insulating films 23
and 25 and the sacrificial films 27 are formed on the sacrificial
film 17T; and the memory hole MH that has a depth reaching the
insulating film 33 from the upper surface of the inter-layer
insulating film 25T is formed. The connection portion JP is formed
in the interior of the inter-layer insulating film 23. This process
is the same as the manufacturing processes shown in FIG. 5A to FIG.
8A.
[0098] As shown in FIG. 21B, the support hole HR that has a depth
reaching the insulating film 53 from the upper surface of the
inter-layer insulating film 25T is formed in the draw-out region
HUR.
[0099] As shown in FIG. 22A, the memory film MF and the
semiconductor layer SF1 are stacked on the inner surface of the
memory hole MH. For example, the memory film MF has a structure in
which the blocking insulating film BLK, the charge trap film CT,
and the tunneling insulating film TN are stacked (referring to FIG.
3). The semiconductor layer SF1 is, for example, an amorphous
silicon layer and is formed on the memory film MF.
[0100] As shown in FIG. 22B, the memory film MF and the
semiconductor layer SF1 are formed also on the inner surface of the
support hole HR.
[0101] As shown in FIG. 23A, portions of the semiconductor layer
SF1, the memory film MF, and the insulating film 33 are selectively
removed at the bottom surface of the memory hole MH. Thereby, a
portion of the semiconductor base SB is exposed at the bottom
surface of the memory hole MH.
[0102] Also, as shown in FIG. 23B, portions of the semiconductor
layer SF1, the memory film MF, and the insulating film 53 are
selectively removed at the bottom surface of the support hole HR.
The insulating film 53 has a thickness such that the source layer
SL is not exposed at the bottom surface of the support hole HR.
[0103] As shown in FIG. 24A, portions of the insulating film 33 and
the lower end of the memory film MF are removed; and the bottom
portion of the memory hole MH is enlarged in the horizontal
direction.
[0104] Also, as shown in FIG. 24B, portions of the insulating film
53 and the lower end of the memory film MF are removed at the
bottom portion of the support hole HR. After this process as well,
the insulating film 53 is provided to be interposed between the
source layer SL and the bottom portion of the support hole HR.
[0105] As shown in FIG. 25A, the semiconductor layer SF2 that
covers the inner surface of the memory hole MH is formed. The
semiconductor layer SF2 is formed to contact the semiconductor base
SB and the semiconductor layer SF1.
[0106] As shown in FIG. 25B, the semiconductor layer SF2 that
covers the inner surface of the support hole HR is formed. In the
support hole HR, the semiconductor layer SF2 is not connected to
the source layer SL because the insulating film 53 is
interposed.
[0107] As shown in FIG. 26A, the insulating core CA is formed in
the interior of the memory hole MH after forming the semiconductor
layer SF in which the semiconductor layers SF1 and SF2 are formed
as one body. For example, the semiconductor layers SF1 and SF2 are
converted into a polysilicon layer by heat treatment and are formed
as one body. A capping layer SC is filled onto the insulating core
CA. The capping layer SC is, for example, an amorphous silicon
layer.
[0108] As shown in FIG. 26B, the semiconductor layer SF, the
insulating core CA, and the capping layer SC are formed also in the
interior of the support hole HR. The semiconductor layer SF is
electrically insulated from the source layer SL by the insulating
film 53.
[0109] Then, the word lines WL and the select gates SGS and SGD are
formed by the manufacturing processes shown in FIGS. 12A to 14B. In
the embodiment, the semiconductor layer SF that is provided in the
interior of the columnar support body SP is electrically insulated
from the source layer SL by the insulating film 53. For example,
even in the case where the contact plug CC contacts the
semiconductor layer SF due to positional shift of the mask
alignment, etc., the electrical insulation between the source layer
SL and the contact plug CC can be maintained.
Third Embodiment
[0110] FIG. 27 is a schematic cross-sectional view showing a memory
device 6 according to a third embodiment. FIG. 27 is a schematic
view showing a cross section of the columnar body PB. In the memory
device 6, the structure of the memory film MF is different between
the columnar portion PB1 that is positioned lower than the
connection portion JP and the columnar portion PB2 that is
positioned higher than the connection portion JP.
[0111] In the columnar portion PB1 as shown in FIG. 27, the
blocking insulating films BLK are provided respectively between the
charge trap film CT and the word lines WL1 and are separated from
each other in the Z-direction. Conversely, in the columnar portion
PB2, the blocking insulating film BLK is provided to extend to be
continuous in the Z-direction between the charge trap film CT and
the word lines WL2. The charge trap film CT and the tunneling
insulating film TN are provided to extend in the Z-direction along
the semiconductor layer SF.
[0112] A method for manufacturing the memory device 6 according to
the third embodiment will now be described with reference to FIG.
28A to FIG. 32B. FIG. 28A to FIG. 32B are schematic cross-sectional
views showing manufacturing processes of the memory device 6.
[0113] As shown in FIG. 28A, the insulating film 33 and blocking
insulating films BLK1 are formed in the interior of the memory hole
MH1 in which the semiconductor base SB is formed. The insulating
film 33 is, for example, a silicon oxide film and is formed by
oxidizing a portion of the semiconductor base SB. The blocking
insulating films BLK1 are, for example, silicon oxide films and are
formed by oxidizing the sacrificial films 17 exposed at the inner
wall of the memory hole MH1. The insulating film 33 and the
blocking insulating films BLK1 are formed simultaneously; and the
film thicknesses of the insulating film 33 and the blocking
insulating films BLK1 are controlled by the oxidization time of the
semiconductor base SB and the sacrificial films 17.
[0114] As shown in FIG. 28B, after forming the sacrificial layer 35
in the interior of the memory hole MH1, the connection portion JP
is formed; and the sacrificial layer 37 is formed in the interior
of the connection portion JP (referring to FIG. 5A to FIG. 6B). The
sacrificial layers 35 and 37 are, for example, amorphous silicon
layers.
[0115] As shown in FIG. 29A, the memory hole MH2 is formed after
alternately stacking the inter-layer insulating films 25 and the
sacrificial films 27 on the inter-layer insulating film 21 and the
sacrificial layer 37. The memory hole MH2 is formed to communicate
with the sacrificial layer 37 from the upper surface of the
inter-layer insulating film 25T of the uppermost layer.
[0116] As shown in FIG. 29B, a blocking insulating film BLK2 is
formed on the inner wall of the memory hole MH2. The blocking
insulating film BLK2 is, for example, a silicon oxide film. The
blocking insulating film BLK2 is formed by forming the blocking
insulating film BLK2 to cover the inner surface of the memory hole
MH2 and the upper surface of the inter-layer insulating film 25T
and by subsequently selectively removing the portion deposited on
the bottom surface of the memory hole MH2 and the portion deposited
on the upper surface of the inter-layer insulating film 25T. For
example, the blocking insulating film BLK2 is selectively removed
using anisotropic RIE.
[0117] As shown in FIG. 30A, the sacrificial layer 35 that is
filled into the memory hole MH1 and the sacrificial layer 37 that
is filled into the connection portion JP are selectively removed.
Thereby, the memory hole MH is formed in which the memory hole MH1,
the connection portion JP, and the memory hole MH2 are formed as
one body.
[0118] As shown in FIG. 30B, the charge trap film CT, the tunneling
insulating film TN, and the semiconductor layer SF1 are formed in
order on the inner surface of the memory hole MH. The charge trap
film CT is, for example, a silicon nitride film; and the tunneling
insulating film TN is, for example, a silicon oxide film. The
semiconductor layer SF1 is, for example, an amorphous silicon
layer.
[0119] As shown in FIG. 31A, portions of the semiconductor layer
SF1, the tunneling insulating film TN, the charge trap film CT, and
the insulating film 33 at the bottom surface of the memory hole MH
are selectively removed; and a portion of the semiconductor base SB
is exposed.
[0120] As shown in FIG. 31B, the lower ends of the tunneling
insulating film TN and the charge trap film CT and a portion of the
insulating film 33 are removed; and the lower end of the memory
hole MH is enlarged in the horizontal direction.
[0121] As shown in FIG. 32A, the semiconductor layer SF2 that
covers the inner surface of the memory hole MH is formed. The
semiconductor layer SF2 is, for example, an amorphous silicon layer
and contacts the semiconductor layer SF1. The semiconductor layer
SF2 is formed to contact the semiconductor base SB at the lower end
of the memory hole MH.
[0122] As shown in FIG. 32B, the insulating core CA is formed in
the interior of the memory hole MH after forming the semiconductor
layer SF in which the semiconductor layers SF1 and SF2 are formed
as one body. Further, the word lines WL and the select gates SGS
and SGD are formed by the manufacturing processes shown in FIGS.
12A to 14B.
[0123] In the embodiment, the blocking insulating films BLK1 and
the blocking insulating film BLK2 are formed separately in the
columnar portion PB1 and the columnar portion PB2. Thereby, the
electrical characteristics of the memory film MF can be controlled
independently between the columnar portions PB1 and PB2. For
example, a coupling ratio difference that is caused by an outer
diameter difference between the columnar portions PB1 and PB2 can
be reduced.
[0124] Embodiments will now be described with reference to the
drawings. The same portions inside the drawings are marked with the
same numerals; a detailed description is omitted as appropriate;
and the different portions are described. The drawings are
schematic or conceptual; and the relationships between the
thicknesses and widths of portions, the proportions of sizes
between portions, etc., are not necessarily the same as the actual
values thereof. The dimensions and/or the proportions may be
illustrated differently between the drawings, even in the case
where the same portion is illustrated.
* * * * *