U.S. patent application number 16/782623 was filed with the patent office on 2021-08-05 for switched capacitor circuits.
The applicant listed for this patent is Analog Devices International Unlimited Company. Invention is credited to Rares Andrei Bodnar, Pasquale Delizia.
Application Number | 20210242875 16/782623 |
Document ID | / |
Family ID | 1000005720904 |
Filed Date | 2021-08-05 |
United States Patent
Application |
20210242875 |
Kind Code |
A1 |
Bodnar; Rares Andrei ; et
al. |
August 5, 2021 |
SWITCHED CAPACITOR CIRCUITS
Abstract
A device having a capacitive sampling structure that allows for
removal of sampling noise can be implemented in a variety of
applications. Noise cancellation can be achieved by storing on an
auto-zero capacitor a scaled replica of kT/C noise by a mechanism
of correlated sampling. In an example embodiment, a set of switches
can be arranged such that, in switching, scaled thermal noise,
generated in an acquisition phase in which a voltage signal is
input to an input capacitor structure, is captured on an output
capacitor structure and, in a conversion phase, the captured
thermal noise is cancelled or compensated from an output of the
output capacitor structure.
Inventors: |
Bodnar; Rares Andrei;
(Berkshire, GB) ; Delizia; Pasquale; (Newbury,
GB) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Analog Devices International Unlimited Company |
Limerick |
|
IE |
|
|
Family ID: |
1000005720904 |
Appl. No.: |
16/782623 |
Filed: |
February 5, 2020 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03F 2200/372 20130101;
H03K 5/24 20130101; H03F 3/005 20130101; H03M 1/08 20130101 |
International
Class: |
H03M 1/08 20060101
H03M001/08; H03F 3/00 20060101 H03F003/00; H03K 5/24 20060101
H03K005/24 |
Claims
1. A device having a capacitive sampling structure, the device
comprising: an amplifier having an amplifier input and an amplifier
output; an input capacitor structure coupled to the amplifier
input; an output capacitor structure coupled to the amplifier
output; and a set of switches arranged with respect to the
amplifier such that, in switching, scaled thermal noise, generated
in an acquisition phase in which a voltage signal is input to the
input capacitor structure, is captured on the output capacitor
structure and, in a conversion phase, the captured thermal noise is
canceled or compensated from an output of the output capacitor
structure, the set of switches including: a first switch arranged
on an input side of the amplifier; and a second switch arranged on
the output side of the amplifier, with the first and second
switches arranged for synchronous correlated actuation.
2. The device of claim 10, wherein the device includes: a
comparator having a first comparator input coupled to the first
input of the amplifier and a second comparator input coupled to the
second input of the amplifier; a successive approximation register
(SAR) having a SAR input coupled to a comparator output of the
comparator; and an analog-to-digital converter (ADC) coupled to the
SAR, coupled to the input capacitor structure via a third switch,
and coupled to the second input capacitor structure via a fourth
switch.
3. The device of claim 1, wherein the first switch is coupled to a
resistor with the resistor coupled to the input capacitor structure
and to the amplifier.
4. The device of claim 3, wherein the set of switches includes a
third switch in parallel with the first switch coupled to the
resistor such that, in the acquisition phase, the third switch is
controlled to vary bandwidth associated with the input capacitor
structure and the resistor.
5. The device of claim 1, wherein the device includes a third
switch to couple a digital-to-analog converter to the input
capacitor structure with the third switch arranged to open before
the first switch closes and to close after the first switch
opens.
6. The device of claim 1, wherein the amplifier, the input
capacitor structure, the output capacitor structure, and the set of
switches are structured as a stage of an analog-to-digital
converter.
7. The device of claim 1, wherein the input capacitor structure is
an array of capacitors.
8. The device of claim 7, wherein the array of capacitors forms a
sampling charge redistribution digital-to-analog converter with one
or more capacitors of the array arranged to selectively couple
between an input voltage node and one or more voltage reference
nodes.
9. The device of claim 1, wherein the amplifier is one of a stage
of a multi-stage amplifier, a stage of a closed loop amplifier, a
stage of an integrator, and a stage of a comparator.
10. The device of claim 1, wherein the device includes: a second
input capacitor structure coupled to the amplifier at a second
input different from a first input at which the input capacitor
structure is coupled to the amplifier; a second output capacitor
structure coupled to the amplifier at a second output different
from a first output at which the output capacitor structure is
coupled to the amplifier; and a second amplifier coupled to the
output capacitor structure at a first input of the second amplifier
and coupled to the second output capacitor structure at a second
input of the second amplifier.
11. The device of claim 10, wherein the device includes one or more
feedback capacitors coupled between the second amplifier and the
amplifier using one or more switches along two paths of the device
configured with a differential input structure between the first
input capacitor structure and the second input capacitor
structure.
12. The device of claim 10, wherein the set of switches includes:
the first switch coupled to a first resistor with the first
resistor coupled to the input capacitor structure and to the first
input of the amplifier and with the first switch coupled to a
second resistor with the second resistor coupled to the second
input capacitor structure and to the second input of the amplifier;
and the second switch coupled to the output capacitor structure and
to the second output capacitor structure.
13. A method of noise reduction in a sampling structure, the method
comprising: operating a set of switches arranged with respect to an
amplifier to capture scaled thermal noise estimation on an output
capacitor structure coupled to the amplifier, during an acquisition
phase in which a voltage signal is input to an input capacitor
structure coupled to the amplifier; operating the set of switches,
in a conversion phase following the acquisition phase, to provide
an output voltage from an output of the output capacitor structure
without the scaled thermal noise estimation generated in the
acquisition phase; and synchronously actuating a first switch and a
second switch of the set of switches, with the first switch
arranged on an input side of the amplifier and the second switch
arranged on an output side of the amplifier to control the
acquisition phase and the conversion phase.
14. The method of claim 13, wherein the method includes correlated
actuating of the first switch and the second switch to a close
position in the acquisition phase and correlated actuating of the
first switch and the second switch to an open position in the
conversion phase.
15. The method of claim 14, wherein the method includes controlling
a third switch in a closed position for a portion of time that the
first switch is in a closed position to vary a sampling bandwidth
in the acquisition phase.
16. The method of claim 14, wherein the method includes controlling
a third switch to couple a digital-to-analog converter to the input
capacitor structure such that the third switch is opened before the
first switch closes and the third switch closes after the first
switch opens.
17. The method of claim 13, wherein the method includes: receiving
the output voltage from the output of the output capacitor
structure at an input of a second amplifier; and providing a second
output voltage from the second amplifier to an input of an
analog-to-digital stage, in response to generating the output
voltage at the output of the output capacitor structure in the
conversion phase following the acquisition phase.
18. A device having a sampling structure, the device comprising: a
first means for storing charge; a second means for storing charge;
a means for amplifying a signal; a means for capturing thermal
noise on an input of the means for amplifying a signal during an
acquisition phase in which a voltage signal is input to the first
means for storing charge, with the means for capturing thermal
noise being arranged on an input side of the means for amplifying a
signal; and a means for cancelling scaled thermal noise, generated
during the acquisition phase from the means for amplifying a
signal, from an output of the second means for storing charge
during a conversion phase, with the means for cancelling scaled
thermal noise arranged on the output side of the means for
amplifying a signal, with the means for capturing thermal noise and
the means for cancelling scaled thermal noise being arranged for
synchronous correlated actuation.
19. The device of claim 18, wherein the device includes a third
means for storing charge arranged with the first means for storing
charge and the means for amplifying a signal in a differential
implementation of a two-stage successive approximation register
analog-to-digital converter stage.
20. The device of claim 18, wherein the device includes a means for
varying a sampling bandwidth during the acquisition phase.
21. A device arranged for cancellation or compensation of scaled
thermal noise in a conversion phase from capture of the scaled
thermal noise in an acquisition phase, the device comprising: an
amplifier having an amplifier input and an amplifier output; an
input capacitor structure coupled to the amplifier input; an output
capacitor structure coupled to the amplifier output; a first switch
coupled to the amplifier input; and a second switch coupled to the
output capacitor structure with the output capacitor structure
between the second switch and the amplifier output, with the first
and second switches arranged for synchronous correlated
actuation.
22. The device of claim 21, wherein the device includes the first
switch coupled to the amplifier input by a resistor.
23. The device of claim 21, wherein the second switch is coupled to
and between two inputs of a second amplifier, with the second
amplifier having two outputs to provide an output signal.
24. The device of claim 21, wherein the device includes: a third
switch coupled to the input capacitor structure and to the
amplifier input; a fourth switch coupled to the input capacitor
structure at an end of the input capacitor structure opposite the
amplifier; and a digital-to-analog converter coupled to the fourth
switch at an end of the fourth switch opposite the input capacitor
structure.
25. The device of claim 21, wherein the device includes a second
input capacitor structure coupled to the amplifier at a second
input different from a first input of the amplifier at which the
input capacitor structure is coupled to the amplifier; a second
output capacitor structure coupled to the amplifier at a second
output different from a first output of the amplifier at which the
output capacitor structure is coupled to the amplifier with the
second output capacitor structure coupled to the second switch at
end of the second switch opposite the output capacitor structure;
and a comparator having a first comparator input coupled to the
first input of the amplifier and a second comparator input coupled
to the second input of the amplifier; a successive approximation
register (SAR) having a SAR input coupled to a comparator output of
the comparator; and an analog-to-digital converter (ADC) coupled to
the SAR, coupled to the input capacitor structure via a third
switch, and coupled to the second input capacitor structure via a
fourth switch.
26. The device of claim 25, wherein the device includes a second
amplifier coupled to the output capacitor structure at a first
input of the second amplifier and coupled to the second output
capacitor structure at a second input of the second amplifier; and
a set of feedback capacitors coupled between the second amplifier
and the amplifier using one or more switches along two paths to the
first and second inputs to the amplifier.
27. The device of claim 21, wherein the device includes a control
circuit to generate timing signals to the first switch, the second
switch, and a set of additional switches to perform sampling
operations associated with the amplifier.
28. A method of cancellation or compensation of scaled thermal
noise in a conversion phase of a device having a capacitive
sampling structure from capture of the scaled thermal noise in an
acquisition phase, the method comprising: closing a first switch
coupled to an amplifier input of an amplifier of the device with
the amplifier input coupled to an input capacitor structure:
closing a second switch coupled to an output capacitor structure
with the output capacitor structure between the second switch and
an output of the amplifier; opening the first switch after the
first switch has been closed for a first time interval; and opening
the second switch after the second switch has been closed for the
first time interval, with the first and second switches operated
with synchronous correlated actuation of closing and opening.
29. The method of claim 28, wherein the method includes varying a
sampling bandwidth in the acquisition phase by controlling a third
switch in a closed position for a portion of time that the first
switch is in a closed position.
30. The method of claim 28, wherein the method includes controlling
generation of timing signals to the first switch, the second
switch, and a set of additional switches to perform sampling
operations associated with the amplifier in a first stage of an
analog-to-digital converter with a differential arrangement of the
input capacitor structure with a second input capacitor structure
and with the amplifier in communication with a second stage of the
analog-to-digital converter.
Description
FIELD OF THE DISCLOSURE
[0001] This document relates to switched capacitor circuits and in
particular to removing sampling noise in switched
capacitor-amplifier circuits.
BACKGROUND
[0002] One of the main problems in precision converters is the
sampling noise of a capacitive digital-to-analog converter (DAC).
During an acquisition phase, the sampling structure exhibits a
noise with a root mean square (RMS) value equal to
kT C , ##EQU00001##
produced by resistors connected in series with a capacitor. In the
noise expression, k is Boltzmann's constant, T is the absolute
temperature, and C is the value of the sampling capacitor. It can
be seen, from the above relation, that in order to reduce the
acquisition noise, the size of the input capacitor can be increased
to levels which make the kT/C noise tolerable, which is
detrimental. This detrimental aspect is due mainly to the increased
size of the capacitor making it more difficult to drive the
capacitor by an analog front end. In addition, the increased size
of the capacitor slows down the conversion speed. That is, large
capacitors are difficult to drive, occupy large area, and slow down
conversion speed. As CMOS technology is scaling, the reference
voltage is also dropping, which forces the designer to further
increase the size of the sampling capacitors. Therefore, reducing
input capacitor size without impacting the sampled noise becomes
highly desirable.
SUMMARY OF THE DISCLOSURE
[0003] A device having a capacitive sampling structure that allows
for removal of sampling noise can be implemented in a variety of
applications. Noise cancellation can be achieved by storing on an
auto-zero capacitor a scaled replica of kT/C noise by a mechanism
of correlated sampling. In an example embodiment, a set of switches
can be arranged such that, in switching, scaled thermal noise,
generated in an acquisition phase in which a voltage signal is
input to an input capacitor structure, is captured on an output
capacitor structure and, in a conversion phase, the captured
thermal noise is cancelled or compensated from an output of the
output capacitor structure.
[0004] For example, in certain embodiments, a device, having a
capacitive sampling structure, can be provided that discloses: an
amplifier having an amplifier input and an amplifier output; an
input capacitor structure coupled to the amplifier input; an output
capacitor structure coupled to the amplifier output; and a set of
switches arranged with respect to the amplifier such that, in
switching, scaled thermal noise, generated in an acquisition phase
in which a voltage signal is input to the input capacitor
structure, is captured on the output capacitor structure and, in a
conversion phase, the captured thermal noise is canceled or
compensated from an output of the output capacitor structure.
[0005] In certain embodiments, a method of noise reduction in a
sampling structure can be provided that discloses: operating a set
of switches arranged with respect to an amplifier to capture scaled
thermal noise estimation on an output capacitor structure coupled
to the amplifier, during an acquisition phase in which a voltage
signal is input to an input capacitor structure coupled to the
amplifier; and operating the set of switches, in a conversion phase
following the acquisition phase, to provide an output voltage from
an output of the output capacitor structure without the scaled
thermal noise estimation generated in the acquisition phase.
[0006] In certain embodiments, a device, having a sampling
structure, can be provided that discloses: a first means for
storing charge; a second means for storing charge; a means for
amplifying a signal; a means for capturing thermal noise on an
input of the means for amplifying a signal during an acquisition
phase in which a voltage signal is input to the first means for
storing charge; and a means for canceling scaled thermal noise,
generated during the acquisition phase from the means for
amplifying a signal, from an output of the second means for storing
charge during a conversion phase.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The drawings, which are not necessarily drawn to scale,
illustrate generally, by way of example, but not by way of
limitation, various embodiments discussed in the present
disclosure.
[0008] FIG. 1 illustrates an example approach to a
two-stage-pipeline analog-to-digital converter, associated with
various embodiments.
[0009] FIG. 2 illustrates example signals provided to the switches
of the two-stage analog-to-digital converter of FIG. 1, associated
with various embodiments.
[0010] FIG. 3 is a schematic representation of a sampling phase of
an example noise cancellation technique in an analog-to-digital
converter stage, according to various embodiments.
[0011] FIG. 4 is a schematic representation of a residue generation
phase of the example noise cancellation technique in the
analog-to-digital converter stage associated with FIG. 3, according
to various embodiments.
[0012] FIG. 5 is a schematic representation of an example
differential implementation for a two-stage successive
approximation register analog-to-digital converter stage, according
to various embodiments.
[0013] FIG. 6 illustrates example signals provided to the switches
of the two-stage successive approximation register
analog-to-digital converter stage of FIG. 5, according to various
embodiments.
[0014] FIG. 7 is a representation of a successive approximation
register converter that can be adapted for application in noise
cancellation architectures, according to various embodiments.
[0015] FIG. 8 is a schematic representation of an example
differential implementation for a two-stage successive
approximation register analog-to-digital converter, which has the
structure of the example differential implementation for the
two-stage successive approximation register analog-to-digital
converter of FIG. 5 in which several switches are omitted,
according to various embodiments.
[0016] FIG. 9 illustrates example signals provided to the switches
of the two-stage successive approximation register
analog-to-digital converter of FIG. 8, according to various
embodiments.
[0017] FIG. 10 is an illustration of an example variable sampling
bandwidth implementation, according to various embodiments.
[0018] FIG. 11 illustrates example signals provided to the switches
of the implementation of FIG. 10, according to various
embodiments.
[0019] FIG. 12 is a flow diagram of a features of an example of an
example method of noise reduction in a sampling structure,
according to various embodiments.
DETAILED DESCRIPTION
[0020] The following provides a discussion of example embodiments
of switched capacitor circuits, in accordance with the teachings
herein. Such switched capacitor circuits illustrate architectures
that provide methods of removing sampling noise in charge
redistribution circuits. Such charge redistribution circuits can
include, but are not limited to, analog-to-digital converters. In
various embodiments, a tracking and synchronous sampling mechanism
of thermal noise generated by a band-limiting resistor and sampling
switches can be used to achieve a reduction of the noise sampled on
an input capacitor.
[0021] FIG. 1 illustrates an approach to a two-stage-pipeline
analog-to-digital converter (ADC). The approach can be extended to
more than two stages. A pipeline or multi-stage capacitive charge
redistribution ADC operates in two phases, where one phase is an
acquisition phase and the other phase is a conversion and residue
amplification phase. During the acquisition phase, selected ones
(S.sub.01, S.sub.02, and S.sub.03) of a set of switches (S.sub.01,
S.sub.02, S.sub.03, S.sub.04, and S.sub.05,) are closed and other
selected ones (S.sub.04 and S.sub.05) of the set are open. An input
signal, V.sub.IN at node 2, is acquired on a capacitor C that is
coupled to an amplifier 10 by switch S.sub.04 of the set selected
to be open during the acquisition phase. An amplifier is an
electronic device that receives an input signal and outputs a
scaled version of the input signal. The amount of scaling provided
by an amplifier is measured by its gain, which is a ratio of output
voltage, output current, or output power to its input. A resistor
R.sub.BW can be introduced in a capacitive charge redistribution in
order to limit the bandwidth of the acquired signal. Resistor Raw
can be implemented as resistance of switch S.sub.01. The amplifier
10 can have an input connected to a differentially low impedance
node, usually going through an offset nulling phase.
[0022] With switches S.sub.02 and S.sub.01 closed with switches
S.sub.04 and S.sub.05 open, capacitor C is coupled to node 2 to
receive V.sub.IN and is coupled to a comparator 6. A voltage
V.sub.C is developed across capacitor C. An output of comparator 6
is coupled to a successive approximation register (SAR) 7. Logic of
SAR 7 is used to provide an input to a DAC 5. An output of DAC 5
can be coupled to capacitor C when switch S.sub.05 is closed, where
at this time switch S.sub.02 is open.
[0023] During the conversion and residue amplification phase,
switches (S.sub.01, S.sub.02, and S.sub.03) that were closed in the
acquisition phase are opened and switches (S.sub.04 and S.sub.05)
that were open in the acquisition phase are closed. The switch
S.sub.04 that couples the capacitor C to amplifier 10, which can be
realized as a residue amplifier, is closed and a previously open
switch S.sub.05 is closed to selectively connect the other side of
the capacitor C, opposite the amplifier 10, to the output of DAC 5.
With the capacitor C being a capacitor array, selectively
connecting to the capacitor array can be based on a SAR algorithm.
The residue amplifier 10 scales the difference between a quantized
version of the input signal and the input signal, producing an
input voltage to a second stage 15 of the ADC. After the second
stage 15 of the ADC samples the amplifier voltage from the residue
amplifier, the second stage converts it to a numerical version. The
numerical results of the first stage and the second stage of the
ADC are then combined, resulting in a final ADC result. The
two-stage-pipeline ADC of FIG. 1 can be modified with a tracking
and synchronous sampling mechanism of thermal noise to achieve a
reduction of the noise sampled on the input capacitor C.
[0024] FIG. 2 illustrates example signals provided to the switches
of the two-stage ADC of FIG. 1. Signal 40 is provided to switches
S.sub.01, S.sub.02, and S.sub.03 during the acquisition and
conversion phases. With signal 40 high, these switches are closed
for acquisition, and these switches are open for conversion when
signal 40 is low. Signal 50 is provided to switches S.sub.04 and
S.sub.05 during the acquisition and conversion phases. With signal
50 low, these switches are open for acquisition, and these switches
are closed for conversion when signal 50 is high.
[0025] FIG. 3 is a schematic representation of a sampling phase of
an embodiment of an example noise cancellation technique in a first
ADC stage 100. FIG. 4 is a schematic representation of a residue
generation phase of the embodiment of the example noise
cancellation technique in first ADC stage 100 associated with FIG.
3. For ease of discussion, physical elements that tie the
components of FIGS. 3 and 4 to the sampling phase and the residue
generation phase are not shown.
[0026] FIG. 3 shows an input voltage, V.sub.in, at input 102 that
is coupled to an input capacitor C by a closed switch S.sub.2,
where input capacitor C is coupled to an input of amplifier 110,
which has a gain factor A. Amplifier 110 can be implemented as a
residue amplifier or a comparator pre-amplifier. Input capacitor C
and the input to amplifier 110 are also coupled to a band-limiting
resistor R.sub.BW that is coupled to a reference by switch S1.
Resistor Rbw can be implemented as other than a discrete resistor
in the integrated circuit, for example, it can be the resistance of
the switch S1. In the drawings it is introduced for the purpose of
showing that the resistance on the right hand side of the capacitor
dominates the series resistance. Thus, the predominant noise source
will be on the the right hand side of the capacitor C before the
amplifier 110. The noise of R.sub.BW and S1 is represented as a
sampling noise voltage V.sub.N1 to the input of amplifier 110. In
the example of FIG. 3, it can be assumed that the noise of R.sub.BW
and the resistance R.sub.S1 of switch S.sub.1 dominates the
sampling noise of resistance R.sub.S2 of switch S2, that is the
value of R.sub.BW+R.sub.S1 is much greater than R.sub.S2, and that
the bandwidth of the amplifier 110 is wide enough to allow the
tracking of V.sub.N1. A factor associated with much greater than
can be a factor of ten, a hundred, a thousand, or larger.
[0027] During the signal sampling phase, amplifier 110 is connected
to the right-hand side of sampling input capacitor C at node 101
and can operate in auto-zero mode. An auto-zero mode is a mode of
operation in which an input offset voltage of an amplifier is
reduced or cancelled. In some configurations, the right-hand side
101 of sampling input capacitor C is referred to as a top plate of
sampling input capacitor C. At this point in the signal sampling
phase with the voltage across the sampling input capacitor C being
V.sub.IN-V.sub.N1, the inputs of the amplifier 110 will be exposed
to the thermal noise V.sub.N1. Amplifier 110 scales this voltage
V.sub.N1 by the gain factor A, producing a voltage AV.sub.N1 at the
output of amplifier 110.
[0028] With the output of amplifier 110 coupled to an auto-zero
capacitor C.sub.AZ with the auto-zero capacitor C.sub.AZ coupled to
a reference by a closed auto-zero switch S.sub.AZ, the voltage
across C.sub.AZ is equal to AV.sub.N1. The reference can be ground
or some other low impedance node. The right-hand side of C.sub.AZ
is connected to a top of switch S.sub.AZ, opposite the reference to
which switch S.sub.AZ is connected, and to an output 107 of this
stage that can be coupled to a second stage. At the end of the
sampling phase, the top plate switch S.sub.1 and the amplifier
auto-zero switch S.sub.AZ are actuated by the same signal for
correlated action. This signal can be generated from a control
circuit to switches S.sub.1 and S.sub.AZ, though such a control
circuit is not shown in FIG. 3 or other figures for ease of
discussion.
[0029] Switches S.sub.1, S.sub.AZ and other switches, discussed
herein, can be implemented in a number of ways convenient for
integrated circuit construction, for example, but not limited to,
transistors arranged to be selectable between an on-mode or an
off-mode. The correlated action can be implemented in order to
capture the noise on the input capacitor C and auto-zero capacitor
C.sub.AZ. This capture can essentially be a simultaneous capture,
with possible small variation from simultaneous capture, since
there can be a fractional delay between the two instances. After
opening all switches S.sub.1, S.sub.2, and S.sub.AZ with switches
S.sub.1 and S.sub.AZ opened with the same signal, the circuit will
have stored, on the output capacitor C.sub.AZ, a scaled version,
AV.sub.N1, of the noise corrupting the signal sampled in the input
capacitor C.
[0030] After first ADC stage 100 has completed the numerical
conversion of the sampling phase, the switches S.sub.1, S.sub.2,
and S.sub.AZ are in an open state and the left-hand side of input
capacitor C is coupled to a closed switch S.sub.3 for a residue
generation phase. In this phase, the left-hand side of the input
capacitor C can be presented with the quantized representation
(V.sub.DAC) of the input voltage V.sub.IN, from a DAC, via closed
switch S.sub.3 coupled to the input 103 that receives V.sub.DAC.
Though not shown in FIGS. 3 and 4, the left-hand side of input
capacitor C can be coupled to both switch S.sub.2 and switch
S.sub.3, where control logic can provide open/close signals to
switch S.sub.2 and switch S.sub.3 in a complementary manner in
specified time periods. The voltage at node 101 of the right-hand
side of input capacitor C now becomes V.sub.DAC-V.sub.IN+ V.sub.N1
with switch S.sub.3 closed and switch S.sub.2 open. The output of
amplifier 110 can produce a voltage equal to A(V.sub.DAC-V.sub.IN+
V.sub.N1). Since at the end of the sampling phase, the voltage
across C.sub.AZ was AV.sub.IN, with polarity opposite the output of
amplifier 110, as shown in FIGS. 3 and 4, the voltage on the
right-hand-side of the auto-zero capacitor C.sub.AZ, coupled to
open switch S.sub.AZ and output 107 of first ADC stage 100, then
becomes A(V.sub.DAC-V.sub.IN). Thus, the kT/C noise of the input
sampling structure is cancelled out. The noise of amplifier 110 and
noise of output sampling structure (auto-zero) are ignored in the
description above as they would exist, regardless, and their
magnitude is not affected by the cancellation mechanism.
[0031] FIGS. 3 and 4 provide a single ended case for simplicity of
discussion. For the considerations below, the amplifier is assumed
to be an operational transconductance amplifier with a unity gain
bandwidth equal to
g m 2 .times. .times. .pi. .times. .times. C L , ##EQU00002##
where g.sub.m is the transconductance of the amplifier and C.sub.L
is the load capacitance, represented by C.sub.AZ in FIGS. 3 and 4.
In this example, the auto-zero bandwidth can be larger than the
bandwidth of the input signal to capture the noise during the
acquisition, which includes noise generated by R.sub.BW and
resistance R.sub.S1 of the switch S.sub.1:
1 2 .times. .times. .pi. .times. .times. R in .times. C g m 2
.times. .times. .pi. .times. .times. C az .times. A ,
##EQU00003##
where R.sub.in is the sum of R.sub.BW, R.sub.S1, and R.sub.S2, with
g.sub.m being the transconductance of amplifier 110. The sampling
noise can be bigger than the noise of C.sub.AZ:
KT C 4 3 .times. KT C az .times. A .fwdarw. C C az 3 4 .times. A .
##EQU00004##
Combining the above two expressions, the following results:
R i .times. n .times. g m 4 3 . ##EQU00005##
[0032] The above noise cancellation technique and noise
cancellation structure is described from the perspective of first
ADC stage 100, but this technique and structure can also be used in
a number of configurations. For example, the noise cancellation
technique/structure can be implemented in any stage of a
multi-stage ADC. Amplifier 110 can be implemented as a residue
amplifier or replaced with a pre-amplifier of a comparator.
Amplifier 110 can be replaced with a pre-amplifier of an
integrating residue amplifier. The noise cancellation
technique/structure can be implemented in any switched capacitor
circuit that involves a sampling capacitor and amplifier with or
without a feedback loop. For simplicity, the circuit in FIGS. 3 and
4 were presented in single-ended configuration, but it can be used
in differential configuration.
[0033] FIG. 5 is a schematic representation of an embodiment of an
example differential implementation for a two-stage SAR ADC 300.
Though a two-stage structure is shown in FIG. 5, practical
implementations can be extended for a multi-stage SAR converter.
Two-stage SAR ADC 300 includes a first ADC stage 315-1 and a second
ADC stage 315-2. First ADC stage 315-1 can include a positive rail
with input 302-1 for V.sub.IN+ and a negative rail with input 302-2
for V.sub.IN- for an input signal V.sub.IN between 302-1 and 302-2.
During the acquisition phase, switches S.sub.2P, S.sub.2N,
S.sub.3P, S.sub.3N, S.sub.1, S.sub.7P, S.sub.7N, S.sub.4P,
S.sub.4N, S.sub.5P, S.sub.5N, S.sub.6P, and S.sub.6N are configured
as shown in FIG. 5. During acquisition, the circuit works in a
similar manner to first ADC stage 100 of FIG. 3.
[0034] Similar to FIG. 3, input 302-1 for V.sub.IN+ is coupled to
the sampling capacitor C.sub.DAP by closed switch S.sub.2P and
input 302-2 for V.sub.IN- is coupled to the sampling capacitor
C.sub.DACN by closed switch S.sub.2N. Sampling capacitor C.sub.DACP
is coupled to an input of amplifier 310-1, where amplifier has a
gain factor A1, and to a band-limiting resistor having resistance
R.sub.BW/2. Sampling capacitor C.sub.DACN is coupled to another
input of amplifier 310-1 and to another band-limiting resistor
having resistance R.sub.BW/2. In this example, the value of the two
band-limiting resistors are equal. With switch S.sub.1 closed the
noise voltage of top resistance having value of R.sub.BW/2, bottom
resistance having value of R.sub.BW/2, and noise of switch S.sub.1
are presented to amplifier 310-1. Amplifier 310-1 scales the noise
input and presents the scaled noise at two outputs: one to the
designated positive auto-zero capacitor, C.sub.AZP, and one to the
designated negative auto-zero capacitor, C.sub.AZN. With switch
S.sub.AZ closed, the voltages across C.sub.AZP and C.sub.AZN are
the captured scaled noise. Rather than a reference, such as ground
or other low impedance node, switch S.sub.AZ is coupled between and
end of C.sub.AZP and an end of C.sub.AZN. One end of switch
S.sub.AZ is coupled to an input of an amplifier 310-2 and the other
end of switch S.sub.AZ is coupled to another input of amplifier
310-2. Amplifier 310-2 has a gain factor A2. An output voltage
V.sub.OUT can be taken between two outputs of amplifier 310-2.
These two outputs of amplifier 310-2 can be coupled to second ADC
stage 315-2.
[0035] In this example embodiment, first ADC stage 315-1 includes
feedback capacitors, C.sub.FBP and C.sub.FBN. In the acquisition
stage, C.sub.FBP is coupled to a reference, such as ground or other
low impedance node, by closed switches S.sub.4P and S.sub.5P, while
C.sub.FBN is coupled to a reference, such as ground or other low
impedance node, by closed switches S.sub.4N and S.sub.5N. C.sub.FBP
is uncoupled from an input of amplifier 310-1 by open switch
S.sub.7P and is uncoupled from an output of amplifier 310-2 by open
switch S.sub.6P. C.sub.FBN is uncoupled from the other input of
amplifier 310-1 by open switch S.sub.7N and is uncoupled from the
other output of amplifier 310-2 by open switch S.sub.6N. Thus, are
isolated from the noise capture process.
[0036] During the residue amplification phase, the position of each
of the switches is complemented, which means that closed switches
are opened, and open switches are closed. The voltages at the end
of sampling capacitors C.sub.DACP and C.sub.DACN are amplified to
comparator 306 whose output is coupled to a SAR register 307 that
feeds s DAC 305. With correlated switching, an output signal of DAC
305 at output 303-1 is provided to sampling capacitors C.sub.DACP
via closed switch S.sub.3P, and another output signal of DAC 305 at
output 303-2 is provided to sampling capacitors C.sub.DACN via
closed switch S.sub.3N. The residue charge of first ADC stage 315-1
is scaled via the feedback capacitors C.sub.FBP and C.sub.FBN. The
voltage V.sub.OUT produced at the output of amplifier 310-2 of
first ADC stage 315-1 equals:
V OUT = ( V D .times. A .times. C - V IN ) * C D .times. A .times.
C C F .times. B . ##EQU00006##
[0037] FIG. 6 illustrates an embodiment of example signals provided
to the switches of two-stage SAR ADC 300 of FIG. 5. Signal 440 is
provided to switches S.sub.1, S.sub.2P, S.sub.2N, S.sub.4P,
S.sub.4N, S.sub.5P, S.sub.5N, and S.sub.AZ during the acquisition
and conversion phases. With signal 440 high, these switches are
closed for acquisition, and these switches are open for conversion
when signal 440 is low. Signal 450 is provided to switches
S.sub.3P, S.sub.3N, S.sub.6P, S.sub.6N, S.sub.7P, and S.sub.7N
during the acquisition and conversion phases. With signal 450 low,
these switches are open for acquisition, and these switches are
closed for conversion when signal 450 is high.
[0038] FIG. 7 is a representation of a SAR converter 500 that can
be adapted for SAR register 307 and DAC 305 of first stage ADC
315-1 of two-stage SAR ADC 300 of FIG. 5. Sampling charge
redistribution DAC 305 is arranged to receive input from SAR
register 307 and provide an output to comparator 306. In this
example, an left capacitor terminal can selectively be switched to
V.sub.IN, a negative reference V.sub.REF- or a positive reference
V.sub.REF+ via a set of switches that can be controlled by SAR
logic, in order to sample the signal and produce the V.sub.DAC
voltage during the conversion phase.
[0039] FIG. 8 is a schematic representation of an embodiment of an
example differential implementation for a two-stage SAR ADC 400,
which has the structure of the example differential implementation
for two-stage SAR ADC 300 of FIG. 5 in which two switches in each
of the positive and negative path are omitted. Switches S.sub.7P,
S.sub.7P, S.sub.4P, and S.sub.4N are omitted, which directly
connects the feedback capacitors C.sub.FBP and C.sub.FBN to the
inputs of amplifier 310-1. This can provide for better noise
cancellation, which is otherwise limited by the feedback ratio
shown above in the discussion of FIG. 5. This enhanced noise
cancellation comes at the cost of extra load capacitance and charge
disturbance on S.sub.1 during the acquisition phase.
[0040] FIG. 9 illustrates an embodiment of example signals provided
to the switches of two-stage SAR ADC 400 of FIG. 8. Signal 740 is
provided to switches S.sub.1, S.sub.2P, S.sub.2N, S.sub.5P,
S.sub.5N and S.sub.AZ during the acquisition and conversion phases.
With signal 740 high, these switches are closed for acquisition,
and these switches are open for conversion when signal 740 is low.
Signal 750 is provided to switches S.sub.3P, S.sub.3N, S.sub.6P,
and S.sub.6N during the acquisition and conversion phases. With
signal 750 low, these switches are open for acquisition, and these
switches are closed for conversion when signal 750 is high.
[0041] The settling of an input signal for an RC sampling structure
is described by an exponential equation:
V.sub.C(t)=V.sub.IN+(V.sub.C(t.sub.0)-V.sub.IN)e.sup.-t/RC,
where V.sub.C(t.sub.0) is the capacitor voltage at the beginning of
the input phase, V.sub.IN is the input voltage (assumed constant
for simplicity), t is the time duration of the input signal
acquisition, and R is the total resistance in series with the
capacitor (C). From this, it can be seen that, if R.sub.BW is made
very large in the example of FIGS. 3, 4, 5, and 8, the input signal
will not be acquired accurately. Once again, a large R.sub.BW with
respect to R.sub.S2 of switch S.sub.2 in FIGS. 3-5 and 8 is
desirable such that the noise on the right-hand side of the input
capacitor dominates the sampling noise (kT/C).
[0042] In order to avoid incomplete settling of the signal during
acquisition, the bandwidth of the sampling structure can be varied
during the acquisition phase. This would allow for a fast settling
of the signal at the beginning of the acquisition phase, followed
by a noise tracking/cancellation, with nominal bandwidth that is
most suited for the signal and circuit.
[0043] FIG. 10 is an illustration of an embodiment of an example
variable sampling bandwidth implementation 800. Switch S.sub.9 is
introduced in parallel with R.sub.BW and S.sub.1 in the arrangement
of first ADC stage 100 of FIGS. 3 and 4, allowing for a wider
sampling bandwidth for the first part of the acquisition period.
FIG. shows the implementation 800 in an acquisition phase with V
coupled by closed switch S.sub.2 to the sampling capacitor C, where
switch S.sub.3 is open such that the output 803 of DAC 805 is
uncoupled from the sampling capacitor C. With switches S.sub.1 and
S.sub.AZ closed, the voltage V.sub.N1 is presented to amplifier
810, having gain factor A, the scaled voltage AV.sub.N1 captured by
capacitor C.sub.AZ at the output of amplifier.
[0044] FIG. 11 illustrates an embodiment of example signals
provided to the switches of implementation 800 of FIG. 10. Signal
940 is provided to switches S.sub.1, S.sub.2, and S.sub.AZ during
the acquisition and conversion phases. With signal 940 high, these
switches are closed for acquisition, and these switches are open
for conversion when signal 940 is low. Signal 950 is provided to
switch S.sub.3 during the acquisition and conversion phases. With
signal 950 low, switch S.sub.3 is open for acquisition, and is
closed for conversion when signal 950 is high. Signal 960 is
provided to switch S.sub.9 during the acquisition and conversion
phases, which allows for a wider sampling bandwidth for the first
part of the acquisition period. Switch S.sub.9 is changed from its
open position to its closed position when switches S.sub.1,
S.sub.2, and S.sub.AZ changed from their open positions to their
closed positions. Switch S.sub.9 is changed from its closed
position to its open position, while switches S.sub.1, S.sub.2, and
S.sub.AZ remain their closed positions. Switch S.sub.9 is again
changed from its open position to its closed position when switches
S.sub.1, S.sub.2, and S.sub.AZ are again changed from their open
positions to their closed positions.
[0045] The structures and signals of FIGS. 3-11 illustrate a noise
reduction technique for an electronic capacitive sampling structure
that can be applied in a number of architectures. A first example
capacitive signal sampling circuit with reduced noise can comprise:
an input node that in use receives a voltage signal; a switch
connected to the input node and a second node; a switch connected
between the second node and a low impedance node; a capacitor
connected between the second node and a third node; a switch
connected between the third node and a low impedance node; an
amplifier having an input connected to the third node; and a
voltage sampling structure at the output of the amplifier, in which
these components are arranged such that during a signal acquisition
phase, the circuit tracks the input voltage and the switch on the
right-hand side of the input capacitor is closed, which is
conveniently sized to dominate the noise sampled on the input
capacitor at the end of the acquisition phase. The amplifier output
produces a scaled version of the voltage across the switch
connected to its input coupled to the third node. The switch
connected to the input of the amplifier can be actuated
synchronously with the switching circuitry of the sampling
structure connected to the output of the amplifier.
[0046] Example capacitive signal sampling circuits can be realized
as variations of the first example capacitive signal sampling
circuit. For example, variations of the first example capacitive
signal sampling circuit can be structured as a stage of an
analog-to-digital converter. For such a structure, the sampling
structure at the output of the amplifier can be part of a second
analog-to-digital converter. These variations of the first example
capacitive signal sampling circuit can include another charge
redistribution structure connected at the third node, which is the
amplifier input node.
[0047] The input capacitor of a variation of the first example
capacitive signal sampling circuit can be formed of an array of
capacitors. The array of capacitors can form a sampling charge
redistribution DAC, where the left-hand side of the capacitor array
can be selectively connected between the input node and voltage
reference nodes. A variation of the first example capacitive signal
sampling circuit can include, the during the acquisition phase,
operating with the bandwidth of the input sampling structure being
variable.
[0048] A variation of the first example capacitive signal sampling
circuit can include a second switch that is connected in parallel
with the switch connected at the input of the amplifier, which is
open before the switch is connected at the input of the amplifier.
Variations of the first example capacitive signal sampling circuit
can include the amplifier realized in a number of different
implementations. The amplifier can be a stage of a multi-stage
amplifier. The amplifier can be a stage of a closed loop amplifier.
Such a structure can include feedback via capacitors. The amplifier
can be a stage of an integrator. The amplifier can be a stage of a
comparator.
[0049] A variation of the first example capacitive signal sampling
circuit can include an auxiliary circuit introduced to reduce the
variation of the signal at node 3, which is the input of the
amplifier. A variation of the first example capacitive signal
sampling circuit can include two or more stages, where each stage
is structured similar or identical to the first example capacitive
signal sampling circuit. A variation of the first example
capacitive signal sampling circuit can include the bandwidth of the
amplifier and output sampling structure conveniently configured to
give maximum noise rejection.
[0050] FIG. 12 is a flow diagram of features of an embodiment of an
example method 1200 of noise reduction in a sampling structure. At
1210, a set of switches arranged with respect to an amplifier are
operated to capture scaled thermal noise estimation on an output
capacitor structure coupled to the amplifier. The capture of the
scaled thermal noise estimation is conducted during an acquisition
phase in which a voltage signal is input to an input capacitor
structure coupled to the amplifier. At 1220, the set of switches
are operated, in a conversion phase following the acquisition
phase, to provide an output voltage from an output of the output
capacitor structure without the scaled thermal noise estimation
generated in the acquisition phase.
[0051] Variations of method 1200 or methods similar to method 1200
can include a number of different embodiments that may be combined
depending on the application of such methods and/or the
architecture of systems in which such methods are implemented. Such
methods can include actuating a first switch and a second switch of
the set of switches in a correlated manner to a close position in
the acquisition phase and actuating, in another correlated manner,
the first switch and the second switch to an open position in the
conversion phase. Such methods can include controlling a third
switch in a closed position for a portion of time that the first
switch is in a closed position to vary a sampling bandwidth in the
acquisition phase.
[0052] Variations of method 1200 or methods similar to the method
1200 can include controlling a fourth switch to couple a
digital-to-analog converter to the input capacitor structure such
that the fourth switch is opened before the first switch closes and
the fourth switch closes after the first switch opens. Variations
of method 1200 or methods similar to the method 1200 can include
receiving the output voltage from the output of the output
capacitor structure at an input of a second amplifier: and
providing a second output voltage from the second amplifier to an
input of an analog-to-digital stage, in response to generating the
output voltage at the output of the output capacitor structure in
the conversion phase following the acquisition phase.
[0053] In various embodiments, a device, having a capacitive
sampling structure, can comprise: an amplifier having an amplifier
input and an amplifier output; an input capacitor structure coupled
to the amplifier input; an output capacitor structure coupled to
the amplifier output; and a set of switches arranged with respect
to the amplifier. The set of switches can be operated such that, in
switching, scaled thermal noise is captured on the output capacitor
structure in an acquisition phase, and, in a conversion phase, the
captured thermal noise is canceled or compensated from an output of
the output capacitor structure. The scaled thermal noise can be
generated in the acquisition phase in which a voltage signal is
input to the input capacitor structure. The set of switches can
include a first switch arranged on an input side of the amplifier
and a second switch arranged on the output side of the amplifier,
with the first and second switches arranged for correlated
actuation.
[0054] Variations of such a device or similar devices can include a
number of different embodiments that may be combined depending on
the application of such devices and/or the architecture of systems
in which such devices are implemented. The device can include the
first switch coupled to a resistor with the resistor coupled to the
input capacitor structure and to the amplifier. The set of switches
can include a third switch in parallel with the first switch
coupled to the resistor such that, in the acquisition phase, the
third switch is controlled to vary bandwidth associated with the
input capacitor structure and the resistor. Variations of such a
device or similar devices can include a fourth switch to couple a
digital-to-analog converter to the input capacitor structure with
the fourth switch arranged to open before the first switch closes
and to close after the first switch opens.
[0055] Variations of such a device or similar devices can include
the amplifier, the input capacitor structure, the output capacitor
structure and the set of switches structured as a stage of an
analog-to-digital converter. The amplifier can be one of a stage of
a multi-stage amplifier, a stage of a closed loop amplifier, a
stage of an integrator, and a stage of a comparator. In various
embodiments, the input capacitor structure can be an array of
capacitors. The array of capacitors can form a sampling charge
redistribution digital-to-analog converter with one or more
capacitors of the array arranged to selectively couple between an
input voltage node and one or more voltage reference nodes.
[0056] Variations of such a device or similar devices can include a
second input capacitor structure coupled to the amplifier at a
second input different from a first input at which the input
capacitor structure is coupled to the amplifier; a second output
capacitor structure coupled to the amplifier at a second output
different from a first output at which the output capacitor
structure is coupled to the amplifier; and a second amplifier
coupled to the output capacitor structure at a first input of the
second amplifier and coupled to the second output capacitor
structure at a second input of the second amplifier. Variations can
include the device including one or more feedback capacitors
coupled between the second amplifier and the amplifier using one or
more switches along two paths of the device configured with a
differential input structure between the first input capacitor
structure and the second input capacitor structure.
[0057] Variations of such a device or similar devices, having a
capacitive sampling structure, can include the set of switches
having: a first switch arranged on an input side of the amplifier
with the first switch coupled to a first resistor with the first
resistor coupled to the input capacitor structure and to the first
input of the amplifier and with the first switch coupled to a
second resistor with the second resistor coupled to the second
input capacitor structure and to the second input of the amplifier;
and a second switch arranged on the output side of the amplifier
with the second switch coupled to the output capacitor structure
and to the second output capacitor structure, with the second
switch arranged with the first switch for correlated actuation.
[0058] In various embodiments, a device, having a capacitive
sampling structure, can comprise: a first means for storing charge;
a second means for storing charge; a means for amplifying a signal;
a means for capturing thermal noise on an input of the means for
amplifying a signal during an acquisition phase in which a voltage
signal is input to the first means for storing charge; and a means
for cancelling scaled thermal noise, generated during the
acquisition phase from the means for amplifying a signal, from an
output of the second means for storing charge during a conversion
phase.
[0059] Variations of such a device or similar devices can include a
number of different embodiments that may be combined depending on
the application of such devices and/or the architecture of systems
in which such devices are implemented. The device can include the
means for capturing thermal noise being arranged on an input side
of the means for amplifying a signal and the means for cancelling
scaled thermal noise is arranged on the output side of the means
for amplifying a signal, with the means for capturing thermal noise
and the means for cancelling scaled thermal noise arranged for
simultaneous actuation. Such devices can include a means for
varying a sampling bandwidth during the acquisition phase.
[0060] The following are example embodiments of switched capacitor
circuits and associated methods, in accordance with the teachings
herein. Such architectures and methods allow for removing sampling
noise in charge redistribution circuits. Such charge redistribution
circuits can include, but are not limited to, analog to digital
converters.
[0061] An example device 1, having a capacitive sampling structure,
can comprise: an amplifier having an amplifier input and an
amplifier output: an input capacitor structure coupled to the
amplifier input; an output capacitor structure coupled to the
amplifier output; and a set of switches arranged with respect to
the amplifier such that, in switching, scaled thermal noise,
generated in an acquisition phase in which a voltage signal is
input to the input capacitor structure, is captured on the output
capacitor structure and, in a conversion phase, the captured
thermal noise is canceled or compensated from an output of the
output capacitor structure.
[0062] An example device 2, having a capacitive sampling structure,
can include features of example device 1 and can include the set of
switches including a first switch arranged on an input side of the
amplifier and a second switch arranged on the output side of the
amplifier, with the first and second switches arranged for
correlated actuation.
[0063] An example device 3, having a capacitive sampling structure,
can include features of example device 2 or features of any of the
preceding example devices and can include the first switch is
coupled to a resistor with the resistor coupled to the input
capacitor structure and to the amplifier.
[0064] An example device 4, having a capacitive sampling structure,
can include features of example device 3 or features of any of the
preceding example devices and can include the set of switches
including a third switch in parallel with the first switch coupled
to the resistor such that, in the acquisition phase, the third
switch is controlled to vary bandwidth associated with the input
capacitor structure and the resistor.
[0065] An example device 5, having a capacitive sampling structure,
can include features of example device 2 or features of any of the
preceding example devices and can include another switch to couple
a digital-to-analog converter to the input capacitor structure with
the other switch arranged to open before the first switch closes
and to close after the first switch opens.
[0066] An example device 6, having a capacitive sampling structure,
can include features of any of the preceding example devices and
can include the amplifier, the input capacitor structure, the
output capacitor structure and the set of switches being structured
as a stage of an analog-to-digital converter.
[0067] An example device 7, having a capacitive sampling structure,
can include features of any of the preceding example devices and
can include the input capacitor structure being an array of
capacitors.
[0068] An example device 8, having a capacitive sampling structure,
can include features of example device 7 or features of any of the
preceding example devices and can include the array of capacitors
forming a sampling charge redistribution digital-to-analog
converter with one or more capacitors of the array arranged to
selectively couple between an input voltage node and one or more
voltage reference nodes.
[0069] An example device 9, having a capacitive sampling structure,
can include features of any of the preceding example devices and
can include the amplifier being one of a stage of a multi-stage
amplifier, a stage of a closed loop amplifier, a stage of an
integrator, and a stage of a comparator.
[0070] An example device 10, having a capacitive sampling
structure, can include features of any of the preceding example
devices and can include a second input capacitor structure coupled
to the amplifier at a second input different from a first input at
which the input capacitor structure is coupled to the amplifier; a
second output capacitor structure coupled to the amplifier at a
second output different from a first output at which the output
capacitor structure is coupled to the amplifier; and a second
amplifier coupled to the output capacitor structure at a first
input of the second amplifier and coupled to the second output
capacitor structure at a second input of the second amplifier.
[0071] An example device 11, having a sampling structure, can
include features of example device 10 or features of any of the
preceding example devices and can include the device including one
or more feedback capacitors coupled between the second amplifier
and the amplifier using one or more switches along two paths of the
device configured with a differential input structure between the
first input capacitor structure and the second input capacitor
structure.
[0072] An example device 12, having a sampling structure, can
include features of example device 10 or features of any of the
preceding example devices and can include the set of switches
including: a first switch arranged on an input side of the
amplifier with the first switch coupled to a first resistor with
the first resistor coupled to the input capacitor structure and to
the first input of the amplifier and with the first switch coupled
to a second resistor with the second resistor coupled to the second
input capacitor structure and to the second input of the amplifier;
and a second switch arranged on the output side of the amplifier
with the second switch coupled to the output capacitor structure
and to the second output capacitor structure, with the second
switch arranged with the first switch for correlated actuation.
[0073] An example device 13, having a sampling structure, can
comprise: a first means for storing charge; a second means for
storing charge; a means for amplifying a signal; a means for
capturing thermal noise on an input of the means for amplifying a
signal during an acquisition phase in which a voltage signal is
input to the first means for storing charge; and a means for
cancelling scaled thermal noise, generated during the acquisition
phase from the means for amplifying a signal, from an output of the
second means for storing charge during a conversion phase.
[0074] An example device 14, having a capacitive sampling
structure, can include features of example device 13 and can
include the means for capturing thermal noise being arranged on an
input side of the means for amplifying a signal and the means for
cancelling scaled thermal noise is arranged on the output side of
the means for amplifying a signal, with the means for capturing
thermal noise and the means for canceling scaled thermal noise
arranged for simultaneous actuation.
[0075] An example device 15, having a capacitive sampling
structure, can include features of example devices 13 and 14 and
can include a means for varying a sampling bandwidth during the
acquisition phase.
[0076] An example method 1 of noise reduction in a sampling
structure can comprise: operating a set of switches arranged with
respect to an amplifier to capture scaled thermal noise estimation
on an output capacitor structure coupled to the amplifier, during
an acquisition phase in which a voltage signal is input to an input
capacitor structure coupled to the amplifier; and operating the set
of switches, in a conversion phase following the acquisition phase,
to provide an output voltage from an output of the output capacitor
structure without the scaled thermal noise estimation generated in
the acquisition phase.
[0077] An example method 2 of noise reduction in a sampling
structure can include features of example method 1 and can include
correlated actuating of a first switch and a second switch of the
set of switches to a close position in the acquisition phase and
correlated actuating of the first switch and the second switch to
an open position in the conversion phase.
[0078] An example method 3 of noise reduction in a sampling
structure can include features of example method 2 or features of
any of the preceding example methods and can include controlling a
third switch in a closed position for a portion of time that the
first switch is in a closed position to vary a sampling bandwidth
in the acquisition phase.
[0079] An example method 4 of noise reduction in a sampling
structure can include features of example method 2 or features of
any of the preceding example methods and can include controlling
another switch to couple a digital-to-analog converter to the input
capacitor structure such that the other switch is opened before the
first switch closes and the third switch closes after the first
switch opens.
[0080] An example method 5 of noise reduction in a sampling
structure can include features of any of the preceding example
methods and can include receiving the output voltage from the
output of the output capacitor structure at an input of a second
amplifier; and providing a second output voltage from the second
amplifier to an input of an analog-to-digital stage, in response to
generating the output voltage at the output of the output capacitor
structure in the conversion phase following the acquisition
phase.
[0081] An example method 6 of noise reduction in a sampling
structure can include features of any of the preceding example
methods of noise reduction in a sampling structure and can include
performing functions associated with any features of example
devices 1-15 having a capacitive sampling structure and any
features of example devices associated with the figures herein.
[0082] The above detailed description refers to the accompanying
drawings that show, by way of illustration and not limitation,
various embodiments that can be practiced. These embodiments are
described in sufficient detail to enable those skilled in the art
to practice these and other embodiments. Other embodiments may be
utilized, and structural, logical, mechanical, and electrical
changes may be made to these embodiments. The various embodiments
are not necessarily mutually exclusive, as some embodiments can be
combined with one or more other embodiments to form new
embodiments. The above detailed description is, therefore, not to
be taken in a limiting sense.
[0083] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement that is calculated to achieve the
same purpose may be substituted for the specific embodiments shown.
Various embodiments use permutations and/or combinations of
embodiments described herein. It is to be understood that the above
description is intended to be illustrative, and not restrictive,
and that the phraseology or terminology employed herein is for the
purpose of description.
* * * * *