U.S. patent application number 17/162188 was filed with the patent office on 2021-07-15 for semiconductor device and semiconductor device manufacturing method.
This patent application is currently assigned to SONY CORPORATION. The applicant listed for this patent is SONY CORPORATION. Invention is credited to Takushi SHIGETOSHI, Takanori TADA.
Application Number | 20210217623 17/162188 |
Document ID | / |
Family ID | 1000005481935 |
Filed Date | 2021-07-15 |
United States Patent
Application |
20210217623 |
Kind Code |
A1 |
SHIGETOSHI; Takushi ; et
al. |
July 15, 2021 |
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING
METHOD
Abstract
The present invention aims to improve the accuracy and stability
when removing an insulating film at a bottom of a TSV to allow a
through hole to open toward a connection target electrode. A
semiconductor device manufacturing method including: forming a
through hole in a semiconductor substrate by using anisotropic
etching performed from a first surface side of the semiconductor
substrate; forming a thin film being an insulating film on an
entire inner surface of the through hole; forming a
carbon-containing thin film using plasma deposition on the first
surface including an opening edge portion of the through hole;
engraving an inner bottom of the through hole by using anisotropic
plasma etching with the carbon-containing thin film as a mask;
removing the carbon-containing thin film by ashing; and forming a
through-substrate electrode in the through hole.
Inventors: |
SHIGETOSHI; Takushi;
(Nagasaki, JP) ; TADA; Takanori; (Nagasaki,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SONY CORPORATION |
Tokyo |
|
JP |
|
|
Assignee: |
SONY CORPORATION
Tokyo
JP
|
Family ID: |
1000005481935 |
Appl. No.: |
17/162188 |
Filed: |
January 29, 2021 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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16308071 |
Dec 7, 2018 |
10930516 |
|
|
PCT/JP2017/017327 |
May 8, 2017 |
|
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17162188 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/32136 20130101;
H01L 21/3205 20130101; H01L 21/31116 20130101; H01L 21/768
20130101; H01L 23/522 20130101; H01L 23/481 20130101; H01L 21/76802
20130101; H01L 21/3065 20130101; H01L 21/31144 20130101 |
International
Class: |
H01L 21/3065 20060101
H01L021/3065; H01L 23/522 20060101 H01L023/522; H01L 21/311
20060101 H01L021/311; H01L 23/48 20060101 H01L023/48; H01L 21/768
20060101 H01L021/768; H01L 21/3205 20060101 H01L021/3205; H01L
21/3213 20060101 H01L021/3213 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 15, 2016 |
JP |
2016-118730 |
Claims
1-5. (canceled)
6. A semiconductor device comprising: a semiconductor substrate; a
wiring layer stacked on a first surface of the semiconductor
substrate, wherein a first portion of the wiring layer comprises a
metal film and a second portion of the wiring layer comprises a
first insulating film, wherein the first insulating film is
provided adjacent to a semiconductor substrate-side of the metal
film; a through-substrate electrode penetrating from a second
surface of the semiconductor substrate; a second insulating film
interposed between the through-substrate electrode and the
semiconductor substrate; and a third insulating film adhered to an
end portion of the second insulating film adjacent to the second
surface of the semiconductor substrate.
7. The semiconductor device of claim 6, wherein the first
insulating film is etched.
8. The semiconductor device of claim 7, wherein the
through-substrate electrode is formed to a depth reaching a midway
depth of the first insulating film.
9. The semiconductor device of claim 6, wherein the second
insulating film covers an inner surface of a through hole.
10. The semiconductor device of claim 6, wherein the second
insulating film comprises a low dielectric constant interlayer
insulating film material.
11. The semiconductor device of claim 6, wherein the third
insulating film comprises one of SiO2, SiN, and SiON.
12. The semiconductor device of claim 6, wherein the third
insulating film comprises a thickness between 10 nm and 100 nm.
13. A method of manufacturing a semiconductor device, the method
comprising: forming a semiconductor substrate; forming a wiring
layer on a first surface of the semiconductor substrate, wherein a
first portion of the wiring layer comprises a metal film and a
second portion of the wiring layer comprises a first insulating
film, wherein the first insulating film is provided adjacent to a
semiconductor substrate-side of the metal film; forming a
through-substrate electrode penetrating from a second surface of
the semiconductor substrate to the metal film; forming a second
insulating film interposed between the through-substrate electrode
and the semiconductor substrate; and forming a third insulating
film adhered to an end portion of the second insulating film
adjacent to the second surface of the semiconductor substrate.
14. The method of claim 13, wherein the first insulating film is
etched.
15. The method of claim 14, wherein the through-substrate electrode
is formed to a depth reaching a midway depth of the first
insulating film.
16. The method of claim 6, wherein the second insulating film
covers an inner surface of a through hole.
17. The method of claim 13, wherein the second insulating film
comprises a low dielectric constant interlayer insulating film
material.
18. The method of claim 13, wherein the third insulating film
comprises one of SiO2, SiN, and SiON.
19. The method of claim 13, wherein the third insulating film
comprises a thickness between 10 nm and 100 nm.
20. An electronic device comprising: a semiconductor device
comprising: a semiconductor substrate; a wiring layer stacked on a
first surface of the semiconductor substrate, wherein a first
portion of the wiring layer comprises a metal film and a second
portion of the wiring layer comprises a first insulating film,
wherein the first insulating film is provided adjacent to a
semiconductor substrate-side of the metal film; a through-substrate
electrode penetrating from a second surface of the semiconductor
substrate to the metal film; a second insulating film interposed
between the through-substrate electrode and the semiconductor
substrate; and a third insulating film adhered to an end portion of
the second insulating film adjacent to the second surface of the
semiconductor substrate.
21. The electronic device of claim 20, wherein the first insulating
film is etched.
22. The electronic device of claim 21, wherein the
through-substrate electrode is formed to a depth reaching a midway
depth of the first insulating film.
23. The electronic device of claim 20, wherein the second
insulating film covers an inner surface of a through hole.
24. The electronic device of claim 20, wherein the second
insulating film comprises a low dielectric constant interlayer
insulating film material.
25. The electronic device of claim 20, wherein the third insulating
film comprises one of SiO2, SiN, and SiON.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 16/308,071, filed on Dec. 7, 2018, which is a national stage
application under 35 U.S.C. 371 and claims the benefit of PCT
Application No. PCT/JP2017/017327 having an international filing
date of May 8, 2017, which designated the United States, which PCT
application claimed the benefit of Japanese Patent Application No.
2016-118730 filed Jun. 15, 2016, the entire disclosures of each of
which are incorporated herein by reference.
TECHNICAL FIELD
[0002] The present technology relates to a semiconductor device and
a semiconductor device manufacturing method.
BACKGROUND ART
[0003] In recent years, the development of three-dimensional
mounting technology using a through silicon via (TSV) is gaining
momentum as a method to realize further enhanced functionality of
semiconductor devices. Although the size of the current TSV has a
width of several .mu.m and an aspect ratio of about 10 or less, it
is expected to achieve further downsized TSV with higher
integration in order to achieve more signal transmission volume and
smaller device size.
[0004] The formation of TSV is implemented by first forming a
through hole penetrating a silicon substrate to reach a connection
target electrode or its vicinity, forming an insulating film on a
field portion and an inner surface of the through hole, removing
the insulating film at the bottom of the through hole to allow the
through hole to open toward the connection target electrode, and
burying a barrier metal film and a metal inside the through hole to
form a through-substrate electrode.
[0005] Here, Patent Documents 1 and 2 disclose technologies of
removing the insulating film at the bottom of the TSV to allow the
through hole to open toward the connection target electrode.
[0006] Patent Document 1 discloses that an insulating film provided
on a field portion and an inner surface of a through hole is formed
by using an insulating film with low coverage so that the
insulating film on the inner surface near an upper portion of the
through hole becomes thicker so as to form the through hole in an
overhanging shape. This makes it possible to remove the insulating
film alone at the bottom of the through hole while protecting the
insulating film on the inner surface of the through hole.
[0007] In Patent Document 2, an insulating film provided on a field
portion and an inner surface of a through hole is formed by using
an insulating film with high coverage, and a resist film is formed
above the field portion and the inner surface of the through hole
from above the insulating film by a lithography method so that the
width in the vicinity of the upper portion of the through hole
becomes narrower than the width of the bottom of the through hole.
This makes it possible to remove the insulating film alone at the
bottom of the through hole while protecting the insulating film on
the inner surface of the through hole.
CITATION LIST
Patent Document
[0008] Patent Document 1: Japanese Patent Application Laid-Open No.
2014-110287
[0009] Patent Document 2: Japanese Patent Application Laid-Open No.
2010-114201
SUMMARY OF THE INVENTION
Problems to be Solved by the Invention
[0010] The technique described in Patent Document 1 described above
forms the insulating film inside the through hole so as to have an
overhanging shape, leading to reduction of the opening width of the
upper portion of the through hole due to compression by the
insulating film. In enhancing the miniaturization of TSV compared
to the current status, the reduction of the opening width of the
through hole would have a greater influence on the processing
difficulty degree. Especially when the aspect ratio of the through
hole is 10 or more, the influence on the processing difficulty
degree becomes extremely large. In addition, since the shape of the
through hole is inversely tapered, it has also a great influence on
the difficulty degree in burying the metal. On the other hand, in a
case where the deposition amount of the insulating film with low
coverage is reduced in order to avoid such influence, the upper
insulating film might vanish before opening the bottom insulating
film, causing the etching to reach the silicon substrate.
[0011] Furthermore, in the technology described in Patent Document
2 described above, enhancing the miniaturization of the TSV as
compared with the current status might make the influence of the
misalignment occurring at the time of mask alignment at the time of
lithography noticeable, making it difficult to stably expose to the
bottom of the hole, causing a processing accuracy problem.
[0012] The present technology has been made in view of the above
problems and aims to improve the accuracy and stability when
removing the insulating film at the bottom of the TSV to allow the
through hole to open toward the connection target electrode.
Solutions to Problems
[0013] One aspect of the present technology is a semiconductor
device manufacturing method including: a first step of forming a
through hole in a semiconductor substrate by using anisotropic
etching performed from a first surface side of the semiconductor
substrate; a second step of forming a thin film being an insulating
film on an entire inner surface of the through hole; a third step
of forming a carbon-containing thin film using plasma deposition on
the first surface including an opening edge portion of the through
hole; a fourth step of engraving an inner bottom of the through
hole by using anisotropic plasma etching with the carbon-containing
thin film as a mask; a fifth step of removing the carbon-containing
thin film by ashing, and a sixth step of forming a
through-substrate electrode in the through hole.
[0014] Another aspect of the present technology is a semiconductor
device including: a semiconductor substrate; a wiring layer formed
to be stacked on a first surface of the semiconductor substrate; a
metal film constituting a portion of the wiring layer; a first
insulating film constituting a portion of the wiring layer and
provided adjacent to the semiconductor substrate side of the metal
film; a through-substrate electrode penetrating from the first
surface of the semiconductor substrate and from a second surface of
the semiconductor substrate opposite to the first surface, to the
metal film; a second insulating film interposed between the
through-substrate electrode and the semiconductor substrate; and a
third insulating film formed to adhere to a second surface-side end
portion of the second insulating film.
[0015] Note that the semiconductor device described above includes
various aspects such as being implemented in a state of being
incorporated in another device or being implemented together with
other methods. Furthermore, the present technology can also be
realized as a system including the semiconductor device. In
addition, the above-described method of manufacturing a
semiconductor device includes various aspects such as being
implemented as a part of another manufacturing method.
Effects of the Invention
[0016] According to the present technology, it is possible to
improve the accuracy and stability when removing the insulating
film at the bottom of the TSV to allow the through hole to open
toward the connection target electrode. Note that effects described
in the present description are provided for purposes of exemplary
illustration and are not intended to be limiting. Still other
additional effects may also be contemplated.
BRIEF DESCRIPTION OF DRAWINGS
[0017] FIG. 1 is a diagram schematically illustrating a cross
section of a main portion of a semiconductor device according to a
first embodiment.
[0018] FIG. 2A is a diagram schematically illustrating a method of
manufacturing a main portion of a semiconductor device according to
a first embodiment.
[0019] FIG. 2B is a diagram schematically illustrating a method of
manufacturing a main portion of a semiconductor device according to
the first embodiment.
[0020] FIG. 3A is a diagram schematically illustrating a method for
manufacturing a main portion of the semiconductor device according
to the first embodiment.
[0021] FIG. 3B is a diagram schematically illustrating a method for
manufacturing a main portion of the semiconductor device according
to the first embodiment.
[0022] FIG. 4A is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to a first embodiment.
[0023] FIG. 4B is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the first embodiment.
[0024] FIG. 5A is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the first embodiment.
[0025] FIG. 5B is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the first embodiment.
[0026] FIG. 6A is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the first embodiment.
[0027] FIG. 6B is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the first embodiment.
[0028] FIG. 7A is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the first embodiment.
[0029] FIG. 7B is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the first embodiment.
[0030] FIG. 8A is a diagram illustrating a shape of an additional
insulating film.
[0031] FIG. 8B is a diagram illustrating a shape of an additional
insulating film.
[0032] FIG. 9A is a diagram illustrating a shape of an additional
insulating film.
[0033] FIG. 9B is a diagram illustrating a shape of an additional
insulating film.
[0034] FIG. 10A is a diagram schematically illustrating a method of
manufacturing a main portion of a semiconductor device according to
a second embodiment.
[0035] FIG. 10B is a diagram schematically illustrating a method of
manufacturing a main portion of a semiconductor device according to
the second embodiment.
[0036] FIG. 11A is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the second embodiment.
[0037] FIG. 11B is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the second embodiment.
[0038] FIG. 12A is a diagram schematically illustrating a method of
manufacturing a main portion of a semiconductor device according to
a third embodiment.
[0039] FIG. 12B is a diagram schematically illustrating a method of
manufacturing a main portion of a semiconductor device according to
the third embodiment.
[0040] FIG. 13A is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the third embodiment.
[0041] FIG. 13B is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the third embodiment.
[0042] FIG. 14 is a diagram schematically illustrating a method of
manufacturing a main portion of a semiconductor device according to
a fourth embodiment.
[0043] FIG. 15 is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the fourth embodiment.
[0044] FIG. 16 is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the fourth embodiment.
[0045] FIG. 17 is a diagram schematically illustrating a method for
manufacturing a main portion of a semiconductor device according to
a fifth embodiment.
[0046] FIG. 18 is a diagram schematically illustrating a method for
manufacturing a main portion of the semiconductor device according
to the fifth embodiment.
[0047] FIG. 19 is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the fifth embodiment.
[0048] FIG. 20 is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the fifth embodiment.
[0049] FIG. 21 is a diagram schematically illustrating a method of
manufacturing a main portion of a semiconductor device according to
a sixth embodiment.
[0050] FIG. 22 is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the sixth embodiment.
[0051] FIG. 23 is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the sixth embodiment.
[0052] FIG. 24 is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the sixth embodiment.
[0053] FIG. 25 is a diagram schematically illustrating a method of
manufacturing a main portion of the semiconductor device according
to the sixth embodiment.
[0054] FIG. 26A is a diagram illustrating a difference between
first engraving and second engraving.
[0055] FIG. 26B is a diagram illustrating a difference between the
first engraving and the second engraving.
[0056] FIG. 27A is a diagram illustrating a difference between the
first engraving and the second engraving.
[0057] FIG. 27B is a diagram illustrating a difference between the
first engraving and the second engraving.
[0058] FIG. 28A is a diagram illustrating a difference between the
first engraving and the second engraving.
[0059] FIG. 28B is a diagram illustrating a difference between the
first engraving and the second engraving.
MODE FOR CARRYING OUT THE INVENTION
[0060] Hereinafter, the present technology will be described in the
following order.
[0061] (A) First embodiment:
[0062] (B) Second Embodiment:
[0063] (C) Third embodiment:
[0064] (D) Fourth Embodiment:
[0065] (E) Fifth embodiment:
[0066] (F) Sixth Embodiment:
(A) First Embodiment
[0067] FIG. 1 is a diagram schematically illustrating a cross
section of a main portion of a semiconductor device 100 according
to the present embodiment.
[0068] The semiconductor device 100 has a configuration in which a
wiring layer 20 including an insulating film, a metal film, a
transistor element, or the like, is provided on a semiconductor
substrate 10 such as a silicon substrate. FIG. 1 illustrates a
state in which the wiring layer 20 is stacked on the semiconductor
substrate 10 and thereafter the substrate is reversed, having the
wiring layer 20 positioned below the semiconductor substrate 10.
The thickness of the semiconductor substrate 10 is 1 .mu.m to 10
.mu.m, for example.
[0069] Note that in the following description of the surface of the
semiconductor substrate 10, the surface on the lower side in FIG. 1
(side on which the wiring layer 20 is stacked) will be denoted as a
front surface 10a, and the surface on the upper side in FIG. 1 as a
back surface 10b in some cases.
[0070] Furthermore, a side on the wiring layer 20 closer to the
semiconductor substrate 10 will be referred to as a lower side, and
a side away from the semiconductor substrate 10 as an upper
side.
[0071] The wiring layer 20 includes at least an insulating film 21
as a first insulating film and a metal film 22 (in FIG. 1, the
insulating film 21 and the metal film 22 alone are illustrated),
with the insulating film 21 being formed adjacent to a lower layer
side of the metal film 22. The metal film 22 constitutes an
electrode in the wiring layer 20.
[0072] A through hole 11 is formed in the semiconductor substrate
10. The through hole 11 has a form penetrating from the back
surface 10b as a first surface of the semiconductor substrate 10 to
the front surface 10a as a second surface on the opposite side
thereof and further penetrating a layer below the metal film 22 in
the wiring layer 20 to reach the metal film 22. The through hole 11
may partially include a hole formed in the metal film 22, and for
example, may include a recess formed by etching or the like on the
metal film 22 exposed at the bottom of the through hole 11.
[0073] On the semiconductor substrate 10, an insulating film 30 is
continuously formed over the entire surface along the inner surface
of the through hole 11 and the surface along the back surface 10b
(at least in the vicinity of opening periphery of the through hole
11 of the back surface 10b) of the semiconductor substrate 10. The
insulating film 30 is formed so as to cover the inner surface of
the through hole 11 and the back surface 10b of the semiconductor
substrate 10 with a substantially constant thickness and is
interposed between a through-substrate electrode 12 formed in the
through hole 11, and the semiconductor substrate 10. However, the
insulating film 21 and the metal film 22 constituting the side
surface and the bottom surface at the bottom of the through hole 11
of the semiconductor device 100 are not covered with the insulating
film 30. The insulating film 30 is formed by using a low dielectric
constant interlayer insulating film material (low-k material), and
is formed by using, for example, at least one of SiO.sub.2, SiN,
SiON, SiOC, or SiOCH.
[0074] The through hole 11 has a size inside the insulating film
30, being 50 nm to 500 nm in an opening width a, and an aspect
ratio (=b/a (b is the depth of the through hole 11)) of 10 or more.
Since the through hole 11 is formed through the semiconductor
substrate 10, the depth b of the through hole 11 is greater than
the thickness of the semiconductor substrate 10, for example, the
depth b is about 1 .mu.m.
[0075] At least a portion of the vicinity of the opening of the
through hole 11 of the insulating film 30 is constituted with an
additional insulating film 32 as a third insulating film formed by
a process different from the process for an insulating film main
body 31 as a second insulating film constituting substantially the
whole of the insulating film 30. In the insulating film 30
illustrated in FIG. 1, the additional insulating film 32 stacked on
the insulating film main body 31 forms a corner of the opening of
the through hole 11. The additional insulating film 32 may be
formed not merely on the corner of the opening of the through hole
11 but also on the insulating film main body 31. The additional
insulating film 32 is formed by using at least one of SiO.sub.2,
SiON, SiN, SiOC, or SiOCH.
[0076] In the insulating film 30, with the presence of the
additional insulating film 32, it is possible to improve uniformity
of the thickness of the insulating film 30 and the flatness of the
front surface (side not facing the semiconductor substrate 10) as
compared with the case of forming the insulating film 30 with the
insulating film main body 31 alone.
[0077] The through-substrate electrode 12 (TSV) is buried inside
the insulating film 30 formed along the inner surface of the
through hole 11. The through-substrate electrode 12 includes a
barrier metal film and a metal. The barrier metal film is formed by
using at least one of Ti, TiN, Ta, or TaN. The metal is formed by
using at least one of Cu, W, or Al.
[0078] The barrier metal film is a barrier film for preventing
diffusion of metal and is continuously formed over an entire
surface along the inner side of the insulating film 30 formed along
the inner surface of the through hole 11 and the entire surface
along the back surface 10b in the vicinity of the opening of the
through hole 11. That is, a barrier metal film is formed to be
interposed between the semiconductor substrate 10 and the
metal.
[0079] FIGS. 2A-7B are diagrams schematically illustrating a method
of manufacturing a main portion of the semiconductor device 100
described above.
[0080] The manufacturing method illustrated in these figures can be
applied to manufacturing methods such as "Via Last TSV" and "Via
after bondig", for example. "Via Last TSV" is a manufacturing
method of first forming the wiring layer 20 on the semiconductor
substrate 10 and thereafter forming a TSV to reach the wiring layer
20 from the back surface 10b side of the semiconductor substrate
10. The "Via after bondig" is a manufacturing method of first
laminating and integrating two or more semiconductor substrates
each having undergone wafer processing steps such as stacking of
wiring layers, and then forming TSV to penetrate a depth of one
semiconductor substrate or more from either the front or back side
of the integrated substrate so as to reach another semiconductor
substrate.
[0081] First, the semiconductor substrate 10 on which the wiring
layer 20 is stacked on the front surface 10a side of the
semiconductor substrate 10 is prepared, and then, the semiconductor
substrate 10 is mounted with its back surface 10b facing upwards,
on a wafer stage of a semiconductor exposure apparatus for
lithography (FIG. 2A).
[0082] Next, a resist 40 is formed on the back surface 10b of the
semiconductor substrate 10 by using a photolithography technology
FIG. 2B. The resist 40 has an opening 41 formed at a position where
the through hole 11 is to be formed.
[0083] Next, anisotropic plasma etching is performed on the resist
40 to form a through hole 11A (FIG. 3A). The through hole 11A
formed in this step has a depth to reach the insulating film 21
from the back surface 10b of the semiconductor substrate 10,
penetrating through the semiconductor substrate 10. Note that in
this step, the insulating film 21 may be partially engraved by
etching, and in this case, the through hole 11A is formed to a
depth to reach a midway depth of the insulating film 21.
[0084] Next, ashing is performed to remove the resist to form a
high coverage insulating film 30A (not illustrated) over the entire
surface along the inner surface (including the bottom surface) of
the through hole 11A and along the back surface 10b of the
semiconductor substrate 10 (at least vicinity of the opening of the
through hole 11 of the back surface 10b) (FIG. 3B). The insulating
film 30A is formed to cover the through hole 11 and the back
surface 10b of the semiconductor substrate 10, with a substantially
constant thickness. The insulating film 30A is formed by using at
least one of SiO.sub.2, SiN, or SiON.
[0085] The insulating film 30A is formed by an atomic layer
deposition (ALD) method, for example. Furthermore, the insulating
film 30A can be formed by a thermal oxidation method, a low
pressure chemical vapor deposition (LP-CVD) method, and a
plasma-enhanced chemical vapor deposition (PE-CVD) method, for
example.
[0086] The insulating film 30A formed by an ALD method is performed
so as to form a film with high coverage by using an
aminosilane-based precursor gas. The insulating film 30A formed by
the LP-CVD method is formed by using SiH.sub.4 or tetraethoxysilane
(TEOS) as a precursor gas for SiO.sub.2. In the case of SiN,
SiH.sub.4 or dichlorosilane (DCS) is used as a precursor gas. Note
that formation of the insulating film 30A needs to be done before
formation of the wiring layer 20 in a case where the LP-CVD method
is used, since the LP-CVD method is high-temperature processing. In
the formation of the insulating film 30A using the PE-CVD method,
it is preferable to use organic silane as a precursor gas rather
than SiH.sub.4. In the case of SiO.sub.2, it is possible to use
TEOS, methylsilane (1MS), dimethylsilane (2MS), trimethylsilane
(3MS), tetramethylsilane (4MS), or the like, as the precursor gas.
In the case of SiN, Trisilylamine (TSA) can be used as the
precursor gas. As a plasma source, PE-CVD by radial-line-slot
antenna (RLSA) system has been reported as a high coverage method
(Reference: Jpn. J. Appl. Phys. 48 (2009) 126001). SiOC and SiOCH
are formed by the ALD method or the PE-CVD method. In this case, as
the precursor gas, it is possible to use Bistrimethylsilylmethane
(BTMSM), methyltrimethoxysilane (MTMS),
tetramethylcyclotelrasiloxane (TMCTS), octamethylcyclotetrasiloxane
(OMCTS), and Decamethylcyclopentasiloxane (DMCPS) in addition to
the above 1MS, 2MS, 3MS, and 4MS. Note that in a case where the
insulating film 30A is formed as a process after forming the wiring
layer 20 as in the present embodiment, the insulating film 30A is
formed in processing performed at a low temperature of less than
400.degree. C.
[0087] Next, the bottom of the through hole 11A is engraved by
etching to achieve a depth at which the metal film 22 is exposed at
the bottom of the through hole 11A (FIGS. 4A to 5A and FIGS. 5B to
6B). As described below, the manufacturing method according to the
present embodiment uses a technique of suppressing occurrence of a
damage to the insulating film 30A other than the bottom of the
through hole 11A by this etching.
[0088] First, a carbon-containing thin film 50 for protecting the
insulating film 30A formed on the back surface 10b of the
semiconductor substrate 10 is formed (FIG. 4A). It is possible to
form the carbon-containing thin film 50 by using plasma having at
least one of fluorocarbons CF.sub.4, C.sub.4F.sub.8,
C.sub.4F.sub.6, etc.) or hydrofluorocarbons (CHF.sub.3,
CH.sub.2F.sub.2, CH.sub.3F, C.sub.5HF.sub.7, etc.) as the process
gas in a low ion energy state (for example, substrate bias of 100V
or less).
[0089] The carbon-containing thin film 50 is formed as a thin film
with low coverage. Therefore, as illustrated in FIG. 4A, while the
carbon-containing thin film 50 adheres to the back surface 10b side
of the semiconductor substrate 10 with a constant thickness or
more, the formation of the film onto the inner surface of the
through hole 11A is in such a degree that the film thickness
gradually decreases toward the deeper portion of the through hole
11A in the vicinity of the opening of the through hole 11A (in the
range of about several nm to several tens nm from the opening). The
carbon-containing thin film 50 is formed with a thickness d of, for
example, about 10 nm to 100 nm on the back surface 10b side of the
semiconductor substrate 10.
[0090] The carbon-containing thin film 50 is formed in a shape
protruding toward the center of the through hole 11A in the
vicinity of the opening of the through hole 11A, and the film
thickness gradually decreases toward the deeper portion of the
through hole 11A as described above, leading to an overhanging
shape of the carbon-containing thin film 50 in the vicinity of the
opening of the through hole 11A. A protrusion amount x toward the
center of the through hole 11A of the carbon-containing thin film
50 is about 3 nm in a case where the thickness d of the
carbon-containing thin film 50 is about 10 nm to 100 nm. Therefore,
when the through hole 11A has an opening width of about 50 nm on
the inner side of the insulating film 30A, an opening width in a
state where the carbon-containing thin film 50 has been formed
would be about 43 nm.
[0091] Next, the bottom of the through hole 11A is engraved by
anisotropic plasma etching using the carbon-containing thin film 50
as a mask (FIG. 4B). This anisotropic plasma etching uses plasma
having at least one of fluorocarbons (CF4, C4F8, C4F6, etc.) or
hydrofluorocarbons (CHF3, CH2F2, CH3F, C5HF7, etc.) as the process
gas in a high ion energy state (for example, substrate bias of 500V
or more). Note that the process gas may contain at least one of
hydrocarbon (CH4, C2H4, etc.), He, Ar, O2, CO, or N2. At this time,
the ratio of C in the gas chemistry is decreased compared with the
case of forming the carbon-containing thin film 50 to prevent
clogging of the opening of the through hole 11A due to excess
polymer. Execution time for the anisotropic etching is set to a
time that the carbon-containing thin film 50 formed on the back
surface 10b of the semiconductor substrate 10 would not vanish due
to the etching.
[0092] Next, the carbon-containing thin film 50 is removed by
ashing (FIG. 5A). This ashing is performed by plasma discharge
including, for example, O2, H2, or N2 to remove the
carbon-containing thin film 50 and remove C polymer adhered during
the anisotropic plasma etching. The processing time may be set to a
time period sufficient to remove the C polymer adhering to the
inside of the carbon-containing thin film 50 and the through hole
11A.
[0093] Thereafter, processing of plasma deposition of the
carbon-containing thin film 50 similar to FIGS. 4A to 5A, plasma
etching using the carbon-containing thin film 50 as a mask, ashing
of removing the carbon-containing thin film 50 and the C polymer
adhered during etching (FIG. 5B to FIG. 6B) is repeatedly performed
in a short cycle. In this manner, by repeating the plasma
deposition, the plasma etching, and the ashing in a short cycle, it
is possible to gradually engrave the bottom of the through hole
11A. This repetitive processing is performed until the bottom of
the through hole 11A reaches the metal film 22 to form the through
hole 11.
[0094] As described above, according to the present embodiment, the
processing of the plasma deposition, the plasma etching, and the
ashing is repeated in a short cycle to engrave the bottom of the
through hole 11A to form the through hole 11. This makes it
possible to eliminate the necessity of using a lithography
technology and possible to complete processing within a same plasma
apparatus.
[0095] Furthermore, since it is possible to reduce the thickness of
the carbon-containing thin film 50 formed by each of plasma
deposition processing, enabling decreasing the oppression of
opening width of the through hole 11A by the carbon-containing thin
film 50, leading to stabilized processing of the bottom of the
through hole 11A. Furthermore, the carbon-containing thin film 50
can be easily removed, making it possible to minimize the influence
on the subsequent process.
[0096] Note that there is no need to match processing times of
plasma deposition, plasma etching, and ashing in each of cycles,
and the processing time may be adjusted at each of cycles to adjust
the film thickness and degree of coverage. Furthermore, it is
allowable to perform a washing step of removing the processing
residues deposited on the bottom of the through hole 11A during or
after the repetitive processing described above.
[0097] Furthermore, there is a possibility that a damage occurring
in the above-described repetitive processing causes reduction of
the thickness of the insulating film 30 formed on the back surface
10b of the semiconductor substrate 10 (FIGS. 6B and 8A), scraping
of the opening corner of the through hole 11A of the insulating
film 30 formed on the back surface 10b of the semiconductor
substrate 10 (FIGS. 6A and 8B), or roughening of the surface (FIG.
9A) of the insulating film 30 formed on the back surface 10b of the
semiconductor substrate 10. In these cases, as illustrated in FIGS.
7A, 8A, 6A, 8B, and 9A, the low coverage additional insulating film
32 may be formed on the insulating film 30A as the insulating film
main body 31 so as to compensate for roughness, decrease in film
thickness, and rounding of the corner.
[0098] For example, SiO.sub.2, SiN, or SiON may be used as the
additional insulating film 32, and the film can be formed by a
PE-CVD method using SiH.sub.4, Si.sub.2H.sub.6, Si.sub.3H.sub.8, or
TEOS as a precursor gas and using CCP or ICP plasma as a plasma
source, for example. In the case of SiOC or SiOCH, the precursor
gas same as that for the insulating film 30 can be used. The
additional insulating film 32 is to be formed with a thickness (for
example, about 10 nm to 100 nm) to such an extent that the amount
of film formed on the bottom of the through hole 11 is extremely
small. Alternatively, the additional insulating film 32 may be SiON
or SiN.
[0099] Furthermore, the surface of the additional insulating film
32 may be flattened with chemical mechanical polishing (CMP) or the
like to eliminate irregularities on the surface or uniformize the
thickness of the insulating film 30.
[0100] In addition, as illustrated in FIG. 9B, there is a
possibility that the damage occurring in the above-described
repetitive processing causes formation of wave-like irregularities
in a direction along a depth direction on the inner surface of the
through hole 11A engraved by repetition of plasma deposition,
plasma etching, and ashing, in a short cycle. In a case where the
wave-like irregularities are left, a shape obtained by front/back
inverting the wave-like irregularities is going to be formed in the
structure of the bottom of the through-substrate electrode 12.
[0101] Thereafter, a barrier metal film and a metal are buried in
the through hole 11 (FIG. 7B). The barrier metal film is formed by
using Ti, TiN, Ta, or TaN by a sputtering method, the ALD method,
or the like. The metal is formed by using Cu, W, or Al, for
example, by an electrolytic plating method.
[0102] Main portions of the semiconductor device 100 according to
the present embodiment can be produced by using the manufacturing
method described above.
(B) Second Embodiment
[0103] Next, a semiconductor device 200 according to a second
embodiment and a method of manufacturing the same will be
described. While the semiconductor device 200 is different from the
above-described semiconductor device 100 in a manufacturing method,
its shape and structure are substantially the same as those of the
above-described semiconductor device 100, and thus, description of
the shape and structure will be omitted. In addition, the reference
signs of individual portions will also be denoted by the same
reference signs as those of the semiconductor device 100.
[0104] FIGS. 10A-11B are diagrams schematically illustrating a
method of manufacturing main portions of the semiconductor device
200 (the semiconductor device 200 itself is not illustrated). Note
that FIGS. 10A-11B illustrate steps different from the
manufacturing method of the semiconductor device 100 alone.
[0105] Steps before forming the through hole 11A and the step of
forming the electrode within the through hole 11 in the
semiconductor device 200 are similar to the steps in the method of
manufacturing the semiconductor device 100 (FIGS. 2A and 2B, FIGS.
3A and 3B, and FIG. 7B).
[0106] In the present embodiment, an additional insulating film 32A
is adhered to be formed beforehand on the insulating film 30A (FIG.
10A) in a period after formation of the through hole 11A and before
formation of the carbon-containing thin film 50 and engraving of
the bottom of the through hole 11A. That is, the low coverage
additional insulating film 32A formed in a separate process from
the insulating film 30A is formed so as to cover the insulating
film 30A at least in the vicinity of the opening of the through
hole 11A on the back surface 10b of the semiconductor substrate
10.
[0107] The additional insulating film 32A is formed by using at
least one of SiO.sub.2, SiON, or SiN. The manufacturing method is
similar to the method for forming the additional insulating film 32
described in the first embodiment. For example, the film of
SiO.sub.2 is formed by using the PE-CVD method that uses SiH.sub.4
or tetraethoxysilane (TEOS) as a precursor gas. The thickness of
the additional insulating film 32A may be at a level that would not
vanish during the etching or ashing performed at the engraving of
the bottom of the through hole 11A, and at a level that would not
damage the insulating film 30A (corresponding to the insulating
film main body 31) during the etching or ashing performed at the
engraving of the bottom of the through hole 11A.
[0108] The additional insulating film 32A is formed as a thin film
with low coverage. Accordingly, as illustrated in FIG. 10B, the
amount of adhesion formed on the back surface 10b of the
semiconductor substrate 10 is large whereas the amount of adhesion
to the inner surface of the through hole 11A is small. Therefore,
the film thickness gradually decreases toward the deeper portion of
the through hole 11A in the vicinity of the opening of the through
hole 11A (in the range of several nm to several tens nm from the
opening).
[0109] Next, the bottom of the through hole 11A is engraved by
etching to achieve a depth at which the bottom of the hole reaches
the metal film 22 (FIGS. 10B to 11B). The present embodiment also
uses a technique of etching that suppresses occurrence of damage to
the insulating film 30A other than the bottom of the through hole
11A.
[0110] First, a carbon-containing thin film 50 for protecting the
additional insulating film 32A (particularly the additional
insulating film 32A in the vicinity of the opening of the through
hole 11A) formed along the back surface 10b of the semiconductor
substrate 10 is formed (FIG. 10B). It is possible to form the
carbon-containing thin film 50 by using plasma having at least one
of fluorocarbons CF4, C4F8, C4F6, etc.) or hydrofluorocarbons
(CHF3, CH2F2, CH3F, C5HF7, etc.) as the process gas in a low ion
energy state (for example, substrate bias of 100V or less). Note
that the process gas may contain at least one of hydrocarbon (CH4,
C2H4, etc.), He, Ar, O2, CO, or N2.
[0111] The carbon-containing thin film 50 is formed as a thin film
with low coverage. Therefore, as illustrated in FIG. 10B, while the
carbon-containing thin film 50 adheres to be formed on the back
surface 10b side of the semiconductor substrate 10 with a constant
thickness or more, the adhesion formation of the film onto the
inner surface of the through hole 11A is in such a degree that the
film thickness gradually decreases toward the deeper portion of the
through hole 11A in the vicinity of the opening of the through hole
11A (in the range of about several nm to several tens nm from the
opening). The carbon-containing thin film 50 is formed with a
thickness of, for example, about 10 nm to 100 nm on the back
surface 10b side of the semiconductor substrate 10.
[0112] The carbon-containing thin film 50 is formed in a shape
protruding toward the center of the through hole 11A in the
vicinity of the opening of the through hole 11A, and the film
thickness gradually decreases toward the deeper portion of the
through hole 11A as described above, leading to an overhanging
shape of the carbon-containing thin film 50 in the vicinity of the
opening of the through hole 11A. The protrusion amount x toward the
center of the through hole 11A of the carbon-containing thin film
50 is about 3 nm in a case where the thickness d of the
carbon-containing thin film 50 is about 10 nm to 100 nm. In the
present embodiment, the additional insulating film 32A of low
coverage is adhered to be formed beforehand on the insulating film
30A, and the additional insulating film 32A also has a shape
protruding toward the center of the through hole 11A similarly to
the carbon-containing thin film 50. Accordingly, assuming that the
additional insulating film 32A has a protrusion amount of 3 nm, for
example, the through hole 11A having an opening width of about 50
nm in a state where the insulating film 30A is adhered is going to
have an opening with of about 37 nm in a state where the additional
insulating film 32A and the carbon-containing thin film 50 are
formed.
[0113] The bottom of the through hole 11A having such an opening
width is engraved by anisotropic plasma etching using the
carbon-containing thin film 50 as a mask (FIG. 11A). This
anisotropic plasma etching method is similar to the case of the
first embodiment described above.
[0114] Next, the carbon-containing thin film 50 and the C polymer
adhered during the anisotropic plasma etching are removed by ashing
(FIG. 11B). This ashing method is also similar to the case of the
above-described first embodiment.
[0115] Thereafter, similarly to the first embodiment, processing of
forming the carbon-containing thin film 50 by using plasma
deposition again, plasma etching using the carbon-containing thin
film 50 as a mask, and ashing of removing the carbon-containing
thin film 50 and the C polymer adhered during etching is repeatedly
performed in a short cycle so as to gradually engrave the bottom of
the through hole 11A until the bottom of the through hole 11A
reaches the metal film 22 to form the through hole 11.
[0116] Note that the additional insulating film 32A may be
partially or entirely removed by a method such as CMP before
burying the barrier metal and the metal, for example, or may be
used as it is.
[0117] With the method of manufacturing the semiconductor device
200 according to the present embodiment described above, there is
an advantage of being able to suppress the damage to the high
coverage insulating film 30A initially formed to an extremely low
level in addition to the advantages of the manufacturing method of
the semiconductor device 100 according to the above-described first
embodiment.
(C) Third Embodiment
[0118] Next, a semiconductor device 300 according to a third
embodiment and a method of manufacturing the same will be
described. While the semiconductor device 300 is different from the
above-described semiconductor device 100 in a manufacturing method,
its shape and structure are substantially the same as those of the
above-described semiconductor device 100, and thus, description of
the shape and structure will be omitted. In addition, the reference
signs of individual portions will also be denoted by the same
reference signs as those of the semiconductor device 100.
[0119] FIGS. 12A-13B are diagrams schematically illustrating a
method of manufacturing main portions of the semiconductor device
300 (the semiconductor device 300 itself is not illustrated). Note
that FIGS. 12A-13B illustrate steps different from the
manufacturing method of the semiconductor device 100 alone.
[0120] Steps before forming the through hole 11A and the step of
forming the electrode within the through hole 11 in the
semiconductor device 300 are similar to the steps in the method of
manufacturing the semiconductor device 100 (FIGS. 2A and 2B, FIGS.
3A and 3B, and FIG. 7B).
[0121] Furthermore, the present embodiment also performs
processing, after the formation of the through hole 11A, of
engraving the bottom of the through hole 11A by etching so as to
achieve the depth at which the bottom of the through hole 11A
reaches the metal film 22. The present embodiment also uses a
technique of etching that suppresses occurrence of damage to the
insulating film 30 other than the bottom of the through hole
11A.
[0122] However, this takes a configuration in which the step of
repeatedly performing processing of: plasma deposition of the
carbon-containing thin film 50 (FIG. 12A); the plasma etching using
the carbon-containing thin film 50 as a mask (FIG. 12B); and ashing
of removing the carbon-containing thin film 50 and the C polymer
adhered during the etching in a short period is different from the
above in that ashing is not performed every period but performed
just after the plasma deposition and the plasma etching are
repeated a plurality of times in a short cycle. That is, the
configuration is different from the first embodiment in that ashing
is not performed after the plasma deposition of the
carbon-containing thin film 50 (FIG. 12A) and after the plasma
etching using the carbon-containing thin film 50 as a mask (FIG.
12B), and that plasma deposition of stacking the carbon-containing
thin film 50 further on the remaining carbon-containing thin film
50 (FIG. 13A), and that plasma etching using the carbon-containing
thin film 50 remaining in the previous step and the
carbon-containing thin film 50 stacked thereon as a mask (d)) is
performed (FIG. 13B).
[0123] In this manner, the carbon-containing thin film 50 used as a
mask while being stacked is completely removed by ashing once at a
stage where the closure of the opening of the through hole 11A
becomes unacceptable, and then, the carbon-containing thin film 50
is newly deposited on the insulating film 30A. In this manner, the
bottom of the through hole 11A is gradually engraved while adding
and updating the carbon-containing thin film 50 as a mask for
plasma etching, the bottom of the through hole 11A reaches the
metal film 22 to form the through hole 11. The steps after this
processing are similar to the first embodiment described above.
[0124] With the manufacturing method according to the present
embodiment described above, there is no need to perform ashing
every time plasma etching is performed, making it possible to
improve efficiency of the manufacturing steps.
(D) Fourth Embodiment
[0125] Next, a semiconductor device 400 according to a fourth
embodiment and a method of manufacturing the same will be
described. After forming the wiring layer 420 on a semiconductor
substrate 410, the semiconductor device 400 forms, as an example, a
through-substrate electrode 412 penetrating through the wiring
layer 420 from a back surface 410b side of the semiconductor
substrate 410 to reach a metal electrode pad 460 provided near a
front surface 410a.
[0126] FIGS. 14 to 16 are diagrams schematically illustrating a
method of manufacturing main portions of the semiconductor device
400 according to the present embodiment.
[0127] As illustrated in FIG. 14, the method of manufacturing the
semiconductor device 400 includes: first forming a through hole
411A to penetrate the semiconductor substrate 410; and stacking an
insulating film 430A over the entire surface including the back
surface 410b of the semiconductor substrate 410 and an inner
surface of the through hole 411A. The semiconductor substrate 410,
the through hole 411A, and the insulating film 430A respectively
correspond to the semiconductor substrate 10, the through hole 11A,
and the insulating film 30A of the first embodiment.
[0128] Thereafter, similarly to the engraving of the bottom of the
through hole 11A in the first embodiment, the bottom of the through
hole 411A is engraved by processing of plasma deposition, plasma
etching, and ashing repeatedly performed in a short cycle, so as to
form a through hole 411 that penetrates through the wiring layer
420 to reach the metal electrode pad 460 (FIG. 15). The through
hole 411 is a configuration corresponding to the through hole 11 of
the first embodiment. Note that at engraving the wiring layer 420,
etching is performed while appropriately changing etching
conditions in accordance with individual film types of the stacked
film constituting the wiring layer 420.
[0129] For the through hole 411 thus formed, similarly to the
through hole 11 of the first embodiment, a through-substrate
electrode 412 (TSV) is formed by burying a barrier metal film and a
metal (not illustrated) into the through hole 411 (FIG. 16).
[0130] In this manner, with the manufacturing method of the
semiconductor device 400 according to the present embodiment, the
through hole 411 penetrating the wiring layer 420 can be formed by
the processing performed in the same plasma device, making it
possible to eliminate the necessity of using a lithography
technology in the processing of engraving the bottom of the through
hole 411A to penetrate the wiring layer 420. In addition,
processing of the bottom of the through hole 411A is stabilized.
Furthermore, since the carbon-containing thin film 50 is easy to
remove, the influence on the subsequent process can be
minimized.
(E) Fifth Embodiment
[0131] Next, a semiconductor device 500 according to a fifth
embodiment and a method of manufacturing the same will be
described. The semiconductor device 500 is formed by stacking
lamination of a plurality of elements including a wiring layer or
the like on a semiconductor substrate. This example includes: a
through-substrate electrode penetrating at least one element to be
connected to an electrode of another element; and a
through-substrate electrode penetrating solely the semiconductor
substrate of the same single element to be connected to an
electrode in the wiring layer within the same element.
[0132] FIGS. 17 to 20 are diagrams schematically illustrating a
method of manufacturing a main portion of the semiconductor device
500 according to the present embodiment.
[0133] As illustrated in FIGS. 17 to 20, the semiconductor device
500 is formed by adding processing to be described later to a
combination obtained by joining a first element X and a second
element Y by lamination. In the first element X, a wiring layer
520X is formed on a semiconductor substrate 510X. In the second
element Y, a wiring layer 520Y is formed on a semiconductor
substrate 510Y. The first element X and the second element Y are
joined with each other by lamination with the wiring layer 520X
side and the wiring layer 520Y side facing each other.
[0134] Hereinafter, a boundary between the first element X and the
second element Y will be referred to as a joining surface Z.
[0135] Accordingly, in the semiconductor device 500, the wiring
layer 520X is located at a position more toward the joining surface
Z than the semiconductor substrate 510X within the first element X,
while the wiring layer 520Y is located at a position more toward
the joining surface Z than the semiconductor substrate 510Y within
the second element Y.
[0136] As illustrated in FIG. 17, a through hole 511A and a through
hole 511B are formed (FIG. 17) as a first step of the method of
manufacturing the semiconductor device 500. The through hole 511A
is formed to penetrate through the semiconductor substrate 510X
from the back surface llb and having a depth not reaching the metal
film 522 as a connection target of the wiring layer 520X of the
first element X. The through hole 511B is formed to go beyond the
joining surface Z from the back surface 510b to reach the second
element Y and having a depth not reaching a metal electrode pad 560
formed in the wiring layer 520Y of the second element Y.
[0137] The through hole 511A and the through hole 511B are formed
by a method similar to the method for forming the through hole 11A
of the above-described first embodiment. For example, etching is
performed after resist formation on the opening of the forming
range of the through hole 511A and on the back surface 510b so as
to form the through hole 511A, and thereafter, the resist is
removed once. Next, while burying the resist in the formed through
hole 511A for protection, etching is performed after resist
formation on the opening of the forming range of the through hole
511B and on the back surface 510b so as to form the through hole
511B, and thereafter, the resist is removed. With this processing,
the through hole 511A and the through hole 511B are formed.
[0138] Next, an insulating film 530A with high coverage is formed
over the entire surface of the back surface 510b of the
semiconductor substrate 510X, the entire inner side surface of the
through hole 511A, and the entire inner surface of the through hole
511B (FIG. 18). The insulating film 530A is formed using the
similar material and manufacturing method as the insulating film
30A of the first embodiment.
[0139] Thereafter, the inner bottom surfaces of the through hole
511A and the through hole 511B are engraved by the method similar
to the method of engraving the inner bottom surface of the through
hole 11A of the first embodiment (FIG. 19). In the present
embodiment, the through hole 511B is engraved toward the metal film
522 constituting the wiring layer 520X of the first element X,
while the through hole 511A is engraved toward the metal electrode
pad 560 constituting the wiring layer 520Y of the second element Y.
Note that it is desirable that the engraving of the inner bottom
surface of the through hole 511A and the engraving of the inner
bottom surface of the through hole 511B be completed almost at the
same time. For example, at formation of the through hole 511A and
the through hole 511B, the depths of the through hole 511A and the
through hole 511B are formed so that the distance between the inner
bottom surface of the through hole 511B and the metal film 522 is
substantially equal to the distance between the inner bottom
surface of the through hole 511A and the metal electrode pad
560.
[0140] Subsequently, similarly to the through hole 11 of the first
embodiment, a barrier metal film (not illustrated) and a metal are
buried in the through hole 511A and the through hole 511B
respectively penetrating the metal electrode pad 560 and the metal
film 522 so as to form through-substrate electrodes 512A and 512B
(FIG. 20). The through-substrate electrode 512A and the
through-substrate electrode 512B are electrically connected to each
other by a metal film 570 formed along the back surface 510b of the
semiconductor substrate 510X.
[0141] As described above, with the manufacturing method of the
semiconductor device 500 according to the present embodiment, it is
possible to form the through hole 511A and the through hole 511B
penetrating the wiring layer 520 in parallel in processing
performed in the same plasma apparatus without using a lithography
technology. In addition, processing of the bottoms of the through
hole 511A and the through hole 511B is stabilized. Furthermore,
since the carbon-containing thin film 50 is easy to remove, the
influence on the subsequent process can be minimized.
(F) Sixth Embodiment
[0142] Next, a semiconductor device 600 according to a sixth
embodiment and a method of manufacturing the same will be
described. The semiconductor device 600 is formed by stacking
lamination of a plurality of elements including a wiring layer or
the like on a semiconductor substrate, and is an example in which a
through-substrate electrode penetrating through at least one
element to be connected to an electrode of another element is
connected to another electrode in the middle via side contact.
[0143] FIGS. 21 to 23 are diagrams schematically illustrating a
method of manufacturing a main portion of the semiconductor device
600 according to the present embodiment.
[0144] As illustrated in FIGS. 21 to 23, similarly to the
semiconductor device 500 according to the fifth embodiment, the
semiconductor device 600 is formed by adding processing to be
described later to a combination obtained by joining the first
element X and the second element Y by lamination.
[0145] First, a through hole 611A is formed in the semiconductor
device 600 (FIG. 21). The through hole 611A is formed to penetrate
through a semiconductor substrate 610X and having a depth not
reaching a metal film 622 as a connection target of a wiring layer
620X of the first element X. Note that the through hole 611A and
the metal film 622 overlap each other in plan view from the back
surface 610b side of the semiconductor substrate 610X, indicating
that there is a positional relationship such that the end portion
of the through hole 611A partially overlaps the end portion of the
metal film 622.
[0146] Next, an insulating film 630A with high coverage is stacked
over the entire surface including the back surface 610b of the
semiconductor substrate 610X and the inner surface of the through
hole 611A (FIG. 22). The insulating film 630A is formed by the
material and manufacturing method similar to those of the
insulating film 30A of the first embodiment.
[0147] Thereafter, the first engraving is performed on the inner
bottom surface of the through hole 611A (FIG. 23) by the method
substantially similar to the method of engraving the inner bottom
surface of the through hole 11A of the first embodiment. In the
present embodiment, the through hole 611A is engraved toward the
metal electrode pad 660 constituting a wiring layer 620Y of the
second element Y.
[0148] However, a first engraving hole 611A1 formed in first
engraving is formed by simply engraving a portion of the inner
bottom surface of the through hole 611A. Specifically, the first
engraving hole 611A1 is formed by engraving a range not interfering
with the metal film 622 in a plan view from the back surface 610b
side of the semiconductor substrate 610X. Therefore, the first
engraving hole 611A1 reaches the metal electrode pad 660 with no
exposure of the metal film 622 in the middle.
[0149] After completion of the formation of the first engraving
hole 611A1 in this manner, second engraving of engraving another
inner bottom surface of the through hole 611A is performed to form
a second engraving hole 611A2 having a depth to reach the metal
film 622 (FIG. 24). The second engraving can also be defined as
engraving to expand the first engraving hole 611A1 to a depth to
reach the metal film 622. This process exposes the metal film 622
in the middle of the second engraving hole 611A2 (the side surface
of the lower end portion and the corner portion of the bottom
surface).
[0150] For the through hole 611 thus formed, similarly to the
through hole 11 of the first embodiment, a through-substrate
electrode 612 is formed by burying a barrier metal film and a metal
(not illustrated) inside the insulating film 630 formed in the
through hole 611 (FIG. 25). The through-substrate electrode 612 is
connected to the metal electrode pad 660 at the inner end thereof
and comes in side contact with the metal film 622 on the way. This
makes it possible to form the through hole 611 that penetrates
through the wiring layer 620X and in which both the metal electrode
pad 660 and the metal film 622 are exposed in the hole by the
processing performed in the same plasma apparatus without using a
lithography technology. In addition, processing of the bottom of
the through hole 611A is stabilized. Furthermore, since the
carbon-containing thin film 50 is easy to remove, the influence on
the subsequent process can be minimized.
[0151] Here, a difference between the first engraving and the
second engraving will be described with reference to FIGS. 26A-28B.
Diagrams illustrated in FIGS. 26A-28B correspond to the engraving
method in which processing including: plasma deposition of the
carbon-containing thin film 50; the plasma etching using the
carbon-containing thin film 50 as a mask; and ashing of removing
the carbon-containing thin film 50 and the C polymer adhered during
etching is repeated in a short cycle, and these diagrams simply
illustrate the main points of the manufacturing method of the
present embodiment, similar to the first embodiment.
[0152] First, at the time of forming the first engraving hole
611A1, the low coverage carbon-containing thin film 50 is formed to
be thick so as to set the protrusion amount x which protrudes
toward the center of the through hole 611A near the opening of the
through hole 611A to a large amount (FIG. 26A). With this setting,
the opening size of the through hole 611A is narrowed to a size
substantially equal to the hole width of the first engraving hole
611A1.
[0153] When anisotropic plasma etching using the carbon-containing
thin film 50 as a mask is performed in this state, the inner bottom
surface of the through hole 611A is etched to be substantially the
same size as the opening of the narrowed through hole 611A (FIG.
26B). Thereafter, processing of plasma deposition, plasma etching,
and ashing is repeatedly performed in a short cycle so as to form
the first engraving hole 611A1 (FIG. 27A) to a depth to reach the
metal electrode pad 660 (not illustrated in FIGS. 26A-28B).
[0154] Next, at the time of forming the second engraving hole
611A2, the low coverage carbon-containing thin film 50 is formed to
be thin so as to set the protrusion amount x which protrudes toward
the center of the through hole 611A near the opening of the through
hole 611A to a small amount (FIG. 27B). With this setting, the
opening size of the through hole 611A is maintained to a size
substantially equal to the inner bottom surface of the through hole
611A.
[0155] When anisotropic plasma etching using the carbon-containing
thin film 50 as a mask is performed in this state, a range of
substantially the same size as the opening of the through hole
611A, that is, a substantially entire range of the inner bottom
surface of the through hole 611A is etched (FIG. 28A). Thereafter,
processing of the plasma deposition, plasma etching, and ashing is
repeated in a short cycle, so as to form the second engraving hole
611A2 to a depth to reach the metal film 622 (FIG. 28B).
[0156] In this manner, by adjusting the thickness of the
carbon-containing thin film 50 and adjusting the protrusion amount
x protruding toward the center of the through hole 611A near the
opening of the through hole 611A, it is possible to adjust the
width of the engraving hole to be formed on the inner bottom
surface of the through hole 611A. Therefore, in a case where there
is an object to be avoided in a layer being engraved, the
carbon-containing thin film 50 can be formed to be thick so that
the engraving hole is narrowed to form a small-width engraving
hole, making it easy to form the engraving hole while avoiding the
through-substrate electrode and the object in the through hole 611.
Furthermore, the metal film 622 to be connected to the
through-substrate electrode formed in the middle of the engraving
hole can be managed as follows. That is, while controlling to
narrow the hole width so as not to interfere with the metal film
622 during engraving toward the metal electrode pad 660 at a deep
position, and after completion of engraving into the metal
electrode pad 660, the second engraving is performed by controlling
the hole width to be wider so as to expose the metal film 622 at a
shallow position again. This method can improve processing
stability of the first engraving.
[0157] Note that the present technology is not limited to each of
the above-described embodiments and modifications and includes
configurations including mutual replacement or various
modifications of combinations of individual formations disclosed in
the above embodiments and modifications, configurations including
mutual replacement or various modifications of combinations of
individual formations disclosed in known technologies and the above
embodiments and modifications, or the like. Furthermore, the
technical scope of the present technology is not limited to the
above-described embodiments, but extends to matters described in
the claims and their equivalents.
[0158] Moreover, the present technology may also be configured as
below.
[0159] (1)
[0160] A semiconductor device manufacturing method including:
[0161] a first step of forming a through hole in a semiconductor
substrate by using anisotropic etching performed from a first
surface side of the semiconductor substrate;
[0162] a second step of forming a thin film being an insulating
film on an entire inner surface of the through hole;
[0163] a third step of forming a carbon-containing thin film using
plasma deposition on the first surface including an opening edge
portion of the through hole;
[0164] a fourth step of engraving an inner bottom of the through
hole by using anisotropic plasma etching with the carbon-containing
thin film as a mask;
[0165] a fifth step of removing the carbon-containing thin film by
ashing; and
[0166] a sixth step of forming a through-substrate electrode in the
through hole.
[0167] (2)
[0168] The semiconductor device manufacturing method according to
(1),
[0169] in which the carbon-containing thin film is formed by plasma
deposition using at least one of hydrocarbon, fluorocarbon, or
hydrofluorocarbon, as a process gas.
[0170] (3)
[0171] The semiconductor device manufacturing method according to
(1) or (2),
[0172] in which the anisotropic plasma etching in the fourth step
is performed by plasma etching using at least one of a fluorocarbon
or a hydrofluorocarbon, as a process gas.
[0173] (4)
[0174] The semiconductor device manufacturing method according to
any one of (1) to (3),
[0175] in which the carbon-containing thin film is formed in a
shape such that the vicinity of an opening of the through hole
protrudes toward a center of the through hole.
[0176] (5)
[0177] The semiconductor device manufacturing method according to
any one of (1) to (4),
[0178] in which an additional insulating film covering at least a
portion of the thin film being an insulating film formed in the
vicinity of the opening of the through hole is formed before the
sixth step.
[0179] (6)
[0180] A semiconductor device including:
[0181] a semiconductor substrate;
[0182] a wiring layer formed to be stacked on a first surface of
the semiconductor substrate;
[0183] a metal film constituting a portion of the wiring layer;
[0184] a first insulating film constituting a portion of the wiring
layer and provided adjacent to the semiconductor substrate side of
the metal film;
[0185] a through-substrate electrode penetrating from the first
surface of the semiconductor substrate and from a second surface of
the semiconductor substrate opposite to the first surface, to the
metal film;
[0186] a second insulating film interposed between the
through-substrate electrode and the semiconductor substrate; and a
third insulating film formed to adhere to a second surface-side end
portion of the second insulating film.
REFERENCE SIGNS LIST
[0187] 10 Semiconductor substrate 10a Front surface 10b Back
surface 11 Through hole 11A Through hole 12 Through-substrate
electrode 20 Wiring layer 21 Insulating film 22 Metal film 30
Insulating film 30A Insulating film 31 Insulating film main body 32
Additional insulating film 32A Additional insulating film
40 Resist
41 Opening
[0188] 50 Carbon-containing thin film 100 Semiconductor device 200
Semiconductor device 300 Semiconductor device 400 Semiconductor
device 410 Semiconductor substrate 410a Front surface 410b Back
surface 411 Through hole 411A Through hole 412 Through-substrate
electrode 420 Wiring layer 430 Insulating film 430A Insulating film
460 Metal electrode pad 500 Semiconductor device 510X Semiconductor
substrate 510Y Semiconductor substrate 510b Back surface 511A
Through hole 511B Through hole 512 Through-substrate electrode 520
Wiring layer 520X Wiring layer 520Y Wiring layer 522 Metal film 530
Insulating film 530A Insulating film 560 Metal electrode pad 600
Semiconductor device 610X Semiconductor substrate 610b Back surface
611 Through hole 611A Through hole 611A1 First engraving hole 611A2
Second engraving hole 612 Through-substrate electrode 620X Wiring
layer 620Y Wiring layer 622 Metal film 630 Insulating film 630A
Insulating film 660 Metal electrode pad X First element Y Second
element Z Joining surface
* * * * *