U.S. patent application number 16/734999 was filed with the patent office on 2021-07-08 for charge-cycle control for burst-mode dc-dc converters.
The applicant listed for this patent is NXP B.V.. Invention is credited to Hendrik Johannes Bergveld, Jitendra Prabhakar Harshey, Koteswararao Nannapaneni, Edevaldo Pereira da Silva Junior, Uday Kumar Sajja.
Application Number | 20210211055 16/734999 |
Document ID | / |
Family ID | 1000005666543 |
Filed Date | 2021-07-08 |
United States Patent
Application |
20210211055 |
Kind Code |
A1 |
Harshey; Jitendra Prabhakar ;
et al. |
July 8, 2021 |
CHARGE-CYCLE CONTROL FOR BURST-MODE DC-DC CONVERTERS
Abstract
A DC-DC converter operates in a burst mode having at least one
charge cycle with a charging phase followed by a discharging phase.
A charging phase is terminated when an inductor current flowing
through an inductance connected to the DC-DC converter reaches a
compensated peak-current threshold, wherein the compensated
peak-current threshold compensates for charging-phase loop delay. A
discharging phase is terminated when the inductor current reaches a
compensated valley-current threshold, wherein the compensated
valley-current threshold compensates for discharging-phase loop
delay.
Inventors: |
Harshey; Jitendra Prabhakar;
(Bangalore, IN) ; Bergveld; Hendrik Johannes;
(Eindhoven, NL) ; Pereira da Silva Junior; Edevaldo;
(Austin, TX) ; Nannapaneni; Koteswararao;
(Yelahanka, IN) ; Sajja; Uday Kumar; (Vetapalem,
IN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
NXP B.V. |
Eindhoven |
|
NL |
|
|
Family ID: |
1000005666543 |
Appl. No.: |
16/734999 |
Filed: |
January 6, 2020 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H02M 1/0009 20210501;
H02M 3/1588 20130101 |
International
Class: |
H02M 3/158 20060101
H02M003/158 |
Claims
1. Circuitry comprising a DC-DC converter, wherein: when an
inductance and a capacitance are connected to the DC-DC converter,
the DC-DC converter is configured to convert an input voltage into
an output voltage at an output port to drive a load connected to
the output port; the DC-DC converter is configured to operate in a
burst mode comprising at least one charge cycle comprising a
charging phase followed by a discharging phase; the charging phase
is terminated when an inductor current flowing through the
inductance reaches a compensated peak-current threshold, wherein
the compensated peak-current threshold compensates for
charging-phase loop delay; and the discharging phase is terminated
when the inductor current reaches a compensated valley-current
threshold, wherein the compensated valley-current threshold
compensates for discharging-phase loop delay.
2. The circuitry of claim 1, wherein: the circuitry is an
integrated circuit comprising the DC-DC converter; and the
inductance and the capacitance are external to the integrated
circuit.
3. The circuitry of claim 1, wherein the DC-DC converter comprises:
an output driver configured to selectively charge the inductance
and the capacitance; a control circuit configured to control the
output driver; comparator circuitry configured to generate feedback
signals to the control circuit for use in controlling the output
driver; and current generation circuitry configured to generate
reference currents for the comparator circuitry, wherein: the
current generation circuitry is configured to generate a
charging-phase reference current corresponding to the compensated
peak-current threshold, and the comparator circuitry is configured
to compare the charging-phase reference current to a current
corresponding to the inductor current to determine when to
terminate the charging phase of a burst-mode charge cycle; and the
current generation circuitry is configured to generate a
discharging-phase reference current corresponding to the
compensated valley-current threshold, and the comparator circuitry
is configured to compare the discharging-phase reference current to
a current corresponding to the inductor current to determine when
to terminate the discharging phase of a burst-mode charge
cycle.
4. The circuitry of claim 3, wherein the output driver comprises: a
high-side power switch connected between the input voltage and the
inductance; a low-side power switch connected between the
inductance and ground, wherein the high-side power switch, the
inductance, the low-side power switch, and a first input to an
over-current comparator of the comparator circuitry are
interconnected at a first node (e.g., 602); a high-side sense
switch connected between the input voltage and a second input to
the over-current comparator, wherein the charging-phase reference
current is applied to the second input to the over-current
comparator; and a low-side sense switch connected between the first
node and a first input to an under-current comparator of the
comparator circuitry, wherein (i) the discharging-phase reference
current is applied to the first input of the under-current
comparator and (ii) a second input to the under-current comparator
is connected to ground.
5. The circuitry of claim 3, wherein: the current generation
circuitry is configured to generate the charging-phase reference
current as a function of the charging-phase loop delay, the input
voltage, the output voltage, and the inductance; and the current
generation circuitry is configured to generate the
discharging-phase reference current as a function of the
discharging-phase loop delay, the output voltage, and the
inductance.
6. The circuitry of claim 3, wherein the current generation
circuitry comprises: a peak sense current source configured to
generate a peak sense current that is independent on the
charging-phase loop delay; a peak compensation current source
configured to generate a peak compensation current that is
dependent on the charging-phase loop delay, wherein the
charging-phase reference current is based on the peak sense current
and the peak compensation current; a valley sense current source
configured to generate a valley sense current that is independent
on the discharging-phase loop delay; and a valley compensation
current source configured to generate a valley compensation current
that is dependent on the discharging-phase loop delay, wherein the
discharging-phase reference current is based on the valley sense
current and the valley compensation current.
7. The circuitry of claim 1, wherein: the compensated peak-current
threshold is lower than the inductor current when the output driver
is turned off at the end of a charging phase; and the compensated
valley-current threshold is higher than the inductor current when
the output driver is turned on at the end of a discharging
phase.
8. A method for operating a DC-DC converter in burst mode, the
method comprising, for at least one burst-mode charge cycle:
charging an inductance and a capacitance connected to the DC-DC
converter until an inductor current flowing through the inductance
reaches a compensated peak-current threshold, wherein the
compensated peak-current threshold compensates for charging-phase
loop delay; and discharging the inductance until the inductor
current reaches a compensated valley-current threshold, wherein the
compensated valley-current threshold compensates for
discharging-phase loop delay.
9. The method of claim 8, wherein: the DC-DC converter is
implemented in an integrated circuit; and the inductance and the
capacitance are external to the integrated circuit.
10. The method of claim 8, wherein the DC-DC converter comprises:
an output driver that selectively charges the inductance and the
capacitance; a control circuit that controls the output driver;
comparator circuitry that generates feedback signals to the control
circuit for use in controlling the output driver; and current
generation circuitry that generates reference currents for the
comparator circuitry, wherein: the current generation circuitry
generates a charging-phase reference current corresponding to the
compensated peak-current threshold, and the comparator circuitry
compares the charging-phase reference current to a current
corresponding to the inductor current to determine when to
terminate the charging phase of a burst-mode charge cycle; and the
current generation circuitry generates a discharging-phase
reference current corresponding to the compensated valley-current
threshold, and the comparator circuitry compares the
discharging-phase reference current to a current corresponding to
the inductor current to determine when to terminate the discharging
phase of a burst-mode charge cycle.
11. The method of claim 10, wherein the output driver comprises: a
high-side power switch connected between the input voltage and the
inductance; a low-side power switch connected between the
inductance and ground, wherein the high-side power switch, the
inductance, the low-side power switch, and a first input to an
over-current comparator of the comparator circuitry are
interconnected at a first node (e.g., 602); a high-side sense
switch connected between the input voltage and a second input to
the over-current comparator, wherein the charging-phase reference
current is applied to the second input to the over-current
comparator; and a low-side sense switch connected between the first
node and a first input to an under-current comparator of the
comparator circuitry, wherein (i) the discharging-phase reference
current is applied to the first input of the under-current
comparator and (ii) a second input to the under-current comparator
is connected to ground.
12. The method of claim 10, wherein: the current generation
circuitry generates the charging-phase reference current as a
function of the charging-phase loop delay, the input voltage, the
output voltage, and the inductance; and the current generation
circuitry generates the discharging-phase reference current as a
function of the discharging-phase loop delay, the output voltage,
and the inductance.
13. The method of claim 10, wherein the current generation
circuitry comprises: a peak sense current source that generates a
peak sense current that is independent on the charging-phase loop
delay; a peak compensation current source that generates a peak
compensation current that is dependent on the charging-phase loop
delay, wherein the charging-phase reference current is based on the
peak sense current and the peak compensation current; a valley
sense current source that generates a valley sense current that is
independent on the discharging-phase loop delay; and a valley
compensation current source that generates a valley compensation
current that is dependent on the discharging-phase loop delay,
wherein the discharging-phase reference current is based on the
valley sense current and the valley compensation current.
14. The method of claim 8, wherein: the compensated peak-current
threshold is lower than the inductor current when the output driver
is turned off at the end of a charging phase; and the compensated
valley-current threshold is higher than the inductor current when
the output driver is turned on at the end of a discharging phase.
Description
TECHNICAL FIELD
[0001] The present disclosure is related to electronics and more
particularly to burst-mode direct-current-to-direct-current (DC-DC)
voltage converters and related voltage regulation for integrated
circuits and the like.
BACKGROUND
[0002] Many existing electronic products rely upon low-power or
battery-powered operation of one or more integrated circuits (ICs).
These integrated circuits can be used in a wide variety of
low-power or battery-operated applications including, for example,
mobile phones, smart watches, sensing applications, or other
low-power or battery-operated devices or applications. For many
low-power ICs, an external voltage (e.g., from a battery) is
converted to a lower voltage and regulated on-chip using a DC-DC
converter that operates using switched output drivers that control
power switches to control energy storage and release to and from
reactive components. The DC-DC converters are controlled to
maintain an output voltage that is provided to a load on the
integrated circuit irrespective of variations in the input voltage
and/or the load current.
[0003] Compared to a linear regulator, a DC-DC converter, whether
using capacitive or inductive reactive components, can achieve a
higher power efficiency, especially for large differences between
the higher input voltage and the lower output voltage. Compared to
using capacitive reactive components, using an inductive DC-DC
converter has the advantage that, for different input and/or
desired output voltages, the desired output voltage can be
maintained by changing the timing of how the power switches are
controlled, instead of changing the voltage conversion topology as
would be needed for a capacitive DC-DC converter. However,
maintaining a good power efficiency at low output power still
remains a challenge.
[0004] Applying burst-mode control has advantages because good
power efficiency can be maintained over a large load-current range.
In conventional burst-mode DC-DC converters, the voltage regulation
control is designed such that the DC-DC converter performs
switching of the power switches only after the output voltage drops
to a certain defined low-voltage threshold. This minimizes the
converter switching actions and increases efficiency, especially
for low output power since the DC-DC converter switches only when
really needed. For burst-mode DC-DC converters, a burst includes
one or more charge cycles that are performed by the DC-DC converter
for a short period of time after detecting that the output voltage
has reached a low-voltage threshold. During a burst, the DC-DC
converter typically operates in continuous-conduction mode (CCM)
with a controlled inductor current while ramping up the output
voltage from the defined low-voltage threshold to a defined
high-voltage threshold. Thus, the output voltage of such a
burst-mode DC-DC converter is controlled to be within a
voltage-regulation window defined by the low- and high-voltage
thresholds.
[0005] For burst-mode implementations, the switching activity of
the DC-DC converter (i.e., the frequency and/or duration of bursts)
increases with the load current. If the load current increases,
then the output capacitor for the DC-DC converter is drained
faster. As soon as the low-voltage threshold of the
voltage-regulation window is reached, a burst is started. For high
load conditions, bursts with longer durations are typically needed
because the load current subtracts from the inductor current during
each burst. The resulting lower current into the output capacitor
causes the output voltage to rise more slowly, thereby extending
the duration of each burst. Furthermore, since the load current
draws energy from the output capacitor between bursts, during high
load conditions, the bursts typically need to be more frequent.
Thus, both the burst frequency and the burst duration typically
depend on the load current. Further, within a burst, in order to
satisfy the output load, the inductor valley- and peak-current
thresholds that define the burst-mode charge cycles are selected to
ensure that the average inductor current is sufficient to achieve
the output current for the maximum allowable output load. In other
words, the average inductor current during the burst should be
higher than the maximum load current to ensure that the DC-DC
converter can continue operating in burst mode even for the maximum
allowable load current. As soon as the high-voltage threshold is
reached, the burst is ended by stopping the switching of the DC-DC
converter, such that the output load draws energy exclusively from
the output capacitor until the low-voltage threshold of the
voltage-regulation window is again reached and another burst is
started.
DESCRIPTION OF THE DRAWINGS
[0006] It is noted that the appended figures illustrate only
example embodiments and are, therefore, not to be considered as
limiting the scope of the present invention. Elements in the
figures are illustrated for simplicity and clarity and have not
necessarily been drawn to scale.
[0007] FIG. 1 is a schematic block diagram of an example embodiment
including an integrated circuit (IC) having a DC-DC converter
controlled by control signals asserted by a controller, external to
the DC-DC converter, but on the same IC;
[0008] FIG. 2 is a schematic diagram of a portion of the example
embodiment of FIG. 1 showing further circuit details for the DC-DC
converter;
[0009] FIG. 3 provides an example timing diagram for the DC-DC
converter 106 of FIGS. 1 and 2 during ideal burst-mode
operations;
[0010] FIG. 4 is a graphical representation of the inductor current
I.sub.L flowing through the inductance of FIGS. 1 and 2 as a
function of time for two of the intermediate charge cycles during a
burst of FIG. 3;
[0011] FIG. 5 is a graphical representation of the inductor current
I.sub.L flowing through the inductance of FIGS. 1 and 2 as a
function of time for two of the intermediate charge cycles during a
burst of FIG. 3 that illustrates the impact of the charging-phase
and discharging-phase loop delays in terminating the charging and
discharging phases of the charge cycles due to the processing
delays in real-world implementations of the DC-DC converter;
[0012] FIG. 6 is a schematic block diagram of a portion of the
DC-DC converter of FIGS. 1 and 2 that is involved in detecting when
to terminate an existing charging phase of a burst-mode charge
cycle;
[0013] FIG. 7 is a schematic block diagram of a portion of the
DC-DC converter of FIGS. 1 and 2 that is involved in detecting when
to terminate an existing discharging phase of a burst-mode charge
cycle;
[0014] FIG. 8 is an example timing diagram showing the four drive
signals of FIGS. 6 and 7 for two bursts separated by an off-burst
period;
[0015] FIG. 9 is a schematic block diagram of one embodiment of the
peak sense current source I.sub.pk_sns of FIG. 6;
[0016] FIG. 10 is a schematic block diagram of one embodiment of
the peak compensation current source I.sub.pk_comp of FIG. 6;
[0017] FIG. 11 is a schematic block diagram of one embodiment of
the valley sense current source I.sub.valley_sns of FIG. 7;
[0018] FIG. 12 is a schematic block diagram of one embodiment of
the valley compensation current source I.sub.valley_comp of FIG.
7;
[0019] FIG. 13 is a schematic block diagram of a portion of an
embodiment of the DC-DC converter of FIGS. 1 and 2 that can be
selectively configured to operate in either a normal-power mode or
a low-power mode; and
[0020] FIG. 14 is a timing diagram of the operations of the DC-DC
converter 106 of FIG. 13 for both the normal-power mode and the
low-power mode.
DETAILED DESCRIPTION
[0021] Embodiments are disclosed that provide techniques for
controlling charge cycles for burst-mode DC-DC converters.
[0022] The techniques described herein can be used with any
suitable type of burst-mode DC-DC converter such as (without
limitation) a buck converter, a boost converter, or a buck-boost
converter. Further, it is noted that the disclosed techniques can
also be used with other types of DC-DC converters, including hybrid
power converters containing both inductors and capacitors, such as
multi-level DC-DC converters, where charge cycles are used to raise
an output voltage to a high-voltage threshold after detecting that
the output fell to a low-voltage threshold. Other variations and
advantages can also be implemented while taking advantage of the
techniques described herein.
[0023] FIG. 1 is a schematic block diagram of an example embodiment
100 including an integrated circuit (IC) 102 having a DC-DC
converter 106 controlled by control signals 105 asserted by a
controller 104, external to the DC-DC converter 106, but on the
same IC 102. The DC-DC converter 106 is powered by and coupled
between an external supply voltage (V.sub.in) 112 and ground 111.
The DC-DC converter 106 operates to charge an output capacitance
(C) 118 through an inductance (L) 116 to provide an output voltage
(V.sub.out) 114 to a load 108.
[0024] In the example embodiment 100, the controller 104 and the
load 108 are implemented within the IC 102, and the inductance 116
and the capacitance 118 are implemented off chip. In alternative
embodiments, (i) the controller 104 and/or the load 108 may be
external to the IC 102 and/or (ii) the inductance 116 and/or the
capacitance 118 may be implemented within the IC 102. It is further
noted that the inductance 116 can be provided by one or more
inductors, and the capacitance 118 can be provided by one or more
capacitors. Different and/or additional circuits (not shown in FIG.
1) can also be included within the IC 102.
[0025] FIG. 2 is a schematic diagram of a portion of the example
embodiment 100 of FIG. 1 showing further circuit details for the
DC-DC converter 106. As shown in FIG. 2, the DC-DC converter 106
includes a control circuit 202 and an output driver 204. The
external voltage supply 112 is coupled to supply the input voltage
V.sub.in to power the control circuit 202 and the output driver
204. The control circuit 202 receives control signals 105 from the
controller 104 of FIG. 1 and outputs drive signals 226 to the
output driver 204.
[0026] The control circuit 202 can be implemented as a dedicated
logic circuit, dedicated controller, or other hardware digital
solution that implements the control actions and functions
described herein. The control circuit 202 can also be implemented
as a microcontroller, a processor, a programmable logic device, or
other programmable circuit that executes program instructions
stored in a non-volatile data storage device to carry out the
control actions and functions described herein.
[0027] As described further below, the drive signals 226 are
capable of turning on and off high-side and low-side power switches
(e.g., SW.sub.H and SW.sub.L in FIGS. 6, 7, and 13) in the output
driver 204. When the high-side power switch SW.sub.H is turned on
and the low-side power switch SW.sub.L is turned off, the output
driver 204 connects the supply voltage 112 to charge the
capacitance 118 through the inductance 116 to deliver the output
voltage 114 to the load 108. When the high-side power switch
SW.sub.H is turned off and the low-side power switch SW.sub.L is
turned on, the output driver 204 disconnects the supply voltage 112
such that energy stored in the inductance 116 and the capacitance
118 is used to deliver the output voltage 114 to the load 108.
[0028] A burst of the DC-DC converter burst-mode operation consists
of multiple charge cycles of reciprocally switching on and off the
high-side and low-side power switches SW.sub.H and SW.sub.L to
charge the capacitance 118 until the output voltage V.sub.out
reaches a specified high-voltage threshold V.sub.H. Each charge
cycle during a burst consists of (i) a charging phase during which
the high-side power switch SW.sub.H in the output driver 204 is
turned on and the low-side power switch SW.sub.L is turned off and
(ii) a discharging phase during which the high-side power switch
SW.sub.H is turned off and the low-side power switch SW.sub.L is
turned on. The current I.sub.L flowing through the inductance 116
increases during each charging phase and decreases during each
discharging phase. As long as the inductor current I.sub.L is
greater than the load current, the output voltage V.sub.out at the
capacitance 118 will increase. When the DC-DC converter 106 is
designed and operating properly, the voltage increase during the
charging phase of a charge cycle and the beginning of the
charge-cycle's discharging phase is greater than any voltage
decrease during the end of the charge-cycle's discharging phase,
such that the output voltage V.sub.out has a net increase with each
charge cycle.
[0029] A burst is initiated when the output voltage V.sub.out drops
to a low-voltage threshold V.sub.L, and a burst is terminated when
the output voltage V.sub.out reaches the high-voltage threshold
V.sub.H.
[0030] During a burst, which typically consists of a number of
charge cycles, each charging phase of a current charge cycle is
terminated and the discharging phase is initiated when the inductor
current I.sub.L reaches a specified peak-current threshold
I.sub.peak. Analogously, each discharging phase is terminated and
the charging phase of the next charge cycle is initiated when the
inductor current I.sub.L reaches a specified valley-current
threshold I.sub.valley. The peak and valley currents I.sub.peak and
I.sub.valley are selected such that the average inductor current
I.sub.ave (i.e., (I.sub.peak+I.sub.valley)/2) is greater than the
inductor current level needed to satisfy the maximum load current.
In that case, there will be a net increase in the energy stored in
the capacitance 118 with every charge cycle of the DC-DC converter
106, such that the output voltage V.sub.out will eventually rise to
the high-voltage threshold V.sub.H at which point the high-side
power switch SW.sub.H in the output driver 204 is turned off. The
low-side power switch SW.sub.L in the output driver 204 remains on
until the inductor current I.sub.L ramps down to zero, at which
point the low-side switch SW.sub.L is turned off, thereby
terminating the burst. Both power switches SW.sub.H and SW.sub.L
will remain off, and the inductor current I.sub.L will remain at
zero until the output voltage V.sub.out falls to the low-voltage
threshold V.sub.L and another burst is initiated.
[0031] The control circuit 202 receives certain monitor signals to
facilitate internal control of the DC-DC converter 106. In
particular, as shown in FIG. 2, the control circuit 202 receives an
over-voltage (OV) detection signal 208, an under-voltage (UV)
detection signal 212, a zero-current detection (ZCD) signal 216, an
under-current (UC) detection signal 220, and an over-current (OC)
detection signal 224. In alternative embodiments, different and/or
additional monitor signals can be provided depending upon
operational functions desired for the DC-DC converter 106.
[0032] The OV detection signal 208 is used to detect when the
output voltage (V.sub.out) 114 rises above the high-voltage
threshold V.sub.H. For the example detector circuit shown in FIG.
2, a high-voltage comparator 206 is coupled to compare the output
voltage 114 to the high-voltage threshold V.sub.H (207) to generate
the OV detection signal 208 such that the OV detection signal 208
is high when the output voltage V.sub.out is greater than the
high-voltage threshold V.sub.H and otherwise the OV detection
signal 208 is low. In some implementations, a voltage divider (not
shown) can be used to divide the output voltage down to a lower
voltage level for the comparison.
[0033] The UV detection signal 212 is used to detect when the
output voltage (V.sub.out) 114 falls below the low-voltage
threshold V.sub.L. For the example detector circuit shown in FIG.
2, a low-voltage comparator 210 is coupled to compare the output
voltage 114 to the low-voltage threshold V.sub.L (211) to generate
the UV detection signal 212 such that the UV detection signal 212
is high when the output voltage V.sub.out is less than the
low-voltage threshold V.sub.L and otherwise the UV detection signal
212 is low. In some implementations, the same voltage divider is
used to divide down the output voltage for the comparison.
[0034] The ZCD detection signal 216 is used to indicate when the
inductor current I.sub.L has fallen back to zero at the end of a
burst. For the example detector circuit shown in FIG. 2, a ZCD
current comparator 214 is coupled to compare (i) a scaled version
205a of a low-side sensed current from the output driver connection
path to ground 111 to (ii) a ZCD reference current 215 (i.e., zero
current) to generate the ZCD detection signal 216 such that the ZCD
detection signal 216 is high when the scaled low-side sensed
current 205a is sufficiently close to the ZCD reference current
215, and otherwise the ZCD detection signal 216 is low.
[0035] The UC detection signal 220 is used to detect when the
scaled low-side sensed current 205a for the output driver 204 falls
below a scaled version of the valley current I.sub.valley. For the
example detector circuit shown in FIG. 2, a low-current comparator
218 is coupled to compare the scaled low-side sensed current 205a
to the scaled valley current I.sub.valley (219) to generate the UC
detection signal 220 such that the UC detection signal 220 is high
when the scaled low-side sensed current 205a is below the scaled
valley current I.sub.valley and otherwise the UC detection signal
220 low.
[0036] The OC detection signal 224 is used to detect when a scaled
version 205b of a high-side sensed current from the output driver
connection path from the voltage supply 112 rises above a scaled
version of the peak current I.sub.peak. For the example detector
circuit shown in FIG. 2, a high-current comparator 222 is coupled
to compare the scaled high-side sensed current 205b to the scaled
peak current I.sub.peak (223) to generate the OC detection signal
224 such that the OC detection signal 224 is high when the scaled
high-side sensed current 205b is above the scaled peak current
I.sub.peak and otherwise the OC detection signal 224 is low.
[0037] As shown in FIG. 2, the DC-DC converter 106 has a current
(I) block 230 that generates the zero current reference current
215, the scaled valley current I.sub.valley 219, and the scaled
peak current I.sub.peak 223 based on control signals 228 received
from the control circuit 202.
[0038] Note that, in alternative implementations, the UC detection
signal 220 can also be used as the ZCD detection signal 216 by
changing the scaled valley current I.sub.valley (219) to zero when
the OV detection signal 218 goes high. When the UV detection signal
212 goes high, the scaled valley current I.sub.valley (219) is
restored to its non-zero value. In such implementations, the ZCD
current comparator 214 and its inputs and outputs are omitted from
FIG. 2.
[0039] FIG. 3 provides an example timing diagram 300 for the DC-DC
converter 106 during ideal burst-mode operations. FIG. 3 shows the
inductor current I.sub.L through the inductance 116, the output
voltage (V.sub.out) 114, and a burst-active signal 308 generated by
the control circuit 202 and which is driven high at the beginning
of each burst and low at the end of each burst. Note that the
burst-active signal may be considered to be part of the signals
labeled 105 in FIGS. 1 and 2. During burst-mode operations, the
DC-DC converter 106 maintains the output voltage 114 within a
voltage-regulation window 320 between the high-voltage threshold
(V.sub.H) 207 and the low-voltage threshold (V.sub.L) 211. This
control is provided through burst events 302 for the DC-DC
converter 106. Note that, in this particular implementation, the
valley current I.sub.valley is negative. In other implementations,
the valley current I.sub.valley may be zero or positive.
[0040] The DC-DC converter 106 ideally starts a new burst 302
through normal internal control as soon as the output voltage 114
reaches the low-voltage threshold (V.sub.L) 211, at which time, the
control circuit 202 asserts the burst-active signal 308. During
each burst 302, the high-side and low-side power switches SW.sub.H
and SW.sub.L in the output driver 204 are reciprocally cycled on
and off multiple times where the inductor current I.sub.L is kept
between the valley-current threshold (I.sub.alley) (i.e., the UC
reference current 219 of FIG. 2) and the peak-current threshold
(I.sub.peak) (i.e., the OC reference current 223 of FIG. 2). During
each burst 302, the output voltage 114 rises from the low-voltage
threshold (V.sub.L) (i.e., the UV reference voltage 211 of FIG. 2)
to the high-voltage threshold (V.sub.H) (i.e., the OV reference
voltage 207 of FIG. 2). In this ideal operation, as soon as the OV
comparator 206 detects that the output voltage 114 has reached the
high-voltage threshold (V.sub.H) 207, the control circuit 202 turns
off the high-side power switch SW.sub.H and, when the inductor
current I.sub.L reaches zero, the burst 302 is terminated by the
control circuit 202 turning off the low-side power switch SW.sub.L
and driving the burst-active signal 308 low.
[0041] It is further noted that assertion of a burst-done signal
could also be used by the control circuit 202 to indicate to
controller 104 that the burst has completed, and this burst-done
signal can be in addition to or instead of the burst-active signal
308. Other variations and additional, different, or fewer control
signals can also be used while still taking advantage of the
techniques described herein.
[0042] It is noted that FIG. 3 is described with signals being
asserted with high logic levels and de-asserted with low logic
levels. If desired, one or more of these signals could be
implemented such that assertion is a low logic level and
de-assertion is a high logic level. Further, the control signals
could be adjusted to indicate an opposite action. For example, as
indicated above, assertion of a burst-done signal could be used
instead of de-assertion of a burst-active signal, and vice versa.
Additional or different variations could also be implemented while
still taking advantage of the techniques described herein.
[0043] FIG. 4 is a graphical representation of the inductor current
I.sub.L flowing through inductance 116 as a function of time for
two of the intermediate charge cycles during a burst 302 of FIG. 3,
where each charge cycle has a charging phase during which the
inductor current I.sub.L rises followed by a discharging phase
during which the inductor current I.sub.L falls. (Note that the
initial charge cycle of each burst starts with the inductor current
I.sub.L at 0, which will typically be different from the valley
current valley, and that the final charge cycle of each burst ends
with the inductor current I.sub.L at 0.) At the beginning of the
charging phase of an intermediate charge cycle, the low-side power
switch SW.sub.L in the output driver 204 of FIG. 2 is turned off
followed soon after by the high-side power switch SW.sub.H being
turned on, such that the inductor current I.sub.L rises from the
valley current valley to the peak current I.sub.peak, at which
point the high-side power switch SW.sub.H is turned off followed
soon after by the low-side power switch SW.sub.L being turned on to
initiate the discharging phase of the charge cycle, during which
the inductor current I.sub.L falls from the peak current I.sub.peak
to the valley current valley, at which time the next charge cycle
begins by again turning off the low-side power switch SW.sub.L and
then turning on the high-side power switch SW.sub.H.
[0044] In FIG. 4, t.sub.on is the duration of the charging phase of
an intermediate charge cycle, and t.sub.off is the duration of the
discharging phase, such that the total duration T.sub.sw of each
intermediate charge cycle is (t.sub.on+t.sub.off). When the
durations t.sub.on and t.sub.off of the charging and discharging
phases are constant from charge cycle to charge cycle within a
burst such that the total charge-cycle duration T.sub.sw remains
constant during the burst, the frequency F.sub.sw of the charge
cycles (i.e., 1/T.sub.sw) also remains constant during the
burst.
[0045] As indicated in FIG. 4, the rate of change of the inductor
current I.sub.L during the charging phase of each charge cycle
is
( V in - V out L ) , ##EQU00001##
and the rate of change of the inductor current I.sub.L during the
discharging phase of each charge cycle is
( - V out L ) , ##EQU00002##
where V.sub.in is the input voltage 112, V.sub.out is the output
voltage 114, and L is the inductance 116, such that the valley and
peak currents I.sub.valley and I.sub.peak are related according to
Equations (1) and (2) as follows:
I peak = I valley + t on V in - V out L and ( 1 ) I valley = I peak
- t off V out L . ( 2 ) ##EQU00003##
Note that these equations are valid for buck converters, like the
buck converter 106 of FIGS. 1 and 2. Those skilled in the art will
understand how to derive corresponding equations for other types of
DC-DC converters such as boost and buck-boost converters. In any
case, for all such DC-DC converters, the inductor current I.sub.L
rises and falls in an analogous manner during the charging and
discharging phases of burst-mode charging cycles, albeit at
different rates.
[0046] A particular instance of the DC-DC converter 106 of FIGS. 1
and 2 is designed to operate for specified ranges of input voltage
levels V.sub.in, output voltage levels V.sub.out, and load current
levels. For a specific application of the DC-DC converter 106 in
which the expected input voltage V.sub.in, the desired output
voltage V.sub.out, and the maximum load current, are known, the
value for the inductance L (116 in FIGS. 1 and 2) is selected to
achieve acceptable levels of efficiency and current ripple, and the
value for the output capacitance C (118 in FIGS. 1 and 2) is
selected to achieve an acceptable level of voltage ripple. In
addition, the values for the inductor valley and peak currents
I.sub.valley and I.sub.peak are selected to achieve a desired
charge-cycle frequency F.sub.sw and to ensure that the average
inductor current I.sub.ave (i.e., (I.sub.valley+I.sub.peak)/2) is
sufficient to satisfy the maximum load current. In that case, the
DC-DC converter 106 is configured to operate for the specified
values of the input voltage V.sub.in, the output voltage V.sub.out,
and the inductance L such that the durations t.sub.on, t.sub.off,
and T.sub.sw and the frequency F.sub.sw are all known. Note that
the charge-cycle frequency F.sub.sw is typically selected to avoid
electromagnetic interference (EMI) associated with certain specific
frequency ranges.
[0047] According to Equations (1) and (2), for constant values of
the output voltage V.sub.out, the inductance L, and the valley- and
peak-current thresholds I.sub.valley and I.sub.peak, a higher value
for the input voltage V.sub.in decreases the duration t.sub.on of
the charging phases, while maintaining the same value for the
duration t.sub.off of the discharging phases, resulting in a higher
charge-cycle frequency F.sub.sw. Furthermore, for constant values
of the input voltage V.sub.in, the inductance L, and the valley-
and peak-current thresholds valley I.sub.valley and I.sub.peak, a
higher value for the output voltage V.sub.out increases the
duration t.sub.on of the charging phase, while decreasing the
duration t.sub.off of the discharging phase, which might or might
not affect the charge-cycle frequency F.sub.sw. In addition, for
constant values of the input voltage V.sub.in, the output voltage
V.sub.out, and the valley- and peak-current thresholds I.sub.valley
and I.sub.peak, a higher value for the inductance L increases both
the durations t.sub.on and t.sub.off, resulting in a lower
charge-cycle frequency F.sub.sw.
Loop-Delay Compensation
[0048] If the DC-DC converter 106 were able to react
instantaneously, then, for given values for the input voltage
V.sub.in, the output voltage V.sub.out, and the inductance L,
Equations (1) and (2) could be used to determine values for the
valley- and peak-current thresholds valley and I.sub.peak that
would achieve a desired switch-cycle frequency F.sub.sw.
[0049] In the real world, however, the DC-DC converter 106 is not
able to react instantaneously. Instead, for example, when, during
the charging phase of a burst-mode charge cycle, the rising
inductor current I.sub.L reaches the peak-current threshold
I.sub.peak, it takes non-zero amounts of time (i) for the
high-current comparator 222 of FIG. 2 to drive the OC detection
signal 224 high, (ii) for the control circuit 202 to react to the
assertion of the OC detection signal 224 to assert the drive
signals 226, and (iii) for the output driver 204 to react to the
assertion of the drive signals 226 to turn the high-side power
switch SW.sub.H off and then the low-side power switch SW.sub.L on.
In the meantime, during this overall processing delay, referred to
herein as the charging-phase loop delay T.sub.peak_dly, the end of
the charging phase and the corresponding beginning of the next
discharging phase are delayed, such that the inductor current
I.sub.L continues to rise beyond the peak-current threshold
I.sub.peak.
[0050] Similarly, when, during the discharging phase of a
burst-mode charge cycle, the falling inductor current I.sub.L
reaches the valley-current threshold I.sub.valley, it takes
non-zero amounts of time (i) for the low-current comparator 218 of
FIG. 2 to drive the UC detection signal 220 high, (ii) for the
control circuit 202 to react to the assertion of the UC detection
signal 220 to de-assert the drive signals 226, and (iii) for the
output driver 204 to react to the de-assertion of the drive signals
226 to turn the low-side power switch SW.sub.L off and then the
high-side power switch SW.sub.H on. In the meantime, during this
discharging-phase loop delay T.sub.valley_dly, the end of the
discharging phase and the corresponding beginning of the next
charging phase are delayed, such that the inductor current I.sub.L
continues to fall below the valley-current threshold
I.sub.valley.
[0051] FIG. 5 is a graphical representation of the inductor current
I.sub.L flowing through inductance 116 as a function of time for
two of the intermediate charge cycles during a burst 302 of FIG. 3
that illustrates the impact of the charging-phase and
discharging-phase loop delays in terminating the charging and
discharging phases of the charge cycles due to the processing
delays in real-world implementations of the DC-DC converter 106. In
FIC. C, the solid curve represents the inductor current I.sub.L for
instantaneous reaction by an ideal implementation of the DC-DC
converter 106, while the dotted curve represents the inductor
current I.sub.L for the delayed reaction by a real-world
implementation of the DC-DC converter 106.
[0052] As shown in FIG. 5, in the real world, due to the
charging-phase loop delay T.sub.peak_dly, the inductor current
I.sub.L continues to rise after reaching the peak-current threshold
I.sub.peak until the high-side and low-side power switches SW.sub.H
and SW.sub.L can be switched, by which time the inductor current
I.sub.L has risen to I.sub.peak_dly. Similarly, due to the
discharging-phase loop delay T.sub.valley_dly, the inductor current
I.sub.L continues to fall after reaching the valley-current
threshold I.sub.valley until the high-side and low-side power
switches can be switched, by which time the inductor current
I.sub.L has fallen to I.sub.valley_dly. In addition, during each
subsequent discharging phase, the inductor current I.sub.L begins
falling from the higher initial current level I.sub.peak_dly due to
the previous charging-phase loop delay T.sub.peak_dly, and, during
each subsequent charging phase, the inductor I.sub.L begins rising
from the lower initial current level I.sub.valley_dly due to the
previous discharging-phase loop delay T.sub.valley_dly. All of this
contributes to the overall charge-cycle duration T.sub.sw_dly being
longer than the desired duration T.sub.sw and the corresponding
charge-cycle frequency F.sub.sw_dly being lower than the desired
frequency F.sub.sw, which can result in undesirable EMI levels and
increased current ripple. Furthermore, if the rise above the
peak-current threshold I.sub.peak and the fall below valley-current
threshold I.sub.valley are not equal (which they are usually not),
then the average burst current will change which may affect the
ability of the DC-DC converter 106 to deliver the desired maximum
load current.
[0053] If the input voltage V.sub.in, the output voltage V.sub.out,
and the inductance L were fixed and if the desired charge-cycle
frequency F.sub.sw were known, then factory (or other) testing
could be performed to determine the charging-phase and
discharging-phase loop delays for the charging and discharging
phases of the charge cycles for a real-world instance of the DC-DC
converter 106. Those loop delays could then be taken into account
to select the value (I.sub.peak-(I.sub.peak_dly-I.sub.peak)) or
(2*I.sub.peak-I.sub.peak_dly) for the OC reference current 223 of
FIG. 2 and the value (I.sub.valley+(I.sub.valley-I.sub.valley_dly))
or (2*I.sub.valley-I.sub.valley_dly) for the UC reference current
219 of FIG. 2 that would achieve the desired charge-cycle duration
T.sub.sw and the desired charge-cycle frequency F.sub.sw.
[0054] However, as described above, the DC-DC converter 106 is
designed to operate for different applications having different
values for the input voltage V.sub.in, the output voltage
V.sub.out, and/or the inductance L, which can result in different
values for I.sub.peak_dly and/or I.sub.valley_dly such that the
results from factory testing for one possible application will not
apply to all possible applications. Note that the charging-phase
loop delay T.sub.peak_dly and the discharging-phase loop delay
T.sub.valley_dly are fixed for a given real-world implementation of
the DC-DC converter 106, but that the values for I.sub.peak_dly and
I.sub.valley_dly will vary depending on V.sub.in, V.sub.out, and L
for different applications of that real-world implementation.
[0055] To address these issues, certain embodiments of the DC-DC
converter 106 of this disclosure have circuitry designed and
configured to compensate for variations in one or more of the input
voltage V.sub.in, the output voltage V.sub.out, and the inductance
L to achieve a desired efficiency, a desired maximum load current,
and a desired charge-cycle frequency F.sub.sw or at least to be
within a desired range of the desired charge-cycle frequency
F.sub.sw.
[0056] FIG. 6 is a schematic block diagram of a portion of the
DC-DC converter 106 of FIGS. 1 and 2 that is involved in detecting
when to terminate an existing charging phase of a burst-mode charge
cycle. As shown in FIG. 6, the DC-DC converter 106 has a high-side,
p-type field-effect transistor (FET) switch SW.sub.H and a
low-side, n-type FET switch SW.sub.L that are part of the output
driver 204 of FIG. 2 and whose drains are interconnected at the
driver output port 602 which is in turn connected to the (external)
inductance (L) 116 and thereby to the (external) output capacitance
(C) 118. Note that, as understood by those skilled in the art, in
alternative implementations, the high-side switch SW.sub.H could be
implemented using an n-type FET. In that case, a so-called
bootstrap circuit is provided to generate the appropriate the drive
voltage when the high-side switch SW.sub.H is on.
[0057] FIG. 6 also shows the OC comparator 222 of FIG. 2, whose
negative input is connected to the driver output port 602 and whose
positive input is connected to the high-side current sense node
604, through which flows the charging-phase reference current
I.sub.pk_sns_ref (i.e., the OC reference current 223 of FIG. 2)
when the p-type FET, high-side sense switch SW.sub.HS is on. The
charging-phase reference current I.sub.pk_sns_ref is generated by
the peak sense current source I.sub.pk_sns and the peak
compensation current source I.sub.pk_comp, where
I.sub.pk_sns_ref=I.sub.pk_sns-I.sub.pk_comp.
[0058] The OC detection signal 224 generated by the OC comparator
222 is applied to the control circuit 202 of FIG. 2 and used to
generate the drive signals 226, which include: [0059] The high-side
power drive signal hs_dr, which is applied to the gate of the
high-side power switch SW.sub.H; [0060] The low-side power drive
signal ls_dr, which is applied to the gate of the low-side power
switch SW.sub.L; and [0061] The high-side sense drive signal
hs_sns_dr, which is applied to the gate of the high-side sense
switch SW.sub.HS. In a typical real-world implementation, the
transistor size of the high-side sense switch SW.sub.HS is M times
smaller than the transistor size of the high-side power switch
SW.sub.H, where (M>1) in order to scale down the magnitude of
the charging-phase reference current I.sub.pk_sns_ref to save
power.
[0062] In certain embodiments, the peak sense current source
I.sub.pk_sns is designed to generate a current given by Equation
(3) as follows:
I.sub.pk_sns=I.sub.peak/M (3)
where I.sub.peak is the ideal peak-current threshold of FIGS. 3-5,
and the peak compensation current source I.sub.pk_comp is designed
to generate a current given by Equation (4) as follows:
I pk_comp = T peak_dly * V in - V out M * L ( 4 ) ##EQU00004##
where T.sub.peak_dly is the fixed (e.g., factory-determined)
charging-phase loop delay.
[0063] At the beginning of the charging phase of a burst-mode
charge cycle, the drive signals hs_dr, ls_dr, and hs_sns_dr are all
driven low, such that the switches SW.sub.H and SW.sub.HS are on,
the switch SW.sub.L is off, the scaled (rising) current I.sub.L
flowing through the inductance 116 will be lower than the
charging-phase reference current I.sub.pk_sns_ref, and the OC
detection signal 224 will be low. Eventually, the inductor current
I.sub.L will exceed the charging-phase reference current
I.sub.pk_sns_ref causing the OC comparator 222 to drive the OC
detection signal 224 high, which will in turn cause the control
circuit 202 to drive the drive signals hs_dr and ls_dr high,
thereby turning off the high-side power switch SW.sub.H and turning
on the low-side power switch SW.sub.L to start the next discharging
phase. Note that, in a practical circuit implementation, a dead
time is guaranteed between switching off the high-side switch
SW.sub.H and switching on the low-side switch SW.sub.L to prevent
cross conduction. Note also that the drive signal hs_sns_dr remains
low throughout a burst such that the high-side sense switch
SW.sub.HS remains on throughout the burst to prevent transients
associated with switching the sense circuitry on and off from
leading to false triggers of the OC comparator 222. As indicated by
its dependence on V.sub.in, V.sub.out, and L in Equation (4), the
peak compensation current I.sub.pk_comp will adjust the
peak-current threshold for different values of V.sub.in, V.sub.out,
and/or L such that the charging phase will be terminated at a lower
peak-current threshold that compensates for the charging-phase loop
delay T.sub.peak_dly, such that the switches will be thrown just as
the inductor current I.sub.L reaches the ideal peak-current
threshold I.sub.peak.
[0064] FIG. 7 is a schematic block diagram of a portion of the
DC-DC converter 106 of FIGS. 1 and 2 that is involved in detecting
when to terminate an existing discharging phase of a burst-mode
charge cycle. FIG. 7 shows the high-side power switch SW.sub.H and
the low-side power switch SW.sub.L of FIG. 6.
[0065] FIG. 7 also shows the UC comparator 218 of FIG. 2, whose
negative input is connected to ground and whose positive input is
connected to the low-side sense node 702, through which flows the
discharging-phase reference current I.sub.valley_sns_ref (i.e., the
UC reference current 219 of FIG. 2). The discharging-phase
reference current I.sub.valley_sns_ref is generated by the valley
sense current source I.sub.valley_sns and the valley compensation
current source I.sub.valley_comp when the n-type FET, low-side
sense switch SW.sub.LS is turned on, where
I.sub.valley_sns_ref=I.sub.valley_sns+I.sub.valley_comp.
[0066] The UC detection signal 220 generated by the UC comparator
218 is applied to the control circuit 202 of FIG. 2 and used to
generate the drive signals 226, which include: [0067] The high-side
power drive signal hs_dr, which is applied to the gate of the
high-side power switch SW.sub.H; [0068] The low-side power drive
signal ls_dr, which is applied to the gate of the low-side power
switch SW.sub.L; and [0069] The low-side sense drive signal
ls_sns_dr, which is applied to the gate of the low-side sense
switch SW.sub.LS.
[0070] In a typical real-world implementation, the transistor size
of the low-side sense switch SW.sub.LS is N times smaller than the
transistor size of the low-side power switch SW.sub.L, where
(N>1) in order to scale down the magnitude of the
discharging-phase reference current I.sub.valley_sns_ref to save
power.
[0071] In certain embodiments, the valley sense current source
I.sub.valley_sns is designed to generate a current given by
Equation (5) as follows:
I.sub.valley_sns=I.sub.valley/N (5)
where I.sub.valley is the ideal valley-current threshold of FIGS.
3-5, and the valley compensation current source I.sub.valley_comp
is designed to generate a current given by Equation (6) as
follows:
I valley_comp = T valley_dly * V out N * L ( 6 ) ##EQU00005##
where T.sub.valley_dly is the fixed (e.g., factory-determined)
discharging-phase loop delay.
[0072] At the beginning of the discharging phase of a charge cycle,
the drive signals hs_dr, ls_dr, and ls_sns_dr are all driven high,
such that the switches SW.sub.L and SW.sub.LS are on, the switch
SW.sub.H is off, the (falling) current I.sub.L flowing through the
inductance 116 will be higher than the discharging-phase reference
current I.sub.valley_sns_ref, and the UC detection signal 220 will
be low. Eventually, the scaled inductor current I.sub.L will fall
below the discharging-phase reference current I.sub.valley_sns_ref
causing the UC comparator 218 to drive the UC detection signal 220
high, which will in turn cause the control circuit 202 to drive the
drive signals hs_dr and ls_dr low, thereby turning on the high-side
power switch SW.sub.H and turning off the low-side power switch
SW.sub.L to Start the next charging phase. Again, an appropriate
dead time will be ensured in a practical design to prevent cross
conduction of the power switches. Note that the drive
signalls_sns_dr remains high throughout a burst such that the
low-side sense switch SW.sub.LS remains on throughout the burst. As
for the high-side current detection, this is done to prevent
transients associated with switching the sense circuitry on and off
during the burst from leading to false triggers of the UC
comparator 218. As indicated by its dependence on V.sub.out and L
in Equation (6), the valley compensation current I.sub.valley_comp
will adjust the valley-current threshold for different values of
V.sub.out and/or L such that the discharging phase will be
terminated at a higher valley-current threshold that compensates
for the discharging-phase loop delay T.sub.valley_dly, such that
the switches will be thrown just as the inductor current I.sub.L
reaches the ideal valley-current threshold I.sub.valley.
[0073] Those skilled in the art will understand that, at the moment
that the low-current comparator 218 trips, the drain, gate, and
source voltages of the low-side sense switch SW.sub.LS are
respectively equal to the drain, gate, and source voltages of the
low-side power switch SW.sub.L, indicating that the inductor
current I.sub.L is equal to a scaled-up version of the
discharging-phase reference current I.sub.valley_sns_ref. Since the
source of the low-side power switch SW.sub.L is connected directly
to ground, connecting the negative input of the low-current
comparator 218 to ground is equivalent to connecting the negative
input to the source of the low-side power switch. Note that, at the
start of the discharging phase, the drain voltage at the driver
output port 602 will be negative, such that current will flow from
the ground node through the low-side power switch SW.sub.L to the
driver output port 602.
[0074] While the current flowing through the low-side power switch
SW.sub.L is higher than the target valley current, the drain
voltage, to which the low-side sense switch SW.sub.LS is also
connected, is more negative than the drain voltage at the trip
point. Since the discharging-phase reference current
I.sub.valley_sns_ref through the low-side sense switch SW.sub.LS is
a fixed current, this means that, at that moment, the source of the
low-side sense switch SW.sub.LS is still below 0V. Therefore, the
UC comparator 218 will not trip because the (zero) voltage at the
comparator's negative input will be higher than the (negative)
voltage at the comparator's positive input. As the current through
the low-side power switch SW.sub.L drops, the drain voltage rises,
pulling the source of the low-side sense switch SW.sub.LS up until
it reaches 0V. At that moment, the low-side power switch current
has reached N*I.sub.valley_sns_ref. The valley compensation current
I.sub.valley_comp is chosen to be higher than the ideal valley
sense current I.sub.valley_sns, such that, given the
discharging-phase loop delay, the actual current level at which the
low-side power switch SW.sub.L turns off is N*I.sub.valley_sns,
which is the desired result.
[0075] With the compensation for the charging-phase loop delay
T.sub.peak_dly provided by the circuitry of FIG. 6 and with the
compensation for the discharging-phase loop delay T.sub.valley_dly
provided by the circuitry of FIG. 7, real-world implementations of
the DC-DC converter 106 are able to achieve the desired efficiency,
maximum load current, and burst-mode charge-cycle frequency
F.sub.sw for all of the different supported combinations of input
voltage V.sub.in, output voltage V.sub.out, and inductance.
[0076] Assume, for example, an implementation of the DC-DC
converter 106 of FIGS. 1, 2, 6, and 7 that is designed to operate
for input voltages V.sub.in between 1.7V and 3.6V, output voltages
V.sub.out between 0.7V and 2V, drop-out voltages
(V.sub.in-V.sub.out) of a minimum of 500 mV, inductances L between
500 nH and 2.2 .mu.H, output capacitances C between 6 .mu.F and 14
.mu.F, maximum load currents between 40 mA and 60 mA, and
charge-cycle frequencies F.sub.sw between 2 MHz and 10 MHz, where
(i) the high-side power switch SW.sub.H is M=1350 times larger than
the high-side sense switch SW.sub.HS and (ii) the low-side power
switch SW.sub.L is N=530 times larger than the low-side sense
switch SW.sub.LS. Assume further that the DC-DC converter 106 has a
charging-phase loop delay T.sub.peak_dly of 15 ns and a
discharging-phase loop delay T.sub.valley_dly of 15 ns. Note that,
just because certain parameters have ranges of possible values,
that does not mean that the DC-DC converter 106 will operate
properly for every possible combination of those parameters within
those ranges.
[0077] One possible application for that example implementation of
the DC-DC converter 106 has an input voltage V.sub.in of 3V, an
output voltage V.sub.out of 1.1V, an inductance L of 1 .mu.H, an
output capacitance C of 10 .mu.F, a maximum load current of 50 mA,
and a charge-cycle frequency F.sub.sw of 5 MHz. In that case,
Equations (1) and (2) can be used to configure the DC-DC converter
106 to operate with an ideal peak current I.sub.peak of 169.3 mA,
an ideal valley current I.sub.valley of 30 mA, a charging-phase
duration t.sub.on of 73.3 ns, and a discharging phase duration
t.sub.off of 126.6 ns.
[0078] Based on Equation (3), the peak sense current source
I.sub.pk_sns is configured to generate a current given by Equation
(7) as follows:
I.sub.pk_sns=I.sub.peak/M=169.3 mA/1350=125 .mu.A. (7)
Based on Equation (4), the peak compensation current source
I.sub.pk_comp is configured to generate a current given by Equation
(8) as follows:
I pk_comp = T peak_dly * V in - V out M * L = 15 ns * 3 V - 1.1 V
1350 * 1 H = 21 A . ( 8 ) ##EQU00006##
Based on Equation (5), the valley sense current source
I.sub.valley_sns is configured to generate a current given by
Equation (9) as follows:
I.sub.valley_sns=I.sub.valley/N=30 mA/530=57 .mu.A. (9)
Based on Equation (6), the valley compensation current source
I.sub.valley_comp is configured to generate a current given by
Equation (10) as follows:
I valley_comp = T valley_dly * V out N * L = 15 ns * 1.1 V 530 * 1
H = 31 A . ( 10 ) ##EQU00007##
[0079] Another possible application for that same example
implementation of the DC-DC converter 106 has an input voltage
V.sub.in of 2.5V, an output voltage V.sub.out of 1V, an inductance
L of 1 .mu.H, an output capacitance C of 10 .mu.F, a maximum load
current of 15 mA, and a charge-cycle frequency F.sub.sw of 6 MHz.
In that case, Equations (1) and (2) can be used to configure the
DC-DC converter 106 to operate with an ideal peak current
I.sub.peak of 85 mA, an ideal valley current I.sub.valley of -15
mA, a charging-phase duration t.sub.on of 66.7 ns, and a
discharging phase duration t.sub.off of 100 ns.
[0080] In that case, based on Equation (3), the peak sense current
source I.sub.pk_sns is configured to generate a current given by
Equation (11) as follows:
I.sub.pk_sns=I.sub.peak/M=85 mA/1350=63 .mu.A. (11)
Based on Equation (4), the peak compensation current source
I.sub.pk_comp is configured to generate a current given by Equation
(12) as follows:
I pk_comp = T peak_dly * V in - V out M * L = 15 ns * 2.5 V - 1 V
1350 * 1 H = 17 A . ( 12 ) ##EQU00008##
Based on Equation (5), the valley sense current source
I.sub.valley_sns is configured to generate a current given by
Equation (13) as follows:
I.sub.valley_sns=I.sub.valley/N=-15 mA/530=-28 .mu.A. (13)
Based on Equation (6), the valley compensation current source
I.sub.valley_comp is configured to generate a current given by
Equation (14) as follows:
I valley_comp = T valley_dly * V out N * L = 15 ns * 1 V 530 * 1 H
= 28 A . ( 14 ) ##EQU00009##
Note that, by coincidence, since the delay time is 15 ns while the
current is -15 mA and the slope is -1 A/.mu.s, the compensated
valley reference ends up at (-28.3 .mu.A+28.3 .mu.A)=0 .mu.A.
[0081] FIG. 8 is an example timing diagram showing the four drive
signals of FIGS. 6 and 7 for two bursts separated by an off-burst
period, where each burst has four charge cycles. As shown in FIG.
8, in order to avoid a cross-conduction current flowing directly
from V.sub.in to ground at the beginning of each charging period
(T.sub.on), the high-side power drive signal hs_dr is driven low
after the low-side power drive signal ls_dr has been driven low in
order to ensure that the low-side power switch SW.sub.L has been
turned off before the high-side power switch SW.sub.H is turned on.
Similarly, in order to avoid a similar cross-conduction current at
the beginning of each discharging period (T.sub.off), the high-side
power drive signal hs_dr is driven high before the low-side power
drive signal ls_dr is driven high in order to ensure that the
high-side power switch SW.sub.H has been turned off before the
low-side power switch SW.sub.L is turned on.
[0082] As shown in FIG. 8, during each burst, the high-side sense
drive signal hs_sns_dr is low (to turn on the high-side sense
switch SW.sub.HS) and the low-side sense drive signal ls_sns_dr is
high (to turn on the low-side sense switch SW.sub.LS).
[0083] At the end of each burst, the high-side power and sense
drive signals hs_dr and hs_sns_dr are both driven high and the
low-side power and sense drive signals ls_dr and ls_sns_dr are both
driven low to turn off all four switches SW.sub.H, SW.sub.HS,
SW.sub.L, and SW.sub.LS.
[0084] FIG. 9 is a schematic block diagram of one embodiment of the
peak sense current source I.sub.pk_sns of FIG. 6. On the top side
of FIG. 9, two circuits generate currents that depend on V.sub.in
and V.sub.out, respectively. In both cases, the voltage (V.sub.in
or V.sub.out) is placed across a resistor R using an opamp-based
feedback loop, and using a mirror ratio of 2:1, currents
V.sub.in/2R and V.sub.out/R are obtained using the two indicated
circuits. These two currents, and derivatives thereof, serve as
inputs to the Gilbert cell, i.e., a current multiplier. Using the
trans-linear loop of M1, M2, M3, and M4, it can be found that
I.sub.D1=(I.sub.D3*I.sub.D4/I.sub.D2). When filling in the valid
equations for I.sub.D2, I.sub.D3, and I.sub.D4, it is found
that:
I D 2 = V in 4 R , I D 3 = V in - V out 2 R , and ##EQU00010## I D
4 = V out 2 R . ##EQU00010.2##
[0085] Since I.sub.D1=(I.sub.D3*I.sub.D4/I.sub.D2), the following
equation of the output current I.sub.D1 is obtained:
I D 1 = V OUT R - V OUT 2 R V IN ##EQU00011##
[0086] This current I.sub.D1 is in fact the intended current ripple
I.sub.peak-I.sub.valley to obtain the desired switching frequency
F.sub.sw, where R=L*F.sub.SW. Current I.sub.D1 is then added to the
intended valley current reference I.sub.valley_sns to obtain the
intended peak current reference I.sub.pk_sns. This current
I.sub.pk_sns then flows to V.sub.ss (i.e., ground) as shown in FIG.
6.
[0087] FIG. 10 is a schematic block diagram of one embodiment of
the peak compensation current source I.sub.pk_comp of FIG. 6.
Similar to the circuit in FIG. 9, two opamp-based circuits generate
currents V.sub.in/R and V.sub.out/R. These currents are then
subtracted from each other using the 1:1 current mirror. Using
another current mirror, the resulting current
(V.sub.in-V.sub.out)/R is then multiplied by a defined value
T.sub.dly_pk. The current I.sub.pk_comp then flows from V.sub.in,
as shown in FIG. 6. If R is chosen/trimmed to be equal to M*L, then
the desired Equation (4) is obtained.
[0088] FIG. 11 is a schematic block diagram of one embodiment of
the valley sense current source I.sub.valley_sns of FIG. 7. Bias
current I.sub.bias is taken as an input current, which is mirrored
twice to get the desired I.sub.valley_sns reference current coming
from V.sub.in, in line with what is shown in FIG. 7.
[0089] FIG. 12 is a schematic block diagram of one embodiment of
the valley compensation current source I.sub.valley_comp of FIG. 7.
Similar to the circuit in FIG. 9, an opamp-based circuit is used to
generate current V.sub.out/R. This current is mirrored first via a
1:1 mirror to make it flow to V.sub.ss to be able to multiply it in
the second mirror with value T.sub.dly_vly. This current now flows
from V.sub.in, as shown in FIG. 6, and in accordance with Equation
(6). Again, R is trimmed to be equal to N*L.
Programmable Valley Current
[0090] The preceding description assumed that the desired peak- and
valley-current thresholds I.sub.peak and I.sub.valley,
respectively, used to detect the ends of the charging and
discharging phases of burst-mode charge cycles are fixed for a
given application of the DC-DC converter 106 of FIGS. 1 and 2.
According to alternative embodiments of this disclosure, the DC-DC
converter 106 is capable to operating at two (or more) different,
configurable valley-current thresholds I.sub.valley and, as a
result, at two (or more) different peak-current thresholds
I.sub.peak. For example, in some embodiments, the DC-DC converter
106 is designed to receive a control signal 105 from the controller
104 of FIG. 1 that instructs the DC-DC converter 106 to operate in
either a normal-power (NP) mode or a low-power (LP) mode, where the
NP mode may correspond to situations in which the DC-DC converter
106 may have to generate relatively high load currents up to the
converter's specified maximum allowable load current, while the LP
mode may correspond to situations in which the DC-DC converter 106
is operating in its standby mode with little or no load
current.
[0091] FIG. 13 is a schematic block diagram of a portion of an
embodiment of the DC-DC converter 106 of FIGS. 1 and 2 that can be
selectively configured to operate in either a normal-power mode or
a low-power mode. Similar to the embodiments of FIGS. 6 and 7, the
embodiment of FIG. 13 includes a high-side power switch SW.sub.H, a
low-side power switch SW.sub.L, a high-side sense switch SW.sub.HS,
a UC comparator 218, and an OC comparator 222. In FIG. 13, the peak
reference current source I.sub.pk,ref corresponds to the
combination of the peak sense current source I.sub.pksns and the
peak compensation current source I.sub.pkcomp of FIG. 6.
[0092] Unlike the embodiment of FIG. 7 which has a single low-side
sense switch SW.sub.LS, the embodiment of FIG. 13 has two low-side
sense switches: an NP-mode, n-type FET, low-side sense switch
SW.sub.LS_NP and an LP-mode, n-type FET, low-side sense switch
SW.sub.LS_LP, where each low-side sense switch has its own
discharging-phase reference current source. In particular, the
NP-mode discharging-phase reference current source I.sub.vly,ref,NP
has a combination of (i) an NP valley sense current source
analogous to the valley sense current source I.sub.valley_sns of
FIG. 7 and (ii) an NP valley compensation current source analogous
to the valley compensation current source I.sub.valley_comp of FIG.
7. Similarly, the LP-mode discharging-phase reference current
source I.sub.vly,ref,LP has a combination of (i) an LP valley sense
current source analogous to the valley sense current source
I.sub.valley_sns of FIG. 7 and (ii) an LP valley compensation
current source analogous to the valley compensation current source
I.sub.valley_comp of FIG. 7.
[0093] As shown in FIG. 13, the DC-DC converter 106 receives a
low-power mode control signal mode_low_pwr (105) from the
controller 104 of FIG. 1, which controls positive and negative
input switches 1302 and 1304. When the mode_low_pwr is low,
indicating that the DC-DC converter 106 is to operate in the NP
mode, the switches 1302 and 1304 are set to connect (i) the
positive input of the UC comparator 218 to the source of the NP
low-side sense switch SW.sub.LS_NP and (ii) the negative input of
the UC comparator 218 to ground. In that case, the circuitry of
FIG. 13 is configured to operate similar to the circuitry of FIG.
7.
[0094] However, when the mode_low_pwr is high, indicating that the
DC-DC converter 106 is to operate in the LP mode, the switches 1302
and 1304 are set to connect (i) the positive input to the UC
comparator 218 to the drain of the low-side power switch SW.sub.L
(i.e., the driver output port 602 of FIGS. 6 and 7) and (ii) the
negative input to the UC comparator 218 to the drain of the LP
low-side sense switch SW.sub.LS_LP. In that case, the circuitry of
FIG. 13 is configured to operate differently from the circuitry of
FIG. 7. The reason is that, in LP mode, from an efficiency point of
view, it is advantageous to use a negative valley current, i.e., a
current that pushes the drain of the low-side power switch SW.sub.L
above ground. In that case, if the drain of the low-side power
switch SW.sub.L is above the drain of the senseFET SW.sub.LS_LP,
then the comparator 218 should toggle. Having a negative valley
current at the moment the low-side power switch SW.sub.L is
switched off allows for applying zero-voltage switching of the
high-side power switch SW.sub.H. Since the valley current is
negative, it can charge up the driver output port 602 when both
switches are off, and SW.sub.H can be switched on when there is
zero voltage across its drain-to-source terminals. This reduces
switching losses and thereby improves efficiency, which is
especially important in LP mode.
[0095] FIG. 14 is a timing diagram of the operations of the DC-DC
converter 106 of FIG. 13 for both the normal-power mode and the
low-power mode. As shown in FIG. 14, during normal-power mode
(i.e., when mode_low_pwr is low (e.g., 0)), during a burst, the
inductor current I.sub.L cycles back and forth between an NP-mode
valley-current threshold I.sub.vly,NP and an NP-mode peak-current
threshold I.sub.pk,NP. Similarly, during low-power mode (i.e., when
mode_low_pwr is high (e.g., V.sub.in), during a burst, the inductor
current I.sub.L cycles back and forth between an LP-mode
valley-current threshold I.sub.vly,LP and an LP-mode peak-current
threshold I.sub.pk,LP, where (i) the LP-mode valley-current
threshold I.sub.vly,LP is lower than the NP-mode valley-current
threshold I.sub.vly,NP and (ii) the LP-mode peak-current threshold
I.sub.pk,LP is lower than the NP-mode peak-current threshold
I.sub.pk,NP, such that overall power consumption is lower during
LP-mode than during NP-mode, thereby avoiding inefficient standby
power consumption when the DC-DC converter 106 is driving little or
no output load. In particular, making the LP-mode valley-current
threshold I.sub.vly,LP slightly negative, as is shown in FIG. 14,
enables zero-voltage switching when switching on the high-side
power switch SW.sub.H to start the next charging phase. This
reduces switching losses and therefore increases efficiency.
[0096] For example, in one possible implementation, the NP-mode
valley-current threshold I.sub.vly,NP is 30 mA and the LP-mode
valley-current threshold I.sub.vly,LP is -15 mA.
[0097] Note that, as indicated in FIG. 14 by the drive signals
hs_sns_dr and ls_sns_dr, in this implementation of the DC-DC
converter 106 of FIG. 13, in NP mode, the high-side and low-side
sense switches SW.sub.HS and SW.sub.LS are always on, both during a
burst and during an off-burst. On the other hand, in LP mode,
although the high-side and low-side sense switches SW.sub.HS and
SW.sub.LS are both on during a burst, they are both off during an
off-burst. This prevents losing power between bursts due to the
reference currents in the senseFETs flowing and thereby increases
efficiency.
[0098] In order to generate the valley current references
I.sub.vly,ref,NP and I.sub.vly,ref,LP shown in FIG. 13, circuits as
shown in FIG. 11 are used, where either a single circuit may
generate two different reference currents based on the same bias
current, by having two differently scaled outputs of the output
current mirror, or two separate circuits are used. Compensation of
the references to deal with delays of comparators, controller, and
drivers may be implemented using the circuitry of FIG. 12, where
only one such circuit is used (i.e., the same compensation current
is used for both NP and LP mode). In order to generate the peak
current references I.sub.pk,ref,NP and I.sub.pk,ref,LP in FIG. 13,
circuits as shown in FIG. 9 are used, where either the same deltaI
current can be added to the corresponding valley current
I.sub.vly,ref,NP or I.sub.vly,ref,LP, respectively, in both modes,
or a different deltaI current can be added in the two different
modes. An example of the latter situation would be to deny the use
of frequency control via the deltaI circuit in LP mode, which
instead of a V.sub.in-dependent and V.sub.out-dependent ripple
current deltaI current used when frequency control is used, would
add a deltaI current that is constant over V.sub.in and V.sub.out
variations. A reason to do this would be to limit power consumption
of blocks to increase efficiency in LP mode, and generating a
constant deltaI current is simpler, i.e., requiring less circuitry
and therefore less power, than a V.sub.in-dependent and
V.sub.out-dependent deltaI current used for frequency control as
shown in FIG. 9. As is the case for the valley currents,
compensation of the references to deal with delay of comparators,
controller, and drivers may be implemented using the circuitry of
FIG. 10, where only one such circuit is used (i.e., the same
compensation current is used for both NP and LP mode).
[0099] Embodiments of this disclosure have been described in the
context of buck-type DC-DC converters having two power switches
(i.e., a high-side power switch SW.sub.H and a low-side power
switch SW.sub.L), an inductor, and a capacitor configured to be
connected to provide output voltage to a load. Those skilled in the
art will understand that alternative embodiments of this disclosure
may be two-switch boost-type DC-DC converters, two-switch or
four-switch buck/boost-type DC-DC converters, or two-switch
Cuk-type DC-DC converters, all of which have (at least) one
inductor and (at least) one capacitor configured to be connected to
provide output voltage to a load. Note that a Cuk DC-DC converter
has two inductors and two capacitors. Note that, in some
implementations of these different types of DC-DC converters, at
least one of the switches may be implemented using a diode.
[0100] Furthermore, as understood by those skilled in the art, each
of those different types of DC-DC converters has a control switch
that is turned on for the charging phase and a
synchronous-rectification (SR) switch that is turned on for the
discharging phase. The latter switch then replaces the diode in the
basic circuit configuration. In the buck converters described
above, the high-side power switch SW.sub.H is the control switch,
and the low-side power switch SW.sub.L is the
synchronous-rectification (SR) switch. In a boost DC-DC converter,
the control switch is a low-side power switch, and the SR switch is
a high-side power switch. In a buck/boost DC-DC converter, both the
control switch and the SR switch are high-side power switches, and,
in a Cuk DC-DC converter, both the control switch and the SR switch
are low-side power switches.
[0101] Although embodiments have been described that have two
operating modes, i.e., (i) a normal-power (NP) mode having an
NP-mode valley current and an NP-mode peak current and (ii) a
low-power (LP) mode having an LP-mode valley current and an LP-mode
peak current, where the LP-mode valley current is negative, in
general, embodiments may have two or more different operating
modes, each having a corresponding pair of valley and peak
currents, where each valley current may be positive, negative, or
zero.
[0102] According to certain embodiments, the disclosure describes
circuitry comprising a DC-DC converter. When an inductance and a
capacitance are connected to the DC-DC converter, the DC-DC
converter is configured to convert an input voltage into an output
voltage at an output port to drive a load connected to the output
port. The DC-DC converter is configured to operate in a burst mode
comprising at least one charge cycle comprising a charging phase
followed by a discharging phase. The charging phase is terminated
when an inductor current flowing through the inductance reaches a
compensated peak-current threshold, wherein the compensated
peak-current threshold compensates for charging-phase loop delay.
The discharging phase is terminated when the inductor current
reaches a compensated valley-current threshold, wherein the
compensated valley-current threshold compensates for
discharging-phase loop delay.
[0103] According to certain embodiments, the disclosure describes a
method for operating a DC-DC converter in burst mode. The method
comprises, for at least one burst-mode charge cycle, charging an
inductance and a capacitance connected to the DC-DC converter until
an inductor current flowing through the inductance reaches a
compensated peak-current threshold, wherein the compensated
peak-current threshold compensates for charging-phase loop delay
and discharging the inductance until the inductor current reaches a
compensated valley-current threshold, wherein the compensated
valley-current threshold compensates for discharging-phase loop
delay.
[0104] According to certain embodiments of the above, the circuitry
is an integrated circuit comprising the DC-DC converter and the
inductance and the capacitance are external to the integrated
circuit.
[0105] According to certain embodiments of the above, the DC-DC
converter comprises an output driver configured to selectively
charge the inductance and the capacitance; a control circuit
configured to control the output driver; comparator circuitry
configured to generate feedback signals to the control circuit for
use in controlling the output driver; and current generation
circuitry configured to generate reference currents for the
comparator circuitry. The current generation circuitry is
configured to generate a charging-phase reference current
corresponding to the compensated peak-current threshold, and the
comparator circuitry is configured to compare the charging-phase
reference current to a current corresponding to the inductor
current to determine when to terminate the charging phase of a
burst-mode charge cycle. The current generation circuitry is
configured to generate a discharging-phase reference current
corresponding to the compensated valley-current threshold, and the
comparator circuitry is configured to compare the discharging-phase
reference current to a current corresponding to the inductor
current to determine when to terminate the discharging phase of a
burst-mode charge cycle.
[0106] According to certain embodiments of the above, the output
driver comprises a high-side power switch connected between the
input voltage and the inductance; a low-side power switch connected
between the inductance and ground, wherein the high-side power
switch, the inductance, the low-side power switch, and a first
input to an over-current comparator of the comparator circuitry are
interconnected at a first node (e.g., 602); a high-side sense
switch connected between the input voltage and a second input to
the over-current comparator, wherein the charging-phase reference
current is applied to the second input to the over-current
comparator; and a low-side sense switch connected between the first
node and a first input to an under-current comparator of the
comparator circuitry, wherein (i) the discharging-phase reference
current is applied to the first input of the under-current
comparator and (ii) a second input to the under-current comparator
is connected to ground.
[0107] According to certain embodiments of the above, the current
generation circuitry is configured to generate the charging-phase
reference current as a function of the charging-phase loop delay,
the input voltage, the output voltage, and the inductance and the
current generation circuitry is configured to generate the
discharging-phase reference current as a function of the
discharging-phase loop delay, the output voltage, and the
inductance.
[0108] According to certain embodiments of the above, the current
generation circuitry comprises a peak sense current source
configured to generate a peak sense current that is independent on
the charging-phase loop delay; a peak compensation current source
configured to generate a peak compensation current that is
dependent on the charging-phase loop delay, wherein the
charging-phase reference current is based on the peak sense current
and the peak compensation current; a valley sense current source
configured to generate a valley sense current that is independent
on the discharging-phase loop delay; and a valley compensation
current source configured to generate a valley compensation current
that is dependent on the discharging-phase loop delay, wherein the
discharging-phase reference current is based on the valley sense
current and the valley compensation current.
[0109] According to certain embodiments of the above, the
compensated peak-current threshold is lower than the inductor
current when the output driver is turned off at the end of a
charging phase and the compensated valley-current threshold is
higher than the inductor current when the output driver is turned
on at the end of a discharging phase.
[0110] It is further noted that the functional blocks, components,
systems, devices, or circuitry described herein can be implemented
using hardware, software, or a combination of hardware and software
along with analog circuitry as needed. For example, the disclosed
embodiments can be implemented using one or more integrated
circuits that are programmed to perform the functions, tasks,
methods, actions, or other operational features described herein
for the disclosed embodiments. The one or more integrated circuits
can include, for example, one or more processors or configurable
logic devices (CLDs) or a combination thereof. The one or more
processors can be, for example, one or more central processing
units (CPUs), controllers, microcontrollers, microprocessors,
hardware accelerators, ASICs (application specific integrated
circuit), or other integrated processing devices. The one or more
CLDs can be, for example, one or more CPLDs (complex programmable
logic devices), FPGAs (field programmable gate arrays), PLAs
(programmable logic array), reconfigurable logic circuits, or other
integrated logic devices. Further, the integrated circuits,
including the one or more processors, can be programmed to execute
software, firmware, code, or other program instructions that are
embodied in one or more non-transitory tangible computer-readable
mediums to perform the functions, tasks, methods, actions, or other
operational features described herein for the disclosed
embodiments. The integrated circuits, including the one or more
CLDs, can also be programmed using logic code, logic definitions,
hardware description languages, configuration files, or other logic
instructions that are embodied in one or more non-transitory
tangible computer-readable mediums to perform the functions, tasks,
methods, actions, or other operational features described herein
for the disclosed embodiments. In addition, the one or more
non-transitory tangible computer-readable mediums can include, for
example, one or more data storage devices, memory devices, flash
memories, random access memories, read only memories, programmable
memory devices, reprogrammable storage devices, hard drives, floppy
disks, DVDs, CD-ROMs, or any other non-transitory tangible
computer-readable mediums. Other variations can also be implemented
while still taking advantage of the techniques described
herein.
[0111] Unless stated otherwise, terms such as "first" and "second"
are used to arbitrarily distinguish between the elements such terms
describe. Thus, these terms are not necessarily intended to
indicate temporal or other prioritization of such elements.
[0112] Further modifications and alternative embodiments of the
described systems and methods will be apparent to those skilled in
the art in view of this description. It will be recognized,
therefore, that the described systems and methods are not limited
by these example arrangements. It is to be understood that the
forms of the systems and methods herein shown and described are to
be taken as example embodiments. Various changes may be made in the
implementations. Thus, although the invention is described herein
with reference to specific embodiments, various modifications and
changes can be made without departing from the scope of the present
invention. Accordingly, the specification and figures are to be
regarded in an illustrative rather than a restrictive sense, and
such modifications are intended to be included within the scope of
the present invention. Further, any benefits, advantages, or
solutions to problems that are described herein with regard to
specific embodiments are not intended to be construed as a
critical, required, or essential feature or element of any or all
the claims.
* * * * *