U.S. patent application number 17/180835 was filed with the patent office on 2021-06-10 for secure semiconductor integration.
This patent application is currently assigned to BroadPak Corporation. The applicant listed for this patent is BroadPak Corporation. Invention is credited to Farhang YAZDANI.
Application Number | 20210175162 17/180835 |
Document ID | / |
Family ID | 1000005407549 |
Filed Date | 2021-06-10 |
United States Patent
Application |
20210175162 |
Kind Code |
A1 |
YAZDANI; Farhang |
June 10, 2021 |
SECURE SEMICONDUCTOR INTEGRATION
Abstract
A system comprising a plurality of electronic components,
wherein said plurality of electronic components including a first
component and a second component, and said first component is a
security component configured to generate and/or store security
key(s); a substrate; one or more standoff substrate(s) comprising
of cavity(3ies), wherein said one or more standoff substrate(s)
is/are coupled to said substrate, said one or more standoff
substrate(s) completely encircles said substrate, said security
component is disposed inside said cavity(ies), said security
component is coupled to said substrate, said security component is
obfuscated by said substrate and said one or more standoff
substrate(s), and said security component and said second component
are configured to communicate security key(s) for performing device
identification, authentication, encryption, and/or device integrity
verification.
Inventors: |
YAZDANI; Farhang; (Santa
Clara, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
BroadPak Corporation |
San Jose |
CA |
US |
|
|
Assignee: |
BroadPak Corporation
San Jose
CA
|
Family ID: |
1000005407549 |
Appl. No.: |
17/180835 |
Filed: |
February 21, 2021 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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16724319 |
Dec 22, 2019 |
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17180835 |
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15810050 |
Nov 11, 2017 |
10515886 |
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16724319 |
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14746045 |
Jun 22, 2015 |
9818680 |
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15810050 |
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14717798 |
May 20, 2015 |
9893004 |
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14746045 |
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13192217 |
Jul 27, 2011 |
10236275 |
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14717798 |
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62015459 |
Jun 22, 2014 |
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62002794 |
May 24, 2014 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 23/473 20130101;
H01L 2924/207 20130101; H01L 23/49838 20130101; Y10T 29/53178
20150115; H01L 2224/48227 20130101; H01L 2224/13147 20130101; H01L
2924/19041 20130101; H01L 2225/06513 20130101; H01L 2225/107
20130101; H01L 24/08 20130101; H01L 23/573 20130101; H01L 21/486
20130101; H01L 25/50 20130101; Y10T 29/53183 20150115; H01L 25/105
20130101; H01L 2225/1058 20130101; H01L 2924/00014 20130101; H01L
2223/6677 20130101; H01L 24/16 20130101; H01L 23/49833 20130101;
H01L 2225/06572 20130101; H01L 2224/16227 20130101; H01L 23/66
20130101; H01L 24/48 20130101; H01L 2924/19105 20130101; H01L
2225/06527 20130101; H01L 2225/1023 20130101; H01L 2924/30107
20130101; H01L 2924/15311 20130101; H01L 25/18 20130101; H01L
2225/06541 20130101; H01L 2225/06517 20130101; H01L 2224/16145
20130101; H01L 2924/15153 20130101; H01L 21/52 20130101; H01L
23/3107 20130101; H01L 24/80 20130101; H01L 23/04 20130101; H01L
25/0657 20130101; H01L 2224/08235 20130101; H01L 2223/6683
20130101; H01L 2224/08145 20130101; H01L 25/0652 20130101; H01L
23/49827 20130101; H01L 2924/15331 20130101; Y10T 29/53174
20150115; H01L 2225/06548 20130101; H01L 2224/80203 20130101; H01L
2924/10253 20130101 |
International
Class: |
H01L 23/498 20060101
H01L023/498; H01L 25/00 20060101 H01L025/00; H01L 23/00 20060101
H01L023/00; H01L 21/48 20060101 H01L021/48; H01L 23/31 20060101
H01L023/31; H01L 21/52 20060101 H01L021/52; H01L 23/473 20060101
H01L023/473; H01L 23/66 20060101 H01L023/66; H01L 23/04 20060101
H01L023/04; H01L 25/065 20060101 H01L025/065; H01L 25/18 20060101
H01L025/18; H01L 25/10 20060101 H01L025/10 |
Claims
1. A system comprising: a plurality of components, wherein said
plurality of components including a first component and a second
component, and said first component is a security component
configured to generate and/or store security key(s); a substrate;
one or more standoff substrate(s) comprising of cavity(ies),
wherein said one or more standoff substrate(s) is/are coupled to
said substrate, said one or more standoff substrate(s) completely
encircles said substrate, said security component is disposed
inside said cavity(ies), said security component is coupled to said
substrate, said security component is obfuscated by said substrate
and/or said one or more standoff substrate(s) to minimize
tampering, and said security component and said second component
are configured to communicate security key(s) for performing device
identification, authentication, encryption, and/or device integrity
verification.
2. A system according to claim 1, wherein one of said plurality of
components is configured to perform tamper detection.
3. A system according to claim 1, wherein one of said plurality of
components disposed inside said cavity(ies) is a power (voltage)
regulator.
4. A system according to claim 1, wherein said the one standoff
substrate doesn't encircle said substrate(s).
5. A system according to claim 1, wherein said one or more standoff
substrate(s) are spaced apart.
6. A system according to claim 1, wherein said substrate(s)
comprises of one or more cavity(ies).
7. A system according to claim 1, wherein said substrate(s) and/or
standoff substrate(s) comprises of anti-tamper mesh.
8. A system according to claim 1, wherein said substrate(s) and/or
standoff substrate(s) comprises of molding compound.
9. A system according to claim 1, wherein one of said plurality of
the components is a power management/regulator or security
sub-circuit or tamper detect circuit or router or switch or antenna
or radar or phased array or modem or baseband or transceiver or
mm-wave subsystem or silicon-on-insulator or amplifier or Field
Programmable Gate Array (FPGA) or capacitor or resistor or inductor
or processor or memory or sensor or analog-to-digital converter or
digital-to-analog converter or electrical-optical converter or
optical-electrical converter or Light Emitting Diode (LED) or
Application-Specific Integrated Circuit (ASIC) or Through-Silicon
Via (TSV) or laser or analog circuit or digital circuit or
Serializer/Deserializer (SerDes) or filter or Lens or Graphics
Processing Unit (GPU) or magnet or waveguide or wirebond or epoxy
mold compound (EMC) or under-fill material or heat-pipe or mirror
or fan or bump or fiber or accelerator/co-processor or processor
core or Microelectromechanical Systems (MEMS) or membrane or heat
spreader or energy source or sensing material or piezoelectric or
light source or touch screen or Liquid Crystal Display (LCD) or
organic light-emitting diode (OLED) or battery or Electromagnetic
Shield (EMI) coating.
10. A system comprising: a plurality of components, wherein said
plurality of components including a first component and a second
component, and said first component is a security component
configured to generate and/or store security key(s); a first
substrate; a second substrate; one or more standoff substrate(s)
comprising of cavity(ies), wherein said one or more standoff
substrate(s) is/are coupled to said first substrate and said second
substrate, said one or more standoff substrate(s) completely
encircles said first substrate and/or said second substrate, said
security component is disposed inside said cavity(ies), said
security component is coupled to said first substrate and/or said
second substrate, said security component is obfuscated by said
first substrate and/or said second substrate and/or said one or
more standoff substrate(s) to minimize tampering, said second
component is coupled to said first substrate and/or said second
substrate, said second component is configured to communicate with
said security component, and said security component and said
second component are configured to communicate security key(s) for
performing device identification, authentication, encryption,
and/or device integrity verification.
11. A system according to claim 10, wherein one of said plurality
of components is configured to perform tamper detection.
12. A system according to claim 10, wherein one of said plurality
of components disposed inside said cavity(ies) is a power (voltage)
regulator.
13. A system according to claim 10, wherein said the one standoff
substrate doesn't encircle said first substrate and/or said second
substrate.
14. A system according to claim 10, wherein said one or more
standoff substrate(s) are spaced apart.
15. A system according to claim 10, wherein said first substrate
and/or said second substrate comprises of one or more
cavity(ies).
16. A system according to claim 10, wherein said first substrate
and/or said second substrate and/or said standoff substrate(s)
comprises of anti-tamper mesh.
17. A system according to claim 10, wherein said first substrate
and/or said second substrate and/or said standoff substrate(s)
comprises of molding compound.
18. A system according to claim 10, wherein one of said plurality
of the components is a power management/regulator or security
sub-circuit or tamper detect circuit or router or switch or antenna
or radar or phased array or modem or baseband or transceiver or
mm-wave subsystem or silicon-on-insulator or amplifier or Field
Programmable Gate Array (FPGA) or capacitor or resistor or inductor
or processor or memory or sensor or analog-to-digital converter or
digital-to-analog converter or electrical-optical converter or
optical-electrical converter or Light Emitting Diode (LED) or
Application-Specific Integrated Circuit (ASIC) or Through-Silicon
Via (TSV) or laser or analog circuit or digital circuit or
Serializer/Deserializer (SerDes) or filter or Lens or Graphics
Processing Unit (GPU) or magnet or waveguide or wirebond or epoxy
mold compound (EMC) or under-fill material or heat-pipe or mirror
or fan or bump or fiber or accelerator/co-processor or processor
core or Microelectromechanical Systems (MEMS) or membrane or heat
spreader or energy source or sensing material or piezoelectric or
light source or touch screen or Liquid Crystal Display (LCD) or
organic light-emitting diode (OLED) or battery or Electromagnetic
Shield (EMI) coating.
19. A system comprising: a plurality of components, wherein said
plurality of components including a first component and a second
component, and said first component is a security component
configured to generate and/or store security key(s); a first
substrate; a second substrate, wherein said second substrate
comprising cavity(ies); and one or more standoff substrate(s),
wherein said one or more standoff substrate comprising said
cavity(ies), said security component is disposed inside said second
substrate cavity(ies), said second substrate is coupled to said
first substrate, said one or more standoff substrate(s) is/are
coupled to said first substrate and/or said second substrate, said
one or more standoff substrate(s) completely encircles said first
substrate and/or said second substrate, said security component is
obfuscated by said first substrate and/or said second substrate
and/or said one or more standoff substrate(s) to minimize
tampering, said second component is coupled to said first substrate
or said second substrate, said second component is configured to
communicate with said security component, and said security
component and said second component are configured to communicate
security key(s) for performing device identification,
authentication, encryption, and/or device integrity
verification.
20. A system according to claim 19, wherein one of said plurality
of components is configured to perform tamper detection.
21. A system according to claim 19, wherein one of said plurality
of components disposed inside said cavity(ies) is a power (voltage)
regulator.
22. A system according to claim 19, wherein said the one standoff
substrate doesn't encircle said first substrate and/or said second
substrate.
23. A system according to claim 19, wherein said one or more
standoff substrate(s) are spaced apart.
24. A system according to claim 19, wherein said first substrate
and/or said second substrate comprises of one or more
cavity(ies).
25. A system according to claim 19, wherein said first substrate
and/or said second substrate and/or said standoff substrate(s)
comprises of anti-tamper Redistribution layer(s).
26. A system according to claim 19, wherein said first substrate
and/or said second substrate and/or said standoff substrate(s)
comprises of molding compound.
27. A system according to claim 19, wherein one of said plurality
of the components is a power management/regulator or security
sub-circuit or tamper detect circuit or router or switch or antenna
or radar or phased array or modem or baseband or transceiver or
mm-wave subsystem or silicon-on-insulator or amplifier or Field
Programmable Gate Array (FPGA) or capacitor or resistor or inductor
or processor or memory or sensor or analog-to-digital converter or
digital-to-analog converter or electrical-optical converter or
optical-electrical converter or Light Emitting Diode (LED) or
Application-Specific Integrated Circuit (ASIC) or Through-Silicon
Via (TSV) or laser or analog circuit or digital circuit or
Serializer/Deserializer (SerDes) or filter or Lens or Graphics
Processing Unit (GPU) or magnet or waveguide or wirebond or epoxy
mold compound (EMC) or under-fill material or heat-pipe or mirror
or fan or bump or fiber or accelerator/co-processor or processor
core or Microelectromechanical Systems (MEMS) or membrane or heat
spreader or energy source or sensing material or piezoelectric or
light source or touch screen or Liquid Crystal Display (LCD) or
organic light-emitting diode (OLED) or battery or Electromagnetic
Shield (EMI) coating.
28. A system according to claim 24, wherein said one or more
standoff substrate(s) is/are coupled to said one or more
cavity(ies) of said first substrate and/or said second
substrate.
29. A system according to claim 15, wherein said one or more
standoff substrate(s) is/are coupled to said one or more
cavity(ies) of said first substrate and/or said second
substrate.
30. A system according to claim 6, wherein said one or more
standoff substrate(s) is/are coupled to said substrate cavity(ies).
Description
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] The present application claims benefit and is a continuation
of application Ser. No. 16/724,319 filed on Dec. 22, 2019, the
content of which is incorporated herein by reference in its
entirety. Application Ser. No. 16/724,319 claims benefit and is a
continuation of application Ser. No. 15/810,050 filed on Nov. 11,
2017 (now U.S. Pat. No. 10,515,886 issued on Dec. 24, 2019), the
content of which is incorporated herein by reference in its
entirety, whereby Ser. No. 15/810,050 claims benefit and is a
continuation of application Ser. No. 14/746,045 filed on Jun. 22,
2015, the content of which is incorporated herein by reference in
its entirety, whereby application Ser. No. 14/746,045 claims
benefit and is a continuation-in-part of application Ser. No.
14/717,798 filed May 20, 2015, the content of which is incorporated
herein by reference in its entirety
[0002] The present application claims benefit and is a continuation
of allowed application Ser. No. 14/746,045 filed on Jun. 22, 2015
which claims benefit under 35 USC 119 (e) of U.S. Provisional
Application No. 62/015,459 filed Jun. 22, 2014 (now expired), the
content of which is incorporated herein by reference in its
entirety.
[0003] The present application claims benefit and is a continuation
of allowed application Ser. No. 14/746,045 filed on Jun. 22, 2015
which claims benefit and is a continuation-in-part of allowed
application Ser. No. 14/717,798 filed May 20, 2015 which claims
benefit under 35 USC 119 (e) of U.S. Provisional Application No.
62/002,794 filed May 24, 2014 (now expired), the content of which
is incorporated herein by reference in its entirety.
FIELD
[0004] The subject matter herein relates to packaging semiconductor
devices.
BACKGROUND
[0005] The packaging of electronic devices is becoming more
important as demands increase for miniaturization, speed, improved
reliability, weight reduction and security. A variety packages are
under development such as a die-scale package, at a wafer level;
and a die stack-type package. Die have been attached to an
interposer to mount the die onto a printed circuit board (PCB)
through an organic package substrate to translate the fine
geometries of the interposer to the much larger spacing of the
printed circuit board. An increasing number of conductive pads of
the printed circuit board must be coordinated with more bonding
pads on the semiconductor die to improve input/output (I/O)
throughput.
[0006] As Moore's law approaches its decrescendo and the cost per
transistor increases below the 22 nm node, device makers are
seeking alternative solutions to stay competitive. Semiconductor
device manufacturers have been relying on Multi-Chip-Module (MCM)
100 shown in FIGS. 1A and 1B. 2D monolithic dies (120, 130) are
integrated on an organic substrate 160 assembled on a Printed
Circuit Board (PCB) 110. 2D monolithic dies 120 may be flip chip
dies mechanically and electrically connected to organic substrate
160 by way of solder bumps 140. Alternatively, 2D monolithic dies
130 may be electrically connected to organic substrate 160 by way
of wirebonds 131. Ball Grid Array (BGA) 150 may be used to connect
organic substrate 160 to PCB 110. This approach results in a
relatively low yield due to the increase in substrate size which
causes mechanical stresses and other yield killing effects.
[0007] These shortcomings were partially addressed by moving to a
Package-on-Package (POP) architecture as shown in FIGS. 2A and 2B.
A Package-on-Package architecture may possess a vertical stacking
of one monolithic die 201 above a second monolithic die 202 in the
depicted manner. Monolithic die 201 and monolithic die 202 each
have their own organic substrate (231 and 232, respectively).
Monolithic die 201 is individually packaged on organic substrate
231 using solder balls 221 whereas monolithic die 202 is
individually packaged onto organic substrate 232 using solder balls
222. Clearance is provided for monolithic die 202 by incorporating
organic substrates 210 which may provide electrical connections
between organic substrate 231 and organic substrate 232 through
additional solder balls 220. Practical considerations (e.g.
reliability and maintaining a low profile) limit the number of
levels which can be implemented in this Package-on-Package
architecture. A perspective view is provided in FIG. 2B to help
visualize the completed package in three dimensions. The size of
the solder bumps may be increased and provide the clearance for
monolithic die 202 which does indeed lower the profile, however,
the technique also reduces the number of electrical connections
which may be made between organic substrate 231 and organic
substrate 232.
[0008] More recently, "2.5D" and "3D" integration techniques have
been developed to improve yield, profile and performance. 2.5D/3D
approaches may also increase the reuse of monolithic integrated
circuit ("chip") designs whose development costs have already been
amortized. Various chip designs (often referred to as IP) perhaps
from differing process nodes and perhaps from different foundries
can be integrated together to form a functional circuit device. In
a homogeneous 2.5D/3D integration approach, as illustrated in FIG.
3A, a single chip 300 is partitioned into number of smaller chips
(305, 310, 315, 320). Smaller chips (305, 310, 315, 320) are then
assembled onto interposer 325 and wired together to form an
electronic package. FIG. 3B shows a heterogeneous 2.5D/3D
integration approach. Single chip 330 includes a number of
circuitry blocks including memory 335, logic 340, DSP 345, and RF
350 manufactured separately and mounted on interposer 355 and wired
together to form an electronic package. Smaller chips (335, 340,
345, 350) may be manufactured by different foundries and may have
different process nodes selected for performance, availability
and/or cost reasons.
[0009] Hardware is needed which further increase the number of
transistors per device to improve processing performance and/or
lower the cost per transistor.
SUMMARY
[0010] Semiconductor packages are described which increase the
density of electronic components within. The semiconductor package
may incorporate interposers with cavities formed into the top
and/or bottom. The cavities may then be used as locations for the
electronic components. Alternatively, narrow spacer interposers may
be used to space apart standard more laterally elongated
interposers to form the indentations used to house the electronic
components. The height of the clearance is equal to the height of
the standoff interposers in embodiments. The semiconductor package
designs described herein may be used to reduce footprint, reduce
profile and increase electronic component and transistor density
for semiconductor products. The cavities and clearances may form a
conduit configured to promote fluid flow and enhance cooling of the
integrated circuits during operation in embodiments.
[0011] Embodiments disclosed herein pertain to electronic packages
including a substantially-planar first semiconductor interposer.
The first semiconductor interposer includes a first plurality of
through-substrate vias perpendicular to the major plane of the
first semiconductor interposer and passing through the entire
thickness of the first semiconductor interposer. Embodiments
further include a substantially-planar second semiconductor
interposer having a second major plane parallel to the first major
plane. The second semiconductor interposer includes a second
plurality of through-substrate vias perpendicular to the major
plane of the second semiconductor interposer and passing through
the entire thickness of the second semiconductor interposer.
Embodiments further include at least one standoff interposer
disposed between the first semiconductor interposer and the second
semiconductor interposer. The at least one standoff interposer is
affixed to each of the first semiconductor interposer and the
second semiconductor interposer. The at least one standoff
interposer forms a clearance between the first semiconductor
interposer and the second semiconductor interposer. The standoff
interposer includes an intervening plurality of through-substrate
vias passing through the entire thickness of the at least one
standoff interposer. A portion of the second plurality of
through-substrate vias are electrically connected to a portion of
the first through-substrate vias by way of a portion of the
intervening through-substrate vias. Embodiments further include at
least one electronic component disposed within the clearance and
electrically coupled to the first semiconductor interposer by a
first plurality of electrical connections.
[0012] Each of the first semiconductor interposer, the second
semiconductor interposer and the standoff interposer may be
crystalline silicon or single crystal silicon. The at least one
standoff interposer may include at least two standoff interposers
forming two parallel lines near two opposing edges of the first
semiconductor interposer. The clearance may be the region between
the two parallel lines and between the first semiconductor
interposer and the second semiconductor interposer. The at least
one standoff interposer may encircle the clearance resulting in no
pathways for fluid egress or ingress. In other words, the standoff
may go all the way around the perimeter of the interposers above
and below to increase security in embodiments. The at least one
standoff interposer may include at least nine standoff interposers
arranged in a regular grid pattern. A width of the standoff
interposer may be between 5% and 45% of a width of the interposer.
A height of the standoff interposer may be between 50 .mu.m and 300
.mu.m. Embodiments may further include a cloaking plurality of
through-substrate vias through the standoff interposer ground on
the outside of the intervening plurality of through-substrate vias.
A cloaking linear density of the cloaking plurality of
through-substrate vias may exceed the intervening linear density of
the intervening plurality of through-substrate vias.
[0013] Embodiments disclosed herein pertain to electronic packages
including a substantially-planar first semiconductor interposer
having a rectilinear cavity formed into one or more of a top
surface of the first semiconductor interposer or the bottom surface
of the first semiconductor interposer when the first major plane of
the first semiconductor interposer is positioned horizontally. The
first semiconductor interposer includes a first plurality of
through-substrate vias perpendicular to the major plane of the
first semiconductor interposer and passing through the entire
thickness of the first semiconductor interposer. The first
through-substrate vias are disposed outside the rectilinear cavity.
Embodiments further include a substantially-planar second
semiconductor interposer having a second major plane parallel to
the first major plane. The second semiconductor interposer includes
a second plurality of through-substrate vias perpendicular to the
major plane of the second semiconductor interposer and passing
through the entire thickness of the second semiconductor
interposer. A portion of the second plurality of through-substrate
vias are electrically connected to a portion of the first plurality
of through-substrate vias. Embodiments further include at least one
electronic component disposed entirely within the rectilinear
cavity and electrically coupled to the first semiconductor
interposer by a first plurality of electrical connections within
the rectilinear cavity.
[0014] At least one electronic component may include at least one
monolithic integrated circuit. Each of the first semiconductor
interposer and the second semiconductor interposer may be silicon
interposers. A width of the rectilinear cavity may be between 10%
and 90% of the width of the first semiconductor interposer. The
widths of the first semiconductor interposer and the second
semiconductor interposer may be essentially the same. A depth of
the rectilinear cavity may be between 50 .mu.m and 300 .mu.m.
[0015] Embodiments disclosed herein pertain to electronic packages
including a substantially-planar first semiconductor interposer.
The first semiconductor interposer includes a first plurality of
electrical connections generally perpendicular to the major plane
of the first semiconductor interposer and passing through the
thickness of the first semiconductor interposer. Embodiments
further include a substantially-planar second semiconductor
interposer having a second major plane parallel to the first major
plane. The second semiconductor interposer includes a second
plurality of electrical connections generally perpendicular to the
major plane of the second semiconductor interposer and passing
through the thickness of the second semiconductor interposer. A
portion of the second plurality of electrical connections are
electrically connected to a portion of the first plurality of
electrical connections. A first space is disposed between the first
semiconductor interposer and the second semiconductor interposer.
Embodiments further include a substantially-planar third interposer
having a third major plane parallel to the first major plane. A
second space is disposed between the third interposer and the
second semiconductor interposer. Embodiments further include at
least one first electronic component disposed between the first
semiconductor interposer and the second semiconductor
interposer.
[0016] The first space may include a cavity. The first space may
include a clearance between two or more standoff interposers. The
first space may be configured to pass a cooling fluid to keep an
operating temperature of the at least one first electronic
component below a threshold value. The at least one first
electronic component may be encapsulated within a molding compound
filling the remainder of the first space. All electrical
connections between the first semiconductor interposer and the
second semiconductor interposer may be direct ohmic contacts. The
third interposer may have no electrical connections on top as a
security measure. The portion of the first plurality of electrical
connections and the portion of the second plurality of electrical
connections are essentially directly electrically connected to one
another with no intervening interposer. The portion of the first
plurality of electrical connections and the portion of the second
plurality of electrical connections are electrically connected by
way of one or more standoff interposer. The third semiconductor
interposer may include a third plurality of electrical connections
generally perpendicular to the major plane of the third
semiconductor interposer and passing through the thickness of the
third semiconductor interposer. A portion of the third plurality of
electrical connections are electrically connected to a portion of
the second plurality of electrical connections. Embodiments may
further include a sensor affixed to the top of the third
semiconductor interposer and electrically connected to a portion of
the third plurality of electrical connections. At least one of the
at least one first electronic component and at least one of the at
least one second electronic component may be a monolithic
integrated circuit, a passive electronic component, an antenna, a
sensor, or a power source. The third interposer may be a cap having
no electronic connections on top. Embodiments may further include
at least one second electronic component disposed between the
semiconductor interposer and the third interposer. At least two of
the at least one first electronic component may be keyed such that
two of the electronic components will only operate properly when
both are present.
[0017] Additional embodiments and features are set forth in part in
the description that follows, and in part will become apparent to
those skilled in the art upon examination of the specification or
may be learned by the practice of the disclosed embodiments. The
features and advantages of the disclosed embodiments may be
realized and attained by means of the instrumentalities,
combinations, and methods described in the specification.
DESCRIPTION OF THE DRAWINGS
[0018] A further understanding of the nature and advantages of the
embodiments may be realized by reference to the remaining portions
of the specification and the drawings.
[0019] FIG. 1A is a side-view schematic of a Multi-Chip-Module
package according to the prior art.
[0020] FIG. 1B is a top-view schematic of a Multi-Chip Module
package according to the prior art.
[0021] FIG. 2A is a side-view schematic of a Package-on-Package
architecture according to the prior art.
[0022] FIG. 2B is a perspective-view schematic of a
Package-on-Package architecture according to the prior art.
[0023] FIG. 3A is a top-view schematic of homogeneous partitioning
according to the prior art.
[0024] FIG. 3B is a top-view schematic of heterogeneous
partitioning according to the prior art.
[0025] FIGS. 4A, 4B and 4C are side-view schematics of interposers
during the formation of cavities according to embodiments.
[0026] FIGS. 5A and 5B are side-view schematics of portions of
semiconductor packages with electronic components positioned in
cavities according to embodiments.
[0027] FIGS. 6A and 6B are side-view schematics of portions of
semiconductor packages with electronic components positioned in a
clearance created by standoff interposers according to
embodiments.
[0028] FIG. 6C is a perspective view of a portion of a
semiconductor package with electronic components positioned in a
clearance created by standoff interposers according to
embodiments.
[0029] FIGS. 7A and 7B are side view schematics of portions of
semiconductor packages with electronic components positioned in
clearance formed by a combination of standoff interposers and a
cavity according to embodiments.
[0030] FIG. 8A is a side view schematic of a portion of a
semiconductor package with electronic components positioned in
multiple stacked cavities according to embodiments.
[0031] FIG. 8B is a side view schematic of a portion of a
semiconductor package with electronic components positioned in
cavities on both sides of a single interposer according to
embodiments.
[0032] FIG. 9A is a side-view schematic of a portion of a
semiconductor package with electronic components positioned in
clearances created by standoff interposers according to
embodiments.
[0033] FIG. 9B is a perspective view of a portion of a
semiconductor package with electronic components positioned in
clearances created by standoff interposers according to
embodiments.
[0034] FIG. 10A is a side-view schematic of a portion of a
semiconductor package with electronic components positioned in
clearances created by standoff interposers according to
embodiments.
[0035] FIG. 10B is a perspective view of a portion of a
semiconductor package with electronic components positioned in
clearances created by standoff interposers according to
embodiments.
[0036] FIGS. 11A and 11B are side-view schematics of portions of
semiconductor packages with electronic components positioned in
clearances created by standoff interposers according to
embodiments.
[0037] FIG. 12A is a side-view schematic of a portion of a
semiconductor package with electronic components positioned in
clearances created by standoff interposers according to
embodiments.
[0038] FIG. 12B is a perspective view of a portion of a
semiconductor package with electronic components positioned in
clearances created by standoff interposers according to
embodiments.
[0039] FIGS. 13A and 13B are top-view schematics of portions of
semiconductor packages with electronic components positioned in
clearances created by standoff interposers according to
embodiments.
[0040] FIG. 14 is a top-view schematic of a portion of a
semiconductor package with electronic components positioned in
clearances created by standoff interposers according to
embodiments.
[0041] FIG. 15 is a top-view schematic of a portion of a standoff
interposer according to embodiments.
[0042] FIGS. 16A, 16B, 16C and 16D are top-view schematics of
portions of semiconductor packages according to embodiments.
[0043] FIG. 17 is a side view schematic of a portion of a
semiconductor package with keyed electronic components positioned
within a clearance according to embodiments.
[0044] FIGS. 18A and 18B are side-view schematics of portions of
semiconductor packages with electronic components positioned in
clearances created by standoff interposers according to
embodiments.
[0045] FIG. 19 is a perspective view of a portion of a
semiconductor package according to embodiments.
[0046] FIG. 20 is a perspective view of a portion of a
semiconductor package according to embodiments.
[0047] In the appended figures, similar components and/or features
may have the same reference label. Further, various components of
the same type may be distinguished by following the reference label
by a dash and a second label that distinguishes among the similar
components. If only the first reference label is used in the
specification, the description is applicable to any one of the
similar components having the same first reference label
irrespective of the second reference label.
DETAILED DESCRIPTION
[0048] Semiconductor packages are described which increase the
density of electronic components within. The semiconductor package
may incorporate interposers with cavities formed into the top
and/or bottom. The cavities may then be used as locations for the
electronic components. Alternatively, narrow spacer interposers may
be used to space apart standard more laterally elongated
interposers to form the indentations used to house the electronic
components. The height of the clearance is equal to the height of
the standoff interposers in embodiments. The semiconductor package
designs described herein may be used to reduce footprint, reduce
profile and increase electronic component and transistor density
for semiconductor products. The cavities and clearances may form a
conduit configured to promote fluid flow and enhance cooling of the
electronic components during operation in embodiments.
[0049] The semiconductor packages described herein possess cavities
and/or standoff interposers to create spaces for a plurality of
electronic components in a high density and high performance
configuration. In embodiments, the semiconductor packages described
may result in a smaller footprint, lower profile, miniaturized,
higher performance, and thermally enhanced, and more secure
packages. The packages may involve a combination of interposers,
redistribution layers (RDL), through-substrate vias (TSV),
so-called "zero-ohm" links, copper pillars, solder bumps,
compression bonding, and bumpless packaging. In addition to these
techniques, cavities may be made into the interposer and/or
standoff interposers may be used to provide spaces (clearance) for
a plurality of electronic components (e.g. passives, antennas,
integrated circuits or chips) in embodiments. The standoff
interposers may include redistribution layers on the top and/or
bottom while a through-substrate via passes vertically through the
standoff interposer. Standoff interposers may be formed, for
example, by bonding multiple interposers together by
thermocompression bonding or another low-profile connection
technique. Oxide bonding techniques or laterally shifting any
standoff interposer described herein enable wirebonds to be used to
connect the standoff interposer to a printed circuit board, a
substrate, or an underlying interposer in embodiments. Generally
speaking, any interposer described herein may be shifted relative
to the other interposers in the stack to allow the formation of
wirebonds. The semiconductor interposer may be a silicon interposer
according to embodiments.
[0050] Electronic packages formed in the manner described herein
possess improved reliability, lower cost, and higher performance
due to a shortening of electrical distance and an increase in
density of integrated circuit mounting locations. Reliability may
be improved for embodiments which use the same semiconductor (e.g.
silicon) for all interposers used to form the semiconductor
package. The techniques presented also provide improvement in
solder joint reliability and a reduction in warpage. Warping may
occur during the wafer processing and thinning of the semiconductor
interposer. The second opportunity for warping occurs during the
packaging and assembly. The chance of warping increases for larger
interposer lengths and package dimensions which is currently
necessary for a variety of 2.5D/3D integration applications (e.g.
networking). The vertical density of integrated circuits may be
increased which allows the horizontal area to be reduced to achieve
the same performance.
[0051] FIG. 4A, 4B and 4C are side-view schematics of interposers
during the formation of cavities according to embodiments. An
interposer 400-1 is shown in FIG. 4A prior to forming any cavities
for electronic components. FIG. 4B shows an interposer 400-2 having
a top cavity 410 as well as a bottom cavity 420. FIG. 4C shows an
interposer 400-3 having four cavities (430, 440, 450, 460) formed
into its top and bottom surfaces. The dotted lines define the
extent of the cavity in the direction of the opening for the
purposes of determining whether a die is within the cavity or
entirely within the cavity herein.
[0052] When describing all embodiments herein, "Top" and "Up" will
be used herein to describe portions/directions perpendicularly
distal from the printed circuit board (PCB) plane and further away
from the center of mass of the PCB in the perpendicular direction.
"Vertical" will be used to describe items aligned in the "Up"
direction towards the "Top". Other similar terms may be used whose
meanings will now be clear. "Major planes" of objects will be
defined as the plane which intersects the largest area of an object
such as an interposer. Some standoff interposers may be "aligned"
in "lines" along the longest of the three dimensions and may
therefore be referred to as "linear" standoff interposers.
Electrical connections may be made between interposers (standoff or
planar interposer) and the pitch of the electrical connections may
be between 1 .mu.m and 150 .mu.m or between 10 .mu.m and 100 .mu.m
in all embodiments described herein. Electrical connections between
neighboring semiconductor interposers herein may be direct ohmic
contacts which may include direct bonding/oxide bonding or adding a
small amount of metal such as a pad between, for example, through
silicon vias.
[0053] FIG. 5A and 5B are side-view schematics of interposers with
electronic components positioned in cavities according to
embodiments. Following the formation of cavities in interposer 500,
four electronic components (dies 510, 515, 520, 525) are then
assembled within the cavities using a variety of electrical
connection methods (e.g. copper pillar or micro bumps). A plurality
of dies are placed within or entirely within a cavity of an
interposer in embodiments. Interposer 500 is then electrically and
mechanically attached to printed circuit board 530 using solder
balls 540. Multiple interposers having dies placed in cavities may
be stacked vertically and electrically/mechanically attached to a
printed circuit board, according to embodiments, as further shown
in FIG. 5B.
[0054] FIGS. 6A, 6B and 6C are side-view and perspective view
schematics of interposers with electronic components positioned in
a clearance created by standoff interposers according to
embodiments. No cavity is created in interposer 630, however,
clearance for die is provided by standoff interposers 600. Silicon
cap 650 may be used to create a confined channel for fluid flow.
Silicon cap 650 may include a redistribution layer on the bottom
for routing electrical signals in the completed semiconductor
package which is shown assembled in FIG. 6B. Silicon cap 650 (or a
cap more generally) may include passive components or active
components in embodiments. Silicon cap 650 may have no electrical
connections on the top, according to embodiments, to increase
security and to provide protection against probing by electrical
taps. Alternatively, silicon cap 650 may be replaced by an
interposer with through-connections such as through-substrate vias
in embodiments. All elements of the package depicted in FIG. 6A can
be manufactured separately and may have bonding pads (610, 620,
640) included for electrical connections in the assembled
configuration of FIG. 6B. Thermocompression bonding or low
temperature bonding method may be used to fuse all the elements
together according to embodiments. The perspective view of FIG. 6C
shows the assembled device with silicon cap 650 removed to allow
viewing of some 3-d aspects of the semiconductor package. Standoff
interposers 600 may be linearly parallel to one another as shown
and may be positioned near two edges of interposer 630 to create a
path for fluid or air flow in embodiments. Standoff interposers,
interposers and caps may all be formed from the same semiconducting
material (e.g. silicon), in embodiments, to match the coefficients
of thermal expansion and reduce application of repetitive
stresses.
[0055] The dimensions of interposers and standoff interposers
described herein vary widely. Interposers may be as large as a full
wafer, e.g. hundreds of millimeters across. Interposers may be as
small as several millimeters across (e.g. 5 mm.times.5 mm). The
interposers may be asymmetric as well for certain applications.
Cavities may vary in dimensions as well and may depend on the size
of the electronic component (e.g. a monolithic integrated circuit)
ultimately placed within the cavity as well as the number of
connections across the interposer outside the cavity (where the
interposer-interposer direct connection is made). Cavity widths may
be between 10% and 90%, 20% to 70% or 20% to 40% of the width of
the interposer itself according to embodiments. Correspondingly,
standoff interposer widths may be between 5% and 45%, between 15%
and 40% or between 30% and 40% of the width of the interposer in
embodiments. Cavity depths may be between 50 .mu.m and 300 .mu.m,
between 75 .mu.m and 250 .mu.m or between 100 .mu.m and 200 .mu.m
according to embodiments. Correspondingly, standoff interposer
heights may be between 25 .mu.m and 1,000 .mu.m, between 50 .mu.m
and 300 .mu.m, between 75 .mu.m and 250 .mu.m or between 100 .mu.m
and 200 .mu.m according to embodiments. These dimensions apply to
all embodiments described herein.
[0056] FIG. 7A and 7B are side view schematics of interposers with
electronic components positioned in clearance formed by a
combination of standoff interposers and a cavity according to
embodiments. A cavity 700 is formed on the top side of silicon
interposer 710. Electrical components are then electrically and
mechanically attached to silicon interposer 710 and attachment may
occur prior to assembly in embodiments. The electrical components
in the example include two (e.g. monolithic) integrated circuits
760 and 770. The electrical components may be entirely within
cavity 700 according to embodiments (as with all components and
cavities described herein). A silicon cap 740 is also formed and
electrical components may be electrically and mechanically attached
to the underside of silicon cap 740 in embodiments. FIG. 7B shows
an integrated circuit 783, a passive electrical component 781 and
an antenna 782. Electronic components will be used herein to
describe integrated circuits or other active component, a passive
electrical component such as an inductor, an antenna or a power
source such as a battery according to embodiments. Integrated
circuits may be used to refer to monolithic integrated circuits in
embodiments. Standoff interposers 720 (which may be silicon as with
all interposers herein) are also formed and used to attach a cap
740 to interposer 710 (each of which may also be silicon in all
examples herein) and also to leave an additional clearance for the
additional electronic components (783, 781 and 782). Standoff
interposers 720 may also provide high density electrical routing
and connectivity between interposer 710 and cap 740. Again, cap 740
may be included to improve security (as with all embodiments
described herein) and also to confine a fluid flow channel to
increase the speed and concentration of the coolant flow. The
height of the cavity and/or the height of the silicon stand-off
help determine the cooling effectiveness and may be selected based
on thermal management considerations.
[0057] FIG. 8A is a side view schematic of a portion of a
semiconductor package with electronic components positioned in
multiple stacked cavities according to embodiments. FIG. 8A shows
an embodiment where no silicon standoffs are used but electronic
components 830 (e.g. monolithic integrated circuits) are placed
among a plurality of vertically arranged cavities in a stack of
interposers 810. Thermocompression or low temperature bonding may
be used to bond interposers 810 directly together for enhanced
miniaturization and to form a low profile package. In all
embodiments herein, the clearances and/or cavities may or may not
be filled with molding compound. All sides of the semiconductor
packages described herein may be closed to enhance security
especially in cases where the design does not require a coolant
fluid (e.g. air) to be flowed through the channel to cool the (e.g.
monolithic) integrated circuits.
[0058] FIG. 8B is a side view schematic of a portion of a
semiconductor package with electronic components positioned in
cavities on both sides of a single interposer according to
embodiments. Standoff interposers 820 are also present to create a
clearance between interposer 810-5 and interposer 810-6. Note that
the top interposers (810-4 and 810-6) may also be caps or silicon
caps as before in embodiments. Electronic components 830 of FIG. 8B
may be located entirely within cavities made in an interposer as
shown. The cavities are defined as stopping at the top or bottom
plane of the interposer (e.g. the dotted line) and the clearance
begins at the dotted line and continues to the top or bottom
surface of the nearest neighboring interposer. In other words, the
clearance is defined by the height of standoff interposers 820.
Electronic components may be placed partially or wholly inside a
cavity, not only to increase packing density, but also to make
electronic probing of the electrical connections (e.g. ball grid
arrays) on the underside of the electronic components according to
embodiments.
[0059] FIGS. 9A and 9B are a side-view schematic and a perspective
view of a portion of a semiconductor package with electrical
components 930 positioned in clearances created by standoff
interposers 920 according to embodiments. Components may be
assembled using direct thermocompression or low temperature bonding
methods on an interposer 910 without a cavity in embodiments. FIGS.
9A and 9B illustrate an example of a very low profile semiconductor
package in which there is little or no gap on the side of the
electrical component 930 opposite from the electrical and
mechanical attachment according to embodiments. The height of the
standoff interposers 920 may be the same or within 5% of the height
of the electrical components 930 located on the same level in
embodiments. The front and back of the semiconductor package (FIGS.
9A-9B) may still be left open to allow some small amount of cooling
fluid flow.
[0060] FIGS. 10A and 10B are a side-view schematic and a
perspective view of a portion of a semiconductor package with
electrical components 1030 positioned in clearances created by
standoff interposers 1020 according to embodiments. Components may
be assembled using direct thermocompression or low temperature
bonding methods on an interposer 1010 without a cavity in
embodiments. Alternatively, solder balls may be used when the
clearance is adequate according to embodiments. FIGS. 10A and 10B
illustrate an example of a high electric component density
semiconductor package in which there are electronic components 1030
near the top and bottom a clearance created by standoff interposers
1020 between interposers 1010 in embodiments. In applications where
thermal generation is more significant, thicker standoff
interposers may be used to create adequate passage for fluid flow
according to embodiments. The height of the standoff interposers
1020 may be greater than twice the height of electronic components
1030 or greater than thrice the height of electronic components
1030 in embodiments. As with all embodiments described herein, the
front and back of the semiconductor package (FIGS. 10A-10B) may be
left open to allow some small amount of cooling fluid flow or else
the remaining clearance may be filled with molding compound to
encapsulate the electronic components 1030 according to
embodiments.
[0061] FIGS. 11A and 11B are side-view schematics of portions of
semiconductor packages with electronic components positioned in
clearances created by standoff interposers according to
embodiments. Embodiments implementing solder bumps in place of
thermocompression or low temperature bonding are shown. A cap (e.g.
an interposer cap or a silicon cap) may be incorporated at the top
of the stack to increase security of the completed semiconductor
package in embodiments. As with all embodiments described herein,
electronic components may be assembled on interposers using solder
bumps or copper pillars according to embodiments. The underside of
the caps may be configured with redistribution layers but no
connections may be present on the top or through the caps in
embodiments. A semiconductor interposer right below the cap (e.g.
the silicon cap in FIG. 11B) may provide additional routing
channels on the top for routing signals or power according to
embodiments. The cap on the top may contain one or more antennas to
allow package-to-package or stack-to-stack wireless communication
in embodiments. FIGS. 12A and 12B are side-view schematics of
portions of semiconductor packages showing a standoff interposer
between two other standoff interposers. Complex scalable systems
may be formed using multiple standoff interposers placed at various
intervals to allow high bandwidth chip-to-chip communication in
embodiments. Three or more standoff interposers may be implemented
to provide additional structure to a semiconductor package
according to embodiments.
[0062] FIGS. 13A and 13B are top-view schematics of portions of
semiconductor packages with electronic components positioned in
clearances created by standoff interposers according to
embodiments. Shown are interposer 1310, electronic component 1330,
standoff interposer 1320, a battery and a storage register.
Standoff interposer 1320-1 may encircle electronic components or
standoff interposer 1320-2 may not encircle electronic components
(which allows an air channel for example) in embodiments. Security
may be increased by reducing or eliminating access to electrical
signals within a semiconductor package in embodiments. An energy
source (e.g. a battery) may be included, according to embodiments,
to allow continued operation of electronic components for a period
of time when power is interrupted. During this period of time,
stored code may be executed which completes an operation such as a
transfer, cleans up (e.g. zeros storage locations), scrambles
and/or encrypts the data present in various memory locations in or
near an integrated circuit (e.g. the storage register). The energy
source is shown inside the package in FIGS. 13A and 13B but may be
located outside or completely off the semiconductor package in
embodiments.
[0063] FIG. 14 is a top-view schematic of a portion of a
semiconductor package with electronic components positioned in
clearances created by standoff interposers according to
embodiments. The standoff interposer shown in FIG. 14 encircles
electronic components as was the case for standoff interposer
1320-1 in FIG. 13A to increase security by making signals more
difficult to tap into during operation in the field. Signal vias
(1401, 1450) pass through the standoff interposer and expanded
views are included as a visual convenience. Dummy vias (1410, 1420,
1430, 1440, 1460, 1470) may be included to obscure electromagnetic
signals which may otherwise be read, e.g. outside the semiconductor
package, according to embodiments. Two columns of dummy vias (1410,
1420) are included outside of signal vias 1401. The example
involves dummy vias but dummy vias may also be replaced by power
supply vias which then serve two purposes in embodiments. According
to alternative embodiments, power supply vias may be protected by
dummy vias since sensitive signals may sometimes ride on the power
supply voltage. All vias which are helpful in shielding or
obscuring sensitive signals may be referred to as signal-blocking
vias. Two columns of dummy vias are shown outside (1430, 1440) and
inside (1460, 1470) the signal vias 1450. The dummy vias may simply
obscure an electromagnetic signal outside the semiconductor package
or may conduct dummy/gibberish electrical signals intentionally
included to further obscure the electromagnetic signal from signal
vias (1401, 1450) or from power supplies in some cases. One column
of dummy vias may be included on the outside or inside of a column
of signal vias in embodiments. One column of dummy vias may be
included on the outside and inside of a column of signal vias
according to embodiments. Two or more columns of dummy vias may be
included on the outside or inside of a column of signal vias in
embodiments. The two (or more) columns of dummy vias may be
staggered (as shown e.g. with dummy vias 1410 and 1420) to further
avoid having meaningful electromagnetic signals pass to the outside
of a semiconductor package according to embodiments. Generally
speaking, a variety of signal transmission items may be used beyond
the exemplary vias (1401, 1450). The signal transmission items may,
for example, be vias, solder bumps or pads in embodiments.
[0064] FIG. 15 is a top-view schematic of a portion of a standoff
interposer according to embodiments. Signal vias 1501 (or power
vias in embodiments) may be shielded on the outside, the inside or
both sides by a column of signal-blocking vias (e.g. ground supply,
power supply or dummy vias 1510) according to embodiments. The
column of signal-blocking vias 1510 (also referred to herein as
cloaking vias) may be more closely spaced together compared to
signal vias 1501 (or power vias in embodiments) to increase the
security by discouraging propagation of electromagnetic signals
outside a semiconductor package in embodiments.
[0065] FIGS. 16A, 16B, 16C and 16D are top-view schematics of
portions of semiconductor packages according to embodiments. To
further minimize or eliminate tampering with the package from top
and bottoms sides a series of mesh is created to mask the signal
traces on layer below. In embodiments, ground mesh 1610-1 is
created on a layer (e.g. layer one in the figure) with power mesh
1601-1 created in staggered position with respect to layer one on a
separate layer (e.g. layer two). The presence of ground mesh
1610-1, a dummy mesh (not shown) and/or power mesh 1601-1 may mask
signal traces 1620 (and power traces in embodiments) routed on
layer three increasing privacy and security. Ground mesh 1610-2 and
power mesh 1601-2 may both be present on a single layer or each of
multiple layers in embodiments. FIG. 16D shows power mesh 1601-2
and ground mesh 1610-2 on each of layer one and layer two to thwart
attempts to tap the electromagnetic signals formed by signal traces
1620. These techniques may also be used inside or on the integrated
circuits to improve security as well.
[0066] FIG. 17 is a side view schematic of a portion of a
semiconductor package with keyed electronic components positioned
within a clearance according to embodiments. A security code/master
key may be stored inside integrated circuit 1701 in embodiments
such that only select additional chips (also storing the
corresponding key) may operate properly when present in the same
semiconductor package. Integrated circuits (1710, 1720, 1730) are
equipped with the proper security code in the example. According to
embodiments, some or all keyed integrated circuits may be located
within a clearance as shown, or located in a cavity according to
embodiments. One or a plurality of integrated circuits may have the
matching code to select the difficulty associated with a potential
counterfeiting operation.
[0067] Electronic packages described herein may include
high-performance miniature scalable and secure processing units
equipped with a variety of integrated circuit types. A plurality of
processors may be mounted on one side of an interposer while a
plurality of memory dies may be mounted on the opposite side in
embodiments. Processor cores may be mounted on one side of an
interposer while memory is mounted on the opposite side according
to embodiments. Processor cores and memory dies may be interspersed
on both sides of an interposer in embodiments. According to
embodiments, processor cores and memory dies may be both present on
each side of an interposer but segregated into homogeneous
integrated circuit groups. A homogeneous group of processor cores
may be separated from a homogeneous group of memory dies by a
standoff interposer in embodiments.
[0068] FIGS. 18A and 18B are side-view schematics of portions of
semiconductor packages with electronic components positioned in
clearances created by standoff interposers according to
embodiments. Semiconductor packaged described herein may be
scalable heterogeneous units for interne-of-things (IOT)
applications. A plurality of sensors may be place on one side of
the interposer while an analog-to-digital convertor maybe placed on
the opposite side or same side as the sensors. Processors and
memory units may be placed in the lower stacks of the semiconductor
package. A cap (e.g. a silicon cap) may be used, in embodiments, in
situations where the presence of a silicon cap may not interfere
with the operation of the sensors (see FIG. 18A). Sensors may be
placed on top of an uppermost interposer (FIG. 18B) to facilitate
access of the sensors to environmental conditions.
[0069] Semiconductor packages described herein may include
heterogeneous or homogeneous memory units in embodiments. Memory
dies may be placed on one side or both sides interposers while high
bandwidth standoff interposers may be used with bumps or
compression bonding attachments method. Dimensions of the high
bandwidth standoff interposers may be selected to manage heat
generated during the operation of the electronic components (memory
in this case).
[0070] FIG. 19 and FIG. 20 are perspective views of portions of
semiconductor packages according to embodiments. Previous examples
showed standoff interposers in the form of walls aligned in the
same direction, in part, to guide airflow and promote cooling in
embodiments. Standoff interposers may also be more discrete
elements positioned at regular intervals in a two-dimensional array
(FIG. 19) according to embodiments. FIG. 20 shows a more irregular
distribution of standoff interposers still positioned discretely
across the two-dimensional surface of an interposer. The
distribution may be random in embodiments. Generally speaking,
standoff interposers may be of any size or shape and may be located
anywhere on the substrate to provide high speed and/or high
bandwidth local connections among nearby electronic components
(e.g. die as shown).
[0071] Semiconductor packages and devices formed according to the
designs described herein may be used to form higher performance,
cooler, more secure and tamper resistant, and more scalable 2.5D/3D
heterogeneous systems than prior art designs.
[0072] Having disclosed several embodiments, it will be recognized
by those of skill in the art that various modifications,
alternative constructions, and equivalents may be used without
departing from the spirit of the disclosed embodiments.
Additionally, a number of well-known processes and elements have
not been described to avoid unnecessarily obscuring the embodiments
described herein. Accordingly, the above description should not be
taken as limiting the scope of the claims.
[0073] Where a range of values is provided, it is understood that
each intervening value, to the tenth of the unit of the lower limit
unless the context clearly dictates otherwise, between the upper
and lower limits of that range is also specifically disclosed. Each
smaller range between any stated value or intervening value in a
stated range and any other stated or intervening value in that
stated range is encompassed. The upper and lower limits of these
smaller ranges may independently be included or excluded in the
range, and each range where either, neither or both limits are
included in the smaller ranges is also encompassed within the
embodiments described, subject to any specifically excluded limit
in the stated range. Where the stated range includes one or both of
the limits, ranges excluding either or both of those included
limits are also included.
[0074] As used herein and in the appended claims, the singular
forms "a", "an", and "the" include plural referents unless the
context clearly dictates otherwise. Thus, for example, reference to
"a process" includes a plurality of such processes and reference to
"the dielectric material" includes reference to one or more
dielectric materials and equivalents thereof known to those skilled
in the art, and so forth.
[0075] Also, the words "comprise," "comprising," "include,"
"including," and "includes" when used in this specification and in
the following claims are intended to specify the presence of stated
features, integers, components, or steps, but they do not preclude
the presence or addition of one or more other features, integers,
components, steps, acts, or groups.
* * * * *