U.S. patent application number 17/108830 was filed with the patent office on 2021-06-03 for microelectronic device and method for manufacturing such a device.
This patent application is currently assigned to STMicroelectronics (Rousset) SAS. The applicant listed for this patent is STMicroelectronics (Rousset) SAS. Invention is credited to Romeric GAY, Abderrezak MARZAKI.
Application Number | 20210167062 17/108830 |
Document ID | / |
Family ID | 1000005291128 |
Filed Date | 2021-06-03 |
United States Patent
Application |
20210167062 |
Kind Code |
A1 |
GAY; Romeric ; et
al. |
June 3, 2021 |
MICROELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SUCH A
DEVICE
Abstract
A device includes a MOS transistor and a bipolar transistor at a
same first portion of a substrate. The first portion includes a
first well doped with a first type forming the channel of the MOS
transistor and two first regions doped with a second type opposite
to the first type that are arranged in the first well which form
the source and drain of the MOS transistor. The first portion
further includes: a second well doped with the second type that is
arranged laterally with respect to the first well to form the base
of the bipolar transistor; a second region doped with the first
type that is arranged in the second well to form the emitter of the
bipolar transistor; and a third region doped with the first type
that is arranged under the second well to form the collector of the
bipolar transistor.
Inventors: |
GAY; Romeric;
(Aix-en-Provence, FR) ; MARZAKI; Abderrezak; (Aix
en Provence, FR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STMicroelectronics (Rousset) SAS |
Rousset |
|
FR |
|
|
Assignee: |
STMicroelectronics (Rousset)
SAS
Rousset
FR
|
Family ID: |
1000005291128 |
Appl. No.: |
17/108830 |
Filed: |
December 1, 2020 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/8249 20130101;
H01L 27/0623 20130101 |
International
Class: |
H01L 27/06 20060101
H01L027/06; H01L 21/8249 20060101 H01L021/8249 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 2, 2019 |
FR |
1913605 |
Claims
1. A microelectronic device, comprising: a substrate; a
high-voltage MOS transistor in and/or on a first portion of said
substrate; and a bipolar transistor in and/or on the same first
portion of said substrate; wherein said first portion comprises: a
first well doped with a first type that is electrically insulated
from the substrate and configured to form a channel of the
high-voltage MOS transistor; two first regions doped with a second
type opposite to the first type that are arranged in the first well
and configured to form, respectively, a source and a drain of the
high-voltage MOS transistor; a second well doped with the second
type that is arranged laterally with respect to the first well to
form a base of the bipolar transistor; a second region doped with
the first type that is arranged in the second well to form an
emitter of the bipolar transistor; and a third region doped with
the first type that is arranged under and in contact with the
second well to form a collector of the bipolar transistor.
2. The device according to claim 1, wherein said first portion
further comprises: a fourth region doped with the second type that
is arranged in the second well laterally with respect to the second
region, said fourth region configured to form an electrical contact
plug for the base of the bipolar transistor; and an insulation
region in the second well that laterally separates the fourth
region from the second region.
3. The device according to claim 2, wherein the insulation region
is a shallow trench isolation having a depth that is deeper than a
depth of the second region and deeper than a depth of the fourth
region.
4. The device according to claim 2, wherein said first portion
further comprises: a third well doped with the first type that is
arranged at a periphery of the second well and in electrical
contact with the third region; and a fifth region doped with the
first type that is arranged in the third well; wherein said fifth
region and said third well are configured to form together an
electrical contact plug for the collector of the bipolar
transistor; and a further insulation region in the second well that
laterally separates the third well and the fifth region from the
fourth region.
5. The device according to claim 4, wherein the further insulation
region is a shallow trench isolation having a depth that is deeper
than a depth of the fifth region and deeper than a depth of the
fourth region.
6. The device according to claim 1, further comprising a
low-voltage MOS transistor in a second portion of the substrate
that is different from the first portion.
7. The device according to claim 6, wherein the second portion
comprises: a fourth well doped with the first type that is
electrically insulated from the substrate and configured to form a
channel of the low-voltage MOS transistor; and two sixth regions
doped with the second type that are arranged in the fourth well and
configured to form, respectively, a source and a drain of the
low-voltage MOS transistor; wherein a doping of the first and
second wells of the first portion is lower than a doping of the
fourth well of the second portion.
8. The device according to claim 1, wherein the bipolar transistor
is of the NPN-type with the first doping type being an N-type
doping and the second doping type being a P-type doping; and
wherein the third region is an insulation well that is arranged
between the first and second wells and the substrate.
9. The device according to claim 1, wherein the bipolar transistor
is of the PNP-type with the first doping type being a P-type doping
and the second doping type being an N-type doping; and wherein the
third region is a region of the substrate that is arranged under
the second well.
10. A method for manufacturing a microelectronic device comprising
a high-voltage MOS transistor and a bipolar transistor formed in a
same first portion of a substrate, said method comprising the
following steps: (a) forming trenches in the substrate so as to
define first and second active areas in the first portion; (b)
forming a first well doped with a first type in the first active
area and a second well doped with a second type opposite to the
first type in the second active area, wherein the first well forms
a channel of the high-voltage MOS transistor and the second well
forms a base of the bipolar transistor; (c) forming two first
regions doped with the second type that are arranged in the first
well, wherein the two first regions form a source and a drain of
the high-voltage MOS transistor; (d) forming a second region doped
with the first type that is arranged on the second well, wherein
the second region forms an emitter of the bipolar transistor; and
(e) forming a third region doped with the first type that is
arranged under and in contact with the second well to form a
collector of the bipolar transistor.
11. The method according to claim 10, wherein step (c) comprises:
forming a fourth region doped with the second type that is arranged
in the second well laterally with respect to the emitter, wherein
said fourth region forms an electrical contact plug for the base of
the bipolar transistor; and forming an insulator that laterally
separates the fourth region from the second region.
12. The method according to claim 10, further comprising: forming a
third well doped with the first type that is arranged at the
periphery of the second well and in electrical contact with the
third region; and forming a fifth region doped with the first type
that is arranged in the third well; wherein said fifth region and
said third well together form an electrical contact plug for the
collector of the bipolar transistor.
13. The method according to claim 10, wherein each step implements
a single mask.
14. The method according to claim 10, further comprising forming a
low-voltage MOS transistor in a second portion of the substrate
different from the first portion.
Description
PRIORITY CLAIM
[0001] This application claims the priority benefit of French
Application for Patent No. 1913605, filed on Dec. 2, 2019, the
content of which is hereby incorporated by reference in its
entirety to the maximum extent allowable by law.
TECHNICAL FIELD
[0002] The present text relates to a microelectronic device
comprising at least one MOS transistor and one bipolar transistor,
as well as a method for manufacturing such a device.
BACKGROUND
[0003] The combination, in a microelectronic device, of MOS
transistors and bipolar transistors can be useful insofar as these
two types of transistors have different properties and can fulfill
different functions.
[0004] Thus, for example, the bipolar transistors can be used to
form "bandgap"-type circuits defining a very stable reference
voltage with respect to temperature variations.
[0005] However, the different structures of the MOS transistors and
of the bipolar transistors generally involve different
manufacturing steps, in particular requiring the use of specific
masks, which complicate the method for manufacturing the
microelectronic device and increase the duration and cost
thereof
[0006] There is a need in the art for a circuit and a method of
manufacture to provide a circuit which includes, on the same
substrate, at least one high-voltage MOS transistor and at least
one bipolar transistor.
SUMMARY
[0007] In an embodiment, a microelectronic device comprises: a
substrate including at least one high-voltage MOS transistor and at
least one bipolar transistor in the same first portion of said
substrate. The first portion comprises a first well doped with a
first type and electrically insulated from the substrate to form
the channel of the high-voltage MOS transistor and two first
regions doped with a second type opposite to the first type that
are arranged on the first well to form, respectively, the source
and the drain of the high-voltage MOS transistor. The first portion
further comprises: a second well doped with the second type that is
arranged laterally with respect to the first well to form the base
of the bipolar transistor; a second region doped with the first
type that is arranged on the second well to form the emitter of the
bipolar transistor; and a third region doped with the first type
that is arranged under the second well to form the collector of the
bipolar transistor.
[0008] It is meant by "vertical" in the present text an arrangement
of regions (for example layers or wells) in the thickness direction
of the device. The terms "on" and "under" or "upper" and "lower"
are understood in relation to this vertical direction, the main
surface of 2 0 the substrate on which the gate of the MOS
transistor and the emitter of the bipolar transistor are arranged
being considered as the upper surface of the device. In the present
text, unless otherwise indicated, the terms "on" and "under" should
also be understood as meaning that the considered regions are in
direct contact.
[0009] It is meant by "lateral" in the present text an arrangement
of regions in the direction of a main surface of the device. Such a
main surface generally extends perpendicularly to the thickness of
the device. Unless otherwise indicated, the term "laterally" does
not mean that the considered regions are in direct contact.
[0010] The bipolar transistor is arranged vertically in the device,
that is to say the emitter, the base and the collector are stacked
in the thickness direction of the device. The high-voltage MOS
transistor is however arranged laterally in the device.
[0011] It is meant by "high-voltage" (HV) in the present text an
electrical voltage greater than or equal to 5 V.
[0012] It is meant by "low-voltage" (LV) in the present text an
electrical voltage less than or equal to 3.6 V.
[0013] It is meant by "portion" in the present text a portion of
the substrate that undergoes the same set of steps during the
method for manufacturing transistors. Such a portion may be
continuous or discontinuous, that is to say formed of several areas
separate from each other within the substrate. Two portions that do
not undergo the same set of steps are considered to be different in
the present text. Depending on the doping level of the different
wells or regions formed in one portion, said portion will be
adapted for high-voltage MOS transistors or for low-voltage MOS
transistors.
[0014] In such a device, the integration of the bipolar transistor
in a portion dedicated to the formation of a high-voltage MOS
transistor benefits from the fact that the base is formed in a well
which is doped more lightly than the corresponding well of a
low-voltage MOS transistor.
[0015] This results in a significant improvement in the current
gain of the bipolar transistor, without requiring specific steps
for the formation of said bipolar transistor in the method for
manufacturing the high-voltage MOS transistor. The masks used to
form the high-voltage MOS transistors can be adapted to define the
different parts of the bipolar transistor, in the same doping
steps.
[0016] The bipolar transistor can be of the NPN or PNP type.
[0017] In some embodiments, the first portion comprises at least a
fourth region doped with the second type that is arranged on the
second well laterally with respect to the second region, said
fourth region forming an electrical contact plug for the base of
the bipolar transistor.
[0018] Furthermore, said first portion may comprise at least a
third well doped with the first type that is arranged at the
periphery of the second well and in electrical contact with the
third region and at least a fifth region doped with the first type
that is arranged on the third well, said fifth region and said
third well forming together an electrical contact plug for the
collector of the bipolar transistor.
[0019] In some embodiments, the device further comprises at least
one low-voltage MOS transistor in a second portion of the
substrate, different from the first portion.
[0020] Said second portion comprises a first well doped with the
first type, electrically insulated from the substrate to form the
channel of the low-voltage MOS transistor and two first regions
doped with the second type that are arranged on the first well to
form, respectively, the source and the drain of the low-voltage MOS
transistor, the doping of the first and second wells of the first
portion being lower than the doping of the well of the second
portion.
[0021] In some embodiments, the bipolar transistor is of the
NPN-type, the first doping type being an N-type doping and the
second doping type being a P-type doping, the third region being an
insulation well that is arranged between the first and second wells
and the substrate.
[0022] In other embodiments, the bipolar transistor is of the
PNP-type, the first doping type being a P-type doping and the
second doping type being an N-type doping, the third region being a
region of the substrate that is arranged under the second well.
[0023] In another embodiment, a method for manufacturing a
microelectronic device, comprises the following steps: (a) forming
trenches in the substrate so as to define active areas in the first
portion; (b) forming a first well doped with a first type in a
first active area and a second well doped with a second type
opposite to the first type in a second active area, the first well
forming the channel of the high-voltage MOS transistor and the
second well forming the base of the bipolar transistor; (c) forming
two first regions doped with the second type that are arranged on
the first well and forming a second region doped with the first
type that is arranged on the second well, the first regions forming
the source and the drain of the high-voltage MOS transistor and the
second region forming the emitter of the bipolar transistor, and
forming a third region doped with the first type that is arranged
under the second well to form the collector of the bipolar
transistor.
[0024] In some embodiments, step (c) comprises the formation of at
least a fourth region doped with the second type that is arranged
on the second well laterally with respect to the emitter, said
fourth region forming an electrical contact plug for the base of
the bipolar transistor.
[0025] In some embodiments, step (b) comprises the formation of at
least a third well doped with the first type that is arranged at
the periphery of the second well and in electrical contact with the
third region, and step (c) comprises the formation of at least a
fifth region doped with the first type that is arranged on the
third well, said fifth region and said third well forming together
an electrical contact plug for the collector of the bipolar
transistor.
[0026] In a particularly advantageous manner, each step implements
a single mask. In some embodiments, the method further comprises
the formation of at least one low-voltage MOS transistor in a
second portion of the substrate different from the first
portion.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Other characteristics and advantages of these embodiments
will appear in the following detailed description, with reference
to the appended drawings in which:
[0028] FIG. 1 is a schematic sectional view of a microelectronic
device during a first step of integrating an NPN bipolar transistor
in a portion intended to form a high-voltage MOS transistor,
comprising the definition of the active areas in a semi-conductor
substrate and the formation of electrically insulating trenches
separating said areas;
[0029] FIG. 2 is a schematic sectional view of the device of FIG. 1
during a second step of integrating the NPN bipolar transistor, in
which an N-doped insulation implant and N-doped and P-doped wells
are formed by implantation and make it possible to form the wells
of the high-voltage MOS transistors and the collector and the base
of the bipolar transistor;
[0030] FIG. 3 is a schematic sectional view of the device of FIG. 2
during a third step of integrating the NPN bipolar transistor in
which doped regions are formed on the wells to form the source and
the drain of the high-voltage MOS transistor as well as the
emitter, the contact plug of the base and the contact plug of the
collector of the bipolar transistor;
[0031] FIG. 4 is a schematic sectional view of the NPN bipolar
transistor of FIG. 3;
[0032] FIG. 5 is a schematic sectional view of a microelectronic
device comprising an NPN bipolar transistor formed in a portion
comprising a low-voltage MOS transistor;
[0033] FIG. 6 presents the current gain, noted respectively
.beta..sub.HV and .beta..sub.LV of the bipolar transistors of FIGS.
4 and 5;
[0034] FIG. 7 is a schematic sectional view of a microelectronic
device comprising a PNP bipolar transistor integrated in a portion
comprising a high-voltage MOS transistor.
[0035] For reasons of readability of the figures, the drawings are
not drawn to scale. Furthermore, the drawings have been simplified
so as to show only the elements useful for the understanding of the
figures.
DETAILED DESCRIPTION
[0036] The formation of the bipolar transistor and of the
high-voltage MOS transistor is implemented in the same portion of
the substrate, that is to say a portion which undergoes the same
set of treatments, common to the formation of the high-voltage MOS
transistor and to the formation of the bipolar transistor.
Particularly, the bipolar transistor is produced during steps
dedicated to the formation of the high-voltage MOS transistor, and
requires no specific step, in particular no step requiring a
masking or an implantation dedicated only to the bipolar
transistor.
[0037] The integration of the bipolar transistor in the portion
intended for the high-voltage MOS transistor is reflected in the
following structure: a first well doped with a first type that is
electrically insulated from the substrate, wherein said first well
forms the channel of the high-voltage MOS transistor; two first
regions doped with a second type opposite to the first type that
are arranged on the first well and form, respectively, the source
and the drain of the high-voltage MOS transistor; a second well
doped with the second type that is arranged laterally with respect
to the first well and forms the base of the bipolar transistor; a
second region doped with the first type that is arranged on the
second well and forms the emitter of the bipolar transistor; and a
third region doped with the first type that is arranged under the
second well and forms the collector of the bipolar transistor.
[0038] Depending on its doping type, the third region, which forms
the collector of the bipolar transistor, can be a region doped with
a type opposite to that of the substrate or, if the collector is
doped with the same type as the substrate, the third region is a
region of the substrate itself.
[0039] Advantageously, since the base is not flush with the surface
of the substrate, it is possible to form at least a fourth region
doped with the second type that is arranged on the second well
laterally with respect to the second region; said fourth region
forming an electrical contact plug for the base of the bipolar
transistor.
[0040] Finally, with the collector being buried in the substrate,
it is possible to form an electrical contact plug for the collector
by stacking a third well doped with the first type that is arranged
at the periphery of the second well and in electrical contact with
the third region which forms the collector and a fifth region doped
with the first type that is arranged on the third well.
[0041] The formation of said wells and regions is carried out by
steps common to the formation of the high-voltage MOS transistor
and of the bipolar transistor. In other words, wells or regions
doped with the same type and located at similar locations within
the thickness of the substrate are formed in implantation steps
common to the high-voltage MOS transistor and to the bipolar
transistor.
[0042] Said steps typically comprise: the formation of electrically
insulating trenches in the substrate so as to define active areas
in the substrate portion; the formation of the first well and the
third well in two different active areas by an implantation of
dopants of the first type through a first mask; the formation of
the second well in a second active area by an implantation of
dopants of the second type through a second mask; thus, during the
two first implantation steps mentioned above, the wells of the
high-voltage MOS transistors and the base of the bipolar transistor
are formed, as well as a well that is configured to electrically
connect the collector to the surface of the bipolar transistor; the
formation of the two first regions on the first well and the fourth
region on the second well by implantation of dopants of the second
type through a third mask; the source and the drain of the
high-voltage MOS transistor and the contact plug of the base of the
bipolar transistor are thus formed in the same step; and the
formation of the second region on the second well and of the fifth
region on the third well by implantation of dopants of the first
type through a fourth mask, wherein the emitter and the contact
plug of the collector of the bipolar transistor are thus formed in
a single step.
[0043] Depending on the doping type, said wells or regions can be
adapted to the formation of N-channel or P-channel MOS transistors,
and NPN or PNP bipolar transistors.
[0044] The microelectronic device may comprise another portion
dedicated to the formation of at least one low-voltage MOS
transistor.
[0045] The method for manufacturing the microelectronic device then
implements a first series of masks dedicated to the formation of
the high-voltage MOS transistor integrating the bipolar transistor
in a first portion of the substrate, and a second series of masks
dedicated to the formation of the low-voltage MOS transistor in a
second portion of the substrate. The formation of the low-voltage
MOS transistor involves steps similar to those described above for
the high-voltage MOS transistor, but with different implanted doses
of dopants.
[0046] FIGS. 1 to 3 illustrate some of these steps, for the
manufacture of an NPN bipolar transistor, in a portion dedicated to
the formation of a high-voltage MOS transistor.
[0047] FIG. 1 is a sectional view of a substrate S in which were
formed electrically insulating trenches STI configured to delimit
active areas of the device.
[0048] Although represented separately in FIGS. 1 to 3, the left
and right parts belong to the same portion of the substrate,
referenced I in FIG. 3. The left part of said first portion is
intended for the formation of a high-voltage MOS transistor HVMOS,
the right part of said first portion is intended for the formation
of a bipolar transistor BIP.
[0049] The substrate is a semiconductor substrate, for example of
silicon. The substrate is generally P-type doped.
[0050] With reference to FIG. 2, a first N-doped well 1N1 is formed
in the active area dedicated to the high-voltage MOS transistor and
a second P-doped well 1P is formed in the active area dedicated to
the bipolar transistor. The first well 1N1 forms the well (body,
channel) of the transistor HVMOS and the second well 1P forms the
base of the bipolar transistor.
[0051] Two N-doped wells 1N2 are also formed on either side of the
well 1P.
[0052] The formation of the wells 1N1 and 1N2 is carried out during
the same N-type doping step, through a single mask applied on the
first portion of the substrate. The wells 1N2 are therefore
identical to the well 1N1 but have been designated by a different
reference sign to distinguish the description of the MOS transistor
and of the bipolar transistor. The formation of the second well is
carried out during another P-type doping step, through another
mask.
[0053] To electrically insulate the wells 1N1, 1N2 and 1P, a
heavily N-doped insulation (NISO) well 3N is also formed beforehand
under said wells. The well 3N in the transistor HVMOS area and the
well 3N in the transistor BIP area are each, preferably, formed by
a single dopant implant. This results, in particular, in the
formation of the collector of the transistor BIP being made of a
single buried dopant implant with well 3N in contact with the
bottom of well 1P. The well 3N is intended to form the collector of
the bipolar transistor. Preferably, the collector is formed from a
single implantation step, which may allow a better electrical
control of the collector as compared to a collector presenting a
gradual architecture comprising a stack of two N-doped regions with
different doping levels.
[0054] With reference to FIG. 3, two P-doped regions 2P forming the
source and the drain of the transistor HVMOS are formed on the
first well 1N1. An N-doped region 2N1 forming the emitter of the
bipolar transistor, an N-doped region 2N2 on each of the two wells
1N2 and two P-doped regions 2P on the second well 1P are also
formed on the second well 1P. The regions 2N2 form, with the wells
1N2, contact plugs for the collector of the transistor BIP. The
regions 2P form contact plugs for the base of the transistor BIP.
The shallow trench isolation provides a lateral separation of the
region 2P from region 2N1, with the shallow trench isolation having
a depth that greater than a depth of either of the region 2P or the
region 2N1. It may be noted that the base contact regions 2P are
electrically isolated from the emitter 2N1 by electrically
insulating trenches STI, which allows preventing any short-circuit
between the base and the emitter after deposition onto the doped
regions, at a final stage of the manufacturing process, of a
silicide layer intended to improve the electrical contact.
[0055] The formation of the regions 2P of the transistor HVMOS and
of the transistor BIP is carried out during the same P-type doping
step, through a single mask applied on the first portion of the
substrate. The formation of the regions 2N1 and 2N2 is carried out
during another N-type doping step, through another mask applied on
the first portion of the substrate.
[0056] FIG. 4 is a view of the bipolar transistor of FIG. 3, on
which the typical diagram of the bipolar transistor was
superimposed to facilitate the identification of the collector C,
of the base B and of the emitter E of said transistor.
[0057] For comparison, FIG. 5 illustrates an NPN bipolar transistor
BIP' formed in a portion II of the substrate dedicated to the
formation of a low-voltage MOS transistor LVMOS.
[0058] The reference signs identical to those of FIG. 3 refer to
the same wells or regions; they are followed by a symbol ' when
these wells or regions are doped differently between the portion I
dedicated to the high-voltage and the portion II dedicated to the
low-voltage.
[0059] There is a doping difference between the bipolar transistor
BIP formed in the portion I and the bipolar transistor BIP' formed
in the portion II in the following regions: the base which is
formed in the well 1P, respectively 1P'; and the well 1N2' which
electrically connects the well 3N to the region 2N2 to form the
contact plug for the base.
[0060] Thus, by way of example, in the case of the transistor BIP'
formed in the portion II, the well 1P' is formed by two
implantations of boron with, respectively, a dose of
2.8.times.10.sup.13 at/cm.sup.3 and an energy of 75 keV, and a dose
of 1.3.times.10.sup.13 at/cm.sup.3 and an energy of 190 keV, and an
implantation of boron fluoride (BF.sub.2) with a dose of
7.0.times.10.sup.12 at/cm.sup.3 and an energy of 25 keV. On the
other hand, in the case of the transistor BIP formed in the portion
I, the well 1P is formed by two implantations of boron with
respectively a dose of 1.4.times.10.sup.13 at/cm.sup.3 and an
energy of 195 keV, and a dose of 4.0.times.10.sup.12 at/cm.sup.3
and an energy of 15 keV.
[0061] The doping levels of the other wells or regions are
substantially identical in the bipolar transistors formed in the
portions I and II.
[0062] FIG. 6 illustrates the current gain .beta..sub.HV of a
bipolar transistor formed in a portion dedicated to the formation
of a high-voltage MOS transistor (FIG. 4) and the current gain
.beta..sub.LV of a bipolar transistor formed in a portion dedicated
to the formation of a low-voltage MOS transistor (FIG. 5).
[0063] The gain .beta..sub.HV is approximately equal to twice the
gain .beta..sub.LV, which represents a significant advantage of the
bipolar transistor of FIG. 4. The gain .beta..sub.LV, which is in
the order of 6, is considered to be low, but the gain .beta..sub.HV
which is in the order of 12, is considered to be an interesting
gain for a bipolar transistor formed in a manufacturing method not
comprising a step dedicated to said bipolar transistor.
[0064] This difference between the current gains of the two bipolar
transistors is explained by the definition of the gain .beta. as a
function of the properties of the emitter, of the base and of the
collector of the bipolar transistor:
.beta. = f ( n p 1 W b N e N b ) ##EQU00001##
[0065] where: [0066] .mu..sub.n is the mobility of the electrons
and .mu..sub.p is the mobility of the holes, [0067] W.sub.b is the
width of the base (see FIG. 4), [0068] N.sub.e is the dopant
concentration of the emitter and N.sub.b is the dopant
concentration of the base.
[0069] The base being less doped in the bipolar transistor formed
in the high-voltage portion than in the bipolar transistor formed
in the low-voltage portion, the ratio N.sub.e/N.sub.b is higher in
the bipolar transistor formed in the high-voltage portion.
[0070] Furthermore, in the high-voltage portion, the dopants
implanted in the insulation well (3P in the case of the transistor
of FIG. 3) diffuse further towards the surface of the substrate
than in the low-voltage portion, so that the width W.sub.b of the
base is smaller in the bipolar transistor formed in the
high-voltage portion than in the bipolar transistor formed in the
low-voltage portion.
[0071] These two modifications contribute to an increase in the
current gain between a bipolar transistor formed in a high-voltage
portion and a bipolar transistor formed in a low-voltage
portion.
[0072] Although the description above concerns an NPN bipolar
transistor, the method for integrating the bipolar transistor with
a high-voltage MOS transistor also applies to a PNP bipolar
transistor. Indeed, there are also observed substantially lower
dopant concentrations in the base of the bipolar transistor formed
in the high-voltage portion than in the base of the bipolar
transistor formed in the low-voltage portion, which are reflected
by higher current gain for the bipolar transistor formed in the
high-voltage portion than for the bipolar transistor formed in the
low-voltage portion.
[0073] FIG. 7 is a schematic sectional view of a microelectronic
device comprising such a PNP bipolar transistor integrated in a
portion comprising a high-voltage MOS transistor.
[0074] The left part of FIG. 7 represents the high-voltage MOS
transistor HVMOS. In this part, the substrate S, which is a P-doped
semiconductor substrate, comprises a P-doped well 1P1 forming the
channel of the transistor HVMOS. The source and the drain of the
transistor HVMOS are N-doped regions on the well 1P1, on either
side of the channel.
[0075] The right part of FIG. 7 represents the PNP-type bipolar
transistor BIP. Although the two parts are represented separate,
they belong to the same portion of the substrate.
[0076] In the part dedicated to the bipolar transistor, the
substrate S comprises a well 1N surrounded by two P-doped wells
1P2. The well 1N forms the base of the transistor.
[0077] The collector of the transistor is formed by a P-doped
region 3P extending under the well 1N. The substrate being P-doped,
the region 3P does not have to be individualized in the form of a
well in the substrate.
[0078] The wells 1P2 are each surmounted by a P-doped region 2P2.
The regions 2P2 form a contact plug for the buried collector, the
wells 1P2 ensuring an electrical continuity between the regions 2P2
and the region 3P that forms the collector.
[0079] The emitter of the bipolar transistor is formed by a P-doped
region 2P1 on the well 1N. Two regions 2N are also formed on the
well 1N to form each a contact plug for the base.
[0080] Said transistors HVMOS and BIP are formed by a method
similar to that of FIGS. 1 to 3, by reversing the doping types in
the different wells and regions formed in the substrate.
[0081] In the PNP bipolar transistor thus formed, the dose of N
dopant implanted to form the base is approximately 20 times lower
than if said bipolar transistor had been formed in a portion
dedicated to the formation of a low-voltage MOS transistor.
[0082] Thus, by way of example, in the case of a PNP bipolar
transistor formed in a low-voltage portion, the well can be formed
by two implantations of phosphorus with respectively a dose of
2.8.times.10.sup.13 at/cm.sup.3 and an energy of 200 keV, and a
dose of 1.0.times.10.sup.13 at/cm.sup.3 and an energy of 320 keV,
and an implantation of arsenic with a dose of 2.7.times.10.sup.12
at/cm.sup.3 and an energy of 60 keV. On the other hand, in the case
of a PNP bipolar transistor formed in the high-voltage portion I,
the well 1N can be formed by two implantations of phosphorus with
respectively a dose of 1.0.times.10.sup.13 at/cm.sup.3 and an
energy of 315 keV, and a dose of 1.2.times.10.sup.12 at/cm.sup.3
and an energy of 160 keV, and an implantation of arsenic with a
dose of 1.0.times.10.sup.11 at/cm.sup.3 and an energy of 95
keV.
* * * * *