U.S. patent application number 16/675200 was filed with the patent office on 2021-05-06 for bonded semiconductor structure and method for forming the same.
The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Po-Yu Yang.
Application Number | 20210134747 16/675200 |
Document ID | / |
Family ID | 1000004480863 |
Filed Date | 2021-05-06 |
United States Patent
Application |
20210134747 |
Kind Code |
A1 |
Yang; Po-Yu |
May 6, 2021 |
BONDED SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
Abstract
A semiconductor structure is disclosed, including a substrate,
an insulating layer on the substrate, a barrier layer on the
insulating layer, a bonding dielectric layer on the barrier layer,
and a bonding pad extending through the insulating layer, the
barrier layer and the bonding dielectric layer. A top surface of
the bonding pad exposed from the bonding dielectric layer for
bonding to another bonding pad on another substrate. A liner on a
bottom surface of the bonding pad directly contacts the
substrate.
Inventors: |
Yang; Po-Yu; (Hsinchu City,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsin-Chu City |
|
TW |
|
|
Family ID: |
1000004480863 |
Appl. No.: |
16/675200 |
Filed: |
November 5, 2019 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2924/05042
20130101; H01L 2224/0311 20130101; H01L 2224/05681 20130101; H01L
2224/2908 20130101; H01L 25/0657 20130101; H01L 2224/05576
20130101; H01L 2224/29083 20130101; H01L 2224/29187 20130101; H01L
2224/05684 20130101; H01L 2224/32145 20130101; H01L 2224/05567
20130101; H01L 2224/05624 20130101; H01L 24/29 20130101; H01L 24/08
20130101; H01L 2924/059 20130101; H01L 24/03 20130101; H01L
2224/05647 20130101; H01L 24/32 20130101; H01L 2924/05442 20130101;
H01L 2224/08147 20130101; H01L 2224/05666 20130101; H01L 24/05
20130101 |
International
Class: |
H01L 23/00 20060101
H01L023/00; H01L 25/065 20060101 H01L025/065 |
Claims
1. A semiconductor structure, comprising: a substrate; an
insulating layer on the substrate; a barrier layer on the
insulating layer, wherein the barrier layer comprises multiple
diffusion barrier layers and at least a dielectric layer stacking
alternatively on the insulating layer; a bonding dielectric layer
on the barrier layer; and a bonding pad extending through the
bonding dielectric layer, the barrier layer and the insulating
layer and having a top surface exposed from the bonding dielectric
layer for bonding to another bonding pad of another semiconductor
structure, wherein the bonding pad comprises a conductive material
and a liner lining the conductive material, and the liner on a
bottom surface of the conductive material directly contacts the
substrate.
2. The semiconductor structure according to claim 1, further
comprising a conductive structure formed in the substrate, wherein
the liner on the bottom surface of the bonding pad directly
contacts a top surface of the conductive structure.
3. The semiconductor structure according to claim 1, wherein a
thickness of the bonding dielectric layer on the barrier layer is
smaller than a thickness of the insulating layer under the barrier
layer.
4. The semiconductor structure according to claim 1, wherein the
liner on a sidewall of the bonding pad directly contacts the
insulating layer, the bonding dielectric layer and the barrier
layer.
5. The semiconductor structure according to claim 1, wherein the
bonding dielectric layer comprises silicon oxide (SiO2).
6. The semiconductor structure according to claim 1, wherein the
diffusion barrier layers respectively comprise silicon nitride
(SiN) or silicon oxynitride (SiON).
7. (canceled)
8. The semiconductor structure according to claim 1, wherein the
insulating layer and the dielectric layer comprise silicon oxide
(SiO2), silicon oxynitride (SiON), or silicon nitride (SiN).
9. The semiconductor structure according to claim 1, further
comprising an etching stop layer intervening between the substrate
and the insulating layer, wherein the bottom surface of the bonding
pad is flush with or lower than a bottom surface of the etching
stop layer.
10. The semiconductor structure according to claim 1, wherein the
etching stop layer comprises silicon carbide (SiC).
11. A bonded semiconductor structure, comprising: a first substrate
and a second substrate disposed on the first substrate; a first
insulating layer and a first bonding dielectric layer between the
first substrate and the second substrate; a first barrier layer
between the first insulating layer and the first bonding dielectric
layer, wherein the first barrier layer comprises multiple first
diffusion barrier layers and at least a first dielectric layer
alternatively arranged between the first insulating layer and the
first bonding dielectric layer; a first bonding pad extending
through the first bonding dielectric layer, the first barrier layer
and the first insulating layer, wherein the first bonding pad
comprises a first conductive material and a first liner lining the
first conductive material, and the first liner on a bottom surface
of the first conductive material directly contacts the first
substrate; a second bonding dielectric layer between the first
bonding dielectric layer and the second substrate and being bonded
to the first bonding dielectric layer; and a second bonding pad in
the second bonding dielectric layer and being bonded to the first
bonding pad.
12. The bonded semiconductor structure according to claim 11,
further comprising a first conductive structure formed in the first
substrate, wherein the first liner on the bottom surface of the
first bonding pad directly contacts a top surface of the first
conductive structure.
13. The bonded semiconductor structure according to claim 11,
wherein the first bonding dielectric layer and the second bonding
dielectric layer comprise silicon oxide (SiO2).
14. The bonded semiconductor structure according to claim 11,
wherein the first diffusion barrier layers respectively comprise
silicon nitride (SiN) or silicon oxynitride (SiON).
15. (canceled)
16. The bonded semiconductor structure according to claim 11,
further comprising an etching stop layer intervening between the
first substrate and the first insulating layer, wherein the bottom
surface of the first bonding pad is flush with or lower than a
bottom surface of the etching stop layer.
17. The bonded semiconductor structure according to claim 11,
further comprising: a second insulating layer between the second
bonding dielectric layer and the second substrate; a second barrier
layer between the second insulating layer and the second bonding
dielectric layer, wherein the second barrier layer comprises
multiple second diffusion barrier layers and at least a second
dielectric layer alternatively arranged between the second
insulating layer and the second bonding dielectric layer; and a
second conductive structure formed in the second substrate and
connected to the second bonding pad, wherein a second liner on the
surface of second bonding pad directly contacts the second
substrate.
18. The bonded semiconductor structure according to claim 11,
wherein a thickness of the first bonding dielectric layer on the
first barrier layer is smaller than a thickness of the first
insulating layer under the first barrier layer.
19. The bonded semiconductor structure according to claim 11,
wherein the first liner on a sidewall of the first bonding pad
directly contacts the first insulating layer, the first bonding
dielectric layer and the first barrier layer.
20. The bonded semiconductor structure according to claim 11,
wherein the second bonding pad is not in direct contact with the
first barrier layer.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0001] The invention relates to a bonded semiconductor structure
and a method for forming the same, and more particularly, to a
bonded semiconductor structure and a method for forming the same
using hybrid bonding.
2. Description of the Prior Art
[0002] In advanced semiconductor industry, integration density of
various electronics components has been continuously improved by
reducing minimum feature size, which allows more electronics
components to be integrated into given areas. These smaller
electronic components also require smaller packages that utilize
less area than packages of the past, in some applications.
[0003] Three dimensional integrated circuits (3DICs) are recently
development in which multiple semiconductor dies are stacked upon
one another, such as package-on-package (PoP) and system-in-package
(SiP) packaging techniques. 3DICs provide improved integration
density and other advantages such as faster speeds and higher
bandwidth because of the decreased length of interconnects between
the stacked dies.
[0004] Bonding of multiple semiconductor dies of 3DICs may be
achieved by placing dies over dies on a wafer level and forming a
bonding interface between the dies by a hybrid bonding process.
Hybrid bonding (also known as "metal/dielectric hybrid bonding")
can be a direct bonding technology (e.g., forming bonding between
surfaces without using intermediate layers, such as solder or
adhesives), which obtains metal-to-metal bonding and
dielectric-to-dielectric bonding simultaneously.
[0005] However, there are many challenges related to 3DICs. For
example, conductive material such as copper (Cu) for forming the
bonding pads may diffuse in the plane of the bonding interface,
which may cause electrical shorts and reliability problems in the
bonded structure.
SUMMARY OF THE INVENTION
[0006] In light of the above, the present invention is directed to
provide a semiconductor structure for hybrid bonding by which a
high adhesion strength and containment of interfacial impurity
diffusion may be achieved.
[0007] According to an embodiment of the present invention, a
semiconductor structure is disclosed, which includes a substrate,
an insulating layer disposed on the substrate, a barrier layer
disposed on the insulating layer, a bonding dielectric layer
disposed on the barrier layer, and a bonding pad extending through
the bonding dielectric layer, the barrier layer and the insulating
layer and having a top surface exposed from the bonding dielectric
layer for bonding to another bonding pad of another semiconductor
structure, wherein the bonding pad comprises a conductive material
and a liner lining the conductive material, and the liner on a
bottom surface of the conductive material directly contacts the
substrate.
[0008] According to another embodiment of the present invention, a
bonded semiconductor structure is disclosed, which includes a first
substrate and a second substrate disposed on the first substrate, a
first insulating layer and a first bonding dielectric layer between
the first substrate and the second substrate, a first barrier layer
between the first insulating layer and the first bonding dielectric
layer, a first bonding pad extending through the first bonding
dielectric layer, the first barrier layer and the first insulating
layer, wherein the first bonding pad comprises a first conductive
material and a first liner lining the first conductive material,
and the first liner on a bottom surface of the first conductive
material directly contacts the first substrate, a second bonding
dielectric layer between the first bonding dielectric layer and the
second substrate and being bonded to the first bonding dielectric
layer, and a second bonding pad in the second bonding dielectric
layer and being bonded to the first bonding pad.
[0009] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The accompanying drawings are included to provide a further
understanding of the embodiments, and are incorporated in and
constitute a part of this specification. The drawings illustrate
some of the embodiments and, together with the description, serve
to explain their principles. Relative dimensions and proportions of
parts of the drawings have been shown exaggerated or reduced in
size, for the sake of clarity and convenience in the drawings. The
same reference signs are generally used to refer to corresponding
or similar features in modified and different embodiments.
[0011] FIG. 1 to FIG. 4 are schematic cross-sectional drawings
illustrating a sequential process flow for forming a semiconductor
structure according to an embodiment of the present invention.
[0012] FIG. 5, FIG. 6 and FIG. 7 are schematic cross-sectional
drawings illustrating various hybrid bonded semiconductor
structures according to some embodiments of the present
invention.
DETAILED DESCRIPTION
[0013] To provide a better understanding of the present invention
to those of ordinary skill in the art, several exemplary
embodiments of the present invention will be detailed as follows,
with reference to the accompanying drawings using numbered elements
to elaborate the contents and effects to be achieved. The
accompanying drawings are included to provide a further
understanding of the embodiments, and are incorporated in and
constitute a part of this specification. These embodiments are
described in sufficient detail to enable those skilled in the art
to practice the invention. Other embodiments may be utilized and
that structural, logical and electrical changes may be made without
departing from the spirit and scope of the present invention.
[0014] It should be readily understood that the meaning of "on",
"above", "over" and the like in the present disclosure should be
interpreted in the broadest manner such that these terms not only
means "directly on something" but also includes the meaning of "on
something with an intermediate feature or a layer
therebetween".
[0015] Furthermore, spatially relative terms, such as "beneath",
"below", "under`, "lower", "above", "upper", "on", "over" and the
like may be used herein to describe one element or feature's
spatial relationship to another element(s) or feature(s) as
illustrated in the figures. The spatially relative terms are
intended to encompass different orientations of the device in use
or operation in addition to the orientation depicted in the
figures. The apparatus may be otherwise oriented (rotated 90
degrees or at other orientations) and the spatially relative
descriptors used herein may likewise be interpreted
accordingly.
[0016] The terms "wafer" and "substrate" used herein include any
structure having an exposed surface onto which a layer is deposited
according to the present invention, for example, to form the
circuit structure. The term substrate is understood to include
semiconductor wafers, but not limited thereto. The term substrate
is also used to refer to semiconductor structures during
processing, and may include other layers that have been fabricated
thereupon.
[0017] Please refer to FIG. 1 to FIG. 4, which are schematic
cross-sectional drawings illustrating a sequential process flow for
forming a semiconductor structure 1 according to an embodiment of
the present invention.
[0018] As shown in FIG. 1, a substrate 100 is provided. An etching
stop layer 118, an insulating layer 120, a barrier layer 122 and a
bonding dielectric layer 124 are successively disposed on the
substrate 100 and extend across the entire surface of the substrate
100.
[0019] The substrate 100 may be a partially processed semiconductor
wafer. The substrate 100 may include multiple material layers
having semiconductor devices and/or interconnecting structures
formed therein. As shown in FIG. 1, the substrate 100 may include a
semiconductor substrate 102, such as a silicon substrate, a
silicon-on-insulator (SOI) substrate, germanium-on-insulator (GOI)
substrate, or a Group III-V semiconductor substrate, but not
limited thereto. The semiconductor substrate 102 may comprise large
numbers and types of devices formed therein, such as memory, logic
circuits, amplifiers, inverters, transistors, and the like, which
are not shown in the diagrams for the sake of simplification.
[0020] Metallization structures comprising multilevel dielectric
layers and conductive layers may be formed on the semiconductor
substrate 102. For the sake of simplification, only the two
top-most dielectric layers 110 and 114 and the conductive
structures 112 and 116 are shown. The dielectric layers 110 and 114
may respectively include a dielectric material selected from a
group comprising silicon oxide (SiO.sub.2), silicon oxynitride
(SiON), silicon nitride (SiN), low-k dielectric materials such as
fluorinated silica glass (FSG), silicon oxycarbide (SiCOH), spin on
glass, porous low-k dielectric material, organic dielectric
polymers, or a combination thereof, but not limited thereto.
[0021] The conductive structure 112 may be a conductive pad or an
interconnecting structure to provide electrical access to the
circuits of the semiconductor substrate 102. The conductive
structure 116 may be a conductive via for electrically connecting
the bonding pad 136 formed in later process (shown in FIG. 4) to
the conductive structure 112. The conductive structures 112 and 116
may comprise metal such as tungsten (W), copper (Cu), aluminum
(Al), or other suitable metals, but not limited thereto. According
to an embodiment, the conductive structures 112 and 116 comprise
copper (Cu). The conductive structures 112 and 116 may be
respectively lined by a liner (not shown).
[0022] The insulating layer 120 and the bonding dielectric layer
124 may be made of a same or different materials selected form, but
not limited to, silicon oxide (SiO.sub.2), silicon oxynitride
(SiON), silicon nitride (SiN), or low-k dielectric materials such
as fluorinated silica glass (FSG), silicon oxycarbide (SiCOH), spin
on glass, porous low-k dielectric material, organic dielectric
polymers, or a combination thereof. According to an embodiment, the
insulating layer 120 and the bonding dielectric layer 124 are made
of silicon oxide (SiO.sub.2).
[0023] The etching stop layer 118 may protect the substrate 100
from being over-etched during the etching process for forming the
bonding pad 136. The etching stop layer 118 may comprise dielectric
material having an adequate etching selectivity with respect to the
insulating layer 120, such as silicon nitride (SiN), silicon
carbide (SiC), silicon carbon nitride (SiCN) or silicon oxynitride
(SiON), and a combination thereof, but not limited thereto.
According to an embodiment, the etching stop layer 118 comprises
silicon carbide (SiC).
[0024] The barrier layer 122 sandwiched between the insulating
layer 120 and the bonding dielectric layer 124 may comprise a
diffusion barrier layer 122a made of a dielectric material that
blocks the diffusion of interfacial impurity. The diffusion barrier
layer 122a may comprise silicon nitride (SiN), silicon carbide
(SiC), silicon carbon nitride (SiCN) or silicon oxynitride (SiON),
and a combination thereof, but not limited thereto. According to an
embodiment, the diffusion barrier layer 122a comprises silicon
nitride (SiN).
[0025] Please refer to FIG. 2. Subsequently, a patterning process
such as a photolithography-etching process is performed to remove
portions of the bonding dielectric layer 124, the barrier layer
122, the insulating layer 120 and the etching stop layer 118,
thereby forming a recess 130 exposing a top surface 116a of the
conductive structure 116 and a portion of the dielectric layer 114
beside the conductive structure 116.
[0026] Please refer to FIG. 3. Subsequently, a liner 132 is
conformally formed on the upper surface of the dielectric layer
124, the sidewall and bottom surface of the recess 130. After that,
a conductive material layer 134 is deposited on the dielectric
layer 124 in a blanket manner, completely covering the substrate
100 and filling up the recess 130. The liner 132 may comprise
single or multiple layers made of tungsten nitride (WN), titanium
(Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride
(TaN), or a combination thereof, but not limited thereto. The
conductive material layer 134 may comprise metal such as tungsten
(W), copper (Cu), aluminum (Al), or other suitable metals, but not
limited thereto. According to an embodiment, the conductive
material layer 134 comprises copper (Cu). The liner 132 may improve
adhesion between the conductive material 134 and the dielectric
layers 114, 120, 124. The liner 132 also serves as a barrier layer
for blocking the metal of the conductive material 134 from
diffusing into the dielectric layers 114, 120, 124. A seed layer
(not shown) may be conformally formed on the liner 132 before
depositing the conductive material layer 134.
[0027] Please refer to FIG. 4. Subsequently, a chemical mechanical
polishing (CMP) process or an etching process may be performed to
remove the liner 132 and the conductive material layer 134 outside
the recess 130. The liner 132a and the conductive material layer
134 remaining in the recess 130 form a bonding pad 136. The top
surface 136a of the bonding pad 136 is exposed from the upper
surface of the bonding dielectric layer 124 for hybrid bonding to
another bonding pad of another semiconductor structure.
[0028] A portion of the bonding dielectric layer 124 may be removed
during the CMP process or the etching process. The remaining
thickness T1 of the bonding dielectric layer 124 may be equal or
smaller than the thickness T2 of the insulating layer 120.
According to an embodiment, the thickness T1 of the bonding
dielectric layer 124 may range from 50 to 10000 angstroms (.ANG.),
but not limited thereto; the thickness T2 of the insulating layer
120 may range from 50 to 10000 angstroms but not limited thereto.
The thickness T3 of the barrier layer 122 may range from 5 to 1000
angstroms, but not limited thereto.
[0029] As shown in FIG. 4, according to the embodiment, the bonding
pad 136 is vertically disposed on the conductive structure 116. The
liner 132a on the bottom surface 136b of the bonding pad 136
directly covers the top surface 116a of the conductive structure
116 and a top surface of the dielectric layer 114 beside the
conductive structure 116. The liner 132a on the sidewall 136c of
the bonding pad 136 directly contacts the insulating layer 120, the
bonding dielectric layer 124, the barrier layer 122 and the etching
stop layer 118. The bottom surface 136b of the bonding pad 136 may
be flush with a bottom surface of the etching stop layer 118, as
shown in FIG. 4. In other embodiments, the recess 130 for forming
the bonding pad 136 may extend into a portion of the dielectric
layer 114, and therefore the bottom surface 136b of the bonding pad
136 may be lower than the bottom surface of the etching stop layer
118.
[0030] Please refer to FIG. 5, which is a schematic cross-sectional
diagram illustrating a hybrid bonded structure having a
semiconductor structure 1 bonded to another semiconductor structure
2 according to an embodiment of the present invention. The
semiconductor structure 1 and the semiconductor structure 2 may be
respectively prepared by the process illustrated in FIG. 1 to FIG.
4. For example, the semiconductor structure 1 may comprise a
substrate 100 (first substrate) having a semiconductor substrate
102 and multilevel dielectric layers and conductive layers such as
the dielectric layers 110 and 114 and the conductive structure 116
(first conductive structure) and a conductive structure 112 formed
on the semiconductor substrate 102. An etching stop layer 118
(first etching stop layer), an insulating layer 120 (first
insulating layer), a barrier layer 122 (first barrier layer) and a
bonding dielectric layer 124 (first bonding dielectric layer) are
successively formed on the substrate 100. A bonding pad 136 (first
bonding pad) is formed on the substrate 100 and extends through the
insulating layer 120, the barrier layer 122, the bonding dielectric
layer 124 and the etching stop layer 118 and directly connects the
conductive structure 116. The liner 132a on the sidewall and bottom
surface of the bonding pad 136 directly covers the top surface 116a
of the conductive structure 116 and a top surface of the dielectric
layer 114 besides the conductive structure 116.
[0031] Similarly, the semiconductor structure 2 may comprise a
substrate 200 (second substrate) having a semiconductor substrate
202 and multilevel dielectric layers and conductive layers such as
dielectric layers 210 and 214 and conductive structure 216 (second
conductive structure) and conductive structure 212 formed on the
semiconductor substrate 202. An etching stop layer 218 (second
etching stop layer), an insulating layer 220 (second insulating
layer), a barrier layer 222 (second barrier layer) and a bonding
dielectric layer 224 (second bonding dielectric layer) are
successively formed on the substrate 200. A bonding pad 236 (second
bonding pad) is formed on the substrate 200 and extends through the
insulating layer 220, the barrier layer 222, the bonding dielectric
layer 224 and the etching stop layer 218 and directly connects the
conductive structure 216. The liner 232a on the sidewall and bottom
surface of the bonding pad 236 directly covers the top surface 116a
of the conductive structure 116 and the top surface of the
dielectric layer 114 besides the conductive structure 116.
[0032] In the embodiment shown in FIG. 5, the semiconductor
structure 1 and the semiconductor structure 2 are bonded together
by placing the semiconductor structure 2 upside-down upon the
semiconductor structure 1, making the substrate 200 of the
semiconductor structure 2 upon the substrate 100 of the
semiconductor structure 1, allowing the interface between the
bonding dielectric layer 124 and the bonding dielectric layer 224
and the interface between the bonding pad 136 and the bonding pad
236. Afterward, a thermal treatment or other suitable bonding
process may be carried out to form dielectric-to-dielectric bonding
between the bonding dielectric layer 124 and the bonding dielectric
layer 224 and metal-to-metal bonding between the bonding pad 136
and the bonding pad 236, thereby obtaining the hybrid bonding
interface 300 between the semiconductor structure 1 and the
semiconductor structure 2.
[0033] In some embodiments, due to process variation such as
miss-alignment between the bonding pad 136 and the bonding pad 236,
a portion of the conductive material 134 of the bonding pad 136 may
be directly exposed to the bonding dielectric layer 224 and/or a
portion of the conductive material 234 may be directly exposed to
the bonding dielectric layer 124. The barrier layers 122 and 222
horizontally extending across the entire surface of the substrates
100 and 200 may effectively contain the diffusion of the conductive
material 134 or the conductive material 234 into the substrates 100
and 200, and thereby device failure due to diffused metal may be
reduced.
[0034] Please refer to FIG. 6, which is a schematic cross-sectional
diagram illustrating a hybrid bonded structures according to
another embodiment of the present invention. For the sake of
simplicity, like reference numerals are used to refer to the same
material layers or process steps described previously. In the
embodiment shown in FIG. 6, the barrier layer 122 may comprise
multiple layers. For example, the barrier layer 122 may comprise
multiple diffusion barrier layers 122a and dielectric layers 122b
stacking alternatively on the insulating layer 120. Likewise, the
barrier layer 222 may comprise multiple diffusion barrier layers
222a and dielectric layers 222b stacking alternatively on the
insulating layer 220. The dielectric layers 122b and 222b may
comprise a dielectric material such as silicon oxide (SiO.sub.2),
silicon oxynitride (SiON), silicon nitride (SiN), or low-k
dielectric materials such as fluorinated silica glass (FSG),
silicon oxycarbide (SiCOH), spin on glass, porous low-k dielectric
material, organic dielectric polymers, or a combination thereof,
but not limited thereto. According to an embodiment, the dielectric
layers 122b and 222b, the insulating layer 120 and the insulating
layer 220 comprise a same dielectric material, such as silicon
oxide (SiO2). Multiple diffusion barrier layers may provide more
protection to the substrates 100 and the substrate 200 from being
contaminated by the diffused metal.
[0035] Please refer to FIG. 7, which is a schematic cross-sectional
diagram illustrating a hybrid bonded structures according to still
another embodiment of the present invention. For the sake of
simplicity, like reference numerals are used to refer to the same
material layers or process steps described previously. In the
embodiment shown in FIG. 7, the barrier layer 122 and the barrier
layer 222 may be formed much closer to the hybrid bonding interface
300 than to the surface of the substrate 100 and the substrate 200.
In this way, when metal diffusion occurs, the diffused metal may be
contained within a smaller region near the hybrid bonding interface
300. According to an embodiment, for example, the thickness T1 of
the bonding dielectric layer 124 may range from 50 to 10000
angstroms, but not limited thereto. The thickness T2 of the
insulating layer 120 may range from 50 to 10000 angstroms, but not
limited thereto. The thickness T1 of the bonding dielectric layer
124 may be approximately one-tenth of the thickness T2 of the
insulating layer 120.
[0036] Overall, one feature of the present invention is that by
forming the diffusion barrier layer extending across the bonded
substrate, metal diffusion near the bonding interface of a hybrid
bonded semiconductor structure may be effectively controlled and
the risk of the diffused metal diffusing into the circuit of the
semiconductor structure may be reduced. Device failure due to metal
diffusion may be prevented. Furthermore, bonding strength of the
bonded semiconductor structure may also be improved by forming the
oxide-to-oxide and metal-to-metal hybrid bonding interface.
[0037] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *