U.S. patent application number 16/587122 was filed with the patent office on 2021-04-01 for thin film based passive devices and methods of forming the same.
The applicant listed for this patent is GLOBALFOUNDRIES Singapore Pte. Ltd.. Invention is credited to Tze Ho Simon CHAN, Chor Shu CHENG, Handoko LINEWIH, Yudi SETIAWAN.
Application Number | 20210098363 16/587122 |
Document ID | / |
Family ID | 1000004408531 |
Filed Date | 2021-04-01 |
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United States Patent
Application |
20210098363 |
Kind Code |
A1 |
LINEWIH; Handoko ; et
al. |
April 1, 2021 |
THIN FILM BASED PASSIVE DEVICES AND METHODS OF FORMING THE SAME
Abstract
A device may include a substrate, and an interlevel dielectric
arranged over the substrate. The interlevel dielectric may include
a first interlevel dielectric layer in an interconnect level i, the
first interlevel dielectric layer having a first interconnect and a
second interconnect therein. A nitride block insulator may be
arranged over the first interlevel dielectric layer and over the
first interconnect and the second interconnect. An opening may be
arranged in the nitride block insulator, the opening extending
through the nitride block insulator to expose a surface of the
first interconnect in the first interlevel dielectric layer. A
contact plug may be arranged in the opening of the nitride block
insulator. The contact plug at least lines the opening and prevents
out-diffusion of conductive material from the first interconnect. A
thin film of a passive component may be arranged over the nitride
block insulator and over the contact plug.
Inventors: |
LINEWIH; Handoko;
(Singapore, SG) ; CHENG; Chor Shu; (Singapore,
SG) ; CHAN; Tze Ho Simon; (Singapore, SG) ;
SETIAWAN; Yudi; (Singapore, SG) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
GLOBALFOUNDRIES Singapore Pte. Ltd. |
Singapore |
|
SG |
|
|
Family ID: |
1000004408531 |
Appl. No.: |
16/587122 |
Filed: |
September 30, 2019 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 23/5228 20130101;
H01L 23/5223 20130101; H01L 28/24 20130101; H01L 23/5226 20130101;
H01L 21/707 20130101; H01L 28/40 20130101 |
International
Class: |
H01L 23/522 20060101
H01L023/522; H01L 49/02 20060101 H01L049/02; H01L 21/70 20060101
H01L021/70 |
Claims
1. A device comprising: a substrate; an interlevel dielectric
arranged over the substrate, the interlevel dielectric comprising:
a first interlevel dielectric layer in an interconnect level i, the
first interlevel dielectric layer having a first interconnect and a
second interconnect therein; a nitride block insulator arranged
over the first interlevel dielectric layer and over the first
interconnect and the second interconnect; an opening arranged in
the nitride block insulator, the opening extending through the
nitride block insulator to expose a surface of the first
interconnect in the first interlevel dielectric layer; a contact
plug arranged in the opening of the nitride block insulator,
wherein the contact plug at least lines the opening and prevents
out-diffusion of conductive material from the first interconnect;
and a thin film of a passive component arranged over the nitride
block insulator and over the contact plug.
2. The device of claim 1, wherein the contact plug and the nitride
block insulator have a substantially planar top surface.
3. The device of claim 1, wherein the thin film conforms to a
topography of the nitride block insulator and the contact plug.
4. The device of claim 1, further comprising: a second opening
arranged in the nitride block insulator, the second opening
extending through the nitride block insulator to expose a surface
of the second interconnect in the first interlevel dielectric
layer; a second contact plug arranged in the second opening of the
nitride block insulator, wherein the second contact plug at least
lines the second opening and prevents out-diffusion of conductive
material from the second interconnect; and wherein the thin film
further covers the second contact plug and serves as a thin film
resistor, the thin film resistor electrically connects the first
interconnect and the second interconnect.
5. The device of claim 1, wherein the thin film, nitride block
insulator, and the first interconnect and the second interconnect
form a metal-insulating-metal (MIM) capacitor.
6. The device of claim 5, further comprising: a second opening
arranged in the nitride block insulator, the second opening
extending through the nitride block insulator to expose a surface
of the second interconnect in the first interlevel dielectric
layer; a second contact plug arranged in the second opening of the
nitride block insulator, wherein the second contact plug at least
lines the second opening and prevents out-diffusion of conductive
material from the second interconnect; a second thin film of the
passive component arranged over the nitride block insulator and
over the second contact plug; and wherein the thin film comprises a
plurality of interconnected first film fingers coupled to the first
interconnect, and the second thin film comprises a plurality of
interconnected second film fingers coupled to the second
interconnect, wherein each first film finger is arranged
alternately with a second film finger for forming an alternating
polarity MIM capacitor.
7. The device of claim 1, further comprising a second thin film of
the passive component arranged over the first interlevel dielectric
layer and beneath the nitride block insulator, wherein the second
thin film covers a surface of the second interconnect.
8. The device of claim 1, wherein a material of the contact plug
comprises tungsten, tantalum, titanium, tantalum nitride, titanium
nitride, or combinations thereof.
9. The device of claim 8, wherein the first interconnect and the
second interconnect each comprises a copper metal line.
10. The device of claim 1, wherein the nitride block insulator
comprises one or more layers of silicon nitride, silicon
oxynitride, or combinations thereof.
11. A method of forming a device, comprising: providing a
substrate; arranging an interlevel dielectric over the substrate,
wherein arranging the interlevel dielectric comprises: forming a
nitride block insulator over a first interlevel dielectric layer in
an interconnect level i of the interlevel dielectric, wherein the
first interlevel dielectric layer comprises a first interconnect
and a second interconnect therein; forming an opening in the
nitride block insulator, the opening extending through the nitride
block insulator to expose a surface of the first interconnect in
the first interlevel dielectric layer; forming a contact plug in
the opening of the nitride block insulator, wherein the contact
plug at least lines the opening and prevents out-diffusion of
conductive material from the first interconnect; and forming a thin
film of a passive component over the nitride block insulator and
over the contact plug.
12. The method of claim 11, wherein forming the contact plug
comprises: depositing contact plug material over the nitride block
insulator to fill the opening in the nitride block insulator, and
performing planarization to provide a substantially planar top
surface between the contact plug and the nitride block
insulator.
13. The method of claim 11, wherein forming the contact plug
comprises depositing contact plug material to at least line the
opening in the nitride block insulator, and wherein the thin film
is conformal to a topography of the nitride block insulator and the
contact plug.
14. The method of claim 11, further comprising: forming a second
opening in the nitride block insulator, the second opening
extending through the nitride block insulator to expose a surface
of the second interconnect in the first interlevel dielectric
layer; forming a second contact plug in the second opening of the
nitride block insulator, wherein the second contact plug at least
lines the second opening and prevents out-diffusion of conductive
material from the second interconnect; and wherein the thin film
further covers the second contact plug and serves as a thin film
resistor, the thin film resistor electrically connects the first
interconnect and the second interconnect.
15. The method of claim 11, wherein the thin film, nitride block
insulator, and the first interconnect and the second interconnect
form a metal-insulating-metal (MIM) capacitor.
16. The method of claim 15, further comprising: forming a second
opening in the nitride block insulator, the second opening
extending through the nitride block insulator to expose a surface
of the second interconnect in the first interlevel dielectric
layer; forming a second contact plug in the second opening of the
nitride block insulator, wherein the second contact plug at least
lines the second opening and prevents out-diffusion of conductive
material from the second interconnect; forming a second thin film
of the passive component arranged over the nitride block insulator
and over the second contact plug; and wherein the thin film further
comprises a plurality of interconnected first film fingers coupled
to the first interconnect, and the second thin film comprises a
plurality of interconnected second film fingers coupled to the
second interconnect, wherein each first film finger is arranged
alternately with a second film finger for forming an alternating
polarity MIM capacitor.
17. The method of claim 11, further comprising forming a second
thin film of the passive component over the first interlevel
dielectric layer and beneath the nitride block insulator, wherein
the second thin film covers a surface of the second
interconnect.
18. The method of claim 11, wherein a material of the contact plug
is comprises tungsten, tantalum, titanium, tantalum nitride,
titanium nitride, or combinations thereof.
19. The method of claim 18, wherein the first interconnect and the
second interconnect each comprises a copper metal line.
20. The method of claim 11, wherein the nitride block insulator
comprises one or more layers of silicon nitride, silicon
oxynitride, or combinations thereof.
Description
TECHNICAL FIELD
[0001] The present disclosure relates generally to semiconductor
devices, and more particularly to thin film based passive
components embedded in devices and methods for forming the
same.
BACKGROUND
[0002] Thin film (TF) based passive components such as thin film
resistors (TFRs) and thin film capacitors (TFCs) are employed in
high precision analog and mixed signal or radio frequency
applications, and have been utilized in many technology nodes.
TFRs, for example, are mostly used as part of a complex integrated
circuit to provide high precision resistance in a device having low
temperature coefficient of resistance (TCR). Generally, in the
fabrication of a thin film, evaporation or sputtering methods are
employed followed by subsequent patterning and etching. Special
care may be required to integrate thin films into existing process
flows of an integrated circuit. For example, the process to contact
the overlying metal interconnect layer and the TFR in a
conventional top side via pick-up configuration requires the
contact points of the TFR to protect the underlying TFR during the
via etch which may otherwise cause punch through due to the
reactive-ion etch process. In a further technique, a buffer layer
is formed on top of the deposited thin film. In other fabrication
processes such as in a via-less technology, a liner is deposited on
top of the TFR, and selectively removed.
[0003] It is desirable to provide improved integration of thin film
based passive components in devices.
SUMMARY
[0004] Embodiments generally relate to semiconductor devices and
methods for forming the semiconductor devices. According to various
non-limiting embodiments, a device may include a substrate, and an
interlevel dielectric arranged over the substrate. The interlevel
dielectric may include a first interlevel dielectric layer in an
interconnect level i, the first interlevel dielectric layer having
a first interconnect and a second interconnect therein. A nitride
block insulator may be arranged over the first interconnect and the
second interconnect. An opening may be arranged in the nitride
block insulator, the opening extending through the nitride block
insulator to expose a surface of the first interconnect in the
first interlevel dielectric layer. A contact plug may be arranged
in the opening of the nitride block insulator. The contact plug at
least lines the opening and prevents out-diffusion of conductive
material from the first interconnect. A thin film of a passive
component may be arranged over the nitride block insulator and over
the contact plug. According to various non-limiting embodiments,
the passive component may be a high precision back-end capacitor.
For example, the thin film, the nitride block insulator, and the
first interconnect and the second interconnect may form a
metal-insulating-metal (MIM) capacitor, in a non-limiting
embodiment.
[0005] According to various non-limiting embodiments, the passive
component may be a high precision back-end resistor. For example, a
second opening may be arranged in the nitride block insulator, the
second opening extending through the nitride block insulator to
expose a surface of the second interconnect in the first interlevel
dielectric layer, and a second contact plug may be arranged in the
second opening of the nitride block insulator. The thin film
further covers the second contact plug and serves as a thin film
resistor, the thin film resistor electrically connects the first
interconnect and the second interconnect.
[0006] According to various non-limiting embodiments, a method of
forming the device is provided. The method may include providing a
substrate, and arranging an interlevel dielectric over the
substrate. Arranging the interlevel dielectric may include forming
a nitride block insulator over a first interlevel dielectric layer
in an interconnect level i of the interlevel dielectric, where the
first interlevel dielectric layer comprises a first interconnect
and a second interconnect therein. An opening may be formed in the
nitride block insulator, the opening extending through the nitride
block insulator to expose a surface of the first interconnect in
the first interlevel dielectric layer. A contact plug may be formed
in the opening of the nitride block insulator, where the contact
plug at least lines the opening and prevents out-diffusion of
conductive material from the first interconnect. A thin film of a
passive component may be formed over the nitride block insulator
and over the contact plug.
[0007] These and other advantages and features of the embodiments
herein disclosed, will become apparent through reference to the
following description and the accompanying drawings. Furthermore,
it is to be understood that the features of the various embodiments
described herein are not mutually exclusive and can exist in
various combinations and permutations.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] In the drawings, like reference characters generally refer
to the same parts throughout the different views. Also, the
drawings are not necessarily to scale, emphasis instead generally
being placed upon illustrating the principles of the invention. In
the following description, various embodiments of the present
invention are described with reference to the following:
[0009] FIGS. 1A-1E show simplified cross-sectional views of
embodiments of a device;
[0010] FIG. 2 shows another simplified cross-sectional view of an
embodiment of the device; and
[0011] FIGS. 3A-3E show simplified cross-sectional views of a
process for forming a device;
[0012] FIGS. 4A-4D show simplified cross-sectional views of another
exemplary process for forming a device;
[0013] FIGS. 5A-5C show simplified cross-sectional views of yet
another exemplary process for forming a device; and
[0014] FIGS. 6A-6D show simplified perspective views of embodiments
of the device.
DETAILED DESCRIPTION
[0015] The following detailed description refers to the
accompanying drawings that show, by way of illustration, specific
details and embodiments in which the embodiments may be practiced.
These embodiments are described in sufficient detail to enable
those skilled in the art to practice the embodiments. Other
embodiments may be utilized, and structural, logical, and
electrical changes may be made without departing from the scope of
the invention. The various embodiments are not necessarily mutually
exclusive, as some embodiments can be combined with one or more
other embodiments to form new embodiments.
[0016] Aspects of the present invention and certain features,
advantages, and details thereof, are explained more fully below
with reference to the non-limiting examples illustrated in the
accompanying drawings. Descriptions of well-known materials,
fabrication tools, processing techniques, etc., are omitted so as
not to unnecessarily obscure the invention in detail. It should be
understood, however, that the detailed description and the specific
examples, while indicating aspects of the invention, are given by
way of illustration only, and are not by way of limitation. Various
substitutions, modifications, additions, and/or arrangements,
within the spirit and/or scope of the underlying inventive concepts
will be apparent to those skilled in the art from this
disclosure.
[0017] Approximating language, as used herein throughout the
specification and claims, may be applied to modify any quantitative
representation that could permissibly vary without resulting in a
change in the basic function to which it is related. Accordingly, a
value modified by a term or terms, such as "about," is not limited
to the precise value specified. In some instances, the
approximating language may correspond to the precision of an
instrument for measuring the value.
[0018] The terminology used herein is for the purpose of describing
particular examples only and is not intended to be limiting of the
invention. As used herein, the singular forms "a", "an" and "the"
are intended to include the plural forms as well, unless the
context clearly indicates otherwise. It will be further understood
that the terms "comprise" (and any form of comprise, such as
"comprises" and "comprising"), "have" (and any form of have, such
as "has" and "having"), "include (and any form of include, such as
"includes" and "including"), and "contain" (and any form of
contain, such as "contains" and "containing") are open-ended
linking verbs. As a result, a method or device that "comprises,"
"has," "includes" or "contains" one or more steps or elements
possesses those one or more steps or elements, but is not limited
to possessing only those one or more steps or elements. Likewise, a
step of a method or an element of a device that "comprises," "has,"
"includes" or "contains" one or more features possesses those one
or more features, but is not limited to possessing only those one
or more features. Furthermore, a device or structure that is
configured in a certain way is configured in at least that way, but
may also be configured in ways that are not listed.
[0019] As used herein, the term "connected," when used to refer to
two physical elements, means a direct connection between the two
physical elements. The term "coupled," however, can mean a direct
connection or a connection through one or more intermediary
elements.
[0020] As used herein, the terms "may" and "may be" indicate a
possibility of an occurrence within a set of circumstances; a
possession of a specified property, characteristic or function;
and/or qualify another verb by expressing one or more of an
ability, capability, or possibility associated with the qualified
verb. Accordingly, usage of "may" and "may be" indicates that a
modified term is apparently appropriate, capable, or suitable for
an indicated capacity, function, or usage, while taking into
account that in some circumstances the modified term may sometimes
not be appropriate, capable or suitable. For example, in some
circumstances, an event or capacity can be expected, while in other
circumstances the event or capacity cannot occur--this distinction
is captured by the terms "may" and "may be."
[0021] Embodiments of the present disclosure generally relate to
devices and methods for forming devices. The devices may be
semiconductor devices. For example, the semiconductor devices may
be integrated circuits (ICs) having embedded thin film based
passive components. The thin film based passive components may be
arranged in an interlevel dielectric of the device. According to
various non-limiting embodiments, a thin film based passive
component may be arranged between any interconnect level (between
inter-metal dielectric (IMD) layers), and below a layer of the
uppermost interconnect in the interlevel dielectric. According to
various non-limiting embodiments, the thin film based passive
components may be formed using CMOS processing. Embodiments
according to the present invention as will be described
advantageously enables uniform contact pick-up on thin film
throughout a wafer (e.g., wafer center, wafer edge). Further,
embodiments according to the present invention avoid punch-through
due to reactive-ion etching compared to existing thin film passive
components having conventional top side via pick-up. Furthermore,
embodiments according to the present invention avoid or obviate the
opening or exposure of metallic element of the thin film such as
chromium (Cr) after deposition and patterning of the thin film
during CMOS back-end-of-line (BEOL) process. Exposure of such
material from the thin film will require a special handling during
BEOL processing, i.e., separate route process due to production
line contamination risks, which is undesirable. Accordingly, no
contamination is introduced using a bottom pick-up connection
according to various embodiments as will be described.
[0022] According to various non-limiting embodiments, the
interlevel dielectric may be arranged over a substrate and may
include a first interlevel dielectric layer in an interconnect
level i. The first interlevel dielectric layer may include or
surround a first interconnect and a second interconnect. A nitride
block insulator may be arranged over the first interlevel
dielectric layer and over the first interconnect and the second
interconnect. One or more openings may be arranged in the nitride
block insulator, the openings extending through the nitride block
insulator to expose a surface of the first interconnect and/or the
second interconnect in the first interlevel dielectric layer. A
contact plug may be arranged in an opening of the nitride block
insulator. The contact plug at least lines the opening and prevents
out-diffusion of conductive material from the first interconnect. A
thin film of a passive component may be arranged over the nitride
block insulator and over the contact plug.
[0023] FIGS. 1A-1E show simplified cross-sectional views of
embodiments of a device 100. The device 100 may be a semiconductor
device (e.g., an integrated circuit (IC) chip). The device may
include a substrate 105. The substrate 105 may be a semiconductor
substrate, such as a silicon substrate in a non-limiting example.
In some embodiments, the substrate may be a
crystalline-on-insulator (COI) substrate. A COI substrate may
include a surface crystalline layer separated from a bulk
crystalline by an insulator layer. The insulator layer, for
example, may be formed of a dielectric insulating material, such as
silicon oxide, which provides a buried oxide (BOX) layer. Other
types of substrates may also be useful. One or more circuit
elements may be formed over and/or within the substrate (not
illustrated). The circuit elements may include, for example,
transistors, capacitors, or combinations thereof.
[0024] An interlevel dielectric or metallization layer 120 may be
arranged over the substrate. For example, the interlevel dielectric
120 may be formed over the components on the substrate. The
interlevel dielectric 120, for example, may include a plurality of
interlevel dielectric (ILD) layers. The interlevel dielectric, for
example, may be formed by back-end-of-line (BEOL) processing, such
as in copper-based BEOL process, in a non-limiting embodiment. The
ILD layers of the interlevel dielectric 120, for example, may be
formed of dielectric materials, such as low-k dielectric (e.g.,
SiCOH), tetraethyl orthosilicate (TEOS), silicon oxide, silicon
nitride and etc. The dielectric layers may be formed by chemical
vapor deposition (CVD) or physical vapor deposition (PVD). Other
suitable material and techniques for forming the ILD layers may
also be useful.
[0025] The interlevel dielectric 120 may include interconnects
disposed in the ILD layers (not fully illustrated in the interest
of brevity). The interconnects connect the various components of
the IC to perform the desired functions. For example, the
interlevel dielectric 120 may include a plurality of interconnect
levels. Each interconnect level i may include a metal level M and a
contact or via level V.sub.i-1. The first interconnect level in the
case i=1, for example, may include metal lines M1 and via contacts
CA. The subsequent interconnect level, for example in the case i=2,
may include metal lines M2 and via contacts V1. For example, a
metal level may include metal or conductive lines, while a contact
level may include via contacts. It is understood that there may be
a plurality of metal lines in the same metal level, and a plurality
of via contacts in the same contact level. The number of
interconnect levels may depend on, for example, design
requirements.
[0026] The metal lines and via contacts may be formed of metals,
such as copper (Cu), copper alloy, aluminum (Al), or a combination
thereof. Other suitable types of metal, alloys, or conductive
materials for the interconnects may also be useful. The via
contacts and metal lines of an interconnect level may be of the
same type of conductive material or of different types of
materials. For example, in upper levels of the interlevel
dielectric 120, the metal lines and via contacts may be formed by
dual damascene processes. This results in the metal lines and via
contacts having the same material. Where the metal lines and via
contacts are formed by single damascene processes, the materials of
the metal lines and via contacts may be different.
[0027] According to various non-limiting embodiments, a thin film
based passive component may be arranged in the interlevel
dielectric 120. The thin film based passive component may be
arranged between any metal level in the interlevel dielectric 120
(e.g., between M1 and M2, between M2 and M3, between M3 and M4,
etc., up to the uppermost metal level). According to various
non-limiting embodiments, a thin film 150 of the passive component
may be arranged over a first ILD layer 122 in an interconnect level
i 124 of the interlevel dielectric 120, where i may be from 1 to x.
In a non-limiting example, x may be 10 in the case the interlevel
dielectric 120 is designed with ten interconnect levels. It is
understood that other numbers of interconnect levels may also be
applicable. The interconnect level i may include a first
interconnect 130 and a second interconnect 140 therein. The first
interconnect 130 and the second interconnect 140 may each include a
metal line in metal level i and a via contact in via level 1-1 of
the interconnect level i 124. As illustrated in FIGS. 1A-1E, the
first ILD layer 122 may include the first interconnect 130 and the
second interconnect 140. For example, the first ILD layer 122 may
at least surround the metal lines of the first interconnect 130 and
the second interconnect 140. The first ILD layer 122 may be formed
of dielectric materials, such as low-k dielectric (e.g., SiCOH),
TEOS, silicon oxide, silicon nitride, or combinations thereof. The
first interconnect 130 and the second interconnect 140 may be
single damascene structures or dual damascene structures.
[0028] According to various non-limiting embodiments, a nitride
block insulator 160 may be arranged over the first ILD layer 122
and over the first interconnect 130 and the second interconnect
140. As illustrated in FIGS. 1A-1E, the nitride block insulator 160
may be arranged beneath the thin film 150. The nitride block
insulator 160 may be a nitride-based insulator. In other words, the
nitride block insulator 160 may include a nitride-containing layer.
The nitride block insulator 160 may be formed of one or more layers
of silicon nitride, silicon oxynitride, silicon oxide, or
combinations thereof, in a non-limiting example. According to
various non-limiting embodiments, the nitride block insulator 160
may have a thickness ranging from about 300 A to about 1000 A, in a
non-limiting example.
[0029] One or more openings 165 may be arranged in the nitride
block insulator 160. An opening 165 may extend through the nitride
block insulator 160 to expose a surface (e.g., top surface) of an
interconnect in the first ILD layer 122. As illustrated in FIGS.
1A-1B, a first opening 165.sub.1 and a second opening 165.sub.2 may
extend through the nitride block insulator 160 to expose a surface
of the first interconnect 130 and the second interconnect 140 in
the first ILD layer 122, respectively.
[0030] A contact plug 170 may be arranged in each opening 165 of
the nitride block insulator 160. The contact plug 170 at least
lines the opening 165 and prevents out-diffusion of conductive
material from the interconnect in the ILD layer 122 over which it
is disposed. For example, a first contact plug 170.sub.1 at least
lines the first opening 165.sub.1 and prevents out-diffusion of
conductive material from the first interconnect 130. Similarly, a
second contact plug 170.sub.2 at least lines the second opening
165.sub.2 and prevents out-diffusion of conductive material from
the second interconnect 140. The contact plug 170 may be formed of
tungsten (W), tantalum (Ta), titanium (Ti), tantalum nitride (TaN),
titanium nitride (TiN), or combinations thereof, in a non-limiting
example. Other types of material for the contact plug may also be
useful.
[0031] The thin film 150 may be arranged over the nitride block
insulator 160 and over the contact plug 170. The thin film 150 may
be formed of silicon chromium (SiCr), TiN, TaN, metallic mixtures,
mixtures of ceramic-metal (cermet), or combinations thereof, in a
non-limiting example. The material of the thin film 150 may include
additional organic and/or inorganic elements, in a non-limiting
embodiment. In other embodiments, the material of the thin film 150
may be provided without additional organic and/or inorganic
elements. The yield properties (e.g., sheet resistivity, voltage
coefficient of resistance (VCR), temperature coefficient of
resistance (TCR)) of mixture elements can be tailored accordingly
as desired. According to various non-limiting embodiments, the thin
film 150 may have a thickness ranging from about 10 A to about 1500
A, in a non-limiting example.
[0032] According to various non-limiting embodiments, the contact
plug 170 fills the opening 165 in the nitride block insulator 160.
As illustrated in FIG. 1A, the contact plug 170 and the nitride
block insulator 160 may have a substantially planar top surface.
Accordingly, the thin film 150 may be arranged over the nitride
block insulator 160 such that it is substantially planar.
[0033] According to various non-limiting embodiments, the contact
plug 170 lines the opening 165 in the nitride block insulator 160.
For example, the contact plug 170 lines sidewalls and a bottom of
the opening 165 in the nitride block insulator 160, without
completely filling the opening 165, as illustrated in FIG. 1B.
Accordingly, the thin film 150 may be arranged over the nitride
block insulator 160 such that the thin film 150 conforms to a
topography of the nitride block insulator 160 and the contact plug
170 (i.e., thin film 150 conformal to the underlying nitride block
insulator 160 and the contact plug 170).
[0034] According to various non-limiting embodiments, the thin film
150 covers the first contact plug 170.sub.1 and the second contact
plug 170.sub.2 and serves as a thin film resistor. The thin film
resistor electrically connects the first interconnect 130 and the
second interconnect 140, as illustrated in FIGS. 1A and 1B. For
example, the thin film resistor may have a bottom pick-up
configuration. The first contact plug 170.sub.1 and the second
contact plug 170.sub.2 form conductive paths between the thin film
resistor 150 and interconnects 130 and 140. The conductive paths of
the thin film resistor are formed without arranging via contacts
between the thin film 150 and the interconnects 130 and 140.
[0035] According to various non-limiting embodiments, etch stop
liners may be arranged in the interlevel dielectric 120. For
example, a first nitride liner 182 and a second nitride liner 184
may be arranged in the interconnect level i. The first nitride
liner 182 and the second nitride liner 184 may be arranged beneath
the metal lines in the interconnect level i. For example, the first
nitride liner 182 and the second nitride liner 184 may be arranged
between metal lines in interconnect level i and metal lines in a
preceding interconnect level i-1. The etch stop liners may be used
as an etch stop layer for the via etch process for forming the
interconnects. The etch stop liners may be formed of silicon
nitride, in a non-limiting embodiment. In other embodiments, such
as in a dual damascene interconnect structure, the second nitride
liner 184 may not be formed below the metal lines in the
interconnect level i.
[0036] According to various non-limiting embodiments, the thin film
embedded in the interlevel dielectric 120 may be a thin film
capacitor, as will be described with respect to FIGS. 1C-1E.
[0037] According to various non-limiting embodiments, the thin film
150, the nitride block insulator 160, and the first interconnect
130 and the second interconnect 140 may form a
metal-insulating-metal (MIM) capacitor. A contact plug 170
electrically connects the thin film 150 and the first interconnect
130. According to various non-limiting embodiments, the contact
plug 170 fills the opening 165 in the nitride block insulator 160.
The contact plug 170 and the nitride block insulator 160 may have a
substantially planar top surface. The thin film 150 of the
capacitor may be arranged over the nitride block insulator 160 such
that it is substantially planar.
[0038] In other embodiments, the contact plug 170 lines the opening
165 in the nitride block insulator 160 without completely filling
the opening 165, as illustrated in FIG. 1D. The thin film 150 of
the capacitor may be arranged over the nitride block insulator 160
such that the thin film 150 conforms to a topography of the nitride
block insulator 160 and the contact plug 170 (i.e., thin film 150
conformal to the underlying nitride block insulator 160 and the
contact plug 170).
[0039] According to various non-limiting embodiments, a second thin
film 185 of the capacitor may be arranged over the first interlevel
dielectric layer 122 and beneath the nitride block insulator 160,
as illustrated in FIG. 1D. The second thin film 185 contacts the
second interconnect 140. The second thin film 185 may cover a
surface of the second interconnect 140. The nitride block insulator
160 may be sandwiched between the thin film 150 and the second thin
film 185 forming the MIM capacitor, in a non-limiting embodiment.
For example, the thin film 150 and the second thin film 185 serves
as top and bottom plates of an embedded capacitor in the interlevel
dielectric 120 and forms conductive paths with the interconnects
130 and 140. As illustrated in FIG. 1D, the first nitride liner 182
and the second nitride liner 184 may be arranged between metal
lines in interconnect level i and metal lines in a preceding
interconnect level i-1, in a non-limiting embodiment.
[0040] In another non-limiting embodiment, the back-end capacitor
(e.g., including thin film 150 and second thin film 185 serving as
top and bottom plates) may be formed over the first interconnect
level, i.e., i=1. The metal lines M1 in the first interconnect 130
and the second interconnect 140 may be coupled to the substrate by
via contacts CA. For example, the via contacts CA may be formed by
tungsten. The via contacts CA may be coupled to the semiconductor
substrate through salicided region over the substrate. In the case
the interconnect level i=1 for the back-end capacitor, the second
nitride liner 184 may be provided below M1, while the first nitride
liner 182 is not needed.
[0041] According to various non-limiting embodiments, the first
interconnect 130 and the second interconnect 140 may each include a
plurality of interconnected metal fingers.
[0042] According to various non-limiting embodiments, the thin film
150 may be arranged to have a plurality of interconnected film
fingers over the nitride block insulator 160.
[0043] According to various non-limiting embodiments, the second
thin film 185 may be arranged in the same level as the thin film
150. As shown in FIG. 1E, the second thin film 185 of the passive
component (e.g., capacitor) may be arranged over the nitride block
insulator 160, where the thin film 150 and the second thin film 185
may be arranged to form an alternating polarity MIM capacitor with
the first interconnect 130 and the second interconnect 140. The
nitride block insulator 160 may be sandwiched between the thin
films 150 and 185 and the first interconnect 130 and the second
interconnect 140, as illustrated in FIG. 1E.
[0044] A first opening 165.sub.1 and a second opening 165.sub.2 may
be arranged in the nitride block insulator 160 and may extend
through the nitride block insulator 160 to expose a surface of the
first interconnect 130 and the second interconnect 140 in the first
ILD layer 122, respectively. A first contact plug 170.sub.1 at
least lines the first opening 165.sub.1 and prevents out-diffusion
of conductive material from the first interconnect 130. Similarly,
a second contact plug 170.sub.2 at least lines the second opening
165.sub.2 and prevents out-diffusion of conductive material from
the second interconnect 140. The thin film 150 contacts and may
cover first contact plug 170.sub.1, while the second thin film 185
contacts and may cover the second contact plug 170.sub.2. The first
contact plug 170.sub.1 electrically connects the thin film 150 and
the first interconnect 130, while the second contact plug 170.sub.2
electrically connects the second thin film 185 and the second
interconnect 140.
[0045] According to various non-limiting embodiments, the thin film
150 may include a plurality of interconnected first film fingers
coupled to the first interconnect 130, while the second thin film
185 may include a plurality of interconnected second film fingers
coupled to the second interconnect 140. Each first film finger may
be arranged alternately with a second film finger for forming the
alternating polarity MIM capacitor.
[0046] The one or more thin films of the passive component (e.g.,
thin film 150, second thin film 185) and the first interconnect 130
and the second interconnect 140 as described with respect to FIGS.
1C-1E may be a one metal-stack back-end capacitor. It is understood
that other numbers of metal-stacks such as two metal-stack, three
metal-stack, four metal-stack, five metal-stack, six metal-stack,
or seven metal-stack may be arranged in other embodiments depending
on connection between each level through via contacts.
[0047] FIG. 2 illustrates another simplified cross-sectional view
of an embodiment of the device 100. According to various
non-limiting embodiments, the device 100 may relate to a back-end
capacitor and may include a multi metal-stack back-end capacitor
embedded in the interlevel dielectric 120. A pair of thin film 150
and second thin film 185, each having interconnected film fingers
arranged in alternating order, may be formed over various
interconnect levels of the interlevel dielectric 120. For example,
a three metal-stack back-end capacitor (e.g., three metal-stack
alternating polarity MIM) may be arranged in the interlevel
dielectric 120.
[0048] FIGS. 3A-3E show simplified cross-sectional views of a
process 300 for forming a device. The device formed, for example,
is similar or the same as that shown and described in FIG. 1A.
Common elements may not be described or described in detail. As
illustrated in FIG. 3A, a substrate 105 may be provided. The
substrate may be a semiconductor substrate, such as a silicon
substrate in a non-limiting embodiment. Other types of substrates
may also be useful. For simplicity of discussion and in the
interest of brevity, the processing of the substrate to form one or
more circuit elements are not described. An interlevel dielectric
120 may be arranged over the substrate 105. The interlevel
dielectric 120 may be formed by BEOL processing. Arranging the
interlevel dielectric 120 may include forming a plurality of ILD
layers and interconnects in the plurality of ILD layers depending
on the design and number of interconnect levels in the interlevel
dielectric 120. In a non-limiting example, the ILD layers may be
formed by deposition such as plasma-enhanced chemical vapor
deposition (PECVD). For example, the ILD layers may be patterned to
form via openings and trenches by mask and etch techniques. For
example, a via opening and a trench may be formed in an
interconnect level for forming a via contact and a metal line.
Metal may be deposited over the ILD layer, and a planarization
process may be performed to form interconnects in the interconnect
level. Other suitable material and techniques for forming the
interlevel dielectric may also be useful. In the case the
interconnect is formed of Cu (e.g., in a Cu BEOL process), a
barrier layer, such as TaN in a non-limiting example, may be
deposited prior to deposition of Cu to form the metal line and the
via contact so as to prevent out-diffusion of Cu into the ILD
layer.
[0049] According to various non-limiting embodiments, a first
interlevel dielectric layer 122 may be formed in an interconnect
level i 124. The interconnect level i 124 may be arranged over one
or more lower interconnect levels in the case of forming a thin
film resistor, in a non-limiting example. For example, the first
interlevel dielectric layer 122 may include a first interconnect
130 and a second interconnect 140. A nitride block insulator 160
may be formed over the first interlevel dielectric layer 122. The
nitride block insulator 160 may be formed after the planarization
process to form the interconnects (e.g., first interconnect 130 and
a second interconnect 140) in the first interlevel dielectric layer
122. The nitride block insulator 160 may be deposited by CVD or
PVD, in a non-limiting example.
[0050] One or more openings 165 (e.g., first opening 165.sub.1 and
second opening 165.sub.2) may be formed in the nitride block
insulator 160, as illustrated in FIG. 3B. The first opening
165.sub.1 and the second opening 165.sub.2 may be formed by mask
and etch techniques, in a non-limiting example. The first opening
165.sub.1 and the second opening 165.sub.2 extends through the
nitride block insulator 160 to expose a top surface of the first
interconnect 130 and the second interconnect 140 in the first
interlevel dielectric layer 122. The mask may be removed after
patterning the opening 165.
[0051] A contact plug may be formed in the first opening 165.sub.1
and second opening 165.sub.2 of the nitride block insulator, where
the contact plug at least lines the first opening 165.sub.1 and
second opening 165.sub.2 and prevents out-diffusion of conductive
material from the underlying interconnects. Referring to FIG. 3C, a
contact plug material 310 may be deposited over the nitride block
insulator 160 to fill the opening 165 in the nitride block
insulator 160 for forming the contact plug. The contact plug
material 310 may be formed by PVD or CVD, in a non-limiting
example. A planarization process, such as chemical mechanical
polishing (CMP) in a non-limiting example, may be performed to
provide a substantially planar top surface between the nitride
block insulator 160 and the contact plug 170. For example, a first
contact plug 170.sub.1 may be formed in the first opening
165.sub.1, and a second contact plug 170.sub.2 may be formed in the
second opening 165.sub.2 of the nitride block insulator 160.
[0052] A thin film 150 of a passive component may be formed over
the nitride block insulator 160 and over the first contact plug
170.sub.1 and the second contact plug 170.sub.2. For example, a
layer of the thin film 150 may be deposited or sputtered over the
nitride block insulator 160. The layer of the thin film 150 may be
formed by blanket deposition. The layer of the thin film 150 may be
patterned by mask and etch techniques to a desired active area of
the thin film resistor. For example, the thin film 150 may be etch
to a desired width and length. As illustrated in FIG. 3E, the thin
film 150 covers the first contact plug 170.sub.1 and the second
contact plug 170.sub.2 and serves as a thin film resistor. The thin
film resistor electrically connects the first interconnect 130 and
the second interconnect 140.
[0053] The process, for example, may continue to form additional
dielectric layers (e.g., one or more TEOS layers and additional
interconnect levels) and interconnects for the interlevel
dielectric 120 until the uppermost interconnect in the interlevel
dielectric 120.
[0054] FIGS. 4A-4D show simplified cross-sectional views of another
exemplary process 400 for forming a device. The device formed, for
example, is similar or the same as that shown and described in FIG.
1B. Common elements may not be described or described in
detail.
[0055] The process 400 may be similar to process 300 as described
in FIGS. 3A-3B. As illustrated in FIG. 4A, the first opening
165.sub.1 and the second opening 165.sub.2 may be formed in the
nitride block insulator 160 using a patterned hard mask 420. The
patterned hard mask 420 may be removed prior to forming the contact
plug. The contact plug may be formed in the first opening 165.sub.1
and the second opening 165.sub.2 of the nitride block insulator 160
by depositing or sputtering contact plug material to at least line
the first opening 165.sub.1 and the second opening 165.sub.2 in the
nitride block insulator 160. For example, the contact plug material
may be deposited to a thickness ranging from about 300 A to about
1000 A. Excess contact plug material external to the first opening
165.sub.1 and the second opening 165.sub.2 may be removed by a
planarization process such as CMP. FIG. 4B illustrates the first
contact plug 170.sub.1 and the second contact plug 170.sub.2 lining
the first opening 165.sub.1 and the second opening 165.sub.2,
respectively.
[0056] The thin film 150 of the passive component may be formed
over the nitride block insulator 160 and over the first contact
plug 170.sub.1 and the second contact plug 170.sub.2. For example,
a layer of the thin film 150 may be deposited or sputtered over the
nitride block insulator 160, as illustrated in FIG. 4C. The thin
film 150 may be patterned by mask and etch techniques. The thin
film 150 may be etched to a desired width and length, forming a
desired active area of the thin film resistor. The thin film 150
may be etched such that it completely covers a top surface of the
first contact plug 170.sub.1 and the second contact plug 170.sub.2.
As illustrated in FIG. 4D, the thin film 150 may be conformal to a
topography of the nitride block insulator 160 and the first contact
plug 170.sub.1 and the second contact plug 170.sub.2.
[0057] FIGS. 5A-5C show simplified cross-sectional views of another
exemplary process 500 for forming a device. The device formed, for
example, is similar or the same as that shown and described in
FIGS. 1C-1E. For example, the process 500 may be used to form a
back-end thin film capacitor. Common elements may not be described
or described in detail.
[0058] The process 500 may be similar to that described with
respect to FIGS. 3A-3E and FIGS. 4A-4D. As shown in FIG. 5A, the
nitride block insulator 160 may be formed over the first interlevel
dielectric layer 122. In some embodiments, a second thin film of
the passive component may be formed prior to forming the nitride
block insulator 160. For example, the second thin film of the
passive component may contact and cover a top surface of the second
interconnect 140 (not shown in FIG. 5A).
[0059] Referring to FIG. 5B, an opening 165 may be formed in the
nitride block insulator 160. A contact plug 170 may be formed in
the opening of the nitride block insulator 160. The contact plug
170 at least lines the opening and prevents out-diffusion of
conductive material from the first interconnect 130, as illustrated
in FIG. 5C. A layer of thin film for the passive component may be
deposited over the nitride block insulator 160 by sputtering, in a
non-limiting example, and may be patterned by mask and etch
techniques. The layer of the thin film may be patterned to define
an active area of a thin film 150, as illustrated in FIG. 5C. For
example, the thin film 150 may be arranged over the nitride block
insulator 160 and over the contact plug 170. The thin film 150
contacts the first interconnect 130. In other embodiments, the
layer of the thin film may be patterned to define an active area of
the thin film 150 and a second thin film 185, as illustrated in
FIG. 1E.
[0060] The process, for example, may continue to form additional
dielectric layers (e.g., additional interconnect levels) and
interconnects for the interlevel dielectric 120 until the uppermost
interconnect.
[0061] FIG. 6A shows a simplified perspective view of an embodiment
of the device 100. For example, the thin film 150 may be patterned
to define an active area of a thin film resistor in the interlevel
dielectric 120. The thin film 150 may cover the first contact plug
and the second contact plug (not visible in FIG. 6A) disposed in
the nitride block insulator 160. The thin film resistor
electrically connects the first interconnect 130 and the second
interconnect 140.
[0062] FIGS. 6B-6D show simplified perspective views of an
embodiment of the device 100 having a thin film capacitor embedded
in the interlevel dielectric 120. As illustrated in FIG. 6B, the
first interconnect 130 and the second interconnect 140 may be
arranged in the first interlevel dielectric layer 122. The first
interconnect 130 and the second interconnect 140 in the first
interlevel dielectric layer 122 may be metal lines in the metal
level (e.g., M1, M2, M3, etc.). As illustrated in FIG. 6C, the
nitride block insulator 160 may be arranged over the first
interlevel dielectric layer 122 and the first interconnect 130 and
the second interconnect 140. The first contact plug 170.sub.1 and
the second contact plug 170.sub.2 may be arranged in the nitride
block insulator 160 to contact the first interconnect 130 and the
second interconnect 140, respectively. FIG. 6D illustrates thin
film 150 and second thin film 185 arranged over the nitride block
insulator 160. As described, a layer of thin film may be sputtered
over the nitride block insulator 160. The layer of thin film may be
patterned to define an active area of the thin film 150 and a
second thin film 185. The thin film 150 contacts and may cover
first contact plug 170.sub.1, while the second thin film 185
contacts and may cover the second contact plug 170.sub.2. The first
contact plug 170.sub.1 electrically connects the thin film 150 and
the first interconnect 130, while the second contact plug 170.sub.2
electrically connects the second thin film 185 and the second
interconnect 140.
[0063] The invention may be embodied in other specific forms
without departing from the spirit or essential characteristics
thereof. The foregoing embodiments, therefore, are to be considered
in all respects illustrative rather than limiting the invention
described herein. Scope of the invention is thus indicated by the
appended claims, rather than by the foregoing description, and all
changes that come within the meaning and range of equivalency of
the claims are intended to be embraced therein.
* * * * *