U.S. patent application number 17/111867 was filed with the patent office on 2021-03-25 for silicon film forming method and substrate processing apparatus.
The applicant listed for this patent is TOKYO ELECTRON LIMITED. Invention is credited to Keisuke FUJITA, Tatsuya MIYAHARA, Mitsuhiro OKADA.
Application Number | 20210090887 17/111867 |
Document ID | / |
Family ID | 1000005253522 |
Filed Date | 2021-03-25 |
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United States Patent
Application |
20210090887 |
Kind Code |
A1 |
OKADA; Mitsuhiro ; et
al. |
March 25, 2021 |
SILICON FILM FORMING METHOD AND SUBSTRATE PROCESSING APPARATUS
Abstract
There is provided a method of forming a silicon film, which
includes: a film forming step of forming the silicon film on a
base, the silicon film having a film thickness thicker than a
desired film thickness; and an etching step of reducing the film
thickness of the silicon film by supplying an etching gas
containing bromine or iodine to the silicon film.
Inventors: |
OKADA; Mitsuhiro; (Nirasaki
City, JP) ; MIYAHARA; Tatsuya; (Nirasaki City,
JP) ; FUJITA; Keisuke; (Nirasaki City, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TOKYO ELECTRON LIMITED |
Tokyo |
|
JP |
|
|
Family ID: |
1000005253522 |
Appl. No.: |
17/111867 |
Filed: |
December 4, 2020 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
16291485 |
Mar 4, 2019 |
10892162 |
|
|
17111867 |
|
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/02645 20130101;
H01L 21/02664 20130101; H01L 21/02592 20130101; C23C 14/542
20130101; H01L 21/02532 20130101; C23C 14/5873 20130101; H01L
21/3065 20130101; C23C 14/14 20130101; H01L 21/0262 20130101 |
International
Class: |
H01L 21/02 20060101
H01L021/02; C23C 14/58 20060101 C23C014/58; H01L 21/3065 20060101
H01L021/3065; C23C 14/14 20060101 C23C014/14; C23C 14/54 20060101
C23C014/54 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 5, 2018 |
JP |
2018-038719 |
Claims
1-10. (canceled)
11. A method of forming a silicon film, the method comprising: a
film forming step of forming the silicon film on a base; and an
etching step of reducing a film thickness of the silicon film by
supplying an etching gas containing bromine or iodine to the
silicon film, wherein concave-convex portions are formed in a
surface of the base, and wherein the etching step includes etching
the silicon film formed on the concave-convex portions of the base
in a conformal manner.
12. The method of claim 11, wherein the film thickness of the
silicon film is a film thickness at which no pinhole is
generated.
13. The method of claim 11, wherein the film forming step includes:
a seed layer forming step of forming a seed layer on a surface of
the base by supplying an aminosilane-based gas onto the base; and a
first silicon film forming step of forming another silicon film on
the seed layer by supplying an amino group-free silane-based gas
onto the seed layer.
14. The method of claim 13, further comprising: a second silicon
film forming step of supplying a higher-order silane-based gas than
the amino group-free silane-based gas used in the first silicon
film forming step to the seed layer between the seed layer forming
step and the first silicon film forming step.
15. The method of claim 11, wherein the film forming step includes
forming the silicon film on the concave-convex portions of the base
in a conformal manner.
16. The method of claim 11, wherein the film forming step and the
etching step are successively performed in a same processing
chamber.
17. The method of claim 11, wherein the etching step is performed
at a temperature higher than a temperature in the film forming
step.
18. The method of claim 11, wherein the etching gas is at least one
selected from a group consisting of a Br2 gas, an HBr gas, an I2
gas, and an HI gas.
19. The method of claim 11, wherein a surface roughness of the
silicon film decreases in the etching step.
20. A substrate processing apparatus comprising: a processing
container in which a substrate is accommodated; a gas supply part
configured to introduce a film-forming gas and an etching gas into
the processing container; and a controller configured to perform a
control such that a silicon film is formed on the substrate, and
the etching gas containing bromine or iodine is supplied onto the
silicon film to reduce the film thickness of the silicon film,
wherein concave-convex portions are formed in a surface of the
substrate, and wherein the silicon film formed on the
concave-convex portions of the substrate is etched in a conformal
manner.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of Japanese Patent
Application No. 2018-038719, filed on Mar. 5, 2018, in the Japan
Patent Office, the disclosure of which is incorporated herein in
its entirety by reference.
TECHNICAL FIELD
[0002] The present disclosure relates to a silicon film forming
method and a substrate processing apparatus.
BACKGROUND
[0003] Conventionally, there is known a method of supplying an
aminosilane-based gas to a base to form a seed layer and supplying
an amino group-free silane-based gas to the seed layer to form a
silicon film, thereby reducing the thickness of the silicon film.
In addition, there is also known a method of forming an amorphous
silicon film on a base and then dry-etching the amorphous silicon
film using Cl.sub.2 gas to reduce the film thickness of the
amorphous silicon film, thereby reducing the thickness of the
amorphous silicon film and smoothing the surface of the amorphous
silicon film. In this method, it is possible to form a thin silicon
film, which has good surface smoothness and has no pinhole.
[0004] However, with the methods described above, it is difficult
to reduce the thickness of a silicon film to meet the needs of
further film thickness reduction.
SUMMARY
[0005] Some embodiments of the present disclosure provide a method
capable of forming an ultra-thin silicon film, which has good
surface smoothness.
[0006] According to one embodiment of the present disclosure, there
is provided a method of forming a silicon film, the method
including: a film forming step of forming the silicon film on a
base, the silicon film having a film thickness thicker than a
desired film thickness, and an etching step of reducing the film
thickness of the silicon film by supplying an etching gas
containing bromine or iodine to the silicon film.
[0007] According to another embodiment of the present disclosure,
there is provided a substrate processing apparatus including: a
processing container in which a substrate is accommodated; a gas
supply part configured to introduce a film-forming gas and an
etching gas into the processing container; and a controller
configured to perform a control such that a silicon film having a
film thickness thicker than a desired film thickness is formed on
the substrate, and the etching gas containing bromine or iodine is
supplied onto the silicon film to reduce the film thickness of the
silicon film.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The accompanying drawings, which are incorporated in and
constitute a part of the specification, illustrate embodiments of
the present disclosure, and together with the general description
given above and the detailed description of the embodiments given
below, serve to explain the principles of the present
disclosure.
[0009] FIG. 1 is a cross-sectional view illustrating an example of
a vertical heat treatment apparatus according to an embodiment of
the present disclosure.
[0010] FIG. 2 is a view for explaining a processing container of
the vertical heat treatment apparatus of FIG. 1.
[0011] FIG. 3 is a flowchart illustrating an example of a silicon
film forming method according to an embodiment of the present
disclosure.
[0012] FIGS. 4A to 4C are views for explaining a method of
evaluating the presence or absence of pinholes.
[0013] FIG. 5 is a view showing an SEM image on a surface of a
silicon film.
[0014] FIG. 6 is a view showing an SEM image on the surface of the
silicon film.
[0015] FIG. 7 is a view showing an SEM image on the surface of the
silicon film.
[0016] FIG. 8 is a view showing an SEM image on the surface of the
silicon film.
[0017] FIG. 9 is a diagram representing the relationship between a
film thickness of the silicon film and the number of pinholes.
[0018] FIGS. 10A and 10B are views illustrating a sectional shape
of a line-and-space pattern, respectively.
[0019] FIG. 11 is a diagram representing a dependence of an etching
rate of an etching gas on temperature in an a-Si film.
DETAILED DESCRIPTION
[0020] Hereinafter, embodiments for carrying out the present
disclosure will be described with reference to drawings. In the
subject specification and the drawings, components having
substantially identical configurations will be designated by like
reference numerals with the duplicate descriptions thereof omitted.
In the following detailed description, numerous specific details
are set forth in order to provide a thorough understanding of the
present disclosure. However, it will be apparent to one of ordinary
skill in the art that the present disclosure may be practiced
without these specific details. In other instances, well-known
methods, procedures, systems, and components have not been
described in detail so as not to unnecessarily obscure aspects of
the various embodiments.
[Overall Configuration of Substrate Processing Apparatus]
[0021] A substrate processing apparatus capable of carrying out a
silicon film forming method according to an embodiment of the
present disclosure will be described by taking, as an example, a
batch-type vertical heat treatment apparatus. FIG. 1 is a
cross-sectional view illustrating an example of a vertical heat
treatment apparatus according to an embodiment of the present
disclosure.
[0022] A substrate processing apparatus 1 includes a processing
container 34 configured to accommodate a semiconductor wafer
(hereinafter referred to as a "wafer W") as a substrate, a lid part
36 configured to hermetically close an opening defined at a lower
end of the processing container 34, a wafer boat 38 as a substrate
holder received in the processing container 34 and configured to
hold a plurality of wafers W at predetermined intervals, a gas
supply part 40 configured to introduce a predetermined gas into the
processing container 34, an exhaust part 40 configured to exhaust
gas from the processing container 34, and a heating part 42
configured to heat the wafer W.
[0023] The processing container 34 includes a cylindrical inner
tube 44 having a ceiling and an opened lower end portion, and a
cylindrical outer tube 46 having a ceiling and an opened lower end
portion. The cylindrical outer tube 46 covers the outer side of the
inner tube 44. The inner tube 44 and the outer tube 46 are formed
of a heat-resistant material such as quartz, and are arranged in a
coaxial relationship with each other to form a double-tube
structure.
[0024] A ceiling portion 44A of the inner tube 44 is, for example,
flat. A nozzle accommodation portion 48 in which gas nozzles are
accommodated is formed at one side of the inner tube 44 along the
longitudinal direction (vertical direction). In the embodiment of
the present disclosure, as illustrated in FIG. 2, a portion of a
sidewall of the inner tube 44 protrudes outward so as to form a
convex portion 50. An interior of the convex portion 50 is defined
as the nozzle accommodation portion 48.
[0025] In addition, in a portion facing the nozzle accommodation
portion 48 in the sidewall of the inner tube 44, a rectangular
opening 52 having a width L1 is formed in the longitudinal
direction (vertical direction).
[0026] The opening 52 functions as a gas exhaust port formed
exhaust gas from the inner tube 44. In some embodiments, a vertical
length of the opening 52 is equal to a vertical of the wafer boat
38. Alternatively, the vertical length of the opening 52 may extend
upwards and downwards in the vertical direction to be longer than
the vertical length of the wafer boat 38. That is to say, an upper
end of the opening 52 extends to a height equal to or higher than a
position corresponding to an upper end of the wafer boat 38, and a
lower end of the opening 52 extends to a height equal to or less
than a position corresponding to a lower end of the wafer boat 38.
Specifically, as illustrated in FIG. 1, a distance L2 in the height
direction between the upper end of the wafer boat 38 and the upper
end of the opening 52 falls within a range of about 0 mm to 5 mm. A
distance L3 in the height direction between the lower end of the
wafer boat 38 and the lower end of the opening 52 falls within a
range of about 0 mm to 350 mm.
[0027] The lower end of the processing container 34 is supported by
a cylindrical manifold 54 made of, for example, stainless steel. A
flange portion 56 is formed on an upper end of the manifold 54. The
lower end portion of the outer tube 46 is installed on the flange
portion 56 so that the outer tube 46 is supported on the flange
portion 56. A seal member 58 such as an O-ring is interposed
between the flange portion 56 and the lower end portion of the
outer tube 46 to hermetically seal the interior of the outer tube
46.
[0028] A circular ring-shaped supporting portion 60 is formed on an
upper inner wall of the manifold 54. The lower end portion of the
inner tube 44 is installed on the supporting portion 60 so that the
inner tube 44 is supported on the supporting portion 60. The lid
part 36 is hermetically installed to an opening defined at a lower
end of the manifold 54 via a seal member 62 such as an O-ring.
Thus, the opening at the lower end of the processing container 34,
namely the opening of the manifold 54, is hermetically sealed. The
lid part 36 is formed of, for example, stainless steel.
[0029] A rotary shaft 66 is provided in the central portion of the
lid part 36 so as to penetrate through a magnetic fluid seal part
64. A lower end of the rotary shaft 66 is rotatably supported by an
arm 68A of a lift part 68 such as a boat elevator.
[0030] A rotary plate 70 is provided on an upper end of the rotary
shaft 66. The wafer boat 38 that holds the wafers W is mounted on
the rotary plate 70 via a quartz heat-insulating base 72. With this
configuration, by moving the lift part 68 up and down, the lid part
36 and the wafer boat 38 move vertically as a unit, so that the
wafer boat 38 can be inserted into and removed from the processing
container 34.
[0031] The gas supply part 40 is provided in the manifold 54 and
supplies gases such as a processing gas and a purge gas into the
inner tube 44. The gas supply part 40 includes a plurality of
(e.g., three) quartz-made gas nozzles 76, 78, and 80. Each of the
gas nozzles 76, 78, 80 is installed inside the inner tube 44 in the
longitudinal direction. A base end of each of the gas nozzles 76,
78, 80 is bent in an L shape and penetrates through the manifold 54
so that the gas nozzles 76, 78, 80 are supported by the manifold
54.
[0032] As illustrated in FIG. 2, the gas nozzles 76, 78, and 80 are
installed inside the nozzle accommodation portion 48 of the inner
tube 44 in a row along the circumferential direction. A plurality
of gas holes 76A, 78A, and 80A are formed in the respective gas
nozzles 76, 78, and 80 at predetermined intervals in the
longitudinal direction. The respective gases can be ejected
horizontally from each of the plurality of gas holes 76A, 78A, and
80A. The predetermined intervals are set, for example, to be equal
to intervals of the wafers W supported by the wafer boat 38. A
position of each of the gas holes 76A, 78A, and 80A in the height
direction is set such that each of the gas holes 76A, 78A, and 80A
is located in the middle between two wafers W adjacent to each
other in the vertical direction. Thus, each gas can be efficiently
supplied to a space defined between the respective two wafers
W.
[0033] Various kinds of gases such as a film-forming gas, an
etching gas, and a purge gas are used as the respective gases.
These gases can be supplied through the gas nozzles 76, 78, and 80,
respectively, while controlling the flow rates thereof as
necessary.
[0034] The film-forming gas may be, for example, a
silicon-containing gas. For example, aminosilane-based gases such
as diisopropylaminosilane (DIPAS), tris(dimethylamino)silane
(3DMAS), bis tertiary butylaminosilane (BTBAS) and the like, and
amino group-free silane-based gases such as SiH.sub.4 (monosilane),
Si.sub.2H.sub.6 (disilane), dichlorosilane (DCS),
hexachlorodisilane (HCD) and the like, may be used as the
silicon-containing gas.
[0035] The etching gas may be a gas containing bromine or iodine.
As the bromine-containing gas, for example, Br.sub.2 (bromine) and
HBr (hydrogen bromide) may be used. As the iodine-containing gas,
for example, I.sub.2 (iodine) and HI (hydrogen iodide) may be
used.
[0036] The purge gas may be an inert gas. As the inert gas, for
example, N.sub.2 (nitrogen) and Ar (argon) may be used.
[0037] A gas outlet 82 is formed in an upper sidewall of the
manifold 54 above the supporting portion 60. The gas exhausted from
the inner tube 44 through the opening 52 is exhausted from the gas
outlet 82 through a space 84 between the inner tube 44 and the
outer tube 46. An exhaust part 41 is provided in the gas outlet 82.
The exhaust part 41 includes an exhaust passage 86 connected to the
gas outlet 82. A pressure regulation valve 88 and a vacuum pump 90
are sequentially provided in the exhaust passage 86, so that the
interior of the processing container 34 can be evacuated.
[0038] The heating part 42 of a cylindrical shape is provided at
the side of an outer periphery of the outer tube 46 so as to cover
the outer tube 46. The heating part 42 heats the wafers W
accommodated in the processing container 34.
[0039] The entire operation of the substrate processing apparatus 1
configured as above is controlled by a control part 110 such as a
computer. A computer program that performs the entire operation of
the substrate processing apparatus 1 is stored in a storage medium
112. The storage medium 112 may be, for example, a flexible disk, a
compact disk, a hard disk, a flash memory, or a DVD.
[Silicon Film Forming Method]
[0040] A silicon film forming method according to an embodiment of
the present disclosure will be described. FIG. 3 is a flowchart
illustrating an example of the silicon film forming method
according to the embodiment of the present disclosure.
[0041] The silicon film forming method according to the embodiment
of the present disclosure includes a film forming step S1 of
forming a silicon film having a film thickness thicker than a
desired film thickness on a base, and an etching step S2 of
supplying an etching gas containing bromine or iodine onto the
silicon film to reduce the film thickness of the silicon film. In
the embodiment of the present disclosure, first, the wafer boat 38
which holds a plurality of wafers W at a predetermined interval is
loaded into the processing container 34. Subsequently, the film
forming step S1 and the etching step S2 are successively performed
inside the processing container 34 as a same processing chamber in
a vacuum atmosphere. Thus, the silicon film having a desired film
thickness is formed on each wafer W. In some embodiments, a purging
step of replacing the gas in the processing container 34 may be
performed between the film forming step and the etching step.
Subsequently, the wafer boat 38, which holds each wafer W on which
the silicon film is formed, is unloaded from the processing
container 34. The film forming step S1 and the etching step S2 may
be performed in different processing chambers.
[0042] The film forming step S1 is a step of forming a silicon film
having a film thickness thicker than a desired film thickness by
supplying a film-forming gas onto a base. The silicon film formed
in the film forming step S1 may be a silicon film having a thick
thickness, in which no pinhole is formed. The film thickness of the
silicon film may be selected depending on film-forming conditions
of the silicon film. For example, in a film-forming condition in
which pinholes are formed in a silicon film when the film thickness
is 25 .ANG. or less, in the film forming step S1, a silicon film
having a film thickness thicker than 25 .ANG. may be formed on a
base. As an example, a silicon film having a film thickness of 30
.ANG., which is thicker by 5 .ANG., may be formed on the base. That
is to say, a silicon film having a film thickness larger than a
pinhole limit by 5 .ANG. or more may be formed.
[0043] The film forming step S1 may include, for example, a seed
layer forming step of forming a seed layer on the surface of the
base by supplying an aminosilane-based gas to the base, and a
silicon film forming step of forming a silicon film on the seed
layer by supplying an amino group-free silane-based gas onto the
seed layer. In some embodiments, another silicon film forming step
of supplying a higher-order silane-based gas than the silane-based
gas used in the silicon film forming step onto the seed layer may
be included between the seed layer forming step and the silicon
film forming step. In some embodiments, a purging step of replacing
the gas in the processing container 34 may be included between the
respective steps.
[0044] The etching step S2 is a step of supplying an etching gas
containing bromine or iodine onto a silicon film to reduce a film
thickness of the silicon film, thus adjusting the film thickness of
the silicon film to a desired film thickness. At this time, the
etching of the silicon film using the etching gas containing
bromine or iodine becomes conformal etching without deteriorating
the surface roughness of the silicon film. Thus, even if the
silicon film has a concave-convex pattern having a large surface
area, the silicon film may be etched with enhanced controllability.
From the viewpoint of productivity, it is desirable to perform the
etching step S2 at a temperature higher than that in the film
forming step S1.
[0045] The purging step is a step of replacing the gas in the
processing container 34. In the purging step, a purge gas is
introduced into the processing container 34 from the gas nozzle 80
so that the film-forming gas and the etching gas remaining in the
processing container 34 are replaced with the purge gas.
[0046] As described above, the silicon film forming method
according to the embodiment of the present disclosure includes
forming the silicon film having a film thickness thicker than a
desired film thickness on the base. This makes it possible to
obtain a silicon film having fewer pinholes than those in the
silicon film having a desired film thickness. Subsequently, the
etching gas containing bromine or iodine is supplied onto the
silicon film to reduce the film thickness of the silicon film.
Thus, the film thickness of the silicon film is adjusted to a
desired film thickness. It is therefore possible to perform
conformal etching without deteriorating the surface roughness of
the silicon film. Even if the silicon film has a concave-convex
pattern having a large surface, it is possible to etch the silicon
film with enhanced controllability. As a result, it is possible to
form an ultra-thin silicon film which has good surface
smoothness.
Example 1
[0047] Example 1, from which the action and effect of the silicon
film forming method according to the embodiment of the present
disclosure was confirmed, will be described.
<Sample>
[0048] A sample fabricated in Example 1 will be described.
(Samples 1A to 1F)
[0049] A silicon film having a thickness of 50 .ANG. was formed on
each of the silicon substrates on each of which an oxide film is
formed (in the film forming step S1). Subsequently, the silicon
film was etched-back (in the etching step S2). As a result, silicon
films having film thicknesses of 19 .ANG., 20.ANG., 21.ANG.,
23.ANG., 25.ANG., and 26 .ANG. were formed. The silicon substrates
and the oxide films are examples of the base. The silicon film is
an example of a film to be evaluated for the presence or absence of
pinholes. The silicon substrates having the silicon films having
film thicknesses of 19 .ANG., 20 .ANG., 21 .ANG., 23 .ANG., 25
.ANG., and 26 .ANG. formed thereon are referred to as Samples 1A,
1B, 1C, 1D, 1E, and 1F, respectively. Process conditions used in
the film forming step S1 and the etching step S2 are as follows.
[0050] <Film forming Step S1 (seed layer forming step)>
[0051] Substrate temperature: 380 degrees C. [0052] Internal
pressure of processing container 34: 1.0 Torr (133.3 Pa) [0053]
Gas: DIPAS [0054] <Film forming Step S1 (silicon film forming
step)> [0055] Substrate temperature: 470 degrees C. [0056]
Internal pressure of processing container 34: 3.0 Torr (399.9 Pa)
[0057] GAS: DCS/SiH.sub.4 [0058] <Etching Step S2> [0059]
Substrate temperature: 550 degrees C. [0060] Internal pressure of
processing container 34: 20 to 80 Torr (2,666 to 10,666 Pa) [0061]
Gas: HBr
(Samples 2A to 2G)
[0062] Silicon films having film thicknesses of 25 .ANG., 27.7
.ANG., 33.7 .ANG., 34.8 .ANG., 39.5 .ANG., 42.8 .ANG., and 54.7
.ANG. were formed on silicon substrates each having an oxide film
formed thereon, respectively. The silicon substrates having the
silicon films having film thicknesses of 25 .ANG., 27.7 .ANG., 33.7
.ANG., 34.8 .ANG., 39.5 .ANG., 42.8 .ANG., and 54.7 .ANG. formed
thereon are referred to as Samples 2A, 2B, 2C, 2D, 2E, 2F, and 2G,
respectively. Process conditions used in the film forming step S1
were the same as those used in the samples 1A to 1F1.
(Sample 3A)
[0063] Sample 3A was obtained by forming a silicon film having a
film thickness of 50 .ANG. on a silicon substrate having an oxide
film formed thereon (in the film forming step S1), and etching back
the silicon film to have a film thickness of 15 .ANG. (in the
etching step S2). Process conditions used in the film forming step
S1 and the etching step S2 were as follows. [0064] <Film Forming
Step S1 (seed layer forming step)> [0065] Substrate temperature:
380 degrees C. [0066] Internal pressure of processing container 34:
1.0 Torr (133.3 Pa) [0067] Gas: DIPAS [0068] <Film Forming Step
S1 (another silicon film forming step)> [0069] Substrate
temperature: 380 degrees C. [0070] Internal pressure of processing
container 34: 1.0 Torr (133.3 Pa) [0071] Gas: Si.sub.2H.sub.6
[0072] <Film Forming Step S1 (silicon film firming step)>
[0073] Substrate temperature: 470 degrees C. [0074] Internal
pressure of processing container 34: 3.0 Torr (399.9 Pa) [0075]
GAS: DCS/SiH.sub.4 [0076] <Etching Step S2> [0077] Substrate
temperature: 550 degrees C. [0078] Internal pressure of processing
container 34: 20 to 80 Torr (2,666 to 10,666 Pa) [0079] Gas:
HBr
(Sample 4A)
[0080] Sample 4A was obtained by forming a silicon film having a
film thickness of 15 .ANG. on a silicon substrate having an oxide
film formed thereon. Process conditions used in the film forming
step S1 were the same as those used in Sample 3A.
<Evaluation Method>
[0081] A method of evaluating the presence or absence of pinholes
on the surface of the silicon film will be described. FIGS. 4A to
4C are views for explaining the method of evaluating the presence
or absence of pinholes. FIG. 4A shows a schematic cross section of
a sample in which an oxide film and a silicon film are formed on a
silicon substrate, and a surface image obtained by a Scanning
Electron Microscope (SEM). FIG. 4B shows a schematic cross section
of a sample obtained by immersing the sample of FIG. 4A in diluted
hydrofluoric acid (Min of 0.5 wt % for 10 minutes and a surface
image obtained by SEM. FIG. 4C shows a schematic cross section of a
sample obtained by immersing the sample of FIG. 4B in
tetramethylammonium. hydroxide (TMAH) of 2.5% whose temperature was
adjusted to 33 degrees C. and a surface image obtained by SEM.
[0082] First, as illustrated in FIG. 4A, Samples 1A to 1F, Samples
2A to 2G. Sample 3A, and Sample 4A, in each of which an oxide film
202 and a silicon film 203 is formed on a silicon substrate 201,
are prepared. At this time, as illustrated in FIG. 4A, even if a
pinhole 204 is generated in the silicon film 203, since the size of
the pinhole 204 is quite small, it is difficult to evaluate the
presence or absence of the pinhole 204 using the surface image
obtained by SEM.
[0083] Subsequently, as illustrated in FIG. 4B, the silicon
substrate 201 is immersed in DHF of 0.5 wt % for 10 minutes. The
DHF hardly etches the silicon film but has the property of etching
the oxide film. Thus, the silicon film 203 functions as an etching
mask. A portion of the oxide film 202 is etched through the pinhole
204 formed in the silicon film 203. As a result, a recess 205
having a larger diameter than that of the pinhole 204 generated in
the silicon film 203 in plan view is formed in the surface of the
oxide film 202.
[0084] Subsequently, as shown in FIG. 4C, the silicon substrate 201
was immersed in TMAH of 2.5% whose temperature is adjusted to 33
degrees C. The TMAH has a high selectivity of silica film to oxide
film. Thus, the silicon film 203 is etched away and the oxide film
202 remains. As a result, the oxide film 202, which has the recess
205 formed at a position corresponding to the pinhole 204 formed in
the silicon film 203, is exposed on the surface.
[0085] Thereafter, the surface of the sample of FIG. 4C is observed
with SEM to obtain a SEM-based surface image. In addition, pinholes
on the SEM-based surface image are detected by an image analysis
software to measure the number of pinholes, Various software may be
used as the image analysis software. This makes it possible to
clearly confirm the presence or absence of pinholes and the number
of pinholes.
[Evaluation Result 1]
[0086] For each of Sample 1B and Sample 2A, the presence or absence
of pinholes on the surface of the silicon film was evaluated by the
aforementioned evaluation method. FIGS. 5 and 6 are views showing
SEM-based surface images of oxide films in Sample 1B and Sample 2A,
respectively.
[0087] Pinholes were not generated in Sample 1B (see FIG. 5),
whereas a large number of pinholes were generated in Sample 2A (see
FIG. 6). From these results, it is considered that by performing
the etching step S2 after the film forming step S1, it is possible
to prevent the generation of pinholes on the surface of the silicon
film and to form an ultra-thin silicon film having good surface
smoothness.
[Evaluation Result 2]
[0088] For each of Sample 3A and Sample 4A, the presence or absence
of pinholes on the surface of the silicon film was evaluated by the
aforementioned evaluation method. FIGS. 7 and 8 are views showing
SEM-based surface images of oxide films in Sample 3A and Sample 4A,
respectively.
[0089] Pinholes were not generated in Sample 3A (see FIG. 7),
whereas a large number of pinholes were generated in Sample 4A (see
FIG. 8). From these results, it is considered that by performing
the etching step S2 after the film forming step S1, it is possible
to prevent the generation of pinholes on the surface of the silicon
film and to form a ultra-thin silicon film having the good surface
smoothness.
[0090] [Evaluation Result 3]
[0091] For each of Samples 1A to 1F and Samples 2A to 2G, the
number of pinholes on the surface of the silicon film was evaluated
by the aforementioned evaluation method. FIG. 9 is a diagram
representing the relationship between a film thickness of the
silicon film and the number of pinholes in the silicon film. In
FIG. 9, the horizontal axis represents the film thickness (.ANG.)
of the silicon film, and the vertical axis represents the number of
pinholes (EA) on the surface of the silicon film (an observation
area: about 1.2 .mu.m.times.0.9 .mu.m). In addition, in FIG. 9,
circles indicate Samples 1A to 1F, and triangles indicate Samples
2A to 2G.
[0092] In Samples 1A to 1F indicated by the circles in FIG. 9, in
the case of the film thickness of 19 .ANG., one pinhole was
generated. In the case of the film thicknesses of 20 .ANG., 21
.ANG., 23 .ANG., 25 .ANG., and 26 .ANG., no pinhole was generated.
Meanwhile, in Samples 2A to 2G indicated by the triangles in FIG.
9, in the case of the film thicknesses of 34.8 .ANG., 39.5 .ANG.,
42.8 .ANG., and 54.7 .ANG., no pinhole was generated. In the case
of the film thicknesses of 25 .ANG., 27.7 .ANG., and 33.7 .ANG.,
410 pinholes, 224 pinholes, and 9 pinholes were generated,
respectively. From these results, it is considered that by
performing the etching step S2 after the film forming step S1, it
is possible to prevent the generation of pinholes on the surface of
the silicon film and to form an ultra-thin silicon film having good
surface smoothness.
Example 2
[0093] In Example 2, a cross-section shape and surface shape of a
silicon film obtained when using HBr, which is an example of the
etching gas, were evaluated using SEM and an Atomic Force
Microscope (AFM). For comparison, a cross-sectional shape and
surface shape of a silicon film obtained using chlorine (Cl.sub.2)
as an etching gas were also evaluated in the same manner.
[0094] First, a silicon oxide film was firmed in conformity to a
concave-convex shape of a silicon substrate having a line-and-space
(L&S) pattern formed thereon. Subsequently, a first seed layer
was formed by supplying DIPAS as an aminosilane-based gas onto the
silicon oxide film. A second seed layer was formed by supplying
Si.sub.2H.sub.6 onto the first seed layer. Subsequently, an
amorphous silicon (a-Si) film was formed in conformity to the
L&S pattern by supplying SiH.sub.4 onto the second seed layer.
Subsequently, the film thickness of the a-Si film was reduced by
supplying Cl.sub.2 or HBr as an etching gas onto the a-Si film. The
total thickness of the first seed layer, the second seed layer, and
the a-Si film was about 25 nm. In the etching using Cl.sub.2, the
internal pressure of the processing container 34 was set to 3.0
Torr (399.9 Pa) and the substrate temperature was set to 325
degrees C. In the etching using HBr, the internal pressure of the
processing container 34 was set to 20 Torr (2,666 Pa) and the
substrate temperature was set to 550 degrees C.
[0095] Next, the cross-sectional shapes of the prepared samples
were evaluated using SEM.
[0096] FIGS. 10A and 10B illustrate cross-sectional shapes of the
L&S pattern. FIG. 10A illustrates the cross-sectional shape of
a sample obtained by etching an a-Si film using HBr, and FIG. 10B
illustrates the cross-sectional shape of a sample obtained by
etching the a-Si film using Cl.sub.2. Since the silicon oxide film
formed between the silicon substrate and the a-Si film is extremely
thin relative to the a-Si film, it was impossible to confirm the
silicon oxide film in FIGS. 10A and 10B.
[0097] As illustrated in FIG. 10A, it can be seen that, when the
a-Si film was etched using HBr, the a-Si film formed in conformity
to the L&S pattern of the silicon substrate was etched in a
conformal manner, in other words, it can be seen that a film
thickness Ttop of an a-Si film remaining on an upper sidewall of
each line in the L&S pattern and a film thickness Tbtm of the
a-Si film remaining on a lower sidewall of each line in the L&S
pattern are substantially equal to each other, and thus the
sectional shape of each space in the L&S pattern is
substantially a U-formation.
[0098] Meanwhile, as illustrated in FIG. 10B, it can be seen that,
when the a-Si film was etched using Cl.sub.2, the a-Si film formed
in conformity to the L&S pattern of the silicon substrate was
more etched on the upper sidewall of each line of the L&S
pattern than on the lower sidewall of each line in the L&S
pattern. In other words, it can be seen that the film thickness
Ttop of the a-Si film remaining on the upper sidewall of each line
in the L&S pattern becomes smaller than the film thickness Tbtm
of the a-Si film remaining on the lower sidewall of each line in
the L&S pattern, and thus the sectional shape of each space in
the L&S pattern are substantially a V-formation.
[0099] From the foregoing, it can be said that by etching the a-Si
film using HBr, it is possible to etch the a-Si film formed in
conformity to the concave-convex shape in a conformal manner.
[0100] Subsequently, the surface shapes of the prepared samples
were evaluated using AFM.
[0101] As a result of the AFM-based evaluation, a surface roughness
Ra of each line in the L&S pattern before etching the a-Si film
was 0.289. In addition, when the a-Si film was etched using HBr,
the surface roughness Ra of each line in the L&S pattern was
0.244. Thus, a surface smoother than that before etching the a-Si
film was obtained. Meanwhile, when the a-Si film was etched using
Cl.sub.2, the surface roughness Ra of each line in the L&S
pattern was 0.342, which becomes larger than that before etching
the a-Si film.
[0102] From the foregoing, it can be said that, by etching the a-Si
film using HBr, it is possible to form an a-Si film having good
surface smoothness,
Example 3
[0103] In Example 3, a dependence of an etching rate of HBr used as
an example of etching gas on temperature in an a-Si film was
evaluated. For comparison, the dependence of the etching rate on
temperature when the a-Si film was etched using Cl.sub.2 was also
evaluated.
[0104] FIG. 11 is a diagram representing a dependence of an etching
rate of an etching gas on temperature in an a-Si film. In FIG. 11,
the horizontal axis represents the etching temperature (degree C.),
and the vertical axis represents the etching rate (.ANG./min). In
addition, in FIG. 11, the film-forming temperature range of a
general a-Si film is represented as a range enclosed by a broken
line.
[0105] As represented in FIG. 11, in the case of using HBr as an
etching gas, it is possible to etch the a-Si film at a temperature
substantially equal to or slightly higher than the film-forming
temperature of the a-Si film after forming the a-Si film at a
generally-used temperature (e.g., 380 degrees C. to 530 degrees
C.). Therefore, it takes little time in stabilizing the temperature
before etching the a-Si film.
[0106] Meanwhile, in the case of using Cl.sub.2 as an etching gas,
when etching is performed after forming the a-Si film at the
generally-used temperature, it is necessary to lower the
temperature to a temperature at which the film thickness of the
a-Si film is capable of being controlled (e.g., 350 degrees C. or
less) after the formation of the a-Si film. Therefore, the time
required for stabilizing the temperature before etching the a-Si
film is prolonged.
[0107] From the foregoing, in the case of etching the a-Si film, by
using HBr as the etching gas, it is possible to shorten the time
required for stabilizing the temperature before etching the a-Si
film and to improve the productivity.
[0108] Although some embodiments for carrying out the present
disclosure have been described above, the above contents do not
limit the contents of the present disclosure, and various
modifications and improvements are possible within the scope of the
present disclosure.
[0109] According to the present disclosure in some embodiments, it
is possible to form an ultra-thin silicon film having good surface
smoothness.
[0110] In the embodiments described above, a batch-type vertical
heat treatment apparatus, which performs processing on a plurality
of wafers at a time, has been described as an example of a
substrate processing apparatus, but the present disclosure is not
limited thereto. For example, the substrate processing apparatus
may be a single wafer type apparatus, which processes wafers one by
one. In some embodiments, for example, the substrate processing
apparatus may be a semi-batch type apparatus, which revolves a
plurality of wafers arranged on a rotary table inside a processing
container by the rotary table and causes the wafers to sequentially
pass through a region to which a source gas is supplied and a
region to which a reaction gas reacting with the source gas is
supplied, thus forming a film on the surface of each wafer.
* * * * *