U.S. patent application number 16/996595 was filed with the patent office on 2021-02-25 for systems and methods for addressing devices in a superconducting circuit.
The applicant listed for this patent is D-WAVE SYSTEMS INC.. Invention is credited to Christopher B. Rich, George E.G. Sterling, Loren J. Swenson.
Application Number | 20210057631 16/996595 |
Document ID | / |
Family ID | 1000005121331 |
Filed Date | 2021-02-25 |
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United States Patent
Application |
20210057631 |
Kind Code |
A1 |
Swenson; Loren J. ; et
al. |
February 25, 2021 |
SYSTEMS AND METHODS FOR ADDRESSING DEVICES IN A SUPERCONDUCTING
CIRCUIT
Abstract
Addressing a superconducting flux storage device may include
applying a bias current, a low-frequency flux bias, and a
high-frequency flux bias in combination to cause a combined address
signal level to exceed a defined address signal latching level for
the superconducting flux storage device. A bias current that, in
combination with a low-frequency flux bias and a high-frequency
flux bias, causes a combined address signal level to exceed a
defined address signal latching level for a superconducting flux
storage device is at least reduced by an asymmetry in the Josephson
junctions of the CJJ. A low-frequency flux bias that, in
combination with a bias current and a high-frequency flux bias,
causes a combined address signal level to exceed a defined address
signal latching level for a superconducting flux storage device is
at least reduced by an asymmetry in the Josephson junctions of the
CJJ.
Inventors: |
Swenson; Loren J.; (San
Jose, CA) ; Sterling; George E.G.; (Vancouver,
CA) ; Rich; Christopher B.; (Vancouver, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
D-WAVE SYSTEMS INC. |
Burnaby |
|
CA |
|
|
Family ID: |
1000005121331 |
Appl. No.: |
16/996595 |
Filed: |
August 18, 2020 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62888605 |
Aug 19, 2019 |
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03K 3/38 20130101; H01L
39/223 20130101; H01L 27/18 20130101; H03K 17/92 20130101; H01L
39/025 20130101; G11C 11/44 20130101 |
International
Class: |
H01L 39/22 20060101
H01L039/22; H01L 39/02 20060101 H01L039/02; H01L 27/18 20060101
H01L027/18; H03K 3/38 20060101 H03K003/38; H03K 17/92 20060101
H03K017/92; G11C 11/44 20060101 G11C011/44 |
Claims
1. A superconducting integrated circuit comprising: a microwave
transmission line; a superconducting flux storage device comprising
a loop of material that is superconductive below a critical
temperature interrupted by an asymmetric compound Josephson
junction (CJJ), the asymmetric CJJ comprising: a first parallel
current path interrupted by a first Josephson junction, the first
Josephson junction characterized by a first critical current; and a
second parallel current path interrupted by a second Josephson
junction, the second parallel current path electrically in parallel
with the first parallel current path, the second Josephson junction
characterized by a second critical current, the second critical
current of the second Josephson junction different from the first
critical current of the first Josephson junction; a first
superconducting resonator communicatively coupled to the microwave
transmission line; and a first signal interface that inductively
communicatively couples the first superconducting resonator to the
superconducting flux storage device, wherein the first signal
interface is operable to provide a first flux bias to the
superconducting flux storage device.
2. The superconducting integrated circuit of claim 1 further
comprising: a low-frequency address bias line; and an address
interface that inductively communicatively couples the
low-frequency bias address line to the superconducting flux storage
device, wherein the address interface is operable to provide a
second flux bias to the superconducting flux storage device.
3. The superconducting integrated circuit of claim 2, wherein the
superconducting flux storage device comprises a superconducting
digital-to-analog converter (DAC), the superconducting DAC which is
operable to perform latching, and the superconducting DAC is
programmed by a low-frequency bias signal carried by the
low-frequency address bias line and by a microwave signal carried
by the first superconducting resonator, which combine
constructively to exceed a threshold address latching level, the
low-frequency bias signal carried by the low-frequency address bias
line which is at least reduced by a factor that depends on a
difference between the first critical current of the first
Josephson junction of the CJJ and the second critical current of
the second Josephson junction of the CJJ.
4. The superconducting integrated circuit of claim 1, further
comprising a current bias line, wherein a current in the current
bias line is an alternating current.
5. The superconducting integrated circuit of claim 4, wherein the
alternating current has no DC component.
6. The superconducting integrated circuit of claim 1, further
comprising: a second superconducting resonator communicatively
coupled to the microwave transmission line; and a second signal
interface that inductively communicatively couples the second
superconducting resonator to the superconducting flux storage
device, wherein the second signal interface is operable to provide
a second flux bias to the superconducting flux storage device.
7. The superconducting integrated circuit of claim 6, wherein the
first superconducting resonator extends along a first axis and the
second superconducting resonator extends along a second axis, the
second axis perpendicular to the first axis.
8. The superconducting integrated circuit of claim 6, wherein the
superconducting flux storage device is XY-addressed by two
microwave signals, a first one of the two microwave signals carried
by the first superconducting resonator, and a second one of the two
microwave signals carried by the second superconducting resonator,
each of the first and the second superconducting resonator having a
respective resonant frequency, the respective resonant frequencies
of the first and the second superconducting resonators which in
operation add constructively at the superconducting flux storage
device.
9. The superconducting integrated circuit of claim 8, wherein the
respective resonant frequencies of the first and the second
superconducting resonators add constructively at the
superconducting flux storage device to provide a beat signal, a
frequency of the beat signal which is matched to a linewidth of at
least one of the first and the second superconducting
resonators.
10. The superconducting integrated circuit of claim 6, wherein the
superconducting flux storage device comprises a superconducting
digital-to-analog converter (DAC), the superconducting DAC which is
operable to perform latching, and the superconducting DAC is
programmed by a low-frequency bias signal carried by a
low-frequency address bias line and by two microwave signals, which
combine constructively to exceed a threshold address latching
level, the low-frequency bias signal carried by the low-frequency
address bias line which is at least reduced by a factor that
depends on a difference between the first critical current of the
first Josephson junction of the CJJ and the second critical current
of the second Josephson junction of the CJJ.
11. The superconducting integrated circuit of claim 1, wherein a
size of the second Josephson junction is different from a size of
the first Josephson junction.
12. A method of loading a superconducting flux storage device with
a magnetic flux quantum, the superconducting flux storage device
comprising a superconducting flux storage loop interrupted by an
asymmetric compound Josephson junction (CJJ), the asymmetric CJJ
comprising: a first parallel current path interrupted by a first
Josephson junction, the first Josephson junction characterized by a
first critical current; and a second parallel current path
interrupted by a second Josephson junction, the second parallel
current path electrically in parallel with the first parallel
current path, the second Josephson junction characterized by a
second critical current, the second critical current of the second
Josephson junction different than the first critical current of the
first Josephson junction, the superconducting flux storage devices,
the method comprising: applying a first high-frequency pulse to at
least a first superconducting resonator by a microwave transmission
line, the microwave transmission line communicatively coupled to
the at least a first superconducting resonator; and applying the
first high-frequency pulse to the superconducting flux storage
device by the at least a first superconducting resonator, the at
least a first superconducting resonator communicatively coupled to
the superconducting flux storage device, to cause a flux quantum to
be added to the asymmetric CJJ of the superconducting flux storage
device.
13. The method of claim 12, further comprising: setting a current
bias line to a first current bias value; setting a low-frequency
address line to a first address line value; setting the current
bias line to a second current bias line value to cause a current
bias to be applied to the superconducting flux storage device;
setting the low-frequency address line to a second address line
value to cause a flux bias to be applied to the asymmetric CJJ of
the superconducting flux storage device; after the applying a first
high-frequency pulse to the superconducting flux storage device,
setting the low-frequency address line to a third address line
value to cause the flux quantum to be loaded into the
superconducting flux storage loop of the superconducting flux
storage device; returning the current bias line to the first
current bias line value; and returning the low-frequency address
line to the first address line value, wherein applying a first
high-frequency pulse to the superconducting flux storage device by
a microwave transmission line and a first superconducting resonator
includes causing a combined low-frequency and high-frequency signal
level applied to the superconducting flux storage device to exceed
a predetermined upper threshold, and wherein at least one of the
second current bias line value and the second address line value is
at least reduced by a factor that depends on a difference between
the first critical current of the first Josephson junction of the
asymmetric CJJ and the second critical current of the second
Josephson junction of the asymmetric CJJ.
14. The method of claim 13, wherein setting the low-frequency
address line to a third address line value to cause the flux
quantum to be loaded into the superconducting flux storage loop of
the superconducting flux storage device includes setting the
low-frequency address line to a third address line value to cause
the flux quantum to be loaded into a superconducting
digital-to-analog converter (DAC).
15. The method of claim 12, wherein applying a first high-frequency
pulse to the superconducting flux storage device by a microwave
transmission line and at least a first superconducting resonator
includes applying a set of frequency-domain multiplex signals to
each of the first superconducting resonator and at least a second
superconducting resonator.
16. The method of claim 12, further comprising: applying the first
high-frequency pulse to a second superconducting flux storage
device by the microwave transmission line and the at least a first
superconducting resonator.
17. The method of claim 12, wherein applying a first high-frequency
pulse to the superconducting flux storage device by a microwave
transmission line and at least a first superconducting resonator
includes applying a first high-frequency pulse to a superconducting
digital-to-analog converter (DAC) by the microwave transmission
line and a first and at least a second superconducting resonator,
the superconducting DAC operable to perform latching.
18. The method of claim 17, further comprising programming the
superconducting DAC by a low-frequency bias signal carried by a
first low-frequency address bias line and by two microwave signals,
the low-frequency bias signal and the two microwave signals which
combine constructively to exceed a threshold address latching
level.
19. The method of claim 12, further comprising applying an
alternating current on a current bias line.
20. The method of claim 19, wherein applying an alternating current
on a current bias line includes applying an alternating current
having no DC component.
21. A superconducting integrated circuit comprising: a
superconducting flux storage device, the superconducting flux
storage device which comprises a loop of material that is
superconductive in a range of temperatures, the loop of material
which is interrupted by at least one Josephson junction; and a
first addressing line communicatively coupled to the
superconducting flux storage device, wherein a current in the first
addressing line is an alternating current.
22. The superconducting integrated circuit of claim 21, wherein the
at least one Josephson junction is a compound Josephson junction
(CJJ), the CJJ comprising: a first parallel current path which is
interrupted by a first Josephson junction; and a second parallel
current path which is interrupted by a second Josephson junction,
the second parallel current path which is electrically in parallel
with the first parallel current path.
23. The superconducting integrated circuit of claim 22, the first
parallel current path which is further interrupted by a first
inductance and the second parallel current path which is further
interrupted by a second inductance, the superconducting integrated
circuit further comprising: a second addressing line which is
inductively coupled to the first inductance; and a third addressing
line which is inductively coupled to the second inductance.
24. The superconducting integrated circuit of claim 23, the loop of
material which includes a third inductance, the superconducting
integrated circuit further comprising a device inductively
communicatively coupled to the superconducting flux storage device
by the third inductance.
Description
TECHNICAL FIELD
[0001] This disclosure generally relates to systems and methods for
addressing devices in a superconducting circuit, and, more
specifically, to systems and methods for resonator-addressing of
superconducting flux storage devices and digital-to-analog
converters (DAC) in superconducting integrated circuits.
BACKGROUND
[0002] Frequency Multiplexed Resonant (FMR) Readout
[0003] Superconducting microwave resonators can be used in a
variety of fields including, but not limited to, quantum
computation and astronomy. In quantum computation, superconducting
resonators can be used to detect the state of qubits, for example
the state of superconducting qubits in a superconducting quantum
processor. In astronomy, superconducting microwave resonators can
be used in Microwave Kinetic Inductance Detectors (MKIDs).
[0004] Multiple resonators (detectors) can be coupled to a common
transmission line and integrated through frequency domain
multiplexing. Frequency-domain multiplexing (FDM) is a technique in
which a communication bandwidth is divided into a number of
non-overlapping sub-bands, and each sub-band used to carry a
separate signal. Frequency-domain multiplexing is also referred to
in the present application as frequency multiplexing and
frequency-division multiplexing.
[0005] Using FMR technology, superconducting resonators of
different resonant frequencies can be used for readout of multiple
qubits, for example. The resonators can share a common microwave
transmission line by using frequency-domain multiplexing.
BRIEF SUMMARY
[0006] A superconducting integrated circuit may be summarized as
comprising a microwave transmission line; a superconducting flux
storage device comprising a loop of material that is
superconductive below a critical temperature interrupted by an
asymmetric compound Josephson junction (CJJ), the asymmetric CJJ
comprising a first parallel current path interrupted by a first
Josephson junction, the first Josephson junction characterized by a
first critical current; and a second parallel current path
interrupted by a second Josephson junction, the second parallel
current path electrically in parallel with the first parallel
current path, the second Josephson junction characterized by a
second critical current, the second critical current of the second
Josephson junction different from the first critical current of the
first Josephson junction; a first superconducting resonator
communicatively coupled to the microwave transmission line; and a
first signal interface that inductively communicatively couples the
first superconducting resonator to the superconducting flux storage
device, wherein the first signal interface is operable to provide a
first flux bias to the superconducting flux storage device.
[0007] The superconducting integrated circuit may further comprise
a low-frequency address bias line; and an address interface that
inductively communicatively couples the low-frequency bias address
line to the superconducting flux storage device, wherein the
address interface is operable to provide a second flux bias to the
superconducting flux storage device. The superconducting flux
storage device may comprise a superconducting digital-to-analog
converter (DAC), the superconducting DAC which is operable to
perform latching, and the superconducting DAC is programmed by a
low-frequency bias signal carried by the low-frequency address bias
line and by a microwave signal carried by the first superconducting
resonator, which combine constructively to exceed a threshold
address latching level, the low-frequency bias signal carried by
the low-frequency address bias line which is at least reduced by a
factor that depends on a difference between the first critical
current of the first Josephson junction of the CJJ and the second
critical current of the second Josephson junction of the CJJ.
[0008] The superconducting integrated circuit may further comprise
a current bias line, wherein a current in the current bias line is
an alternating current. The alternating current may have no DC
component.
[0009] The superconducting integrated circuit may further comprise
a second superconducting resonator communicatively coupled to the
microwave transmission line; and a second signal interface that
inductively communicatively couples the second superconducting
resonator to the superconducting flux storage device, wherein the
second signal interface is operable to provide a second flux bias
to the superconducting flux storage device. The first
superconducting resonator may extend along a first axis and the
second superconducting resonator may extend along a second axis,
the second axis perpendicular to the first axis. The
superconducting flux storage device may be XY-addressed by two
microwave signals, a first one of the two microwave signals carried
by the first superconducting resonator, and a second one of the two
microwave signals carried by the second superconducting resonator,
each of the first and the second superconducting resonator having a
respective resonant frequency, the respective resonant frequencies
of the first and the second superconducting resonators which in
operation add constructively at the superconducting flux storage
device. The respective resonant frequencies of the first and the
second superconducting resonators may add constructively at the
superconducting flux storage device to provide a beat signal, a
frequency of the beat signal which is matched to a linewidth of at
least one of the first and the second superconducting resonators.
The superconducting flux storage device may comprise a
superconducting digital-to-analog converter (DAC), the
superconducting DAC which is operable to perform latching, and the
superconducting DAC may be programmed by a low-frequency bias
signal carried by a low-frequency address bias line and by two
microwave signals, which combine constructively to exceed a
threshold address latching level, the low-frequency bias signal
carried by the low-frequency address bias line which is at least
reduced by a factor that depends on a difference between the first
critical current of the first Josephson junction of the CJJ and the
second critical current of the second Josephson junction of the
CJJ.
[0010] A size of the second Josephson junction may be different
from a size of the first Josephson junction.
[0011] A method of loading a superconducting flux storage device
with a magnetic flux quantum, the superconducting flux storage
device comprising a superconducting flux storage loop interrupted
by an asymmetric compound Josephson junction (CJJ), the asymmetric
CJJ comprising a first parallel current path interrupted by a first
Josephson junction, the first Josephson junction characterized by a
first critical current; and a second parallel current path
interrupted by a second Josephson junction, the second parallel
current path electrically in parallel with the first parallel
current path, the second Josephson junction characterized by a
second critical current, the second critical current of the second
Josephson junction different than the first critical current of the
first Josephson junction, the superconducting flux storage devices,
may be summarized as comprising applying a first high-frequency
pulse to at least a first superconducting resonator by a microwave
transmission line, the microwave transmission line communicatively
coupled to the at least a first superconducting resonator; and
applying the first high-frequency pulse to the superconducting flux
storage device by the at least a first superconducting resonator,
the at least a first superconducting resonator communicatively
coupled to the superconducting flux storage device to cause a flux
quantum to be added to the asymmetric CJJ of the superconducting
flux storage device.
[0012] The method may further comprise setting a current bias line
to a first current bias value; setting a low-frequency address line
to a first address line value; setting the current bias line to a
second current bias line value to cause a current bias to be
applied to the superconducting flux storage device; setting the
low-frequency address line to a second address line value to cause
a flux bias to be applied to the asymmetric CJJ of the
superconducting flux storage device; after the applying a first
high-frequency pulse to the superconducting flux storage device,
setting the low-frequency address line to a third address line
value to cause the flux quantum to be loaded into the
superconducting flux storage loop of the superconducting flux
storage device; returning the current bias line to the first
current bias line value; and returning the low-frequency address
line to the first address line value, wherein applying a first
high-frequency pulse to the superconducting flux storage device by
a microwave transmission line and a first superconducting resonator
includes causing a combined low-frequency and high-frequency signal
level applied to the superconducting flux storage device to exceed
a predetermined upper threshold, and wherein at least one of the
second current bias line value and the second address line value is
at least reduced by a factor that depends on a difference between
the first critical current of the first Josephson junction of the
asymmetric CJJ and the second critical current of the second
Josephson junction of the asymmetric CJJ. Setting the low-frequency
address line to a third address line value to cause the flux
quantum to be loaded into the superconducting flux storage loop of
the superconducting flux storage device may include setting the
low-frequency address line to a third address line value to cause
the flux quantum to be loaded into a superconducting
digital-to-analog converter (DAC).
[0013] Applying a first high-frequency pulse to the superconducting
flux storage device by a microwave transmission line and at least a
first superconducting resonator may include applying a set of
frequency-domain multiplex signals to each of the first
superconducting resonator and at least a second superconducting
resonator.
[0014] The method may further comprise applying the first
high-frequency pulse to a second superconducting flux storage
device by the microwave transmission line and the at least a first
superconducting resonator.
[0015] Applying a first high-frequency pulse to the superconducting
flux storage device by a microwave transmission line and at least a
first superconducting resonator may include applying a first
high-frequency pulse to a superconducting digital-to-analog
converter (DAC) by the microwave transmission line and a first and
at least a second superconducting resonator, the superconducting
DAC operable to perform latching. The method may further comprise
programming the superconducting DAC by a low-frequency bias signal
carried by a first low-frequency address bias line and by two
microwave signals, the low-frequency bias signal and the two
microwave signals which combine constructively to exceed a
threshold address latching level.
[0016] The method may further comprise applying an alternating
current on a current bias line. Applying an alternating current on
a current bias line may include applying an alternating current
having no DC component.
[0017] A superconducting integrated circuit may be summarized as
comprising a superconducting flux storage device, the
superconducting flux storage device which comprises a loop of
material that is superconductive in a range of temperatures, the
loop of material which is interrupted by at least one Josephson
junction; and a first addressing line communicatively coupled to
the superconducting flux storage device, wherein a current in the
first addressing line is an alternating current. The at least one
Josephson junction may be a compound Josephson junction (CJJ), the
CJJ comprising a first parallel current path which is interrupted
by a first Josephson junction; and a second parallel current path
which is interrupted by a second Josephson junction, the second
parallel current path which is electrically in parallel with the
first parallel current path. Where the first parallel current path
is further interrupted by a first inductance and the second
parallel current path is further interrupted by a second
inductance, the superconducting integrated circuit may further
comprise a second addressing line which is inductively coupled to
the first inductance; and a third addressing line which is
inductively coupled to the second inductance. Where the loop of
material includes a third inductance, the superconducting
integrated circuit may further comprise a device inductively
communicatively coupled to the superconducting flux storage device
by the third inductance.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0018] In the drawings, identical reference numbers identify
similar elements or acts. The sizes and relative positions of
elements in the drawings are not necessarily drawn to scale. For
example, the shapes of various elements and angles are not
necessarily drawn to scale, and some of these elements are
arbitrarily enlarged and positioned to improve drawing legibility.
Further, the particular shapes of the elements as drawn, are not
necessarily intended to convey any information regarding the actual
shape of the particular elements, and have been solely selected for
ease of recognition in the drawings.
[0019] FIG. 1 is a schematic diagram illustrating an example
implementation of a microwave path to a superconducting circuit,
according to the present disclosure.
[0020] FIG. 2 is a schematic diagram illustrating another example
implementation of a microwave path to a superconducting circuit,
according to the present disclosure.
[0021] FIG. 3A is a schematic layout of a portion of an example
implementation of a superconducting circuit that includes a
superconducting half-wave resonator and a transmission line,
according to the present disclosure.
[0022] FIG. 3B is an enlarged view of a coupling region of the
superconducting half-wave resonator of FIG. 3A.
[0023] FIG. 4A is a schematic layout of a portion of an example
implementation of a superconducting circuit that includes a
superconducting lumped-element resonator and a transmission line,
according to the present disclosure.
[0024] FIG. 4B is an enlarged view of a coupling region of the
superconducting lumped-element resonator of FIG. 4A.
[0025] FIG. 4C is a cross-section of a portion of an example
implementation of a superconducting circuit that includes a
superconducting lumped-element resonator and a transmission line,
according to the present disclosure.
[0026] FIG. 5A is a schematic diagram illustrating an example
implementation of a superconducting circuit that includes a
resonator-addressed digital-to-analog converter (DAC), according to
the present disclosure.
[0027] FIG. 5B is a schematic diagram illustrating another example
implementation of a superconducting circuit that includes a
resonator-addressed digital-to-analog converter (DAC), according to
the present disclosure.
[0028] FIG. 5C is a schematic diagram illustrating an example
implementation of a superconducting circuit that includes a pair of
resonator-addressed digital-to-analog converters (DACs), according
to the present disclosure.
[0029] FIG. 5D is a schematic diagram illustrating another example
implementation of a superconducting circuit that includes a
resonator-addressed digital-to-analog converter (DAC), according to
the present disclosure.
[0030] FIG. 5E is a schematic diagram illustrating an example
implementation of a superconducting circuit that includes a
resonator-addressed digital-to-analog converter (DAC), and a
resonator that is inductively coupled to a transmission line,
according to the present disclosure.
[0031] FIG. 5F is a schematic diagram illustrating another example
implementation of a superconducting circuit that includes a
resonator-addressed digital-to-analog converter (DAC), and a
resonator that is inductively coupled to a transmission line,
according to the present disclosure.
[0032] FIG. 6 is a flow chart illustrating an example method for
programming a superconducting DAC, according to the present
disclosure.
[0033] FIGS. 7A, 7B and 7C are schematic plots illustrating an
example time series for loading of a single flux quantum, according
to the present disclosure, and in particular FIG. 7A is a graph
showing a plot of an address signal current as a function of time;
FIG. 7B is a graph showing a plot of a power signal current as a
function of time; and FIG. 7C is a graph showing a plot of a
persistent current in a compound Josephson junction (CJJ) loop of
the superconducting DAC as a function of time.
[0034] FIG. 8 is a schematic diagram of an exemplary computing
system including a digital computer and an analog computer, in
accordance with the present disclosure.
[0035] FIG. 9A is a schematic diagram illustrating an example
implementation of a superconducting circuit, according to the
present disclosure.
[0036] FIG. 9B is a schematic diagram illustrating another example
implementation of a superconducting circuit, according to the
present disclosure.
[0037] FIG. 9C is a schematic diagram illustrating an example
implementation of a superconducting circuit with asymmetric
Josephson junctions in a compound Josephson junction of a
superconducting flux storage device, according to the present
disclosure.
[0038] FIG. 10 is a schematic diagram illustrating an example
implementation of a superconducting circuit that includes an array
of resonators, according to the present disclosure.
[0039] FIG. 11 is a schematic diagram illustrating an example
implementation of a superconducting circuit that includes a switch,
according to the present disclosure.
[0040] FIG. 12 is a schematic diagram of an example implementation
of a transmission line layout with N cascade elements, according to
the present disclosure.
[0041] FIG. 13 is a schematic diagram of an example implementation
of a single cascade element, according to the present
disclosure.
[0042] FIG. 14 is a schematic diagram of a superconducting DAC,
according to the present disclosure.
DETAILED DESCRIPTION
Preamble
[0043] In the following description, some specific details are
included to provide a thorough understanding of various disclosed
implementations and embodiments. One skilled in the relevant art,
however, will recognize that embodiments may be practiced without
one or more of these specific details, or with other methods,
components, materials, etc. In other instances, well-known
structures associated with superconductive devices and integrated
superconductive circuits have not been shown or described in detail
to avoid unnecessarily obscuring descriptions of the
implementations or embodiments of the present methods. Throughout
this specification and the appended claims, the words "element" and
"elements" are used to encompass, but are not limited to, all such
structures, systems, and devices associated with superconductive
circuits and integrated superconductive circuits.
[0044] Unless the context requires otherwise, throughout the
specification and claims which follow, the word "comprise" is
synonymous with "including," and is inclusive or open-ended (i.e.,
does not exclude additional, unrecited elements or acts).
[0045] Reference throughout this specification to "one embodiment"
"an embodiment", "another embodiment", "one example", "an example",
"another example", "one implementation", "another implementation",
or the like means that a particular referent feature, structure, or
characteristic described in connection with the embodiment,
example, or implementation is included in at least one embodiment,
example, or implementation. Thus, the appearances of the phrases
"in one embodiment", "in an embodiment", "another embodiment" or
the like in various places throughout this specification are not
necessarily all referring to the same embodiment, example, or
implementation. Furthermore, the particular features, structures,
or characteristics may be combined in any suitable manner in one or
more embodiments, examples, or implementations.
[0046] It should be noted that, as used in this specification and
the appended claims, the singular forms "a," "an," and "the"
include plural referents unless the content clearly dictates
otherwise. Thus, for example, reference to a readout system
including "a superconducting resonator" includes a single
superconducting resonator, or two or more superconducting
resonators. It should also be noted that the term "or" is generally
employed in its sense including "and/or" unless the content clearly
dictates otherwise.
[0047] The headings provided herein are for convenience only and do
not interpret the scope or meaning of the embodiments.
Superconducting Flux Storage Devices
[0048] Superconducting flux storage devices are also referred to in
the present application as superconducting digital-to-analog
converters (DACs) and flux DACs.
[0049] While a single qubit, or a handful of them, can be precisely
controlled using dedicated analog lines driven by room-temperature
electronics, integrating more than a few dozen qubits on a single
chip can preferably be implemented using on-chip control circuitry.
In one implementation of a quantum processor that includes
superconducting qubits and couplers, there can be six control
parameters per qubit, and one control parameter per coupler. Static
flux biases can be selectively applied to superconducting loops in
order to realize at least some of the control parameters. The
desired values of flux biases can be programmed into control
devices using a relatively small number of control lines that carry
signals generated at room temperature.
[0050] In some implementations, control devices can combine the
functions of persistent memory and digital-to-analog conversion,
and are referred to in the present application as flux DACs. In an
example implementation, each flux DAC has a size of about 10 .mu.m.
Having several of them attached to a single qubit can set a lower
bound on qubit size, and can influence possible qubit shapes,
hardware graph topologies, and processor architecture.
[0051] XYZ-Addressing of Flux DACs In an example implementation of
a quantum processor, 512 qubits and associated coupling devices can
be controlled by 4608 flux DACs. An XYZ-addressing approach can
control the quantum processor using only 56 lines. The processor
can be arranged as an 8.times.8 array of tiles, each tile having 72
flux DACs. The flux DACs of each tile can be arranged in a
respective 3-DAC plaquette. One of each set of three DACs in a
3-DAC plaquette can be selected using one of three lines (referred
to in the present application as address (ADDR) lines), all three
sharing another line (referred to in the present application as a
trigger (TRIG) line), in an arrangement that uses 15 ADDR lines and
5 TRIG lines to address DACs in the tile. The 8.times.8 array of
tiles can be divided into 16 domains (referred to in the present
application as power (PWR) domains), and arranged such that 4608
flux DACs can be addressed using 30 ADDR lines, 10 TRIG lines, and
16 PWR lines in total. See for example Bunyk P. et al.,
"ARCHITECTURAL CONSIDERATIONS IN THE DESIGN OF A SUPERCONDUCTING
QUANTUM ANNEALING PROCESSOR", arXiv:1401.5504v1, 21 Jan. 2014.
[0052] A shortcoming of the DAC addressing scheme described above
can be that implementation can include a large number of wires and
superconducting low-pass filters which can be costly to produce,
vulnerable to failure, and a source of high-energy photons from
internal filter heating. In some implementations, the wires are
twisted-pairs and the low-pass filters are custom-made
superconducting low-pass filters. The systems and methods described
in the present application include replacing wires by coaxial cable
which can provide greater bandwidth and reduced complexity. A
benefit of greater bandwidth can be improved processor input/output
(I/O) speed.
Superconducting Resonators
[0053] When high-bandwidth lines are available for communicating
with the processor, more efficient use of the bandwidth can be made
by coupling the high-bandwidth line to a suitable on-chip element.
An example on-chip element suitable for coupling to a
high-bandwidth transmission line is a superconducting resonator. An
advantage of using a superconducting resonator is that, similar to
FMR readout or microwave kinetic-inductance detectors (MKIDs),
these devices can be compatible with frequency-domain multiplexing.
An array of resonators can be coupled to a single transmission line
using frequency-domain multiplexing by tuning a resonant frequency
of each resonator. The resonant frequency can be tuned, for
example, by adjusting a length of the resonator, and/or by adding
additional capacitance. In one implementation, the resonator is a
half-wave superconducting resonator. Microwave current can be
excited when the resonator is driven near its resonant frequency.
Addressing can be achieved by selectively transmitting a set of
tones corresponding to a set of resonators in the array of
resonators.
Distributed Superconducting Resonators
[0054] One implementation of a superconducting resonator is a
distributed superconducting resonator. An example of a distributed
superconducting resonator is half-wavelength (.lamda./2) resonator.
A half-wavelength resonator can generally provide sufficient usable
wiring length for coupling to another device. A shortcoming of a
half-wavelength resonator can be that the presence of harmonics at
integer multiples of the fundamental resonant frequency can
constrain an array of superconducting resonators to one octave of
bandwidth.
[0055] An additional shortcoming can be that the current
distribution can vary sinusoidally along the wiring length, with a
peak value occurring at the center of the device. One approach to
mitigating the variation in current is to use only a section of the
length of the resonator, for example a section in which the
variation in current remains within, say, 90% of the peak value.
Another approach is to vary the strength of coupling of the
resonator to devices coupled along the length of the resonator. Yet
another approach is to adjust the driving amplitudes of
intersecting resonators to compensate for the resonator current
distribution. The latter approach can be used in the XY-addressing
scheme described below, for example. In some implementations,
resonators are operated individually. In some implementations,
resonators are operated in groups of resonators.
[0056] Another example of a distributed superconducting resonator
is a quarter-wavelength (.lamda./4) resonator. The peak current for
a quarter-wavelength resonator is at one end of the resonator.
Variation in current along the body of the resonator can be
mitigated by using only a section of the length of the resonator,
specifically a section at or near the end where the current is
within, say 90% of the peak value.
Lumped-Element Resonators
[0057] Another implementation of a superconducting resonator is a
lumped-element resonator. An advantage of a lumped-element
resonator is that the current distribution can be substantially
uniform along an inductive portion of the lumped-element resonator.
Furthermore, a lumped-element resonator can be compact and, in at
least some implementations, is not constrained to one octave of
bandwidth. In an example implementation, a lumped element resonator
can operate from 5 GHz to 15 GHz, and yield 10 GHz of
bandwidth.
[0058] There are several constraints that can influence achievable
electronic bandwidth utilization of a resonator-multiplexed
programming system (also referred to in the present application as
system bandwidth). The same or similar constraints can also
influence the system bandwidth of implementations of
superconducting resonators other than lumped-element
resonators.
[0059] Firstly, system bandwidth can be constrained by cross-talk.
The effective system bandwidth can be limited by as much as 30% in
some implementations where resonances are spaced apart from each
other to reduce cross-talk. The spacing between resonances can be
several linewidths. In an example implementation, the system
bandwidth is 4-8 GHz, and the per-resonator bandwidth is
approximately 30 MHz centered on a resonant frequency within the
system bandwidth.
[0060] Secondly, variations in fabrication, such as variations in
layer thickness, can shift a resonant frequency by as much as 10%
in some implementations.
[0061] Thirdly, layout of resonators and associated wiring can
cause resonator-to-resonator frequency shifts. In some
implementations, resonator bodies are routed in a single wiring
layer to reduce resonator-to-resonator frequency shifts. In some
implementations, where vias are used, an array of resonators can
use the same number of vias with approximately the same
distribution along the resonator length for every resonator in the
array, to avoid or at least reduce differential changes in
resonator lengths, resonator-to-resonator frequency shifts, and
contaminant electronic cross-talk.
[0062] Fourthly, a higher-frequency resonator can be shorter than a
lower-frequency resonator, and, in some instances, can become too
short to span a width of a processor in which an array of
resonators is used for DAC addressing. The constraint can be
mitigated in some implementations by using a thin dielectric layer
in the fabrication of parallel-plate capacitors in the resonators
to reduce the footprint of the capacitors. See for example U.S.
Provisional Patent Application Ser. No. 62/660,719, "SYSTEMS AND
METHODS FOR FABRICATION OF SUPERCONDUCTING DEVICES", filed Apr. 20,
2018, and U.S. patent application Ser. No. 16/389,669, "SYSTEMS AND
METHODS FOR FABRICATION OF SUPERCONDUCTING DEVICES".
[0063] A superconducting integrated circuit may include a
substrate; a base electrode overlying at least a portion of the
substrate, the base electrode superconductive in a range of
temperatures; a parallel-plate capacitor overlying at least a
portion of the base electrode, the parallel-plate capacitor
comprising: a first capacitor plate that is superconductive in a
range of temperatures; a metal-oxide layer overlying the first
capacitor plate; a second capacitor plate overlying the metal-oxide
layer, the second capacitor plate superconductive in a range of
temperatures, wherein the base electrode is superconductingly
electrically coupled to the first capacitor plate.
[0064] A method of fabricating a parallel-plate capacitor in a
superconducting integrated circuit may include forming a
metal-oxide layer to overlie at least a portion of a first
capacitor plate, the first capacitor plate comprising a material
that is superconductive in a range of temperatures; depositing a
second capacitor plate to overlie at least a portion of the
metal-oxide layer, the second capacitor plate comprising a material
that is superconductive in a range of temperatures; depositing a
base electrode to overlie at least a portion of a substrate, the
base electrode comprising a material that is superconductive in a
range of temperatures; depositing the first capacitor plate to
overlie at least a portion of the base electrode, the first
capacitor plate superconductingly electrically coupled to the base
electrode; and depositing a counter electrode to overlie at least a
portion of the second capacitor plate, the counter electrode
comprising a material that is superconductive in a range of
temperatures, wherein the counter electrode is superconductingly
electrically coupled to the second capacitor plate.
[0065] In some implementations, a kinetic-inductance transmission
line is used to route microwave signals with high isolation within
the processor fabric using three layers or less. See, for example,
PCT Patent Application No. WO2018US016237, SYSTEMS AND METHODS FOR
FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS, filed Jan. 31,
2018. On-chip transmission lines are ideally designed to be fully
enclosed (except at the point of coupling) and 50 ohm matched.
Impedance matching ensures that minimal, or at least reduced,
signal distortion occurs. Enclosing the transmission line ensures
minimal, or at least reduced, coupling to box modes or on-chip
structures. Additionally, the shield enclosing the transmission
line can at least partially isolate an on-chip device (for example,
a qubit) from high-frequency noise propagating on the line.
[0066] There can be challenges in implementing a 50 ohm
transmission line in a 3-layer (or higher) superconducting
integrated circuit. For example, there can be an undesirably large
capacitance between the center line and the ground in a fabrication
stack, in particular where the dielectric thickness is low and the
wire width is too large. A higher capacitance can result in a lower
characteristic impedance.
[0067] Some implementations include a transmission line with a
center conductor having a large kinetic inductance. For example,
the center conductor of the transmission line can include titanium
nitride (TiN). A higher inductance of the center line can
compensate for a higher capacitance between the center line and
ground. This approach can be used to form a fully-enclosed, 50 ohm
transmission line in as few as three metal layers in the
fabrication stack.
[0068] A method for fabricating a superconducting integrated
circuit may include depositing a first superconducting metal layer
to overlie at least a portion of a substrate; depositing a first
dielectric layer to overlie at least a portion of the first
superconducting metal layer; and depositing a kinetic inductance
layer to overlie at least a portion of the first dielectric layer,
wherein the kinetic inductance layer forms a center conductor for
an on-chip transmission line. The method may further include
depositing a passivation layer to overlie at least a portion of the
kinetic inductance layer. In some implementations, the method
further includes depositing a second superconducting metal layer to
overlie at least a portion of the passivation layer; depositing a
second dielectric layer to overlie at least a portion of the second
superconducting metal layer; and depositing a third superconducting
metal layer to overlie at least a portion of the second dielectric
layer, wherein the first and the third superconducting metal layers
form an outer conductor of the on-chip transmission line. In some
implementations, the method further includes depositing a second
dielectric layer to overlie at least a portion of the passivation
layer; and depositing a second superconducting metal layer to
overlie at least a portion of the second dielectric layer, wherein
the first and the second superconducting metal layers form an outer
conductor of the on-chip transmission line.
High-Bandwidth Lines
[0069] FIG. 1 is a schematic diagram illustrating an example
implementation of a microwave path 100 to a superconducting
circuit, according to the present disclosure. Microwave path 100 is
positioned in a cryogenic refrigeration system. The cryogenic
refrigeration system includes a still 102, a sample holder 104, and
mixing chamber 106. Microwave path 100 travels between still 102
and sample holder 104. Microwave path 100 is a microwave path
through the cryogenic refrigeration system. Still 102, sample
holder 104, and mixing chamber 106 are shown as dashed lines in
FIG. 1 to provide context for microwave path 100.
[0070] Sample holder 104 can contain or hold the superconducting
circuit. In some implementations, the superconducting circuit is an
integrated superconducting circuit. In some implementations, the
integrated superconducting circuit includes a quantum processor. In
some implementations, the quantum processor includes a plurality of
superconducting flux qubits. See, for example, PCT Patent
Application No. PCT/US2009/055939 (published as International
patent application publication WO 2010/028183A2), SYSTEMS, METHODS
AND APPARATUS FOR ACTIVE COMPENSATION OF QUANTUM PROCESSOR
ELEMENTS, filed Sep. 3, 2009.
[0071] Microwave path 100 traverses mixing chamber 106. Microwave
path 100 includes a superconducting coaxial cable 108 between still
102 and mixing chamber 106. In some implementations,
superconducting cable 108 is superconducting NbTi (niobium
titanium) coaxial cable.
[0072] Microwave path 100 includes a bandpass filter 110, a powder
filter 112, and a switch 114 for the operating band. In some
implementations, powder filter 112 is a superconducting powder
filter. Bandpass filter 110 is communicatively coupled to powder
filter 112 by a coaxial cable 116. In some implementations,
bandpass filter 110 is a GHz bandpass filter with greater than 90
dB out-of-band suppression of frequencies below 60 GHz. Bandpass
filter 110 and powder filter 112 in combination can determine at
least in part the filtering of signals on microwave path 100. The
use of one or both of bandpass filter 110 and powder filter 112 can
be optional in some implementations. One reason for including
filters is to reduce noise on high-bandwidth lines used for
programming devices such as devices in a quantum processor.
[0073] In some implementations operating at a temperature of
approximately 4 K (Kelvin), switch 114 is a CMOS (Complementary
Metal-Oxide-Semiconductor) switch. In other implementations
operating at a temperature of approximately 4 K, switch 114 is a
superconducting switch, e.g., a cryotron. In some implementations
operating at a temperature of approximately 10 mK, switch 114 is a
superconducting switch, e.g., a cryotron. In yet other
implementations, switch 114 is a broadband switch as described in
the present application with reference to FIGS. 11, 12, and 13. The
broadband switch of FIGS. 11, 12, and 13 is further described in
U.S. patent application Ser. No. 16/397,790, DYNAMICAL ISOLATION OF
A CRYOGENIC PROCESSOR, filed Apr. 29, 2019.
[0074] In some implementations, coaxial cable 116 is a copper
coaxial cable. Powder filter 112 is communicatively coupled to
switch 114 by coaxial cable 118. In some implementations, coaxial
cable 118 is a copper coaxial cable. Switch 114 is communicatively
coupled to sample holder 104 by coaxial cable 120. In some
implementations, coaxial cable 120 is a copper coaxial cable.
[0075] FIG. 2 is a schematic diagram illustrating another example
implementation of a microwave path to a superconducting circuit,
according to the present disclosure. Microwave path 200 is
positioned in a cryogenic refrigeration system. The cryogenic
refrigeration system includes a still 202, a sample holder 204, and
a mixing chamber 206. Microwave path 200 travels between still 202
and sample holder 204. Microwave path 200 is a microwave path
through the cryogenic refrigeration system. Still 202, sample
holder 204, and mixing chamber 206 are shown as dashed lines in
FIG. 2 to provide context for microwave path 200.
[0076] Sample holder 204 can contain or hold the superconducting
circuit. In some implementations, the superconducting circuit is an
integrated superconducting circuit. The integrated superconducting
circuit may comprise or include a quantum processor with one or
more other superconducting processors or devices, or may consist of
a quantum processor. In some implementations, the quantum processor
includes a plurality of superconducting flux qubits.
[0077] Microwave path 200 traverses mixing chamber 206. Microwave
path 200 includes a coaxial cable 208 between still 202 and mixing
chamber 206. In some implementations, coaxial cable 208 is a
superconducting coaxial cable. In some implementations, coaxial
cable is a stainless steel coaxial cable.
[0078] Microwave path 200 includes a bandpass filter 210 and a
switch 212. Bandpass filter 210 is communicatively coupled to
switch 212 by a coaxial cable 214. In some implementations,
bandpass filter 210 is a GHz bandpass filter with greater than 90
dB out-of-band suppression of frequencies below 60 GHz. In some
implementations, coaxial cable 214 is a copper coaxial cable.
Switch 212 is communicatively coupled to sample holder 204 by
coaxial cable 216. In some implementations, coaxial cable 216 is a
copper coaxial cable.
[0079] In some implementations operating at a temperature of
approximately 4 K, switch 212 is a CMOS switch. In other
implementations operating at a temperature of approximately 4 K,
switch 212 is a superconducting switch, e.g., a cryotron. In some
implementations operating at a temperature of approximately 10 mK,
switch 212 is a superconducting switch, e.g., a cryotron. In yet
other implementations, switch 212 is a broadband switch as
described in the present application with reference to FIGS. 11,
12, and 13.
Example Lumped-Element Resonators
[0080] FIG. 3A is a schematic layout of a portion of an example
implementation of a superconducting circuit 300 that includes a
superconducting half-wave resonator 302 and a transmission line
304, according to the present disclosure. For example,
superconducting half-wave resonator 302 can be a microstrip
resonator, a coplanar waveguide (CPW) resonator, or a
lumped-element resonator. For example, transmission line 304 can be
a microstrip transmission line, a CPW transmission line, or a
coaxial transmission line.
[0081] Superconducting half-wave resonator 302 includes a resonator
body 306. FIG. 3A illustrates a portion of resonator body 306. In
one implementation, resonator body 306 is 7 mm in length.
[0082] Region 308 (shown in FIG. 3A by hatching) is a region over
which a current in resonator body 306 is within a suitable
threshold of a maximum current. In some implementations, the
suitable threshold is 90% of the maximum current. In some
implementations, one portion of a length of resonator body 306 is
used for coupling to a DAC, and another portion of the length is
serpentine, e.g., to increase compactness of superconducting
half-wave resonator 302.
[0083] FIG. 3B is an enlarged view of a coupling region 310 of
superconducting half-wave resonator 302 of FIG. 3A. Superconducting
half-wave resonator 302 includes wiring 312 and a coupling
capacitor 314. In some implementations, coupling capacitor 314 is a
parallel-plate capacitor. In some implementations, coupling
capacitor 314 includes a thin-film metal-oxide layer as a
dielectric in the parallel-plate capacitor. See for example U.S.
Provisional Patent Application Ser. No. 62/660,719, "SYSTEMS AND
METHODS FOR FABRICATION OF SUPERCONDUCTING DEVICES", filed Apr. 20,
2018, and U.S. patent application Ser. No. 16/389,669, "SYSTEMS AND
METHODS FOR FABRICATION OF SUPERCONDUCTING DEVICES". In one
implementation, coupling capacitor 314 has dimensions of 30
.mu.m.times.20 .mu.m.
[0084] Superconducting circuit 300 includes a via 316, for example
to provide a superconducting communicative coupling between
transmission line 304 and a lower capacitor plate of coupling
capacitor 314. The lower capacitor plate of coupling capacitor 314
is not shown in FIG. 3B. A via is also referred to in the present
application as a VIA and a vertical interconnect access. A via is
an electrical communicative coupling between layers in an
electronic circuit. The via may pass through a plane of one or more
adjacent layers. The electronic circuit may be an integrated
circuit. The electronic circuit may be a printed circuit board. A
superconducting via is a superconducting electrical communicative
coupling between layers in a superconducting electronic
circuit.
[0085] Superconducting half-wave resonator 302 can have a symmetric
coupling to ground at the other end. The ground is also referred to
in the present application as an electrical ground. The ground is
not shown in FIGS. 3A and 3B. In some implementations, wiring 312
and/or transmission line 304 include 2 .mu.m lines over a 1 .mu.m
silicon dioxide (SiO2) dielectric, which can provide an impedance
close to 50.OMEGA.. In one implementation, superconducting
half-wave resonator 302 has a resonance at 9.58 GHz with
approximately 35 MHz of bandwidth.
[0086] FIG. 4A is a schematic layout of a portion of an example
implementation of a superconducting circuit 400a that includes a
superconducting lumped-element resonator 402 and a transmission
line 404, according to the present disclosure. Superconducting
lumped-element resonator 402 includes a resonator body 406.
[0087] Region 408 (shown in FIG. 4A by hatching) is a region over
which a current in resonator body 406 is within a suitable
threshold of a maximum current. In some implementations, the
suitable threshold is 90% of the maximum current.
[0088] FIG. 4B is an enlarged view of a coupling region 410 of
superconducting lumped-element resonator 402 of FIG. 4A.
Superconducting lumped-element resonator 402 includes wiring 412, a
coupling capacitor 414, and a shunting capacitor 416. In some
implementations, coupling capacitor 414 is a parallel-plate
capacitor. In some implementations, coupling capacitor 414 includes
a thin-film metal-oxide layer for a dielectric in the
parallel-plate capacitor. In one implementation, coupling capacitor
414 has dimensions of 30 .mu.m.times.30 .mu.m. In one
implementation, shunting capacitor 416 has dimensions 100
.mu.m.times.120 .mu.m.
[0089] Superconducting lumped-element resonator 402 can have a
symmetric coupling to ground at the other end. In some
implementations, wiring 412 and/or transmission line 404 include 2
.mu.m lines over a 1 .mu.m silicon dioxide (SiO2) dielectric, which
can provide an impedance close to 50.OMEGA.. In one implementation,
superconducting lumped-element resonator 402 has a resonance at
9.62 GHz with approximately 30 MHz of bandwidth.
[0090] FIG. 4C is a schematic drawing of a cross-section of a
portion of an example implementation of a superconducting circuit
400c that includes a superconducting lumped-element resonator 418
and a transmission line 420, according to the present
disclosure.
[0091] Superconducting circuit 400c is implemented in a multilayer
superconducting integrated circuit. Transmission line 420 is
coupled to a ground plane 422. Transmission line 420 is
superconductingly communicatively coupled by a superconducting via
424 and superconducting wiring 426 to a lower plate 428 of a
coupling capacitor (such as coupling capacitor 414 of FIG. 4B).
[0092] An upper plate 430 of the coupling capacitor is
superconductingly communicatively coupled to a resonator body 432
and an upper plate 434 of a capacitor coupling superconducting
lumped-element resonator 418 to a ground plane 436.
Resonator-Addressed DAC
[0093] Resonator-addressing of a superconducting digital-to-analog
converter (DAC) can use the DAC in operation to perform latching.
Resonator-addressing is also referred to in the present application
as resonator-loading of a DAC. A resonator can be integrated with a
DAC, and can, for example, be used to replace an ADDR line and/or a
TRIG line.
[0094] The superconducting DAC is a flux memory or flux storage
device. The DAC can convert a digital amount of flux into flux
stored in an analog device.
[0095] In some implementations, the DAC includes a loop of material
that is superconducting in a range of temperatures, the loop
interrupted by one or more Josephson junctions. In one
implementation, the DAC is an rf-SQUID (radio-frequency
superconducting quantum interference device) and includes a
superconducting loop interrupted by a single Josephson junction. In
another implementation, the DAC is a superconducting loop
interrupted by a compound Josephson junction (CJJ). A CJJ includes
two parallel current paths each interrupted by a Josephson
junction. The DAC CJJ loop can behave as a summing element for
magnetic flux. The loop can combine a direct current (DC) provided
by a wire (e.g., a twisted-pair) with a current induced by a
resonator. In some implementations, the wire is shared globally,
i.e., shared by multiple DACs in the processor, and the wire can
provide a global bias signal.
[0096] Storing flux in the DAC includes adding flux to the CJJ loop
of the DAC, and moving flux in the CJJ loop of the DAC into the
storage loop of the DAC (i.e., into the superconducting loop of the
DAC). Flux can be added to the CJJ loop of the superconducting DAC
by suppressing a Josephson junction in the CJJ using one or more
control signals or biases. Flux can be moved into the DAC storage
loop by suppressing another Josephson junction in the CJJ loop
using one or more control signals or biases. Multiple flux quanta
can be stored in a superconducting DAC implemented using a CJJ
loop.
[0097] See, for example, Johnson M. W. et al. "A scalable control
system for a superconducting adiabatic quantum optimization
processor", arXiv:0907.3757v2, 24 Mar. 2010 for a description of an
example implementation of flux DACs operable to control
superconducting devices in an integrated circuit.
[0098] An array of resonators can be used to provide one or more
signals that can be combined with the global bias signal to enable
addressing of DACs.
[0099] FIG. 5A is a schematic diagram illustrating an example
implementation of a superconducting circuit 500a that includes a
resonator-addressed DAC 502, according to the present
disclosure.
[0100] In superconducting circuit 500a, resonator-addressed DAC 502
includes a loop 504 of material that is superconductive in a range
of temperatures, and a CJJ 506. CJJ 506 includes two parallel
current paths each interrupted by a Josephson junction, Josephson
junctions 508 and 510, respectively.
[0101] Superconducting circuit 500a further includes a resonator
512, a transmission line 514, and interface 516 operable to provide
a global flux bias by a global flux bias line 516-1. Resonator 512
includes coupling capacitors 518 and 520, an inductive interface
522 to resonator-addressed DAC 502, and an optional shunting
capacitor 524. The term "inductive interface" is also referred to
in the present application as a coupling inductance. Coupling
inductance 522, for example, inductively communicatively couples
resonator 512 and resonator-addressed DAC 502.
[0102] Superconducting circuit 500a further includes a current bias
line 526 operable to provide a current bias to resonator-addressed
DAC 502.
[0103] In some implementations, multiple resonators are coupled to
a single DAC CJJ loop. FIG. 5B is a schematic diagram illustrating
another example implementation of a superconducting circuit 500b
that includes a resonator-addressed digital-to-analog converter
(DAC) 502, according to the present disclosure.
[0104] In FIG. 5B, the same reference numbers as used in FIG. 5A
are used in FIG. 5B to denote the same or similar elements. In
instances where there is more than one of a given element in the
implementation of FIG. 5B, the reference number has a suffix, for
example "a" or "b".
[0105] In superconducting circuit 500b, resonator-addressed DAC 502
includes a loop 504 of material that is superconductive in a range
of temperatures, and a CJJ 506. CJJ 506 includes two parallel
current paths each interrupted by a Josephson junction, Josephson
junctions 508 and 510, respectively.
[0106] Superconducting circuit 500b further includes a pair of
resonators 512a and 512b, a transmission line 514, and interface
516 operable to provide a global flux bias by a global flux bias
line 516-1. Resonator 512a includes coupling capacitors 518a and
520a, an inductive interface 522a to resonator-addressed DAC 502,
and an optional shunting capacitor (not shown in FIG. 5B for
clarity) like optional shunt capacitor 524 of FIG. 5A. Resonator
512b includes coupling capacitors 518b and 520b, an inductive
interface 522b to resonator-addressed DAC 502, and an optional
shunting capacitor (not shown in FIG. 5B for clarity) like optional
shunt capacitor 524 of FIG. 5A.
[0107] Superconducting circuit 500b further includes a current bias
line 526 operable to provide a current bias to resonator-addressed
DAC 502.
[0108] In one implementation, resonators 512a and 512b are both
coupled to transmission line 514. In another implementation,
resonator 512a is coupled to transmission line 514, and resonator
512b is coupled to another transmission line (not shown in FIG.
5B).
[0109] In an example where two resonators are coupled to the same
DAC CJJ loop, programming of the DAC can be achieved by having a
low-frequency bias signal and two microwave signals combine
constructively to exceed a determined address latching level. The
arrangement can be used to construct an XY-addressing scheme for a
set of DACs, for example as follows. Firstly, a DC current bias is
applied to the DAC by a line referred to in the present application
as a power line (PWR). Next, a global low-frequency bias address
line (such global flux bias line 516-1 of FIGS. 5A and 5B) is
coupled to each DAC CJJ loop of the set of DAC CJJ loops. Then, an
array of resonators is laid out across the processor in a
two-dimensional X-Y grid. Programming a selected DAC can be
achieved by pre-biasing the set of DAC CJJ loops, and activating
the two resonators (also referred to in the present application as
the address and trigger resonators) that intersect at the selected
DAC.
[0110] The selected DAC can be programmed when the two microwave
tones (at frequencies f.sub.lo and f.sub.hi respectively) add
constructively at the selected DAC. A relative phase between the
two microwave tones can evolve at an angular frequency co given by
the following expression:
.omega.=2.pi./(f.sub.hi-f.sub.lo)
The higher frequency tone can advance by
.delta..theta.=.omega./f.sub.lo radians per cycle relative to the
low frequency tone. Each time the low frequency tone is at a
maximum, the high frequency tone can have advanced by an angle of
dB. The angle .delta..theta. can represent the closest the maxima
can approach within a cycle at the beat frequency, and, since the
angle .delta..theta. can be linearly proportional to the beat
frequency .omega., it can be desirable to select a smaller beat
frequency .omega.. On the other hand, the smaller the beat
frequency .omega., the longer it will take to complete a full 2.pi.
rotation.
[0111] It can be desirable to leave the resonator charged no more
than a few multiples of .tau.=1/(2.pi..DELTA.f) where .DELTA.f is
the bandwidth per tone (also referred to in the present application
as a linewidth of the resonator). It can typically take a few
multiples of .tau. to charge and discharge the resonator.
Programming can be completed roughly on the same timescale for
efficient bandwidth utilization. This suggests that it can be
desirable to match the beat frequency to the linewidth of the
resonator.
[0112] This leads to a criterion for completing the programming in
a reasonable time--that the beat frequency should be approximately
matched to a resonator linewidth (.omega..about.2.pi..DELTA.f).
This is consistent with a preference for resonances within a single
array to be separated by a few linewidths .DELTA.f to avoid, or at
least reduce, cross-talk between channels. With the beat frequency
determined, the resonant frequencies can, in general, be selected
to be at higher frequencies consistent with the determined beat
frequency.
[0113] FIG. 5C is a schematic diagram illustrating an example
implementation of a superconducting circuit 500c that includes a
pair of resonator-addressed digital-to-analog converters (DACs)
502a and 502b, according to the present disclosure.
[0114] The same reference numbers as used in FIG. 5A are used in
FIG. 5C to denote the same or similar elements. In instances where
there is more than one of a given element in the implementation of
FIG. 5C, the reference number has a suffix, for example "a" or
"b".
[0115] In superconducting circuit 500c, resonator-addressed DAC
502a includes a loop 504a of material that is superconductive in a
range of temperatures, and a CJJ 506a. CJJ 506a includes two
parallel current paths each interrupted by a Josephson junction,
Josephson junctions 508a and 510a, respectively.
Resonator-addressed DAC 502b includes a loop 504b of material that
is superconductive in a range of temperatures, and a CJJ 506b. CJJ
506b includes two parallel current paths each interrupted by a
Josephson junction, Josephson junctions 508b and 510b,
respectively.
[0116] Superconducting circuit 500c further includes a resonator
512, a transmission line 514, and interfaces 516a, 516b operable to
provide a global flux bias by a global flux bias line 516-1.
Resonator 512 includes coupling capacitors 518 and 520, an
inductive interface 522c to resonator-addressed DAC 502a, an
inductive interface 522d to resonator-addressed DAC 502b, and an
optional shunting capacitor 524.
[0117] Superconducting circuit 500c further includes a current bias
line 526a operable to provide a current bias to resonator-addressed
DAC 502a, and a current bias line 526b operable to provide a
current bias to resonator-addressed DAC 502b.
[0118] A variation in current along the body of resonator 512 of
FIG. 5C can be at least partially compensated for by tuning each
coupling of resonator 512 to DAC CJJ loops 502a and 502b. In some
implementations, resonator 512 can be coupled to more than two DAC
CJJ loops (only two DAC CJJ loops are shown in FIG. 5C), and a
variation in current along the body of resonator 512 can be at
least partially compensated for by tuning each coupling of
resonator 512 to a respective DAC CJJ loop.
[0119] FIG. 5D is a schematic diagram illustrating another example
implementation of a superconducting circuit 500d that includes a
resonator-addressed digital-to-analog converter (DAC) 502,
according to the present disclosure. Resonator 512 of FIG. 5D
includes a DC-SQUID (direct current superconducting quantum
interference device) 528. DC-SQUID 528 includes a pair of Josephson
junctions 530 and 532. Superconducting circuit 500d includes an
interface 534. Interface 534 can be provided by a DAC or an analog
line, for example. A resonant frequency of resonator 512 of FIG. 5D
can be tuned by applying a flux bias to DC-SQUID 532 by interface
534.
[0120] In some implementations, a critical current of at least one
of Josephson junctions 530 and 532 is comparable in magnitude to a
current in resonator 512.
[0121] Instead of capacitively communicatively coupling resonator
512 of FIGS. 5A, 5C, and 5D to transmission line 514 by coupling
capacitor 518, resonator 512 can be communicatively coupled to
transmission line 514 by an inductive coupling. For example,
resonator 512 can be inductively communicatively coupled to
transmission line 514 by an inductive coupling to a portion of the
body of resonator 512.
[0122] Similarly, instead of capacitively communicatively coupling
each of resonators 512a and 512b of FIG. 5B to a respective
transmission line by a respective coupling capacitor, at least one
of resonators 512a and 512b can be inductively communicatively
coupled to the respective transmission line by an inductive
coupling to a portion of the body of the resonator.
[0123] FIG. 5E is a schematic diagram illustrating an example
implementation of a superconducting circuit 500e that includes a
resonator-addressed digital-to-analog converter (DAC) 502, and a
resonator 512 that is inductively coupled to transmission line 514,
according to the present disclosure. The same reference numbers as
used in FIG. 5A are used in FIG. 5E to denote the same or similar
elements.
[0124] Superconducting circuit 500e includes a transmission line
inductance 536, and matching capacitors 538 and 540. Matching
capacitors 538 and 540 can at least partially tune an impedance of
transmission line 514 (e.g. to cause the impedance of transmission
line 514 to be approximately 50.OMEGA.).
[0125] Resonator 512 can be inductively communicatively coupled to
transmission line 514 by a shared galvanic inductance 536.
Resonator 512 can be used to address one or more DACs or other
superconducting devices. Resonator 512 includes a first part 542
that includes an inductive interface 522 to resonator-addressed DAC
502, and a second part 544 that includes an inductive interface 546
to another resonator-addressed DAC (not shown in FIG. 5E). First
part 542 includes a capacitor 520, and second part 544 includes a
capacitor 548.
[0126] FIG. 5F is a schematic diagram illustrating another example
implementation of a superconducting circuit 500f that includes a
resonator-addressed digital-to-analog converter (DAC) 502, and a
resonator 512 that is inductively coupled to transmission line 514,
according to the present disclosure. The same reference numbers as
used in FIG. 5A are used in FIG. 5F to denote the same or similar
elements. Superconducting circuit 500f includes a coupling
inductance 550 that can inductively communicatively couple
resonator 512 to transmission line 514 by transmission line
inductance 536. Coupling inductance 550 and transmission line
inductance 536 form a magnetic transformer by which resonator 512
is inductively coupled to transmission line 514.
[0127] FIG. 6 is a flow chart illustrating an example method 600
for programming a DAC according to the present disclosure. FIG. 6
illustrates a sequence of currents used to load a single flux
quantum into a DAC storage loop using standard 30 MHz lines, for
example. Method 600 may be implemented by a programming system. For
example, method 600 may be implemented by electronics, for example
electronics operating at room temperature. In some implementations,
the phases and amplitudes of the high-frequency tones are
controllable, for example, by electronics operating at room
temperature.
[0128] Method 600 includes acts 602 to 620, though those of skill
in the art will appreciate that in alternative embodiments certain
acts may be omitted and/or additional acts may be added. Those of
skill in the art will appreciate that the illustrated order of the
acts is shown for exemplary purposes only and may change in
alterative embodiments.
[0129] Method 600 starts at 602, for example in response to an
initiation of a programming of a DAC. At 604, the DAC power level
in the current line to the resonator-addressed DAC (such as
resonator-addressed DAC 502 of FIG. 5A) is raised to a
pre-calibrated level or defined calibration level. At 606, the
global address bias line is raised to a pre-calibrated level or
defined calibration level, thereby applying a flux bias to one or
more resonator-addressed DACs. The level can be calibrated to cause
the level to cross a predetermined or defined upper threshold when
high-frequency microwave pulses are applied by a transmission line
(such as transmission line 514 of FIG. 5A) and a resonator (such as
resonator 512 of FIG. 5A). The upper threshold can be selected to
cause a flux quantum to be added to the CJJ loop when the upper
threshold is exceeded by applying and combining the global bias and
the high-frequency microwave pulses.
[0130] At 608, the high-frequency ADDR and/or TRIG (e.g., X and/or
Y) microwave pulses are applied to selected devices, e.g., to
selected resonator-addressed DACs. In an XY-addressing scheme, the
flux bias injected into the DAC by the ADDR (or X) line can be
one-half of the flux needed to cause the combined address signal
current (see, for example, FIG. 7A) to exceed a threshold for
programming the DAC, and the flux bias injected into the DAC by the
TRIG (or Y) line can similarly be one-half of the flux needed to
cause the combined address signal current to exceed a threshold for
programming the DAC. The DAC is programmed only when a threshold is
exceeded in the combined address signal current (see, for example,
FIGS. 7A-7C and accompanying description). The systems and methods
described in the present application can cause the threshold to be
exceeded when a) a sufficient flux bias is applied by a global
address bias line, and b) there are pulses on the ADDR (X) and TRIG
(Y) address lines.
[0131] Use of a global flux bias can be beneficial for at least the
following two reasons. Firstly, the global flux bias breaks the
symmetry, and eliminates, or at least reduces, the possibility that
the method described above causes the DAC to be "de-programmed".
De-programming refers to removal of a flux quantum or flux quanta
from a DAC storage loop. In regular operation, a DAC can be
intentionally programmed and de-programmed by adding or removing,
respectively, flux quanta from the DAC storage loop. Unintentional
de-programming can be eliminated or at least reduced by breaking
the DAC symmetry, for example by adding a DC flux offset with a
global line or using asymmetric junctions (as described below).
Secondly, the bias reduces the power requirements for the
high-frequency microwave pulses.
[0132] At 610, the programming system determines whether it is
ready to lower the address line. If, the programming system
determines it is ready to lower the address line, then method 600
proceeds to 612, otherwise it continues to wait. At 612, the global
address bias line level is lowered below a predetermined threshold,
thereby reducing the global flux bias applied to the DACs. Lowering
the address line below the predetermined lower threshold causes the
flux quantum to move into the DAC storage loop.
[0133] At 614, the programming system determines whether
programming is complete. If, the programming system determines that
programming is complete, then method 600 proceeds to 616, otherwise
it continues to wait. At 616, the power line is returned to its
initial level. In some implementations, the power line is returned
to zero current. At 618, the address line is returned to its
initial level. In some implementations, the address line is
returned to zero current.
[0134] FIGS. 7A, 7B and 7C are graphs showing plots illustrating an
example time series for loading of a single flux quantum according
to the present disclosure. FIG. 7A is a plot of the combined
address signal current 702 as a function of time. Combined address
signal current 702 includes a global bias 704 and high-frequency
pulses 706. Combined address signal current is raised above
threshold 708 to cause loading of a single flux quantum into a DAC
CJJ loop.
[0135] FIG. 7B is a plot of a power signal current 710 as a
function of time. At time t.sub.0, power signal current 710 is
raised. At time t.sub.1, power signal current 710 is raised.
[0136] Referring again to FIG. 7A, combined address signal current
exceeds threshold 708 at time t.sub.2. At time t.sub.3, global bias
704 is lowered thereby lowering combined address signal current
702.
[0137] FIG. 7C is a plot of the persistent current 712 in the DAC
storage loop as a function of time. Persistent current 712 steps
down at time t.sub.2, and steps down again at time t.sub.3. At time
t.sub.3, persistent current 712 steps down below a predetermined
lower threshold 714.
[0138] In the example illustrated in FIG. 7C, the DAC persistent
current at to is zero. After t.sub.2, persistent current 712
includes a current induced by magnetic flux added to the DAC CJJ
loop. After t.sub.3, persistent current 712 includes a current
induced by magnetic flux moved from the DAC CJJ loop into the DAC
storage loop. After t.sub.4, persistent current 712 includes a
current induced by the one or more flux quanta stored in the
DAC.
[0139] Loading one or more flux quanta into the DAC is also
referred to in the present application as programming the DAC.
Programming the DAC can also include removing one or more flux
quanta from the DAC storage loop, and is also referred to in the
present application as de-programming. In one implementation,
removing one or more flux quanta from the DAC storage loop includes
reversing a signal on an address line.
[0140] Two additional control interfaces can be included to ensure
programming can be completed by intersecting resonators. The two
additional control interfaces are to control the phase and the
amplitude of the driving tones (also referred to in the present
application as resonant frequencies). Calibration can be used
determine a range over which the phase and the amplitude of the
driving tones can be adjusted consistent with programming for a
target DAC. Depending on the size of the range, it can be possible
to program multiple devices at the same time. The size of the range
can at least partially depend on: a) a variation in the current
amplitude over the length of the resonator, and/or b) a degree of
homogeneity in a coupling between each resonator and a respective
CJJ loop.
Addressing Technology for Superconducting Devices
[0141] FIG. 8 shows a hybrid computing system 800 according to at
least one exemplary implementation, including a digital computer
802 and a quantum computer 804, that may incorporate systems and
methods described in the present application, including
resonator-addressed DACs.
[0142] Digital computer 802 comprises CPU 806, user interface
elements 808, 810, 812 and 814, disk 816, controller 818, bus 820
and memory 822. Memory 822 comprises modules 824, 826, 828, 830,
and 832, and FMR Readout module 834.
[0143] Quantum computer 804 can incorporate FMR technology
comprising superconducting resonators (such as superconducting
resonator 302 of FIG. 3A). Quantum computer 804 can comprise a
resonator-addressed DAC such as resonator-addressed DAC 502 of
FIGS. 5A-5F. Quantum computer 804 comprises quantum processor 836,
FMR readout control system 838, qubit control system 840 and
coupler control system 842.
Power Line (Z) Frequency-Multiplexed Flux-DAC Addressing
[0144] As described above, a shortcoming of a conventional scheme
for addressing a superconducting device, for example a flux storage
device such as DAC, can be that an implementation of the
conventional scheme may include a large number of wires and
superconducting low-pass filters which can be costly to produce,
vulnerable to failure, and a source of high-energy photons from
internal filter heating. In some implementations, the wires are
twisted-pairs and the low-pass filters are custom-made
superconducting low-pass filters. The systems and methods described
in the present application include replacing wires by coaxial cable
which can provide greater bandwidth and reduced complexity. A
benefit of greater bandwidth can be improved processor input/output
(I/O) speed.
[0145] The systems and methods described in the present application
include frequency-domain multiplexing of signals on microwave
lines. The systems and methods described in the present application
include programming a DAC, or other suitable superconducting device
on a superconducting circuit, by using signals to activate power
line resonators with calibrated resonator amplitudes, and by using
signals to implement an XY-addressing scheme (such as trigger and
address signals described in the present application).
[0146] In some implementations of addressing schemes,
superconducting devices are addressable on a three-dimensional grid
using combinations of three external bias signals. One of these
external bias signals is typically a common current bias provided
to a set of one or more superconducting devices. The line that
provides the common current bias is referred to in the present
application as a power (PWR) line. Each PWR line can provide a
current bias to a respective set of one or more superconducting
devices.
[0147] The other two bias signals are referred to in the present
application as trigger (TRIG) and address (ADDR) biases. See, for
example, a description of XYZ-addressing of flux DACs earlier in
the present application.
[0148] As described above with reference to FIGS. 5A through 5F,
FIG. 6, and FIG. 7A through 7C, programming of a DAC coupled to two
superconducting resonators can be achieved by having a
low-frequency bias signal and two microwave signals combine
constructively to exceed a determined address latching level. The
arrangement can be used to construct an XY-addressing scheme for a
set of DACs. In one implementation, an array of superconducting
resonators is laid out across a superconducting integrated circuit
(e.g., a quantum processor) in a two-dimensional grid. A global
low-frequency bias address line is coupled to each DAC CJJ loop of
the set of DAC CJJ loops. Programming a selected DAC can be
achieved by pre-biasing the set of DAC CJJ loops, and activating
the two resonators (also referred to in the present application as
the address and trigger resonators) that intersect at the selected
DAC.
[0149] Some implementations employ an XYZ-addressing scheme in
which a low-frequency or DC current bias is applied to a DAC by a
line referred to in the present application as a power (PWR) line.
Current bias line 526 of FIGS. 5A and 5B, and current bias lines
526a and 526b of FIG. 5C are examples of PWR lines. As described
below, in some implementations, a PWR line can be driven by an
alternating current (AC) signal. The AC signal may include a DC
component. Also, as described below, Josephson junctions in a CJJ
of a DAC may be asymmetric, i.e., may have different critical
currents, in which case a DC bias provided by a PWR line, for
example, may be at least reduced. The phrase "at least reduced" in
the present application means eliminated or reduced. In some
implementations, a PWR line to a DAC with asymmetric junctions is
driven by an AC signal, and the AC signal may have no DC
component.
[0150] A superconducting integrated circuit may be fabricated with
Josephson junctions that have different critical currents.
Josephson junctions may have critical currents that lie within a
range of critical currents. A critical current of a Josephson
current may depend on various factors including junction size.
Adequate control of junction size during fabrication can be
advantageous in targeting a desired critical current value. For
example, in some cases, critical current is at least approximately
proportional to the square of a junction diameter.
[0151] In a conventional arrangement, the PWR lines provide a DC
bias and are generally galvanically coupled to a body of the DAC.
The DC bias can be applied to an array of DACs referred to in the
present application as a domain or power domain. The domains are
the Z-dimension in the XYZ-addressing scheme. In an example
implementation of a quantum processor, the quantum processor
includes 24 domains supplied by 24 twisted pair lines. Programming
a DAC in a domain can include applying a DC bias to the domain, and
applying XY signals (as described above) to a CJJ loop of the
DAC.
[0152] The present application describes a technology for providing
a PWR bias by a superconducting resonator. The domain can include
one or more DACs coupled to a superconducting resonator. The
superconductor resonator can be supplied with a DC bias as a DC
current through a body of the superconducting resonator. The DC
current can be common to multiple resonators and can be supplied,
for example, by a single twisted pair. The domain can be activated
(to provide Z-addressing of the domain) by exciting microwave
current in the resonator.
[0153] The PWR lines can be frequency-multiplexed.
Frequency-multiplexing on the transmission line can be used to
activate one of an array of resonators coupled to the transmission
line.
[0154] In some implementations of the technology described in the
present application, a superconducting resonator used to provide a
PWR bias can be a superconducting resonator that is communicatively
coupled to a microwave transmission line.
[0155] The technology described in the present application can
cause a low-frequency (or DC) PWR bias to be combined with a
high-frequency (e.g., microwave) current along the resonator body
to provide PWR addressing. The low-frequency bias can be applied to
more than one resonator. The low-frequency bias can be a global
bias applied to a set of resonators.
[0156] In some implementations (e.g., implementations described
below with reference to FIGS. 9A and 9B), programming the DAC (or
other suitable superconducting device or flux storage device)
includes summing the low-frequency (or DC) and high-frequency (or
microwave) currents in the resonator body. In other implementations
(e.g., implementations described with references to FIGS. 5A
through 5F, FIG. 6, and FIGS. 7A through 7C), low-frequency and
high-frequency signals are combined by summing of flux in a CJJ
(such as CJJ 506 of FIG. 5A).
[0157] The technology described in the present application
integrates a superconducting resonator with a DC line. In some
implementations, the DC line is integrated with an electronic
filter. In some implementations, a superconducting resonator (or an
array of superconducting resonators) and a DC line are integrated
on-chip. The integrated component can sum currents in at least two
frequency bands (e.g., microwave and DC).
[0158] It is generally desirable for the low-frequency signal path
to the superconducting resonator to have a high impedance at
microwave frequencies. One reason for having a high impedance at
microwave frequencies is to reduce a load on the superconducting
resonator. The inclusion of an electronic filter in the
low-frequency signal path can cause the low-frequency (or DC) line
to appear as a high impedance at a microwave frequency, e.g., a
resonance frequency of the superconducting resonator. In some
implementations (including those discussed with reference to FIG.
10, and those that include an array of superconducting resonators),
the inclusion of an electronic filter in the low-frequency signal
path can cause a decoupling of two superconducting resonators.
[0159] FIG. 9A is a schematic diagram illustrating an example
implementation of a superconducting circuit 900a, according to the
present disclosure. Superconducting circuit 900a includes a
superconducting device addressed by a superconducting resonator.
The superconducting device can be a superconducting flux storage
device such as resonator-addressed DAC 902 of FIG. 9A, according to
the present disclosure.
[0160] Superconducting circuit 900a can provide Z (power line)
addressing of resonator-addressed DAC 902. As described above, a DC
bias can be supplied to a body of a resonator, and summed with a
high-frequency current from a microwave transmission line. Z (power
line) addressing can be achieved by selectively activating a domain
using a high-frequency (microwave) current.
[0161] In superconducting circuit 900a, resonator-addressed DAC 902
includes a loop 904 of material that is superconductive in a range
of temperatures, and a compound Josephson junction (CJJ) 906. CJJ
906 includes two parallel current paths each interrupted by a
Josephson junction, Josephson junctions 908 and 910,
respectively.
[0162] Superconducting circuit 900a further includes a resonator
912a, and a transmission line 914. Resonator 912a of FIG. 9A is
referred to in the present application as a power (PWR) line
resonator. Resonator 912a includes coupling capacitors 916a and
918a, and lines 920a and 922a to resonator-addressed DAC 902.
[0163] Lines 920a and 922a are communicatively coupled to a
low-frequency (or DC) signal source 924 by an electronic filter
926. Electronic filter 926 is operable to remove selected frequency
components. Selected frequency components can include a
high-frequency component. Selected frequency components can include
a resonance frequency of a superconducting resonator. Electronic
filter 926 can be a low-pass filter, a notch filter, or a band-pass
filter.
[0164] Instead of capacitively communicatively coupling resonator
912a to transmission line 914 by coupling capacitor 916a, resonator
912a can be communicatively coupled to transmission line 914 by an
inductive coupling. For example, resonator 912a can be inductively
communicatively coupled to transmission line 914 by an inductive
coupling to a portion of the body of resonator 912a. See, for
example, FIGS. 5E and 5F.
[0165] In some implementations, multiple resonators are coupled to
a single DAC CJJ loop. See, for example, FIG. 5B.
[0166] FIG. 9B is a schematic diagram illustrating another example
implementation of a superconducting circuit 900b, according to the
present disclosure. Superconducting circuit 900b includes a
superconducting device addressed by a superconducting resonator.
The superconducting device can be a superconducting flux storage
device such as resonator-addressed DAC 902 of FIG. 9B. The same
reference numbers as used in FIG. 9A are used in FIG. 9B to denote
the same or similar elements.
[0167] In superconducting circuit 900b, resonator-addressed DAC 902
includes a loop 904 of material that is superconductive in a range
of temperatures, and a CJJ 906. CJJ 906 includes two parallel
current paths each interrupted by a Josephson junction, Josephson
junctions 908 and 910, respectively.
[0168] Superconducting circuit 900a further includes a resonator
912b, and a transmission line 914. Resonator 912b of FIG. 9B is
referred to in the present application as an XY-resonator.
Resonator 912b includes coupling capacitors 916b and 918b, and
lines 920b and 922b which are communicatively coupled to a
low-frequency (or DC) signal source 924 by an electronic filter
926. Electronic filter 926 is operable to remove selected frequency
components. Selected frequency components can include a
high-frequency component. Selected frequency components can include
a resonance frequency of a superconducting resonator. Electronic
filter 926 can be a low-pass filter, a notch filter, or a band-pass
filter.
[0169] Referring again to FIG. 5A, superconducting circuit 500a
includes resonator 512 (referred to in the present application as
an XY resonator--for its role in XY addressing described in the
present application), and interface 516 and global flux bias line
516-1. In the implementation of superconducting circuit 900b of
FIG. 9B, interface 516 and global flux bias line 516-1 are replaced
by a DC current bias supplied to the body of resonator 912b of FIG.
9B by signal source 924 on a signal path that includes electronic
filter 926.
[0170] A benefit of superconducting circuit 900b over
superconducting circuit 500a is that interface 516 and global flux
bias line 516-1 can be eliminated in some implementations, thereby
reducing a challenge of laying out superconducting circuit 900b,
e.g., reducing an area occupied by superconducting circuit 900b on
a superconducting integrated circuit.
[0171] Instead of capacitively communicatively coupling resonator
912b of FIG. 9B to transmission line 914 by coupling capacitor
916b, resonator 912b can be communicatively coupled to transmission
line 914 by an inductive coupling. For example, resonator 912b can
be inductively communicatively coupled to transmission line 914 by
an inductive coupling to a portion of the body of resonator 912.
See, for example, FIGS. 5E and 5F. In some implementations,
multiple resonators are coupled to a single DAC CJJ loop. See, for
example, FIG. 5B.
[0172] Resonator 912b further includes an inductive interface 928
to resonator-addressed DAC 902. The term "inductive interface" is
also referred to in the present application as a coupling
inductance. Coupling inductance 928 inductively communicatively
couples resonator 912b and resonator-addressed DAC 902.
[0173] Resonator 912b further includes an optional shunting
capacitor 930.
Asymmetry of Josephson Junctions in CJJ
[0174] As described above, a compound Josephson junction (CJJ) (for
example, CJJ 906 of FIG. 9) includes two parallel current paths
each interrupted by a Josephson junction (for example, Josephson
junctions 908 and 910, respectively).
[0175] In some implementations, as described above, applying a bias
current, a low-frequency flux bias, and a high-frequency flux bias
in combination may cause a combined address signal level to exceed
a defined address signal latching level for a superconducting flux
storage device.
[0176] In some implementations, the Josephson junctions of the CJJ
are asymmetric, i.e., a critical current of one junction is
different from a critical current of the other junction. A bias
current that, in combination with a low-frequency flux bias and a
high-frequency flux bias, causes a combined address signal level to
exceed a defined address signal latching level for a
superconducting flux storage device may be at least reduced by an
asymmetry in the Josephson junctions of the CJJ. In some
implementations, the current bias line is eliminated.
[0177] FIG. 9C is a schematic diagram illustrating an example
implementation of a superconducting circuit 900c with asymmetric
Josephson junctions in a compound Josephson junction of a
superconducting flux storage device, according to the present
disclosure. Superconducting circuit 900c is the same as
superconducting circuit 900b except that CJJ 906 of FIG. 9B is
replaced by CJJ 932. CJJ 932 comprises asymmetric Josephson
junctions 934 and 936.
[0178] An asymmetry of Josephson junctions 934 and 936 is indicated
for the purposes of FIG. 9C by a smaller symbol for Josephson
junction 934 than for Josephson junction 936. As explained in more
detail below, an asymmetry refers to a difference in critical
currents between Josephson junctions 934 and 936. In some
implementations, the difference in critical currents may at least
in part depend on a difference in size between Josephson junctions
934 and 936. In other implementations, Josephson junction 934 and
936 have different critical currents while being at least
approximately the same size.
[0179] In the present application, a CJJ with an asymmetry in the
Josephson junctions of the CJJ refers to a CJJ that includes two
parallel current paths each parallel current path interrupted by a
respective Josephson junction, in which the critical current of a
Josephson junction interrupting one of the two parallel current
paths of the CJJ is not the same as the critical current of a
Josephson junction interrupting the other of the two parallel
current paths of the CJJ.
[0180] Critical current has a specific meaning with respect to a
Josephson junction that would be known to one of ordinary skill in
the art. Equations governing the dynamics of a Josephson junction
and the Josephson effect include the following:
U ( t ) = 2 e .differential. .PHI. .differential. t
##EQU00001##
[0181] The above equation can be referred to as the superconducting
phase evolution equation and relates the voltage U(t) across a
Josephson junction to the change in phase difference .phi.(t)
across the Josephson junction.
I(t)=I.sub.C sin .phi.(t)
[0182] The above equation can be referred to as the Josephson or
weak-link current-phase relation, and describes the current I(t)
through the Josephson junction. The current I.sub.C is a constant
referred to as the critical current of the Josephson junction.
[0183] These equations can be found, for example, in Barone, A.,
and Paterno, G., Physics and Applications of the Josephson Effect,
(1982), John Wiley & Sons, ISBN 978-0-471-01469-0.
[0184] The critical current is the current in a superconductive
material above which the material is normal (not superconducting)
and below which the material is superconducting, at a specified
temperature and in the absence of external magnetic fields. See,
for example, Critical Current. (n.d.) McGraw-Hill Dictionary of
Scientific & Technical Terms, 6E. (2003). Retrieved Oct. 23,
2018 from
https://encyclopedia2.thefreedictionary.com/Critical+Current.
[0185] In yet other implementations, a low-frequency flux bias
that, in combination with a bias current and a high-frequency flux
bias, causes a combined address signal level to exceed a defined
address signal latching level for a superconducting flux storage
device is at least reduced by an asymmetry in the Josephson
junctions of the CJJ. In some implementations, the low-frequency
flux bias line is eliminated. In some implementations, both the
current bias line and the low-frequency flux line are
eliminated.
[0186] More generally, other suitable DAC addressing schemes can
include asymmetry of Josephson junctions, for example in a CJJ of a
DAC (or other flux storage device). In the case of a
resonator-addressed DAC, a resonator can provide a sinusoidal flux
signal to a CJJ loop of the DAC, and can advantageously allow for
elimination of a global DC flux bias line, for example, and/or a
current bias line.
Process control monitoring (PCM) line for an array of
capacitively-coupled superconducting resonators.
[0187] As described in the present application, an array of
superconducting resonators can be coupled to a single transmission
line, and used, for example, to enable frequency-domain
multiplexing in a variety of applications (e.g., in applications
involving qubits, kinetic-inductance detectors (KIDs),
transition-edge sensors and in other applications which can be
integrated with resonant devices).
[0188] It can be desirable to probe a superconducting device or a
superconducting integrated circuit using a low-frequency or DC
signal at room temperature (or at least at a higher temperature
than a cryogenic temperature) to determine whether a resonator body
in the device, or circuit, includes an electrical short or open, or
has an unexpected resistance. An electrical short, open, or
unexpected resistance can be caused by, for example, shrinkage of a
critical dimension, variations in the thickness of a layer in a
multilayer integrated circuit, material quality issues, and/or
other fabrication issues.
[0189] One approach to dealing with fabrication failures is to
simply accept a loss in yield. In some applications, for example,
KIDs are used for imaging, and the loss of a few resonators
corresponds to the loss of a few pixels in an imaging array. This
can be acceptable as the array can be scanned over the image area
in order to fill-in the missing data arising from the loss of
pixels. In other applications, a frequency-multiplexed resonant
readout uses an array of resonators for readout of qubit values in
a quantum processor. The loss of a few resonators results in a
commensurate reduction in readout speed, and may be acceptable.
[0190] In other applications, it can be important to know that at
least an acceptable number of resonators in an array of resonators
have yielded. In an application where an array of resonators is
used to address an array of superconducting flux-DACs in a quantum
processor, loss of a resonator can result in an inoperable
processor. In another application where a large-scale array of
superconducting transmon qubits is used for gate-model quantum
computing, loss of a resonator can similarly result in an
inoperable system. A transmon qubit is a type of superconducting
charge qubit. Transmon is an abbreviation of transmission line
shunted plasma oscillation qubit.
[0191] For at least these reasons, it can be advantageous to
measure the health of an array of resonators at room temperature
(or at least at a higher temperature than a cryogenic temperature)
to reduce the likelihood of encountering an inoperable resonator
after a system has been cooled to a cryogenic temperature.
[0192] The systems and methods described in the present application
include the use of a low-frequency or DC line at a temperature
higher than a cryogenic temperature to determine the health of a
resonator in an array of superconducting resonators or the health
of a qubit in an array of superconducting qubits. In some
implementations, the resonators in the array of superconducting
resonators is capacitively communicatively coupled to one or more
transmission lines (e.g., microwave transmission lines). In other
implementations, the resonators in the array of superconducting
resonators are inductively coupled to one or more transmission
lines.
[0193] In some implementations, the PCM line is also used, during
operation of a superconducting circuit, as a DC bias line. The DC
bias line may be global DC bias line. The superconducting circuit
may include an array of capacitively-coupled superconducting
resonators.
[0194] As described above with reference to FIGS. 9A and 9B, a DC
bias can be added to a resonator body. The DC bias of FIGS. 9A and
9B can be used to probe the health of a resonator at a temperature
higher than a cryogenic temperature, for example at room
temperature (approximately 20.degree. C.). For example, the DC bias
can be used to probe for an electrical short, an open, or an
unexpected resistance.
[0195] FIG. 10 is a schematic diagram illustrating an example
implementation of a superconducting circuit 1000 that includes an
array of N resonators 1002-1, 1002-2, and 1002-N (collectively
referred to in the present application as resonators 1002),
according to the present disclosure. Though at least three
resonators are shown in FIG. 10, the number N of resonators in
array of N resonators 1002 can be less than three or more than
three.
[0196] Array of N resonators 1002 can be XY resonators or Z
resonators (as described in the present application), for example.
For example, resonator 912a of FIG. 9A (a Z resonator) can be a
member of an array of resonators communicatively coupled to one
another and to a transmission line as illustrated by array of N
resonators 1002 of FIG. 10. Similarly, resonator 912b (an XY
resonator) of FIG. 9B can be a member of an array of resonators
communicatively coupled to one another and to a transmission line
as illustrated by array of N resonators 1002 of FIG. 10.
[0197] FIG. 10 is an example implementation of a superconducting
circuit that can be used to assess whether a DC short or open is
present in a body of a resonator in an array of resonators. The
array of resonators can be an array of superconducting resonators.
A superconducting resonator is a resonator with a resonator body
that is superconducting below a critical temperature. The
superconducting resonator can be capacitively coupled or
inductively coupled to a transmission line, for example a microwave
transmission line. The microwave transmission line can be, for
example, one of a microstrip transmission line, a stripline
transmission line, a coaxial transmission line, and a co-planar
waveguide transmission line.
[0198] Superconducting circuit 1000 of FIG. 10 includes a DC wire
that communicatively couples one or more resonators in an array of
resonators to a signal source. In this configuration, the resonator
bodies can be wired in series at DC. As described with reference to
FIG. 10 below, one or more electronic filters can be used to at
least reduce cross-talk between resonators.
[0199] The example implementation of FIG. 10 includes a DC bias for
DAC power line resonators (see FIGS. 9A and 9B above). In other
implementations, a DC bias can be included for address and trigger
line resonators (e.g., address and trigger line resonators
described in the present application). Each resonator of resonators
1002 is capacitively communicatively coupled to transmission line
1004 by a respective coupling capacitance 1006-1, 1006-2, and
1006-N (collectively referred to in the present application as
coupling capacitances 1006) and a respective coupling capacitance
1008-1, 1008-2, and 1008N (collectively referred to in the present
application as coupling capacitances 1008). While FIG. 10 shows
each resonator of resonators 1002 coupled to transmission line
1004, at least one resonator of resonators 1002 can be coupled to
another transmission line (not shown in FIG. 10).
[0200] Each resonator of resonators 1002 is communicatively coupled
by a respective pair of lines and at least one electronic filter to
a signal source 1010. The at least one electronic filter belongs to
an array of electronic filters 1012-1, 1012-2, 1012-3, and 1012-M
(collectively referred to in the present application as electronic
filters 1012). For example, resonator 1002-1 is communicatively
coupled by lines 1014-1a and 1014-1b and electronic filters 1012-1
and 1012-2. Resonator 1002-2 is communicatively coupled by lines
1014-2a and 1014-2b and electronic filters 1012-2 and 1012-3.
Resonator 1002-N is communicatively coupled by lines 1014-Na and
1014-Nb and electronic filter 1012-M.
[0201] Each filter of electronic filters 1012 can be a low-pass
filter, a notch filter, or a band-pass filter. It is generally
desirable that each filter of electronic filters 1012 at least
reduces the magnitude of components of a signal from signal source
1010 at one or more resonant frequency bands of resonators
1002.
[0202] FIG. 11 is a schematic diagram illustrating an example
implementation of a superconducting circuit 1100 that includes a
first broadband switch 1102a, according to the present disclosure.
In some implementations, a second broadband switch 1102b may be
employed together with first broadband switch 1102a.
[0203] First and second broadband switches 1102a and 1102b may be
implemented as broadband switch 1202 of FIG. 12 and may be used as
part of a superconducting circuit to address a device.
Superconducting circuit 1100 includes a resonator addressed DAC
1104.
[0204] In superconducting circuit 1100, resonator-addressed DAC
1104 includes a loop 1106 of material that is superconductive in a
range of temperatures, and a compound Josephson junction (CJJ)
1108. CJJ 1108 includes two parallel current paths each interrupted
by a Josephson junction, Josephson junctions 1110 and 1112,
respectively.
[0205] Superconducting circuit 1100 further includes a resonator
1114, a transmission line 1116, and interface 1118 operable to
provide a global flux bias by a global flux bias line 1118-1.
Resonator 1114 includes coupling capacitors 1120 and 1122, an
inductive interface 1124 to resonator-addressed DAC 1104, and an
optional shunting capacitor 1126. The term "inductive interface" is
also referred to in the present application as a coupling
inductance. Coupling inductance 1124 inductively communicatively
couples resonator 1114 and resonator-addressed DAC 1104.
[0206] Instead of capacitively communicatively coupling resonator
1114 to transmission line 1116 by coupling capacitor 1120,
resonator 1114 can be communicatively coupled to transmission line
1116 by an inductive coupling. For example, resonator 1114 can be
inductively communicatively coupled to transmission line 1116 by an
inductive coupling to a portion of the body of resonator 1114.
[0207] Superconducting circuit 1100 further includes a current bias
line 1128 operable to provide a current bias to resonator-addressed
DAC 1104.
[0208] FIG. 12 is a schematic diagram of an example implementation
of a transmission line layout 1200 according to the present
systems, methods and apparatus. Transmission line layout 1200 may
be used for dynamically isolating a device, such as a
superconducting processor. Transmission line 1200 comprises a
broadband switch 1202 with a number N of cascade elements 1204_1
through 1204_N (collectively 1204) electrically coupled in
series.
[0209] Each cascade element 1204 may be implemented as cascade
element 1300 of FIG. 13. It is understood by those skilled in the
art that transmission line layout 1200 may be of different
construction, and the description of FIG. 12 is specific to one
implementation. In particular, the number N of cascade elements in
broadband switch 1202 may be different from the number of DC-SQUIDs
1310a and 1310b.
[0210] Transmission line 1200 comprises transmission lines 1206,
1208 and 1210. Transmission line 1210 passes through each cascade
element 1204. A first end of transmission lines 1206, 1208 and 1210
(e.g., the right-hand sides in the plane of the drawing sheet of
FIG. 12) is electrically communicatively coupled to a device (e.g.,
a superconducting processor, not shown in FIG. 12), and a second
end of transmission lines 1206, 1208 and 1210 (e.g., the left-hand
sides) is electrically communicatively coupled to signal
electronics (e.g., readout lines, not shown in FIG. 12).
[0211] Transmission lines 1206, 1208 and 1210 may comprise vias
1212 and 1214 to connect to ground. Vias 1212 and 1214 can cause
transmission lines 1206, 1208 and 1210 to stay at approximately the
same electrical potential during an operation cycle of the
device.
[0212] Each cascade element 1204 in broadband switch 1202 is
electrically connected by lines 1216_1 through 1216_N (collectively
1216) to transmission line 1208 to ground.
[0213] Broadband switch 1202 comprises activation lines 1218 and
1220 and inductances 1218_a and 1220_a that are operable to cause
the state of each cascade element 1204 to change from a suppression
state to a passing state, and vice versa. Activation lines 1218 and
1220 are electrically coupled to cascade elements 1204_1 and
1204_N, respectively. In at least one implementation, activation
lines 1218 and 1220 are poor electrical conductors over the
frequency range used for transmitting electrical signal to the
device, and receiving electric signals from the device (e.g., 4
GHz-8 GHz), for example activation lines 1218 and 1220 can provide
.gtoreq.4 k.OMEGA. impedance at 4 GHz. In the passing phase,
broadband switch 1202 allows the transmission of signals, and, in
the suppression phase, broadband switch 1202 suppresses blackbody
radiation. In one implementation, activation lines 1218 and 1220
may be implemented as a low-frequency twisted pair. Line 1222 and
inductances 1222_a through 1222_n electrically couple successive
cascade elements 1204 (e.g., cascade element 1204_1 to cascade
element 1204_2) to provide high impedance to photons, thus at least
partially obstructing a pathway to the device.
[0214] When broadband switch 1202 is implemented with cascade
elements such as cascade elements 1300 of FIG. 13, activation line
1218 corresponds to activation line 1318 for cascade element
1204_1, and line 1222 to activation line 1320. Similarly, line 1222
corresponds to activation line 1318, and activation line 1220 to
activation line 1320 for cascade element 1204_N.
[0215] In at least one implementation, filtering elements may be
integrated into activation lines 1218 and 1220 to at least limit
the introduction of noise while allowing broadband switch 1202 to
operate at a desired operating speed. For example, passive
filtering elements or inductive chokes can be used. In addition,
filtering elements may be made of superconducting material or
elements, such as kinetic inductors. Examples of kinetic inductors
are discussed in detail in International Patent Publication No.
WO2017192733A2 "SYSTEMS AND METHODS FOR SUPERCONDUCTING DEVICES
USED IN SUPERCONDUCTING CIRCUITS AND SCALABLE COMPUTING", filed May
3, 2017.
[0216] In one implementation, broadband switch 1202 may be used as
part of a superconducting circuit comprising microwave paths, as
described above with reference to FIG. 11.
[0217] FIG. 13 is a schematic diagram of an example implementation
of a single cascade element 1300 according to the present systems,
methods and apparatus. Cascade element 1300 may be used as one of a
plurality of cascade of elements as part of a broadband switch for
dynamically isolating a device, such as a superconducting
processor. See, for example, FIG. 12 and its accompanying
description.
[0218] Cascade element 1300 comprises a transmission line 1302. A
first end of transmission line 1302 (e.g., the right-hand side in
the plane of the page of FIG. 13) is electrically connected to a
device (e.g., a superconducting processor, not shown in FIG. 13)
and a second end of transmission line 1302 (e.g., the left-hand
side in the plane of the page of FIG. 13) is electrically connected
to signal electronics (e.g., readout lines, not shown in FIG. 13).
Readout electronics may be in an exterior environment, at a
different temperature than the operating temperature of the device.
Readout electronics may be in an exterior environment, at a
different temperature than the operating temperature of the
device.
[0219] Cascade element 1300 comprises a first segment 1304 and a
second segment 1306, where first segment 1304 is on the left-hand
side of a matching capacitor 1308 in the plane of the drawing sheet
of FIG. 13, and second segment 1306 is on the right-hand side of
matching capacitor 1308 in the plane of the drawing sheet of FIG.
13. First segment 1304 comprises a number N of DC-SQUIDs 1310a_1
through 1310a_N (collectively 1310a) in series, and second segment
1306 comprises a number M of DC-SQUIDs 1310b_1 through 1310b_M
(collectively 1310b) in series. In at least one implementation, the
number of DC-SQUIDs 1310a is equal to the number of DC-SQUIDs
1310b. In some implementations, cascade element 1300 may comprise
RF-SQUIDs.
[0220] Each DC-SQUID 1310a and 1310b comprises a pair Josephson
junctions 1312a and 1312b (collectively 1312, only one pair called
out to reduce clutter). Each Josephson junction of the pair of
Josephson junctions 1312 has a respective critical current I.sub.c.
Each DC-SQUID 1310a and 1310b is inductively coupled by inductance
1314a_1 through 1314a_N (collectively 1314a, only one called out in
FIG. 13 to reduce clutter) and 1314b_1 through 1314b_M
(collectively 1314b, only one called out in FIG. 13 to reduce
clutter), respectively, to activation line loops 1316a_1 through
1316a_N (collectively 1316a) and 1316b_1 through 1316b_M
(collectively 1316b), respectively.
[0221] Loops 1316a are electrically coupled to activation line
1318, and loops 1316b are electrically coupled to activation line
1320. Activation lines 1318 and 1320 are operable to cause the
state of cascade element 1300 to change from a suppression state to
a passing state, and vice versa, when used as part of a broadband
switch for dynamic isolation of a device, such as a superconducting
processor.
[0222] Cascade element 1300 is symmetric with respect to matching
capacitor 1308. Inductance 1314a and 1314b are approximately the
same for DC-SQUIDs 1310a and 1310b, respectively, and junctions
1312 have approximately the same critical current I.sub.c for
DC_SQUIDs 1310a and 1310b. In some implementations, small
variations during building and assembly may lead to values of
inductance 1314a and 1314b and of critical current I.sub.c that are
not identical for each DC-SQUID of DC-SQUIDs 1310a and 1310b.
[0223] The various embodiments and implementations of the present
application describe addressing schemes that include the
following:
[0224] a low-frequency current bias in combination with a
low-frequency flux bias (also referred to in the present
application as YZ addressing and/or XYZ addressing);
[0225] a low-frequency current bias in combination with a
low-frequency flux bias and a high-frequency flux bias (also
referred to in the present application as YZ addressing and/or XYZ
addressing where Y and/or X can be frequency-domain
multiplexed);
[0226] a low-frequency current bias in combination with a
high-frequency current bias and a low-frequency flux bias (also
referred to in the present application as YZ addressing and/or XYZ
addressing where Z can be frequency-domain multiplexed); and
[0227] a low-frequency current bias in combination with a
high-frequency current bias, a low-frequency flux bias, and a
high-frequency flux bias (also referred to in the present
application as YZ and/or XYZ addressing where X, Y, and/or Z can be
frequency-domain multiplexed.
[0228] In each of the above addressing schemes, the high-frequency
bias (which can be a current bias across a CJJ loop and/or a flux
bias into a CJJ loop) can be provided by a respective
superconducting resonator. The superconducting resonator may enable
frequency-domain multiplexing.
[0229] In each of the above addressing schemes, asymmetry of
Josephson junctions in a CJJ of a DAC can eliminate, or at least
reduce the contribution of, a low-frequency current bias line
and/or a low-frequency flux bias line.
AC-driven DAC--DAC Rectifier
[0230] In some implementations of input/output (I/O) systems, flux
is stored in a DAC by using direct current (DC) and/or DC
pulses.
[0231] The systems and methods described in the present application
include a flux DAC driven by an alternating current (AC). A flux
DAC driven by an alternating current (AC) is also referred to in
the present application as an AC-driven flux DAC. Benefits of an
I/O system that uses an AC-driven flux DAC can include a)
frequency-domain multiplexing (FDM), and b) minimizing, or at least
reducing, drift noise by using higher frequencies and/or by
eliminating DC components.
[0232] In some implementations, an AC signal to an AC-driven flux
DAC (e.g., an AC signal on a PWR line) is periodic (e.g.,
sinusoidal), and a DC bias can be used to break the symmetry. In
some implementations, an asymmetry of Josephson junctions in the
CJJ of the DAC can be used to break the symmetry. Breaking the
symmetry can eliminate, or at least reduce the contribution of, a
DC bias in a DAC addressing scheme. Removing DC components can
advantageously reduce drift noise.
[0233] It can be beneficial to reduce the number of input/output
lines to a quantum processor. The use of FDM can reduce the number
of input/output lines to the quantum processor. In some
implementations, FDM may be particularly suitable for
higher-frequency (e.g. GHz lines, e.g. ADDR and TRIG lines.
[0234] In some implementations of an AC-driven flux DAC, an I/O
system applies a first AC signal to a PWR line. (See the section
above on XYZ-Addressing of Flux DACs for a description of
addressing lines.) The first AC signal may be at a frequency in the
MHz region of the electromagnetic spectrum. The I/O system may
drive an ADDR and/or TRIG line with a second AC signal. The second
AC signal may be at a frequency in the GHz region of the
electromagnetic spectrum. The second AC signal may be used to drive
the ADDR and/or TRIG line selectively on one half-cycle (positive
or negative half-cycle) of the first AC signal applied to the PWR
line.
[0235] The present systems and methods can include determining a
suitable frequency for the first AC signal. For example, a suitable
frequency can be determined at least in part by an analysis of
limits imposed by the I/O system. The limits are also referred to
in the present application as I/O frequency cut-offs. For example,
a suitable frequency can be determined at least in part by
performing a trade-off between an acceptable level of drift noise
and an upper bound on the rate at which flux quanta can be loaded
into a storage loop of the DAC.
[0236] During operation of the DAC, the second AC signal used to
drive the TRIG line can be synchronized with the first AC signal
applied to the PWR line so that the I/O system drives the TRIG line
with pulses selectively on one half-cycle (positive or negative
half-cycle) of the first AC signal for adding or removing flux
quanta to/from the DAC storage loop.
[0237] Storing flux in a superconducting loop by operation of an
AC-driven flux DAC can cause a DC current to circulate in the
superconducting loop.
[0238] In some implementations, an AC-driven flux DAC is included
in the fabric of a quantum processor (such as quantum processor 836
of FIG. 8--also referred to in the present application as a QPU).
In some implementations, an AC-driven flux DAC is an element of an
on-chip memory that is driven by AC signals, rather than DC
signals.
[0239] FIG. 14 is a schematic diagram of a superconducting DAC
1400, according to the present disclosure. Superconducting DAC 1400
can be an element in an I/O system. The I/O system can be an
element of a quantum computer. The I/O system can write data to a
quantum processor, and read data from a quantum processor.
[0240] DAC 1400 includes a superconducting loop 1402.
Superconducting loop 1402 can include or consist of a
superconducting metal, e.g., niobium, aluminum and the like.
Superconducting loop 1402 can be used to store flux. Flux can be
loaded into superconducting loop 1402 of DAC 1400 in multiples of
magnetic flux quanta.
[0241] Superconducting loop 1402 of DAC 1400 is interrupted by an
inductance 1404. DAC 1400 can be inductively communicatively
coupled to a device 1406 by inductance 1404 and a mutual inductance
with device 1406.
[0242] Superconducting loop 1402 of DAC 1400 is also interrupted by
a compound Josephson junction 1408. Compound Josephson junction
(CJJ) 1408 includes two parallel superconducting paths, each of the
two parallel superconducting paths interrupted by a respective
Josephson junction, 1410 and 1412.
[0243] A PWR line is superconductingly electrically communicatively
coupled to superconducting loop 1402 of DAC 1400 at nodes 1414 and
1416. Current enters from the PWR line at node 1414, and leaves
superconducting loop 1402 at node 1416.
[0244] CJJ 1408 interrupts superconducting loop 1402 between nodes
1418 and 1420. An inductance 1422 between node 1418 and Josephson
junction 1410 is inductively communicatively coupled to an ADDR
line 1424. An inductance 1426 between node 1418 and Josephson
junction 1412 is inductively communicatively coupled to a TRIG line
1428.
[0245] Superconductivity is a set of physical properties observed
in a material where electrical resistance of the material vanishes
and magnetic flux fields are expelled from the material. A material
exhibiting these properties is referred to in the present
application as a superconductor. A material exhibiting these
properties is also referred to in the present application as a
superconducting material. A superconductor typically has a
characteristic critical temperature below which its electrical
resistance drops to zero. An electric current in a loop of
superconducting material can persist indefinitely with no power
source.
[0246] The various embodiments described above can be combined to
provide further embodiments. To the extent that they are not
inconsistent with the specific teachings and definitions herein,
all of the U.S. patents, U.S. patent application publications, U.S.
patent applications, foreign patents, and foreign patent
applications referred to in this specification and/or listed in the
Application Data Sheet that are assigned to the assignee of this
patent application, including but not limited to the following: PCT
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FOR ADDRESSING DEVICES IN A SUPERCONDUCTING CIRCUIT, filed Aug. 19,
2019 are incorporated herein by reference, in their entireties.
Aspects of the embodiments can be modified, if necessary, to employ
systems, circuits and concepts of the various patents, applications
and publications to provide yet further embodiments.
[0247] These and other changes can be made to the embodiments in
light of the above-detailed description. In general, in the
following claims, the terms used should not be construed to limit
the claims to the specific embodiments disclosed in the
specification and the claims, but should be construed to include
all possible embodiments along with the full scope of equivalents
to which such claims are entitled. Accordingly, the claims are not
limited by the disclosure.
* * * * *
References