U.S. patent application number 16/579086 was filed with the patent office on 2021-01-07 for storage memory device.
This patent application is currently assigned to National Taiwan Normal University. The applicant listed for this patent is National Taiwan Normal University. Invention is credited to Chun-Hu CHENG.
Application Number | 20210005728 16/579086 |
Document ID | / |
Family ID | |
Filed Date | 2021-01-07 |
United States Patent
Application |
20210005728 |
Kind Code |
A1 |
CHENG; Chun-Hu |
January 7, 2021 |
STORAGE MEMORY DEVICE
Abstract
A storage memory device includes a field effect transistor
including a semiconductor substrate, a first insulating layer that
is disposed on the semiconductor substrate, a source and a drain
that are formed on the semiconductor substrate and spaced apart
from each other, a stacked structure, and a gate. The stacked
structure includes a charge trapping layer and a composite element
that has a ferroelectric layer and an antiferroelectric layer. The
ferroelectric layer is made of a doped hafnium oxide-based material
having a predominantly orthorhombic phase and exhibiting a negative
capacitance. The antiferroelectric layer is made of a zirconium
oxide-based material having a predominantly tetragonal phase.
Inventors: |
CHENG; Chun-Hu; (Taipei
City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
National Taiwan Normal University |
Taipei City |
|
TW |
|
|
Assignee: |
National Taiwan Normal
University
Taipei City
TW
|
Appl. No.: |
16/579086 |
Filed: |
September 23, 2019 |
Current U.S.
Class: |
1/1 |
International
Class: |
H01L 29/423 20060101
H01L029/423; H01L 27/11568 20060101 H01L027/11568; H01L 29/51
20060101 H01L029/51; H01L 29/78 20060101 H01L029/78; G11C 16/14
20060101 G11C016/14; G11C 16/10 20060101 G11C016/10; G11C 16/26
20060101 G11C016/26; H01L 29/792 20060101 H01L029/792; G11C 16/04
20060101 G11C016/04 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 2, 2019 |
TW |
108123213 |
Jul 2, 2019 |
TW |
108123214 |
Claims
1. A storage memory device, comprising a field effect transistor
including: a semiconductor substrate; a first insulating layer
disposed on said semiconductor substrate; a source and a drain
formed on said semiconductor substrate and spaced apart from each
other; a stacked structure disposed on said first insulating layer
opposite to said semiconductor substrate and including a charge
trapping layer and a composite element that has a ferroelectric
layer and an antiferroelectric layer, said ferroelectric layer
being made of a doped hafnium oxide-based material that has a
predominantly orthorhombic phase and that exhibits a negative
capacitance, said antiferroelectric layer being made of a zirconium
oxide-based material having a predominantly tetragonal phase; and a
gate disposed on said stacked structure opposite to said first
insulating layer.
2. The storage memory device of claim 1, wherein said charge
trapping layer is made of a material selected from the group
consisting of silicon nitride, silicon carbide, a high dielectric
constant oxide having a non-orthorhombic phase, and combinations
thereof.
3. The storage memory device of claim 2, wherein said high
dielectric constant oxide is selected from the group consisting of
zirconium oxide, hafnium oxide, aluminum oxide, titanium oxide,
tantalum oxide, zirconium oxynitride, hafnium oxynitride, silicon
oxynitride, aluminum oxynitride, titanium oxynitride, tantalum
oxynitride, hafnium silicon oxide, zirconium silicon oxide, and
combinations thereof.
4. The storage memory device of claim 1, wherein said doped hafnium
oxide-based material is selected from the group consisting of
aluminum (Al)-doped hafnium oxide, silicon (Si)-doped hafnium
oxide, strontium (Sr)-doped hafnium oxide, zirconium (Zr)-doped
hafnium oxide, lanthanum (La)-doped hafnium oxide, yttrium
(Y)-doped hafnium oxide, gadolinium (Gd)-doped hafnium oxide, and
combinations thereof.
5. The storage memory device of claim 4, wherein: when said doped
hafnium oxide-based material is Al-doped hafnium oxide, Al is
present in an amount ranging from 2 mol % to 10 mol % based on a
total molar amount of said Al-doped hafnium oxide; when said doped
hafnium oxide-based material is Si-doped hafnium oxide, Si is
present in an amount ranging from 2 mol % to 10 mol % based on a
total molar amount of said Si-doped hafnium oxide; when said doped
hafnium oxide-based material is Sr-doped hafnium oxide, Sr is
present in an amount ranging from 2 mol % to 15 mol % based on a
total molar amount of said Sr-doped hafnium oxide; when said doped
hafnium oxide-based material is Zr-doped hafnium oxide, Zr is
present in an amount ranging from 1 mol % to 50 mol % based on a
total molar amount of said Zr-doped hafnium oxide; when said doped
hafnium oxide-based material is La-doped hafnium oxide, La is
present in an amount ranging from 2 mol % to 15 mol % based on a
total molar amount of said La-doped hafnium oxide; when said doped
hafnium oxide-based material is Y-doped hafnium oxide, Y is present
in an amount ranging from 2 mol % to 15 mol % based on a total
molar amount of said Y-doped hafnium oxide; and when said doped
hafnium oxide-based material is Gd-doped hafnium oxide, Gd is
present in an amount ranging from 2 mol % to 15 mol % based on a
total molar amount of said Gd-doped hafnium oxide.
6. The storage memory device of claim 1, wherein said zirconium
oxide-based material includes one of undoped zirconium oxide, doped
zirconium oxide and the combination thereof.
7. The storage memory device of claim 6, wherein said zirconium
oxide-based material includes at least one of doped zirconium oxide
that is zirconium oxide doped with a dopant, said dopant being
selected from the group consisting of silicon, aluminum, germanium,
yttrium, hafnium and nitrogen, and being present in an amount
greater than 0 mol % and not greater than 50 mol % based on a total
molar amount of said doped zirconium oxide.
8. The storage memory device of claim 1, wherein each of said
ferroelectric layer, said antiferroelectric layer and said charge
trapping layer has a thickness ranging from 1 nm to 30 nm.
9. The storage memory device of claim 1, wherein said field effect
transistor further includes a second insulating layer disposed
between said stacked structure and said gate.
10. The storage memory device of claim 9, wherein said second
insulating layer is made of a dielectric insulating material having
a non-orthorhombic phase.
11. The storage memory device of claim 1, wherein said stacked
structure further includes a third insulating layer disposed
between said charge trapping layer and said composite element.
12. The storage memory device of claim 11, wherein said third
insulating layer is made of a dielectric insulating material having
a non-orthorhombic phase.
13. The storage memory device of claim 1, wherein said field effect
transistor is a fin field effect transistor.
14. The storage memory device of claim 13, wherein said fin field
effect transistor includes a fin structure that is disposed on said
semiconductor substrate and that contains said source, said drain
and a connecting section between said source and said drain, said
stacked structure being disposed on said connecting section and
covering a portion of said first insulating layer.
15. The storage memory device of claim 14, wherein said fin
structure extending upwardly from said semiconductor substrate,
said first insulating layer covering at least a portion of said
semiconductor substrate and a portion of a peripheral surface of
said fin structure.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims priority of Taiwanese Invention
Patent Application Nos. 108123213 and 108123214, filed on Jul. 2,
2019.
FIELD
[0002] The disclosure relates to a memory device, and more
particularly to a storage memory device.
BACKGROUND
[0003] A conventional non-volatile memory device includes a
substrate, an insulating layer formed on a portion of the
substrate, a source and a drain formed on opposite sides of the
insulating layer, a charge trapping layer formed on the insulating
layer, an insulating barrier formed on the charge trapping layer,
and a gate formed on the insulating barrier. To effectively reduce
the operating voltage of the memory device, a high dielectric
constant (high-k) oxide, such as silicon oxide, hafnium oxide and
aluminum oxide, is commonly used as the insulating barrier.
However, the memory device including the high-k oxide would have
higher off-state current and higher subthreshold swing, which is
generally 70 mV/dec, as well as slower reading/erasing speed (about
100 .mu.s to 1 ms).
[0004] U.S. Invention Patent Application Publication No. 2018182769
A1 discloses a flash memory that includes a stacked structure,
which has a ferroelectric layer exhibiting a negative capacitance
and a charge trapping layer. With such stacked structure, the flash
memory has improved properties such as reduced leakage current,
faster operating speed, lower subthreshold swing, and increased
reading and writing speed.
[0005] Despite the rapid development of memory device, there is
still a need for further improvement of the operating speed and the
operating endurance of the memory device.
SUMMARY
[0006] Therefore, an object of the disclosure is to provide a
storage memory device having greater operating endurance and faster
operating speed.
[0007] The storage memory device includes a field effect transistor
including a semiconductor substrate, a first insulating layer, a
source, a drain, a stacked structure, and a gate. The first
insulating layer is disposed on the semiconductor substrate. The
source and the drain are formed on the semiconductor substrate and
are spaced apart from each other. The stacked structure is disposed
on the first insulating layer opposite to the semiconductor
substrate, and includes a charge trapping layer and a composite
element that has a ferroelectric layer and an antiferroelectric
layer. The ferroelectric layer is made of a doped hafnium
oxide-based material that has a predominantly orthorhombic phase
and that exhibits a negative capacitance. The antiferroelectric
layer is made of a zirconium oxide-based material having a
predominantly tetragonal phase. The gate is disposed on the stacked
structure opposite to the first insulating layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Other features and advantages of the disclosure will become
apparent in the following detailed description of the embodiments
with reference to the accompanying drawings, of which:
[0009] FIG. 1 is a schematic view illustrating a field effect
transistor of a first embodiment of a storage memory device
according to the disclosure;
[0010] FIG. 2 is a schematic view illustrating a variation of the
field effect transistor of the embodiment;
[0011] FIG. 3 is a graph showing simulated transfer characteristics
of two different structures of the field effect transistors;
[0012] FIG. 4 is a graph showing a pulse sequence during
programming, reading and erasing operations of the embodiment;
[0013] FIG. 5 is a graph showing the operating endurance of the
embodiment; and
[0014] FIG. 6 is a schematic perspective view illustrating a second
embodiment of the field effect transistor of the storage memory
device according to the disclosure.
DETAILED DESCRIPTION
[0015] Before the disclosure is described in greater detail, it
should be noted that where considered appropriate, reference
numerals or terminal portions of reference numerals have been
repeated among the figures to indicate corresponding or analogous
elements, which may optionally have similar characteristics.
[0016] A first embodiment of the storage memory device 2 according
to the disclosure includes a plurality of storage cells. Each of
the storage cells includes a planar field effect transistor 200
(1T) (see FIG. 1) and at least one capacitor (1C) (not shown). FIG.
1 only illustrates the planar field effect transistor 200 of one of
the storage cells of the storage memory device 2.
[0017] Referring to FIG. 1, the field effect transistor 200
includes a semiconductor substrate 21, a source 22, a drain 23, a
first insulating layer 24, a stacked structure 25 and a gate
26.
[0018] The first insulating layer 24 is disposed on the
semiconductor substrate 21. The source 22 and the drain 23 are
formed on the semiconductor substrate 21 and spaced apart from each
other. In one aspect, the source 22 and the drain 23 are positioned
on opposite sides of the insulating layer 24. The stacked structure
25 is disposed on the insulating layer 24 opposite to the
semiconductor substrate 21, and the gate 26 is disposed on the
stacked structure 25 opposite to the first insulating layer 24.
[0019] Specifically, the semiconductor substrate 21 may be made of
monocrystalline silicon, polycrystalline silicon, germanium or
other suitable semiconductor materials. The first insulating layer
24 may be a monolayer or multilayers of insulating material stacked
together. Examples of the insulating material may include silicon
oxide, aluminum oxide, etc.
[0020] The stacked structure 25 includes a charge trapping layer
251 and a composite element 252. The charge trapping layer 251 is
made of a conductor, a semiconductor or an insulating material
having a high dielectric constant. The insulating material may be
selected from the group consisting of silicon nitride (SiN.sub.x),
silicon carbide (SiC), a high dielectric constant (high-k) oxide
having a non-orthorhombic phase (predominant crystalline phases of
the high-k oxide are generally monoclinic or tetragonal phases),
and combinations thereof. The high-k oxide is selected from the
group consisting of zirconium oxide (ZrO.sub.2), hafnium oxide
(HfO.sub.2), aluminum oxide (Al.sub.2O.sub.3), titanium oxide
(TiO.sub.2), tantalum oxide (TaO), zirconium oxynitride (ZrON),
hafnium oxynitride (HfON), silicon oxynitride (SiON), aluminum
oxynitride (AlON), titanium oxynitride (TiON), tantalum oxynitride
(TaON), hafnium silicon oxide (HfSiO), zirconium silicon oxide
(ZrSiO), and combinations thereof.
[0021] The composite element 252 has a ferroelectric layer 2521 and
an antiferroelectric layer 2522. The ferroelectric layer 2521 is
made of a doped hafnium oxide-based material that has a
predominantly orthorhombic phase and that exhibits a negative
capacitance. It is noted that a negative capacitance is observed in
the doped hafnium oxide-based material having a predominantly
orthorhombic phase. Examples of the doped hafnium oxide-based
material may include, but are not limited to, aluminum (Al)-doped
hafnium oxide (HfAlO.sub.x), silicon (Si)-doped hafnium oxide
(HfSiO.sub.x), strontium (Sr)-doped hafnium oxide (HfSrO.sub.x),
zirconium (Zr)-doped hafnium oxide (HfZrO.sub.x), lanthanum
(La)-doped hafnium oxide (HfLaO.sub.x), yttrium (Y)-doped hafnium
oxide (HfYO.sub.x), gadolinium (Gd)-doped hafnium oxide
(HfGdO.sub.x), and combinations thereof.
[0022] When the doped hafnium oxide-based material is Al-doped
hafnium oxide, Al is present in an amount ranging from 2 mol % to
10 mol % based on a total molar amount of the Al-doped hafnium
oxide. When the doped hafnium oxide-based material is Si-doped
hafnium oxide, Si is present in an amount ranging from 2 mol % to
10 mol % based on a total molar amount of the Si-doped hafnium
oxide. When the doped hafnium oxide-based material is Sr-doped
hafnium oxide, Sr is present in an amount ranging from 2 mol % to
15 mol % based on a total molar amount of the Sr-doped hafnium
oxide. When the doped hafnium oxide-based material is Zr-doped
hafnium oxide, Zr is present in an amount ranging from 1 mol % to
50 mol % based on a total molar amount of the Zr-doped hafnium
oxide. When the doped hafnium oxide-based material is La-doped
hafnium oxide, La is present in an amount ranging from 2 mol % to
15 mol % based on a total molar amount of the La-doped hafnium
oxide. When the doped hafnium oxide-based material is Y-doped
hafnium oxide, Y is present in an amount ranging from 2 mol % to 15
mol % based on a total molar amount of the Y-doped hafnium oxide.
When the doped hafnium oxide-based material is Gd-doped hafnium
oxide, Gd is present in an amount ranging from 2 mol % to 15 mol %
based on a total molar amount of the Gd-doped hafnium oxide.
[0023] The antiferroelectric layer 2522 is made of a zirconium
oxide-based material having a predominantly tetragonal phase. The
zirconium oxide-based material may include undoped zirconium oxide
(ZrO.sub.2), doped zirconium oxide or the combination thereof. The
doped zirconium oxide may be doped with a dopant that is selected
from the group consisting of silicon (i.e., the doped zirconium
oxide being ZrSiO.sub.x), aluminum (i.e., the doped zirconium oxide
being ZrAlO.sub.x), germanium (i.e., the doped zirconium oxide
being ZrGeO.sub.x), yttrium (i.e., the doped zirconium oxide being
ZrYO.sub.x), hafnium (i.e., the doped zirconium oxide being
ZrHfO.sub.x), and nitrogen (i.e., the doped zirconium oxide being
ZrNO.sub.x). The dopant may be present in an amount greater than 0
mol % and not greater than 50 mol % based on a total molar amount
of the doped zirconium oxide. It is worth mentioning that the
zirconium oxide-based material may include a combination of more
than one of the doped zirconium oxides as mentioned above. For
example, the zirconium oxide-based material may include ZrSiO.sub.x
and ZrAlO.sub.x.
[0024] It is noted that the doping concentration of the
aforementioned doped hafnium oxide-based material and doped
zirconium oxide may be adjusted according to the dopant properties
and the crystalline phases of the ferroelectric and
antiferroelectric layers to be formed.
[0025] In this embodiment, the charge trapping layer 251 is formed
on the first insulating layer 24, and the composite element 252 is
formed on the charge trapping layer 251. In one aspect, the
composite element 252 may be formed on the first insulating layer
24, and the charge trapping layer 251 is formed on the composite
element 252.
[0026] In addition, in this embodiment, the ferroelectric layer
2521 is formed on the charge trapping layer 251, and the
antiferroelectric layer 2522 is formed on the ferroelectric layer
2521. In other aspects, the antiferroelectric layer 2522 is formed
on the charge trapping layer 251, and the ferroelectric layer 2521
is formed on the antiferroelectric layer 2522. The order of forming
the ferroelectric layer 2521 and the antiferroelectric layer 2522
would not influence the object of this disclosure, and may be
changed according to practical requirements. That is, the charge
trapping layer 251, the antiferroelectric layer 2522 and the
ferroelectric layer 2521 may be formed on the first insulating
layer 24 in such order, or in the order of antiferroelectric layer
2522, ferroelectric layer 2521, charge trapping layer 251.
[0027] In this embodiment, each of the ferroelectric layer 2521,
the antiferroelectric layer 2522 and the charge trapping layer 251
has a thickness ranging from 1 nm to 30 nm. In one aspect, to
maintain better ferroelectricity, the ferroelectric layer 2521 may
have a thickness ranging from 3 nm to 20 nm.
[0028] The gate 26 may be a monolayer or multilayer structure and
is made of a metal or semiconductor material. In some aspects, the
metal material may be metal nitride or metal carbide having
stress-induced strain effect, such that the doped hafnium
oxide-based material of the ferroelectric layer 2521 having
predominantly orthorhombic phase may be formed from a doped hafnium
oxide-based material having a predominantly monoclinic phase
through strain by the gate metal. Examples of the metal nitride or
metal carbide may include, but are not limited to, tantalum nitride
(TaN), tungsten nitride (WN), titanium nitride (TiN), tantalum
carbide (TaC), titanium aluminum carbide (TiAlC), titanium carbide
(TiC), and tantalum aluminum carbide (TaAlC).
[0029] Referring to FIG. 2, in a variation of the first embodiment,
the field effect transistor 200 further includes a second
insulating layer 27 disposed between the stacked structure 25 and
the gate 26, and a third insulating layer 253 disposed between the
charge trapping layer 251 and the composite element 252. Both of
the second insulating layer 27 and the third insulating layer 253
are made of a dielectric insulating material having a
non-orthorhombic phase and a high dielectric constant. It is noted
that the second insulating layer 27 and the third insulating layer
253 are optionally positioned individually or simultaneously
according to characteristics and requirements of the storage memory
devices 2.
[0030] Referring to FIG. 3, the graph shows simulated transfer
characteristics of two different structures of field effect
transistors, one of which is the field effect transistor 200 of
FIG. 1 having the antiferroelectric layer 2522, the ferroelectric
layer 2521 and the charge trapping layer 251 (shown as AFE/FE/CT in
FIG. 3), and the other is a field effect transistor containing a
ferroelectric layer and a charge trapping layer without an
antiferroelectric layer (shown as FE/CT in FIG. 3). In these two
types of field effect transistors, the semiconductor substrate is
made of silicon, the ferroelectric layer is made of HfZrO.sub.x
with Zr being present in an amount of 40 mol % and has a thickness
of 10 nm, and the charge trapping layer is made of HfON and has a
thickness of 6 nm. For the AFE/FE/CT storage memory device, the
antiferroelectric layer is made of ZrO.sub.2 and has a thickness of
10 nm.
[0031] In simulation, drain voltages (V.sub.D) applied to the two
types of field effect transistors are both 0.2 V. As shown in FIG.
3, the minimum subthreshold swing (SS.sub.min) of the AFE/FE/CT
storage memory device is 56 mV/dec, which is smaller than that
(i.e., 69 mV/dec) of the FE/CT storage memory device. This
indicates that the AFE/FE/CT storage memory device has better
control of the gate 26 of the field effect transistor 200.
[0032] Referring to FIG. 4, which shows a pulse sequence during
programming, reading and erasing operations of the embodiment,
higher operating speed (<100 ns) may be obtained in the
AFE/FE/CT storage memory device according to the disclosure
compared to the FE/CT storage memory device, which has an operating
speed around 800 ns. Moreover, referring to FIG. 5, which shows the
operating endurance of the embodiment, the simulation result shows
that when programming and erasing voltages of .+-.10 V is applied
for 100 ns, the AFE/FE/CT storage memory device according to the
disclosure is capable of withstanding at least 10.sup.8 program and
erase cycles (P/E cycles), which means the AFE/FE/CT storage memory
device according to the disclosure has better operating endurance
and reliability than that of the conventional flash memory
devices.
[0033] In addition, a second embodiment of the storage memory
device 2' according to the disclosure includes a plurality of
storage cells. Each of the storage cells includes a fin field
effect transistor 300 (1T) (see FIG. 6) and at least one capacitor
(1C) (not shown). FIG. 6 only illustrates the fin field effect
transistor 300 of one of storage cells of the storage memory device
2'.
[0034] Similar to the field effect transistor 200 of FIG. 1, the
fin field effect transistor 300 includes the semiconductor
substrate 21, the source 22, the drain 23, the first insulating
layer 24, the stacked structure 25 and the gate 26. The materials
used for forming the above elements are the same as those used in
the field effect transistor 200 and thus, are not illustrated
herein for the sake of brevity. The differences between the fin
field effect transistor 300 and the field effect transistor 200 are
illustrated in the following.
[0035] The fin field effect transistor 300 further includes a fin
structure 20 that is disposed on the semiconductor substrate 21 and
that contains the source 22, the drain 23 and a connecting section
201 that is disposed between the source 22 and the drain 23. The
stacked structure 25 is disposed on the connecting section 201 and
covers a portion of the first insulating layer 24. The fin
structure 20 extends upwardly from the semiconductor substrate 21,
and the first insulating layer 24 covers a portion of the
semiconductor substrate 21 and a portion of a peripheral surface of
the fin structure 20. Similar to the first embodiment of the
storage memory device 2 having the stacked structure 25 that
includes the ferroelectric layer 2521 and the antiferroelectric
layer 2522, power consumption during switching and the off-state
current of the field effect transistor 300 are reduced, thereby
enhancing the operating endurance of the storage memory device
2'.
[0036] In conclusion, the negative capacitance observed in the
ferroelectric layer 2521 leads to smaller subthreshold swing of the
storage memory devices 2, 2', thus reduces the power consumption
during switching and off-state current of the field effect
transistors 200, 300. In addition, since the antiferroelectric
layer 2522 has a larger coercive field, the saturated polarization
of the ferroelectric layer 2521 during erasing operation under high
electric fields can be maximized. Further, reduction of the
electric field across the ferroelectric layer 2521 and the charge
trapping layer 251 minimizes the occurrence of failure and leakage
current during repeated reading and programming operations.
Therefore, the storage memory devices 2, 2' according to this
disclosure have superior operating endurance and reliability.
[0037] In the description above, for the purposes of explanation,
numerous specific details have been set forth in order to provide a
thorough understanding of the embodiments. It will be apparent,
however, to one skilled in the art, that one or more other
embodiments may be practiced without some of these specific
details. It should also be appreciated that reference throughout
this specification to "one embodiment," "an embodiment," an
embodiment with an indication of an ordinal number and so forth
means that a particular feature, structure, or characteristic may
be included in the practice of the disclosure. It should be further
appreciated that in the description, various features are sometimes
grouped together in a single embodiment, figure, or description
thereof for the purpose of streamlining the disclosure and aiding
in the understanding of various inventive aspects, and that one or
more features or specific details from one embodiment may be
practiced together with one or more features or specific details
from another embodiment, where appropriate, in the practice of the
disclosure.
[0038] While the disclosure has been described in connection with
what are considered the exemplary embodiments, it is understood
that this disclosure is not limited to the disclosed embodiments
but is intended to cover various arrangements included within the
spirit and scope of the broadest interpretation so as to encompass
all such modifications and equivalent arrangements.
* * * * *