U.S. patent application number 16/388092 was filed with the patent office on 2020-10-22 for phase-change random access memory (pram) write disturb mitigation.
The applicant listed for this patent is SAMSUNG ELECTRONICS CO., LTD.. Invention is credited to AMIT BERMAN.
Application Number | 20200335164 16/388092 |
Document ID | / |
Family ID | 1000004004689 |
Filed Date | 2020-10-22 |
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United States Patent
Application |
20200335164 |
Kind Code |
A1 |
BERMAN; AMIT |
October 22, 2020 |
PHASE-CHANGE RANDOM ACCESS MEMORY (PRAM) WRITE DISTURB
MITIGATION
Abstract
A method for writing memory cells including: applying a program
voltage to a target wordline; grounding bitlines of memory cells to
be written to a first resistance state; setting a bitline voltage
of unselected bitlines; and setting a wordline voltage of
unselected wordlines; applying the program voltage to a target
bitline; grounding wordlines of the memory cells to be written to a
second resistance state; setting the wordline voltage of the
unselected wordlines to a first value if a peak of a maximum
voltage drop is greater than or equal to a second value; otherwise,
setting the wordline voltage to zero; and setting the bitline
voltage of the unselected bitlines to a third value if the peak of
the maximum voltage drop is greater than or equal to the second
value; otherwise, setting the bitline voltage to zero.
Inventors: |
BERMAN; AMIT; (Ramat Gan,
IL) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SAMSUNG ELECTRONICS CO., LTD. |
Suwon-si |
|
KR |
|
|
Family ID: |
1000004004689 |
Appl. No.: |
16/388092 |
Filed: |
April 18, 2019 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G11C 13/0069 20130101;
G11C 13/0004 20130101; G11C 2013/0092 20130101 |
International
Class: |
G11C 13/00 20060101
G11C013/00 |
Claims
1. A method for writing memory cells in a nonvolatile memory device
comprising wordlines overlapping bitlines, the method comprising:
in a first phase: applying a program pulse voltage to a target
wordline; grounding bitlines of memory cells to be written to a
first resistance state; setting a bitline voltage of unselected
bitlines; and setting a wordline voltage of unselected wordlines;
in a second phase: applying the program pulse voltage to a target
bitline; grounding wordlines of the memory cells to be written to a
second resistance state; setting the wordline voltage of the
unselected wordlines to a first value if a peak of a maximum
voltage drop over memory cells which were not meant, to be changed
is greater than or equal to a second value, and setting the
wordline voltage to zero if the peak of the maximum voltage drop is
not greater than or equal to the second value; and setting the
bitline voltage of the unselected bit lines to a third value if the
peak of the maximum voltage drop is greater than or equal to the
second value, and setting the bitline voltage to zero if the pedk
of the maximum voltage drop is not greater than or equal to the
second value.
2. The method of claim 1, wherein the first phase is a set phase
and the second phase is a reset phase.
3. The method of claim 1, wherein the nonvolatile memory device is
phase-change random access memory.
4. The method of claim l wherein the first resistance state is a
low resistance state the second resistance state is a high
resistance state.
5. The method of claim 1, wherein the wordlines and the bitlines
form an M.times.N array, wherein M and N are each integers greater
than one, and wherein the bitline voltage of the unselected
bitlines is represented by V BL = 2 M + 1 V PP , ##EQU00022## where
V.sub.BL is the bitline voltage of the unselected bitlines and
V.sub.PP is the program, pulse voltage.
6. The method of claim 1, wherein the wordlines and the bitlines
form an M.times.N array, wherein M and N are each integers greater
than one, and wherein the wordline voltage of the unselected
wordlines is represented by V WL = 1 M + 1 V PP , ##EQU00023##
where V.sub.WL is the wordline voltage of the unselected wordlines
and V.sub.PP is the program pulse voltage.
7. The method of claim 1, wherein the first value is
(0.9965-09934.alpha.) multiplied by the program pulse voltage,
wherein .alpha. is a value between zero and one.
8. The method of claim 7, wherein the third value is
(0.4982-0.4967.alpha.) multiplied by the program pulse voltage,
wherein .alpha. is a value between zero and one.
9. The method of claim 8, wherein the second value is the program
pulse voltage divided by 3.
10. A method for writing memory cells in a nonvolatile memory
device comprising wordlines overlapping bitlines, the method
comprising: in a first phase: applying a program pulse voltage to a
target wordline; grounding bitlines of memory cells to be written
to a first resistance state; grounding unselected bitlines and
unselected wordlines; in a second phase: applying the program pulse
voltage to a target bitline; grounding wordlines of the memory
cells to be written to a second resistance state; setting a
wordline voltage of the unselected wordlines; and setting a bitline
voltage of unselected bitlines.
11. The method of claim 10, wherein the fist phase is a set phase
and the second phase is a reset phase.
12. The method of claim 10, wherein the nonvolatile memory device
is phase-change random access memory.
13. The method of claim 10, wherein the first resistance state is a
low resistance state the second resistance state is a high resista
ice state.
14. The method of claim 10, wherein the wordline voltage is
represented by V WL = 2 V PP 3 , ##EQU00024## where V.sub.WL is the
wordline voltage of the unselected wordlines in the second phase
and V.sub.PP is the program pulse voltage.
15. The method of claim 10, wherein the bitline voltage is
represented by V BL = V PP 3 , ##EQU00025## where V.sub.BL is the
bitline voltage of the unselected bit lines in the second phase and
V.sub.PP is the program pulse voltage.
16. A method for witing memory cells in a nonvolatile memory device
comprising wordlines overlapping bitlines, the method comprising:
applying a program pulse voltage to a target wordline; grounding
bitlines of memory cells to be written to a first resistance state;
setting a bitline voltage of unselected bitlines; setting a
wordline voltage of unselected wordlines; applying the program
pulse voltage to a target bitline; grounding wordlines of the
memory cells to be written to a second resistance state; and
setting the wordline voltage of the unselected wordlines to a first
value if a peak maximumvoltage drop of memory cells which were not
meant to be changed is greater than or equal to a second value.
17. The method of claim 16, further comprising setting the wordline
voltage to zero if the peak maximum voltage drop is not greater
than or equal to the second value.
18. The method of claim 16, further composing: setting the bitline
voltage of the unselected bitlines to a third value if the peak
maximum voltage drop is greater than or equal to the second
value.
19. The method of claim 17, further comprising setting the bitline
voltage to zero if the peak maximum voltage drop is not greater
than or equal to the second value.
20. The method of claim 16, wherein the nonvolatile memory device
is phase-change random access memory.
Description
TECHNICAL FIELD
[0001] Exemplary embodiments of the present inventive concept
relate to write methods of nonvolatile memory devices, and more
particularly, to a nonvolatile memory device write method with
reduced write disturbs.
DISCUSSION OF RELATED ART
[0002] Phase-change random access memory (PRAM) has improved
scaling potential compared to traditional memory technologies. In
order to obtain small feature size and enable capacity through
vertical stacks, proper vertical three-dimensional architecture is
required. Cross-point structures, where separate wordline and
bitline wire bars (or planes as in V-PRAM) are connected with
variable-resistance materials, are able to exploit PRAM's inherent
characteristics and take advantage of process vertical buildup
while tolerating high temperatures. However, the cross-point
construction raises reliability and power consumption
challenges.
[0003] Write disturb phenomenon occurs in cross-point formation
when applying a write voltage for target cells. Since all cells in
a row share the same wordline, the potential is applied to every
cell. In a SET operation (e.g., setting low-resistance by positive
top-to-bottom electrodes) cells that are meant to be changed have a
ground connection in their associated bitline. Cells that have to
retain their resistance shell have a bitline voltage that minimizes
their voltage drop which causes disturb. If the bitlines in those
cells are set to write voltage, their voltage drop and disturb
reduces to zero. However, corresponding cells that are located in
the same bitline and unselected wordlines now have write potential
in their bottom electrode, requiring their wordline voltage to be
the same which leads to setting low-resistance in unselected
cells.
[0004] Conventional write schemes tackle write voltage disturbs by
V/2 or V/3 settings. In V/2, the unselected wordlines and bitlines
are biased with half of a write voltage. FIG. 1A demonstrates such
a configuration with a 5.times.3 array matrix. Wordline (WL) rows
are placed above the bitlines (BL) and each intersection connects
WL to BL within a PRAM device. The centered cell is meant to be
written and is marked with a full circle. The unfilled circles are
cells that are affected by write disturb. Cells that share a
bitline with written cells and cells on the same wordline that are
not meant to be written have voltage drop disturb at V/2 magnitude.
Due to limited SET/RESET endurance cycles, and since efficient
error-correction schemes exist for a binary symmetric channel, it
can be assumed that data would be scrambled to binary IID
Bernoulli-1/2 probability for each bit. In this case, nearly half
of each wordline contains high-resistance cells and therefore about
half of an array matrix would suffer from right disturb. In V/3,
unselected wordlines are biased with V/3 and =selected bitlines
with 2V/3, as shown in FIG. 1B. This approach is to reduce the
voltage's disturb magnitude to |V/3| but nearly all array cells are
affected, both in a single bit flip and random wordline data
distribution (unwanted cells in the same row as a written cell are
biased with .+-.V/3, other cells in different wordlines are
affected by V/3).
SUMMARY
[0005] According to an exemplary embodiment of the present
inventive concept, there is provided a method for writing memory
cells in a nonvolatile memory device comprising wordlines
overlapping bitlines, the method comprising: in a first phase:
applying a program pulse voltage to a target wordline; grounding
bitlines of memory cells to be written to a first resistance state;
setting a bitline voltage of unselected bitlines; and setting a
wordline voltage of unselected wordlines; in a second phase:
applying the program pulse voltage to a target bitline; grounding
wordlines of the memory cells to be written to a second resistance
state; setting the wordline voltage of the unselected wordlines to
a first value if a peak of a maximum voltage drop over memory cells
which were not meant to be changed is greater than or equal to a
second value, and setting the wordline voltage to zero if the peak
of the maximum voltage drop is not greater than or equal to the
second value; and setting the bitline voltage of the unselected
bitlines to a third value if the peak of the maximum voltage drop
is greater than or equal to the second value, and setting the
bitline voltage to zero if the peak of the maximum voltage drop is
not greater than or equal to the second value.
[0006] The first phase is a set phase and the second phase is a
reset phase.
[0007] The nonvolatile memory device is phase-change random access
memory.
[0008] The first resistance state is a low resistance state the
second resistance state is a high resistance state.
[0009] The wordlines and the bitlines form an M.times.N array,
wherein M and N are each integers greater than one, and wherein the
bitline voltage of the unselected bitlines is represented by
V BL = 2 M + 1 V PP , ##EQU00001##
[0010] where V.sub.BL is the bitline voltage of the unselected
bitlines and V.sub.PP is the program pulse voltage.
[0011] The wordlines and the bitlines form an M.times.N array,
wherein M and N are each integers greater than one, and wherein the
wordline voltage of the unselected wordlines is represented by
V WL = 1 M + 1 V PP , ##EQU00002##
[0012] where V.sub.WL is the wordline voltage of the unselected
bitlines and V.sub.PP is the program pulse voltage.
[0013] The first value is (0.9965-0.9934 .alpha.) multiplied by the
program pulse voltage, wherein .alpha. is a value between zero and
one.
[0014] The third value is (0.4982-0.4967 .alpha.) multiplied by the
program pulse voltage, wherein .alpha. is a value between zero and
one.
[0015] The second value is the program pulse voltage divided by
3.
[0016] According to an exemplary embodiment of the present
inventive concept, there is provided a method for writing memory
cells in a nonvolatile memory device comprising wordlines
overlapping bitlines, the method comprising: in a first phase:
applying a program pulse voltage to a target wordline; grounding
bitlines of memory cells to be written to a first resistance state;
grounding unselected bitlines and wordlines; in a second phase:
applying the program pulse voltage to a target bitline; grounding
wordlines of the memory cells to be written to a second resistance
state; setting a wordline voltage of the unselected wordlines; and
setting a bitline voltage of the unselected bitlines.
[0017] The first phase is a set phase and the second phase is a
reset phase.
[0018] The nonvolatile memory device is phase-change random access
memory.
[0019] The first resistance state is a low resistance state the
second resistance state is a high resistance state.
[0020] The wordline voltage is represented by
V WL = 2 V PP 3 , ##EQU00003##
where V.sub.WL is the wordline voltage and V.sub.PP is the program
pulse voltage.
[0021] The bitline voltage is represented by
V BL = V PP 3 , ##EQU00004##
where V.sub.BL is the bitline voltage and V.sub.PP is the program
pulse voltage.
[0022] According to an exemplary embodiment of the present
inventive concept, there is provided a method for writing memory
cells in a nonvolatile memory device comprising wordlines
overlapping bitlines, the method comprising: applying a program
pulse voltage to a target wordline; grounding bitlines of memory
cells to be written to a first resistance state; setting a bitline
voltage of unselected bitlines; setting a wordline voltage of
unselected wordlines; applying the program pulse voltage to a
target bitline; grounding wordlines of the memory cells to be
written to a second resistance state; and setting the wordline
voltage of the unselected wordlines to a first value if a peak
maximum voltage drop of memory cells which were not meant to be
changed is greater than or equal to a second value.
[0023] The method further comprises setting the wordline voltage to
zero if the peak maximum voltage drop is not greater than or equal
to the second value.
[0024] The method further comprises setting the bitline voltage of
the unselected bitlines to a third value if the peak maximum
voltage drop is greater than or equal to the second value.
[0025] The method further comprises setting the bitline voltage to
zero if the peak maximum voltage drop is not greater than or equal
to the second value.
[0026] The nonvolatile memory device is phase-change random access
memory.
BRIEF DESCRIPTION OF THE FIGURES
[0027] The above and other features of the present inventive
concept will become apparent from the following description taken
in conjunction with the accompanying figures in which:
[0028] FIG. 1A illustrates a conventional write scheme;
[0029] FIG. 1B illustrates another conventional write scheme;
[0030] FIG. 2 illustrates parametric modeling of array cell
voltage-drops during a write operation in cross-point phase-change
random access memory (PRAM), according to an exemplary embodiment
of the inventive concept;
[0031] FIG. 3 illustrates a power tinction computing in accordance
with an exemplary embodiment of the inventive concept versus
unselected wordline and bitline voltages;
[0032] FIG. 4A illustrates optimization results for minimum average
disturbs and power consumption, according to an exemplary
embodiment of the inventive concept;
[0033] FIG. 4B is additional tabular data for FIG. 4A;
[0034] FIGS. 5A and 5B illustrate a write scheme that minimizes the
average voltage disturb and power, according to an exemplary
embodiment of the inventive concept;
[0035] FIG. 6 illustrates a write process for minimal park disturb
per cell, according to an exemplary embodiment of the inventive
concept;
[0036] FIG. 7 illustrates gain analysis results of algorithms 1 and
2 according to exemplary embodiments of the inventive concept
compared to conventional write schemes of V/2 and V/3;
[0037] FIG. 8 illustrates gain difference between algorithms 1 and
2 and write schemes of V/2 and V/3; and
[0038] FIG. 9 is a block diagram illustrating a phase change memory
device according to an exemplary embodiment of the inventive
concept.
[0039] It is to be understood that the values in the figures are
provided for reference example, and thus, the inventive concept is
not limited thereto.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0040] In accordance with an exemplary embodiment of the inventive
concept, there is provided a write algorithm that can reduce
voltage disturb and leakage power dissipation, thereby enabling
reliability and reducing cost.
[0041] Hereinafter, power consumption and disturb of a phase-change
random access memory (PRAM) cross-point matrix as a function or
wordlinelbitline voltages is modeled, and power optimization with
constrained peak voltage per cell is performed. The power-efficient
write algorithm according to an exemplary embodiment of the
inventive concept is then presented.
Constrained Power-Optimized Write Operation
[0042] A. Notations
[0043] Notation 1 (Write operation in M.times.N array matrix): the
memory cell array is marked to have M rows and N columns. Each
write operation is done in wordline granularity and has two steps:
first set the low-resistance states (positive worline-to-bitline
voltage) and second write to high-resistance cells. This write
order is referred to as SET-before-RESET, which the reverse order
is RESET-before-SET.
[0044] Notation 2 (Program pulse voltage): the voltage magnitude
that is required for a program (SET write, low resistance
state--LRS) pulse is denoted with V.sub.PP or simply V. The
negative voltage with the same value is used for RESET (setting
high resistance state--HRS).
[0045] Notation 3 (Unselected wordline/bitline voltage): the
applied potential for unselected wordlines and bitlines is marked
with A.sub.WL and V.sub.BL. The abbreviations for wordline and
bitline are WL and BL, respectively.
[0046] Notation 4 (Redundant power dissipation): when performing a
write operation, unwanted voltage drops (marked V.sub.U) may apply
on memory cells that are not meant to be changed. This voltage
multiplied by the resulting current through the device I.sub.U is
referred to as redundant power dissipation during write and denoted
with P.sub.U. For the set S={V.sub.U1, V.sub.U2, . . . } of
different possiHe V.sub.U values and for each resistance R.sub.j
out of R={R.sub.0, R.sub.1, . . . , R.sub.L-1}, the number of
corresponding affected cells is denoted G(V.sub.U1, R.sub.j).
Therefore, P.sub.U is:
P U ( S , R ) = V Ui .di-elect cons. S ( R j .di-elect cons. R I Ui
( R j ) V Ui G ( V Ui , R j ) ) = V Ui .di-elect cons. S ( R j
.di-elect cons. R V Ui 2 R j G ( V Ui , R j ) ) ##EQU00005##
[0047] It is to be assumed that data is randomized to binary IID
Bernoulli-1/2 distribution, and therefore the number of cells with
voltage drop V.sub.U1 (denoted G(V.sub.U1)) is scattered equally
among resistance levels: G(V.sub.U1)/L cells for each level. In a
memory array that occupies cells with L levels:
P U ( S ) = R eq L V Ui .di-elect cons. S ( V Ui 2 G ( V Ui ) )
##EQU00006## R eq = 1 / ( 1 R 0 + 1 R 1 + + 1 R L - 1 )
##EQU00006.2##
[0048] The constant R.sub.ee/L does not depend on the write
algorithm and thus would be assigned the value of 1 for
normalization.
[0049] Notation 5 (Maximal voltage disturb): the maximum voltage
drop over an array cell that was not meant to be changed is denoted
with V.sub.MD:
V.sub.MD(S)=max(S)=max{V.sub.U1, V.sub.U2, . . . }
[0050] Notation 6 (Cell disturb and array size constraints):
wordline write can tolerate a limited amount of resistance drift
caused by voltage disturb. Therefore, the maximal voltage drop over
cells which were not meant to be changed is constrained by up to
V.sub.PEAK. Memory array size is limited by the peak of redundant
power dissipation, denoted with P.sub.PEAK. Clearly:
V.sub.PEAK.gtoreq.V.sub.MD(S)
P.sub.PEAK.gtoreq.P.sub.U(S)
[0051] The constraints depend on each other as would be noted when
performing power and disturb optimization.
[0052] B. Electric Model of Write Operation
[0053] In a SET operation, a target wordline is biased with
V.sub.PP(V) and bitlines of cells that are meant to be written to
LRS are grounded. The unselected WL/BL are assigned with
V.sub.WL/V.sub.BL parameters as shown in FIG. 2. In a RESET
operation, the same voltages are assigned while replacing WL to BL
and vice-versa (in writing cells to HRS in the same wordline).
[0054] FIG. 2 illustrates parametric modeling of array cell
voltage-drops during a write operation in cross-point phase-change
random access memory (PRAM), according to an exemplary embodiment
of the inventive concept. The selected cells to be SET to LRS are
with voltage drop V, and variables V.sub.WL/V.sub.BL are assigned
to unselected wordlines and bitlines. Analysis shows that there are
four types for voltage drops on array cells: I. Target cells with
V; II. Cells that are on the same bitline with target written cells
are with voltage drop V.sub.WL; III. Cells that are on the same
wordline with written cells are V-V.sub.BL and IV. Cells that do
not belong to one of the previous groups get V.sub.WL-V.sub.BL
voltage drop. The RESET process has similar analysis.
[0055] Observing the framework of voltage drops on array cells,
there are four possibilities:
[0056] I. Target Cells to LRS
V.sub.1=V.sub.PP
[0057] II. Cells that Share the Same Bitline with Target LRS
Cell
V.sub.2=V.sub.WL
[0058] III. Cells on the Target WL that are Meant for IIRS
V.sub.3=V.sub.PP-V.sub.BL
[0059] IV. Other Cells that do Not Share WL/BL with LRS Cells
V.sub.4=V.sub.WL-V.sub.BL
[0060] The amount of cells of each type is evaluated for power
purposes, and therefore, it would be sufficient to simplify and
assume that the number of cells in HRS is equal to those in LRS
(IID Bernoulli-1/2 distribution with randomizer). Therefore, write
SET addresses of half the wordline cells:
G(V.sub.1)=G(V.sub.3)=1/2N
G(V.sub.2)=G(V.sub.4)=1/2N(M-1)
[0061] C. Optimization for Minimum Average Disturb and Power
[0062] Average voltage disturbs over unwanted cells and power
consumption are correlated, hence both can be optimized by
minimizing the redundant power. The power function with set S of
voltage types I to IV and the calculated affected cells is:
P U ( S ) = V Ui .di-elect cons. S ( V Ui 2 G ( V Ui ) ) = N 2 V PP
2 + N ( M - 1 ) 2 V WL 2 + N 2 ( V PP - V BL ) 2 + N ( M - 1 ) 2 (
V WL - V BL ) 2 ##EQU00007##
[0063] The power function should be minimized subject to
constraints that V.sub.1 to V.sub.4 do not exceed V.sub.PEAK or
below -V.sub.PEAK:
{ - V PEAK .ltoreq. V WL .ltoreq. V PEAK - V PEAK .ltoreq. V PP - V
BL .ltoreq. V PEAK - V PEAK .ltoreq. V WL - V BL .ltoreq. V PEAK
##EQU00008##
[0064] Optimization of the given function is performed by finding
maxima/minima points:
.differential. P U .differential. V WL = N ( M - 1 ) V WL + N ( M -
1 ) ( V WL - V BL ) ##EQU00009##
[0065] Equalizing the derivation by V.sub.WL to zero, results
in:
V WL = V BL 2 ##EQU00010##
[0066] Same analysis for the derivation by V.sub.BL results in:
.differential. P U .differential. V BL = N ( V PP - V BL ) - N ( M
- 1 ) ( V WL - V BL ) ##EQU00011##
[0067] Again, equalizing the derivation by V.sub.BL to zero,
results in:
V BL = ( M - 1 ) V BL + V PP M ##EQU00012##
[0068] The extremum point:
V BL = 2 M + 1 V PP ##EQU00013## V WL = 1 M + 1 V PP
##EQU00013.2##
[0069] The analysis of the extremurn type is:
.differential. P U .differential. V WL .differential. V BL = - N (
M - 1 ) ##EQU00014## .differential. 2 P U .differential. V WL 2 = 2
N ( M - 1 ) ##EQU00014.2## .differential. 2 P U .differential. V BL
2 = N ( M - 1 ) + N = NM ##EQU00014.3## .differential. 2 P U
.differential. V WL 2 .differential. 2 P U .differential. V BL 2 -
( .differential. P U .differential. V WL .differential. V BL ) 2 =
N 2 ( M 2 - 1 ) > 0 ##EQU00014.4##
[0070] Therefore the point is not a saddle and is either maximum or
minimum.
[0071] Since
.differential. 2 P U .differential. V WL 2 > 0 and
.differential. 2 P U .differential. V BL 2 > 0 ##EQU00015##
(M,N) are integers larger than 1) it is a minimum.
[0072] The value of M is expected to be large and may shift the
optimal point out of constrained peak values. Parameterizing
V.sub.PEAK to .alpha. a fraction of V.sub.PP:
V.sub.PEAK=.alpha.V.sub.PP
[0073] Would result in corresponding constraints:
- .alpha. .ltoreq. 1 M + 1 .ltoreq. .alpha. and - .alpha. .ltoreq.
M - 1 M + 1 .ltoreq. .alpha. ##EQU00016##
[0074] The requirement of
M - 1 M + 1 .ltoreq. .alpha. ##EQU00017##
with a large M would require a peak voltage that is close to
V.sub.PP and the current optimization may change the resistance of
neighbor cells. However, the requirement of
-V.sub.PEAK.ltoreq.V.sub.PP-V.sub.BL.ltoreq.V.sub.PEAK holds for
cells in the same wordline that are meant to be written to HRS
during RESET. Therefore, disturb on those cells can be tolerated in
the SET phase, since the consecutive write step will correct
it.
[0075] The following RESET phase voltages have to be re-optimized
since it cannot tolerate disturbs. Unselected WL and BL voltages
depend on an .alpha.V.sub.PP value. We analyze the power function
based on .alpha. to obtain the coefficients C.sub.WL and C.sub.BL
which would be multiplied by V.sub.PP to obtain the optimal
unselected W.sub.L and B.sub.L voltages:
V.sub.BL=C.sub.BL(.alpha.)V.sub.PP
V.sub.WL=C.sub.WL(.alpha.)V.sub.PP
[0076] Results of the constrained optimization are:
C BL ( .alpha. ) = { 0.9965 - 0.9934 .alpha. .alpha. .gtoreq. 1 / 3
0 else C WL ( .alpha. ) = { 0.4982 - 0.4967 .alpha. .alpha.
.gtoreq. 1 / 3 0 else ##EQU00018##
[0077] FIG. 3 illustrates a power function (P.sub.U) versus
unselected WL/BL voltages .alpha.=1/2.
[0078] Optimization results are verified by simulation and are
depicted in FIGS. 4A and 4B. For example, if write voltage
V.sub.PP=1[V], V.sub.PEAK=V.sub.PP/2, the corresponding voltages
are V.sub.WL=C.sub.WL=0.5[V] and V.sub.BL=C.sub.BL=0.25 [V].
[0079] More specifically, FIG. 4A illustrates optimization results
for minimum average disturbs and power consumption, according to an
exemplary embodiment of the inventive concept. The graph of FIG. 4A
shows the optimal voltage coefficients for unselected WLs and. BLs
during a write operation versus Alpha. It is can be seen that given
the constraint of V.sub.PEAK<.alpha.V.sub.PP, the desired
voltages are zero. The values have to be multiplied by V.sub.PP for
nominal voltage. For example, if V.sub.PP=2V, V.sub.PEAK=1V, then
unselected V.sub.WL=1V and V.sub.BL=0.5V.
[0080] The write scheme that minimizes the average voltage disturb
and power according to an exemplary embodiment of the inventive
concept is illustrated in FIGS. 5A and 5B.
[0081] FIG. 5A illustrates a SET phase of the write scheme. As
shown in FIG. 5A, V.sub.PP is applied to a target wordline (505),
and bitlines of cells to be written to LRS are grounded (510).
Next, unselected bitlines voltages are set to
V BL = 2 M + 1 V PP ( 515 ) , ##EQU00019##
and unselected wordlines voltages are set to
V WL = 1 M + 1 V PP ( 520 ) . ##EQU00020##
[0082] FIG. 5B illustrates a RESET phase of the write scheme. As
shown in FIG. 5B, V.sub.PP is applied to a target bitline (525),
and wordlines of cells to be written to HRS are grounded (530).
Then, it is determined if V.sub.PEAK.gtoreq.V.sub.PP/3 (535). If
V.sub.PEAK.gtoreq.V.sub.PP/3, the unselected wordlines voltage is
set to V.sub.WL=(0.9965-0.9934 .alpha.)V.sub.PP (540). In addition,
if V.sub.PEAK.gtoreq.V.sub.PP/3, the unselected bitlines voltage is
set to V.sub.BL=(0.4982-0.4967 .alpha.)V.sub.PP (545). In the event
that V.sub.PEAK is not .gtoreq.V.sub.PP/3, the unselected wordlines
voltage is set to zero (550) and the unselected bitlines voltage is
set to zero (555).
[0083] D. Optimization for Minimum Peak Disturb
[0084] The minimal peak disturb approach is provided to reduce
V.sub.MD(S) as much as possible. As V.sub.MD(S) depends on the set
of voltages S, the following constrained optimization is
considered:
min(|V.sub.WL|,|V.sub.PP-V.sub.BL|,|V.sub.WL-V.sub.BL|)
[0085] Subject to:
{ - .alpha. V PP .ltoreq. V WL .ltoreq. .alpha. V PP - .alpha. V PP
.ltoreq. V PP - V BL .ltoreq. .alpha. V PP - .alpha. V PP .ltoreq.
V WL - V BL .ltoreq. .alpha. V PP ##EQU00021##
[0086] The solution depends on the voltage of .alpha.. If
.alpha.<1/3 there do not exist voltages that satisfy the
constraints. If .alpha..gtoreq.1/3, the solution is:
V.sub.BL=2/3V.sub.PP
[0087] In this case
V.sub.MD(S)=1/3V.sub.PP.
[0088] Now we now observe that peak disturb is not required in
cells of type III,
-.alpha.V.sub.PP.ltoreq.V.sub.PP-V.sub.BL.ltoreq..alpha.V.sub.P- P
during the SET phase, since those would be changed to HRS during
reset. Therefore, we can reduce write disturb to zero in all cells
that are not on the target wordline during the SET operation and
use the above-described voltage optimization for the RESET phase.
In this scheme, the write disturb can be reduced by 50%.
[0089] The write process for minimal perk disturb per cell
according to an exemplary embodiment of the inventive concept is
illustrated in FIG. 6.
[0090] As shown in FIG. 6, in a SET phase: V.sub.PP is applied to a
target wordline (605), bitlines of cells to be written to LRS are
grounded (610), and unselected wordlines and bitlines are grounded
(615). In a RESET phase: V.sub.PP is applied to a target bitline
(620), wordlines of cells to be written to HRS are grounded (625),
unselected wordlines voltages are set to V.sub.WL=2V.sub.PP/3 (630)
and unselected bitlines voltages are set to V.sub.BL=V.sub.PP/3
(635).
Gain Analysis and Implementations
[0091] Hereinafter, the write schemes discussed above and
illustrated in FIGS. 5A, 5B and 6 will be compared to conventional
write schemes. The write scheme of FIGS. 5A and 5B will be referred
to as Algorithm 1 and the write scheme of FIG. 6 will be referred
to as Algorithm 2.
[0092] For comparison in power consumption, we used Algorithm 1
with .alpha.=1/2 for peak write disturb V.sub.PP/2 (same as V/2
scheme) and Algorithm 2 has a peak of V.sub.PP/3 (similar to V/3
scheme) but it is only applied at the RESET phase. Power was
calculated as described in the Electric Model of Write Operation
section above.
[0093] Results are depicted in FIG. 7. In reference to FIG. 7, we
can observe that Algorithm 1 with .alpha.=1/2 has 50% and 25%
reduction in write disturb and 70% and 80% power reduction
comparing to V/2 and V/3 write schemes, respectively. Analysis of
algorithm 2 shows 66% and 50% less write disturb and 55% and 70%
less power regarding V/2 and V/3 schemes. The gain difference from
the conventional schemes is presented in FIG. 8.
[0094] Implementation of Algorithms 1 and 2 requires support of a
WL/BL voltage regulator in a power supply chip module. Algorithms 1
and 2 also require proper program software at the chip embedded
microcontroller to manage the write operation.
[0095] FIG. 9 is a block diagram illustrating a phase change memory
device according to an exemplary embodiment of the inventive
concept.
[0096] Examples of phase change memory devices and systems for use
in accordance with exemplary embodiments of the inventive concept
are described in U.S. Pat. No. 8,134,866 entitled "Phase Change
Memory Devices and Systems, and Related Programming Methods," the
disclosure of which is incorporated by reference herein in its
entirety.
[0097] Referring to FIG. 9, a phase change memory device 200
comprises a memory cell array 210 wherein each memory cell stores
N-bit data. (N is an integer greater than 0). Although not shown in
detail in FIG. 9, memory cell array 210 comprises a plurality of
rows corresponding to word lines and columns corresponding to bit
lines, and memory cells arranged in a matrix at intersections
between the bit lines and word lines.
[0098] Each of the memory cells in memory cell array 210 typically
comprises a switching device and a resistor. In general, the
switching device may be embodied by various elements such as a
metal-oxide semiconductor (MOS) transistor or a diode. In addition,
each memory cell in memory cell array 210 is an over-writable
memory cell. Examples of memory cells that could be used in memory
cell array 210 are described in U.S. Pat. No. 6,928,022 entitled
"Write Drive Circuit in Phase Change Memory Device and Method for
Applying Write Current", U.S. Pat. No. 6,967,865 entitled
"Low-Current and High-Speed Phase-Change Memory Devices and Methods
of Driving The Same", and U.S. Pat. No. 6,982,913 entitled "Data
Read Circuit for Use in a Semiconductor Memory and a Memory
Thereof". The respective disclosures of these patents are hereby
incorporated by reference.
[0099] A row select circuit 220 selects at least one word line
among the plurality of word lines in response to a row address RA,
and a row select circuit 230 selects a subset of the plurality of
bit lines in response to a column address CA. A control logic unit
240 is configured to control overall operations of phase change
memory device 200 in response write/read commands from an external
source. A high voltage generating circuit 250 is controlled by
control logic unit 240, and is configured to generate a high
voltage used by row and column select circuits 220 and 230 and a
write driver circuit 290. For example, high voltage generating
circuit 250 may comprise a charge pump. However, those skilled in
the art will recognize that high voltage generating circuit 250
could be embodied by a variety of other elements besides a charge
pump.
[0100] A first sense amplifier circuit 260, labeled RSA, is
controlled by control logic unit 240, and senses cell data through
bit lines selected by column select circuit 230 in a normal read
operation. The sensed data is output via a data input/output buffer
circuit 270. First sense amplifier circuit 260 is connected to a
data bus RDL and applies sense current I_SENSE to data bus RDL in
the normal read operation. A second sense amplifier circuit 280,
labeled VSA, is also controlled by control logic unit 240 and
senses cell data through the bit lines selected by column select
circuit 230 using program data stored in data input/output buffer
circuit 270 during the verify read operation. Second sense
amplifier circuit 280 variably applies verify current I_SET or
I_RESET to the selected bit lines according to program data
temporarily stored in data input/output buffer circuit 270.
[0101] Cell data sensed by second sense amplifier circuit 280 is
applied to control logic unit 240. Control logic unit 240
determines whether or not the cell data sensed by second sense
amplifier circuit 280 is identical to the program data stored in
data input/output circuit 270. Control logic unit 240 controls
write driver circuit 290 according a result of this determination.
For instance, where the program data is determined to be identical
to the sensed data, control logic unit 240 does not generate set
and reset pulse signals corresponding to program data. On the other
hand, where the program data value is determined not to be
identical to the sensed data, control logic unit 240 generates set
and reset pulse signals corresponding to the program data, or in
other words, a program loop is repeated.
[0102] With each repetition of the program loop, control logic unit
240 controls write drive circuit 290 such an amount of a write
current I_SET_W or I_RESET_W applied to selected bit lines in the
program loop increases or decreases gradually. A bias voltage
generating circuit 300 is controlled by control logic unit 240, and
is configured to generate bias voltages to be applied to first and
second sense amplifier circuits 260 and 280 and write driver
circuit 290, respectively.
[0103] The phase change memory device 200 may be part of a memory
system that includes a memory controller.
[0104] The memory controller may include a microprocessor, a
read-only memory (ROM), a random access memory (RAM), a memory
interface, and a bus. The elements of the memory controller may be
electrically connected to each other through the bus.
[0105] The microprocessor controls the overall operation of the
memory system including the memory controller. The microprocessor
is a circuit that controls other elements by generating control
signals. When power is supplied to the memory system, the
microprocessor drives firmware (e.g., stored in the ROM) for
operating the memory system on the RAM, thereby controlling the
overall operation of the memory system. According to an exemplary
embodiment of the inventive concept, the microprocessor may also
issue instructions for controlling operations of other elements of
the memory controller including, for example, some or all of the
ROM, RAM, memory interface, and a bus. According to an exemplary
embodiment of the inventive concept, any operations described
herein as being performed by the memory controller may be performed
by, or under the control of, the microprocessor. According to an
exemplary embodiment of the inventive concept, any operations
described herein as being performed by the memory controller may be
performed by, or under the control of, the microprocessor executing
instructions that correspond to the operations and are included in
program code (e.g., stored in the ROM).
[0106] While a driving firmware code of the memory system is stored
in the ROM, exemplary embodiments of the inventive concept are not
limited thereto. The firmware code can also be stored in a portion
of the memory device 200 other than the ROM. Therefore, the control
or intervention of the microprocessor may encompass not only the
direct control of the microprocessor but also the intervention of
firmware which is software driven by the microprocessor.
[0107] The RAM, which is a memory serving as a buffer, may store an
initial command, data, and various variables input from a host or
the microprocessor, or data output from the memory device 200. The
RAM may store data and various parameters and variables input to
and output from the memory device 200.
[0108] The memory interface may serve as an interface between the
memory controller and the memory device 200. The memory interface
is connected to an I/O pad of the memory device 200 and may
exchange data with the I/O pad. In addition, the memory interfitce
may create a command suitable for the memory device 200 and provide
the created command to the I/O pad of the memory device 200. The
memory interface provides a command to be executed by the memory
device 200 and an address of the memory device 200.
[0109] It is to be understood that the above described methods of
the inventive concept may be carried out by one or more of the
above described elements of the controller and memory device
200.
[0110] It is to be further understood that components described
herein and illustrated in drawings may be implemented with
software, hardware, or a combination thereof, for example. In an
exemplary embodiment of the inventive concept, the software may be
a machine code, firmware, an embedded code, and application
software. For example, the hardware may include an electrical
circuit, an electronic circuit, a processor, a computer, an
integrated circuit, integrated circuit cores, or a combination
thereof.
[0111] The write schemes discussed above and illustrated in FIGS.
5A, 5B and 6 addressed single-level cell (SLC) architecture. It is
to be understood, however, that their adaptation to multi-level
cell (MLC), either 4 or 8 levels or any other, is straightforward
by supplying the relevant voltages, and other multi-phase scenarios
such as RESET-before-SET or any composition that considers the
write time in addition to voltage magnitude.
Conclusions
[0112] PRAMS have to be packed in an efficient array structure in
order to reflect device behavior in a product specification. In
data storage applications, cost-per-bit is very important, and
currently the densest topology is with cross-point array
structures.
[0113] Although cross-point structures achieve competitive cell
size, they have drawbacks. One shortcoming is the cell disturb and
redundant power dissipation during write operation. Disturbs are
the voltage drops over cells which were meant to remain in their
resistance state, and may cause data errors. Redundant power is
consumed by parasitic currents and limits the array size, thus
blocking the cross-point array from achieving its density
potential.
[0114] Optimizing the write process has inherent conflicts. Setting
low peak write disturb by certain voltage configurations limits
cell's resistance change and prevents errors, but causes increased
redundant power consumption that dissipates in cells that are not
involved in the write mechanism. The other aspect of the matter is
that using other sets for voltages to reduce power may result in
more disturbs and thus harm data integrity.
[0115] In this disclosure, we presented two novel write algorithms
that achieve better characteristics that conventional write
schemes. In both of the write algorithms, we observe that write has
at least two time phases with different voltages, and consequently
disturbs in cells on the same wordline in the first phase will be
corrected in the second one. Therefore, the early step is optimized
for power reduction. In the first algorithm, we modeled PRAM
cross-point topology and explored optimal voltages for minimal
power. The second algorithm was constrained to peak disturb.
Analysis shows that the write algorithms achieve up to 66% less
disturb and 80% lower power than the conventional write
schemes.
[0116] The novel write algorithms presented herein enable PRAM
array size to be enlarged and PRAM reliability to be enhanced.
[0117] While the present inventive concept has been described with
reference to exemplary embodiments thereof, it will be apparent to
those skilled in the art that various changes and modifications may
be made thereto without departing from the spirit and scope of the
present inventive concept as defined by the attached claims.
* * * * *