U.S. patent application number 16/876365 was filed with the patent office on 2020-10-01 for method and apparatus to generate zero content over garbage data when encryption parameters are changed.
This patent application is currently assigned to WESTERN DIGITAL TECHNOLOGIES, INC.. The applicant listed for this patent is WESTERN DIGITAL TECHNOLOGIES, INC.. Invention is credited to Darin Edward Gerhart, Cory Lappi, Daniel Robert Lipps, William Jared Walker.
Application Number | 20200310989 16/876365 |
Document ID | / |
Family ID | 1000004888821 |
Filed Date | 2020-10-01 |
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United States Patent
Application |
20200310989 |
Kind Code |
A1 |
Gerhart; Darin Edward ; et
al. |
October 1, 2020 |
METHOD AND APPARATUS TO GENERATE ZERO CONTENT OVER GARBAGE DATA
WHEN ENCRYPTION PARAMETERS ARE CHANGED
Abstract
A method is provided that includes reading data in a storage
medium, detecting, during the reading of the data in the storage
medium, by a controller a change in an encryption/decryption scheme
used to read and write the data in the storage medium, in response
to detecting the change in encryption/decryption scheme in the
data, causing, by the controller, a logical block address to return
an indication of being written in zeros when a physical block
address associated with the logical block address encrypted using
an first encryption/decryption scheme, and causing, by the
controller, a write channel to write zeroes using a second
encryption/decryption scheme to the physical block address.
Inventors: |
Gerhart; Darin Edward;
(Oronoco, MN) ; Lappi; Cory; (Rochester, MN)
; Lipps; Daniel Robert; (Kasson, MN) ; Walker;
William Jared; (Rochester, MN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
WESTERN DIGITAL TECHNOLOGIES, INC. |
San Jose |
CA |
US |
|
|
Assignee: |
WESTERN DIGITAL TECHNOLOGIES,
INC.
San Jose
CA
|
Family ID: |
1000004888821 |
Appl. No.: |
16/876365 |
Filed: |
May 18, 2020 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15967033 |
Apr 30, 2018 |
10698840 |
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16876365 |
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15226639 |
Aug 2, 2016 |
9959218 |
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15967033 |
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15051539 |
Feb 23, 2016 |
9436618 |
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15226639 |
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14467724 |
Aug 25, 2014 |
9298647 |
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15051539 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F 21/602 20130101;
G06F 2221/2123 20130101; G06F 2221/2143 20130101; H04L 2209/12
20130101; H04L 9/0894 20130101; G06F 21/00 20130101; H04L 2209/34
20130101; G06F 12/1408 20130101; G06F 21/6227 20130101; G09C 1/00
20130101 |
International
Class: |
G06F 12/14 20060101
G06F012/14; G09C 1/00 20060101 G09C001/00; H04L 9/08 20060101
H04L009/08; G06F 21/60 20060101 G06F021/60; G06F 21/00 20060101
G06F021/00; G06F 21/62 20060101 G06F021/62 |
Claims
1. A method comprising: reading data in a storage medium;
detecting, during the reading of the data in the storage medium, by
a controller a change in an encryption/decryption scheme used to
read and write the data in the storage medium; in response to
detecting the change in encryption/decryption scheme in the data,
causing, by the controller, a logical block address to return an
indication of being written in zeros when a physical block address
associated with the logical block address encrypted using an first
encryption/decryption scheme; and causing, by the controller, a
write channel to write zeroes using a second encryption/decryption
scheme to the physical block address.
2. The method of claim 1, further comprising mapping, by the
controller, the logical block address to the physical block address
using the map.
3. The method of claim 2, further comprising removing, by the
controller, a pointer from the logical block address to the
physical block address in response to detecting to detecting the
change in encryption/decryption scheme.
4. The method of claim 2, wherein removing the pointer from the
logical block address to the physical address comprises removing,
by the controller, pointers for the plurality of logical block
addresses.
5. The method of claim 1, wherein the information representing data
written to the respective physical block address associated with
the respective logical block address is written using the first
encryption/decryption scheme.
6. The method of claim 1, wherein respective logical block
addresses of a plurality of logical block addresses are associated
with respective physical block addresses of a plurality of physical
block addresses written with the first encryption/decryption
scheme, wherein the plurality of logical block addresses mapped to
the physical block addresses in a map, and wherein the map
comprises at least one flag indicating that information
representing data at a respective logical block address is
invalid.
7. An apparatus comprising: means for reading data in a storage
medium; means for detecting, during the reading of the data in the
storage medium, by a controller a change in an
encryption/decryption scheme used to read and write the data in the
storage medium; means for detecting the change in
encryption/decryption scheme in the data, causing, by the
controller, a logical block address to return an indication of
being written in zeros when a physical block address associated
with the logical block address encrypted using an first
encryption/decryption scheme; and means for causing, by the
controller, a write channel to write data using a second
scheme.
8. The apparatus of claim 7, wherein the means for causing the
write channel to write data using the second scheme involves using
an encryption/decryption scheme.
9. The apparatus of claim 7, wherein the means for causing the
write channel to write data uses the physical block address.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. patent application
Ser. No. 15/967,033, filed Apr. 30, 2018, now U.S. Pat. No. ______,
which is a continuation of U.S. patent application Ser. No.
15/226,639, filed Aug. 2, 2016, now U.S. Pat. No. 9,959,218, which
is a continuation of U.S. patent application Ser. No. 15/051,539,
filed Feb. 23, 2016, now U.S. Pat. No. 9,436,618, which is a
continuation of U.S. patent application Ser. No. 14/467,724, filed
Aug. 25, 2014, now U.S. Pat. No. 9,298,647. Each of the
aforementioned related patent applications is herein incorporated
by reference herein in their entirety for all purposes.
BACKGROUND
[0002] Various embodiments described herein relate to a method and
apparatus that is used to prevent the generation of garbage data
after certain parameters associated with the data, such as an
encryption parameter, are changed.
[0003] Storing data includes writing information representing the
data to a storage device or apparatus. There are many types of
storage devices. Even though varied, most of the storage devices
have common goals. Among the goals are to store increased amounts
of data, and to provide a means to make sure the data as stored is
secure. Encryption is one way to make the data secure. Encryption
is the process of encoding information in such a way that only
authorized parties can read it. Encryption doesn't prevent hacking
but it reduces the likelihood that the hacker will be able to read
the data that is encrypted.
[0004] In an encryption scheme, the information, referred to as
plaintext, is encrypted using an encryption algorithm, turning it
into an unreadable cipher text. This is usually done with the use
of an encryption key, which specifies how the message is to be
encoded. Any adversary that can see the cipher text should not be
able to determine anything about the original information. An
authorized party, however, is able to decode the cipher text using
a decryption algorithm, that usually requires a secret decryption
key, that adversaries do not have access to. For technical reasons,
an encryption scheme usually needs a key-generation algorithm to
randomly produce keys.
[0005] From time to time, encryption parameters, such as
encryption/decryption keys, can be changed for a storage device.
When encryption parameters are changed, like a key or range
parameter, it is possible to have garbage data with cyclic
redundancy check ("CRC") errors in the logical block address
("LBA") space of the change.
[0006] Currently, a solution for preventing the CRC errors is to
disable all data protection on encrypted drives. This exposes the
data. The data are not secure when the data protection scheme is
disabled. Of course, this solution falls short of certain standards
for the security of the data. Many manufacturers that use storage
devices in products they offer qualify the storage devices on the
basis of compliance with standards. Turning off the security
feature prevents proper T10 data protection on encrypted storage
devices. Another standard many have to comply with is the Opal SSC
standard. The standard states that: [0007] "An Opal SSC compliant
SD SHALL implement Full Disk Encryption for all host accessible
user data stored on media. AES-128 or AES-256 SHALL be supported
[Paragraph 2.4, page 10 of 81 of the TCG Storage Opal SSC, version
1.0." [0008] "The Opal SSC is an implementation profile for Storage
Devices built to: [0009] Protect the confidentiality of stored user
data against unauthorized access once it leaves the owner's control
(involving a power cycle and subsequent deauthentication) [0010]
Enable interoperability between multiple SD vendors [0011] "An Opal
SSC compliant SD: [0012] Facilitates feature discoverability [0013]
Provides some user definable features (e.g., access control,
locking ranges, user passwords, etc.) [0014] Supports Opal SSC
unique behaviors (e.g., communication, table management) [Section
2.1, page 10/81]
[0015] If the data are secure at all times, the confidentiality of
stored user data is protected against unauthorized access once it
leaves the owner's control. In addition, meeting a standard for
security of the data on a storage apparatus enables
interoperability between multiple storage device vendors. Meeting a
standard also facilitates feature discoverability, provides some
user definable features (e.g., access control, locking ranges, user
passwords, etc.) and supports unique behaviors (e.g.,
communication, table management).
SUMMARY
[0016] A memory device including at least one memory location for
storing information representing data written using a first
encryption/decryption method, and a read channel using a second
encryption/decryption method for reading and decrypting information
as written. The memory device also includes an apparatus that
prevents the reading of the at least one memory location using the
second encryption/decryption method, in response to an indication
that the at least one memory location was written using the first
encryption/decryption method.
[0017] The apparatus that prevents the reading of the at least one
physical block address also includes a device for returning zero
content for the at least one memory location written using the
first encryption/decryption method in response to an indication the
read channel uses a second encryption/decryption method. The
apparatus that prevents the reading of the at least one memory
location written with the first encryption/decryption method, in
one embodiment, includes a device for writing zeroes to the at
least one memory location written using the first
encryption/decryption method.
[0018] A storage apparatus includes a solid state device having a
plurality of memory locations, a write channel for writing
information representing data to the plurality of memory locations
in a solid state device, and a read channel for reading information
representing data from the plurality of memory locations in a solid
state device. The storage apparatus also includes a controller that
controls operations of the storage apparatus including the writing
of information to the plurality of memory locations in a solid
state device and the reading of information representing data from
the plurality of memory locations in a solid state device.
[0019] The storage apparatus also includes an indirection system
further including a set of logical block addresses, and a set of
physical block addresses that correspond to the plurality of memory
locations in the solid state device of the storage apparatus. The
indirection system also includes a map that associates a logical
block addresses to at least one physical block address. The map
also includes at least one flag indicating an encryption/decryption
method used to write and read data from the physical block address.
The controller returns a reading of zeroes when the
encryption/decryption method used to read the physical block
address has changed.
[0020] A method for decreasing the generation of garbage data in a
storage apparatus includes monitoring a storage apparatus for a
change in an encryption/decryption scheme used to read and write
data, and in response to the change in encryption/decryption
scheme, causing at least one logical block address to return an
indication of being written in zeroes when the physical block
address associated with the logical block address had been
encrypted using the old encryption/decryption scheme.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The embodiments will be readily understood by the following
detailed description in conjunction with the accompanying drawings,
wherein like reference numerals designate like structural elements,
and in which:
[0022] FIG. 1 A is a schematic diagram of NAND flash type memory,
according to an example embodiment.
[0023] FIG. 1B is another schematic diagram of NAND flash type
memory device, according to an example embodiment.
[0024] FIG. 2 is a schematic diagram of a memory apparatus or
device, according to an example embodiment.
[0025] FIG. 3 is schematic of an indirection system of a memory
device, according to an example embodiment.
[0026] FIG. 4 is one type of table associated with an indirection
system of a memory device, according to an example embodiment.
[0027] FIG. 5 is a method for returning "zeroes" from data written
with a different or old encryption scheme, according to an example
embodiment.
[0028] FIG. 6 is a method for returning "zeroes" from data written
with a different or old encryption scheme, according to an example
embodiment.
[0029] FIG. 7 is another type of table associated with an
indirection controller of a memory device, according to an example
embodiment.
[0030] FIG. 8 is a method for returning "zeroes" from data written
with a different or old encryption scheme, according to an example
embodiment.
[0031] FIG. 9 is yet another type of table associated with an
indirection controller of a memory device, according to an example
embodiment.
[0032] FIG. 10 is a flow diagram of a method for preventing the
generation of garbage data, according to an example embodiment.
DETAILED DESCRIPTION
[0033] In the following paper, numerous specific details are set
forth to provide a thorough understanding of the concepts
underlying the described embodiments. It will be apparent, however,
to one skilled in the art that the described embodiments can be
practiced without some or all of these specific details. In other
instances, well known process steps have not been described in
detail in order to avoid unnecessarily obscuring the underlying
concepts.
[0034] In general, this disclosure describes techniques for writing
and reading data to a solid state device or other storage medium
such as hard disk drives, hybrid devices, and the like. In this
particular application, this disclosure describes writing and
reading information representing data to a flash memory-based solid
state device. It should be noted that this is one type of storage
medium or solid state device and that the invention could be used
in solid state devices that employ other types of storage
technologies. In other words, the invention is not limited to flash
memory and could be used in other types of memory, such as
phase-change-memory (PCM), Magnetoresistive random-access memory
(MRAM), Resistive random-access memory (RRAM or ReRAM), or the
like.
[0035] Now, returning to the discussion of flash memory. There are
two main types of flash memory, which are named after the type of
logic gates used to form the flash memory. There is NAND type flash
memory, and NOR type flash memory. The internal characteristics of
the individual flash memory cells exhibit characteristics similar
to those of the corresponding gates. NAND type flash memory can be
easily written and read in blocks (or pages) which are generally
much smaller than the entire device. NOR type flash allows a single
machine word (byte) to be easily written-to an erased location-or
read independently.
[0036] The NAND type is primarily used in main memory, memory
cards, USB flash drives, solid-state drives, and similar products,
for general storage and transfer of data. The NOR type, which
allows true random access and therefore direct code execution, is
used as a replacement for the older EPROM and as an alternative to
certain kinds of ROM applications, whereas NOR flash memory can
emulate ROM primarily at the machine code level; many digital
designs need ROM (or PLA) structures for other uses, often at
significantly higher speeds than (economical) flash memory may
achieve.
[0037] FIG. 2 is a schematic diagram of a memory apparatus or
device 200. Memory is made up of memory locations or bits 210, 211,
212, 213, 214 arranged in a two-dimensional grid. The bits 210,
211, 212, 213, 214 are arranged in columns (CAS) 220, 221, 222,
223, 224, 225, 226, 227 and rows (RAS) 230, 231, 232, 233, 234,
235, 236, 237. Each bit can be identified by a column and row. For
example, bit 211 is in column 225 and row 232. This particular bit
is cross hatched to represent a "1" value. A bit not cross hatched,
such as bot 214, represents a "0" value.
[0038] To write data to a column, a column is selected and then
rows are charged to write data into the bits associated with the
specific column. As an example, when column 225 is written, column
225 is selected. Rows 230, 232, 234, 235 and 236 are charged
resulting in a "1" value stored at the particular bit locations
(shown as cross hatched).
[0039] Put another way, memory cells are etched onto a silicon
wafer in an array of columns (bitlines) and rows (wordlines). The
intersection of a bitline and wordline constitutes the address of
the memory cell.
[0040] A charge is passed through the appropriate column (CAS) to
activate the transistor at each bit in the column. When writing,
the row lines contain the state the capacitor should take on. When
reading, a sense-amplifier determines the level of charge in the
capacitor. If it is more than 50 percent, it reads it as a 1;
otherwise it reads it as a 0. The counter tracks the refresh
sequence based on which rows have been accessed in what order. The
length of time necessary to do all this is expressed in
nanoseconds.
[0041] Memory cells alone would be worthless without some way to
get information in and out of them. Memory devices include circuits
associated with the memory to identify each row and column, to read
and restore signals from cells, and to enable charges at various
memory addresses.
[0042] FIGS. 1A and 1B each show a schematic diagram of NAND flash
type memory 100 and 100', according to an example embodiment. In
each case, a NAND Flash solid state device 100 is attached to a
host computer via a host processor 130. In FIG. 1A, the host
processor 130 handles many of the operations associated with
reading and writing information representing data to the NAND flash
solid state device 100.
[0043] The host processor 130 includes an error correction code
(ECC) module 131, bad block management module 132, a wear leveling
module 133, a NAND Flash driver module 134, and address indirection
module 135. All of these modules can be hardware, software or a
combination of hardware and software. The error correction code
(ECC) module 131 handles the determination of an error in data read
and the application of error correction code (ECC) to the data as
read. The error correction code is used to locate and correct the
error in a block of data as read.
[0044] The bad block management module 132 handles bad blocks in
the NAND Flash 100. Data from a host will generally come from the
host as a block of data. The block of data can be of any length,
although 512 bytes and 4000 have been standardized lengths and are
very common. The NAND Flash is able to receive blocks of data. The
manufacturing of a solid state device, in some instances, is less
than perfect.
[0045] As a result, there may be one or more memory locations which
are defective and will not allow a block of data to be stored
reliably there so that it can be later retrieved. The bad block
management module 132 stores these bad block locations and prevents
data from being stored there. Bad blocks can also appear during the
life of the NAND Flash 110 so the bad block management module 132
also notes any other memory locations that have developed into bad
blocks.
[0046] The address indirection module 135 works in concert with the
bad block management module 132. The address indirection module 135
includes a mapping of actual physical block addresses (PBAs) to
logical block addresses (LBAs). The LBAs stay constant. The host
can then give a command to write to a particular LBA. The actual
address where the data are stored (PBA) can change. The address
indirection module 135 tracks the location of the LBA as written to
or stored on the NAND Flash 110.
[0047] Thus, when the host needs to read data from the NAND Flash
110, the address indirection module 135 makes sure the proper PBA
associated with the LBA is read to assure that the information
representing the data is read and presented for further processing
to duplicate the data as input to the NAND Flash solid state
device.
[0048] The address indirection module 135 is also necessary for
wear leveling. If data are written to a particular memory location
more than a number of wear cycles, the memory location can wear out
or become unreliable. Wear leveling recognizes this and elongates
the life of the memory by changing memory locations or actual
physical locations where the information is written. The LBA will
stay the same while the PBA will change to prevent excessive early
wear.
[0049] The wear leveling module 133 monitors and manages where data
are written. A NAND Flash has many memory locations where data can
be written to. These memory locations "wear out" over time. The
memory locations within a NAND Flash 110 can only be reliably
rewritten for a number of cycles. The wear leveling module 133
monitors the number of reads and writes to various memory locations
and will switch the memory location to elongate the life of the
NAND Flash 110.
[0050] For example, if only half of the memory locations were
constantly written to that half of the NAND Flash would wear out.
Although the entire device would not be worn out, the capacity to
store data would be severely hindered resulting in poor
performance. The wear leveling module 133 manages the wear on the
NAND Flash 110. The wear leveling module 133 effectively lengthens
the life of the NAND Flash 110. It too works with the address
indirection module 135 as the wear leveling module 133 can decide a
particular set of blocks (PBAs) need to be set aside to prevent
premature wearing of the memory locations in the NAND Flash
110.
[0051] The NAND Flash driver module 134 is an instruction set for
operation of the NAND Flash 110.
[0052] The solid state device 100 also includes a security module
136. The security module 136 encrypts data as written and decrypts
the data when read. The encryption of the data keeps the data
secure. It is important to keep the data secure at all times,
according to common sense as well as certain criteria for products
which must be met for the product to qualify for use in other
products. In some instances, qualifying a product can include
meeting a standard for security of the data.
[0053] In some encryption and decryption schemes, a key piece of
information (also known as a parameter) determines the functional
output of a cryptographic algorithm or cipher. Without a key, the
algorithm would produce no useful result. In encryption, a key
specifies the particular transformation of plaintext into
ciphertext, or vice versa during decryption. Keys are also used in
other cryptographic algorithms, such as digital signature schemes
and message authentication codes for products which standards
organizations set.
[0054] This particular invention deals with instances where a
parameter is changed. For example, a key might be changed. It
should be noted that when encoded information is read, the key
associated with the writing must be used along with the algorithm
to decode the information and transform it to the data as
written.
[0055] Without the parameter, or when the parameter is incorrect,
the decoding algorithm does not work. An output of information
representing data decoded with the wrong key is generally termed as
garbage. It is not the original data as written. Garbage can also
tax a data channel during an attempted read.
[0056] For example, when garbage information is read, the error
correction module will determine that there is a mistake in the
data as read. The "error" resulting from garbage data will not be
correctable on-the-fly. Depending on the scheme for error
correction, the error correction module could seek to recover the
data using various deep data recovery techniques. This wastes time
and also will waste the time of the processor trying to correct the
"error". This of course is just one example of the problems that
can result from reading information which turns out to be garbage
data.
[0057] FIG. 1B shows a schematic diagram of another type of NAND
flash type memory device 100', according to an example embodiment.
In each case, a NAND Flash solid state device 110 is attached to a
host computer via a host processor 130. The main difference between
memory device 100' and memory device 100, is the processor 120
which is located with the NAND type solid state device 100'. The
processor 120 is separate from the host processor 130. The host
processor 130, in the case of the NAND type solid state device
100', offloads some of the processing modules to the processor 120
associated with the NAND type solid state device 100'.
[0058] The processor 120 can be a general purpose processor or can
be a dedicated processor which handles a specific task or tasks. As
shown in FIG. 1B, the processor 120 includes the error correction
code (ECC) module 131, the bad block management module 132, and the
wear leveling module 133, for example. These operations are passed
off from the host processor 130 to the processor 120 or NAND
controller. These blocks 131, 132, and 133 function in the same way
as discussed above with respect to FIG. 1A. These functions will
not be repeated here for the sake of brevity.
[0059] In FIG. 1B, a data bus 160, a command line 161 and a clock
signal 162 communicatively couple the host processor and the NAND
controller or processor 120. Some of the commands passed over the
command line 161 merely command one of the modules 131, 132, 133 to
begin their specific processes. This is helpful in that the host
processor 130 is freed up to do other tasks. The number of tasks
passed off from the host to the NAND controller 120 is a matter of
a balance of determining which tasks are totally specialized and
better accomplished by the NAND controller 120. Other tasks may be
more generally applicable and kept resident the host processor
130.
[0060] As described above, data stored on NAND type flash memory
110, 110' can be organized as data blocks. In some example
embodiments, the address indirection is used to write blocks of
data to NAND type flash memory 110, 110'. That is, host file
systems deal with logical block addresses (LBAs) in commands to
write blocks of data to NAND type flash memory 110, 110' and read
blocks of data from the NAND type flash memory 110, 110' without
regard for actual locations in the NAND type flash memory 110,
110'.
[0061] The actual physical address is the physical block address
(PBA) used internally by the NAND type flash memory 110, 110'.
Address indirection is typically implemented in the controller
portion of the memory device's architecture (e.g., NAND controller
120 of FIG. 1B) using indirection tables which are used to keep
track of the physical location associated with a LBA. Put another
way, the indirection tables map the LBA to a PBA in the NAND type
flash memory 110, 110'.
[0062] As described above, data are typically written to or read
from NAND type flash memory 110, 110' in blocks or sectors
contained in a set of memory locations within the NAND type flash
memory 102. The block sizes can be 512 bytes or 4000 bytes, in some
embodiments.
[0063] FIG. 3 is schematic of an indirection system of a storage
device 300, according to an example embodiment. More specifically,
FIG. 3 is a schematic diagram of the storage system 300
communicatively coupled to a host computer 310. The storage system
300 receives write commands from the host 310. The storage system
300 stores information representative of data in logical block
addresses (LBAs). The storage system 300 also retrieves information
or reads the data and delivers logical block addresses (LBAs) back
to the host 310.
[0064] As shown, the storage system 300 includes an indirection
system 320, a first memory device 330, and a second memory device
332. The indirection system 320 can map LBAs to one or more memory
devices, such as memory device 330 and 332. The first memory device
330 and the second memory device 332 can be a NAND flash 110, 110',
or a general memory device, such as device 200. The host system 310
can be a processor, an independent computer system, a server
system, or other hardware component that communicates with the
storage device 300.
[0065] Indirection controller 320 includes processor 307, memory
communicatively coupled to the processor 307, and computer readable
medium 309. Processor 307 may be a programmable logic controller
(PLC), micro-processor or micro-controller. Computer readable
medium 309 can be separate from the memory devices 330, 332 or can
refer to space reserved within memory devices 330, 332 for storing
data structures and/or instructions for execution by processor
307.
[0066] In direction controller 320 provides a dynamic translation
layer between logical block addresses (LBAs) utilized by host
system and physical blocks addresses (PBAs) used to access data
stored in the solid state device 330, 332. The "physical block
address" corresponds to an actual memory location or a plurality of
actual memory locations within the memory devices: no, 332. The
indirection controller 320 manages the assignment of LBAs to
PBAs.
[0067] In a some storage systems, mapping LBAs to PBAs remains
relatively static because individual memory cells may be re-written
very infrequently. In more complex architectures, the mapping
between LBAs and PBAs can change with every write operation because
the system dynamically determines the physical location (i.e., PBA)
assigned a particular logical location (i.e., LBA). The data for
the same LBA will be written to a different location the next time
the host LBA is updated. In this way, indirection controller 320
provides a dynamic translation layer between LBAs provided by host
system 310 and PBAs associated with memory devices 330, 332.
Indirection controller 320 is responsible for managing the
assignment of LBAs to the plurality of PBAs.
[0068] In order to keep data in memory devices 330, 332 secure,
many times the data are encrypted using a key or other parameter.
As long as the key or other parameter stays the same, the data are
secure. The key or other parameter is used to encrypt the data
before writing the data to the memory device 330, 332. The key or
other parameter is also used to decrypt the information as read
from the memory device 330, 332 to decode the information and
transform it back to the data as written.
[0069] Problems occur when the key or other parameter is changed
from the key or other parameter as written. If a key or other
parameter used to write the data is changed, decoding or decrypting
the information will not result in the data as written. In fact,
meaningless or "garbage" data are returned. This can trigger many
time consuming processes such as error recovery procedures which
may slow the responsiveness of the storage system 300. It is not
desirable to have slow response times. Rather than trigger these
procedures that may degrade the performance of the storage system
300, the storage system 300 is provided with a method of returning
a more desirable response. These are described below. These avoid
"garbage" data and produce a response as though no data or
information was present.
[0070] This disclosure now describes ways to generate a reading of
zero content from memory devices that have been previously written
with a different writing parameter. One writing parameter that
could be changed is a key which is generally used to write the
information representing data. Rather than read back "garbage" data
or information, an indication of zero content is generated. For
example, zero content may be indicated by a reading of all "1s" or
all "0s" for a block or set of blocks of data. The generation of
zero content is accomplished as the data are read while keeping the
security measures in place. As mentioned above, this is a
requirement for many devices as manufacturers do not want to expose
the data.
[0071] FIG. 4 is one type of table 400 associated with an
indirection controller 320 of a memory system 300, according to an
example embodiment. The table 400 is stored in memory 109 of the
indirection controller 300. The table 400 includes a logical block
address 410, a physical block address 420, a number of blocks 430,
and an encryption scheme 440. The number of blocks is the length of
the string of logical block addresses or physical block addresses.
For example, the logical block address 11111 start said physical
block address 11211 and is eight blocks long. The encryption scheme
is designated by a "1."
[0072] The table 400 is a map of the logical block addresses to the
physical block addresses within the memory devices 330, 332.
Logical block address 3 has a starting address "SSD 1" which
corresponds to a solid-state device, such as SSD 332 shown in FIG.
3. The table 400 includes a number of pointers. A pointer is a
variable that contains the memory location (address) of some data
rather than the data itself In other words, the physical block
address 420 for each of the blocks of data could be termed a
pointer as it is the address of the beginning of the block of data,
whether it is within the first memory device 330 or the second
memory device 332.
[0073] There are several methods for returning "zeroes" from data
that has been written with an old or another encryption scheme. The
several methods will be discussed with respect to the tables, such
as table 400, and other tables introduced below.
[0074] FIG. 5 is a method 500 for returning "zeroes" from data
written with a different or old encryption scheme, according to an
example embodiment. The method 500 includes monitoring the memory
or storage device for a change in the encryption/decryption scheme
used to read and write the data 510. Monitoring the storage device
for the change in the encryption/decryption scheme includes
monitoring column 440 of the table 400. Column 440 provides an
indication of the encryption scheme used.
[0075] As shown in FIG. 4, the encryption scheme used for logical
block addresses 1 and 2 is depicted by a value of "1" in column 440
of the table 400. This is a different or an old encryption scheme
in this example embodiment. The encryption scheme used for logical
block addresses 3 and 4 is depicted by a value of "2". This is a
new encryption scheme which is different from the encryption scheme
used to write the data associated with logical block addresses 1
and 2.
[0076] The method 500 includes returning an indication of being
written in zeroes for at least one logical block address when the
physical block address associated with the logical block address
has been encrypted using an old encryption/decryption scheme 512.
In this case, the value "1" in column 440 indicates that an old
encryption scheme was used for logical block addresses 1 and 2. The
new encryption scheme or changed or different encryption scheme is
depicted by a value of "2" in column 440 of table 4. The current
encryption scheme is depicted by the value of "2". As a result, the
read channel will be provided with an input of all zeroes for the
data associated with logical block addresses 1 and 2 since the
indicated encryption scheme associated with that data has a value
of "1".
[0077] FIG. 6 is a method 600 for returning "zeroes" from data
written with a different or old encryption scheme, according to an
example embodiment. The method 600 includes monitoring the memory
device for a change in the encryption/decryption scheme used to
read and write the data 610. Monitoring the memory device for the
change in the encryption/decryption scheme includes monitoring
column 440 of the table 400, shown in FIG. 4.
[0078] Once it is determined that some of the data associated with
certain logical block addresses have been encrypted using an old or
different encryption scheme, zeroes are written to the physical
block address is previously encrypted using the old
encryption/decryption scheme 612. Therefore in FIG. 4, the data are
associated with logical block addresses 1 and 2 will be over
written or rewritten with zeroes.
[0079] More particularly physical block address 2 and the eight
physical block addresses associated with logical block address 1,
will be overwritten with zeroes. Similarly, physical block address
172 and the 21 physical block addresses associated with logical
block address 2 will also be overwritten with zeroes. Thus, at the
actual, physical memory locations indicated by the table 400, there
will be zeroes written to those data locations.
[0080] The method also includes reading the rewritten physical
block addresses that correspond to the associated logical block
addresses 614. In other words, the physical block addresses
associated with the logical block address will have zeroes written
thereto. When read, actual zeroes will be returned to the read
channel rather than garbage data. Again it should be noted that the
logical block addresses that are rewritten with zeroes are the ones
where an old or different encryption scheme is used, such as the
logical block addresses 1 and 2 as shown in FIG. 4. This assumes
that the encryption scheme 2 is the current encryption scheme.
[0081] FIG. 7 is another type of table 700 associated with an
indirection controller 300 of storage system 300, according to an
example embodiment. The table 700 includes columns for the logical
block addresses 710, the physical block addresses which correspond
to the logical block addresses 720, the number of blocks written
730, an indication of invalidity 734, and an indication of the
encryption scheme used 740.
[0082] As shown in FIG. 7, when an old or different encryption
scheme is used, the logical block address is flagged or indicated
as invalid as depicted by column 734 in table 700. The current
encryption scheme is depicted by the number 11211 and the old or
different encryption scheme is depicted by the number 11111 in
column 740 of table 700. In column 734, the first two entries that
correspond to logical block addresses 11111 and 11211 carry a value
of 1 which indicates that the data associated with those logical
block addresses is invalid. The remaining two entries for logical
block addresses "3" and "4" have a value of "0" which indicates
that these logical block addresses or the information representing
data in these logical block addresses was written with the current
encryption scheme.
[0083] FIG. 8 is a method 800 for returning "zeroes" from data
written with a different or old encryption scheme, according to an
example embodiment. The method 800 includes monitoring the storage
system, and specifically a memory device 330, 332, for a change in
the encryption/decryption scheme used to read and write the data
810. Monitoring the memory device for the change in the
encryption/decryption scheme includes monitoring column 740 of the
table 700, shown in FIG. 7. Setting the invalidity to a value of
"1" can also be termed as setting a flag with respect to the
logical block addresses "1" and "2".
[0084] A flag is a marker of some type used by computer processing
or interpreting information. A flag as a signal indicating the
existence or status of a particular condition. In this example
embodiment the particular big condition is that the data or
information representing data associated with a particular logical
block address was written with an encryption scheme that differs
from the current encryption scheme being used. This is indicated by
the value of one in the invalidity column 734 of the table 700.
[0085] The method 800 also includes associating at least one flag
with at least one physical block address that is associated with a
logical block address that indicates that the information
representing data at the associated physical block address is
written using an old encryption scheme. The read channel or the
controller that controls a read channel will not read the physical
block addresses of the invalid data and will return a reading of
all zeroes for further processing. In other words, zeroes will be
returned based on the indication of invalidity of the logical block
addresses. This prevents the return of garbage data from the
physical block addresses associated with the logical block
addresses.
[0086] FIG. 9 is yet another type of table 900 associated with an
indirection controller 300 of a storage device 300, according to an
example embodiment. In this particular embodiment, when it is
determined that the encryption scheme used does not match the
current encryption scheme, the physical block address for a
particular logical block address is removed. In other words, the
pointer which shows the starting physical block address is removed.
This is shown in table 900 in column 920.
[0087] More specifically, the physical block addresses indicating
the starting physical block address for logical block addresses
11111 and 11211 have been removed since the encryption scheme,
indicated by a value of 11111, is old or different from the current
encryption scheme. Without a physical block address for a starting
point, the memory device assumes that the logical block address
corresponding to the values of "1" and "2" are empty and therefore
will automatically return zeroes as read from the logical block
addresses.
[0088] FIG. 10 is a flow diagram of a method 1000 for preventing
the generation of garbage data, according to an example embodiment.
The method 1000 includes monitoring the storage apparatus or memory
device for a change in the encryption/decryption scheme used to
read and write the data 1010. Monitoring the storage apparatus for
the change in the encryption/decryption scheme 1010 includes
monitoring column 440 of the table 900, shown in FIG. 9.
[0089] The method also includes removing a pointer from the logical
block address to the physical block address upon an indication that
a new encryption/decryption scheme is being used to read the data
1012. In other words, the pointer associated with the information
representing data written with an old or different
encryption/decryption scheme will be removed so that the logical
block address appears empty. When no data are at a logical block
address, the read channel will return zeroes to indicate that there
is no data present. In this way, the reading of garbage data is
prevented once again.
[0090] A memory device including at least one memory location for
storing information representing data written using a first
encryption/decryption method, and a read channel using a second
encryption/decryption method for reading and decrypting information
as written.
[0091] The memory device also includes an apparatus that prevents
the reading of the at least one memory location using the second
encryption/decryption method, in response to an indication that the
at least one memory location was written using the first
encryption/decryption method.
[0092] The apparatus that prevents the reading of the at least one
physical block address includes a device for associating a flag
with the at least one memory location written using the first
encryption/decryption method.
[0093] The apparatus that prevents the reading of the at least one
physical block address also includes a device for returning zero
content for the at least one memory location written using the
first encryption/decryption method in response to an indication the
read channel uses a second encryption/decryption method.
[0094] The apparatus that prevents the reading of the at least one
memory location written with the first encryption/decryption
method, in one embodiment, includes a device for writing zeroes to
the at least one memory location written using the first
encryption/decryption method.
[0095] In one embodiment, the information representing data is in a
block and the at least one memory location is at least one physical
block address. In some embodiments, memory device also includes an
indirection system. The indirection system includes at least one
logical block address, and a database that maps the at least one
logical block address to the at least one physical block
address.
[0096] In an embodiment, the indirection system includes an
apparatus that makes the mapping of the at least one logical block
address to the at least one physical address inaccessible in
response to the read channel using a second encryption/decryption
method when the at least one physical block address is written
using the first encryption/decryption method. The second
encryption/decryption method differs from the first
encryption/decryption method. A second encryption parameter
associated with the second encryption/decryption method differs
from a first encryption parameter associated with the first
encryption/decryption method.
[0097] In another example embodiment, a second encryption range
parameter associated with the second encryption/decryption method
differs from a first encryption range parameter associated with the
first encryption/decryption method. In still other embodiments, a
second encryption key parameter of the second encryption/decryption
method differs from a first encryption key parameter of the first
encryption/decryption method.
[0098] A storage apparatus includes a solid state device having a
plurality of memory locations, a write channel for writing
information representing data to the plurality of memory locations
in a solid state device, and a read channel for reading information
representing data from the plurality of memory locations in a solid
state device.
[0099] The storage apparatus also includes a controller that
controls operations of the storage apparatus including the writing
of information to the plurality of memory locations in a solid
state device and the reading of information representing data from
the plurality of memory locations in a solid state device.
[0100] The storage apparatus also includes an indirection system
further including a set of logical block addresses, and a set of
physical block addresses that correspond to the plurality of memory
locations in the solid state device of the storage apparatus.
[0101] The indirection system also includes a map that associates a
logical block addresses to at least one physical block address. The
map also includes at least one flag indicating an
encryption/decryption method used to write and read data from the
physical block address. The controller returns a reading of zeroes
when the encryption/decryption method used to read the physical
block address has changed.
[0102] In one example embodiment, the controller causes the
physical block address to be written with zeroes in response to a
change in the encryption/decryption method. In another example
embodiment, the controller returns all zeroes in response to an
indication of to a change in the encryption/decryption method. In
still another embodiment, the controller removes a pointer in the
map between the logical block address and the physical block
address in response to an indication of to a change in the
encryption/decryption method.
[0103] In yet another embodiment, the controller generates a flag
indicating information at a physical block address is invalid in
response to an indication of to a change in the
encryption/decryption method. The controller controls the writing
of information to the solid state device and the reading of
information representing data from the solid state device.
[0104] The indirection system includes a set of physical block
addresses that correspond to actual memory locations of the solid
state device. The map for associating logical block addresses to at
least one actual memory locations of the solid state device also
includes at least one flag indicating an encryption/decryption
method used to write and read data from the actual memory locations
of the solid state device. When the flag is set, the controller
returns a reading of zeroes when the encryption/decryption method
used to read the actual memory locations of the solid state device
has changed.
[0105] A method for decreasing the generation of garbage data in a
storage apparatus includes monitoring a storage apparatus for a
change in an encryption/decryption scheme used to read and write
data, and in response to the change in encryption/decryption
scheme, causing at least one logical block address to return an
indication of being written in zeroes when the physical block
address associated with the logical block address had been
encrypted using the old encryption/decryption scheme.
[0106] In one embodiment, the physical block address previously
encrypted using the old encryption/decryption scheme is written as
zeroes using the new encryption/decryption scheme. In another
embodiment, a pointer from the logical block address to the
physical block address is removed upon an indication that a new
encryption/decryption scheme is being used to read data. This
produces an all zeros type reading and prevents the generation of
garbage data.
[0107] In still another embodiment, there are a plurality of
logical block addresses that are associated with a plurality of
physical block addresses written to with an old
encryption/decryption scheme. The pointers for the plurality of
logical block addresses are removed to the plurality of physical
block addresses previously written with an old
encryption/decryption scheme.
[0108] In still another embodiment, the plurality of logical block
addresses mapped to the physical block addresses in a map. The map
further includes at least one flag indicating that information
representing data at a logical block address is invalid when the
information representing data written to the physical block address
associated with the logical block address is written using an old
encryption scheme.
[0109] In one or more examples, the functions described can be
implemented in hardware, software, firmware, or any combination
thereof. If implemented in software, the functions can be stored on
or transmitted over, as one or more instructions or code, a
computer-readable medium and executed by a hardware-based
processing unit. Computer-readable media can include
computer-readable storage media, which corresponds to a tangible
medium such as data storage media, or communication media including
any medium that facilitates transfer of a computer program from one
place to another, e.g., according to a communication protocol.
[0110] In this manner, computer-readable media generally can
correspond to (1) tangible computer-readable storage media which is
non-transitory or (2) a communication medium such as a signal or
carrier wave. Data storage media can be any available media that
can be accessed by one or more computers or one or more processors
to retrieve instructions, code and/or data structures for
implementation of the techniques described in this disclosure. A
computer program product can include a computer-readable
medium.
[0111] By way of example, and not limitation, such
computer-readable storage media can comprise RAM, ROM, EEPROM,
CD-ROM or other optical disk storage, magnetic disk storage, or
other magnetic storage devices, flash memory, or any other medium
that can be used to store desired program code in the form of
instructions or data structures and that can be accessed by a
computer. Also, any connection is properly termed a
computer-readable medium.
[0112] For example, if instructions are transmitted from a website,
server, or other remote source using a coaxial cable, fiber optic
cable, twisted pair, digital subscriber line (DSL), or wireless
technologies such as infrared, radio, and microwave, then the
coaxial cable, fiber optic cable, twisted pair, DSL, or wireless
technologies such as infrared, radio, and microwave are included in
the definition of medium.
[0113] It should be understood, however, that computer-readable
storage media and data storage media do not include connections,
carrier waves, signals, or other transient media, but are instead
directed to non-transient, tangible storage media. Disk and disc,
as used herein, includes compact disc (CD), laser disc, optical
disc, digital versatile disc (DVD), floppy disk and Blu-ray disc,
where disks usually reproduce data magnetically, while discs
reproduce data optically with lasers. Combinations of the above
should also be included within the scope of computer-readable
media.
[0114] Instructions can be executed by one or more processors, such
as one or more digital signal processors (DSPs), general purpose
microprocessors, application specific integrated circuits (ASICs),
field programmable logic arrays (FPGAs), or other equivalent
integrated or discrete logic circuitry. Accordingly, the term
"processor," as used herein can refer to any of the foregoing
structure or any other structure suitable for implementation of the
techniques described herein. Also, the techniques could be fully
implemented in one or more circuits or logic elements.
[0115] The techniques of this disclosure can be implemented in a
wide variety of devices or apparatuses, including a wireless
handset, an integrated circuit (IC) or a set of ICs (e.g., a chip
set). Various components, modules, or units are described in this
disclosure to emphasize functional aspects of devices configured to
perform the disclosed techniques, but do not necessarily require
realization by different hardware units. Rather, as described
above, various units can be combined in a hardware unit or provided
by a collection of interoperative hardware units, including one or
more processors as described above, in conjunction with suitable
software and/or firmware.
[0116] The foregoing description, for purposes of explanation, used
specific nomenclature to provide a thorough understanding of the
invention. However, it will be apparent to one skilled in the art
that the specific details are not required in order to practice the
invention. Thus, the foregoing descriptions of specific embodiments
of the present invention are presented for purposes of illustration
and description. They are not intended to be exhaustive or to limit
the invention to the precise forms disclosed. It will be apparent
to one of ordinary skill in the art that many modifications and
variations are possible in view of the above teachings.
[0117] The embodiments were chosen and described in order to best
explain the principles of the invention and its practical
applications, to thereby enable others skilled in the art to best
utilize the invention and various embodiments with various
modifications as are suited to the particular use contemplated. It
is intended that the scope of the invention be defined by the
following claims and their equivalents.
[0118] While the embodiments have been described in terms of
several particular embodiments, there are alterations,
permutations, and equivalents, which fall within the scope of these
general concepts. It should also be noted that there are many
alternative ways of implementing the methods and apparatuses of the
present embodiments. It is therefore intended that the following
appended claims be interpreted as including all such alterations,
permutations, and equivalents as fall within the true spirit and
scope of the described embodiments. These and other example
embodiments are within the scope of the following claims.
* * * * *