U.S. patent application number 16/353122 was filed with the patent office on 2020-09-17 for charge pump with load driving clock frequency management.
This patent application is currently assigned to STMicroelectronics Design and Application S.R.O.. The applicant listed for this patent is STMicroelectronics Design and Application S.R.O.. Invention is credited to Sandor PETENYI.
Application Number | 20200295767 16/353122 |
Document ID | / |
Family ID | 1000003989229 |
Filed Date | 2020-09-17 |
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United States Patent
Application |
20200295767 |
Kind Code |
A1 |
PETENYI; Sandor |
September 17, 2020 |
CHARGE PUMP WITH LOAD DRIVING CLOCK FREQUENCY MANAGEMENT
Abstract
A charge pump circuit has load driven clock frequency
management. The charge pump circuit includes a CCO generating a CCO
output signal that has a frequency generally proportional to a
feedback current, and a charge pump operated by the CCO output
signal and boosting a supply voltage to produce a charge pump
output voltage at an output coupled to a load. A current sensing
circuit senses a load current drawn by the load and generates the
feedback current as having a magnitude that varies as a function of
the sensed load current if a magnitude of the load current is
between a lower load current threshold and an upper load current
threshold. The magnitude of the feedback current does not vary with
the sensed load current if the magnitude of the sensed load current
is not between the lower load current threshold and the upper load
current threshold.
Inventors: |
PETENYI; Sandor; (Lysa nad
Labem (CZ), CZ) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STMicroelectronics Design and Application S.R.O. |
Prague |
|
CZ |
|
|
Assignee: |
STMicroelectronics Design and
Application S.R.O.
Prague
CZ
|
Family ID: |
1000003989229 |
Appl. No.: |
16/353122 |
Filed: |
March 14, 2019 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03L 7/0891 20130101;
G11C 5/145 20130101; G11C 11/4074 20130101; H02M 3/33507
20130101 |
International
Class: |
H03L 7/089 20060101
H03L007/089; G11C 5/14 20060101 G11C005/14; G11C 11/4074 20060101
G11C011/4074; H02M 3/335 20060101 H02M003/335 |
Claims
1. A circuit, comprising: a current controlled oscillator (CCO)
configured to generate a CCO output signal at a CCO output, the CCO
output signal having a frequency that is generally proportional to
a feedback current; a charge pump circuit operated by the CCO
output signal and configured to boost a supply voltage to produce a
charge pump output voltage at a charge pump output node associated
with an output coupled to a load; and a current sensing circuit
configured to sense a load current drawn by the load and to
generate the feedback current having a magnitude that varies as a
function of the sensed load current if a magnitude of the sensed
load current is between a lower load current threshold and an upper
load current threshold wherein the current sensing circuit
comprises: a first resistor directly electrically connected between
the charge pump output node and the output a diode coupled
transistor directly electrically connected in series between the
charge pump output node and the output and a transistor having a
source directly electrically connected to the charge pump output
node and a drain directly electrically connected to the CCO.
2. The circuit of claim 1, wherein the current sensing circuit
generates the feedback current as not having a magnitude that
varies as a function of the sensed load current if the magnitude of
the sensed load current is not between the lower load current
threshold and the upper load current threshold.
3. (canceled)
4. The circuit of claim 1, wherein the drain of the transistor is
directly electrically connected to the CCO in an unbroken fashion
without intervening components such that the feedback current flows
directly from the output into the CCO.
5. (canceled)
6. (canceled)
7. The circuit of claim 1, wherein the current sensing circuit
generates the feedback current as generally constant if the sensed
load current is below the lower load current threshold.
8. The circuit of claim 1, wherein the current sensing circuit
generates the feedback current as asymptotically rising if the
sensed load current is above the upper load current threshold.
9. The circuit of claim 1, wherein the load is a gate of a power
transistor and the charge pump output voltage serves to charge the
gate of the power transistor; and wherein the frequency of the CCO
output signal being proportional to the feedback current serves to
reduce the frequency of the CCO output signal once the power
transistor is in a linear mode of operation.
10. The circuit of claim 1, wherein the charge pump circuit
comprises: first, second, and third capacitors; first and second
inverters coupled in series between the CCO output and a first
plate of the first capacitor; a third inverter coupled between the
CCO output and a first plate of the second capacitor; and a bridge
rectifier comprising: a first diode having an anode coupled to a
first node and a cathode coupled to a second node, wherein the
second node is the charge pump output node; a second diode having a
cathode coupled to the first node and an anode coupled to a third
node; a third diode having an anode coupled to the third node and a
cathode coupled to a fourth node; and a fourth diode having an
anode coupled to the fourth node and a cathode coupled to the
second node; wherein a second plate of the first capacitor is
coupled to the first node; wherein a second plate of the second
capacitor is coupled to the fourth node; and wherein the third
capacitor has a first plate coupled to the supply voltage and the
third node and a second plate coupled to the output and the second
node.
11. (canceled)
12. The circuit of claim 1, wherein the CCO does not operate in a
pulse skipping mode.
13. (canceled)
14. (canceled)
15. (canceled)
16. (canceled)
17. A circuit, comprising: a current controller oscillator (CCO)
having a CCO input and a CCO output; a charge pump circuit
comprising: first, second, and third capacitors; first and second
inverters coupled in series between the CCO output and a first
plate of the first capacitor; a third inverter coupled between the
CCO output and a first plate of the second capacitor; and a bridge
rectifier comprising of: a first diode having an anode coupled to a
first node and a cathode coupled to a second node; a second diode
having a cathode coupled to the first node and an anode coupled to
a third node; a third diode having an anode coupled to the third
node and a cathode coupled to a fourth node; and a fourth diode
having an anode coupled to the fourth node and a cathode coupled to
the second node; wherein a second plate of the first capacitor is
coupled to the first node; wherein a second plate of the second
capacitor is coupled to the fourth node; and wherein the third
capacitor has a first plate coupled to a supply voltage and the
third node and a second plate coupled to the second node; and a
current sensing circuit comprising: a first resistor directly
electrically connected between the second node and an output; a
diode coupled transistor directly electrically connected in series
between the second node and the output; and a transistor having a
source directly electrically connected to the second node and a
drain directly electrically connected to the CCO input.
18. The circuit of claim 17, wherein the drain of the transistor is
directly electrically connected to the CCO in an unbroken fashion
without intervening components.
19-20. (canceled)
21. The circuit of claim 1, wherein the charge pump output voltage
is a voltage source for the load.
22. The circuit of claim 17, wherein the second node acts as a
voltage source for a load connected to the output.
Description
TECHNICAL FIELD
[0001] This application is directed to the field of charge pump
technology, and in particular, to a charge pump circuit utilizing a
load current as feedback to adjust an oscillator within the charge
pump circuit.
BACKGROUND
[0002] Charge pumps are routinely used in analog electronic
circuits to boost a voltage or invert a voltage without the use of
an inductor. A typical charge pump utilizes switched capacitors
operated by a clock signal generated by an oscillator. Such charge
pumps are effective at the goals of voltage boosting or voltage
inversion.
[0003] However, in some (or most) instances, the output of a charge
pump is provided to a variable load, meaning that the load draws
different amount of currents at different times. Since, as
explained, capacitors are used by a charge pump to provide a
boosted voltage, it should be appreciated that as current is
delivered by a charge pump, charge stored by those capacitors is
depleted. Therefore, when sufficient current is delivered by a
charge pump, the voltage output by the charge pump would fall.
Since the frequency of the oscillator used to operate the charge
pump in part determines the speed at which the capacitors are
recharged, it can be appreciated that in order to maintain the
voltage output by the charge pump at a consistent level despite the
current drawn by the load, the frequency at which the oscillator
operates must be sufficiently high.
[0004] One solution is to simply set the frequency of the
oscillator at a constant frequency sufficiently high such that in a
worst case operating scenario, the capacitors are recharged quickly
enough to maintain the voltage output by the charge pump at a
consistent level regardless of the current drawn by the load.
However, the drawback to this is that when the load is not drawing
much current, losses due to switching within the charge pump are
high.
[0005] Another solution is to operate the oscillator in a pulse
skipping mode where the oscillator is enabled when current at the
load is required and disabled otherwise. This can be sufficient in
reducing pump losses at times when the load is not drawing much
current. However, the drawback to this is that pulse skipping
introduces undesirable harmonics, which can be particularly
undesirable when a charge pump is used to drive a ballast
transistor as a power source.
[0006] As such, further development in the area of charge pump
technology is needed.
SUMMARY
[0007] Disclosed herein is a circuit including a current controller
oscillator (CCO) configured to generate a CCO output signal at a
CCO output that has a frequency that is generally proportional to a
feedback current. A charge pump circuit is operated by the CCO
output signal and configured to boost a supply voltage to produce a
charge pump output voltage at an output, and the output is coupled
to a load. A current sensing circuit is configured to sense load
current drawn by the load and to generate the feedback current as
having a magnitude that varies as a function of the sensed load
current if a magnitude of the load current is between a lower load
current threshold and an upper load current threshold. Note that
the current sensing circuit does not generate the feedback current
as having a magnitude that varies as a function of the sensed load
current if the magnitude of the sensed load current is not between
the lower load current threshold and the upper load current
threshold.
[0008] Also disclosed herein is a method embodiment. The method
involves boosting a supply voltage to a charge pump output voltage
provided to a load, using a charge pump operating based upon an
output signal from a current controlled oscillator (CCO). The
method also involves sensing a load current flowing into the load
as a result of the charge pump output voltage, and generating a
feedback current that is generally proportional to the load current
if a magnitude of the load current is between a lower load current
threshold and an upper load current threshold. The method
additionally involves adjusting a frequency of the output signal
from the CCO as a function of the feedback current. Note that the
frequency of the output signal is proportional to the feedback
current.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1A is a block diagram of an electronic device utilizing
a charge pump circuit to drive a load, in accordance with this
disclosure.
[0010] FIG. 1B is a schematic diagram of the electronic device of
FIG. 1A showing the details of the charge pump circuit.
[0011] FIG. 1C is a block diagram of an embodiment of electronic
device utilizing a charge pump circuit such as that of FIG. 1A-1B
to drive a ballast transistor, in accordance with this
disclosure.
[0012] FIG. 2A is a block diagram of an electronic device utilizing
another embodiment of charge pump circuit to drive a load, in
accordance with this disclosure.
[0013] FIG. 2B is a schematic diagram of the electronic device of
FIG. 2A showing the details of the charge pump circuit.
[0014] FIG. 2C is a schematic diagram of the electronic device of
FIG. 2A showing details of another embodiment of the charge pump
circuit.
[0015] FIG. 2D is a block diagram of an embodiment of an electronic
device utilizing a charge pump circuit such as that of FIGS. 2A-2C
to drive a ballast transistor, in accordance with this
disclosure.
[0016] FIG. 3 is a schematic diagram of a current controlled
oscillator such as may be used in FIGS. 1A-1C and 2A-2D.
[0017] FIG. 4 is a graph showing load current vs frequency of the
current controlled oscillator output signal for FIGS. 1A-1C, and
2A-2D.
[0018] FIG. 5 is a graph showing real feedback current
characteristics versus load current of charge pump circuit of FIG.
2C.
[0019] FIG. 6 is a graph showing load supply characteristics of the
charge pump circuit of FIG. 2C.
DETAILED DESCRIPTION
[0020] The following disclosure enables a person skilled in the art
to make and use the subject matter disclosed herein. The general
principles described herein may be applied to embodiments and
applications other than those detailed above without departing from
the spirit and scope of this disclosure. This disclosure is not
intended to be limited to the embodiments shown, but is to be
accorded the widest scope consistent with the principles and
features disclosed or suggested herein. Note that in this detailed
description section, where components are described as being
"coupled", it means that those components can be directly
electrically connected without intervening components, or connected
through other components.
[0021] First disclosed with reference to FIG. 1A is an electronic
device 50 including a charge pump circuit 100 to boost a supply
voltage VCC to a charge pump output voltage VHCP which is applied
to a load 60. The load 60 draws a load current ILOAD. A current
sensor 99 senses the load current ILOAD and generates a feedback
current IFBK that is representative of the load current ILOAD (for
example, having a magnitude that varies as a function of the load
current ILOAD, such as by being proportional to the load
current).
[0022] A current controller oscillator (CCO) 54 receives the
feedback current IFBK and generates a CCO output signal OUTcco that
has a frequency that is a function of the received feedback current
IFBK (for example, being nearly proportional to, proportional to,
directly proportional to, or in another relationship with).
Therefore, as the magnitude of the feedback current IFBK increases,
the frequency of the CCO output signal OUTcco increases.
[0023] In general, the charge pump 100 includes a driver and a
rectifier. The driver can be any switching circuit generating a
rectangular signal, and the rectifier can be any circuit
commutating in correct phases for delivering a pumped charge into
its output capacitance.
[0024] Further details of one example structure for the charge pump
100 of the electronic device 50 are shown in FIG. 1B, but it should
be understood that any charge pump meeting the general description
given above may be used. Here, inverters 51 and 55 receive the CCO
output signal OUTcco as input. The inverter 51 provides output to
inverter 53. Capacitor C1 couples the output of the inverter 53 to
node N1. Capacitor C2 couples the output of inverter 55 to node N4.
A capacitor C3 is coupled between a supply node VCC and node
N2.
[0025] A bridge rectifier is formed from diodes D1-D4. Diode D1 has
its anode coupled to node
[0026] N1 and its cathode coupled to node N2. Diode D2 has its
cathode coupled to node N1 and its anode coupled to node N3. Diode
D3 has its anode coupled to node N3 and its cathode coupled to node
N4. Diode D4 has its anode coupled to node N4 and its cathode
coupled to node N2.
[0027] Operation of the charge pump 100 will now be described. In
this description, assume that "high" refers to a voltage of VCC,
and that "low" refers to ground, although understand that in some
applications other values may be used. For ease of explanation of
the node and capacitor voltages, diode voltage drops will be
ignored, but understand that the actual voltage values will be less
than those stated due to voltage drops across the diodes D1-D4.
[0028] Consider a startup condition where neither C1 nor C2 are
charged, and assume the CCO output signal OUTcco is low. This
results in the output of the inverter 53 going low and the output
of the inverter 55 going high. Since the output of the inverter 53
is low and capacitor C1 is not yet charged, node N1 will go low,
diode D2 will become forward biased by VCC, and capacitor C1 will
charge to VCC. At this time, since the output of the inverter 55 is
high and the capacitor C2 is not yet charged, diode D3 will not
become forward biased, so capacitor C2 does not charge.
[0029] When the CCO output signal OUTcco transitions high, the
output of the inverter 53 will go high and the output of the
inverter 55 will go low. Since the output of the inverter 53 is
high, the potential at the output of the inverter 53 adds to
potential stored in the capacitor C1, meaning that the voltage at
node N1 will be 2*VCC. Since node N2 is at VCC, diode D1 will
become forward biased, and capacitors C1 and C3 will share charge,
with the result being that capacitor C3 will be charged to 1.5*VCC,
assuming the capacitances of C1 and C3 are equal. Also at this
time, since the output of the inverter 55 is low and capacitor C2
is not yet charged, node N4 will be low, the diode D3 will become
forward biased by VCC, and capacitor C2 will charge to VCC.
[0030] This operation repeats. Therefore, for example, when the CCO
output signal OUTcco transitions back low, the output of the
inverter 53 will go low and the output of the inverter 55 will go
high. Since the output of the inverter 55 is high, the potential at
the output of the inverter 55 adds to the potential stored in the
capacitor C2, meaning that the voltage at node N4 will be 2*VCC.
Since node N2 is at VCC, diode D4 will become forward biased, and
capacitors C2 and C3 will share charge, with the result being that
capacitor C3 will be charged to 1.75*VCC.
[0031] Ultimately, through this pumping that occurs during each
half cycle of the CCO output signal OUTcco, C3 will be charged to
approximately 2*VCC.
[0032] A potential use of this charge pump 100 and the frequency
regulation of its CCO 54 via the directly received feedback current
IFBK is shown in the electronic device 60 shown in FIG. 1C. The
electronic device 60 includes a charge pump 100 and CCO 54 that
operate as described above. Here, the output VCHP of the charge
pump 100 is used to bias the gate of a ballast NMOS transistor
(power NMOS transistor) T1, which in turn provides an output OUT
for use in powering other components (not shown). The ballast
transistor T1 has its drain coupled to VCC and provides the output
OUT at its source. The electronic device 60 also includes a pull
down NMOS transistor T2 having its drain coupled to the gate of the
ballast NMOS transistor T1, its source coupled to ground, and its
gate biased by a pull down signal PULL DOWN. In addition, a soft
start control circuit 52 is coupled to ground through capacitor C2
and provides bias to the ballast transistor T1 during startup when
the charge pump 100 is charging up its output.
[0033] The advantages of the charge pump 100 and CCO 54 arrangement
become readily apparent in the context of the electronic device 60.
Once the gate of the ballast transistor T1 is sufficiently charged
to place the ballast transistor T1 into a linear mode of operation,
little to no current is drawn by the ballast transistor T1 from the
charge pump 100. If the frequency of the CCO output signal OUTcco
were constant, high switching losses within the charge pump 100
would increase the quiescent current consumed. However, using the
arrangement shown where the feedback current IFBK controls the
frequency of the CCO output signal OUTcco, the magnitude of the
feedback current IFBK would be low once the gate of the ballast
transistor T1 is sufficiently charged. This would result in the
frequency of the CCO output signal OUTcco lowering, reducing
switching losses, and therefore reducing power consumption of the
electronic device 60. Indeed, the frequency of the CCO output
signal OUTcco may go as low as (or in some cases lower than) 100
kHz in this instance, reducing switching losses by as much as sixty
times. Where the magnitude of the feedback current IFBK is high to
indicate that a high current is flowing into the gate of the
ballast transistor T1, the frequency of the CCO output signal
OUTcco may go as high as (or in some cases higher than) 6 MHz,
maintaining VCHP at a constant level despite the high current
draw.
[0034] Now disclosed with reference to FIG. 2A is an electronic
device 70 including a charge pump circuit 100 to boost a supply
voltage VCC to a charge pump output voltage VHCP which is applied
to a load 60. The load 60 draws a load current ILOAD. A current
sensor 56 senses the load current ILOAD and generates a feedback
current IFBK that has a magnitude that is generally constant where
the load current ILOAD is below a lower load current threshold,
generally constant or asymptotically rising where the load current
ILOAD is above an upper load current threshold, and related to (for
example, being nearly proportional to, proportional to, directly
proportional to, or in another relationship with) the load current
ILOAD where the load current ILOAD is between the lower and upper
load current thresholds.
[0035] Therefore, as can be seen in the graph of FIG. 4, the
frequency of the CCO output signal OUTcco will be generally
constant at a lower frequency threshold where the load current
ILOAD is below a lower load current threshold, generally constant
at or asymptotically rising to an upper frequency threshold where
the load current ILOAD is above an upper load current threshold,
and related to (for example, being nearly proportional to,
proportional to, directly proportional to, or in another
relationship with) the load current ILOAD where the load current
ILOAD is between the lower and upper load current thresholds. As
can be seen in FIG. 4, the frequency of the CCO output signal rises
generally (but not perfectly) linearly where the load current ILOAD
is between the lower and upper load current thresholds. The goal of
the control of the frequency of the CCO output signal is to
maintain lowest possible output impedance of the charge pump 100 in
all load conditions, keeping in mind the reduction of switching
losses.
[0036] The purpose of this described generation of the feedback
current IFBK by the current sensor 56 is to maintain the frequency
of the CCO output signal OUTcco at a minimum nonzero threshold
where the load current ILOAD is below the lower load current
threshold to maintain VCHP at a generally constant level, to permit
the frequency of the CCO output signal OUTcco to rise as the load
current ILOAD rises to maintain VCHP at a generally constant level
despite the increasing load current ILOAD, yet to protect the
components of the charge pump 100 or current sensor 56 from damage
if the load current ILOAD rises above the upper load current
threshold.
[0037] Further details of the current sensor 56 of the electronic
device 70 are shown in FIG. 2B. Here, the CCO 54 and charge pump
100 are as described above with respect to FIG. 1B. The current
sensor 56 includes a current sensing resistor R1 coupled between
node N2 and the load 60. A PMOS transistor DCT has its source
coupled to node N2, its drain coupled to the load 60, and its gate
coupled to its drain. A PMOS transistor MP has its source coupled
to node N2, its drain directly electrically connected to CCO 54
without intervening components, and its gate coupled to the gate
and drain of the PMOS transistor DCT.
[0038] In operation, the PMOS transistors MP and DCT form a current
mirror, with the drain of DCT forming the input of the current
mirror and the drain of MP forming the output of the current
mirror. Therefore, IFBK is a mirrored version of ILOAD, meaning
that the frequency of the CCO output signal OUTcco will be related
to the load current ILOAD. The current sensing performed by the
current sensor 56 would function without the resistor R1, but the
result would be a drop of 1*VGS on DCT. To overcome this drawback
and to allow a higher VCHP in an unloaded state, the resistor R1 is
utilized. Resistor R1 does not contribute to the current sensing,
but instead is used to allow VOUT to reach VCHP in a completely
unloaded state (where the gate of DCT is fully charged). The value
of R1 can be high, such as 1 M.OMEGA., whereas the native output
impedance of the charge pump 100 at its maximum operating frequency
can be 10 .OMEGA..
[0039] Therefore, until the voltage across R1 reaches the proper
VGS to turn on DCT (prior to which current sensing is not
functional), the output impedance of the charge pump 100 will be 1
M.OMEGA.. Once the voltage across R1 reaches the proper VGS to turn
on DCT to begin current sensing, the output impedance drops and the
CCO 54 begins tracking IFBK (and thus, ILOAD).
[0040] Put more simply, until the voltage drop across the resistor
R1 is the required VGS of DCT, the current sensor 56 provides
little to no current, meaning that DCT is in an off condition or in
a subthreshold region. In this mode, the charge pump 100 runs at
its minimum frequency. The benefit of this design of the current
sensor 56 is that in an unloaded state, it draws no current from
node N2, therefore allowing VCHP to be at its maximum possible
value.
[0041] Another embodiment of the current sensor 56' of the
electronic device 70' is shown in FIG. 2C. Here, the CCO 54 and
charge pump 100 are as described above with respect to FIG. 2B. The
current sensor 56' includes a current sensing resistor R2 coupled
between node N2 and the load 60. A diode D is coupled between node
N2 and the load 60. A resistor R3 is coupled between node N2 and a
source of PMOS transistor MP1. A drain of PMOS transistor MP1
produces the feedback current IFBK and is directly electrically
connected to the CCO 54 without any intervening components. A PMOS
transistor MP2 has its source coupled to the load 60, its drain
coupled to current source 57, and its gate coupled to its drain and
to the gate of PMOS transistor MP1.
[0042] In operation, if the load current ILOAD is zero, then the
source voltages of PMOS transistors MP1 and MP2 will be equal, and
the PMOS transistors MP1 and MP2 will act as a current mirror,
resulting in the reference current IREF (e.g. 100 nA) being
mirrored to the drain of PMOS transistor MP1 as the feedback
current IFBK. The minimum magnitude that IFBK will reach will be
below the minimum current defined inside the CCO 54. Therefore, the
minimum frequency of OUTcco will be precisely defined inside the
CCO 54. Once IFBK becomes higher than the minimum current inside
the CCO 54, the frequency of OUTcco becomes a function of IFBK.
[0043] If the load current ILOAD is nonzero, but the voltage across
resistor R2 (resulting from the load current ILOAD flowing through
R2) is insufficient to forward bias the diode D, then the source
voltages of PMOS transistors MP1 and MP2 will be unequal, and
current mirror operation will unbalanced. In this condition, the
load current ILOAD will control biasing of the PMOS transistor MP1,
and the feedback current IFBK will be related to (for example,
being nearly proportional to, proportional to, directly
proportional to, or in another relationship with) the load current
ILOAD.
[0044] Once the voltage across resistor R2 becomes sufficient to
forward bias the diode D, the diode D will clamp the resistor R2,
lowering the output impedance of the charge pump 54 under high load
conditions. Prior to diode D becoming forward biased, the CCO 54
outputs OUTcco at its maximum output frequency. Also in this case,
the maximum frequency of OUTcco will be defined inside the CCO, not
by IFBK from the current sensor 56.
[0045] Note that in the design of FIG. 2C, the load current ILOAD
does not pass through MP2, but instead passes through R2 and at
higher current also passes through diode D. The current source IREF
is used for pre-biasing the current mirror formed by PMOS
transistors MP1 and MP2, resulting in a small magnitude of the
feedback current IFBK in an unloaded state. However, IFBK in this
state is not to be used for setting the minimum frequency of
OUTcco, but instead the minimum frequency of OUTcco is set directly
in the CCO 54 itself.
[0046] Therefore, a primary advantage of the design of FIG. 2C is
that current sensing starts from very low load current ILOAD
magnitude levels, because the current sensing is based on AVGS of
PMOS transistors MP2 and MP1. The current sensing functions until
the voltage drop on R2 saturates at the forward voltage of diode D.
At this point, the CCO 54 is already outputting OUTcco at its
maximum frequency. The diode D helps to guarantee minimum output
impedance in heavily loaded state. Note, however, that with this
design, some current from the charge pump 100 is consumed in an
unloaded state.
[0047] A potential use of this charge pump 100 and the frequency
regulation of its CCO 54 via the feedback current IFBK is shown in
the electronic device 80 of FIG. 2D. The electronic device 80
includes a charge pump 100 and CCO 54 that operate as described
above. Here, the output VCHP of the charge pump 100 is used to bias
the gate of a ballast NMOS transistor (power NMOS transistor) T1,
which in turn provides an output OUT for use in powering other
components (not shown). The ballast transistor T1 has its drain
coupled to VCC and provides the output OUT at its source. The
electronic device 60 also includes a pull down NMOS transistor T2
having its drain coupled to the gate of the ballast NMOS transistor
T2, its source coupled to ground, and its gate biased by a pull
down signal PULL DOWN. In addition, a soft start control circuit 52
is coupled to ground through capacitor C2 and provides bias to the
ballast transistor T1 during startup when the charge pump 100 is
charging up its output.
[0048] The advantages of the charge pump 100 and CCO 54 arrangement
become readily apparent in the context of the electronic device 80.
Once the gate of the ballast transistor T1 is sufficiently charged
to place the ballast transistor T1 into a linear mode of operation,
little to no current is drawn by the ballast transistor T1 from the
charge pump 100. If the frequency of the CCO output signal OUTcco
were constant, high switching losses within the charge pump 100
would increase the quiescent current consumed. However, using the
arrangement shown, the feedback current IFBK would be low once the
gate of the ballast transistor T1 is sufficiently charged, with the
result being that the frequency of the CCO output signal OUTcco
would lower, reducing switching losses, and therefore reduce power
consumption of the electronic device 60. Indeed, the frequency of
the CCO output signal OUTcco may go as low as (or in some cases
lower than) 100 kHz in this instance, reducing switching losses by
as much as sixty times. Where the feedback current IFBK is high to
indicate that a high current is flowing into the gate of the
ballast transistor T1, the frequency of the CCO output signal
OUTcco may go as high as (or in some cases higher than) 6 MHz,
maintaining VCHP at a constant level despite the high current
draw.
[0049] Shown in FIG. 5 is feedback current IFBK vs. load current
ILOAD for the charge pump circuit of FIG. 2C. As can be seen, the
feedback current IFBK is relatively proportional to the load
current ILOAD until saturation of the current sensor 56' occurs, at
which point the feedback current IFBK rises asymptotically toward a
maximum current.
[0050] Shown in FIG. 6 is a graph showing output voltage VOUT vs
load current ILOAD for the charge pump circuit 100 of FIG. 2C.
[0051] Now described with reference to FIG. 3 is a sample CCO 54
such as may be used with the devices shown in FIGS. 1A-1C, and
2A-2D. A detailed description will be given below, but first a
brief description will be given. Briefly, the structure of the CCO
54 is a low power oscillator that has been designed as 2-phase
structure for achieving minimum switching losses. Timing of one
clock phase is defined by components M2, C4, M6 and M3 and the
timing of the other clock phase is defined by components M4, C5, M7
and M5. Devices M8 and M9 are used for resetting the capacitors.
This CCO structure generates a symmetric square wave signal with
approximately a 50:50 ratio between pulse and gap (depending on the
matching of components between first and second phase).
[0052] In greater detail, the CCO 54 includes PMOS transistors
M1-M5 coupled in a current mirror arrangement. The sources of PMOS
transistors M1-M5 are coupled to VCC, and the gates of PMOS
transistors M1-M5 are coupled to one another and to the drain of
PMOS transistor M1.
[0053] A first current source 91 draws a maximum CCO current IMAX
from the drain of PMOS transistor M1, and a second current source
92 draws a minimum CCO current IMIN from the drain of PMOS
transistor M1. A current mirror is formed from NMOS transistors M10
and M11. The drain of M11 is coupled to the current source 91, the
source of M11 is coupled to ground, and the gate of M11 is coupled
to the gate and drain of M10. The drain of M10 is coupled to
receive IFBK and to the gate of M10, and the source of M10 is
coupled to ground.
[0054] A capacitor C4 is coupled between the drain of PMOS
transistor M2 and ground. An NMOS transistor M6 has its gate
coupled to the drain of PMOS transistor M2, its drain coupled to
the drain of PMOS transistor M3, and its source coupled to ground.
A capacitor C5 is coupled between the drain of PMOS transistor M4
and ground. An NMOS transistor M7 has its drain coupled to the
drain of PMOS transistor M5, its source coupled to ground, and its
gate coupled to the drain of PMOS transistor M4.
[0055] A buffer 81 has its input coupled to the drain of PMOS
transistor M5 and has its output coupled to a first input of NAND
gate 85. A buffer 83 has its input coupled to the drain of PMOS
transistor M3 and has its output coupled to a first input of NAND
gate 87. The output of NAND gate 85 is coupled to the second input
of NAND gate 87, and the output of NAND gate 87 is coupled to the
second input of NAND Gate 85, thereby forming an SR flip flop. An
NMOS transistor M8 has its drain coupled to the drain of PMOS
transistor M2, its source coupled to ground, and its gate coupled
to the output of NAND gate 87. An NMOS transistor M9 has its drain
coupled to the drain of PMOS transistor M4, its source coupled to
ground, and its gate coupled to the output of NAND gate 85. The CCO
output signal OUTcco is produced at the output of NAND gate 85.
[0056] The feedback current IFBK is received by the current mirror
formed from NMOS transistors M10 and M11. If IFBK is zero, then the
bias current for M1 is defined by the current IMIN drawn from the
current source 92, setting for example a frequency for OUTcco to
100 kHz. If the feedback current IFBK is higher than the current
IMAX drawn from the current source 91, then the bias current for M1
is the sum of the currents IMIN drawn from the current source 92
and IMAX, setting for example a frequency for OUTcco to 6 MHz
because the drain current of M11 is limited by the current source
91. If the feedback current IFBK is between IMAX and IMIN, then the
bias current for M1 is proportional to IFBK.
[0057] To understand operation, assume an operating state where the
output of buffer 81 is high and the output of buffer 83 is low. The
output of the buffer 83 being low results in the output of the NAND
gate 87 being high, which means that the output of NAND gate 85
(and thus the CCO output signal OUTcco) will be low. The output of
NAND gate 85 being low while the output of buffer 83 is low serves
to maintain the output of NAND gate 87 high, and thus the output of
NAND gate 85 is stable at this point.
[0058] The output of NAND gate 87 being high turns on transistor
M8, so at this point capacitor C4 does not charge. The output of
NAND gate 85 being low turns off NMOS transistor M9, so capacitor
C5 will be charged by PMOS transistor M4. Therefore, once capacitor
C5 is sufficiently charged to turn on transistor M7, current will
be sunk from the input of buffer 81, and the output of buffer 81
will go low, pulling the output of NAND gate 85 (and thus the CCO
output signal OUTcco) high, turning on transistor M9 and
discharging capacitor C5.
[0059] NAND gate 85 still being high at this point will cause the
output of the NAND gate 87 to go low, which will turn off
transistor M8, and capacitor C4 will begin to be charged by PMOS
transistor M2. Once capacitor C4 is sufficiently charged to turn on
transistor M6, current will be sunk from the input of the buffer
83, the output of the buffer 83 will go low, the output of the NAND
gate 87 will go high, and the initial condition described above is
returned to. This operation continues cycling, generating CCO
output signal OUTcco as having a frequency dependent on the time it
takes for capacitors C4 and C5 to charge. The quicker capacitors C4
and C5 charge, the higher the frequency of the CCO output signal
OUTcco will be; the slower capacitors C4 and C5 charge, the lower
the frequency of the CCO output signal OUTcco will be.
[0060] Since the charging time for capacitors C4 and C5 is
proportional to the magnitude of the bias current for M1 (such as
feedback current IFBK in some operating conditions as explained
above), this means that the frequency of the CCO output signal
OUTcco will be proportional to the magnitude of the feedback
current IFBK.
[0061] The current source 91 is formed by NMOS transistor M13 which
has its drain coupled to the drain of PMOS transistor M1, its
source coupled to the drain of NMOS transistor M11, and its gate
coupled to the gate of M12. The current source 92 is formed by NMOS
transistor M14 which has its drain coupled to the drain of PMOS
transistor M1, its source coupled to ground, and its gate coupled
to the gates of NMOS transistors M13 and M12. NMOS transistor M12
has its drain coupled to current source 93 to receive a constant
current, its source coupled to ground, and its gate coupled to the
gates of NMOS transistors M13 and M14.
[0062] This is but one CCO 54 design that may be used with the
devices shown in FIGS. 1A-1C, and 2A-2D. It should be appreciated
that other CCO designs may also be suitable.
[0063] It should be understood that the operation of the CCO 54
based upon the received feedback signal IFBK is not pulse skipping
and cannot be considered to be a pulse skipping mode. Although the
frequency of the CCO output signal OUTcco varies, it does not skip
pulses as understood by those of skill in the art, and the pulses
of the CCO output signal OUTcco instead are continuously
generated.
[0064] While the disclosure has been described with respect to a
limited number of embodiments, those skilled in the art, having
benefit of this disclosure, will appreciate that other embodiments
can be envisioned that do not depart from the scope of the
disclosure as disclosed herein. Accordingly, the scope of the
disclosure shall be limited only by the attached claims.
* * * * *