U.S. patent application number 16/854250 was filed with the patent office on 2020-08-06 for high frequency amplifier apparatuses.
The applicant listed for this patent is TRUMPF Huettinger GmbH + Co. KG. Invention is credited to Alexander Alt, Andre Grede, Daniel Gruner, Anton Labanc.
Application Number | 20200251309 16/854250 |
Document ID | / |
Family ID | 1000004767974 |
Filed Date | 2020-08-06 |
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United States Patent
Application |
20200251309 |
Kind Code |
A1 |
Grede; Andre ; et
al. |
August 6, 2020 |
HIGH FREQUENCY AMPLIFIER APPARATUSES
Abstract
The invention relates to high-frequency amplifier apparatuses
suitable for generating power outputs of at least 1 kW at
frequencies of at least 2 MHz. The apparatuses include two LDMOS
transistors each connected by their source connection to ground.
The transistors can have the same design and can be arranged in an
assembly (package). The apparatus also includes a circuit board
lying against a cooling plate, which can be connected to ground,
and the assembly is arranged on or against the circuit board. The
apparatuses have a power transformer, whose primary winding is
connected to the drain connections of the transistors, and a signal
transmitter. A secondary winding of the signal transmitter can be
connected to the gate connections of the two transistors. Each of
the gate connections can be connected to ground via at least one
voltage-limiting structural element.
Inventors: |
Grede; Andre; (Bern, CH)
; Alt; Alexander; (Freiburg, DE) ; Gruner;
Daniel; (Muellheim, DE) ; Labanc; Anton;
(Ehrenkirchen, DE) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TRUMPF Huettinger GmbH + Co. KG |
Freiburg |
|
DE |
|
|
Family ID: |
1000004767974 |
Appl. No.: |
16/854250 |
Filed: |
April 21, 2020 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15854163 |
Dec 26, 2017 |
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16854250 |
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PCT/EP2016/065376 |
Jun 30, 2016 |
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15854163 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03F 3/3001 20130101;
H03F 2200/451 20130101; H03F 3/193 20130101; H01J 37/32174
20130101 |
International
Class: |
H01J 37/32 20060101
H01J037/32; H03F 3/30 20060101 H03F003/30; H03F 3/193 20060101
H03F003/193 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 30, 2015 |
DE |
102015212247.6 |
Claims
1. A high-frequency amplifier apparatus suitable for generating
power for plasma excitation, the apparatus comprising: two
Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors
each having a drain terminal and a source terminal that is
connected to a ground connection point, wherein the LDMOS
transistors are embodied alike and are arranged as a package; a
circuit board that lies on a metal cooling plate, wherein the
package is arranged on the circuit board; a power transformer
including a primary winding connected to the drain terminals of the
two LDMOS transistors; and a signal transformer including a
secondary winding having a first end and a second end, wherein the
secondary winding is connected at the first end to a first gate
terminal of one of the two LDMOS transistors by one or more first
resistive elements, and the secondary winding is connected at the
second end to a second gate terminal of the other of the two LDMOS
transistors by one or more second resistive elements, wherein each
of the first gate terminal and second gate terminal is connected to
ground by one or more voltage-limiters, and wherein at least one of
the voltage-limiters comprises at least one diode.
2. The apparatus of claim 1, wherein the at least one diode has a
cathode and an anode, wherein the cathode is arranged on a gate
side and the anode is arranged on a ground side, wherein the gate
side includes the first gate terminal and the second gate terminal,
and the ground side includes at least one of the ground
connections.
3. The apparatus of claim 1, wherein at least one of the
voltage-limiters comprises a plurality of diodes connected in
series.
4. The apparatus of claim 3, wherein the plurality of diodes
comprise at least two diodes of different types.
5. The apparatus of claim 3, wherein at least one of the plurality
of diodes has a reverse recovery time that is less than a quarter
of a cycle duration of a driving frequency of the two LDMOS
transistors.
6. The apparatus of claim 1, wherein the at least one diode is
connected to one resistor in series.
7. The apparatus of claim 1, wherein the first gate terminal and
the second gate terminal are connected by one or more resistors to
a DC voltage source.
8. The apparatus of claim 7, wherein the one or more resistors are
connected to a common capacitor.
9. The apparatus of claim 8, wherein the common capacitor is
connected to the DC voltage source, and is configured to discharge
a gate capacitance.
10. The apparatus of claim 1, wherein the power transformer is
arranged on the circuit board and the primary winding is formed in
a planar manner on the circuit board.
11. The apparatus of claim 1, wherein the package has terminals
that are contacted on the circuit board.
12. A high-frequency amplifier apparatus suitable for generating
power for plasma excitation, the apparatus comprising: two
Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors
each having a drain terminal and a source terminal that is
connected to a ground connection point, wherein the LDMOS
transistors are embodied alike and are arranged as a package; a
circuit board that lies on a cooling plate, wherein the package is
arranged on the circuit board; a power transformer including a
primary winding connected to the drain terminals of the two LDMOS
transistors; and a signal transformer including a secondary winding
having a first end and a second end, wherein the secondary winding
is connected at the first end to a first gate terminal of one of
the two LDMOS transistors by one or more first resistive elements,
and the secondary winding is connected at the second end to a
second gate terminal of the other of the two LDMOS transistors by
one or more second resistive elements, wherein each of the first
gate terminal and second gate terminal is connected to ground by
one or more voltage-limiters, and wherein the package is arranged
on a substrate, in a housing, or both in a housing and on a
substrate.
13. The apparatus of claim 12, wherein the housing of the package
is arranged in a cut-out in the circuit board.
14. The apparatus of claim 13, wherein the package is mounted on a
copper plate, and the copper plate and the package are arranged in
the cut-out in the circuit board.
15. The apparatus of claim 14, wherein the cut-out is stepped to be
matched to surfaces of the copper plate and the package.
16. The apparatus of claim 12, wherein the substrate includes a
copper plate, and the package is mounted on the copper plate.
17. The apparatus of claim 16, wherein the copper plate has a
surface on which the package is mounted, wherein the surface is
larger than a surface of the package that faces the cooling
plate.
18. A high-frequency amplifier apparatus suitable for generating
power for plasma excitation, the apparatus comprising: two
Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors
each having a drain terminal and a source terminal that is
connected to a ground connection point, wherein the LDMOS
transistors are embodied alike and are arranged as a package; a
circuit board that lies on a cooling plate, wherein the package is
arranged on the circuit board; a power transformer including a
primary winding connected to the drain terminals of the two LDMOS
transistors; and a signal transformer including a secondary winding
having a first end and a second end, wherein the secondary winding
is connected at the first end to a first gate terminal of one of
the two LDMOS transistors by one or more first resistive elements,
and the secondary winding is connected at the second end to a
second gate terminal of the other of the two LDMOS transistors by
one or more second resistive elements; and wherein each of the
first gate terminal and second gate terminal is connected to ground
by one or more voltage-limiters, and wherein the circuit board is a
multi-layered circuit board.
19. The apparatus of claim 18, wherein the circuit board has at
least one inner layer.
20. The apparatus of claim 18, wherein the circuit board has four
total layers.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a division of and claims priority under
35 U.S.C. .sctn. 120 from U.S. application Ser. No. 15/854,163,
filed on Dec. 26, 2017, which is a continuation of PCT Application
No. PCT/EP2016/065376, filed on Jun. 30, 2016, which claims
priority from German Application No. DE 10 2015 212 247.6, filed on
Jun. 30, 2015. The entire contents of each of these priority
applications are incorporated herein by reference.
TECHNICAL FIELD
[0002] The invention relates to high-frequency amplifiers that are
suitable for generating output power of at least 1 kW (kilowatt) at
frequencies of at least 2 MHz (Megahertz) for plasma
excitation.
BACKGROUND
[0003] Devices of this type or similar devices are known for
example from the following documents: US 2014/0167858 A1, US
2009/0027936 A1, U.S. Pat. Nos. 6,172,383 B1, 6,064,249 A.
[0004] Laterally Diffused Metal Oxide Semiconductor (LDMOS)
transistors are known, for example, from the following documents:
Freescale Semiconductor, Technical Data, RF Power LDMOS
Transistors, Document Number: MRFE6VP61K25H Rev. 4.1, 3/2014.
[0005] It is known to use transistors, such as LDMOS transistors,
to generate high frequency power, for example power that is
suitable for exciting a plasma. Transistors of this type are often
intended for operation in amplifier class AB. However, if the
transistors are to be used for other amplifier classes, e.g., class
E or class F, it is often not possible to drive the transistors
fully without exceeding the specifications of the manufacturer with
regard to gate voltage. However, exceeding in this way can lead to
the transistors failing and/or having a shorter service life.
SUMMARY
[0006] The present disclosure provides high-frequency amplifier
apparatuses to prevent the above-mentioned disadvantages. These
high-frequency amplifier apparatuses are suitable for generating
output power of at least 1 kW (kilowatt) at frequencies of at least
2 MHz (Megahertz), for example, for plasma excitation. Each of
these apparatuses includes two LDMOS transistors, which are each
connected to a ground connection point by their respective source
terminals. The LDMOS transistors can be embodied alike. The two
transistors are arranged in a package. The apparatus also includes
a circuit board, which lies on a metal cooling plate, which can be
connected to ground, by a plurality of ground connections. The
package is arranged on the circuit board. The apparatus has a power
transformer, the primary winding of which is connected to the drain
terminals of the LDMOS transistors. The apparatus also has a signal
transformer, the secondary winding of which is connected at a first
end to the gate terminal of one LDMOS transistor by one or more
resistive elements, and is connected at a second end to the gate
terminal of the other LDMOS transistor by one or more resistive
elements. Each gate terminal is connected to ground by at least one
voltage-limiter.
[0007] Therefore, the LDMOS transistors can be driven fully without
exceeding the permitted gate voltage. Because voltage-limiters are
provided, the negative peak of a driving signal, which comes from
the secondary winding of the signal transformer, receives the
ground potential. Therefore, the negative voltage is limited to the
voltage drop at the voltage-limiter and the positive peak voltage
is increased. Accordingly, less driving power is necessary for
drivers that actuate the LDMOS transistors. Additionally, the
conduction angle, i.e., the time during which one or both
transistors conduct during a cycle of the driving signal, is
increased without the need to increase the peak voltage over a
permitted value. In other words, the time in which a transistor is
driven can be extended. Furthermore, because a higher DC voltage is
achieved, the input signal is (in relative terms) more frequently
above the threshold voltage Vth of the transistors; thus, the
transistors are more frequently conductive.
[0008] Because of the connection of the two LDMOS transistors to
the cooling plate, thermal loading of the LDMOS transistors can
also be reduced, and, as a result, the likelihood of transistor
failure is further reduced.
[0009] Furthermore, the ground connection point can be configured
to transfer heat from the LDMOS transistors to the cooling plate.
Accordingly, an even better dissipation of heat from the LDMOS
transistors is ensured, and thermal loading of the LDMOS
transistors is further reduced.
[0010] In some implementations, at least one voltage-limiter
includes at least one diode, the cathode of which is arranged on
the gate side and the anode of which is arranged on the ground
side. As a result of this measure, the negative peak of the driving
signal receives the ground potential through the conducting diode.
The negative voltage of the driving signal is therefore limited to
the voltage drop at the diode.
[0011] In some implementations, at least one voltage-limiter
includes a plurality of diodes connected in series. This measure
makes it possible to counteract a disadvantage that arises when the
amplifier is operated in saturation, which causes the gate bias
voltage to further increase and consequently the drain current also
further increases, which leads to decreasing the efficiency. In
some examples, a plurality of fast diodes can be connected in
series. A fast diode within the meaning of the invention is a diode
that has a reverse recovery time of less than a quarter of the
cycle duration. At a driving frequency of the transistors of, e.g.,
40.68 MHz (i.e., a cycle duration of approximately 25 ns), a
quarter of the cycle duration is approximately 6 ns. In this
example, the diodes should therefore have a reverse recovery time
of 6 ns or less. Thus, a fast diode conducts only negligibly
briefly in the reverse direction and blocks only negligibly briefly
in the forward direction.
[0012] The series connection of diodes can include at least two
diodes of different types. For example, the series connection can
include a fast diode and a Z-diode.
[0013] In some implementations, at least one voltage-limiter
includes at least one diode and one resistor, connected in series.
This also can reduce the above-mentioned disadvantages. In some
implementations, the high-frequency amplifier apparatus is
symmetrical, i.e., the two LDMOS transistors have identical
component arrangements.
[0014] In some implementations, the package is arranged on the
circuit board. The package can therefore be cooled via the circuit
board, which is connected to the cooling plate in a heat-conducting
manner. The package can be arranged on a substrate. The package may
be arranged in a housing. The housing of the package can be
arranged in a cut-out in the circuit board. The terminals of the
package can be contacted on the circuit board. The package can be
mounted on a copper plate for the purpose of cooling. The copper
plate can be used for transferring heat from the package to the
cooling plate, for example, for heat distribution. The copper plate
can be arranged in the same cut-out in the circuit board as the
package. The copper plate can have a larger surface area than the
surface of the package that faces the cooling plate. The cut-out
can be stepped, so as to be matched to (e.g., be aligned with) the
surfaces of the copper plate and the package. This can additionally
increase the service life of the transistors, as they may not heat
up to the same extent. In addition, an apparatus that is close to
the cooling plate connected to ground can better suppress
interference that may occur due to high currents during switching
processes.
[0015] The circuit board can be a multi-layered circuit board, for
example, a multi-layered circuit board having at least one inner
layer, or a multi-layered circuit board having at least two, three,
or four layers. An outer layer may be entirely connected to ground
for direct installation and contact with the cooling plate, which
is also connected to ground.
[0016] In some implementations, the power transformer is arranged
on the circuit board or on a separate circuit board. In some
examples, the primary winding is formed in a planar manner on the
relevant circuit board. This results in a particularly
cost-effective construction of the primary winding. The power
transformer can also be easily cooled.
[0017] A gate terminal may be connected, by a resistor, to a
capacitor connected to ground. The gate capacitance can be
discharged through these parts and an operating point voltage
source. In some examples, the resistor has a resistance value of
less than 1 k.OMEGA. (kilo ohm) and the capacitor has a capacitance
of more than 1 nF (nanofarad).
[0018] In some implementations, the resistors are connected to a
common capacitor, which in turn may be connected to the operating
point voltage source.
[0019] Additional features and advantages of the invention can be
found in the following detailed description of embodiments of the
invention, with reference to the figures of the drawings, and in
the claims. The features shown therein are not necessarily to
scale. The different features may each be implemented in isolation
or together in any desired combinations in variants of the
invention.
[0020] Embodiments of the invention are shown in the schematic
drawings and are explained in detail in the following
description.
DESCRIPTION OF DRAWINGS
[0021] FIG. 1 is a schematic circuit diagram that shows a first
embodiment of a high-frequency amplifier apparatus, according to an
embodiment of the invention.
[0022] FIG. 2 is a schematic circuit diagram that shows a second
embodiment of a high-frequency amplifier apparatus, according to an
embodiment of the invention.
[0023] FIG. 3 is a graph that shows two different voltage curves to
illustrate the effect of an embodiment of the invention on a
driving voltage.
DETAILED DESCRIPTION
[0024] FIG. 1 shows a first embodiment of a high-frequency
amplifier apparatus 1. The high-frequency amplifier apparatus 1
includes a circuit board 2, on which a package 3 is arranged. The
package 3 includes two LDMOS transistors S1, S2, which are embodied
alike and are each connected to a ground connection point 5 by
their respective source terminals. The LDMOS transistors S1, S2 are
each connected by their respective drain terminals to an end of a
primary winding 6 of a power transformer 7. The secondary winding 4
of the power transformer 7 is connected to ground 8 and to a
high-frequency output 9. The high-frequency amplifier apparatus 1
further includes a signal transformer 10, which includes a primary
winding 11 that is connected to a high-frequency input 12. The
secondary winding 13 of the signal transformer 10 is connected to
the gate terminal 15 of the LDMOS transistor S1 by a resistive
element 14, for example, a resistor. The secondary winding 13 is
also connected to the gate terminal 17 of the LDMOS transistor S2
by a resistive element 16, for example, a resistor. The resistive
elements 14, 16 and the secondary winding 13 are thus connected in
series. The signal transformer 10 is also arranged on the circuit
board 2, as is the power transformer 7.
[0025] The gate terminal 15 is connected to earth 19 by a
voltage-limiter 18, which is formed as a diode in this case. In
this case, the cathode of the diode is arranged on the gate side
and the anode is arranged on the ground side. Correspondingly, the
gate terminal 17 is also connected to earth 21 by a voltage-limiter
20, which is also formed as a diode in this case. This arrangement
makes it possible for the control signals of the gate terminals 15,
17 to be voltage-shifted (amplitude-shifted).
[0026] The gate terminals 15, 17 are additionally connected, by
means of resistors 22, 23, to a DC voltage source 24, i.e., an
operating point voltage source. A driving circuit for generating
the driving signals of the LDMOS transistors S1, S2 thus includes,
in the embodiment in FIG. 1, the high-frequency input 12, the
signal transformer 10, the resistive elements 14, 16, the
voltage-limiters 18, 20, the resistors 22, 23 and the DC voltage
source 24.
[0027] The circuit board 2 lies flat on a cooling plate 25, which
can also be connected to ground 26. For example, the circuit board
2 is connected to the cooling plate 25 by a plurality of ground
connections 8, 19, 21, 27. The ground connection 5 is a ground
connection point for transferring heat from the LDMOS transistors
S1, S2 to the cooling plate 25.
[0028] FIG. 2 shows an alternative embodiment of a high-frequency
amplifier apparatus 1', in which the components that correspond to
those in FIG. 1 have the same reference signs. One difference of
the high-frequency amplifier apparatus 1' from the apparatus 1 is
that the voltage-limiter 18' in this case includes two diodes
connected in series. The voltage-limiter 20' is designed
correspondingly.
[0029] A further difference is that the resistors 22, 23 are
connected to a capacitor 30 that is in turn connected to ground 27.
A DC voltage source (operating point voltage source) is connected
to the terminal 31.
[0030] FIG. 3 shows a plurality of voltage curves over time, as
they are applied to the gate terminals 15, 17 as driving signals.
The voltage curve 100 is applied to the gate terminal 15 if no
voltage-limiter 18 or 18' is available. The voltage curve 101 is
applied correspondingly to the gate terminal 17 if no
voltage-limiter 20 or 20' is available. The effect of the
voltage-limiters 18, 18', 20, 20' is visible in the voltage curves
102, 103, where the negative peak of the voltage curves 102, 103 is
limited approximately to the voltage of the voltage-limiter 18,
18', 20, 20', for example, to the voltage drop at one or more
diodes. Overall, the voltage of the voltage curves 102, 103, which
are applied to the gate terminals 15, 17, is shifted to higher
voltage values when a voltage-limiter 18, 18', 20, 20' is used. In
other words, the positive peak voltage is increased and the
negative peak of the driving signals of the gate terminals 15, 17
is limited to the voltage drop, for example at the diodes, of the
voltage-limiter 18, 18', 20, 20'. As a result, a lower driving
power, i.e. power of the high frequency signal at the
high-frequency input 12, is required. A lower gate voltage leads to
a reduction in the risk of failure of the LDMOS transistors S1,
S2.
OTHER EMBODIMENTS
[0031] It is to be understood that while the invention has been
described in conjunction with the detailed description thereof, the
foregoing description is intended to illustrate and not limit the
scope of the invention, which is defined by the scope of the
appended claims. Other aspects, advantages, and modifications are
within the scope of the following claims.
* * * * *