U.S. patent application number 16/732921 was filed with the patent office on 2020-07-23 for filter bank multicarrier communication system based on discrete hartley transform.
This patent application is currently assigned to National Tsing Hua University. The applicant listed for this patent is National Tsing Hua University. Invention is credited to Hong-Shiuann PAN, Chin-Liang WANG.
Application Number | 20200235973 16/732921 |
Document ID | / |
Family ID | 71609315 |
Filed Date | 2020-07-23 |
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United States Patent
Application |
20200235973 |
Kind Code |
A1 |
WANG; Chin-Liang ; et
al. |
July 23, 2020 |
FILTER BANK MULTICARRIER COMMUNICATION SYSTEM BASED ON DISCRETE
HARTLEY TRANSFORM
Abstract
A filter bank multicarrier communication system is proposed. The
system adopts the real-valued discrete Hartley transform for both
multicarrier modulation and demodulation, rather than the
complex-valued inverse discrete Fourier transform for multicarrier
modulation and the discrete Fourier transform for multicarrier
demodulation in conventional filter bank multicarrier schemes, so
as to reduce implementation complexity and to enhance system
performance.
Inventors: |
WANG; Chin-Liang; (Hsinchu
City, TW) ; PAN; Hong-Shiuann; (Tainan City,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
National Tsing Hua University |
Hsinchu City |
|
TW |
|
|
Assignee: |
National Tsing Hua
University
Hsinchu City
TW
|
Family ID: |
71609315 |
Appl. No.: |
16/732921 |
Filed: |
January 2, 2020 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H04L 27/264 20130101;
H04L 27/2697 20130101; H04L 27/2649 20130101 |
International
Class: |
H04L 27/26 20060101
H04L027/26 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 18, 2019 |
TW |
108101960 |
Claims
1. A transmitter of a filter bank multicarrier communication system
based on a discrete Hartley transform (DHT), said transmitter
comprising: a serial-to-parallel conversion unit configured to
perform serial-to-parallel conversion on M complex input data
symbols, which are inputted thereto in series and each of which
includes a real part and an imaginary part, and to output M real
parts and M imaginary parts of the complex input data symbols in
parallel, where M is a positive even integer; a first
pre-processing unit coupled to the serial-to-parallel conversion
unit for receiving the M real parts of the complex input data
symbols, and configured to generate M pre-processed real-part
components based on a pre-processing model and the M real parts of
the complex input data symbols; a second pre-processing unit
coupled to the serial-to-parallel conversion unit for receiving the
M imaginary parts of the complex input data symbols, and configured
to generate M pre-processed imaginary-part components based on the
pre-processing model and the M imaginary parts of the complex input
data symbols; a first data separator coupled to the first
pre-processing unit for receiving the M pre-processed real-part
components, and configured to separate the M pre-processed
real-part components into M/2 even-numbered pre-processed real-part
components and M/2 odd-numbered pre-processed real-part components;
a second data separator coupled to the second pre-processing unit
for receiving the M pre-processed imaginary-part components, and
configured to separate the M pre-processed imaginary-part
components into M/2 even-numbered pre-processed imaginary-part
components and M/2 odd-numbered pre-processed imaginary-part
components; a first synthesis filter bank coupled to the first data
separator for receiving the M/2 even-numbered pre-processed
real-part components and the M/2 odd-numbered pre-processed
real-part components, and configured to generate a first-channel
transmitted (Tx) baseband signal of M points by performing at least
up-sampling, filtering, inverse discrete Hartley transform (IDHT),
data combination, and parallel-to-serial conversion on
pre-processed real-part components, the pre-processed real-part
components consisting of the M/2 even-numbered pre-processed
real-part components and the M/2 odd-numbered pre-processed
real-part components; and a second synthesis filter bank coupled to
the second data separator for receiving the M/2 even-numbered
pre-processed imaginary-part components and the M/2 odd-numbered
pre-processed imaginary-part components, and configured to generate
a second-channel Tx baseband signal of M points by performing at
least up-sampling, filtering, IDHT, data combination, and
parallel-to-serial conversion on pre-processed imaginary-part
components, the pre-processed imaginary-part components consisting
of the M/2 even-numbered pre-processed imaginary-part components
and the M/2 odd-numbered pre-processed imaginary-part
components.
2. The transmitter of claim 1, wherein the first synthesis filter
bank includes: M/2 first up-sampling modules coupled to the first
data separator for respectively receiving the M/2 even-numbered
pre-processed real-part components, wherein each of the first
up-sampling modules is configured to perform up-sampling on the
respective one of the M/2 even-numbered pre-processed real-part
components; M/2 second up-sampling modules coupled to the first
data separator for respectively receiving the M/2 odd-numbered
pre-processed real-part components, wherein each of the second
up-sampling modules is configured to perform up-sampling on the
respective one of the M/2 odd-numbered pre-processed real-part
components; M/2 first prototype filters respectively coupled to the
M/2 first up-sampling modules for respectively receiving the M/2
even-numbered pre-processed real-part components that have been
up-sampled by the M/2 first up-sampling modules, wherein each of
the first prototype filters is configured to perform filtering on
the respective one of the M/2 even-numbered pre-processed real-part
components that has been up-sampled; M/2 second prototype filters
respectively coupled to the M/2 second up-sampling modules for
respectively receiving the M/2 odd-numbered pre-processed real-part
components that have been up-sampled by the M/2 second up-sampling
modules, wherein each of the second prototype filters is configured
to perform filtering on the respective one of the M/2 odd-numbered
pre-processed real-part components that has been up-sampled; a
first IDHT module coupled to the M/2 first prototype filters for
receiving the M/2 even-numbered pre-processed real-part components
that have been up-sampled by the first up-sampling modules and
filtered by the first prototype filters, and configured to generate
a first part of the first-channel Tx baseband signal by performing
M/2-point IDHTs on two sets of the M/2 even-numbered pre-processed
real-part components that have been up-sampled and filtered and
that are received consecutively by the first IDHT module; a second
IDHT module coupled to the M/2 second prototype filters for
receiving the M/2 odd-numbered pre-processed real-part components
that have been up-sampled by the second up-sampling modules and
filtered by the second prototype filters, and configured to
consecutively generate two serial second-IDHT results of M/2
points, where the M/2 points of each of the serial second-IDHT
results are outputted in series, by performing M/2-point IDHTs on
two sets of the M/2 odd-numbered pre-processed real-part components
that have been up-sampled and filtered and that are received
consecutively by the second IDHT module; a first serial-to-parallel
conversion module coupled to the second IDHT module for receiving
the two serial second-IDHT results of M/2 points, and configured to
consecutively output two parallel second-IDHT results of M/2
points, where the M/2 points of each of the parallel second-IDHT
results are outputted in parallel, by performing serial-to-parallel
conversion on each of the two serial second-IDHT results of M/2
points; and a first data combination and parallel-to-serial
conversion module coupled to the first serial-to-parallel
conversion module for receiving the two parallel second-IDHT
results of M/2 points, and configured to generate a second part of
the first-channel Tx baseband signal by, for each of the two
parallel second-IDHT results of M/2 points, performing data
combination on the parallel second-IDHT result of M/2 points to
obtain a data combination result, and performing parallel-to-serial
conversion on the data combination result for the parallel
second-IDHT result of M/2 points; and wherein the second synthesis
filter bank includes: M/2 third up-sampling modules coupled to the
second data separator for respectively receiving the M/2
even-numbered pre-processed imaginary-part components, wherein each
of the third up-sampling modules is configured to perform
up-sampling on the respective one of the M/2 even-numbered
pre-processed imaginary-part components received thereby; M/2
fourth up-sampling modules coupled to the second data separator for
respectively receiving the M/2 odd-numbered pre-processed
imaginary-part components, wherein each of the fourth up-sampling
modules is configured to perform up-sampling on the respective one
of the M/2 odd-numbered pre-processed imaginary-part components
received thereby; M/2 third prototype filters respectively coupled
to the M/2 third up-sampling modules for respectively receiving the
M/2 even-numbered pre-processed imaginary-part components that have
been up-sampled by the M/2 third up-sampling modules, wherein each
of the third prototype filters is configured to perform filtering
on the respective one of the M/2 even-numbered pre-processed
imaginary-part components received thereby; M/2 fourth prototype
filters respectively coupled to the M/2 fourth up-sampling modules
for respectively receiving the M/2 odd-numbered pre-processed
imaginary-part components that have been up-sampled by the M/2
fourth up-sampling modules, wherein each of the fourth prototype
filters is configured to perform filtering on the respective one of
the M/2 odd-numbered pre-processed imaginary-part components
received thereby; a third IDHT module coupled to the M/2 third
prototype filters for receiving the M/2 even-numbered pre-processed
imaginary-part components that have been up-sampled by the third
up-sampling modules and filtered by the third prototype filters,
and configured to generate a first part of the second-channel Tx
baseband signal by performing M/2-point IDHTs on two sets of the
M/2 even-numbered pre-processed imaginary-part components that have
been up-sampled and filtered and that are received consecutively by
the third IDHT module; a fourth IDHT module coupled to the M/2
fourth prototype filters for receiving the M/2 odd-numbered
pre-processed imaginary-part components that have been up-sampled
by the fourth up-sampling modules and filtered by the fourth
prototype filters, and configured to consecutively output two
serial fourth-IDHT results of M/2 points, where the M/2 points of
each of the serial fourth-IDHT results are outputted in series, by
performing M/2-point IDHTs on two sets of the M/2 odd-numbered
pre-processed imaginary-part components that have been up-sampled
and filtered and that are received consecutively by the fourth IDHT
module; a second serial-to-parallel conversion module coupled to
the fourth IDHT module for receiving the two serial fourth-IDHT
results of M/2 points, and configured to perform serial-to-parallel
conversion on each of the two serial fourth-IDHT results of M/2
points, and to consecutively output two parallel fourth-IDHT
results of M/2 points, wherein for each of the two parallel
fourth-IDHT results of M/2 points, the M/2 points of the parallel
fourth-IDHT result are outputted in parallel; and a second data
combination and parallel-to-serial conversion module coupled to the
second serial-to-parallel conversion module for receiving the two
parallel fourth-IDHT results of M/2 points, and configured to
generate a second part of the second-channel Tx baseband signal by,
for each of the two parallel fourth-IDHT results of M/2 points,
performing data combination on the parallel fourth-IDHT result of
M/2 points to obtain a data combination result, and performing
parallel-to-serial conversion on the data combination result for
the parallel fourth-IDHT result of M/2 points.
3. The transmitter of claim 2, wherein the first-channel Tx
baseband signal is represented by
s.sup.I[k]=s.sub.0.sup.I[k]+s.sub.1.sup.I[k], and the
second-channel Tx baseband signal is represented by
s.sup.Q[k]=s.sub.0.sup.Q[k]+s.sub.1.sup.Q[k], where k=0, 1, 2, 3, .
. . , M-1; wherein: s I [ k ] = n = - .infin. .infin. m = 0 M - 1 X
m , n I p m [ k - n M ] cas ( 2 .pi. m k M ) ; ##EQU00008## s 0 I [
k ] = .alpha. = 0 M / 2 - 1 ( n = - .infin. .infin. X 2 .alpha. , n
I p 0 [ k - n M ] ) c a s ( 2 .pi. k .alpha. M / 2 ) ;
##EQU00008.2## s 1 I [ k ] = .alpha. = 0 M / 2 - 1 ( n = - .infin.
.infin. X 2 .alpha. + 1 , n I p 1 [ k - n M ] ) cas ( 2 .pi.
.alpha. k M / 2 + 2 .pi. k M ) ; ##EQU00008.3## s Q [ k ] = n = -
.infin. .infin. m = 0 M - 1 X m , n Q p m [ k - n M ] cas ( 2 .pi.
m k M ) ; ##EQU00008.4## s 0 Q [ k ] = .alpha. = 0 M / 2 - 1 ( n =
- .infin. .infin. X 2 .alpha. , n Q p 0 [ k - n M ] ) cas ( 2 .pi.
k .alpha. M / 2 ) ; ##EQU00008.5## s 1 Q [ k ] = .alpha. = 0 M / 2
- 1 ( n = - .infin. .infin. X 2 .alpha. + 1 , n Q p 1 [ k - n M ] )
cas ( 2 .pi. .alpha. k M / 2 + 2 .pi. k M ) ; ##EQU00008.6## cas (
.phi. ) = cos ( .phi. ) + sin ( .phi. ) ; ##EQU00008.7##
s.sub.0.sup.I[k] and s.sub.1.sup.I[k] respectively represent the
first part and the second part of the first-channel Tx baseband
signal; s.sub.0.sup.Q[k] and s.sub.1.sup.Q[k] respectively
represent the first part and the second part of the second-channel
Tx baseband signal; X.sub.m,n.sup.I represents one of the M
pre-processed real-part components that is transmitted on an
m.sup.th one of subcarriers for the pre-processed real-part
components at a time point n; X.sub.m,n.sup.Q represents one of the
M pre-processed imaginary-part components that is transmitted on an
m.sup.th one of subcarriers for the pre-processed imaginary-part
components at a time point n; p.sub.2.alpha.[k]=p.sub.0[k], and
represents one of the M/2 first prototype filters and one of the
M/2 third prototype filters; p.sub.2.alpha.+1[k]=p.sub.1[k], and
represents one of the M/2 second prototype filters and one of the
M/2 fourth prototype filters;
Y.sub.0,.alpha..sup.I[k]=.SIGMA..sub.n=-.infin..sup..infin.X.sub.2.alpha.-
,n.sup.Ip.sub.0[k-nM] represents a result obtained by using one of
the M/2 first up-sampling modules to perform up-sampling on one of
the M/2 even-numbered pre-processed real-part components, which is
represented by X.sub.2.alpha.,n.sup.I, and then using one of the
M/2 first prototype filters p.sub.0[k] to perform filtering on
X.sub.2.alpha.,n.sup.I that has been up-sampled;
Y.sub.1,.alpha..sup.I[k]=.SIGMA..sub.n=-.infin..sup..infin.X.sub.2.alpha.-
+1,n.sup.Ip.sub.1[k-nM] represents a result obtained by using one
of the M/2 second up-sampling modules to perform up-sampling on one
of the M/2 odd-numbered pre-processed real-part components, which
is represented by X.sub.2.alpha.+1,n.sup.I, and then using one of
the M/2 second prototype filters p.sub.1[k] to perform filtering on
X.sub.2.alpha.+1,n.sup.I that has been up-sampled;
Y.sub.0,.alpha..sup.Q[k]=.SIGMA..sub.n=-.infin..sup..infin.X.sub.2.alpha.-
,n.sup.Qp.sub.0[k-nM] represents a result obtained by using one of
the M/2 third up-sampling modules to perform up-sampling on one of
the M/2 even-numbered pre-processed imaginary-part components,
which is represented by X.sub.2.alpha.,n.sup.Q, and then using one
of the M/2 third prototype filters p.sub.0[k] to perform filtering
on X.sub.n that has been up-sampled; and
Y.sub.1,.alpha..sup.Q[k]=.SIGMA..sub.n=-.infin..sup..infin.X.sub.2.alpha.-
+1,n.sup.Qp.sub.1[k-nM] represents a result obtained by using one
of the M/2 fourth up-sampling modules to perform up-sampling on one
of the M/2 odd-numbered pre-processed imaginary-part components,
which is represented by X.sub.2.alpha.+1,n.sup.Q, and then using
one of the M/2 fourth prototype filters p.sub.1[k] to perform
filtering on X.sub.2.alpha.+1,n.sup.Q, that has been
up-sampled.
4. The transmitter of claim 1, wherein the first synthesis filter
bank includes: a first IDHT module coupled to the first data
separator for receiving the M/2 even-numbered pre-processed
real-part components, and configured to generate a first-IDHT
result of M/2 points by performing an M/2-point IDHT on the M/2
even-numbered pre-processed real-part components; a second IDHT
module coupled to the first data separator for receiving the M/2
odd-numbered pre-processed real-part components, and configured to
generate a second-IDHT result of M/2 points by performing an
M/2-point IDHT on the M/2 odd-numbered pre-processed real-part
components; a first data combination module coupled to the second
IDHT module for receiving the second-IDHT result of M/2 points, and
configured to perform data combination on the second-IDHT result of
M/2 points; M/2 different first polyphase filters each coupled to
the first IDHT module for receiving a respective one of the M/2
points of the first-IDHT result, the first polyphase filters being
configured to respectively generate M/2 first filtered outputs,
wherein each of the first polyphase filters generates the
respective one of the first filtered outputs by sequentially
performing up-sampling and filtering on the respective one of the
M/2 points of the first-IDHT result received thereby; M/2 different
second polyphase filters each coupled to the first data combination
module for receiving a respective one of the M/2 points of the
second-IDHT result on which the data combination has been
performed, the second polyphase filters being configured to
respectively generate M/2 second filtered outputs, wherein each of
the second polyphase filters generates the respective one of the
second filtered outputs by sequentially performing up-sampling and
filtering on the respective one of the M/2 points of the
second-IDHT result received thereby; a first parallel-to-serial
conversion module coupled to the M/2 first polyphase filters for
receiving the M/2 first filtered outputs, and configured to
generate a first part of the first-channel Tx baseband signal by
sequentially performing up-sampling and parallel-to-serial
conversion on the M/2 first filtered outputs; and a second
parallel-to-serial conversion module coupled to the M/2 second
polyphase filters for receiving the M/2 second filtered outputs,
and configured to generate a second part of the first-channel Tx
baseband signal by sequentially performing up-sampling and
parallel-to-serial conversion on the M/2 second filtered outputs;
and wherein the second synthesis filter bank includes: a third IDHT
module coupled to the second data separator for receiving the M/2
even-numbered pre-processed imaginary-part components, and
configured to generate a third-IDHT result of M/2 points by
performing an M/2-point IDHT on the M/2 even-numbered pre-processed
imaginary-part components; a fourth IDHT module coupled to the
second data separator for receiving the M/2 odd-numbered
pre-processed imaginary-part components, and configured to generate
a fourth-IDHT result of M/2 points by performing an M/2-point IDHT
on the M/2 odd-numbered pre-processed imaginary-part components; a
second data combination module coupled to the fourth IDHT module
for receiving the fourth-IDHT result of M/2 points, and configured
to perform data combination on the fourth-IDHT result of M/2
points; M/2 different third polyphase filters each coupled to the
third IDHT module for receiving a respective one of the M/2 points
of the third-IDHT result, the third polyphase filters being
configured to respectively generate M/2 third filtered outputs,
wherein each of the third polyphase filters generates the
respective one of the third filtered outputs by sequentially
performing up-sampling and filtering on the respective one of the
M/2 points of the third-IDHT result received thereby; M/2 different
fourth polyphase filters each coupled to the second data
combination module for receiving a respective one of the M/2 points
of the fourth-IDHT result on which the data combination has been
performed, the fourth polyphase filters being configured to
respectively generate M/2 fourth filtered outputs, wherein each of
the fourth polyphase filters generates the respective one of the
fourth filtered outputs by sequentially performing up-sampling and
filtering on the respective one of the M/2 points of the
fourth-IDHT result received thereby; a third parallel-to-serial
conversion module coupled to the M/2 third polyphase filters for
receiving the M/2 third filtered outputs, and configured to
generate a first part of the second-channel Tx baseband signal by
sequentially performing up-sampling and parallel-to-serial
conversion on the M/2 third filtered outputs; and a fourth
parallel-to-serial conversion module coupled to the M/2 fourth
polyphase filters for receiving the M/2 fourth filtered outputs,
and configured to generate a second part of the second-channel Tx
baseband signal by sequentially performing up-sampling and
parallel-to-serial conversion on the M/2 fourth filtered
outputs.
5. The transmitter of claim 4, wherein the first synthesis filter
bank is equivalent to including: a first synthesis filter group of
M/2 synthesis filters respectively corresponding to M/2 subcarriers
for the M/2 even-numbered pre-processed real-part components, and
corresponding to the M/2 first polyphase filters; and a second
synthesis filter group of M/2 synthesis filters respectively
corresponding to M/2 subcarriers for the M/2 odd-numbered
pre-processed real-part components, and corresponding to the M/2
second polyphase filters; wherein the second synthesis filter bank
is equivalent to including: a third synthesis filter group of M/2
synthesis filters respectively corresponding to M/2 subcarriers for
the M/2 even-numbered pre-processed imaginary-part components, and
corresponding to the M/2 third polyphase filters; and a fourth
synthesis filter group of M/2 synthesis filters respectively
corresponding to M/2 subcarriers for the M/2 odd-numbered
pre-processed imaginary-part components, and corresponding to the
M/2 fourth polyphase filters; wherein, for each of the first and
second synthesis filter banks, one of the synthesis filters that
corresponds to a (2.alpha.+.beta.).sup.th one of the subcarriers is
represented by p.sub..beta.[k]cas(2.pi..alpha.k/(M/2)), where k=0,
1, 2, 3, . . . , L-1; wherein each of the first, second, third and
fourth synthesis filter groups has a system function
F.sub..beta.,.alpha.(z) that is obtained from a z-transform of
p.sub..beta.[k]cas(2.pi..alpha.k/(M/2)) and that is represented by
F.sub..beta.,.alpha.(z)=.SIGMA..sub.q=0.sup.M/2-1.psi..sub..alpha.,qP.sub-
..beta..sup.(q)(z.sup.M/2)z.sup.-q with .alpha..di-elect
cons.{0,1,2, . . . , M/2-1}, .beta..di-elect cons.{0,1} and
.psi..sub..alpha.,q=cas(2.pi..alpha.q/(M/2)) representing a kernel
function of an M/2-point IDHT;
P.sub..beta..sup.(q)(z.sup.M/2)=.SIGMA..sub.r=0.sup.2K-1p.sub..beta.[q+r(-
M/2)]z.sup.-r(M/2) represents a q.sup.th one of the first polyphase
filters for the first synthesis filter group with .beta.=0, a
q.sup.th one of the second polyphase filters for the second
synthesis filter group with .beta.=1, a q.sup.th one of the third
polyphase filters for the third synthesis filter group with
.beta.=0, and a q.sup.th one of the fourth polyphase filters for
the fourth synthesis filter group with .beta.=1; each of the first,
second, third and fourth polyphase filters has a length of 2K; and
cas(.PHI.)=cos(.PHI.)+sin(.PHI.).
6. A receiver of a filter bank multicarrier communication system
based on the discrete Hartley transform (DHT), said receiver
comprising: a first analysis filter bank disposed to consecutively
receive two serial first-channel received (Rx) baseband signals of
M/2 points, where M is a positive even integer, and the M/2 points
of each of the two serial first-channel Rx baseband signals are
received in series, and configured to generate a first part and a
second part of a filtered first-channel Rx baseband signal by
performing at least serial-to-parallel conversion, down-sampling,
filtering, data combination and DHT on the two serial first-channel
Rx baseband signals of M/2 points, wherein each of the first part
and the second part of the filtered first-channel Rx baseband
signal has M/2 components; a second analysis filter bank disposed
to consecutively receive two serial second-channel Rx baseband
signals of M/2 points, where the M/2 points of each of the two
serial second-channel Rx baseband signals are received in series,
and configured to generate a first part and a second part of a
filtered second-channel Rx baseband signal by performing at least
serial-to-parallel conversion, down-sampling, filtering, data
combination and DHT on the two serial second-channel Rx baseband
signals of M/2 points, wherein each of the first part and the
second part of the filtered second-channel Rx baseband signal has
M/2 components; a data detection unit coupled to the first analysis
filter bank and the second analysis filter bank, and configured to
generate M/2 first first-channel detection results corresponding to
the first part of the filtered first-channel baseband signal, M/2
first second-channel detection results corresponding to the first
part of the filtered second-channel Rx baseband signal, M/2 second
first-channel detection results corresponding to the second part of
the filtered first-channel Rx baseband signal, and M/2 second
second-channel detection results corresponding to the second part
of the filtered second-channel Rx baseband signal by performing
joint detection on the first part of the filtered first-channel Rx
baseband signal, the first part of the filtered second-channel Rx
baseband signal, the second part of the filtered first-channel Rx
baseband signal, and the second part of the filtered second-channel
Rx baseband signal; a first data combiner coupled to the data
detection unit, and configured to generate M first-channel
detection outcomes by combining the first first-channel detection
results and the second first-channel detection results; a second
data combiner coupled to the data detection unit, and configured to
generate M second-channel detection outcomes by combining the first
second-channel detection results and the second second-channel
detection results; a first post-processing unit coupled to the
first data combiner for receiving the M first-channel detection
outcomes, and configured to generate M first post-processed
components based on the M first-channel detection outcomes and a
post-processing model; a second post-processing unit coupled to the
second data combiner for receiving the M second-channel detection
outcomes, and configured to generate M second post-processed
components based on the M second-channel detection outcomes and the
post-processing model; and a parallel-to-serial unit coupled to the
first post-processing unit and the second post-processing unit, and
configured to output M complex output data symbols in series by
performing parallel-to-serial conversion on the M first
post-processed components and the M second post-processed
components.
7. The receiver of claim 6, wherein the first analysis filter bank
includes: a first DHT module disposed to receive the two serial
first-channel Rx baseband signals of M/2 points, and configured to
consecutively generate two first DHT intermediate results of M/2
points by, for each of the two serial first-channel Rx baseband
signals of M/2 points, multiplying the serial first-channel Rx
baseband signal of M/2 points with a kernel function of an
M/2-point DHT; a first serial-to-parallel conversion and data
combination module disposed to receive the two serial first-channel
Rx baseband signals of M/2 points, and configured to consecutively
output two parallel first-channel combination signals of M/2
points, where the M/2 points of each of the two parallel
first-channel combination signals are outputted in parallel, by
sequentially performing serial-to-parallel conversion and data
combination on each of the two serial first-channel Rx baseband
signals; a first parallel-to-serial conversion module coupled to
the first serial-to-parallel conversion and data combination module
for receiving the two parallel first-channel combination signals of
M/2 points, and configured to consecutively output two serial
first-channel combination signals of M/2 points, where the M/2
points of each of the two serial first-channel combination signals
are outputted in series, by performing parallel-to-serial
conversion on each of the two parallel first-channel combination
signals of M/2 points; a second DHT module coupled to the first
parallel-to-serial conversion module for receiving the two serial
first-channel combination signals of M/2 points, and configured to
consecutively generate two second DHT intermediate results of M/2
points by, for each of the two serial first-channel combination
signals of M/2 points, multiplying the serial first-channel
combination signal of M/2 points with the kernel function of an
M/2-point DHT; M/2 first prototype filters each coupled to the
first DHT module for receiving a respective one of the M/2 points
of each of the two first DHT intermediate results, the M/2 first
prototype filters being configured to generate two filtered first
DHT intermediate results of M/2 points, wherein each of the two
filtered first DHT intermediate results of M/2 points is generated
by the M/2 first prototype filters each performing filtering on the
respective one of the M/2 points of a corresponding one of the two
first DHT intermediate results; M/2 second prototype filters each
coupled to the second DHT module for receiving a respective one of
the M/2 points of each of the two second DHT intermediate results,
the M/2 second prototype filters being configured to generate two
filtered second DHT intermediate results of M/2 points, wherein
each of the two filtered second DHT intermediate results of M/2
points is generated by the M/2 second prototype filters each
performing filtering on the respective one of the M/2 points of a
corresponding one of the two second DHT intermediate results; M/2
first down-sampling modules respectively coupled to the M/2 first
prototype filters for respectively receiving the M/2 points of each
of the two filtered first DHT intermediate results, and configured
to generate the first part of the filtered first-channel Rx
baseband signal by each performing, for each of the two filtered
first DHT intermediate results, down-sampling on the respective one
of the M/2 points of the filtered first DHT intermediate result;
and M/2 second down-sampling modules respectively coupled to the
M/2 second prototype filters for respectively receiving the M/2
points of each of the two filtered second DHT intermediate results,
and configured to generate the second part of the filtered
first-channel Rx baseband signal by each performing, for each of
the two filtered second DHT intermediate results, down-sampling on
the respective one of the M/2 points of the filtered second DHT
intermediate result; and wherein the second analysis filter bank
includes: a third DHT module disposed to receive the two serial
second-channel Rx baseband signals of M/2 points, and configured to
consecutively generate two third DHT intermediate results of M/2
points by, for each of the two serial second-channel Rx baseband
signals of M/2 points, multiplying the serial second-channel Rx
baseband signal of M/2 points with the kernel function of the
M/2-point DHT; a second serial-to-parallel conversion and data
combination module disposed to receive the two serial
second-channel Rx baseband signals of M/2 points, and configured to
consecutively output two parallel second-channel combination
signals of M/2 points, where the M/2 points of each of the two
parallel second-channel combination signals are outputted in
parallel, by sequentially performing serial-to-parallel conversion
and data combination on each of the two serial second-channel Rx
baseband signals; a second parallel-to-serial conversion module
coupled to the second serial-to-parallel conversion and data
combination module for receiving the two parallel second-channel
combination signals of M/2 points, and configured to consecutively
output two serial second-channel combination signals of M/2 points,
where the M/2 points of each of the serial second-channel
combination signals are outputted in series, by performing
parallel-to-serial conversion on each of the two parallel
second-channel combination signals of M/2 points; a fourth DHT
module coupled to the second parallel-to-serial conversion module
for receiving the two serial second-channel combination signals of
M/2 points, and configured to consecutively generate two fourth DHT
intermediate results of M/2 points by, for each of the two sets of
the serial second-channel combination signals of M/2 points,
multiplying the serial second-channel combination signal of M/2
points with the kernel function of an M/2-point DHT; M/2 third
prototype filters each coupled to the third DHT module for
receiving a respective one of the M/2 points of each of the two
third DHT intermediate results, the M/2 third prototype filters
being configured to generate two filtered third DHT intermediate
results of M/2 points, wherein each of the filtered third DHT
intermediate results of M/2 points is generated by the M/2 third
prototype filters each performing filtering on the respective one
of the M/2 points of a corresponding one of the two third DHT
intermediate results; M/2 fourth prototype filters each coupled to
the fourth DHT module for receiving a respective one of the M/2
points of each of the two fourth DHT intermediate results, the M/2
fourth prototype filters being configured to generate two filtered
fourth DHT intermediate results of M/2 points, wherein each of the
filtered fourth DHT intermediate results of M/2 points is generated
by the M/2 fourth prototype filters each performing filtering on
the respective one of the M/2 points of each of the two fourth DHT
intermediate results; M/2 third down-sampling modules respectively
coupled to the M/2 third prototype filters for respectively
receiving the M/2 points of each of the two filtered third DHT
intermediate results, and configured to generate the first part of
the filtered second-channel Rx baseband signal by each performing,
for each of the two filtered third DHT intermediate results,
down-sampling on the respective one of the M/2 points of the
filtered third DHT intermediate result; and M/2 fourth
down-sampling modules respectively coupled to the M/2 fourth
prototype filters for respectively receiving the M/2 points of each
of the two filtered fourth DHT intermediate results, and configured
to generate the second part of the filtered second-channel Rx
baseband signal by each performing, for each of the two filtered
fourth DHT intermediate results, down-sampling on the respective
one of the M/2 points of the filtered fourth DHT intermediate
result.
8. The receiver of claim 6, wherein the first analysis filter bank
includes: a first serial-to-parallel conversion module disposed to
receive the two serial first-channel Rx baseband signals of M/2
points, and configured to consecutively output two parallel first
down-sampled first-channel Rx baseband signals of M/2 points, where
the M/2 points of each of the parallel first down-sampled
first-channel Rx baseband signals are outputted in parallel, by
sequentially performing serial-to-parallel conversion and
down-sampling on the serial first-channel Rx baseband signals of
M/2 points; a second serial-to-parallel conversion module disposed
to receive the two serial first-channel Rx baseband signals of M/2
points, and configured to consecutively output two parallel second
down-sampled first-channel Rx baseband signals of M/2 points, where
the M/2 points of each of the parallel second down-sampled
first-channel Rx baseband signals are outputted in parallel, by
sequentially performing serial-to-parallel conversion and
down-sampling on the serial first-channel Rx baseband signals of
M/2 points; M/2 different first polyphase filters each coupled to
the first serial-to-parallel conversion module for receiving a
respective one of the M/2 points of each of the two parallel first
down-sampled first-channel Rx baseband signals, and configured to
generate a filtered first down-sampled first-channel Rx baseband
signal of M/2 points by each sequentially performing, for each of
the two parallel first down-sampled first-channel Rx baseband
signals, filtering and down-sampling on the respective one of the
M/2 points of the parallel first down-sampled first-channel Rx
baseband signal; M/2 different second polyphase filters each
coupled to the second serial-to-parallel conversion module for
receiving a respective one of the M/2 points of each of the two
parallel second down-sampled first-channel Rx baseband signals, and
configured to generate a filtered second down-sampled first-channel
Rx baseband signal of M/2 points by each sequentially performing,
for each of the two parallel second down-sampled first-channel Rx
baseband signals, filtering and down-sampling on the respective one
of the M/2 points of each of the parallel second down-sampled
first-channel Rx baseband signal; a first data combination module
coupled to the M/2 second polyphase filters for receiving the
filtered second down-sampled first-channel Rx baseband signal of
M/2 points, and configured to generate a second down-sampled
first-channel combination signal of M/2 points by performing data
combination on the filtered second down-sampled first-channel Rx
baseband signal of M/2 points; a first DHT module coupled to the
M/2 first polyphase filters for receiving the filtered first
down-sampled first-channel Rx baseband signal of M/2 points, and
configured to generate the first part of the filtered first-channel
Rx baseband signal by performing an M/2-point DHT on the filtered
first down-sampled first-channel Rx baseband signal of M/2 points;
and a second DHT module coupled to the first data combination
module for receiving the second down-sampled first-channel
combination signal of M/2 points, and configured to generate the
second part of the filtered first-channel Rx baseband signal by
performing an M/2-point DHT on the second down-sampled
first-channel combination signal of M/2 points; and wherein the
second analysis filter bank includes: a third serial-to-parallel
conversion module disposed to receive the two serial second-channel
Rx baseband signals of M/2 points, and configured to consecutively
output two parallel first down-sampled second-channel Rx baseband
signals of M/2 points, where the M/2 points of each of the parallel
first down-sampled second-channel Rx baseband signals are outputted
in parallel, by sequentially performing serial-to-parallel
conversion and down-sampling on the serial second-channel Rx
baseband signals of M/2 points; a fourth serial-to-parallel
conversion module disposed to receive the two serial Rx
second-channel baseband signals of M/2 points, and configured to
consecutively output two parallel second down-sampled
second-channel Rx baseband signals of M/2 points, where the M/2
points of each of the parallel second down-sampled second-channel
Rx baseband signals are outputted in parallel, by sequentially
performing serial-to-parallel conversion and down-sampling on the
serial second-channel Rx baseband signals of M/2 points; M/2
different third polyphase filters each coupled to the third
serial-to-parallel conversion module for receiving a respective one
of the M/2 points of each of the two parallel first down-sampled
second-channel Rx baseband signals, and configured to generate a
filtered first down-sampled second-channel Rx baseband signal of
M/2 points by each sequentially performing, for each of the two
parallel first down-sampled second-channel Rx baseband signals,
filtering and down-sampling on the respective one of the M/2 points
of the parallel first down-sampled second-channel Rx baseband
signal; M/2 different fourth polyphase filters each coupled to the
fourth serial-to-parallel conversion module for receiving a
respective one of the M/2 points of each of the two parallel second
down-sampled second-channel Rx baseband signals, and configured to
generate a filtered second down-sampled second-channel Rx baseband
signal of M/2 points by each sequentially performing, for each of
the two parallel second down-sampled second-channel Rx baseband
signals, filtering and down-sampling on the respective one of the
M/2 points of each of the parallel second down-sampled
second-channel Rx baseband signal; a second data combination module
coupled to the M/2 fourth polyphase filters for receiving the
filtered second down-sampled second-channel Rx baseband signal of
M/2 points, and configured to generate a second down-sampled
second-channel combination signal of M/2 points by performing data
combination on the filtered second down-sampled second-channel Rx
baseband signal of M/2 points; a third DHT module coupled to the
M/2 third polyphase filters for receiving the filtered first
down-sampled second-channel Rx baseband signal of M/2 points, and
configured to generate the first part of the filtered
second-channel Rx baseband signal by performing an M/2-point DHT on
the filtered first down-sampled second-channel Rx baseband signal
of M/2 points; and a fourth DHT module coupled to the second data
combination module for receiving the second down-sampled
second-channel combination signal of M/2 points, and configured to
generate the second part of the filtered second-channel Rx baseband
signal by performing an M/2-point DHT on the second down-sampled
second-channel combination signal of M/2 points.
9. The receiver of claim 8, wherein the first analysis filter bank
is equivalent to including: a first analysis filter group of M/2
analysis filters respectively corresponding to M/2 subcarriers for
the M/2 components of the first part of the filtered first-channel
Rx baseband signal, and corresponding to the M/2 first polyphase
filters; and a second analysis filter group of M/2 analysis filters
respectively corresponding to M/2 subcarriers for the M/2
components of the second part of the filtered first-channel Rx
baseband signal, and corresponding to the M/2 second polyphase
filters; wherein the second analysis filter bank is equivalent to
including: a third analysis filter group of M/2 analysis filters
respectively corresponding to M/2 subcarriers for the M/2
components of the first part of the filtered second-channel Rx
baseband signal, and corresponding to the M/2 third polyphase
filters; and a fourth analysis filter group of M/2 analysis filters
respectively corresponding to M/2 subcarriers for the M/2
components of the second part of the filtered second-channel Rx
baseband signal, and corresponding to the M/2 fourth polyphase
filters; wherein, for each of the first and second analysis filter
banks, one of the analysis filters that corresponds to a
(2.alpha.+.beta.).sup.th one of the subcarriers is represented by
p.sub..beta.[k]cas(2.pi..alpha.k/(M/2)), where k=0, 1, 2, 3, . . .
, L-1; wherein each of the first, second, third and fourth analysis
filter groups has a system function G.sub..beta.,.alpha.(z) that is
obtained from a z-transform of
p.sub..beta.[k]cas(2.pi..alpha.k/(M/2)), k=0, 1, 2, 3, . . . , L-1,
and that is represented by
G.sub..beta.,.alpha.(z)=.SIGMA..sub.q=0.sup.M/2-1.psi..sub..alpha.,qP.sub-
..beta..sup.(q)(z.sup.M/2)z.sup.-q with .alpha..di-elect
cons.{0,1,2, . . . , M/2-1}, .beta..di-elect cons.{0,1} and
.psi..sub..alpha.,q=cas(2.pi..alpha.q/(M/2)) representing a kernel
function of an M/2-point DHT;
P.sub..beta..sup.(q)(z.sup.M/2)=.SIGMA..sub.r=0.sup.2K-1p.sub..beta.[q+r(-
M/2)]z.sup.-r(M/2) represents a q.sup.th one of the first polyphase
filters for the first analysis filter group with .beta.=0, a
q.sup.th one of the second polyphase filters for the second
analysis filter group with .beta.=1, a q.sup.th one of the third
polyphase filters for the third analysis filter group with
.beta.=0, and a q.sup.th one of the fourth polyphase filters for
the fourth analysis filter group with .beta.=1; each of the first,
second, third and fourth polyphase filters has a length of 2K; and
cas(.PHI.)=cos(.PHI.)+sin(.PHI.).
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims priority of Taiwanese Invention
Patent Application No. 108101960, filed on Jan. 18, 2019.
FIELD
[0002] The disclosure relates to a filter bank multicarrier
communication system, and more particularly to a filter bank
multicarrier communication system based on the discrete Hartley
transform (DHT).
BACKGROUND
[0003] To fulfill the continuous growth of market demands, future
wireless communications are required to have a very high data rate,
a very large system capacity, a very low latency, etc. Among a
number of technologies considered for these purposes, filter bank
multicarrier (FBMC) transmission is a promising one, because this
kind of scheme can lessen intersymbol interference (ISI) and
intercarrier interference (ICI) without using guard intervals or
cyclic prefixes and can achieve a higher spectral efficiency than
orthogonal frequency division multiplexing (OFDM) transmission
adopted by 4G wireless communication systems.
[0004] There are several FBMC approaches in the literature,
including cosine modulated multitone, discrete wavelet multitone,
filtered multitone, and OFDM using offset quadrature amplitude
modulation (OFDM/OQAM), which is also referred to as FBMC/OQAM or
staggered modulated multitone. Different from OFDM using quadrature
amplitude modulation (OFDM/QAM) with each complex QAM data symbol
modulated on a subcarrier during an OFDM frame duration, FBMC/OQAM
transmits the real part and the imaginary part (including the
imaginary "j" symbol) of each complex QAM data symbol on a
subcarrier successively according to a staggering arrangement of
timing offset that equals half an FBMC frame duration.
Specifically, the real-part and imaginary-part data are placed on
each subcarrier for FBMC/OQAM in a way that orthogonality among
subcarriers and FBMC symbols holds in the real field, rather than
in the complex field as with OFDM/QAM.
[0005] FBMC/OQAM adopts a time-frequency localized prototype (pulse
shaping) filter with reduced sidelobes in both the time and
frequency domains to lessen the ISI/ICI problems. Several types of
prototype filters have been proposed for this purpose, including
the root raised cosine function, half-cosine function, extended
Gaussian function, isotropic orthogonal transform algorithm, and
physical layer for dynamic access and cognitive radio (PHYDYAS)
filter developed in an EU-funded research project.
[0006] Although an FBMC/OQAM system achieves excellent performance
under single-input single-output (SISO) scenarios, conventional
multiple-input multiple-out (MIMO) techniques such as Alamouti
space-time block coding (STBC) and maximum likelihood detection
cannot be applied directly, and some modifications along with
complicated receivers are required. This is an undesired feature
that limits applications of FBMC/OQAM.
[0007] For an FBMC/OQAM system with M subcarriers, a synthesis
filter bank of a transmitter needs to perform two complex M-point
inverse discrete Fourier transforms (IDFTs) for modulation and
specific synthesis filtering operations in order to transmit a
sequence of complex M-point QAM data symbols. On the other hand, an
analysis filter bank of a receiver needs to perform two complex
M-point discrete Fourier transforms (DFTs) for demodulation,
specific analysis filtering operations, and appropriate data
detection operations in order to receive a sequence of complex
M-point QAM data symbols. Since this scheme uses the complex-valued
IDFT and DFT, it is referred to as DFT-FBMC/OQAM.
[0008] To facilitate extension to MIMO scenarios, another kind of
FBMC using IDFT/DFT and QAM, referred to as DFT-FBMC/QAM, was
proposed recently, where a complete complex QAM data symbol is
transmitted on a subcarrier during an FBMC frame duration. This
kind of scheme adopts a set of two or more specific prototype
filters, instead of a single prototype filter as used in
DFT-FBMC/OQAM, to minimize self-interference. For example, with two
orthogonal prototype filters, we can use one of them for
even-numbered subcarriers and the other for odd-numbered
subcarriers to effectively relieve the ISI/ICI problems. It was
shown that DFT-FBMC/QAM using two prototype filters achieves
slightly worse bit-error-rate (BER) performance than DFT-FBMC/OQAM,
but is more easily combined with existing MIMO techniques.
[0009] For an FBMC/QAM system with M subcarriers and two prototype
filters, a synthesis filter bank of a transmitter needs to perform
two complex M/2-point IDFTs for modulation and specific synthesis
filtering operations in order to transmit a sequence of complex
M-point QAM data symbols. In contrast, an analysis filter bank of a
receiver needs to perform two complex M/2-point DFTs for
demodulation, specific analysis filtering operations, and
appropriate data detection operations in order to receive a
sequence of complex M-point QAM data symbols. Although this
DFT-FBMC/QAM scheme involves complex-valued IDFT/DFT computations,
its implementation complexity is lower than that of the
DFT-FBMC/OQAM system.
SUMMARY
[0010] The disclosure provides a filter bank multicarrier (FBMC)
communication system using QAM, the inverse discrete Hartley
transform (IDHT), and the discrete Hartley transform (DHT) that has
similar advantages in terms of MIMO extension and implementation
complexity to the DFT-FBMC/QAM scheme but is able to achieve better
performance. The DHT-based FBMC communication system is referred to
as DHT-FBMC/QAM, which includes a transmitter and a receiver.
[0011] According to the disclosure, the transmitter includes a
serial-to-parallel conversion unit, a first pre-processing unit, a
second pre-processing unit, a first data separator, a second data
separator, a first synthesis filter bank, and a second synthesis
filter bank. The serial-to-parallel conversion unit is configured
to perform serial-to-parallel conversion on M serial complex data
symbols, each including a real part and an imaginary part, for
outputting M real parts and M imaginary parts of the M complex data
symbols in parallel, where M is a positive even integer. The first
pre-processing unit is coupled to the serial-to-parallel conversion
unit for receiving the M real parts, and is configured to generate
M pre-processed real-part components based on a pre-processing
model. The second pre-processing unit is coupled to the
serial-to-parallel conversion unit for receiving the M imaginary
parts, and is configured to generate M pre-processed imaginary-part
components based on the pre-processing model. The first data
separator is coupled to the first pre-processing unit for receiving
the M pre-processed real-part components, and is configured to
separate the received components into M/2 even-numbered
pre-processed real-part components and M/2 odd-numbered
pre-processed real-part components. The second data separator is
coupled to the second pre-processing unit for receiving the M
pre-processed imaginary-part components, and is configured to
separate the received components into M/2 even-numbered
pre-processed imaginary-part components and M/2 odd-numbered
pre-processed imaginary-part components. The first synthesis filter
bank is coupled to the first data separator for receiving the M/2
even-numbered pre-processed real-part components and the M/2
odd-numbered pre-processed real-part components in parallel, and is
configured to generate a first-channel transmitted (abbreviated as
Tx) baseband signal of M points by performing at least up-sampling,
filtering, IDHT, data combination, and parallel-to-serial
conversion on these pre-processed real-part components. The second
synthesis filter bank is coupled to the second data separator for
receiving the M/2 even-numbered pre-processed imaginary-part
components and the M/2 odd-numbered pre-processed imaginary-part
components, and is configured to generate a second-channel Tx
baseband signal of M points by performing at least up-sampling,
filtering, IDHT, data combination, and parallel-to-serial
conversion on these pre-processed imaginary-part components.
[0012] According to the disclosure, the receiver includes a first
analysis filter bank, a second analysis filter bank, a data
detection unit, a first data combiner, a second data combiner, a
first post-processing unit, a second post-processing unit, and a
parallel-to-serial conversion unit. The first analysis filter bank
is disposed to process a serial first-channel received (abbreviated
as Rx) baseband signal of M points, and is configured to generate a
first part and a second part of a filtered first-channel Rx
baseband signal by performing at least serial-to-parallel
conversion, down-sampling, filtering, data combination, and DHT on
the received signals, wherein each of the first part and the second
part has M/2 components. The second analysis filter bank is
disposed to process a serial second-channel Rx baseband signals of
M points, and is configured to generate a first part and a second
part of a filtered second-channel Rx baseband signal by performing
at least serial-to-parallel conversion, down-sampling, filtering,
data combination, and DHT on the second-channel Rx baseband
signals, wherein each of the first part and the second part has M/2
components. The data detection unit is coupled to the first
analysis filter bank and the second analysis filter bank. This unit
is configured to generate M/2 first first-channel detection results
corresponding to the first part of the filtered first-channel Rx
baseband signal and M/2 first second-channel detection results
corresponding to the first part of the filtered second-channel Rx
baseband signal by performing joint detection on the first parts of
the filtered first-channel and second-channel Rx baseband signals
as well as to generate M/2 second first-channel detection results
corresponding to the second part of the filtered first-channel Rx
baseband signal and M/2 second second-channel detection results
corresponding to the second part of the filtered second-channel Rx
baseband signal by performing joint detection on the second parts
of the filtered first-channel and second-channel Rx baseband
signals. The first data combiner is coupled to the data detection
unit, and is configured to generate M first-channel detection
outcomes by combining the M/2 first first-channel detection results
and the M/2 second first-channel detection results. The second data
combiner is coupled to the data detection unit, and is configured
to generate M second-channel detection outcomes by combining the
M/2 first second-channel detection results and the M/2 second
second-channel detection results. The first post-processing unit is
coupled to the first data combiner, and is configured to generate M
first post-processed components based on the M first-channel
detection outcomes and a post-processing model. The second
post-processing unit is coupled to the second data combiner, and is
configured to generate M second post-processed components based on
the M second-channel detection outcomes and the post-processing
model. The parallel-to-serial unit is coupled to the first
post-processing unit and the second post-processing unit, and is
configured to output complex output data symbols in series by
performing parallel-to-serial conversion on the M first
post-processed components and the M second post-processed
components.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Other features and advantages of the disclosure will become
apparent in the following detailed descriptions of the
embodiment(s) with reference to the accompanying drawings
including:
[0014] FIG. 1 is a block diagram illustrating an embodiment of the
filter bank multicarrier (FBMC) communication system based on the
discrete Hartley transform (DHT) according to the disclosure;
[0015] FIGS. 2 and 3 are block diagrams illustrating first
implementations of synthesis filter banks of the embodiment;
[0016] FIGS. 4 and 5 are block diagrams illustrating second
implementations of the synthesis filter banks of the
embodiment;
[0017] FIGS. 6 and 7 are block diagrams illustrating first
implementations of analysis filter banks of the embodiment;
[0018] FIGS. 8 and 9 are block diagrams illustrating second
implementations of the analysis filter banks of the embodiment;
and
[0019] FIG. 10 is a plot of some simulation results that shows
performance comparisons among the embodiment of this disclosure
(DHT-FBMC/QAM) and two conventional FBMC schemes (DFT-FBMC/OQAM and
DFT-FBMC/QAM) in terms of the bit error rate (BER) versus the
signal-to-noise ratio (SNR).
DETAILED DESCRIPTION
[0020] Before the disclosure is described in greater detail, it
should be noted that where considered appropriate, reference
numerals or terminal portions of reference numerals have been
repeated among the figures to indicate corresponding or analogous
elements, which may optionally have similar characteristics.
[0021] Referring to FIG. 1, the embodiment of the filter bank
multicarrier (FBMC) communication system based on the discrete
Hartley transform (DHT) according to this disclosure is shown that
includes a transmitter end 1 and a receiver end 2.
[0022] In FIG. 1, the transmitter end 1 generates an I-channel Tx
(meaning transmitted) baseband signal (first-channel Tx baseband
signal) and a Q-channel Tx baseband signal (second-channel Tx
baseband signal) based on M complex input data symbols, each
including a real part and an imaginary part, and transmits the
I-channel Tx baseband signal and the Q-channel Tx baseband signal
to the receiver end 2 via an I-channel (first channel) and a
Q-channel (second channel), respectively, where M is a positive
even integer. The transmitter end 1 includes a serial-to-parallel
(S/P) conversion unit 12, two pre-processing units 13, 13', two
data separators 10, 10', and two synthesis filter banks 14, 15.
[0023] The serial-to-parallel conversion unit 12 performs
serial-to-parallel conversion on the M complex input data symbols,
which are inputted thereto in series, and outputs the M real parts
and the M imaginary parts of the complex input data symbols in
parallel. In this embodiment, the complex input data symbols are
represented by d.sub.m,n=d.sub.m,n.sup.I+jd.sub.m,n.sup.Q,
m.di-elect cons.{0,1, . . . , M-1}, where d.sub.m,n represents an
m.sup.th one of the M complex input data symbols that are
transmitted on M subcarriers at a time point n, d.sub.m,n.sup.I
represents the real part of d.sub.m,n, and d represents the
imaginary part of d.sub.m,n.
[0024] The pre-processing unit 13 is a pre-processor coupled to the
serial-to-parallel conversion unit 12 for receiving the M real
parts of the complex input data symbols, and generates M
pre-processed real-part components based on a pre-processing model
and the received M real parts.
[0025] The pre-processing unit 13' is a pre-processor coupled to
the serial-to-parallel conversion unit 12 for receiving the M
imaginary parts of the complex input data symbols, and generates M
pre-processed imaginary-part components based on the pre-processing
model and the received M imaginary parts.
[0026] In this embodiment, the pre-processing model is exemplified
by:
X.sub.m,n=(d.sub.m,n cos .theta..sub.m+(-1).sup.L-1d.sub.M-m,n,sin
.theta..sub.m),m=0,1, . . . ,M-1,
where X.sub.m,n represents a pre-processing result that is based on
d.sub.m,n and d.sub.M-m,n and that is on an m.sup.th one of the
subcarriers at a time point n; .theta.=(2.pi.m/M)(L-1)/2 could be
regarded as a rotation angle on the m.sup.th one of the
subcarriers; and L represents a prototype filter length used for
each of the synthesis filter banks 14, 15.
[0027] Accordingly, one of the M pre-processed real-part components
that is outputted by the pre-processing unit 13 and that is
transmitted on the I-channel of the m.sup.th one of the subcarriers
at the time point n can be represented by X.sub.m,n.sup.I, and one
of the M pre-processed imaginary-part components that is outputted
by the pre-processing unit 13' and that is transmitted on the
Q-channel of the m.sup.th one of the subcarriers at the time point
n can be represented by X.sub.m,n.sup.Q wherein
X.sub.m,n.sup.I=(d.sub.m,n.sup.I cos
.theta..sub.m+(-1).sup.L-1d.sub.M-m,n.sup.I sin
.theta..sub.m),m=0,1, . . . ,M-1
and
X.sub.m,n.sup.Q=(d.sub.m,n.sup.Q cos
.theta..sub.m+(-1).sup.L-1d.sub.M-m,n.sup.Q sin
.theta..sub.m),m=0,1, . . . ,M-1
[0028] The data separator 10 is coupled to the pre-processing unit
13 for receiving the M pre-processed real-part components, and
separates them into M/2 even-numbered pre-processed real-part
components and M/2 odd-numbered pre-processed real-part
components.
[0029] The data separator 10' is coupled to the pre-processing unit
13' for receiving the M pre-processed imaginary-part components,
and separates them into M/2 even-numbered pre-processed
imaginary-part components and M/2 odd-numbered pre-processed
imaginary-part components.
[0030] The synthesis filter bank 14 is coupled to the data
separator 10 for receiving the M/2 even-numbered pre-processed
real-part components and the M/2 odd-numbered pre-processed
real-part components, and generates the I-channel Tx baseband
signal of M points by performing at least up-sampling, filtering,
inverse discrete Hartley transform (IDHT), data combination, and
parallel-to-serial conversion on all the received pre-processed
real-part components. In practice, the synthesis filter 14 may be
realized as a dedicated processor, a general-purpose processor in
cooperation with a firmware that implements the functions described
in this disclosure, or a general-purpose processor that executes a
software program designed to implement the functions described in
this disclosure, but this disclosure is not limited in this
respect.
[0031] The synthesis filter bank 15 is coupled to the data
separator 10' for receiving the M/2 even-numbered pre-processed
imaginary-part components and the M/2 odd-numbered pre-processed
imaginary-part components, and generates a Q-channel Tx baseband
signal of M points by performing at least up-sampling, filtering,
IDHT, data combination, and parallel-to-serial conversion on all
the received pre-processed imaginary-part components.
[0032] In this embodiment, two exemplary implementations for each
of the synthesis filter banks 14, 15 are provided. FIGS. 2 and 4
respectively illustrate first and second exemplary implementations
of the synthesis filter bank 14, and FIGS. 3 and 5 respectively
illustrate first and second exemplary implementations of the
synthesis filter bank 15.
[0033] Referring to FIG. 2, the first implementation of the
synthesis filter bank 14 includes M/2 up-sampling modules 141, M/2
up-sampling modules 141', M/2 prototype filters 142, M/2 prototype
filters 142', two IDHT modules 143, 143', a serial-to-parallel
conversion module 144', a data combination and parallel-to-serial
(P/S) conversion module 145, and an adder 146.
[0034] The M/2 up-sampling modules 141 are coupled to the data
separator 10 (see FIG. 1) for respectively receiving the M/2
even-numbered pre-processed real-part components. Each of the
up-sampling modules 141 performs up-sampling on the respective one
of the M/2 even-numbered pre-processed real-part components by a
factor of M.
[0035] The M/2 up-sampling modules 141' are coupled to the data
separator 10 (see FIG. 1) for respectively receiving the M/2
odd-numbered pre-processed real-part components. Each of the
up-sampling modules 141' performs up-sampling on the respective one
of the M/2 odd-numbered pre-processed real-part components by a
factor of M.
[0036] The M/2 prototype filters 142 are respectively coupled to
the M/2 up-sampling modules 141 for respectively receiving the M/2
even-numbered pre-processed real-part components that have been
up-sampled by the M/2 up-sampling modules 141. Each of the
prototype filters 142 performs filtering on the respective one of
the M/2 even-numbered pre-processed real-part components that has
been up-sampled.
[0037] The M/2 prototype filters 142' are respectively coupled to
the M/2 up-sampling modules 141' for respectively receiving the M/2
odd-numbered pre-processed real-part components that have been
up-sampled by the M/2 up-sampling modules 141'. Each of the
prototype filters 142' performs filtering on the respective one of
the M/2 odd-numbered pre-processed real-part components that has
been up-sampled.
[0038] In this embodiment, the prototype filters 142 are identical
(denoted by p.sub.0[k]) and the prototype filters 142' are
identical (denoted by p.sub.1[k]), where p.sub.0[k] is orthogonal
or nearly orthogonal to p.sub.1[k]. The prototype filter p.sub.0[k]
may be realized by the root raised cosine function, half-cosine
function, extended Gaussian function, isotropic orthogonal
transform algorithm, or physical layer for dynamic access and
cognitive radio (PHYDYAS) filter, while the prototype filter
p.sub.1[k] may be designed based on p.sub.0[k] to minimize
intersymbol interference (ISI) and intercarrier interference (ICI),
and vice versa. The length of each of the prototype filters
p.sub.0[k] and p.sub.1[k] is represented by L, and its value may be
L=KM, L=KM-1, or L=KM+1, where K is a positive integer called an
overlapping factor. However, this disclosure is not limited in each
of the above respects.
[0039] The IDHT module 143 is coupled to the M/2 prototype filters
142 for receiving, in parallel, the M/2 even-numbered pre-processed
real-part components that have been up-sampled by the M/2
up-sampling modules 141 and filtered by the M/2 prototype filters
142. For two sets of the M/2 even-numbered pre-processed real-part
components that have been up-sampled and filtered and that are
consecutively received by the IDHT module 143 (i.e., each set has
M/2 components), the IDHT module 143 consecutively generates two
serial first-IDHT results of M/2 points (for each serial first-IDHT
result of M/2 points, the M/2 points are outputted in series),
which serve as a first part of the I-channel Tx baseband signal, by
performing M/2-point IDHT operations (also referred to as IDHTs
throughout this disclosure) on the two sets of the M/2
even-numbered pre-processed real-part components that have been
up-sampled and filtered and that are received by the IDHT module
143 consecutively.
[0040] In this embodiment, the IDHT module 143 obtains the
first-IDHT results according to:
s 0 I [ k ] = y 0 I [ k ] = .alpha. = 0 M / 2 - 1 Y 0 , .alpha. I [
k ] cas ( 2 .pi. .alpha. k M / 2 ) , k = 0 , 1 , 2 , , M - 1 ,
##EQU00001##
where y.sub.0.sup.I[k] represents an output of the IDHT module 143;
s.sub.0.sup.I[k] represents the first part of the I-channel Tx
baseband signal (namely, the output result obtained from the M/2
even-numbered pre-processed real-part components processed by the
modules 141, 142, 143 of the synthesis filter bank 14);
Y.sub.0,.alpha..sup.I[k]=.SIGMA..sub.n=-.infin..sup..infin.X.sub.2.alpha.-
,np.sub.0[k-nM] represents a result obtained from
X.sub.2.alpha.,n.sup.I being up-sampled by one of the up-sampling
modules 141 followed by being processed by one of the prototype
filters 142 (p.sub.0[k]), wherein X.sub.2.alpha.,n.sup.I is an
.alpha..sup.th one of the M/2 even-numbered pre-processed real-part
components, .alpha..di-elect cons.{0,1,2, . . . ,M/2-1}; and
cas(.PHI.)=cos(.PHI.)+sin(.PHI.).
[0041] The IDHT module 143' is coupled to the M/2 prototype filters
142' for receiving, in parallel, the M/2 odd-numbered pre-processed
real-part components that have been up-sampled by the M/2
up-sampling modules 141' and filtered by the prototype filters
142'. For two sets of the M/2 odd-numbered pre-processed real-part
components that have been up-sampled and filtered and that are
consecutively received by the IDHT module 143', the IDHT module
143' consecutively generates two serial second-IDHT results of M/2
points (for each serial second-IDHT result of M/2 points, the M/2
points are outputted in series) by performing M/2-point IDHTs on
the two sets of the M/2 odd-numbered pre-processed real-part
components that have been up-sampled and filtered and that are
received by the IDHT module 143' consecutively.
[0042] In this embodiment, the IDHT module 143' obtains the
second-IDHT results according to:
y 1 I [ k ] = .alpha. = 0 M / 2 - 1 Y 1 , .alpha. I [ k ] cas ( 2
.pi. .alpha. k M / 2 ) , k = 0 , 1 , 2 , , M - 1 , ##EQU00002##
where y.sub.1.sup.I[k] represents an output of the IDHT module
143'; and
Y.sub.1,.alpha..sup.I[k]=.SIGMA..sub.n=-.infin..sup..infin.X.sub.2.alpha.-
+1,np.sub.1[k-nM] stands for a result obtained from
X.sub.2.alpha.+1,n.sup.I being up-sampled by one of the up-sampling
modules 141' followed by being processed by one of the prototype
filters 142' (p.sub.1[k]), wherein X.sub.2.alpha.+1,n.sup.I is an
.alpha..sup.th one of the M/2 odd-numbered pre-processed real-part
components, .alpha..di-elect cons.{0, 1, 2, . . . , M/2-1}. It is
noted that each of the M/2 prototype filters 142 (p.sub.0[k])
corresponding to even-numbered subcarriers is orthogonal or nearly
orthogonal to each of the M/2 prototype filters 142' (p.sub.1[k])
corresponding to odd-numbered subcarriers, so as to lessen ICI and
ISI.
[0043] The serial-to-parallel conversion module 144' is coupled to
the IDHT module 143' for receiving the two serial second-IDHT
results of M/2 points, and consecutively outputs two parallel
second-IDHT results of M/2 points (the M/2 points of each parallel
second-IDHT result are outputted in parallel) by performing
serial-to-parallel conversion on each of the two serial second-IDHT
results of M/2 points.
[0044] The data combination and parallel-to-serial conversion
module 145 is coupled to the serial-to-parallel conversion module
144' for receiving the two parallel second-IDHT results of M/2
points, and generates a second part of the I-channel Tx baseband
signal by, for each of the two parallel second-IDHT results of M/2
points, performing data combination on the parallel second-IDHT
result of M/2 points to obtain a data combination result in a
manner as described below, and performing parallel-to-serial
conversion on the data combination result for the parallel
second-IDHT result of M/2 points.
[0045] In this embodiment, the second part of the I-channel Tx
baseband signal (namely, the output results obtained from the M/2
odd-numbered pre-processed real-part components processed by
components 141', 142', 143', 144', 145 of the synthesis filter bank
14), which is represented by s.sub.1.sup.I[k] is generated by the
data combination and parallel-to-serial conversion module 145
according to:
s 1 I [ k ] = cos ( 2 .pi. k M ) y 1 I [ k ] + sin ( 2 .pi. k M ) y
1 I [ M / 2 - k + M k ( M / 2 ) ] , k = 0 , 1 , 2 , , M - 1 ,
##EQU00003##
where .left brkt-bot.k/(M/2).right brkt-bot.=0 in case k<M/2,
and .left brkt-bot.k/(M/2).right brkt-bot.=1 in case
k.gtoreq.M/2.
[0046] The adder 146 is coupled to the IDHT module 143 and the data
combination and parallel-to-serial conversion module 145, and
generates the I-channel Tx baseband signal, which is represented by
s.sup.I[k] hereinafter, by adding the first part s.sub.0.sup.I[k]
and the second part s.sub.1.sup.I[k] of the I-channel Tx baseband
signal together.
[0047] As a result, the I-channel Tx baseband signal can be
represented by s.sup.I[k]=s.sub.0.sup.I[k]+s.sub.1.sup.I[k], k=0,
1, 2, . . . , M-1, and
s I [ k ] = n = - .infin. .infin. m = 0 M - 1 X m , n I p m [ k -
nM ] cas ( 2 .pi. mk M ) = n = - .infin. .infin. .alpha. = 0 M / 2
- 1 .beta. = 0 1 X 2 .alpha. + .beta. , n I p 2 .alpha. + .beta. [
k - nM ] cas ( 2 .pi. ( 2 .alpha. + .beta. ) k M ) = .alpha. = 0 M
/ 2 - 1 ( n = - .infin. .infin. X 2 .alpha. , n I p 0 [ k - nM ] )
cas ( 2 .pi. k .alpha. M / 2 ) s 0 I [ k ] + .alpha. = 0 M / 2 - 1
( n = - .infin. .infin. X 2 .alpha. + 1 , n I p 1 [ k - nM ] ) cas
( 2 .pi. .alpha. k M / 2 + 2 .pi. k M ) s 1 I [ k ] ,
##EQU00004##
where .alpha..di-elect cons.{0,1,2, . . . ,M/2-1}; .beta..di-elect
cons.{0,1}; p.sub.2.alpha.[k]=p.sub.0[k] represents one of the M/2
prototype filters 142 that is for a 2.alpha..sup.th one of the
subcarriers; and p.sub.2.alpha.+1[k]=p.sub.1[k] represents one of
the M/2 prototype filters 142' that is for a (2.alpha.+1).sup.th
one of the subcarriers. The first part of the I-channel Tx baseband
signal, s.sub.0.sup.I[k], can be obtained by performing M/2-point
IDHT operations on {Y.sub.0,.alpha..sup.I[0],
Y.sub.0,.alpha..sup.I[1], . . . , Y.sub.0,.alpha..sup.I[M/2-1]} and
{Y.sub.0,.alpha..sup.I[M/2], Y.sub.0,.alpha..sup.I[M/2+1], . . . ,
Y.sub.0,.alpha..sup.I[M-1]}. The second part of the I-channel Tx
baseband signal, s.sub.1.sup.I[k], can be obtained by appropriate
data combination of those results of performing M/2-point IDHTs on
{Y.sub.1,.alpha..sup.I[0],Y.sub.1,.alpha..sup.I[1], . . . ,
Y.sub.1,.alpha..sup.I[M/2-1]} and {Y.sub.1,.alpha..sup.I[M/2],
Y.sub.1,.alpha..sup.I[M/2+1], . . . ,
Y.sub.1,.alpha..sup.I[M-1]}.
[0048] Referring to FIG. 3, the first implementation of the
synthesis filter bank 15 is similar to that of the synthesis filter
bank 14 shown in FIG. 2, and includes M/2 up-sampling modules 151,
M/2 up-sampling modules 151', M/2 prototype filters 152, M/2
prototype filters 152', two IDHT modules 153, 153', a
serial-to-parallel conversion module 154', a data combination and
parallel-to-serial conversion module 155, and an adder 156.
[0049] The M/2 up-sampling modules 151 are coupled to the data
separator 10' (see FIG. 1) for respectively receiving the M/2
even-numbered pre-processed imaginary-part components, and each of
them performs up-sampling operations on the corresponding received
even-numbered pre-processed imaginary-part component by a factor of
M.
[0050] The M/2 up-sampling modules 151' are coupled to the data
separator 10' (see FIG. 1) for respectively receiving the M/2
odd-numbered pre-processed imaginary-part components, and each of
them performs up-sampling operations on the corresponding received
odd-numbered pre-processed imaginary-part component by a factor of
M.
[0051] The M/2 prototype filters 152 are respectively coupled to
the M/2 up-sampling modules 151 for respectively receiving the M/2
even-numbered pre-processed imaginary-part components that have
been up-sampled by the M/2 up-sampling modules 151. Each of the
prototype filters 152 performs filtering on the respective one of
the M/2 even-numbered pre-processed imaginary-part components that
has been up-sampled.
[0052] The M/2 prototype filters 152' are respectively coupled to
the M/2 up-sampling modules 151' for respectively receiving the M/2
odd-numbered pre-processed imaginary-part components that have been
up-sampled by the M/2 up-sampling modules 151'. Each of the
prototype filters 152' performs filtering on the respective one of
the M/2 odd-numbered pre-processed imaginary-part components that
has been up-sampled.
[0053] In this embodiment, the prototype filters 152 are identical
(denoted by p.sub.0[k]) and the prototype filters 152' are
identical (denoted by p.sub.1[k]), where p.sub.0[k] is orthogonal
or nearly orthogonal to p.sub.1[k]. The prototype filter p.sub.0[k]
may be realized by the root raised cosine function, half-cosine
function, extended Gaussian function, isotropic orthogonal
transform algorithm, or physical layer for dynamic access and
cognitive radio (PHYDYAS) filter, while the prototype filter
p.sub.1[k] may be designed based on p.sub.0[k] to minimize ISI and
ICI, and vice versa. The length of each of the prototype filters
p.sub.0[k] and p.sub.1[k] is represented by L, and its value may be
L=KM, L=KM-1, or L=KM+1, where K is a positive integer called an
overlapping factor. However, this disclosure is not limited in each
of the above respects.
[0054] The IDHT module 153 is coupled to the M/2 prototype filters
152 for receiving, in parallel, the M/2 even-numbered pre-processed
imaginary-part components that have been up-sampled by the M/2
up-sampling modules 151 and filtered by the M/2 prototype filters
152. For two sets of the M/2 even-numbered pre-processed
imaginary-part components that have been up-sampled and filtered
and that are consecutively received by the IDHT module 153, the
IDHT module 153 consecutively generates two serial third-IDHT
results of M/2 points (for each serial third-IDHT result of M/2
points, the M/2 points are outputted in series), which serve as a
first part of the Q-channel Tx baseband signal, by performing
M/2-point IDHTs on the two sets of the M/2 even-numbered
pre-processed imaginary-part components that have been up-sampled
and filtered and that are received by the IDHT module 153
consecutively.
[0055] The IDHT module 153' is coupled to the M/2 prototype filters
152' for receiving, in parallel, the M/2 odd-numbered pre-processed
imaginary-part components that have been filtered by the prototype
filters 152' For two sets of the M/2 odd-numbered pre-processed
imaginary-part components that have been up-sampled and filtered
and that are consecutively received by the IDHT module 153', the
IDHT module 153' consecutively generates two serial fourth-IDHT
results of M/2 points (for each serial fourth-IDHT result of M/2
points, the M/2 points are outputted in series) by performing
M/2-point IDHTs on the two sets of the M/2 odd-numbered
pre-processed imaginary-part components that have been up-sampled
and filtered and that are received by the IDHT module 153'
consecutively.
[0056] The serial-to-parallel conversion module 154' is coupled to
the IDHT module 153' for receiving the two serial fourth-IDHT
results of M/2 points, and consecutively outputs two parallel
fourth-IDHT results of M/2 points (the M/2 points of each parallel
fourth-IDHT result are outputted in parallel) by performing
serial-to-parallel conversion on each of the two serial fourth-IDHT
results of M/2 points.
[0057] The data combination and parallel-to-serial conversion
module 155 is coupled to the serial-to-parallel conversion module
154' for receiving the two parallel fourth-IDHT results of M/2
points, and generates a second part of the Q-channel Tx baseband
signal by, for each of the two parallel fourth-IDHT result of M/2
points, performing data combination on the parallel fourth-IDHT
result of M/2 points to obtain a data combination result, and
performing parallel-to-serial conversion on the data combination
result for the parallel fourth-IDHT result of M/2 points.
[0058] The adder 156 is coupled to the IDHT module 153 and the data
combination and parallel-to-serial conversion module 155, and
generates the Q-channel Tx baseband signal, which is represented by
s.sup.Q[k] hereinafter, by adding together the first part and the
second part of the Q-channel Tx baseband signal, which are
hereinafter represented by s.sub.0.sup.Q[k] and s.sub.1.sup.Q[k],
respectively.
[0059] It is noted that operations of the IDHT modules 153, 153',
the serial-to-parallel conversion module 154', the data combination
and parallel-to-serial conversion module 155 and the adder 156 are
similar to operations of the IDHT modules 143, 143', the
serial-to-parallel conversion module 144', the data combination and
parallel-to-serial conversion module 145 and the adder 146, so
details thereof are not repeated herein for the sake of
brevity.
[0060] As a result, the Q-channel Tx baseband signal can be
represented by s.sup.Q[k]=s.sub.0.sup.Q[k]+s.sub.1.sup.Q[k], k=0,
1, 2, . . . , M-1, and
s Q [ k ] = n = - .infin. .infin. m = 0 M - 1 X m , n Q p m [ k -
nM ] cas ( 2 .pi. mk M ) = n = - .infin. .infin. .alpha. = 0 M / 2
- 1 .beta. = 0 1 X 2 .alpha. + .beta. , n Q p 2 .alpha. + .beta. [
k - nM ] cas ( 2 .pi. ( 2 .alpha. + .beta. ) k M ) = .alpha. = 0 M
/ 2 - 1 ( n = - .infin. .infin. X 2 .alpha. , n Q p 0 [ k - nM ] )
cas ( 2 .pi. k .alpha. M / 2 ) s 0 Q [ k ] + .alpha. = 0 M / 2 - 1
( n = - .infin. .infin. X 2 .alpha. + 1 , n Q p 1 [ k - nM ] ) cas
( 2 .pi. .alpha. k M / 2 + 2 .pi. k M ) s 1 Q [ k ] ,
##EQU00005##
where .alpha..di-elect cons.{0,1,2, . . . , M/2-1}; .beta..di-elect
cons.{0,1}; p.sub.2.alpha.[k]=p.sub.0[k] represents one of the M/2
prototype filters 152 that is for a 2.alpha..sup.th one of the
subcarriers; p.sub.2.alpha.+1[k]=p.sub.1[k] represents one of the
M/2 prototype filters 152' that is for a (2.alpha.+1).sup.th one of
the subcarriers;
Y.sub.0,.alpha..sup.Q[k]=.SIGMA..sub.n=-.infin..sup..infin.X.sub.2.alpha.-
+1,np.sub.1[k-nM] denotes a result obtained from
X.sub.2.alpha.,n.sup.Q, being up-sampled by one of the up-sampling
modules 151 followed by being processed by one of the prototype
filters 152, wherein X.sub.2.alpha.,n.sup.Q is an .alpha..sup.th
one of the M/2 even-numbered pre-processed imaginary-part
components; and
Y.sub.1,.alpha..sup.Q[k]=.SIGMA..sub.n=-.infin..sup..infin.X.sub.2.alpha.-
+1,np.sub.1[k-nM] denotes a result obtained from
X.sub.2.alpha.,n.sup.Q being up-sampled by one of the up-sampling
modules 151' followed by being processed by one of the prototype
filters 152', wherein X.sub.2.alpha.+1,n.sup.Q is an .alpha..sup.th
one of the M/2 odd-numbered pre-processed imaginary-part
components. The first part of the Q-channel Tx baseband signal,
s.sub.0.sup.Q[k], can be obtained by performing M/2-point IDHTs on
{Y.sub.0,.alpha..sup.Q[0], Y.sub.0,.alpha..sup.Q[1], . . . ,
Y.sub.0,.alpha..sup.Q[M/2-1]} and {Y.sub.0,.alpha..sup.Q[M/2],
Y.sub.0,.alpha..sup.Q[M/2+1], . . . , Y.sub.0,.alpha..sup.Q[M-1]}.
The second part of the Q-channel Tx baseband signal,
s.sub.1.sup.Q[k], can be obtained by appropriate data combination
of those results of performing M/2-point IDHTs on
{Y.sub.1,.alpha..sup.Q[0], Y.sub.1,.alpha..sup.Q[1], . . . ,
Y.sub.1,.alpha..sup.Q[M/2-1]} and {Y.sub.1,.alpha..sup.Q[M/2],
Y.sub.1,.alpha..sup.Q[M/2+1], . . . , Y.sub.1,.alpha..sup.Q[M-1]}.
Note that each of the M/2 prototype filters 152 (p.sub.0[k])
corresponding to even-numbered subcarriers is orthogonal or nearly
orthogonal to each of the M/2 prototype filters 152' (p.sub.1[k])
corresponding to the odd-numbered subcarriers, so as to lessen ISI
and ICI.
[0061] In this embodiment, each of the synthesis filter banks 14,
15 may be implemented by an equivalent structure that includes M
synthesis filters. The synthesis filter bank 14 includes a first
synthesis filter group of M/2 synthesis filters respectively
corresponding to M/2 subcarriers for the M/2 even-numbered
pre-processed real-part components, and a second synthesis filter
group of M/2 synthesis filters respectively corresponding to M/2
subcarriers for the M/2 odd-numbered pre-processed real-part
components. The synthesis filter bank 15 includes a third synthesis
filter group of M/2 synthesis filters respectively corresponding to
M/2 subcarriers for the M/2 even-numbered pre-processed
imaginary-part components, and a fourth synthesis filter group of
M/2 synthesis filters respectively corresponding to M/2 subcarriers
for the M/2 odd-numbered pre-processed imaginary-part components.
For each of the synthesis filter banks 14, 15, one of the synthesis
filters that corresponds to a (2.alpha.+.beta.).sup.th one of the
subcarriers is represented by
p.sub..beta.[k]cas(2.pi..alpha.k/(M/2)) with the same length as
that of each of the prototype filters 142, 142', 152, 152', where
.alpha..di-elect cons.{0,1,2, . . . , M/2-1}, .beta..di-elect
cons.{0,1}, and k=0, 1, 2, . . . , L-1. For ease of presentation,
an assumption of L=KM is made in the following derivations, and the
results for L=KM can be easily extended to cases where L=KM+1 and
L=KM-1, where K is the overlapping factor. Each of the first,
second, third and fourth synthesis filter groups has a system
function F.sub..beta.,.alpha.(z) that is obtained from a
z-transform of p.sub..beta.[k]cas(2.pi..alpha.k/(M/2)), k=0, 1, 2,
. . . , L-1. Based on the periodicity of cas(2.pi..alpha.k/(M/2)),
each of the prototype filters 142, 142' of length KM can be
separated into 2K segments, in which each segment is multiplied by
a full period of the cas function. In other words, each of the
first, second, third and fourth synthesis filter groups can be
decomposed into M/2 polyphase filters each having a length of 2K.
The system function is represented by:
F .beta. , .alpha. ( z ) = q = 0 M / 2 - 1 .psi. a , q P .beta. ( q
) ( z M / 2 ) z - q , ##EQU00006##
where .alpha.,q.di-elect cons.{0,1,2, . . . , M/2-1};
.beta..di-elect cons.{0,1};
.psi..sub..alpha.,q=cas(2.pi..alpha.q/(M/2)) represents a kernel
function of an M/2-point IDHT; and
P.sub..beta..sup.(q)(z.sup.M/2)=.SIGMA..sub.r=0.sup.2K-1p.sub..beta.[q+r(-
M/2)]z.sup.-r(M/2) represents a q.sup.th one of the polyphase
filters in the corresponding one of the first (.beta.=0), second
(.beta.=1), third (.beta.=0) and fourth (.beta.=1) synthesis filter
groups. Using matrix-vector notations, the system function of each
of the first, second, third and fourth synthesis filter groups can
be represented by:
F.sub..beta.(z)=[F.sub..beta.,0(z)F.sub..beta.,1(z) . . .
F.sub..beta.,M/2-1(z)].sup.T=.psi.P.sub..beta.(z.sup.M/2)c(z),
where .beta..di-elect cons.{0,1}; .psi. is an M/2-by-M/2 matrix
with [.psi.].sub..alpha.,q=.psi..sub..alpha.,q, .alpha.,q.di-elect
cons.{0,1,2, . . . , M/2-1};
P.sub..beta.(z.sup.M/2)=diag[P.sub..beta..sup.(0)(z.sup.M/2)P.sub..beta..-
sup.(1)(z.sup.M/2)P.sub..beta..sup.M/2-1)(z.sup.M/2)] is a diagonal
matrix; and c(z)=[1 z.sup.-1 . . . z.sup.-(M/2-1)].sup.T. As a
result, the z-transforms of the outputs of the IDHT modules 143,
143', which are respectively represented by y.sub.0[k] and
y.sub.1[k], can be represented by:
Y.sub.0.sup.I(z)=F.sub.0.sup.T(z)X.sub.0.sup.I(z.sup.M)=[.psi.P.sub.0(z.-
sup.M/2)c(z)].sup.TX.sub.0.sup.I(z.sup.M)=c.sup.T(z)P.sub.0(z.sup.M/2).psi-
.X.sub.0.sup.I(z.sup.M),
and
Y.sub.1.sup.I(z)=F.sub.1.sup.T(z)X.sub.1.sup.I(z.sup.M)=[.psi.P.sub.1(z.-
sup.M/2)c(z)].sup.TX.sub.1.sup.I(z.sup.M)=c.sup.T(z)P.sub.1(z.sup.M/2).psi-
.X.sub.1.sup.I(z.sup.M),
where Y.sub.0.sup.I(z) represents a z-transform of
y.sub.0.sup.I[k]; Y.sub.1.sup.I(z) represents a z-transform of
y.sub.1.sup.I[k]; X.sub.i.sup.I(z) represents a z-transform of an
input of one of the synthesis filters; X.sub.i.sup.I(z.sup.M)
represents a z-transform of an input of one of the synthesis
filters which has been up-sampled by a factor of M;
X.sub.0.sup.I(z.sup.M)=[X.sub.0.sup.I(z.sup.M)X.sub.2.sup.I(z.sup.M)
. . . X.sub.M-2.sup.I(z.sup.M)].sup.T; and
X.sub.1.sup.I(z.sup.M)=[X.sub.1.sup.I(z.sup.M)X.sub.3.sup.I(z.sup.M)
. . . X.sub.M-1.sup.I(z.sup.M)]. Similarly, a z-transform of the
output of the IDHT module 153 (y.sub.0.sup.Q[k]) and a z-transform
of the output of the IDHT module 153' (y.sub.1.sup.Q[k]) also have
similar representations, and they can be represented by
Y.sub.0.sup.Q(z) and Y.sub.1.sup.Q(z), respectively. Based on the
above-mentioned results and multirate noble identities, the first
implementations of the synthesis filter banks 14, 15 (see FIGS. 2
and 3) can be transformed into the second implementations of the
synthesis filter banks 14, 15 (see FIGS. 4 and 5), which are called
polyphase implementation structures and have lower computational
complexity in comparison to the first implementations.
[0062] Referring to FIG. 4, the second implementation of the
synthesis filter bank 14 includes two IDHT modules 147, 147', a
data combination module 148, M/2 different polyphase filters 149,
M/2 different polyphase filters 149', two parallel-to-serial
conversion modules 140, 140', and an adder 146'.
[0063] The IDHT module 147 is coupled to the data separator 10 (see
FIG. 1) for receiving the M/2 even-numbered pre-processed real-part
components, and generates a first-IDHT result of M/2 points by
performing an M/2-point IDHT on the M/2 even-numbered pre-processed
real-part components.
[0064] The IDHT module 147' is coupled to the data separator 10
(see FIG. 1) for receiving the M/2 odd-numbered pre-processed
real-part components, and generates a second-IDHT result of M/2
points by performing an M/2-point IDHT on the M/2 odd-numbered
pre-processed real-part components.
[0065] The data combination module 148 is coupled to the IDHT
module 147' for receiving the second-IDHT result of M/2 points, and
performs data combination, which is similar to what is done by the
data combination and parallel-to-serial conversion module 145 shown
in FIG. 2, on the second-IDHT result of M/2 points.
[0066] Each of the M/2 polyphase filters 149 is coupled to the IDHT
module 147 for receiving a respective one of the M/2 points of the
first-IDHT result. The polyphase filters 149 respectively generate
M/2 first filtered outputs. Each of the polyphase filters 149
generates the respective one of the first filtered outputs by
sequentially performing up-sampling by a factor of two and
filtering on the respective one of the M/2 points of the first-IDHT
result received thereby. In this embodiment, the M/2 polyphase
filters 149 correspond to the first synthesis filter group as
described hereinbefore.
[0067] Each of the M/2 polyphase filters 149' is coupled to the
data combination module 148 for receiving a respective one of the
M/2 points of the second-IDHT result on which the data combination
has been performed. The polyphase filters 149' respectively
generate M/2 second filtered outputs. Each of them generates the
respective one of the second filtered outputs by sequentially
performing up-sampling by a factor of two and filtering on the
respective one of the M/2 points of the second-IDHT result (on
which the data combination has been performed) received thereby. In
this embodiment, the M/2 polyphase filters 149' correspond to the
second synthesis filter group as described hereinbefore.
[0068] The parallel-to-serial conversion module 140 is coupled to
the M/2 polyphase filters 149 for receiving the M/2 first filtered
outputs, and generates a first part of the I-channel Tx baseband
signal (s.sub.0.sup.I[k]) by sequentially performing up-sampling by
a factor of M/2 and parallel-to-serial conversion on the M/2 first
filtered outputs.
[0069] The parallel-to-serial conversion module 140' is coupled to
the M/2 polyphase filters 149' for receiving the M/2 second
filtered outputs, and generates a second part of the I-channel Tx
baseband signal (s.sub.1.sup.I[k]) by sequentially performing
up-sampling by a factor of M/2 and parallel-to-serial conversion on
the M/2 second filtered outputs.
[0070] The adder 146' is coupled to the parallel-to-serial
conversion modules 140, 140', and generates the I-channel Tx
baseband signal by adding the first part and the second part of the
I-channel Tx baseband signal together (i.e.,
s.sup.I[k]=s.sub.0.sup.I[k]+s.sub.1.sup.I[k]).
[0071] Referring to FIG. 5, the second implementation of the
synthesis filter bank 15 is similar to the second implementation of
the synthesis filter bank 14 as shown in FIG. 4, and includes two
IDHT modules 157, 157', a data combination module 158, M/2
different polyphase filters 159, M/2 different polyphase filters
159', two parallel-to-serial conversion modules 150, 150', and an
adder 156'. In this embodiment, the M/2 polyphase filters 159
correspond to the third synthesis filter group, and the M/2
polyphase filters 159' correspond to the fourth synthesis filter
group, as described hereinbefore. The synthesis filter bank 15
generates a first part and a second part of the Q-channel Tx
baseband signal (s.sub.0.sup.Q[k], s.sub.1.sup.Q[k]) in a similar
manner to that in which the synthesis filter bank 14 generates the
first part and the second part of the I-channel Tx baseband signal
(s.sub.0.sup.I[k], s.sub.1.sup.I[k]), so details thereof are not
repeated herein for the sake of brevity.
[0072] Referring to FIG. 1 again, the receiver end 2 receives a
serial I-channel Rx (meaning received) baseband signal
(first-channel Rx baseband signal) of M points and a serial
Q-channel Rx baseband signal (second-channel Rx baseband signal) of
M points, and generates a series of M complex output data symbols
based on the serial I-channel and Q-channel Rx baseband signals. It
is noted that the I-channel Rx baseband signal and the Q-channel Rx
baseband signal received by the receiver end 2 include channel
noise in addition to the I-channel Tx baseband signal and the
Q-channel Tx baseband signal transmitted at the transmitter end 1.
The receiver end 2 includes two analysis filter banks 21, 22, a
data detection unit 23, two data combiners 24, 24', two
post-processing units 25, 25', and a parallel-to-serial unit 26.
For ease of presentation, the serial I-channel Rx baseband signal
is regarded as two consecutively received serial I-channel Rx
baseband signals of M/2 points, and the serial Q-channel Rx
baseband signal is regarded as two consecutively received serial
Q-channel Rx baseband signals of M/2 points.
[0073] The analysis filter bank 21 is disposed to consecutively
receive the two serial I-channel Rx baseband signals of M/2 points,
where the M/2 points of each serial I-channel Rx baseband signal
are received in series, and generates a first part and a second
part of a filtered I-channel Rx baseband signal by performing at
least serial-to-parallel conversion, down-sampling, filtering, data
combination and DHT on the two serial I-channel Rx baseband signals
of M/2 points. In this embodiment, the first part of the filtered
I-channel Rx baseband signal has M/2 components, and corresponds to
the M/2 even-numbered pre-processed real-part components as
described for the transmitter end 1; and the second part of the
filtered I-channel Rx baseband signal has M/2 components, and
corresponds to the M/2 odd-numbered pre-processed real-part
component as described for the transmitter end 1. However, this
disclosure is not limited in this respect.
[0074] The analysis filter bank 22 is disposed to consecutively
receive the two serial Q-channel Rx baseband signals of M/2 points,
where the M/2 points of each serial Q-channel Rx baseband signal
are received in series, and generates a first part and a second
part of a filtered Q-channel Rx baseband signal by performing at
least serial-to-parallel conversion, down-sampling, filtering, data
combination and DHT on the two serial Q-channel Rx baseband signals
of M/2 points. In this embodiment, the first part of the filtered
Q-channel Rx baseband signal has M/2 components, and corresponds to
the M/2 even-numbered pre-processed imaginary-part components as
described for the transmitter end 1; and the second part of the
filtered Q-channel Rx baseband signal has M/2 components, and
corresponds to the M/2 odd-numbered pre-processed imaginary-part
component as described for the transmitter end 1. However, this
disclosure is not limited in this respect.
[0075] In this embodiment, two exemplary implementations for each
of the analysis filter banks 21, 22 are provided. FIGS. 6 and 8
respectively illustrate first and second exemplary implementations
of the analysis filter bank 21, and FIGS. 7 and 9 respectively
illustrate first and second exemplary implementations of the
analysis filter bank 22.
[0076] Referring to FIG. 6, the first implementation of the
analysis filter bank 21 includes a serial-to-parallel conversion
and data combination module 211, a parallel-to-serial conversion
module 211', two DHT modules 212, 212', M/2 prototype filters 213
(similar to the M/2 prototype filters 142), M/2 prototype filters
213' (similar to the M/2 prototype filters 142'), M/2 down-sampling
modules 214, and M/2 down-sampling modules 214'.
[0077] The serial-to-parallel conversion and data combination
module 211 is disposed to receive the two serial I-channel Rx
baseband signals of M/2 points, and consecutively outputs two
parallel I-channel Rx combination signals of M/2 points (the M/2
points of each parallel I-channel Rx combination signal are
outputted in parallel) by sequentially performing
serial-to-parallel conversion and data combination on each of the
two serial I-channel Rx baseband signals, wherein the data
combination is done in a similar manner to that performed by the
data combination and parallel-to-serial conversion module 145 as
described for the transmitter end 1.
[0078] The parallel-to-serial conversion module 211' is coupled to
the serial-to-parallel conversion and data combination module 211
for receiving the two parallel I-channel Rx combination signals of
M/2 points, and consecutively outputs two serial I-channel Rx
combination signals of M/2 points (the M/2 points of each serial
I-channel Rx combination signal are outputted in series) by
performing parallel-to-serial conversion on each of the two
parallel I-channel Rx combination signals of M/2 points.
[0079] The DHT module 212 is disposed to receive the two serial
I-channel Rx baseband signals of M/2 points, and consecutively
generates two first DHT intermediate results of M/2 points by, for
each of the two serial I-channel Rx baseband signals of M/2 points,
multiplying the serial I-channel Rx baseband signal of M/2 points
with all M/2 points of a kernel function of an M/2-point DHT, which
is similar to multiplication of an exponential kernel function at
the receiver end of a conventional DFT-based FBMC/OQAM system. For
each of the first DHT intermediate results of M/2 points, the M/2
points of the first DHT intermediate result correspond to all
elements of the product of multiplication during DHT performed by
the DHT module 212.
[0080] The DHT module 212' is coupled to the parallel-to-serial
conversion module 211' for receiving the two serial I-channel Rx
combination signals of M/2 points, and consecutively generates two
second DHT intermediate results of M/2 points by, for each of the
two serial I-channel Rx combination signals of M/2 points,
multiplying the serial first-channel Rx combination signal of M/2
points with all the M/2 points of the kernel function of an
M/2-point DHT. For each of the second DHT intermediate results of
M/2 points, the M/2 points of the second DHT intermediate result
correspond to all elements of the product of multiplication in the
DHT performed by the DHT module 212'.
[0081] Each of the M/2 prototype filters 213 is coupled to the DHT
module 212 for receiving a respective one of the M/2 points of each
of the two first DHT intermediate results. The M/2 prototype
filters 213 generate two filtered first DHT intermediate results of
M/2 points, wherein each filtered first DHT intermediate result of
M/2 points is generated by the M/2 prototype filters 213 each
performing filtering on the respective one of the M/2 points of a
corresponding one of the two first DHT intermediate results. During
the filtering, addition operations of the DHT performed by the DHT
module 212 may be performed at the same time. Operations of the
prototype filters 213 are similar to those of the prototype filters
142 as described for the transmitter end 1, so details thereof are
omitted herein for the sake of brevity.
[0082] Each of the M/2 prototype filters 213' is coupled to the DHT
module 212' for receiving a respective one of the M/2 points of
each of the two second DHT intermediate results. The M/2 prototype
filters 213' generate two filtered second DHT intermediate results
of M/2 points, wherein each filtered second DHT intermediate result
of M/2 points is generated by the M/2 prototype filters 213' each
performing filtering on the respective one of the M/2 points of a
corresponding one of the two second DHT intermediate results.
During the filtering, addition of the DHT performed by the DHT
module 212' may be performed at the same time. Operations of the
prototype filters 213' are similar to those of the prototype
filters 142' as described for the transmitter end 1, so details
thereof are omitted herein for the sake of brevity.
[0083] It is noted that each of the M/2 prototype filters 213
(similar to each of the M/2 prototype filters 142) is orthogonal or
nearly orthogonal to each of the M/2 prototype filters 213'
(similar to each of the M/2 prototype filters 142'), so as to
lessen ISI and ICI. In this embodiment, p.sub.0[k] and p.sub.1[k]
described for the synthesis filter banks 14, 15 are used for each
of the M/2 prototype filters 213 and each of the M/2 prototype
filters 213', respectively.
[0084] The M/2 down-sampling modules 214 are respectively coupled
to the M/2 prototype filters 213 for respectively receiving the M/2
points of each of the two filtered first DHT intermediate results,
and generate the first part of the filtered I-channel Rx baseband
signal by each performing, for each of the two filtered first DHT
intermediate results, down-sampling on the respective one of the
M/2 points of the filtered first DHT intermediate result by a
factor of M.
[0085] The M/2 down-sampling modules 214' are respectively coupled
to the M/2 prototype filters 213' for respectively receiving the
M/2 points of each of the two filtered second DHT intermediate
results, and generate the second part of the filtered I-channel Rx
baseband signal by each performing, for each of the two filtered
second DHT intermediate results, down-sampling on the respective
one of the M/2 points of the filtered second DHT intermediate
result by a factor of M.
[0086] Referring to FIG. 7, the first implementation of the
analysis filter bank 22 is shown to be similar to the first
implementation of the analysis filter bank 21 (see FIG. 6), and
includes a serial-to-parallel conversion and data combination
module 221, a parallel-to-serial conversion module 221', two DHT
modules 222, 222', M/2 prototype filters 223, M/2 prototype filters
223', M/2 down-sampling modules 224, and M/2 down-sampling modules
224'. The analysis filter bank 22 generates the first part and the
second part of the filtered Q-channel Rx baseband signal in a
similar manner to that in which the analysis filter bank 21
generates the first part and the second part of the filtered
I-channel Rx baseband signal, so details thereof are not repeated
herein for the sake of brevity.
[0087] In this embodiment, each of the analysis filter banks 21, 22
may be implemented by an equivalent structure that includes M
analysis filters. The analysis filter bank 21 includes a first
analysis filter group of M/2 analysis filters respectively
corresponding to M/2 subcarriers for the M/2 components of the
first part of the filtered I-channel Rx baseband signal, and a
second analysis filter group of M/2 analysis filters respectively
corresponding to M/2 subcarriers for the M/2 components of the
second part of the filtered I-channel Rx baseband signal. The
analysis filter bank 22 includes a third analysis filter group of
M/2 analysis filters respectively corresponding to M/2 subcarriers
for the M/2 components of the first part of the filtered Q-channel
Rx baseband signal, and a fourth analysis filter group of M/2
analysis filters respectively corresponding to M/2 subcarriers for
the M/2 components of the second part of the filtered Q-channel Rx
baseband signal. For each of the analysis filter banks 21, 22, one
of the analysis filters that corresponds to a
(2.alpha.+.beta.).sup.th one of the subcarriers is represented by
p.sub..beta.[k]cas(2.pi..alpha.k/(M/2)) with the same length as
that of each of the prototype filters 213, 213', 223, 223', where
.alpha..di-elect cons.{0,1,2, . . . ,M/2-1}, .beta..di-elect
cons.{0,1} and k 0, 1, 2, . . . , L-1. Each of the first, second,
third and fourth analysis filter groups has a system function
G.sub..beta.,.alpha.(z) that is obtained from a z-transform of
p.sub..beta.[k]cas(2.pi..alpha.k/(M/2)), k=0, 1, 2, . . . , L-1.
Similar to those described for the transmitter end 1, each of the
first, second, third and fourth analysis filter groups can be
decomposed into M/2 polyphase filters each having a length of 2K.
The system function is represented by:
G .beta. , .alpha. ( z ) = q = 0 M / 2 - 1 .psi. .alpha. , q P
.beta. ( q ) ( z M / 2 ) z - q , ##EQU00007##
where .alpha.,q.di-elect cons.{0,1,2, . . . , M/2-1};
.beta..di-elect cons.{0,1};
.psi..sub..alpha.,q=cas(2.pi..alpha.q/(M/2)) represents a kernel
function of an M/2-point DHT; and
P.sub..beta..sup.(q)(z.sup.M/2)=.SIGMA..sub.r=0.sup.2K-1p.sub..beta.[q+r(-
M/2)]z.sup.-r(M/2) represents a q.sup.th one of the polyphase
filters in the corresponding one of the first (.beta.=0), second
(.beta.=1), third (.beta.=0) and fourth (.beta.=1) analysis filter
groups. Using matrix-vector notations, the first part and the
second part of the filtered I-channel Rx baseband signal can be
represented by:
{tilde over (X)}.sub.0.sup.I(z.sup.M)=[.psi.P.sub.0(z.sup.M/2)c(z)]
.sub.0.sup.I(z)
and
{tilde over (X)}.sub.1.sup.I(z.sup.M)=[.psi.P.sub.1(z.sup.M/2)c(z)]
.sub.1.sup.I(z)
where {tilde over (X)}.sub.0.sup.I(z.sup.M) consists of M/2
elements with each representing a z-transform of one point of the
first part of the filtered I-channel Rx baseband signal; {tilde
over (X)}.sub.1.sup.I(z.sup.M) consists of M/2 elements with each
representing a z-transform of one point of the second part of the
filtered I-channel Rx baseband signal; .psi. is an M/2-by-M/2
matrix with [.psi.].sub..alpha.,q=.psi..sub..alpha.,q,
.alpha.,q.di-elect cons.{0,1,2, . . . , M/2-1};
P.sub..beta.(z.sup.M/2)=diag[P.sub..beta..sup.(0)(z.sup.M/2)P.sub..beta..-
sup.(1)(z.sup.M/2) . . . P.sub..beta..sup.(M/2-1)(z.sup.M/2)] is a
diagonal matrix, .beta..di-elect cons.{0,1}; c(z)=[1 z.sup.-1 . . .
z.sup.-(M/2-1)].sup.T; .sub.0.sup.I(z) represents a z-transform
corresponding to the filtered I-channel Rx baseband signal; and
.sub.1.sup.I(z) represents a z-transform corresponding to the
filtered I-channel Rx combination signal. Similarly, z-transforms
of the first part and second part of the filtered Q-channel Rx
baseband signal also have similar representations, and can be
represented by {tilde over (X)}.sub.0.sup.Q(z.sup.M) and {tilde
over (X)}.sub.1.sup.Q(z.sup.M), respectively. Based on the
abovementioned results and multirate noble identities, the first
implementations of the analysis filter banks 21, 22 (see FIGS. 6
and 7) can be transformed into the second implementations of the
analysis filter banks 21, 22 (see FIGS. 8 and 9), which are called
polyphase filtering architecture and which have lower computation
complexity in comparison to the first implementations.
[0088] Referring to FIG. 8, the second implementation of the
analysis filter bank 21 includes two serial-to-parallel conversion
modules 216, 216', M/2 different polyphase filters 217, M/2
different polyphase filters 217', a data combination module 218,
and two DHT modules 219, 219'.
[0089] The serial-to-parallel conversion module 216 is disposed to
receive the two serial I-channel Rx baseband signals of M/2 points,
and consecutively outputs two parallel first down-sampled I-channel
Rx baseband signals of M/2 points (the M/2 points of each parallel
first down-sampled I-channel Rx baseband signal are outputted in
parallel) by sequentially performing serial-to-parallel conversion
and down-sampling by a factor of M/2 on the serial I-channel Rx
baseband signals of M/2 points.
[0090] The serial-to-parallel conversion module 216' is disposed to
receive the two serial I-channel Rx baseband signals of M/2 points,
and consecutively outputs two parallel second down-sampled
I-channel Rx baseband signals of M/2 points (the M/2 points of each
parallel second down-sampled I-channel Rx baseband signal are
outputted in parallel) by sequentially performing
serial-to-parallel conversion and down-sampling by a factor of M/2
on the serial I-channel Rx baseband signals of M/2 points.
[0091] Each of the M/2 polyphase filters 217 is coupled to the
serial-to-parallel conversion module 216 for receiving a respective
one of the M/2 points of each of the two parallel first
down-sampled I-channel Rx baseband signals. The M/2 polyphase
filters 217 generate a filtered first down-sampled I-channel Rx
baseband signal of M/2 points in parallel, wherein one point of the
filtered first down-sampled I-channel Rx baseband signal is
generated by one of the M/2 polyphase filters 217 sequentially
performing filtering and down-sampling by a factor of two on a
sequence of signal points of the respective one of the M/2 points
of each received parallel first down-sampled I-channel Rx baseband
signal, where the sequence of signal points are consecutively
received by the one of the M/2 polyphase filters 217 at consecutive
time points. In this embodiment, the M/2 polyphase filters 217
correspond to the first analysis filter group as described
hereinbefore.
[0092] Each of the M/2 polyphase filters 217' is coupled to the
serial-to-parallel conversion module 216' for receiving a
respective one of the M/2 points of each of the two parallel second
down-sampled I-channel Rx baseband signals. The M/2 polyphase
filters 217' generate a filtered second down-sampled I-channel Rx
baseband signal of M/2 points in parallel, wherein one point of the
filtered second down-sampled I-channel Rx baseband signal is
generated by one of the M/2 polyphase filters 217' sequentially
performing filtering and down-sampling by a factor of two on a
sequence of signal points of the respective one of the M/2 points
of each received parallel second down-sampled I-channel Rx baseband
signal, where the sequence of signal points are consecutively
received by the one of the M/2 polyphase filters 217' at
consecutive time points. In this embodiment, the M/2 polyphase
filters 217' correspond to the second analysis filter group as
described hereinbefore.
[0093] The data combination module 218 is coupled to the M/2
polyphase filters 217' for receiving the filtered second
down-sampled I-channel Rx baseband signal of M/2 points, and
generates a down-sampled I-channel Rx combination signal of M/2
points by performing data combination on the received filtered
signal of M/2 points, wherein the data combination is done in a
similar manner to that performed by the data combination and
parallel-to-serial conversion module 145 as described for the
transmitter end 1.
[0094] The DHT module 219 is coupled to the M/2 polyphase filters
217 for receiving the filtered first down-sampled I-channel Rx
baseband signal of M/2 points, and generates the first part of the
filtered I-channel baseband signal by performing an M/2-point DHT
on the received filtered signal of M/2 points.
[0095] The DHT module 219' is coupled to the data combination
module 218 for receiving the filtered down-sampled I-channel Rx
combination signal of M/2 points, and generates the second part of
the filtered I-channel Rx baseband signal by performing an
M/2-point DHT on the received filtered signal of M/2 points.
[0096] Referring to FIG. 9, the second implementation of the
analysis filter bank 22 is shown to be similar to the second
implementation of the analysis filter bank 21 (see FIG. 8), and
includes two serial-to-parallel conversion modules 226, 226', M/2
different polyphase filters 227, M/2 different polyphase filters
227', a data combination module 228, and two DHT modules 229, 229'.
In this embodiment, the M/2 polyphase filters 227 correspond to the
third analysis filter group, and the M/2 polyphase filters 227'
correspond to the fourth analysis filter group, as described
hereinbefore. The analysis filter bank 22 generates the first part
and the second part of the filtered Q-channel Rx baseband signal in
a similar manner to that the analysis filter bank 21 generates the
first part and the second part of the filtered I-channel Rx
baseband signal, so details thereof are not repeated herein for the
sake of brevity.
[0097] Referring back to FIG. 1, the data detection unit 23 is
coupled to the analysis filter banks 21, 22 for receiving the first
and second parts of the filtered I-channel Rx baseband signal, and
the first and second parts of the filtered Q-channel Rx baseband
signal. The data detection unit 23 generates M/2 first I-channel
detection results corresponding to the first part of the filtered
I-channel Rx baseband signal and M/2 first Q-channel detection
results corresponding to the first part of the filtered Q-channel
Rx baseband signal by performing joint detection on the first parts
of the filtered I-channel and Q-channel Rx baseband signals; and
generates M/2 second I-channel detection results corresponding to
the second part of the filtered I-channel Rx baseband signal and
M/2 second Q-channel detection results corresponding to the second
part of the filtered Q-channel Rx baseband signal by performing
joint detection on the second parts of the filtered I-channel and
Q-channel Rx baseband signals. The data detection unit 23 may use,
for example, joint zero-forcing, joint minimum mean-squared error,
joint maximum likelihood algorithms, and so on, to perform joint
detection of data symbols.
[0098] The data combiner 24 is coupled to the data detection unit
23, and forms M I-channel detection outcomes in parallel by putting
the M/2 first I-channel detection results at even-numbered output
positions and the M/2 second I-channel detection results at
odd-numbered output positions.
[0099] The data combiner 24' is coupled to the data detection unit
23, and forms M Q-channel detection outcomes by putting the M/2
first Q-channel detection results at even-number output positions
and the M/2 second Q-channel detection results at odd-numbered
positions.
[0100] The post-processing unit 25 is a post-processor coupled to
the data combiner 24 for receiving the M I-channel detection
outcomes, and generates M first post-processed components based on
the M I-channel detection outcomes and a post-processing model.
[0101] The post-processing unit 25' is a post-processor coupled to
the data combiner 24' for receiving the M Q-channel detection
outcomes, and generates M second post-processed components based on
the M Q-channel detection outcomes and the post-processing model.
It is noted that the post-processing model is an inverse of the
pre-processing model used by the pre-processing units 13, 13' of
the transmitter end 1 (see FIG. 1).
[0102] The parallel-to-serial unit 26 is coupled to the
post-processing units 25, 25', and outputs the M complex output
data symbols in series by performing parallel-to-serial conversion
on the M first post-processed components and the M second
post-processed components, where each of the complex output data
symbols includes a real part and an imaginary part, each of the
first post-processed components corresponds to the real part of a
respective one of the complex output data symbols, and each of the
second post-processed components corresponds to the imaginary part
of a respective one of the complex output data symbols.
[0103] FIG. 10 illustrates some simulation results that show
performance comparisons among the embodiment of this disclosure
(DHT-FBMC/QAM) and two conventional filter bank multicarrier
schemes (DFT-FBMC/OQAM and DFT-FBMC/QAM) in terms of the bit error
rate (BER) and a signal-to-noise ratio (SNR), where the SNR is
defined as a ratio of the signal energy per bit to the noise power
spectral density (E.sub.b/N.sub.0) at the channel input.
[0104] The simulation environment and parameter settings used for
simulations corresponding to FIG. 10 are listed in Table 1. The
PHYDYAS filter is used as the prototype filter p.sub.0[k] for each
of the even-numbered subcarriers in the DHT-FBMC/QAM and
DFT-FBMC/QAM schemes, and the prototype filter p.sub.1[k] (nearly
orthogonal to p.sub.0[k]) for each of the odd-numbered subcarriers
is with 61 nonzero taps in the frequency domain, which is designed
based on minimizing self-interference. In contrast, the PHYDYAS
filter is used as the prototype filter for each of the subcarriers
in the DFT-FBMC/OQAM system. It can be seen from FIG. 10 that, for
a case using quadrature phase shift keying (QPSK) modulation for
input data symbols, the DHT-FBMC/QAM scheme achieves much better
BER performance than the DFT-FBMC/OQAM system and the DFT-FBMC/QAM
system. For a case using 16 quadrature amplitude modulation
(16-QAM) for input data symbols, the BER performance of the
DHT-FBMC/QAM scheme is still better than that of the DFT-FBMC/QAM
system, but is comparable to that of the DFT-FBMC/OQAM system.
TABLE-US-00001 TABLE 1 Number of Subcarriers (M) 1024 Overlapping
Factor (K) 4 Number of Trials 500 (100 FBMC Frames Per Trial)
Modulation Type and QPSK/16QAM and (2, 1, 7) Convolutional Code
Channel Encoding Prototype Filters DFT-FMBC/OQAM PHYDYAS Filter
(Length L = KM) DFT-FBMC/QAM Even Subcarriers PHYDYAS Filter Odd
Subcarriers 61 Non-Zero Taps (Frequency Domain) DHT-FBMC/QAM Even
Subcarriers PHYDYAS Filter Odd Subcarriers 61 Non-Zero Taps
(Frequency Domain) Channel Bandwidth/Sample 10 MHz/100 ns Period
Channel Model ITU Pedestrian A Relative Delays (ns): [0, 110, 190,
410] (Zero-Mean Complex Additive Channel Power Profile (dB): [0,
-9.7, -19.2, -22.8] White Gaussian Noise) Detection Method Minimum
Mean-Squared Error (MMSE) Equalization + Soft Demapping + Viterbi
Decoding
[0105] Table 2 presents a comparison of computational complexity
for the DHT-FBMC/QAM (the embodiment of this disclosure),
DFT-FBMC/OQAM and DFT-FBMC/QAM schemes, in terms of the number of
real multiplications required for transmission/reception of M-point
complex QAM data symbols. For simplicity, the data detection part
is not considered in the comparison, where the complexities
required for data detection in these three schemes are similar when
minimum mean-squared error algorithms are adopted. It can be seen
from Table 2 that the total number of real multiplications for the
DHT-FBMC/QAM scheme is the same as that for the DFT-FBMC/OQAM
scheme, but is lower than that for the DFT-FBMC/QAM scheme.
[0106] To sum up, the embodiment of the FBMC communication system
based on the DHT (referred to as DHT-FBMC/QAM communication system)
according to this disclosure involves a real-valued IDHT procedure
for the synthesis filter banks 14, 15 of the transmitter end 1 and
a real-valued DHT procedure for the analysis filter banks 21, 22 of
the receiver end 2. Since the DHT and IDHT have identical
mathematic formulations (except for scaling constants), they can be
realized using the same software/hardware unit. It is also shown by
simulation results that the DHT-FBMC/QAM communication system
achieves excellent transmission performance, because of the
exploitation of distinct channel diversity gain within
mirror-symmetrical subcarriers. In comparison to the conventional
DFT-FBMC/OQAM and DFT-FBMC/QAM schemes which require complex-valued
IDFT procedures at their transmitter ends and complex-valued DFT
procedures at their receiver ends, the DHT-FBMC/QAM system has
advantages in terms of implementation and performance. Moreover,
the use of QAM, rather than OQAM, allows the DHT-FBMC/QAM system to
be easily combined with existing MIMO techniques, such as space
time block coding, for further performance improvement.
TABLE-US-00002 TABLE 2 (.mu. = log.sub.2 M) Scheme Function
DFT-FBMC/OQAM DFT-FBMC/QAM DHT-FBMC/QAM Data 4M 4M 4M
Pre-processing IDFT/IDHT for 2[(M/2)(.mu. - 1) - 3(M/2)]
2[(M/2)(.mu. - 1) - 3(M/2)] 2 [(M/2)(.mu. - 1) - 3(M/2)]
Multicarrier Modulation Synthesis 4KM 4KM 4KM Polyphase Filtering
Odd-Part Data 0 4M 4M Combination/ Phase Rotation Analysis 4KM 4KM
4KM Polyphase Filtering DFT/DHT for 2(M.mu. - 3M) 2[(M/2)(.mu. - 1)
- 3(M/2)] 2 [(M/2)(.mu. - 1) - 3(M/2)] Multicarrier Demodulation
Data 8M 4M 4M Post-processing Total 3M.mu. + 8KM + 2M 2M.mu. + 8KM
+ 4M 2 M.mu. + 8KM + 4M
[0107] In the description above, for the purposes of explanation,
numerous specific details have been set forth in order to provide a
thorough understanding of the embodiment(s). It will be apparent,
however, to one skilled in the art, that one or more other
embodiments may be practiced without some of these specific
details. It should also be appreciated that reference throughout
this specification to "one embodiment," "an embodiment," an
embodiment with an indication of an ordinal number and so forth
means that a particular feature, structure, or characteristic may
be included in the practice of the disclosure. It should be further
appreciated that in the description, various features are sometimes
grouped together in a single embodiment, figure, or description
thereof for the purpose of streamlining the disclosure and aiding
in the understanding of various inventive aspects, and that one or
more features or specific details from one embodiment may be
practiced together with one or more features or specific details
from another embodiment, where appropriate, in the practice of the
disclosure.
[0108] While the disclosure has been described in connection with
what is (are) considered the exemplary embodiment(s), it is
understood that this disclosure is not limited to the disclosed
embodiment(s) but is intended to cover various arrangements
included within the spirit and scope of the broadest interpretation
so as to encompass all such modifications and equivalent
arrangements.
* * * * *