U.S. patent application number 16/403706 was filed with the patent office on 2020-05-07 for array substrate, method for making the array substrate, and display apparatus.
The applicant listed for this patent is ORDOS YUANSHENG OPTOELECTRONICS CO., LTD. BOE TECHNOLOGY GROUP CO., LTD.. Invention is credited to Jun FAN, Yongqiang ZHANG.
Application Number | 20200144301 16/403706 |
Document ID | / |
Family ID | 64807102 |
Filed Date | 2020-05-07 |
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United States Patent
Application |
20200144301 |
Kind Code |
A1 |
ZHANG; Yongqiang ; et
al. |
May 7, 2020 |
ARRAY SUBSTRATE, METHOD FOR MAKING THE ARRAY SUBSTRATE, AND DISPLAY
APPARATUS
Abstract
This disclosure discloses an array substrate, a method for
making the same, and a display apparatus. The array substrate
comprises a display area and a peripheral area around the display
area. The method comprises: forming an active layer of a low
temperature polysilicon TFT in the peripheral area of the array
substrate; forming a gate of a oxide TFT disposed in the same layer
as a source and a drain of the low temperature polysilicon TFT in
the display area of the array substrate, and forming an active
layer of the oxide TFT electrically insulated from the gate of the
oxide TFT above the gate of the oxide TFT; forming a source and a
drain of the oxide TFT on the active layer of the oxide TFT.
Inventors: |
ZHANG; Yongqiang; (Beijing,
CN) ; FAN; Jun; (Beijing, CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
BOE TECHNOLOGY GROUP CO., LTD. |
Ordos
Beijing |
|
CN
CN |
|
|
Family ID: |
64807102 |
Appl. No.: |
16/403706 |
Filed: |
May 6, 2019 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G02F 2001/136295
20130101; H01L 27/1259 20130101; H01L 29/42372 20130101; H01L
27/127 20130101; H01L 27/1251 20130101; H01L 27/1225 20130101; G06F
3/047 20130101; H01L 27/124 20130101; G02F 2001/133388
20130101 |
International
Class: |
H01L 27/12 20060101
H01L027/12 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 1, 2018 |
CN |
201811294729.9 |
Claims
1. A method for fabricating an array substrate comprising a display
area and a peripheral area around the display area, the method
comprising: forming an active layer of a low temperature
polysilicon thin film transistor (TFT) in the peripheral area,
forming a gate of the low temperature polysilicon TFT above the
active layer of the low temperature polysilicon TFT, and forming a
source and a drain of the low temperature polysilicon TFT
electrically connected to the active layer of the low temperature
polysilicon TFT; forming a gate of an oxide TFT disposed in the
same layer as the source and the drain of the low temperature
polysilicon TFT in the display area, and forming an active layer of
the oxide TFT electrically insulated from the gate of the oxide TFT
above the gate of the oxide TFT; forming a source and a drain of
the oxide TFT on the active layer of the oxide TFT by using wet
etching.
2. The method for fabricating the array substrate according to
claim 1, wherein forming the gate of the low temperature
polysilicon TFT above the active layer of the low temperature
polysilicon TFT, and forming the source and the drain of the low
temperature polysilicon TFT electrically connected to the active
layer of the low temperature polysilicon TFT comprises: forming a
first insulation layer on the active layer of the low temperature
polysilicon TFT, forming a gate metal layer on the first insulation
layer, and patterning the gate metal layer in the peripheral area
to form the gate of the low temperature polysilicon TFT; forming an
interlayer dielectric layer on the gate metal layer, forming a
first metal layer on the interlayer dielectric layer, and
patterning the first metal layer in the peripheral area to form the
source and the drain of the low temperature polysilicon TFT;
wherein the source and the drain of the low temperature polysilicon
TFT are electrically connected to the active layer of the low
temperature polysilicon TFT through vias.
3. The method for fabricating the array substrate according to
claim 2, further comprising: while forming the source and the drain
of the low temperature polysilicon TFT electrically connected to
the active layer of the low temperature polysilicon TFT, forming a
source wiring of the oxide TFT disposed in the same layer as the
source and the drain of the low temperature polysilicon TFT in the
display area, the source wiring of the oxide TFT being electrically
connected to the source of the oxide TFT positioned above the
source wiring through a via.
4. The method for fabricating the array substrate according to
claim 3, further comprising: while forming the gate of the low
temperature polysilicon TFT above the active layer of the low
temperature polysilicon TFT, forming a gate wiring of the oxide TFT
disposed in the same layer as the gate of the low temperature
polysilicon TFT in the display area, wherein the gate wiring of the
oxide TFT is connected to the gate of the oxide TFT through a via
in the interlayer dielectric layer.
5. The method for fabricating the array substrate according to
claim 3, wherein forming the source wiring of the oxide TFT
disposed in the same layer as the source and the drain of the low
temperature polysilicon TFT in the display area comprises:
patterning the first metal layer in the display area to form the
source wiring of the oxide TFT; while patterning the first metal
layer, forming the source wiring of the oxide TFT and the source
and the drain of the low temperature polysilicon TFT using a single
patterning process.
6. The method for fabricating the array substrate according to
claim 4, wherein forming the gate of the oxide TFT disposed in the
same layer as the source and the drain of the low temperature
polysilicon TFT in the display area comprises: while patterning the
first metal layer, forming the source wiring of the oxide TFT, the
source and the drain of the low temperature polysilicon TFT, and
the gate of the oxide TFT using a same patterning process.
7. The method for fabricating the array substrate according to
claim 3, wherein forming the active layer of the oxide TFT
electrically insulated from the gate of the oxide TFT above the
gate of the oxide TFT comprises: forming a second insulation layer
on the source wiring of the oxide TFT and the gate of the oxide TFT
and depositing the active layer of the oxide TFT on the second
insulation layer in the display area, wherein a material of the
active layer of the oxide TFT comprises a metal oxide or a metal
oxynitride.
8. The method for fabricating the array substrate according to
claim 7, wherein forming the source and the drain of the oxide TFT
on the active layer of the oxide TFT by using wet etching
comprises: forming a second metal layer on the second insulation
layer in the display area, patterning the second metal layer by
using wet etching to form the source and the drain of the oxide
TFT, wherein the source and the drain of the oxide TFT cover ends
of the active layer of the oxide TFT, and wherein the source of the
oxide TFT is connected to the source wiring of the oxide TFT
through a via in the second insulation layer.
9. The method for fabricating the array substrate according to
claim 8, further comprising: forming a first protection layer, a
first planarization layer, a common electrode of the oxide TFT, a
second protection layer, and a pixel electrode of the oxide TFT on
the source and the drain of the oxide TFT in this order, wherein
the pixel electrode is electrically connected to the drain of the
oxide TFT.
10. The method for fabricating the array substrate according to
claim 9, the method further comprising: after forming the first
metal layer and before forming the second insulation layer, forming
a touch wiring of the oxide TFT on the interlayer dielectric layer
in the display area, wherein the touch wiring of the oxide TFT is
electrically connected to the common electrode of the oxide
TFT.
11. The method for fabricating the array substrate according to
claim 9, the method further comprising: after forming the first
planarization layer and before forming the second protection layer,
forming a third protection layer, a touch wiring of the oxide TFT,
and a second planarization layer on the first planarization layer
in the display area in this order, wherein the touch wiring of the
oxide TFT is electrically connected to the common electrode.
12. An array substrate, comprising: at least one low temperature
polysilicon thin film transistor (TFT) in a peripheral area of the
array substrate, the low temperature polysilicon TFT comprising: an
active layer of the low temperature polysilicon TFT, a gate of the
low temperature polysilicon TFT formed above the active layer of
the low temperature polysilicon TFT, and a source and a drain of
the low temperature polysilicon TFT electrically connected to the
active layer of the low temperature polysilicon TFT; and at least
one oxide TFT in a display area of the array substrate, the oxide
TFT comprising: a gate of the oxide TFT disposed in the same layer
as the source and the drain of the low temperature polysilicon TFT,
an active layer of the oxide TFT electrically insulated from and
above the gate of the oxide TFT, and a source and a drain of the
oxide TFT formed on the active layer of the oxide TFT by using wet
etching.
13. The array substrate according to claim 12, further comprising a
source wiring of the oxide TFT, wherein the source wiring of the
oxide TFT is electrically connected to the source of the oxide TFT
through a via.
14. The array substrate according to claim 12, further comprising a
gate wiring of the oxide TFT, wherein the gate wiring of the oxide
TFT is electrically connected to the gate of the oxide TFT through
a via.
15. The array substrate according to claim 12, further comprising a
first protection layer, a first planarization layer, a common
electrode of the oxide TFT, a second protection layer, and a pixel
electrode of the oxide TFT in the display area formed above the
source and the drain of the oxide TFT in this order, wherein the
pixel electrode is electrically connected to the drain of the oxide
TFT.
16. The array substrate according to claim 15, further comprising a
touch wiring of the oxide TFT in the display area, wherein the
touch wiring of the oxide TFT is electrically connected to the
common electrode of the oxide TFT.
17. The array substrate according to claim 12, further comprising a
first protection layer, a first planarization layer, a third
protection layer, a touch wiring of the oxide TFT, a second
planarization, a common electrode of the oxide TFT, a second
protection layer, and a pixel electrode of the oxide TFT in the
display area formed above the source and the drain of the oxide TFT
in this order, wherein the common electrode of the oxide TFT is
electrically connected to the touch wiring of the oxide TFT, and
wherein the pixel electrode is electrically connected to the drain
of the oxide TFT.
18. The array substrate according to claim 12, wherein the active
layer of the low temperature polysilicon TFT comprises a
polysilicon, and wherein the active layer of the oxide TFT
comprises a metal oxide or a metal oxynitride.
19. A display apparatus comprising the array substrate according to
claim 12.
20. The display apparatus according to claim 19, wherein the active
layer of the low temperature polysilicon TFT comprises a
polysilicon, and wherein the active layer of the oxide TFT
comprises a metal oxide or a metal oxynitride.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to Chinese Patent
Application 201811294729.9, filed on Nov. 1, 2018.
TECHNICAL FIELD
[0002] This disclosure relates to an array substrate, a method for
making the array substrate, and a display apparatus.
BACKGROUND
[0003] In the field of display technologies, a thin film transistor
liquid crystal display (TFT-LCD) has advantages such as light
weight, thin profile, low power consumption, high brightness, and
high image quality, which occupies an important status in the field
of flat-panel display. In particular, a flat-panel display
apparatus with large size, high resolution, and high image quality,
such as a liquid crystal television, has dominated the current
flat-panel display market.
[0004] With the development of the TFT-LCD technology, people's
requirements for the low power consumption performance of display
apparatuses become higher and higher. Therefore, there exists a
need for an improved TFT-LCD.
SUMMARY
[0005] In view of the above, embodiments of this disclosure provide
an array substrate and a method for making the array substrate, and
a display apparatus.
[0006] According to an aspect of the present disclosure, there is
provided a method for fabricating an array substrate comprising a
display area and a peripheral area around the display area, the
method comprising: forming an active layer of a low temperature
polysilicon thin film transistor (TFT) in the peripheral area,
forming a gate of the low temperature polysilicon TFT above the
active layer of the low temperature polysilicon TFT, and forming a
source and a drain of the low temperature polysilicon TFT
electrically connected to the active layer of the low temperature
polysilicon TFT; forming a gate of an oxide TFT disposed in the
same layer as the source and the drain of the low temperature
polysilicon TFT in the display area, and forming an active layer of
the oxide TFT electrically insulated from the gate of the oxide TFT
above the gate of the oxide TFT; forming a source and a drain of
the oxide TFT on the active layer of the oxide TFT by using wet
etching.
[0007] In an example, forming the gate of the low temperature
polysilicon TFT above the active layer of the low temperature
polysilicon TFT, and forming the source and the drain of the low
temperature polysilicon TFT electrically connected to the active
layer of the low temperature polysilicon TFT comprises: forming a
first insulation layer on the active layer of the low temperature
polysilicon TFT, forming a gate metal layer on the first insulation
layer, and patterning the gate metal layer in the peripheral area
to form the gate of the low temperature polysilicon TFT; forming an
interlayer dielectric layer on the gate metal layer, forming a
first metal layer on the interlayer dielectric layer, and
patterning the first metal layer in the peripheral area to form the
source and the drain of the low temperature polysilicon TFT;
wherein the source and the drain of the low temperature polysilicon
TFT are electrically connected to the active layer of the low
temperature polysilicon TFT through vias.
[0008] In an example, the method for fabricating the array
substrate further comprises: while forming the source and the drain
of the low temperature polysilicon TFT electrically connected to
the active layer of the low temperature polysilicon TFT, forming a
source wiring of the oxide TFT disposed in the same layer as the
source and the drain of the low temperature polysilicon TFT in the
display area, the source wiring of the oxide TFT being electrically
connected to the source of the oxide TFT positioned above the
source wiring through a via.
[0009] In an example, the method for fabricating the array
substrate further comprises: while forming the gate of the low
temperature polysilicon TFT above the active layer of the low
temperature polysilicon TFT, forming a gate wiring of the oxide TFT
disposed in the same layer as the gate of the low temperature
polysilicon TFT in the display area, wherein the gate wiring of the
oxide TFT is connected to the gate of the oxide TFT through a via
in the interlayer dielectric layer.
[0010] In an example, forming the source wiring of the oxide TFT
disposed in the same layer as the source and the drain of the low
temperature polysilicon TFT in the display area comprises:
patterning the first metal layer in the display area to form the
source wiring of the oxide TFT; while patterning the first metal
layer, forming the source wiring of the oxide TFT and the source
and the drain of the low temperature polysilicon TFT using a single
patterning process.
[0011] In an example, forming the gate of the oxide TFT disposed in
the same layer as the source and the drain of the low temperature
polysilicon TFT in the display area comprises: while patterning the
first metal layer, forming the source wiring of the oxide TFT, the
source and the drain of the low temperature polysilicon TFT, and
the gate of the oxide TFT using a same patterning process.
[0012] In an example, the method for fabricating the array
substrate further comprises: forming the active layer of the oxide
TFT electrically insulated from the gate of the oxide TFT above the
gate of the oxide TFT comprises: forming a second insulation layer
on the source wiring of the oxide TFT and the gate of the oxide TFT
and depositing the active layer of the oxide TFT on the second
insulation layer in the display area, wherein a material of the
active layer of the oxide TFT comprises a metal oxide or a metal
oxynitride.
[0013] In an example, the method for fabricating the array
substrate further comprises: forming the source and the drain of
the oxide TFT on the active layer of the oxide TFT by using wet
etching comprises: forming a second metal layer on the second
insulation layer in the display area, patterning the second metal
layer by using wet etching to form the source and the drain of the
oxide TFT, wherein the source and the drain of the oxide TFT cover
the ends of the active layer of the oxide TFT, and wherein the
source of the oxide TFT is connected to the source wiring of the
oxide TFT through a via in the second insulation layer.
[0014] In an example, the method for fabricating the array
substrate further comprises: forming a first protection layer, a
first planarization layer, a common electrode of the oxide TFT, a
second protection layer, and a pixel electrode of the oxide TFT on
the source and the drain of the oxide TFT in this order, wherein
the pixel electrode is electrically connected to the drain of the
oxide TFT.
[0015] In an example, the method for fabricating the array
substrate further comprises: after forming the first metal layer
and before forming the second insulation layer, forming a touch
wiring of the oxide TFT on the interlayer dielectric layer in the
display area, wherein the touch wiring of the oxide TFT is
electrically connected to the common electrode of the oxide
TFT.
[0016] In an example, the method for fabricating the array
substrate further comprises: after forming the first planarization
layer and before forming the second protection layer, forming a
third protection layer, a touch wiring of the oxide TFT, and a
second planarization layer on the first planarization layer in the
display area in this order, wherein the touch wiring of the oxide
TFT is electrically connected to the common electrode.
[0017] According to another aspect of the present disclosure, there
is provided an array substrate, comprising: at least one low
temperature polysilicon (thin film transistor) TFT in a peripheral
area of the array substrate, the low temperature polysilicon TFT
comprising: an active layer of the low temperature polysilicon TFT,
a gate of the low temperature polysilicon TFT formed above the
active layer of the low temperature polysilicon TFT, and a source
and a drain of the low temperature polysilicon TFT electrically
connected to the active layer of the low temperature polysilicon
TFT; and at least one oxide TFT in a display area of the array
substrate, the oxide TFT comprising: a gate of the oxide TFT
disposed in the same layer as the source and the drain of the low
temperature polysilicon TFT, an active layer of the oxide TFT
electrically insulated from and above the gate of the oxide TFT,
and a source and a drain of the oxide TFT formed on the active
layer of the oxide TFT by using wet etching.
[0018] In an example, the array substrate further comprises a
source wiring of the oxide TFT, wherein the source wiring of the
oxide TFT is electrically connected to the source of the oxide TFT
through a via.
[0019] In an example, the array substrate further comprises a gate
wiring of the oxide TFT, wherein the gate wiring of the oxide TFT
is electrically connected to the gate of the oxide TFT through a
via.
[0020] In an example, the array substrate further comprises a first
protection layer, a first planarization layer, a common electrode
of the oxide TFT, a second protection layer, and a pixel electrode
of the oxide TFT in the display area formed above the source and
the drain of the oxide TFT in this order, wherein the pixel
electrode is electrically connected to the drain of the oxide
TFT.
[0021] In an example, the array substrate further comprises a touch
wiring of the oxide TFT in the display area, wherein the touch
wiring of the oxide TFT is electrically connected to the common
electrode of the oxide TFT.
[0022] In an example, the array substrate further comprises a first
protection layer, a first planarization layer, a third protection
layer, a touch wiring of the oxide TFT, a second planarization, a
common electrode of the oxide TFT, a second protection layer, and a
pixel electrode of the oxide TFT in the display area formed above
the source and the drain of the oxide TFT in this order, wherein
the common electrode of the oxide TFT is electrically connected to
the touch wiring of the oxide TFT, and wherein the pixel electrode
is electrically connected to the drain of the oxide TFT.
[0023] In an example, the active layer of the low temperature
polysilicon TFT comprises a polysilicon, and wherein the active
layer of the oxide TFT comprises a metal oxide or a metal
oxynitride.
[0024] According to yet another aspect of the present disclosure,
there is provided a display apparatus comprising the array
substrate as stated above.
[0025] In an example, the active layer of the low temperature
polysilicon TFT comprises a polysilicon, and wherein the active
layer of the oxide TFT comprises a metal oxide or a metal
oxynitride.
BRIEF DESCRIPTION OF THE DRAWINGS
[0026] FIG. 1 is a schematic flowchart of a method for fabricating
an array substrate provided by the embodiments of this
disclosure;
[0027] FIGS. 2a to 2e are structural schematic diagrams after
performing each step of the method for fabricating an array
substrate provided by the embodiments of this disclosure,
respectively;
[0028] FIG. 3 is a structural schematic diagram of the array
substrate of FIG. 2e;
[0029] FIGS. 4a to 4f are structural schematic diagrams after
performing each step of the method for fabricating an array
substrate provided by the embodiments of this disclosure,
respectively; and
[0030] FIG. 5 is a structural schematic diagram of the array
substrate of FIG. 4f.
DETAILED DESCRIPTION
[0031] Specific implementations of a method for fabricating a thin
film transistor, the thin film transistor, an array substrate, and
a display apparatus provided by embodiments of this disclosure will
be illustrated in detail below in connection with the drawings.
[0032] The thickness and the shape of each film layer in the
drawings do not reflect the true scale of the array substrate,
which is only intended to schematically illustrate the content of
this disclosure.
[0033] In the field of thin film transistor liquid crystal
displays, achieving a LTPS (low temperature polysilicon) display
technology with lower energy consumption is becoming more and more
popular. Compared to a polysilicon display technology, LTPS has
larger electron mobility. However, it has a problem of large
leakage current. Therefore, an oxide thin film transistor (TFT)
which replaces the polysilicon with an oxide as an active layer is
widely used in liquid crystal displays due to its large on-state
current, high mobility, good uniformity, high transparency, and
simple fabrication process.
[0034] Although the leakage current in the oxide thin film
transistor is normally small, which enables reduced pixel refresh
rate and thereby lower power consumption, source and drain metal
layers are mainly fabricated by dry etching in the LTPS process,
which will damage the active layer of the oxide TFT during
fabricating, thereby leading to oxide TFTs with poor
performance.
[0035] Therefore, how to reduce the damage to the active layer of
the oxide TFT is a technical problem to be solved for those skilled
in the art.
[0036] Referring to FIG. 1, FIGS. 2a to 2e, and FIGS. 4a to 4f, an
embodiment of this disclosure provides a method for fabricating an
array substrate, wherein the array substrate comprises a display
area and a peripheral area around the display area. The method for
fabricating the array substrate comprises, for example, the
following steps.
[0037] At step S101, as shown by FIG. 2a and FIG. 4a, an active
layer 3 of a low temperature polysilicon TFT is formed in a
peripheral area of the array substrate, a gate 5 of the low
temperature polysilicon TFT is formed above the active layer 3 of
the low temperature polysilicon TFT, and a source and a drain of
the low temperature polysilicon TFT electrically connected to the
active layer 3 of the low temperature polysilicon TFT are
formed.
[0038] At step S102, as shown by FIGS. 2b to 2c and FIGS. 4b to 4c,
while forming the source and the drain of the low temperature
polysilicon TFT electrically connected to the active layer of the
low temperature polysilicon TFT, a gate 20 of an oxide TFT disposed
in the same layer as the source and the drain of the low
temperature polysilicon TFT is formed in a display area of the
array substrate, and an active layer 11 of the oxide TFT
electrically insulated from the gate 20 of the oxide TFT is formed
above the gate 20 of the oxide TFT.
[0039] At step S103, as shown by FIG. 2d and FIG. 4d, a source 9 of
the oxide TFT and a drain 10 of the oxide TFT is formed on the
active layer 11 of the oxide TFT by using wet etching.
[0040] In the above-described method for fabricating the array
substrate, the erosion of the active layer 11 of the oxide TFT
caused while forming the source 9 of the oxide TFT and the drain 10
of the oxide TFT is avoided by separating source and drain metal
layers into the source and the drain of the low temperature
polysilicon TFT, and the source 9 of the oxide TFT and the drain 10
of the oxide TFT disposed in the same layer as the active layer 11
of the oxide TFT, and forming the source 9 of the oxide TFT and the
drain 10 of the oxide TFT by using wet etching, thus increasing a
product yield of the array substrate.
[0041] In an example, according to the step S101, the active layer
3 of the low temperature polysilicon TFT is formed in the
peripheral area, the gate 5 of the low temperature polysilicon TFT
is formed above the active layer 3 of the low temperature
polysilicon TFT, and the source and the drain of the low
temperature polysilicon TFT electrically connected to the active
layer 3 of the low temperature polysilicon TFT are formed by using
dry etching, wherein a data wiring for the gate 5 of the low
temperature polysilicon TFT has an accurate width.
[0042] In an example, according to the step S102, while forming the
source and the drain of the low temperature polysilicon TFT
electrically connected to the active layer of the low temperature
polysilicon TFT, the gate 20 of the oxide TFT disposed in the same
layer as the source and the drain of the low temperature
polysilicon TFT is formed in the display area, and the active layer
11 of the oxide TFT electrically insulated from the gate 20 of the
oxide TFT is formed above the gate 20 of the oxide TFT.
[0043] According to the step S103, the source 9 of the oxide TFT
and the drain 10 of the oxide TFT are formed on the active layer 11
of the oxide TFT by using wet etching. The source and the drain of
the low temperature polysilicon TFT, and the source 9 of the oxide
TFT and the drain 10 of the oxide TFT, are fabricated through
different steps. That is, the source and drain metal layers are
separated by using different fabrication methods, meanwhile the
source 9 of the oxide TFT and the drain 10 of the oxide TFT
disposed in the same layer as the active layer 11 of the oxide TFT
are fabricated by using wet etching, thereby preventing the active
layer 11 of the oxide TFT from being eroded when etching the source
and drain of the lower temperature polysilicon TFT.
[0044] In an example, the method for fabricating the array
substrate further comprises: forming a source wiring 7 of the oxide
TFT disposed in the same layer as the source and the drain of the
low temperature polysilicon TFT in the display area, wherein the
source wiring 7 of the oxide TFT is electrically connected to the
source 9 of the oxide TFT through a via.
[0045] Disposing the source 9 of the oxide TFT and the drain 10 of
the oxide TFT and the active layer 11 of the oxide TFT in a same
layer and only in the display area, and electrically connecting the
source 9 of the oxide TFT with the source wiring 7 of the oxide TFT
positioned therebelow, can accurately control pixel openings of the
array substrate and increase an etching uniformity and an etching
accuracy for fabricating with wet etching.
[0046] Therefore, the above-described method for fabricating the
array substrate can reduce the damage to the active layer 11 of the
oxide TFT and increase the product yield.
[0047] In an example, the method for fabricating the array
substrate further comprises: while forming the gate 5 of the low
temperature polysilicon TFT above the active layer 3 of the low
temperature polysilicon TFT, forming a gate wiring 21 of the oxide
TFT disposed in the same layer as the gate 5 of the low temperature
polysilicon TFT in the display area, wherein the gate wiring 21 of
the oxide TFT is connected to the gate 20 of the oxide TFT through
a via in an interlayer dielectric layer 6.
[0048] In an example, as shown by FIG. 2a and FIG. 4a, forming the
gate 5 of the low temperature polysilicon TFT above the active
layer 3 of the low temperature polysilicon TFT and forming the
source and the drain of the low temperature polysilicon TFT
electrically connected to the active layer 3 of the low temperature
polysilicon TFT comprises: forming a first insulation layer 4 on
the active layer 3 of the low temperature polysilicon TFT, forming
a gate metal layer on the first insulation layer 4, and patterning
the gate metal layer in the peripheral area to form the gate 5 of
the low temperature polysilicon TFT; forming an interlayer
dielectric layer 6 on the gate metal layer, forming a first metal
layer on the interlayer dielectric layer 6, and patterning the
first metal layer in the peripheral area to form the source and the
drain of the low temperature polysilicon TFT; wherein the source
and the drain of the low temperature polysilicon TFT are connected
to the active layer 3 of the low temperature polysilicon TFT
through vias.
[0049] In the above-described method for fabricating the array
substrate, dry etching is used to fabricate the source and the
drain of the low temperature polysilicon TFT. First, a buffer layer
2 is formed on the entire area of a base substrate 1; next, the
active layer 3 of the low temperature polysilicon TFT is formed in
the peripheral area, wherein the active layer 3 of the low
temperature polysilicon TFT comprises a polysilicon material;
subsequently, the first insulation layer 4 and the gate metal layer
are fabricated on the entire area in this order and the gate metal
layer is patterned, the patterned gate metal layer in the
peripheral area forms the gate 5 of the low temperature polysilicon
TFT; then, the interlayer dielectric layer 6 and the first metal
layer are fabricated on the entire area in this order and the first
metal layer is patterned, the patterned first metal layer in the
peripheral area forming the source and the drain of the low
temperature polysilicon TFT, wherein the source and the drain of
the low temperature polysilicon TFT are connected to the active
layer 3 of the low temperature polysilicon TFT through vias. The
source and the drain of the low temperature polysilicon TFT can be
conveniently and quickly fabricated through the above-described
method.
[0050] In an example, as shown by FIG. 2b and FIG. 4b, forming the
gate wiring 21 of the oxide TFT disposed in the same layer as the
gate of the low temperature polysilicon TFT in the display area
comprises: while forming the gate 5 of the low temperature
polysilicon TFT above the active layer 3 of the low temperature
polysilicon TFT, patterning the gate metal layer in the display
area to form the gate wiring 21 of the oxide TFT.
[0051] In an example, as shown by FIG. 2b and FIG. 4b, forming the
source wiring 7 disposed in the same layer as the source and the
drain of the low temperature polysilicon TFT in the display area
comprises: patterning the first metal layer in the display area to
form the source wiring 7 of the oxide TFT; and while patterning the
first metal layer, forming the source wiring 7 of the oxide TFT and
the source and the drain of the low temperature polysilicon TFT
using a same patterning process.
[0052] In an example, as shown by FIG. 2b and FIG. 4b, forming the
gate 20 of the oxide TFT disposed in the same layer as the source
and the drain of the low temperature polysilicon TFT in the display
area comprises: while patterning the first metal layer, forming the
source wiring 7 of the oxide TFT, the source and the drain of the
low temperature polysilicon TFT, and the gate 20 of the oxide TFT
using a same patterning process.
[0053] In the above-described method for fabricating the array
substrate, the patterned first metal layer in the display area
forms the source wiring 7 of the oxide TFT and the gate 20 of the
oxide TFT, wherein the source wiring 7 of the oxide TFT and the
gate 20 of the oxide TFT comprise a metal material. The patterned
gate metal layer in the display area forms the gate wiring 21 of
the oxide TFT below the gate 20 of the oxide TFT, and the gate
wiring 21 of the oxide TFT and the gate 20 of the oxide TFT are
connected through the via in the interlayer dielectric layer 6. The
gate 20 of the oxide TFT can be conveniently and quickly fabricated
through the above-described method.
[0054] In an example, forming the active layer 11 of the oxide TFT
electrically insulated from the gate of the oxide TFT comprises: as
shown by FIG. 2c and FIG. 4c, forming a second insulation layer 8
on the gate 20 of the oxide TFT, and depositing the active layer 11
of the oxide TFT on the second insulation layer 8 in the display
area, wherein the material for the active layer 11 of the oxide TFT
may be a metal oxide or a metal oxynitride. In an example, the
active layer 11 of the oxide TFT may be deposited, for example, by
using plasma enhanced chemical vapor. However, those skilled in the
art may use other methods to deposit the active layer 11 of the
oxide TFT, which is not limited in the present disclosure.
[0055] In an example, forming the source 9 of the oxide TFT and the
drain 10 of the oxide TFT on the active layer 11 of the oxide TFT
by using wet etching comprises: as shown by FIG. 2D and FIG. 4d,
forming a second metal layer on the second insulation layer 8 in
the display area, patterning the second metal layer by using wet
etching to form the source 9 of the oxide TFT and the drain 10 of
the oxide TFT, wherein the source 9 of the oxide TFT and the drain
10 of the oxide TFT cover the ends of the active layer 11 of the
oxide TFT, and wherein the source 9 of the oxide TFT is connected
to the source wiring 7 of the oxide TFT through a via.
[0056] In the above-described method for fabricating the array
substrate, in order to form the source 9 of the oxide TFT, the
drain 10 of the oxide TFT, and the active layer 11 of the oxide TFT
disposed in the same layer, the following steps are adopted. First,
the active layer 11 of the oxide TFT is deposited on the second
insulation layer 8 in the display area by using plasma enhanced
chemical vapor deposition or other methods that can fulfill the
function, wherein the material for the active layer 11 of the oxide
TFT may be a metal oxide or a metal oxynitride, or may be a
composite of metal oxides and metal oxynitrides, or may also be
other material that can fulfill the function. Next, the source 9 of
the oxide TFT and the drain 10 of the oxide TFT are fabricated on
the second insulation layer 8 in the display area by using wet
etching, wherein the source 9 of the oxide TFT and the drain 10 of
the oxide TFT cover the ends of the active layer 11 of the oxide
TFT. As the source 9 of the oxide TFT and the drain 10 of the oxide
TFT are fabricated by using wet etching, the erosion of the active
layer 11 of the oxide TFT can be avoided. Moreover, as the source 9
of the oxide TFT is connected to the source wiring 7 of the oxide
TFT through a via in the second insulation layer 8 positioned
therebelow, the pixel openings of the array substrate can be
accurately controlled, the etching uniformity and the etching
accuracy can be increased, and the product yield can be
increased.
[0057] In an example, the method for fabricating the array
substrate further comprises forming a first protection layer 12, a
first planarization layer 13, a common electrode 18 of the oxide
TFT, a second protection layer 16, and a pixel electrode 19 of the
oxide TFT on the source 9 of the oxide TFT and the drain 10 of the
oxide TFT in this order, wherein the pixel electrode 19 of the
oxide TFT is electrically connected to the drain 10.
[0058] In the above-described method for fabricating the array
substrate, compared to the conventional 9-mask fabrication process,
masks required for forming light shielding layers are reduced,
masks required for forming the second insulation layer 8, the
active layer 11 of the oxide TFT, the source 9 of the oxide TFT,
the drain 10 of the oxide TFT, and the second protection layer 16
are added, which can simply and quickly fabricate the array
substrate.
[0059] On the basis of the above-described method for fabricating
the array substrate, a touch wiring 17 of the oxide TFT is required
to be added in the array substrate in order to achieve the touch
function.
[0060] In an example, as shown by FIG. 2a and FIG. 3, after forming
the first metal layer and before forming the second insulation
layer 8, a touch wiring 17 of the oxide TFT is formed on the
interlayer dielectric layer 6 in the display area.
[0061] In the above-described method for fabricating the array
substrate, the touch wiring 17 of the oxide TFT is disposed on the
interlayer dielectric layer 6, a same mask may be used to form the
source wiring 7 of the oxide TFT on the interlayer dielectric layer
6 and to form the touch wiring 17 of the oxide TFT in the display
area during fabricating.
[0062] In an example, as shown by FIG. 2e, after forming the first
planarization layer 13 and before forming the second protection
layer 16, a common electrode 18 of the oxide TFT is formed on the
interlayer dielectric layer 6 in the display area, wherein the
common electrode 18 of the oxide TFT is electrically connected to a
touch wiring 17 of the oxide TFT.
[0063] In an example, as shown by FIG. 4c, FIG. 4d, FIG. 4e, FIG.
4f, and FIG. 5, after forming the first planarization layer 13 and
before forming the second protection layer 16, a third protection
layer 14, the touch wiring 17 of the oxide TFT, a second
planarization layer 15, and a common electrode 18 of the oxide TFT
on the first planarization layer 13 are formed in the peripheral
area in this order, wherein the common electrode 18 of the oxide
TFT is electrically connected to the touch wiring 17 of the oxide
TFT.
[0064] In the above-described method for fabricating the array
substrate, the touch wiring 17 of the oxide TFT is disposed between
the third protection layer 14 and the second planarization layer
15. During fabricating, the first metal layer and the touch wiring
17 of the oxide TFT using two masks, thus it is not need to
consider the process limit of same layer metal etching condition,
the case in which the process cannot work well due to very small
interval will not be present. Meanwhile, making the touch wiring 17
of the oxide TFT be in a region of the source 9 of the oxide TFT
shielded by a black matrix as much as possible, the opening area
occupied by the touch wiring 17 of the oxide TFT being relatively
small, can largely increase the product's aperture ratio.
[0065] Furthermore, this disclosure further provides an array
substrate comprising at least one low temperature polysilicon TFT
in a peripheral area and at least one oxide TFT in a display
area.
[0066] The low temperature polysilicon TFT comprises an active
layer 3 of the low temperature polysilicon TFT, a gate 5 of the low
temperature polysilicon TFT formed above the active layer 3 of the
low temperature polysilicon TFT, and a source and a drain of the
low temperature polysilicon TFT electrically connected to the
active layer 3 of the low temperature polysilicon TFT.
[0067] The oxide TFT comprises a gate 20 of the oxide TFT disposed
in the same layer as the source and the drain of the low
temperature polysilicon TFT, and an active layer 11 of the oxide
TFT located on the gate 20 of the oxide TFT and electrically
insulated from the gate 20 of the oxide TFT, and a source 9 of the
oxide TFT and a drain 10 of the oxide TFT formed on the active
layer 11 of the oxide TFT by using wet etching.
[0068] In the above-described array substrate, as the source 9 of
the oxide TFT and the drain 10 of the oxide TFT are fabricated by
using wet etching, the erosion of the active layer 11 of the oxide
TFT when forming the source 9 of the oxide TFT and the drain 10 of
the oxide TFT is avoided, such that the product yield of the active
layer 11 of the oxide TFT is relatively high.
[0069] In an example, the array substrate further comprises a
source wiring 7 of the oxide TFT, wherein the source wiring 7 of
the oxide TFT is electrically connected to the source 9 of the
oxide TFT through a via.
[0070] Disposing the source 9 of the oxide TFT and the drain 10 of
the oxide TFT and the active layer 11 of the oxide TFT in a same
layer and only in the display area, and electrically connecting the
source 9 of the oxide TFT with the source wiring 7 of the oxide TFT
positioned therebelow, can accurately control pixel openings of the
array substrate and increase an etching uniformity and an etching
accuracy for fabricating with wet etching, such that the array
substrate has relatively accurate pixel openings, better accuracy,
and higher product yield.
[0071] In an example, the array substrate further comprises a gate
wiring 21 of the oxide TFT, the gate wiring 21 of the oxide TFT
being electrically connected to the gate 20 of the oxide TFT
through a via.
[0072] As shown by FIG. 2e and FIG. 4f, in an example, the active
layer 3 of the low temperature polysilicon TFT comprises a
polysilicon, the active layer 11 of the oxide TFT comprises a metal
oxide or a metal oxynitride.
[0073] In the above-described array substrate, the active layer 11
of the oxide TFT comprising a metal oxide or a metal oxynitride can
generally lead to a relatively small leakage current of the oxide
TFT, which enables a reduced pixel refresh rate and thus a lower
power consumption and an increased product yield.
[0074] In an example, as shown by FIG. 2e, the array substrate
further comprises a first protection layer 12, a first
planarization layer 13, a common electrode 18 of the oxide TFT, a
second protection layer 16, and a pixel electrode 19 of the oxide
TFT in the display area formed above the source 9 and the drain 10
of the oxide TFT in this order, wherein the pixel electrode 19 is
electrically connected to the drain 10 of the oxide TFT.
[0075] In an example, as shown by FIG. 2e, the array substrate
further comprises a touch wiring 17 of the oxide TFT in the display
area, the touch wiring 17 of the oxide TFT being electrically
connected to the common electrode 18 of the oxide TFT.
[0076] In an example, as shown by FIG. 4f, the array substrate
further comprises a first protection layer 12, a first
planarization layer 13, a third protection layer 14, a touch wiring
17 of the oxide TFT, a second planarization layer 15, a common
electrode 18 of the oxide TFT, a second protection layer 16, and a
pixel electrode 19 of the oxide TFT in the display area formed
above the source 9 and the drain 10 of the oxide TFT in this order,
wherein the common electrode 18 of the oxide TFT is electrically
connected to the touch wiring 17 of the oxide TFT, and wherein the
pixel electrode 19 is electrically connected to the drain 10 of the
oxide TFT.
[0077] Furthermore, this disclosure further provides a display
apparatus comprising the array substrate of any of the
above-described technical solutions. As the array substrate has
relatively accurate pixel openings, better accuracy, and higher
product yield, the display apparatus with the array substrate has a
relatively high product yield.
[0078] Those skilled in the art can make various modifications and
variations to this disclosure without departing from the spirit and
the scope of this disclosure. As such, if these modifications and
variations of this disclosure fall into the scope of this
disclosure's claims and its equivalent technologies, this
disclosure is intended to include these modifications and
variations.
* * * * *