U.S. patent application number 16/152142 was filed with the patent office on 2020-04-09 for gate-lifted nmos esd protection device.
This patent application is currently assigned to NXP B.V.. The applicant listed for this patent is NXP B.V.. Invention is credited to Da-Wei LAI, Wilhelmus Cornelis Maria PETERS, Stephen John SQUE.
Application Number | 20200111778 16/152142 |
Document ID | / |
Family ID | 70051403 |
Filed Date | 2020-04-09 |
United States Patent
Application |
20200111778 |
Kind Code |
A1 |
LAI; Da-Wei ; et
al. |
April 9, 2020 |
GATE-LIFTED NMOS ESD PROTECTION DEVICE
Abstract
An ESD protection device including a PNP transistor connected to
an input pad, a diode connected to the PNP transistor and connected
to an output pad, and an NMOS transistor connected to the PNP
transistor and the output pad, wherein the diode, PNP transistor,
and NMOS transistor are configured to route different levels of an
electrostatic discharge (ESD) current pulse from the input pad to
the output pad.
Inventors: |
LAI; Da-Wei; (Nijmegen,
NL) ; SQUE; Stephen John; (Veldhoven, NL) ;
PETERS; Wilhelmus Cornelis Maria; (Groesbeek, NL) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
NXP B.V. |
Eindhoven |
|
NL |
|
|
Assignee: |
NXP B.V.
|
Family ID: |
70051403 |
Appl. No.: |
16/152142 |
Filed: |
October 4, 2018 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/0821 20130101;
H01L 29/87 20130101; H01L 27/0266 20130101; H02H 9/046 20130101;
H01L 29/735 20130101; H01L 29/0847 20130101; H01L 29/1008 20130101;
H01L 29/0808 20130101; H01L 27/0635 20130101; H01L 29/0649
20130101; H01L 29/861 20130101 |
International
Class: |
H01L 27/02 20060101
H01L027/02; H01L 27/06 20060101 H01L027/06; H02H 9/04 20060101
H02H009/04 |
Claims
1. An electrostatic discharge (ESD) protection device, comprising:
a PNP transistor connected to an input pad; a diode connected to
the PNP transistor and connected to an output pad; and an NMOS
transistor connected to the PNP transistor and the output pad,
wherein the diode, PNP transistor, and NMOS transistor are
configured to route different levels of an electrostatic discharge
(ESD) current pulse from the input pad to the output pad.
2. The ESD protection device of claim 1, wherein the ESD protection
device is triggered by the PNP in series with the diode.
3. The ESD protection device of claim 2, wherein a trigger
mechanism of the ESD protection device is a floating base region of
the PNP transistor in series with the diode.
4. The ESD protection device of claim 3, wherein the NMOS
transistor is in an initial off state because of the floating base
region of the PNP transistor.
5. The ESD protection device of claim 1, wherein the diode and the
PNP transistor combine to form a low current path for the ESD
current.
6. The ESD protection device of claim 1, wherein the PNP transistor
and the NMOS transistor combine to form a medium current path for
the ESD current.
7. The ESD protection device of claim 1, wherein the NMOS
transistor and the PNP transistor combine to form an embedded SCR
configured to route a high current path for the ESD current.
8. The ESD protection device of claim 1, wherein the gate of the
NMOS transistor is connected to the collector of the PNP transistor
and to the anode of the diode.
9. The ESD protection device of claim 1, wherein an emitter of the
PNP transistor is connected to the input pad.
10. The ESD protection device of claim 1, wherein ESD current is
conducted via a channel of the NMOS transistor and a parasitic
parallel NPN transistor of the gate-lifted NMOS and boosted at
higher current levels via embedded SCR action.
11. The ESD protection device of claim 1, comprising a first
isolation region disposed between the diode and the PNP transistor
and a second isolation region disposed between the PNP transistor
and the NMOS transistor.
12. The ESD protection device of claim 11, wherein the first highly
doped isolation region is wider than the second highly doped
isolation region.
13. The ESD protection device of claim 11, wherein the PNP
transistor has emitter and collector contact regions having a same
conductivity type as the first isolation region and the second
isolation region.
14. A method of operating an electrostatic discharge (ESD)
protection device, comprising: receiving a low energy current
portion of an ESD pulse at an PNP transistor; conducting the low
energy current portion of the ESD pulse to an output pad through a
diode; receiving a medium energy current portion of the ESD pulse
at the PNP transistor; conducting the medium energy current portion
of the ESD pulse to the output pad through an NMOS transistor;
receiving a high energy current portion of an ESD pulse at the PNP
transistor and conducting the high energy current portion of the
ESD pulse to the output pad through a silicon controlled rectifier
(SCR) formed from the PNP transistor and the NMOS transistor.
15. The method of claim 14, comprising triggering the ESD
protection device using the PNP transistor in series with the
diode.
16. The ESD protection device of claim 15, wherein a trigger
mechanism of the ESD protection device is a floating base region of
the PNP transistor in series with the diode.
17. The ESD protection device of claim 16, wherein the NMOS
transistor is in an initial off state because of the floating base
region of the PNP transistor.
18. The ESD protection device of claim 14, wherein the gate of the
NMOS transistor is connected to the collector of the PNP transistor
and to the anode of the diode.
19. The ESD protection device of claim 14, wherein an emitter of
the PNP transistor is connected to the input pad.
20. The ESD protection device of claim 14, wherein ESD current is
conducted via a channel of the NMOS transistor and a parasitic
parallel NPN transistor of the gate-lifted NMOS and boosted at
higher current levels via embedded SCR action.
Description
TECHNICAL FIELD
[0001] Various exemplary embodiments disclosed herein relate to
electrostatic discharge (ESD) protection, and more particularly to
a gate-lifted NMOS ESD protection device triggered by a PNP in
series with a diode.
BACKGROUND
[0002] Traditionally, grounded-gate NMOS (GGNMOS) devices are used
as local protection for fail-safe and open-drain applications.
However, a trigger voltage (VT1) of both the GGNMOS and a device to
be protected (victim) are often near identical. In practice, a gate
of the victim is floating during ESD stress, and the fail voltage
of the victim is lower when the gate node is lifted with respect to
the grounded-gate condition. Therefore, the GGNMOS is incapable of
protecting the victim. Drain-engineered (with heavily P-doped or
ESD-implant layers) and Zener-diode-triggered devices have been
demonstrated, using additional process options. Gate-coupled,
gate-driven, or PNP-triggered solutions have been demonstrated for
VT1 reduction, with additional circuitry. In practice, these
approaches are only useful for supply protection, because fast
signals may cause false triggering.
SUMMARY
[0003] A brief summary of various embodiments is presented below.
Some simplifications and omissions may be made in the following
summary, which is intended to highlight and introduce some aspects
of the various embodiments, but not to limit the scope of the
invention. Detailed descriptions of embodiments adequate to allow
those of ordinary skill in the art to make and use the inventive
concepts will follow in later sections.
[0004] Embodiments include an electrostatic discharge (ESD)
protection device including a PNP transistor connected to an input
pad, a diode connected to the PNP transistor and connected to an
output pad, and an NMOS transistor connected to the PNP transistor
and the output pad, wherein the diode, PNP transistor, and NMOS
transistor are configured to route different levels of an
electrostatic discharge (ESD) current pulse from the input pad to
the output pad.
[0005] The ESD protection device may be triggered by the PNP in
series with the diode. A trigger mechanism of the ESD protection
device may be a floating base region of the PNP transistor in
series with the diode. The NMOS transistor may be in an initial off
state because of the floating base region of the PNP
transistor.
[0006] The diode and the PNP transistor may combine to form a low
current path for the ESD current.
[0007] The PNP transistor and the NMOS transistor may combine to
form a medium current path for the ESD current.
[0008] The NMOS transistor and the PNP transistor may combine to
form an embedded SCR configured to route a high current path for
the ESD current.
[0009] The gate of the NMOS transistor may be connected to the
collector of the PNP transistor and to the anode of the diode.
[0010] An emitter of the PNP transistor may be connected to the
input pad.
[0011] ESD current may be conducted via a channel of the NMOS
transistor and a parasitic parallel NPN transistor of the
gate-lifted NMOS and boosted at higher current levels via embedded
SCR action.
[0012] The ESD protection device may include a first isolation
region disposed between the diode and the PNP transistor and a
second isolation region disposed between the PNP transistor and the
NMOS transistor.
[0013] The first highly doped isolation region may be wider than
the second highly doped isolation region.
[0014] The PNP transistor may have emitter and collector contact
regions having a same conductivity type as the first isolation
region and the second isolation region.
[0015] Embodiments may also include a method of operating an
electrostatic discharge (ESD) protection device, including
receiving a low energy current portion of an ESD pulse at an PNP
transistor, conducting the low energy current portion of the ESD
pulse to an output pad through a diode, receiving a medium energy
current portion of the ESD pulse at the PNP transistor, conducting
the medium energy current portion of the ESD pulse to the output
pad through an NMOS transistor, receiving a high energy current
portion of an ESD pulse at the PNP transistor and conducting the
high energy current portion of the ESD pulse to the output pad
through a silicon controlled rectifier (SCR) formed from the PNP
transistor and the NMOS transistor.
[0016] The method may include triggering the ESD protection device
using the PNP transistor in series with the diode.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Additional objects and features of the invention will be
more readily apparent from the following detailed description and
appended claims when taken in conjunction with the drawings.
Although several embodiments are illustrated and described, like
reference numerals identify like parts in each of the figures, in
which:
[0018] FIG. 1 illustrates a circuit diagram of an ESD protection
device in accordance with embodiments described herein;
[0019] FIG. 2 illustrates a layout design of an ESD protection
device in accordance with FIG. 1;
[0020] FIG. 3 illustrates a cross-sectional view along the lines
X-X' of the layout structure of the ESD protection device in
accordance with FIG. 2;
[0021] FIG. 4A illustrates a first operation mechanism for the ESD
protection device during positive ESD stress from the PAD to the
VSS pin in accordance with embodiments described herein;
[0022] FIG. 4B illustrates a second operation mechanism for the ESD
protection device during positive ESD stress from the PAD to the
VSS pin in accordance with embodiments described herein;
[0023] FIG. 4C illustrates a third operation mechanism for the ESD
protection device during positive ESD stress from the PAD to the
VSS pin in accordance with embodiments described herein;
[0024] FIG. 5 illustrates DC current-voltage characteristics over
temperature for the ESD protection device in accordance with
embodiments described herein;
[0025] FIG. 6 illustrates the DC holding voltage (VH) and trigger
voltage (VT1) as a function of temperature for the ESD protection
device in accordance with embodiments described herein;
[0026] FIG. 7 illustrates a test structure for an ESD devices in
parallel with the device to be protected (victim) in accordance
with embodiments described herein;
[0027] FIG. 8 illustrates the VF-TLP characteristics of the ESD
protection device, together with a schematic of a standalone 5-V
gate-monitor test structure in accordance with embodiments
described herein; and
[0028] FIG. 9 illustrates TLP long-pulse characteristics of the
GGNMOS, FBPNP+diode, and ESD protection device.
DETAILED DESCRIPTION
[0029] It should be understood that the figures are merely
schematic and are not drawn to scale. It should also be understood
that the same reference numerals are used throughout the figures to
indicate the same or similar parts.
[0030] The descriptions and drawings illustrate the principles of
various example embodiments. It will thus be appreciated that those
skilled in the art will be able to devise various arrangements
that, although not explicitly described or illustrated herein,
embody the principles of the invention and are included within its
scope. Furthermore, all examples recited herein are principally
intended expressly to be for pedagogical purposes to aid the reader
in understanding the principles of the invention and the concepts
contributed by the inventor(s) to furthering the art and are to be
construed as being without limitation to such specifically recited
examples and conditions. Additionally, the term, "or," as used
herein, refers to a non-exclusive or (i.e., and/or), unless
otherwise indicated (e.g., "or else" or "or in the alternative").
Also, the various embodiments described herein are not necessarily
mutually exclusive, as some embodiments can be combined with one or
more other embodiments to form new embodiments. Descriptors such as
"first," "second," "third," etc., are not meant to limit the order
of elements discussed, are used to distinguish one element from the
next, and are generally interchangeable. Values such as maximum or
minimum may be predetermined and set to different values based on
the application.
[0031] Embodiments described herein include a voltage-triggered ESD
device that is based on PNP, diode, and GGNMOS components. By
connecting a gate of an NMOS to the anode of the diode, a
gate-lifted NMOS is formed and triggered by a floating-base PNP
transistor in series with the diode.
[0032] FIG. 1 illustrates a circuit diagram of an ESD protection
device 100 in accordance with embodiments described herein. FIG. 2
illustrates a layout design of an ESD protection device 100 in
accordance with FIG. 1. FIG. 3 illustrates a cross-sectional view
along the lines X-X' of the layout structure of the ESD protection
device 100 in accordance with FIG. 2
[0033] As illustrated in FIGS. 1-3, the ESD protection device 100
includes a diode 101, a PNP transistor 102, and an NMOS transistor
103. In normal operation, the ESD protection device 100 is in an
off state. The ESD protection device 100 may be configured to
handle ESD pulses that originate from a human body, called human
body model (HBM) or manufacturing discharges known as charged
device model (CDM).
[0034] An ESD current pulse may be received at a pad 105. The ESD
protection device 100 described herein is configured to handle and
channel different current levels of the ESD current pulse. The
diode 101 in combination with the PNP transistor 102 may be
configured to handle a low current path of the ESD current pulse.
The PNP transistor 102 in combination with the diode 101 and NMOS
transistor 103 may be configured to handle a medium current path of
the ESD current pulse. The PNP transistor 102 in combination with
the NMOS transistor 103 may form an embedded silicon controlled
rectifier (SCR) device that is configured to handle a high current
path of the ESD current pulse.
[0035] Regarding the structure of the device, as illustrated in
FIG. 1, the diode 101 has an anode terminal 120 connected to a
collector region 118 of the PNP transistor 102 and a gate of the
NMOS transistor 103. A cathode terminal 130 is connected to a
reference node VSS 107. FIG. 2 illustrates the diode 101 disposed
along one edge of a semiconductor substrate 200. The semiconductor
substrate 200 may be of a first conductivity P type. The diode 101
may be disposed in a first well 310 (illustrated in FIG. 3) of the
second conductivity N type. The diode 101 may include a highly
doped anode terminal 120 of the first conductivity P type and a
highly doped cathode terminal 130 of the second conductivity N
type. The highly doped anode terminal 120 and the highly doped
cathode terminal 130 may be separated by a shallow trench isolation
(STI) region 230. FIG. 3 illustrates the diode 101 disposed along
the one edge of the semiconductor substrate 200. The anode terminal
120 may be connected by a first wire 330 to the collector region
118 of the PNP transistor 102 and to the gate electrode 110 of the
NMOS transistor 103.
[0036] During an ESD event, a low current component of an ESD pulse
may enter through the pad 105 to a highly doped emitter region 122
of the first conductivity type, through a second well 320 of a
second conductivity type acting as a base, to the collector region
118 that is also highly doped of a first conductivity type. The
collector region 118 sends the low current component through the
first wire 330 to the anode terminal 120 of the diode 101, and the
low current is routed to the reference node VSS 107 through the
cathode terminal 130 to complete the low current path.
[0037] FIG. 4A illustrates a first operation mechanism for the ESD
protection device 100 during positive ESD stress from the PAD 105
to the VSS pin 107. Before triggering of the PNP transistor 102 in
series with the diode 101, the NMOS transistor 103 may remain in an
off-state and behave like a large resistance. Thus, the base well
320 and the base contact region 116 (illustrated in FIG. 3) of the
PNP transistor 102 may be treated as floating. As a result, for a
low current path a trigger mechanism of the ESD protection device
100 may be determined by a floating-base PNP transistor 102 (FBPNP)
in series with the diode 101, as indicated in FIG. 3 with small
dashes, and in FIG. 4A which illustrates the low current path
311.
[0038] Regarding the PNP transistor 102, referring to FIG. 1, the
emitter region 122 of the PNP transistor 102 is connected to the
pad 105. A base contact region 116 of the PNP transistor 102 is
connected to a drain region 114 of the NMOS transistor 103. The
collector region 118 of the PNP transistor 102 is connected to the
anode terminal 120 of the diode 101 and to the gate electrode 110
of the NMOS transistor 103.
[0039] As illustrated in FIG. 2, the plurality of PNP transistors
202 may be disposed in a middle section of the semiconductor
substrate 200. The plurality of PNP transistors 202 may include a
parallel configuration of emitter regions 122 and collector contact
regions 118 separated by different segments of an N well 220. The
configuration of emitter regions 122 and collector contact regions
118 may be bordered on four sides by an STI region 240. The STI
region 240 may be further bordered by a high dopant concentration
base contact region 116. The configuration of emitter contact
regions 122, collector contact regions 118, and STI 240 regions may
dwell within a base well 320 of the second conductivity N type.
High dopant concentration base contact regions 116 and 124 may be
bordered STI regions 240 and 250.
[0040] As illustrated in FIG. 3, the string of emitter regions 122
and collector regions 118 are disposed within the second well 320
of the second conductivity type, which is disposed atop the
semiconductor substrate 200 of the first conductivity type. The PNP
transistor 102 may be separated from the diode 101 by a first
highly doped isolation region 326 of the first conductivity P type
and a first well 328 of the first conductivity P type. On the other
side, the PNP transistor 102 may be separated from the NMOS
transistor 103 by a second highly doped isolation region 336 of the
first conductivity P type and a second well 338 of the second
conductivity P type. The first highly doped isolation region 326
may have a wider width than the second highly doped isolation
region 336.
[0041] The PNP transistor 102 funnels a medium current of a
received ESD current pulse into a medium current path 322,
illustrated by the medium dotted lines 332 in FIG. 3. In
conjunction with the low current path routed by the diode 101 and
PNP 102, a medium strength energy of the current pulse penetrates
deep into the N well 320 below the STI regions and is attracted to
an adjacent highly doped P base contact region 124. A second wire
340 connects the base contact region 124 and the drain 114 of the
NMOS transistor 103. ESD current in the NMOS transistor 103 flows
from drain 114 to the source 112 and then to the reference node VSS
through a third wire 350. The reference node 107 VSS may provide a
biasing potential for isolation P regions 326/328 and 336/338.
[0042] FIG. 4B illustrates a second operation mechanism for the ESD
protection device 100 during positive ESD stress from the PAD 105
to the VSS pin 107. For the medium current path, after the FBPNP
transistor 102 conducts ESD current, the gate voltage of the NMOS
transistor 103 is higher than VSS 107 by at least the voltage drop
across the diode 101. Therefore, ESD current is conducted by the
channel of the NMOS 103 and a parasitic NPN of the gate-lifted NMOS
103, as indicated in FIG. 3 with medium dashed arrows 322 and in
the "medium current path" 322 part of FIG. 4B. A parasitic NPN
transistor may extend into the P well region 338, from drain 114 to
source 112.
[0043] Regarding the NMOS transistor 103, FIG. 2 illustrates a
plurality of drain-connected NMOS devices 203a on one side of the
PNP transistor region 202 and a second plurality of NMOS devices
203b on a second side of the PNP transistor region 202. The
cross-section along X' of FIG. 2 illustrates a cross section of a
single NMOS transistor 103.
[0044] The NMOS transistors 103 funnel a high current of a received
ESD current pulse into a high current path 333, illustrated by the
long-dotted lines 333 in FIG. 3. Routing of the high current path
333 in the ESD protection device 100 includes the workings of an
embedded PNPN silicon controlled rectifier (SCR) device. A high
energy component of the ESD current pulse enters the P doped
emitter contact region 122 and is driven farther into the N well
320 that the low and medium components. The high energy component
flows to substantially a bottom of the medium doped N well 320. The
high current path 333 flows into a medium doped P well 338, and out
of the highly doped N source region 112. From the source, discharge
current may be routed through the wire 350 to the reference
potential VSS 107.
[0045] FIG. 4C illustrates a third operation mechanism for the ESD
protection device 100 during positive ESD stress from the PAD 105
to the VSS pin 107. For the high current path, once the currents
are high enough to trigger parasitic transistors PNP (regions 122,
320, 338) and NPN (regions 320, 338, 112), the embedded SCR
discussed above comes into action and shunts the rest of the ESD
current, as indicated in FIG. 3 with long dashed arrows 333 and in
the "high current path" 333 part of FIG. 4C.
[0046] Embodiments described above may be used for positive stress
from the PAD 105 to VSS 107. For negative ESD current pulses, a
dedicated external diode 104 may be used to enhance ESD performance
for negative stress from the PAD 105 to the reference node VSS
107.
[0047] The diode 101, lateral PNP transistor 102, and NMOS
transistor 103 may be silicided or unsilicided depending on
conductivity preferences of a designer. Total widths of the PNP
transistor 102, NMOS transistor 103, and diode 101 may be 1000
.mu.m, 200 .mu.m, and 46 .mu.m, respectively. A finger width of
both the PNP transistor 102 and the NMOS transistor 103 may be 50
.mu.m.
[0048] As illustrated in FIG. 3, to avoid SCR action between the
PNP transistor 102 and the diode 101, the wide highly doped P
region 326 may have about a 10-.mu.m length. To boost the high
current path ESD current capability by triggering the embedded SCR
between the PNP transistor 102 and the GGNMOS 103 in the
high-current regime, a distance dl may be about 7.5 .mu.m,
including an intentionally narrow highly doped P region 336.
[0049] An alternative to using the PNP 102 would be to use a PMOS
device. As illustrated in FIG. 3, the highly doped P emitter 122
and collector 118 regions could be used as P doped source and drain
regions. A gate 360 could be used to create a conduction channel.
Instead of the emitter 122 connected to the PAD 105, the gate 360
would be connected to the PAD 105 to receive the ESD pulse.
[0050] FIG. 5 illustrates DC current-voltage characteristics over
temperature for the ESD protection device 100. The breakdown
voltage is higher than 5 V at all temperatures, and the sub-5-V
leakage current is less than 1 .mu.A, which is a typical product
requirement.
[0051] FIG. 6 illustrates the DC holding voltage (VH) and trigger
voltage (VT1) as a function of temperature for the ESD protection
device 100. VH may be captured at a lowest voltage point in a
zoomed-in view, as illustrated in FIG. 5. For good noise or
transient-event immunity, VT1 may be higher than 5 V. The ESD
protection device 100 illustrates a VT1 of 7.2 V at 150.degree. C.,
which represents a 40% margin. A requirement for VH is that it
should be higher than 5 V for decent latch-up immunity after the
device has been triggered. It is thus clear that the ESD protection
device 100 may safely be used for most mobile applications at
85.degree. C.
[0052] FIG. 7 illustrates a test structure 700 for an ESD devices
in parallel with the device to be protected (victim) in accordance
with embodiments described herein. Embodiments discuss transmission
line pulse (TLP) current-voltage characteristics. To estimate ESD
robustness, a safe operating area, and the voltage and current
conditions over which the device can be expected to operate without
self-damage of an NMOS victim transistor may be characterized. To
increase a snapback voltage of the victim by reducing a base
resistance of a parasitic lateral bipolar transistor, an additional
Psub guard ring may be inserted around every two fingers of the
victim. Use of the floating-base PNP 102 may be used to reduce VT1.
The use of the gate-lifted NMOS 103 reduces VT1 and provides
substantially uniform turn-on for multi-finger implementations. In
this technology, the VT1 of the FBPNP 102 plus the diode 101 is
around 7.6 V, much lower than the 9.3 V of a non-floating base PNP
plus a diode. The VT1 of the parasitic NPN bipolar transistor of
the NMOS 103 is around 6.5-7.0 V when the voltage at the gate 110
is 1-2 V.
[0053] FIG. 7 illustrates the TLP characteristics of the ESD
protection device 100, together with those of FBPNP 102 plus diode
101 and a 200-.mu.m-wide unsilicided GGNMOS 103. The total width of
a silicided-NMOS "victim" may be 240 .mu.m. A last point of each
curve is the point just before hard failure. The ESD protection
device illustrates three ESD-current-conduction regimes. In the
low-current regime (up to 0.4 A), the mechanism is determined by
the FBPNP 102 plus diode 101, as suggested in the "low current" TLP
characteristics via their similar slopes. In the medium-current
regime (0.5-1.7 A), ESD current is conducted by the parallel
combination of the gate-lifted NMOS 103. FBPNP 102, and diode 101,
and is greater than that of the single GGNMOS, as indicated in the
"medium current" TLP characteristics. As discussed previously, the
trigger voltage of the GGNMOS can be reduced if the gate node sees
one diode's worth of potential drop (at least), which is consistent
with the VT1 of 8.6 V (FBPNP 102 plus diode 101=.about.9.2 V at 1.1
A, when a diode dope=.about.0.6 V). Furthermore, extrapolation of
the curve from the medium-current regime to 6 V on the voltage axis
may indicate that the mechanism is determined by the gate-lifted
NMOS 103. In the high-current regime (1.8-4.0 A), extra ESD
conduction current can be attributed to embedded SCR action,
because there are no individual ESD components in this scheme that
could sustain such a high current IT2. Additionally, extrapolation
from the high-current regime to 4.5V on the voltage axis suggests
SCR action with a deep snapback voltage.
[0054] Example ESD parameters of the devices described herein are
summarized in TABLE I.
TABLE-US-00001 TABLE I ESD parameters of ESD devices at 25.degree.
C. ESD device I.sub.leak.sup.a (nA) V.sub.T1 (V) V.sub.H (V)
I.sub.T2 (A) ggNMOS.sup.b 0.1 11.5 6.5 1.2 PNP + Dp.sup.c 0.5 9.3
8.6 1.0 FBPNP + Dp.sup.c 0.5 7.6 7.5 1.1 ESD Protection 0.1 7.7 6.7
4.0 device 100.sup.d .sup.aDC I.sub.leak is assessed at V = 5 V.
.sup.bWidth: 240 .mu.m. .sup.cWidths: PNP = 1000 .mu.m, Dp = 23
.mu.m. .sup.dWidths: PNP = 1000 .mu.m, Dp = 46 .mu.m, ggNMOS = 200
.mu.m.
[0055] There is the possibility of damage to the gate oxide from
ESD events with very short rise times if the ESD device cannot turn
on in time. FIG. 8 illustrates the VF-TLP characteristics of the
ESD protection device 100, together with a schematic of a
standalone 5-V gate-monitor test structure. The last point of the
curve is a point just before hard failure. It can be seen that the
ESD protection device 100 can trigger early enough to protect the
gate oxide.
[0056] Because surge-robustness requirements are becoming
increasingly important, it is interesting to examine the ESD
protection device 100 behavior for long pulse widths. FIG. 9
illustrates TLP long-pulse characteristics of the GGNMOS,
FBPNP+diode, and ESD protection device 100. The last point of each
curve is the point just before hard failure. As can be seen, the
ESD protection device 100 demonstrates performance superior to that
of the traditional GGNMOS and FBPNP+DP ESD devices. The SCR action
persists up to at least tpulse=500 ns. TABLE II illustrates the ESD
mechanisms of the ESD protection device 100 with different pulse
widths, under 10-ns rise-time TLP conditions.
TABLE-US-00002 TABLE II ESD Mechanisms and I.sub.T2 of the ESD
protection device 100 with different pulse widths under 10-ns
rise-time TLP conditions at 25.degree. C. ESD current TLP ESD
current-conduction mechanisms capability Pulse width (ns) FBPNP +
D.sub.p GC-NMOS SCR I.sub.T2 (A) 100 X X X 4.0 500 X X X 2.3 1000 X
X -- 1.4 1600 X X -- 1.3
[0057] The DC current-voltage characteristics over temperature for
the ESD protection device 100 after snapback are illustrated in the
insert of FIG. 5. It can be seen that the conduction of ESD current
at 25.degree. C. is dominated by the parasitic NPN transistor.
Therefore, a high VH can be expected, as indicated in FIG. 6, which
is consistent with the snapback voltage at medium current level
seen in FIG. 7 under 25.degree. C. TLP conditions. In addition, SCR
action is absent from TABLE I for pulse widths of 1000 ns and 1600
ns, because the device cannot handle the power levels involved
(I>1 A). The ESD protection device 100 may already be destroyed
before reaching the current levels at which the SCR action would
begin (see also the curves in FIG. 8).
[0058] FIG. 6 summarizes the DC measurements (with maximum currents
of 90 mA). These DC power levels are approximately a factor of 10
lower than the TLP power levels with the longer pulse widths. The
SCR action starts to dominate the ESD conduction at higher
temperatures as the trigger current of the SCR decreases with
increasing temperature, as seen in FIG. 5. As a result, the VH is
much lower at 150.degree. C. than at 25.degree. C. The deeper VH
(3.2 V) at 150.degree. C. in FIG. 6 is consistent with the SCR
conduction mechanism at high current levels (seen in FIG. 7 under
25.degree. C. TLP conditions) when considering self-heating
effects.
[0059] For better latch-up safety, the ESD current can be re-routed
through the gate-coupled NMOS by increasing the base distance (dl)
with a wider Psub tap. In addition, a higher VH could be expected
by simply increasing the channel length of the NMOS transistor.
Surge-robustness optimization is possible via increasing the size
of the NMOS transistor, according to FIG. 6.
[0060] This combination of devices may be used to form an ESD
device for specific applications such as open-drain, fail-safe,
supply, and surge protections. This well-established approach can
save silicon area, reduce time-to-market, and can easily be ported
to different technologies.
[0061] Embodiments described herein include a gate-lifted NMOS ESD
protection device triggered by a PNP in series with a diode is
demonstrated for 5-V mobile applications up to 85.degree. C. in a
0.18-.mu.m CMOS process. The trigger mechanism may be determined by
a floating-base PNP in series with a diode, while the ESD current
is conducted via the channel and the parasitic parallel NPN
transistor of the gate-lifted NMOS and boosted at higher current
levels via embedded SCR action. This voltage-triggered technique
may protect signal pins due to false-triggering issues with
capacitive-triggered solutions. Furthermore, the ESD protection
device 100 demonstrates long-pulse TLP characteristics superior to
those of traditional GGNMOS and FBPNP+DP ESD devices, hence robust
surge performance can be expected.
[0062] The gate-lifted NMOS ESD protection device triggered by a
PNP in series with a diode in a 0.18-.mu.m bulk CMOS technology for
5-V mobile applications up to 85.degree. C. This voltage-triggering
scheme is suitable for fail-safe, open-drain, supply, and surge
protections. In addition, the robust ESD performance is boosted by
embedded-SCR action in the high-current regime. No extra masks nor
additional RC control circuitry are required for this
implementation.
[0063] Although the various exemplary embodiments have been
described in detail with particular reference to certain exemplary
aspects thereof, it should be understood that the invention is
capable of other embodiments and its details are capable of
modifications in various obvious respects. As is readily apparent
to those skilled in the art, variations and modifications can be
affected while remaining within the spirit and scope of the
invention. Accordingly, the foregoing disclosure, description, and
figures are for illustrative purposes only and do not in any way
limit the invention, which is defined only by the claims.
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